Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 30 | #include <linux/export.h> |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 31 | #include <linux/notifier.h> |
| 32 | #include <linux/reboot.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 34 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drm_crtc.h> |
| 36 | #include <drm/drm_crtc_helper.h> |
| 37 | #include <drm/drm_edid.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 39 | #include <drm/i915_drm.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 40 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 41 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 43 | |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 44 | /* Compliance test status bits */ |
| 45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
| 46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 49 | |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 50 | struct dp_link_dpll { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 51 | int clock; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 52 | struct dpll dpll; |
| 53 | }; |
| 54 | |
| 55 | static const struct dp_link_dpll gen4_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 56 | { 162000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 58 | { 270000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 60 | }; |
| 61 | |
| 62 | static const struct dp_link_dpll pch_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 63 | { 162000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 65 | { 270000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 67 | }; |
| 68 | |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 70 | { 162000, |
Chon Ming Lee | 58f6e63 | 2013-09-25 15:47:51 +0800 | [diff] [blame] | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 72 | { 270000, |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 74 | }; |
| 75 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 76 | /* |
| 77 | * CHV supports eDP 1.4 that have more link rates. |
| 78 | * Below only provides the fixed rate but exclude variable rate. |
| 79 | */ |
| 80 | static const struct dp_link_dpll chv_dpll[] = { |
| 81 | /* |
| 82 | * CHV requires to program fractional division for m2. |
| 83 | * m2 is stored in fixed point format using formula below |
| 84 | * (m2_int << 22) | m2_fraction |
| 85 | */ |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
| 92 | }; |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 93 | |
Sonika Jindal | 64987fc | 2015-05-26 17:50:13 +0530 | [diff] [blame] | 94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
| 95 | 324000, 432000, 540000 }; |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
Ville Syrjälä | f4896f1 | 2015-03-12 17:10:27 +0200 | [diff] [blame] | 97 | 324000, 432000, 540000 }; |
| 98 | static const int default_rates[] = { 162000, 270000, 540000 }; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 99 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 100 | /** |
| 101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 102 | * @intel_dp: DP struct |
| 103 | * |
| 104 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 105 | * will return true, and false otherwise. |
| 106 | */ |
| 107 | static bool is_edp(struct intel_dp *intel_dp) |
| 108 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 110 | |
| 111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 112 | } |
| 113 | |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 115 | { |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 117 | |
| 118 | return intel_dig_port->base.base.dev; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 119 | } |
| 120 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 122 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 124 | } |
| 125 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 131 | enum pipe pipe); |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 133 | |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 134 | static int |
| 135 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 136 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 137 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 138 | |
| 139 | switch (max_link_bw) { |
| 140 | case DP_LINK_BW_1_62: |
| 141 | case DP_LINK_BW_2_7: |
Ville Syrjälä | 1db10e2 | 2015-03-12 17:10:32 +0200 | [diff] [blame] | 142 | case DP_LINK_BW_5_4: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 143 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 144 | default: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 145 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
| 146 | max_link_bw); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 147 | max_link_bw = DP_LINK_BW_1_62; |
| 148 | break; |
| 149 | } |
| 150 | return max_link_bw; |
| 151 | } |
| 152 | |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 153 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
| 154 | { |
| 155 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 156 | u8 source_max, sink_max; |
| 157 | |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 158 | source_max = intel_dig_port->max_lanes; |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 159 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
| 160 | |
| 161 | return min(source_max, sink_max); |
| 162 | } |
| 163 | |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 164 | /* |
| 165 | * The units on the numbers in the next two are... bizarre. Examples will |
| 166 | * make it clearer; this one parallels an example in the eDP spec. |
| 167 | * |
| 168 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 169 | * |
| 170 | * 270000 * 1 * 8 / 10 == 216000 |
| 171 | * |
| 172 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 173 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 174 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 175 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 176 | * |
| 177 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 178 | * get the result in decakilobits instead of kilobits. |
| 179 | */ |
| 180 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 181 | static int |
Keith Packard | c898261 | 2012-01-25 08:16:25 -0800 | [diff] [blame] | 182 | intel_dp_link_required(int pixel_clock, int bpp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 183 | { |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 184 | return (pixel_clock * bpp + 9) / 10; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 188 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 189 | { |
| 190 | return (max_link_clock * max_lanes * 8) / 10; |
| 191 | } |
| 192 | |
Mika Kahola | 70ec064 | 2016-09-09 14:10:55 +0300 | [diff] [blame^] | 193 | static int |
| 194 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) |
| 195 | { |
| 196 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 197 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 198 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 199 | int max_dotclk = dev_priv->max_dotclk_freq; |
| 200 | int ds_max_dotclk; |
| 201 | |
| 202 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 203 | |
| 204 | if (type != DP_DS_PORT_TYPE_VGA) |
| 205 | return max_dotclk; |
| 206 | |
| 207 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, |
| 208 | intel_dp->downstream_ports); |
| 209 | |
| 210 | if (ds_max_dotclk != 0) |
| 211 | max_dotclk = min(max_dotclk, ds_max_dotclk); |
| 212 | |
| 213 | return max_dotclk; |
| 214 | } |
| 215 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 216 | static enum drm_mode_status |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 217 | intel_dp_mode_valid(struct drm_connector *connector, |
| 218 | struct drm_display_mode *mode) |
| 219 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 220 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 221 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 222 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 223 | int target_clock = mode->clock; |
| 224 | int max_rate, mode_rate, max_lanes, max_link_clock; |
Mika Kahola | 70ec064 | 2016-09-09 14:10:55 +0300 | [diff] [blame^] | 225 | int max_dotclk; |
| 226 | |
| 227 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 228 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 229 | if (is_edp(intel_dp) && fixed_mode) { |
| 230 | if (mode->hdisplay > fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 231 | return MODE_PANEL; |
| 232 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 233 | if (mode->vdisplay > fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 234 | return MODE_PANEL; |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 235 | |
| 236 | target_clock = fixed_mode->clock; |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 237 | } |
| 238 | |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 239 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 240 | max_lanes = intel_dp_max_lane_count(intel_dp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 241 | |
| 242 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 243 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 244 | |
Mika Kahola | 799487f | 2016-02-02 15:16:38 +0200 | [diff] [blame] | 245 | if (mode_rate > max_rate || target_clock > max_dotclk) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 246 | return MODE_CLOCK_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 247 | |
| 248 | if (mode->clock < 10000) |
| 249 | return MODE_CLOCK_LOW; |
| 250 | |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 251 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 252 | return MODE_H_ILLEGAL; |
| 253 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 254 | return MODE_OK; |
| 255 | } |
| 256 | |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 257 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 258 | { |
| 259 | int i; |
| 260 | uint32_t v = 0; |
| 261 | |
| 262 | if (src_bytes > 4) |
| 263 | src_bytes = 4; |
| 264 | for (i = 0; i < src_bytes; i++) |
| 265 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 266 | return v; |
| 267 | } |
| 268 | |
Damien Lespiau | c2af70e | 2015-02-10 19:32:23 +0000 | [diff] [blame] | 269 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 270 | { |
| 271 | int i; |
| 272 | if (dst_bytes > 4) |
| 273 | dst_bytes = 4; |
| 274 | for (i = 0; i < dst_bytes; i++) |
| 275 | dst[i] = src >> ((3-i) * 8); |
| 276 | } |
| 277 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 278 | static void |
| 279 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 280 | struct intel_dp *intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 281 | static void |
| 282 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 283 | struct intel_dp *intel_dp); |
Imre Deak | 335f752 | 2016-08-10 14:07:32 +0300 | [diff] [blame] | 284 | static void |
| 285 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 286 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 287 | static void pps_lock(struct intel_dp *intel_dp) |
| 288 | { |
| 289 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 290 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 291 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 292 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 293 | enum intel_display_power_domain power_domain; |
| 294 | |
| 295 | /* |
| 296 | * See vlv_power_sequencer_reset() why we need |
| 297 | * a power domain reference here. |
| 298 | */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 299 | power_domain = intel_display_port_aux_power_domain(encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 300 | intel_display_power_get(dev_priv, power_domain); |
| 301 | |
| 302 | mutex_lock(&dev_priv->pps_mutex); |
| 303 | } |
| 304 | |
| 305 | static void pps_unlock(struct intel_dp *intel_dp) |
| 306 | { |
| 307 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 308 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 309 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 310 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 311 | enum intel_display_power_domain power_domain; |
| 312 | |
| 313 | mutex_unlock(&dev_priv->pps_mutex); |
| 314 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 315 | power_domain = intel_display_port_aux_power_domain(encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 316 | intel_display_power_put(dev_priv, power_domain); |
| 317 | } |
| 318 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 319 | static void |
| 320 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
| 321 | { |
| 322 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 323 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 324 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 325 | enum pipe pipe = intel_dp->pps_pipe; |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 326 | bool pll_enabled, release_cl_override = false; |
| 327 | enum dpio_phy phy = DPIO_PHY(pipe); |
| 328 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 329 | uint32_t DP; |
| 330 | |
| 331 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
| 332 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
| 333 | pipe_name(pipe), port_name(intel_dig_port->port))) |
| 334 | return; |
| 335 | |
| 336 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
| 337 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 338 | |
| 339 | /* Preserve the BIOS-computed detected bit. This is |
| 340 | * supposed to be read-only. |
| 341 | */ |
| 342 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| 343 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 344 | DP |= DP_PORT_WIDTH(1); |
| 345 | DP |= DP_LINK_TRAIN_PAT_1; |
| 346 | |
| 347 | if (IS_CHERRYVIEW(dev)) |
| 348 | DP |= DP_PIPE_SELECT_CHV(pipe); |
| 349 | else if (pipe == PIPE_B) |
| 350 | DP |= DP_PIPEB_SELECT; |
| 351 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 352 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
| 353 | |
| 354 | /* |
| 355 | * The DPLL for the pipe must be enabled for this to work. |
| 356 | * So enable temporarily it if it's not already enabled. |
| 357 | */ |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 358 | if (!pll_enabled) { |
| 359 | release_cl_override = IS_CHERRYVIEW(dev) && |
| 360 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
| 361 | |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 362 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
| 363 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
| 364 | DRM_ERROR("Failed to force on pll for pipe %c!\n", |
| 365 | pipe_name(pipe)); |
| 366 | return; |
| 367 | } |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 368 | } |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 369 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 370 | /* |
| 371 | * Similar magic as in intel_dp_enable_port(). |
| 372 | * We _must_ do this port enable + disable trick |
| 373 | * to make this power seqeuencer lock onto the port. |
| 374 | * Otherwise even VDD force bit won't work. |
| 375 | */ |
| 376 | I915_WRITE(intel_dp->output_reg, DP); |
| 377 | POSTING_READ(intel_dp->output_reg); |
| 378 | |
| 379 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
| 380 | POSTING_READ(intel_dp->output_reg); |
| 381 | |
| 382 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 383 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 384 | |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 385 | if (!pll_enabled) { |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 386 | vlv_force_pll_off(dev, pipe); |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 387 | |
| 388 | if (release_cl_override) |
| 389 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
| 390 | } |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 391 | } |
| 392 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 393 | static enum pipe |
| 394 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 395 | { |
| 396 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 397 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 398 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 399 | struct intel_encoder *encoder; |
| 400 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 401 | enum pipe pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 402 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 403 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 404 | |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 405 | /* We should never land here with regular DP ports */ |
| 406 | WARN_ON(!is_edp(intel_dp)); |
| 407 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 408 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 409 | return intel_dp->pps_pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 410 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 411 | /* |
| 412 | * We don't have power sequencer currently. |
| 413 | * Pick one that's not used by other ports. |
| 414 | */ |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 415 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 416 | struct intel_dp *tmp; |
| 417 | |
| 418 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 419 | continue; |
| 420 | |
| 421 | tmp = enc_to_intel_dp(&encoder->base); |
| 422 | |
| 423 | if (tmp->pps_pipe != INVALID_PIPE) |
| 424 | pipes &= ~(1 << tmp->pps_pipe); |
| 425 | } |
| 426 | |
| 427 | /* |
| 428 | * Didn't find one. This should not happen since there |
| 429 | * are two power sequencers and up to two eDP ports. |
| 430 | */ |
| 431 | if (WARN_ON(pipes == 0)) |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 432 | pipe = PIPE_A; |
| 433 | else |
| 434 | pipe = ffs(pipes) - 1; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 435 | |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 436 | vlv_steal_power_sequencer(dev, pipe); |
| 437 | intel_dp->pps_pipe = pipe; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 438 | |
| 439 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
| 440 | pipe_name(intel_dp->pps_pipe), |
| 441 | port_name(intel_dig_port->port)); |
| 442 | |
| 443 | /* init power sequencer on this pipe and port */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 444 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 445 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 446 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 447 | /* |
| 448 | * Even vdd force doesn't work until we've made |
| 449 | * the power sequencer lock in on the port. |
| 450 | */ |
| 451 | vlv_power_sequencer_kick(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 452 | |
| 453 | return intel_dp->pps_pipe; |
| 454 | } |
| 455 | |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 456 | static int |
| 457 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) |
| 458 | { |
| 459 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 460 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 461 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 462 | |
| 463 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 464 | |
| 465 | /* We should never land here with regular DP ports */ |
| 466 | WARN_ON(!is_edp(intel_dp)); |
| 467 | |
| 468 | /* |
| 469 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance |
| 470 | * mapping needs to be retrieved from VBT, for now just hard-code to |
| 471 | * use instance #0 always. |
| 472 | */ |
| 473 | if (!intel_dp->pps_reset) |
| 474 | return 0; |
| 475 | |
| 476 | intel_dp->pps_reset = false; |
| 477 | |
| 478 | /* |
| 479 | * Only the HW needs to be reprogrammed, the SW state is fixed and |
| 480 | * has been setup during connector init. |
| 481 | */ |
| 482 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
| 483 | |
| 484 | return 0; |
| 485 | } |
| 486 | |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 487 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
| 488 | enum pipe pipe); |
| 489 | |
| 490 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
| 491 | enum pipe pipe) |
| 492 | { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 493 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 494 | } |
| 495 | |
| 496 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
| 497 | enum pipe pipe) |
| 498 | { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 499 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 500 | } |
| 501 | |
| 502 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
| 503 | enum pipe pipe) |
| 504 | { |
| 505 | return true; |
| 506 | } |
| 507 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 508 | static enum pipe |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 509 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
| 510 | enum port port, |
| 511 | vlv_pipe_check pipe_check) |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 512 | { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 513 | enum pipe pipe; |
| 514 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 515 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 516 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 517 | PANEL_PORT_SELECT_MASK; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 518 | |
| 519 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
| 520 | continue; |
| 521 | |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 522 | if (!pipe_check(dev_priv, pipe)) |
| 523 | continue; |
| 524 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 525 | return pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 526 | } |
| 527 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 528 | return INVALID_PIPE; |
| 529 | } |
| 530 | |
| 531 | static void |
| 532 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
| 533 | { |
| 534 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 535 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 536 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 537 | enum port port = intel_dig_port->port; |
| 538 | |
| 539 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 540 | |
| 541 | /* try to find a pipe with this port selected */ |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 542 | /* first pick one where the panel is on */ |
| 543 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 544 | vlv_pipe_has_pp_on); |
| 545 | /* didn't find one? pick one where vdd is on */ |
| 546 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 547 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 548 | vlv_pipe_has_vdd_on); |
| 549 | /* didn't find one? pick one with just the correct port */ |
| 550 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 551 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 552 | vlv_pipe_any); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 553 | |
| 554 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
| 555 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
| 556 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
| 557 | port_name(port)); |
| 558 | return; |
| 559 | } |
| 560 | |
| 561 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
| 562 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
| 563 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 564 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 565 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 566 | } |
| 567 | |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 568 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 569 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 570 | struct drm_device *dev = &dev_priv->drm; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 571 | struct intel_encoder *encoder; |
| 572 | |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 573 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
| 574 | !IS_BROXTON(dev))) |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 575 | return; |
| 576 | |
| 577 | /* |
| 578 | * We can't grab pps_mutex here due to deadlock with power_domain |
| 579 | * mutex when power_domain functions are called while holding pps_mutex. |
| 580 | * That also means that in order to use pps_pipe the code needs to |
| 581 | * hold both a power domain reference and pps_mutex, and the power domain |
| 582 | * reference get/put must be done while _not_ holding pps_mutex. |
| 583 | * pps_{lock,unlock}() do these steps in the correct order, so one |
| 584 | * should use them always. |
| 585 | */ |
| 586 | |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 587 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 588 | struct intel_dp *intel_dp; |
| 589 | |
| 590 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 591 | continue; |
| 592 | |
| 593 | intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 594 | if (IS_BROXTON(dev)) |
| 595 | intel_dp->pps_reset = true; |
| 596 | else |
| 597 | intel_dp->pps_pipe = INVALID_PIPE; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 598 | } |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 599 | } |
| 600 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 601 | struct pps_registers { |
| 602 | i915_reg_t pp_ctrl; |
| 603 | i915_reg_t pp_stat; |
| 604 | i915_reg_t pp_on; |
| 605 | i915_reg_t pp_off; |
| 606 | i915_reg_t pp_div; |
| 607 | }; |
| 608 | |
| 609 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, |
| 610 | struct intel_dp *intel_dp, |
| 611 | struct pps_registers *regs) |
| 612 | { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 613 | int pps_idx = 0; |
| 614 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 615 | memset(regs, 0, sizeof(*regs)); |
| 616 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 617 | if (IS_BROXTON(dev_priv)) |
| 618 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
| 619 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 620 | pps_idx = vlv_power_sequencer_pipe(intel_dp); |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 621 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 622 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
| 623 | regs->pp_stat = PP_STATUS(pps_idx); |
| 624 | regs->pp_on = PP_ON_DELAYS(pps_idx); |
| 625 | regs->pp_off = PP_OFF_DELAYS(pps_idx); |
| 626 | if (!IS_BROXTON(dev_priv)) |
| 627 | regs->pp_div = PP_DIVISOR(pps_idx); |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 628 | } |
| 629 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 630 | static i915_reg_t |
| 631 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 632 | { |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 633 | struct pps_registers regs; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 634 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 635 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
| 636 | ®s); |
| 637 | |
| 638 | return regs.pp_ctrl; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 639 | } |
| 640 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 641 | static i915_reg_t |
| 642 | _pp_stat_reg(struct intel_dp *intel_dp) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 643 | { |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 644 | struct pps_registers regs; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 645 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 646 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
| 647 | ®s); |
| 648 | |
| 649 | return regs.pp_stat; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 650 | } |
| 651 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 652 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
| 653 | This function only applicable when panel PM state is not to be tracked */ |
| 654 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
| 655 | void *unused) |
| 656 | { |
| 657 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
| 658 | edp_notifier); |
| 659 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 660 | struct drm_i915_private *dev_priv = to_i915(dev); |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 661 | |
| 662 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
| 663 | return 0; |
| 664 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 665 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 666 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 667 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 668 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 669 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 670 | u32 pp_div; |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 671 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 672 | pp_ctrl_reg = PP_CONTROL(pipe); |
| 673 | pp_div_reg = PP_DIVISOR(pipe); |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 674 | pp_div = I915_READ(pp_div_reg); |
| 675 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
| 676 | |
| 677 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
| 678 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
| 679 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 680 | msleep(intel_dp->panel_power_cycle_delay); |
| 681 | } |
| 682 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 683 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 684 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 685 | return 0; |
| 686 | } |
| 687 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 688 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 689 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 690 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 691 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 692 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 693 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 694 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 695 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Ville Syrjälä | 9a42356 | 2014-10-16 21:29:48 +0300 | [diff] [blame] | 696 | intel_dp->pps_pipe == INVALID_PIPE) |
| 697 | return false; |
| 698 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 699 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 700 | } |
| 701 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 702 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 703 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 704 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 705 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 706 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 707 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 708 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 709 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Ville Syrjälä | 9a42356 | 2014-10-16 21:29:48 +0300 | [diff] [blame] | 710 | intel_dp->pps_pipe == INVALID_PIPE) |
| 711 | return false; |
| 712 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 713 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 714 | } |
| 715 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 716 | static void |
| 717 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 718 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 719 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 720 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 721 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 722 | if (!is_edp(intel_dp)) |
| 723 | return; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 724 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 725 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 726 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 727 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 728 | I915_READ(_pp_stat_reg(intel_dp)), |
| 729 | I915_READ(_pp_ctrl_reg(intel_dp))); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 730 | } |
| 731 | } |
| 732 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 733 | static uint32_t |
| 734 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 735 | { |
| 736 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 737 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 738 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 739 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 740 | uint32_t status; |
| 741 | bool done; |
| 742 | |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 743 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 744 | if (has_aux_irq) |
Paulo Zanoni | b18ac46 | 2013-02-18 19:00:24 -0300 | [diff] [blame] | 745 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
Imre Deak | 3598706 | 2013-05-21 20:03:20 +0300 | [diff] [blame] | 746 | msecs_to_jiffies_timeout(10)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 747 | else |
Imre Deak | 713a6b6 | 2016-06-28 13:37:33 +0300 | [diff] [blame] | 748 | done = wait_for(C, 10) == 0; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 749 | if (!done) |
| 750 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 751 | has_aux_irq); |
| 752 | #undef C |
| 753 | |
| 754 | return status; |
| 755 | } |
| 756 | |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 757 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 758 | { |
| 759 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 760 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 761 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 762 | if (index) |
| 763 | return 0; |
| 764 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 765 | /* |
| 766 | * The clock divider is based off the hrawclk, and would like to run at |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 767 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 768 | */ |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 769 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 770 | } |
| 771 | |
| 772 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 773 | { |
| 774 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 775 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 776 | |
| 777 | if (index) |
| 778 | return 0; |
| 779 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 780 | /* |
| 781 | * The clock divider is based off the cdclk or PCH rawclk, and would |
| 782 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and |
| 783 | * divide by 2000 and use that |
| 784 | */ |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 785 | if (intel_dig_port->port == PORT_A) |
Ville Syrjälä | fce18c4 | 2015-11-30 16:23:46 +0200 | [diff] [blame] | 786 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 787 | else |
| 788 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 789 | } |
| 790 | |
| 791 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 792 | { |
| 793 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 794 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 795 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 796 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 797 | /* Workaround for non-ULT HSW */ |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 798 | switch (index) { |
| 799 | case 0: return 63; |
| 800 | case 1: return 72; |
| 801 | default: return 0; |
| 802 | } |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 803 | } |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 804 | |
| 805 | return ilk_get_aux_clock_divider(intel_dp, index); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 806 | } |
| 807 | |
Damien Lespiau | b6b5e38 | 2014-01-20 16:00:59 +0000 | [diff] [blame] | 808 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 809 | { |
| 810 | /* |
| 811 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
| 812 | * derive the clock from CDCLK automatically). We still implement the |
| 813 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
| 814 | */ |
| 815 | return index ? 0 : 1; |
| 816 | } |
| 817 | |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 818 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 819 | bool has_aux_irq, |
| 820 | int send_bytes, |
| 821 | uint32_t aux_clock_divider) |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 822 | { |
| 823 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 824 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 825 | uint32_t precharge, timeout; |
| 826 | |
| 827 | if (IS_GEN6(dev)) |
| 828 | precharge = 3; |
| 829 | else |
| 830 | precharge = 5; |
| 831 | |
Ville Syrjälä | f3c6a3a | 2015-11-11 20:34:10 +0200 | [diff] [blame] | 832 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 833 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| 834 | else |
| 835 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| 836 | |
| 837 | return DP_AUX_CH_CTL_SEND_BUSY | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 838 | DP_AUX_CH_CTL_DONE | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 839 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 840 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 841 | timeout | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 842 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 843 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 844 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 845 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 846 | } |
| 847 | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 848 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 849 | bool has_aux_irq, |
| 850 | int send_bytes, |
| 851 | uint32_t unused) |
| 852 | { |
| 853 | return DP_AUX_CH_CTL_SEND_BUSY | |
| 854 | DP_AUX_CH_CTL_DONE | |
| 855 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
| 856 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 857 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
| 858 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
| 859 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
Daniel Vetter | d4dcbdc | 2016-05-18 18:47:15 +0200 | [diff] [blame] | 860 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 861 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
| 862 | } |
| 863 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 864 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 865 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Daniel Vetter | bd9f74a | 2014-10-02 09:45:35 +0200 | [diff] [blame] | 866 | const uint8_t *send, int send_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 867 | uint8_t *recv, int recv_size) |
| 868 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 869 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 870 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 871 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 872 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 873 | uint32_t aux_clock_divider; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 874 | int i, ret, recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 875 | uint32_t status; |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 876 | int try, clock = 0; |
Daniel Vetter | 4e6b788 | 2014-02-07 16:33:20 +0100 | [diff] [blame] | 877 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 878 | bool vdd; |
| 879 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 880 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 881 | |
Ville Syrjälä | 72c3500 | 2014-08-18 22:16:00 +0300 | [diff] [blame] | 882 | /* |
| 883 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
| 884 | * In such cases we want to leave VDD enabled and it's up to upper layers |
| 885 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
| 886 | * ourselves. |
| 887 | */ |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 888 | vdd = edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 889 | |
| 890 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 891 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 892 | * deep sleep states. |
| 893 | */ |
| 894 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 895 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 896 | intel_dp_check_edp(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 897 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 898 | /* Try to wait for any previous AUX channel activity */ |
| 899 | for (try = 0; try < 3; try++) { |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 900 | status = I915_READ_NOTRACE(ch_ctl); |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 901 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 902 | break; |
| 903 | msleep(1); |
| 904 | } |
| 905 | |
| 906 | if (try == 3) { |
Mika Kuoppala | 02196c7 | 2015-08-06 16:48:58 +0300 | [diff] [blame] | 907 | static u32 last_status = -1; |
| 908 | const u32 status = I915_READ(ch_ctl); |
| 909 | |
| 910 | if (status != last_status) { |
| 911 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 912 | status); |
| 913 | last_status = status; |
| 914 | } |
| 915 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 916 | ret = -EBUSY; |
| 917 | goto out; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 918 | } |
| 919 | |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 920 | /* Only 5 data registers! */ |
| 921 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| 922 | ret = -E2BIG; |
| 923 | goto out; |
| 924 | } |
| 925 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 926 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 927 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 928 | has_aux_irq, |
| 929 | send_bytes, |
| 930 | aux_clock_divider); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 931 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 932 | /* Must try at least 3 times according to DP spec */ |
| 933 | for (try = 0; try < 5; try++) { |
| 934 | /* Load the send data into the aux channel data registers */ |
| 935 | for (i = 0; i < send_bytes; i += 4) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 936 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 937 | intel_dp_pack_aux(send + i, |
| 938 | send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 939 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 940 | /* Send the command and wait for it to complete */ |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 941 | I915_WRITE(ch_ctl, send_ctl); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 942 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 943 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 944 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 945 | /* Clear done status and any errors */ |
| 946 | I915_WRITE(ch_ctl, |
| 947 | status | |
| 948 | DP_AUX_CH_CTL_DONE | |
| 949 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 950 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Adam Jackson | d7e96fe | 2011-07-26 15:39:46 -0400 | [diff] [blame] | 951 | |
Todd Previte | 74ebf29 | 2015-04-15 08:38:41 -0700 | [diff] [blame] | 952 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 953 | continue; |
Todd Previte | 74ebf29 | 2015-04-15 08:38:41 -0700 | [diff] [blame] | 954 | |
| 955 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
| 956 | * 400us delay required for errors and timeouts |
| 957 | * Timeout errors from the HW already meet this |
| 958 | * requirement so skip to next iteration |
| 959 | */ |
| 960 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| 961 | usleep_range(400, 500); |
| 962 | continue; |
| 963 | } |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 964 | if (status & DP_AUX_CH_CTL_DONE) |
Jim Bride | e058c94 | 2015-05-27 10:21:48 -0700 | [diff] [blame] | 965 | goto done; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 966 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 967 | } |
| 968 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 969 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 970 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 971 | ret = -EBUSY; |
| 972 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 973 | } |
| 974 | |
Jim Bride | e058c94 | 2015-05-27 10:21:48 -0700 | [diff] [blame] | 975 | done: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 976 | /* Check for timeout or receive error. |
| 977 | * Timeouts occur when the sink is not connected |
| 978 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 979 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 980 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 981 | ret = -EIO; |
| 982 | goto out; |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 983 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 984 | |
| 985 | /* Timeouts occur when the device isn't connected, so they're |
| 986 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 987 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 988 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 989 | ret = -ETIMEDOUT; |
| 990 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 991 | } |
| 992 | |
| 993 | /* Unload any bytes sent back from the other side */ |
| 994 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 995 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Rodrigo Vivi | 14e0188 | 2015-12-10 11:12:27 -0800 | [diff] [blame] | 996 | |
| 997 | /* |
| 998 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
| 999 | * We have no idea of what happened so we return -EBUSY so |
| 1000 | * drm layer takes care for the necessary retries. |
| 1001 | */ |
| 1002 | if (recv_bytes == 0 || recv_bytes > 20) { |
| 1003 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
| 1004 | recv_bytes); |
| 1005 | /* |
| 1006 | * FIXME: This patch was created on top of a series that |
| 1007 | * organize the retries at drm level. There EBUSY should |
| 1008 | * also take care for 1ms wait before retrying. |
| 1009 | * That aux retries re-org is still needed and after that is |
| 1010 | * merged we remove this sleep from here. |
| 1011 | */ |
| 1012 | usleep_range(1000, 1500); |
| 1013 | ret = -EBUSY; |
| 1014 | goto out; |
| 1015 | } |
| 1016 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1017 | if (recv_bytes > recv_size) |
| 1018 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1019 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 1020 | for (i = 0; i < recv_bytes; i += 4) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1021 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 1022 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1023 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1024 | ret = recv_bytes; |
| 1025 | out: |
| 1026 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 1027 | |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 1028 | if (vdd) |
| 1029 | edp_panel_vdd_off(intel_dp, false); |
| 1030 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1031 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1032 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1033 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1034 | } |
| 1035 | |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 1036 | #define BARE_ADDRESS_SIZE 3 |
| 1037 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1038 | static ssize_t |
| 1039 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1040 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1041 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
| 1042 | uint8_t txbuf[20], rxbuf[20]; |
| 1043 | size_t txsize, rxsize; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1044 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1045 | |
Ville Syrjälä | d2d9cbb | 2015-03-19 11:44:06 +0200 | [diff] [blame] | 1046 | txbuf[0] = (msg->request << 4) | |
| 1047 | ((msg->address >> 16) & 0xf); |
| 1048 | txbuf[1] = (msg->address >> 8) & 0xff; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1049 | txbuf[2] = msg->address & 0xff; |
| 1050 | txbuf[3] = msg->size - 1; |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 1051 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1052 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
| 1053 | case DP_AUX_NATIVE_WRITE: |
| 1054 | case DP_AUX_I2C_WRITE: |
Ville Syrjälä | c1e74122 | 2015-08-27 17:23:27 +0300 | [diff] [blame] | 1055 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 1056 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
Jani Nikula | a1ddefd | 2015-03-17 17:18:54 +0200 | [diff] [blame] | 1057 | rxsize = 2; /* 0 or 1 data bytes */ |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 1058 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1059 | if (WARN_ON(txsize > 20)) |
| 1060 | return -E2BIG; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1061 | |
Ville Syrjälä | dd788090 | 2016-07-28 17:55:04 +0300 | [diff] [blame] | 1062 | WARN_ON(!msg->buffer != !msg->size); |
| 1063 | |
Imre Deak | d81a67c | 2016-01-29 14:52:26 +0200 | [diff] [blame] | 1064 | if (msg->buffer) |
| 1065 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1066 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1067 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 1068 | if (ret > 0) { |
| 1069 | msg->reply = rxbuf[0] >> 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1070 | |
Jani Nikula | a1ddefd | 2015-03-17 17:18:54 +0200 | [diff] [blame] | 1071 | if (ret > 1) { |
| 1072 | /* Number of bytes written in a short write. */ |
| 1073 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
| 1074 | } else { |
| 1075 | /* Return payload size. */ |
| 1076 | ret = msg->size; |
| 1077 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1078 | } |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1079 | break; |
| 1080 | |
| 1081 | case DP_AUX_NATIVE_READ: |
| 1082 | case DP_AUX_I2C_READ: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 1083 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1084 | rxsize = msg->size + 1; |
| 1085 | |
| 1086 | if (WARN_ON(rxsize > 20)) |
| 1087 | return -E2BIG; |
| 1088 | |
| 1089 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 1090 | if (ret > 0) { |
| 1091 | msg->reply = rxbuf[0] >> 4; |
| 1092 | /* |
| 1093 | * Assume happy day, and copy the data. The caller is |
| 1094 | * expected to check msg->reply before touching it. |
| 1095 | * |
| 1096 | * Return payload size. |
| 1097 | */ |
| 1098 | ret--; |
| 1099 | memcpy(msg->buffer, rxbuf + 1, ret); |
| 1100 | } |
| 1101 | break; |
| 1102 | |
| 1103 | default: |
| 1104 | ret = -EINVAL; |
| 1105 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1106 | } |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 1107 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1108 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1109 | } |
| 1110 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1111 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1112 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1113 | { |
| 1114 | switch (port) { |
| 1115 | case PORT_B: |
| 1116 | case PORT_C: |
| 1117 | case PORT_D: |
| 1118 | return DP_AUX_CH_CTL(port); |
| 1119 | default: |
| 1120 | MISSING_CASE(port); |
| 1121 | return DP_AUX_CH_CTL(PORT_B); |
| 1122 | } |
| 1123 | } |
| 1124 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1125 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1126 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1127 | { |
| 1128 | switch (port) { |
| 1129 | case PORT_B: |
| 1130 | case PORT_C: |
| 1131 | case PORT_D: |
| 1132 | return DP_AUX_CH_DATA(port, index); |
| 1133 | default: |
| 1134 | MISSING_CASE(port); |
| 1135 | return DP_AUX_CH_DATA(PORT_B, index); |
| 1136 | } |
| 1137 | } |
| 1138 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1139 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1140 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1141 | { |
| 1142 | switch (port) { |
| 1143 | case PORT_A: |
| 1144 | return DP_AUX_CH_CTL(port); |
| 1145 | case PORT_B: |
| 1146 | case PORT_C: |
| 1147 | case PORT_D: |
| 1148 | return PCH_DP_AUX_CH_CTL(port); |
| 1149 | default: |
| 1150 | MISSING_CASE(port); |
| 1151 | return DP_AUX_CH_CTL(PORT_A); |
| 1152 | } |
| 1153 | } |
| 1154 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1155 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1156 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1157 | { |
| 1158 | switch (port) { |
| 1159 | case PORT_A: |
| 1160 | return DP_AUX_CH_DATA(port, index); |
| 1161 | case PORT_B: |
| 1162 | case PORT_C: |
| 1163 | case PORT_D: |
| 1164 | return PCH_DP_AUX_CH_DATA(port, index); |
| 1165 | default: |
| 1166 | MISSING_CASE(port); |
| 1167 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1168 | } |
| 1169 | } |
| 1170 | |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1171 | /* |
| 1172 | * On SKL we don't have Aux for port E so we rely |
| 1173 | * on VBT to set a proper alternate aux channel. |
| 1174 | */ |
| 1175 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) |
| 1176 | { |
| 1177 | const struct ddi_vbt_port_info *info = |
| 1178 | &dev_priv->vbt.ddi_port_info[PORT_E]; |
| 1179 | |
| 1180 | switch (info->alternate_aux_channel) { |
| 1181 | case DP_AUX_A: |
| 1182 | return PORT_A; |
| 1183 | case DP_AUX_B: |
| 1184 | return PORT_B; |
| 1185 | case DP_AUX_C: |
| 1186 | return PORT_C; |
| 1187 | case DP_AUX_D: |
| 1188 | return PORT_D; |
| 1189 | default: |
| 1190 | MISSING_CASE(info->alternate_aux_channel); |
| 1191 | return PORT_A; |
| 1192 | } |
| 1193 | } |
| 1194 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1195 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1196 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1197 | { |
| 1198 | if (port == PORT_E) |
| 1199 | port = skl_porte_aux_port(dev_priv); |
| 1200 | |
| 1201 | switch (port) { |
| 1202 | case PORT_A: |
| 1203 | case PORT_B: |
| 1204 | case PORT_C: |
| 1205 | case PORT_D: |
| 1206 | return DP_AUX_CH_CTL(port); |
| 1207 | default: |
| 1208 | MISSING_CASE(port); |
| 1209 | return DP_AUX_CH_CTL(PORT_A); |
| 1210 | } |
| 1211 | } |
| 1212 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1213 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1214 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1215 | { |
| 1216 | if (port == PORT_E) |
| 1217 | port = skl_porte_aux_port(dev_priv); |
| 1218 | |
| 1219 | switch (port) { |
| 1220 | case PORT_A: |
| 1221 | case PORT_B: |
| 1222 | case PORT_C: |
| 1223 | case PORT_D: |
| 1224 | return DP_AUX_CH_DATA(port, index); |
| 1225 | default: |
| 1226 | MISSING_CASE(port); |
| 1227 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1228 | } |
| 1229 | } |
| 1230 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1231 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1232 | enum port port) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1233 | { |
| 1234 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1235 | return skl_aux_ctl_reg(dev_priv, port); |
| 1236 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1237 | return ilk_aux_ctl_reg(dev_priv, port); |
| 1238 | else |
| 1239 | return g4x_aux_ctl_reg(dev_priv, port); |
| 1240 | } |
| 1241 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1242 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1243 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1244 | { |
| 1245 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1246 | return skl_aux_data_reg(dev_priv, port, index); |
| 1247 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1248 | return ilk_aux_data_reg(dev_priv, port, index); |
| 1249 | else |
| 1250 | return g4x_aux_data_reg(dev_priv, port, index); |
| 1251 | } |
| 1252 | |
| 1253 | static void intel_aux_reg_init(struct intel_dp *intel_dp) |
| 1254 | { |
| 1255 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
| 1256 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1257 | int i; |
| 1258 | |
| 1259 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); |
| 1260 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) |
| 1261 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); |
| 1262 | } |
| 1263 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1264 | static void |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1265 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
| 1266 | { |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1267 | kfree(intel_dp->aux.name); |
| 1268 | } |
| 1269 | |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 1270 | static void |
Mika Kahola | b633958 | 2016-09-09 14:10:52 +0300 | [diff] [blame] | 1271 | intel_dp_aux_init(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1272 | { |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 1273 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1274 | enum port port = intel_dig_port->port; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1275 | |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1276 | intel_aux_reg_init(intel_dp); |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 1277 | drm_dp_aux_init(&intel_dp->aux); |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 1278 | |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 1279 | /* Failure to allocate our preferred name is not critical */ |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1280 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1281 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1282 | } |
| 1283 | |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1284 | static int |
Ville Syrjälä | 12f6a2e | 2015-03-12 17:10:30 +0200 | [diff] [blame] | 1285 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1286 | { |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1287 | if (intel_dp->num_sink_rates) { |
| 1288 | *sink_rates = intel_dp->sink_rates; |
| 1289 | return intel_dp->num_sink_rates; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1290 | } |
Ville Syrjälä | 12f6a2e | 2015-03-12 17:10:30 +0200 | [diff] [blame] | 1291 | |
| 1292 | *sink_rates = default_rates; |
| 1293 | |
| 1294 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1295 | } |
| 1296 | |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1297 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1298 | { |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1299 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1300 | struct drm_device *dev = dig_port->base.base.dev; |
| 1301 | |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1302 | /* WaDisableHBR2:skl */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1303 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1304 | return false; |
| 1305 | |
| 1306 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
| 1307 | (INTEL_INFO(dev)->gen >= 9)) |
| 1308 | return true; |
| 1309 | else |
| 1310 | return false; |
| 1311 | } |
| 1312 | |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1313 | static int |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1314 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1315 | { |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1316 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1317 | struct drm_device *dev = dig_port->base.base.dev; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1318 | int size; |
| 1319 | |
Sonika Jindal | 64987fc | 2015-05-26 17:50:13 +0530 | [diff] [blame] | 1320 | if (IS_BROXTON(dev)) { |
| 1321 | *source_rates = bxt_rates; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1322 | size = ARRAY_SIZE(bxt_rates); |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1323 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 1324 | *source_rates = skl_rates; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1325 | size = ARRAY_SIZE(skl_rates); |
| 1326 | } else { |
| 1327 | *source_rates = default_rates; |
| 1328 | size = ARRAY_SIZE(default_rates); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1329 | } |
Ville Syrjälä | 636280b | 2015-03-12 17:10:29 +0200 | [diff] [blame] | 1330 | |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1331 | /* This depends on the fact that 5.4 is last value in the array */ |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1332 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1333 | size--; |
Ville Syrjälä | 636280b | 2015-03-12 17:10:29 +0200 | [diff] [blame] | 1334 | |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1335 | return size; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1336 | } |
| 1337 | |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1338 | static void |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1339 | intel_dp_set_clock(struct intel_encoder *encoder, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1340 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1341 | { |
| 1342 | struct drm_device *dev = encoder->base.dev; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1343 | const struct dp_link_dpll *divisor = NULL; |
| 1344 | int i, count = 0; |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1345 | |
| 1346 | if (IS_G4X(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1347 | divisor = gen4_dpll; |
| 1348 | count = ARRAY_SIZE(gen4_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1349 | } else if (HAS_PCH_SPLIT(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1350 | divisor = pch_dpll; |
| 1351 | count = ARRAY_SIZE(pch_dpll); |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1352 | } else if (IS_CHERRYVIEW(dev)) { |
| 1353 | divisor = chv_dpll; |
| 1354 | count = ARRAY_SIZE(chv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1355 | } else if (IS_VALLEYVIEW(dev)) { |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 1356 | divisor = vlv_dpll; |
| 1357 | count = ARRAY_SIZE(vlv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1358 | } |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1359 | |
| 1360 | if (divisor && count) { |
| 1361 | for (i = 0; i < count; i++) { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1362 | if (pipe_config->port_clock == divisor[i].clock) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1363 | pipe_config->dpll = divisor[i].dpll; |
| 1364 | pipe_config->clock_set = true; |
| 1365 | break; |
| 1366 | } |
| 1367 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1368 | } |
| 1369 | } |
| 1370 | |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1371 | static int intersect_rates(const int *source_rates, int source_len, |
| 1372 | const int *sink_rates, int sink_len, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1373 | int *common_rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1374 | { |
| 1375 | int i = 0, j = 0, k = 0; |
| 1376 | |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1377 | while (i < source_len && j < sink_len) { |
| 1378 | if (source_rates[i] == sink_rates[j]) { |
Ville Syrjälä | e6bda3e | 2015-03-12 17:10:37 +0200 | [diff] [blame] | 1379 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
| 1380 | return k; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1381 | common_rates[k] = source_rates[i]; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1382 | ++k; |
| 1383 | ++i; |
| 1384 | ++j; |
| 1385 | } else if (source_rates[i] < sink_rates[j]) { |
| 1386 | ++i; |
| 1387 | } else { |
| 1388 | ++j; |
| 1389 | } |
| 1390 | } |
| 1391 | return k; |
| 1392 | } |
| 1393 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1394 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
| 1395 | int *common_rates) |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1396 | { |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1397 | const int *source_rates, *sink_rates; |
| 1398 | int source_len, sink_len; |
| 1399 | |
| 1400 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1401 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1402 | |
| 1403 | return intersect_rates(source_rates, source_len, |
| 1404 | sink_rates, sink_len, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1405 | common_rates); |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1406 | } |
| 1407 | |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1408 | static void snprintf_int_array(char *str, size_t len, |
| 1409 | const int *array, int nelem) |
| 1410 | { |
| 1411 | int i; |
| 1412 | |
| 1413 | str[0] = '\0'; |
| 1414 | |
| 1415 | for (i = 0; i < nelem; i++) { |
Jani Nikula | b2f505b | 2015-05-18 16:01:45 +0300 | [diff] [blame] | 1416 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1417 | if (r >= len) |
| 1418 | return; |
| 1419 | str += r; |
| 1420 | len -= r; |
| 1421 | } |
| 1422 | } |
| 1423 | |
| 1424 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
| 1425 | { |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1426 | const int *source_rates, *sink_rates; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1427 | int source_len, sink_len, common_len; |
| 1428 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1429 | char str[128]; /* FIXME: too big for stack? */ |
| 1430 | |
| 1431 | if ((drm_debug & DRM_UT_KMS) == 0) |
| 1432 | return; |
| 1433 | |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1434 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1435 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
| 1436 | DRM_DEBUG_KMS("source rates: %s\n", str); |
| 1437 | |
| 1438 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
| 1439 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
| 1440 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
| 1441 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1442 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
| 1443 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
| 1444 | DRM_DEBUG_KMS("common rates: %s\n", str); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1445 | } |
| 1446 | |
Mika Kahola | 0e390a3 | 2016-09-09 14:10:53 +0300 | [diff] [blame] | 1447 | static void intel_dp_print_hw_revision(struct intel_dp *intel_dp) |
| 1448 | { |
| 1449 | uint8_t rev; |
| 1450 | int len; |
| 1451 | |
| 1452 | if ((drm_debug & DRM_UT_KMS) == 0) |
| 1453 | return; |
| 1454 | |
| 1455 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 1456 | DP_DWN_STRM_PORT_PRESENT)) |
| 1457 | return; |
| 1458 | |
| 1459 | len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_HW_REV, &rev, 1); |
| 1460 | if (len < 0) |
| 1461 | return; |
| 1462 | |
| 1463 | DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 0xf); |
| 1464 | } |
| 1465 | |
Mika Kahola | 1a2724f | 2016-09-09 14:10:54 +0300 | [diff] [blame] | 1466 | static void intel_dp_print_sw_revision(struct intel_dp *intel_dp) |
| 1467 | { |
| 1468 | uint8_t rev[2]; |
| 1469 | int len; |
| 1470 | |
| 1471 | if ((drm_debug & DRM_UT_KMS) == 0) |
| 1472 | return; |
| 1473 | |
| 1474 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 1475 | DP_DWN_STRM_PORT_PRESENT)) |
| 1476 | return; |
| 1477 | |
| 1478 | len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_SW_REV, &rev, 2); |
| 1479 | if (len < 0) |
| 1480 | return; |
| 1481 | |
| 1482 | DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]); |
| 1483 | } |
| 1484 | |
Ville Syrjälä | f4896f1 | 2015-03-12 17:10:27 +0200 | [diff] [blame] | 1485 | static int rate_to_index(int find, const int *rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1486 | { |
| 1487 | int i = 0; |
| 1488 | |
| 1489 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
| 1490 | if (find == rates[i]) |
| 1491 | break; |
| 1492 | |
| 1493 | return i; |
| 1494 | } |
| 1495 | |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1496 | int |
| 1497 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
| 1498 | { |
| 1499 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1500 | int len; |
| 1501 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1502 | len = intel_dp_common_rates(intel_dp, rates); |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1503 | if (WARN_ON(len <= 0)) |
| 1504 | return 162000; |
| 1505 | |
Ville Syrjälä | 1354f73 | 2016-07-28 17:50:45 +0300 | [diff] [blame] | 1506 | return rates[len - 1]; |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1507 | } |
| 1508 | |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 1509 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
| 1510 | { |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1511 | return rate_to_index(rate, intel_dp->sink_rates); |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 1512 | } |
| 1513 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 1514 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| 1515 | uint8_t *link_bw, uint8_t *rate_select) |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1516 | { |
| 1517 | if (intel_dp->num_sink_rates) { |
| 1518 | *link_bw = 0; |
| 1519 | *rate_select = |
| 1520 | intel_dp_rate_select(intel_dp, port_clock); |
| 1521 | } else { |
| 1522 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
| 1523 | *rate_select = 0; |
| 1524 | } |
| 1525 | } |
| 1526 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 1527 | bool |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1528 | intel_dp_compute_config(struct intel_encoder *encoder, |
Maarten Lankhorst | 0a478c2 | 2016-08-09 17:04:05 +0200 | [diff] [blame] | 1529 | struct intel_crtc_state *pipe_config, |
| 1530 | struct drm_connector_state *conn_state) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1531 | { |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1532 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1533 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 1534 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1535 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1536 | enum port port = dp_to_dig_port(intel_dp)->port; |
Ander Conselvan de Oliveira | 84556d5 | 2015-03-20 16:18:10 +0200 | [diff] [blame] | 1537 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 1538 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1539 | int lane_count, clock; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1540 | int min_lane_count = 1; |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 1541 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 1542 | /* Conveniently, the link BW constants become indices with a shift...*/ |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1543 | int min_clock = 0; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1544 | int max_clock; |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1545 | int bpp, mode_rate; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 1546 | int link_avail, link_clock; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1547 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1548 | int common_len; |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1549 | uint8_t link_bw, rate_select; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1550 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1551 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1552 | |
| 1553 | /* No common link rates between source and sink */ |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1554 | WARN_ON(common_len <= 0); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1555 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1556 | max_clock = common_len - 1; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1557 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1558 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1559 | pipe_config->has_pch_encoder = true; |
| 1560 | |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 1561 | pipe_config->has_drrs = false; |
Jani Nikula | 9fcb170 | 2015-05-05 16:32:12 +0300 | [diff] [blame] | 1562 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1563 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 1564 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 1565 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 1566 | adjusted_mode); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 1567 | |
| 1568 | if (INTEL_INFO(dev)->gen >= 9) { |
| 1569 | int ret; |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 1570 | ret = skl_update_scaler_crtc(pipe_config); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 1571 | if (ret) |
| 1572 | return ret; |
| 1573 | } |
| 1574 | |
Matt Roper | b5667627 | 2015-11-04 09:05:27 -0800 | [diff] [blame] | 1575 | if (HAS_GMCH_DISPLAY(dev)) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 1576 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 1577 | intel_connector->panel.fitting_mode); |
| 1578 | else |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 1579 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 1580 | intel_connector->panel.fitting_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 1581 | } |
| 1582 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 1583 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 1584 | return false; |
| 1585 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1586 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1587 | "max bw %d pixel clock %iKHz\n", |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1588 | max_lane_count, common_rates[max_clock], |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1589 | adjusted_mode->crtc_clock); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1590 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1591 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 1592 | * bpc in between. */ |
Daniel Vetter | 3e7ca98 | 2013-06-01 19:45:56 +0200 | [diff] [blame] | 1593 | bpp = pipe_config->pipe_bpp; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1594 | if (is_edp(intel_dp)) { |
Thulasimani,Sivakumar | 22ce562 | 2015-07-31 11:05:27 +0530 | [diff] [blame] | 1595 | |
| 1596 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
| 1597 | if (intel_connector->base.display_info.bpc == 0 && |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 1598 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1599 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 1600 | dev_priv->vbt.edp.bpp); |
| 1601 | bpp = dev_priv->vbt.edp.bpp; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1602 | } |
| 1603 | |
Jani Nikula | 344c5bb | 2014-09-09 11:25:13 +0300 | [diff] [blame] | 1604 | /* |
| 1605 | * Use the maximum clock and number of lanes the eDP panel |
| 1606 | * advertizes being capable of. The panels are generally |
| 1607 | * designed to support only a single clock and lane |
| 1608 | * configuration, and typically these values correspond to the |
| 1609 | * native resolution of the panel. |
| 1610 | */ |
| 1611 | min_lane_count = max_lane_count; |
| 1612 | min_clock = max_clock; |
Imre Deak | 7984211 | 2013-07-18 17:44:13 +0300 | [diff] [blame] | 1613 | } |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 1614 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1615 | for (; bpp >= 6*3; bpp -= 2*3) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1616 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 1617 | bpp); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 1618 | |
Dave Airlie | c693099 | 2014-07-14 11:04:39 +1000 | [diff] [blame] | 1619 | for (clock = min_clock; clock <= max_clock; clock++) { |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1620 | for (lane_count = min_lane_count; |
| 1621 | lane_count <= max_lane_count; |
| 1622 | lane_count <<= 1) { |
| 1623 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1624 | link_clock = common_rates[clock]; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1625 | link_avail = intel_dp_max_data_rate(link_clock, |
| 1626 | lane_count); |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 1627 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1628 | if (mode_rate <= link_avail) { |
| 1629 | goto found; |
| 1630 | } |
| 1631 | } |
| 1632 | } |
| 1633 | } |
| 1634 | |
| 1635 | return false; |
| 1636 | |
| 1637 | found: |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1638 | if (intel_dp->color_range_auto) { |
| 1639 | /* |
| 1640 | * See: |
| 1641 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 1642 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 1643 | */ |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1644 | pipe_config->limited_color_range = |
| 1645 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
| 1646 | } else { |
| 1647 | pipe_config->limited_color_range = |
| 1648 | intel_dp->limited_color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1649 | } |
| 1650 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 1651 | pipe_config->lane_count = lane_count; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1652 | |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 1653 | pipe_config->pipe_bpp = bpp; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1654 | pipe_config->port_clock = common_rates[clock]; |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 1655 | |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1656 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
| 1657 | &link_bw, &rate_select); |
| 1658 | |
| 1659 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
| 1660 | link_bw, rate_select, pipe_config->lane_count, |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 1661 | pipe_config->port_clock, bpp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1662 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 1663 | mode_rate, link_avail); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1664 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1665 | intel_link_compute_m_n(bpp, lane_count, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1666 | adjusted_mode->crtc_clock, |
| 1667 | pipe_config->port_clock, |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1668 | &pipe_config->dp_m_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1669 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1670 | if (intel_connector->panel.downclock_mode != NULL && |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 1671 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 1672 | pipe_config->has_drrs = true; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1673 | intel_link_compute_m_n(bpp, lane_count, |
| 1674 | intel_connector->panel.downclock_mode->clock, |
| 1675 | pipe_config->port_clock, |
| 1676 | &pipe_config->dp_m2_n2); |
| 1677 | } |
| 1678 | |
Ville Syrjälä | 14d41b3 | 2016-05-13 23:41:22 +0300 | [diff] [blame] | 1679 | /* |
| 1680 | * DPLL0 VCO may need to be adjusted to get the correct |
| 1681 | * clock for eDP. This will affect cdclk as well. |
| 1682 | */ |
| 1683 | if (is_edp(intel_dp) && |
| 1684 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { |
| 1685 | int vco; |
| 1686 | |
| 1687 | switch (pipe_config->port_clock / 2) { |
| 1688 | case 108000: |
| 1689 | case 216000: |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 1690 | vco = 8640000; |
Ville Syrjälä | 14d41b3 | 2016-05-13 23:41:22 +0300 | [diff] [blame] | 1691 | break; |
| 1692 | default: |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 1693 | vco = 8100000; |
Ville Syrjälä | 14d41b3 | 2016-05-13 23:41:22 +0300 | [diff] [blame] | 1694 | break; |
| 1695 | } |
| 1696 | |
| 1697 | to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; |
| 1698 | } |
| 1699 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 1700 | if (!HAS_DDI(dev)) |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1701 | intel_dp_set_clock(encoder, pipe_config); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1702 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1703 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1704 | } |
| 1705 | |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1706 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
Ander Conselvan de Oliveira | dfa1048 | 2016-09-01 15:08:06 -0700 | [diff] [blame] | 1707 | int link_rate, uint8_t lane_count, |
| 1708 | bool link_mst) |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1709 | { |
Ander Conselvan de Oliveira | dfa1048 | 2016-09-01 15:08:06 -0700 | [diff] [blame] | 1710 | intel_dp->link_rate = link_rate; |
| 1711 | intel_dp->lane_count = lane_count; |
| 1712 | intel_dp->link_mst = link_mst; |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1713 | } |
| 1714 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 1715 | static void intel_dp_prepare(struct intel_encoder *encoder, |
| 1716 | struct intel_crtc_state *pipe_config) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1717 | { |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1718 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1719 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1720 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1721 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1722 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 1723 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1724 | |
Ander Conselvan de Oliveira | dfa1048 | 2016-09-01 15:08:06 -0700 | [diff] [blame] | 1725 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
| 1726 | pipe_config->lane_count, |
| 1727 | intel_crtc_has_type(pipe_config, |
| 1728 | INTEL_OUTPUT_DP_MST)); |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1729 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1730 | /* |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1731 | * There are four kinds of DP registers: |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1732 | * |
| 1733 | * IBX PCH |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1734 | * SNB CPU |
| 1735 | * IVB CPU |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1736 | * CPT PCH |
| 1737 | * |
| 1738 | * IBX PCH and CPU are the same for almost everything, |
| 1739 | * except that the CPU DP PLL is configured in this |
| 1740 | * register |
| 1741 | * |
| 1742 | * CPT PCH is quite different, having many bits moved |
| 1743 | * to the TRANS_DP_CTL register instead. That |
| 1744 | * configuration happens (oddly) in ironlake_pch_enable |
| 1745 | */ |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 1746 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1747 | /* Preserve the BIOS-computed detected bit. This is |
| 1748 | * supposed to be read-only. |
| 1749 | */ |
| 1750 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1751 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1752 | /* Handle DP bits in common between all three register formats */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1753 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 1754 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1755 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1756 | /* Split out the IBX/CPU vs CPT settings */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1757 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1758 | if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1759 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1760 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1761 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1762 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1763 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1764 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1765 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1766 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1767 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 1768 | intel_dp->DP |= crtc->pipe << 29; |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1769 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 1770 | u32 trans_dp; |
| 1771 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1772 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 1773 | |
| 1774 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 1775 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1776 | trans_dp |= TRANS_DP_ENH_FRAMING; |
| 1777 | else |
| 1778 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
| 1779 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1780 | } else { |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1781 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 1782 | !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range) |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1783 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1784 | |
| 1785 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1786 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1787 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1788 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1789 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 1790 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1791 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1792 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1793 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1794 | if (IS_CHERRYVIEW(dev)) |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1795 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1796 | else if (crtc->pipe == PIPE_B) |
| 1797 | intel_dp->DP |= DP_PIPEB_SELECT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1798 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1799 | } |
| 1800 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1801 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 1802 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1803 | |
Paulo Zanoni | 1a5ef5b | 2013-12-19 14:29:43 -0200 | [diff] [blame] | 1804 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| 1805 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1806 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1807 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 1808 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1809 | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 1810 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
| 1811 | struct intel_dp *intel_dp); |
| 1812 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1813 | static void wait_panel_status(struct intel_dp *intel_dp, |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1814 | u32 mask, |
| 1815 | u32 value) |
| 1816 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1817 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1818 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1819 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1820 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1821 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1822 | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 1823 | intel_pps_verify_state(dev_priv, intel_dp); |
| 1824 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1825 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1826 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1827 | |
| 1828 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1829 | mask, value, |
| 1830 | I915_READ(pp_stat_reg), |
| 1831 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1832 | |
Chris Wilson | 9036ff0 | 2016-06-30 15:33:09 +0100 | [diff] [blame] | 1833 | if (intel_wait_for_register(dev_priv, |
| 1834 | pp_stat_reg, mask, value, |
| 1835 | 5000)) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1836 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1837 | I915_READ(pp_stat_reg), |
| 1838 | I915_READ(pp_ctrl_reg)); |
Chris Wilson | 54c136d | 2013-12-02 09:57:16 +0000 | [diff] [blame] | 1839 | |
| 1840 | DRM_DEBUG_KMS("Wait complete\n"); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1841 | } |
| 1842 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1843 | static void wait_panel_on(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1844 | { |
| 1845 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1846 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1847 | } |
| 1848 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1849 | static void wait_panel_off(struct intel_dp *intel_dp) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1850 | { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1851 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1852 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1853 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1854 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1855 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1856 | { |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1857 | ktime_t panel_power_on_time; |
| 1858 | s64 panel_power_off_duration; |
| 1859 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1860 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1861 | |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1862 | /* take the difference of currrent time and panel power off time |
| 1863 | * and then make panel wait for t11_t12 if needed. */ |
| 1864 | panel_power_on_time = ktime_get_boottime(); |
| 1865 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); |
| 1866 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1867 | /* When we disable the VDD override bit last we have to do the manual |
| 1868 | * wait. */ |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1869 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
| 1870 | wait_remaining_ms_from_jiffies(jiffies, |
| 1871 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1872 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1873 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1874 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1875 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1876 | static void wait_backlight_on(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1877 | { |
| 1878 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 1879 | intel_dp->backlight_on_delay); |
| 1880 | } |
| 1881 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1882 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1883 | { |
| 1884 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 1885 | intel_dp->backlight_off_delay); |
| 1886 | } |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1887 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1888 | /* Read the current pp_control value, unlocking the register if it |
| 1889 | * is locked |
| 1890 | */ |
| 1891 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1892 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1893 | { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1894 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1895 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1896 | u32 control; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1897 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1898 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1899 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1900 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
Imre Deak | 8090ba8 | 2016-08-10 14:07:33 +0300 | [diff] [blame] | 1901 | if (WARN_ON(!HAS_DDI(dev_priv) && |
| 1902 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 1903 | control &= ~PANEL_UNLOCK_MASK; |
| 1904 | control |= PANEL_UNLOCK_REGS; |
| 1905 | } |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1906 | return control; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1907 | } |
| 1908 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1909 | /* |
| 1910 | * Must be paired with edp_panel_vdd_off(). |
| 1911 | * Must hold pps_mutex around the whole on/off sequence. |
| 1912 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1913 | */ |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 1914 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1915 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1916 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1917 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1918 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1919 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1920 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1921 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1922 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1923 | bool need_to_disable = !intel_dp->want_panel_vdd; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1924 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1925 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1926 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1927 | if (!is_edp(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1928 | return false; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1929 | |
Egbert Eich | 2c623c1 | 2014-11-25 12:54:57 +0100 | [diff] [blame] | 1930 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1931 | intel_dp->want_panel_vdd = true; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1932 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1933 | if (edp_have_panel_vdd(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1934 | return need_to_disable; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1935 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 1936 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1937 | intel_display_power_get(dev_priv, power_domain); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1938 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1939 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
| 1940 | port_name(intel_dig_port->port)); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1941 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1942 | if (!edp_have_panel_power(intel_dp)) |
| 1943 | wait_panel_power_cycle(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1944 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1945 | pp = ironlake_get_pp_control(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1946 | pp |= EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1947 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1948 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1949 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1950 | |
| 1951 | I915_WRITE(pp_ctrl_reg, pp); |
| 1952 | POSTING_READ(pp_ctrl_reg); |
| 1953 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1954 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1955 | /* |
| 1956 | * If the panel wasn't on, delay before accessing aux channel |
| 1957 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1958 | if (!edp_have_panel_power(intel_dp)) { |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1959 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
| 1960 | port_name(intel_dig_port->port)); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1961 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1962 | } |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1963 | |
| 1964 | return need_to_disable; |
| 1965 | } |
| 1966 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1967 | /* |
| 1968 | * Must be paired with intel_edp_panel_vdd_off() or |
| 1969 | * intel_edp_panel_off(). |
| 1970 | * Nested calls to these functions are not allowed since |
| 1971 | * we drop the lock. Caller must use some higher level |
| 1972 | * locking to prevent nested calls from other threads. |
| 1973 | */ |
Daniel Vetter | b80d6c7 | 2014-03-19 15:54:37 +0100 | [diff] [blame] | 1974 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1975 | { |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1976 | bool vdd; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1977 | |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1978 | if (!is_edp(intel_dp)) |
| 1979 | return; |
| 1980 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1981 | pps_lock(intel_dp); |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1982 | vdd = edp_panel_vdd_on(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1983 | pps_unlock(intel_dp); |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1984 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1985 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1986 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1987 | } |
| 1988 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1989 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1990 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1991 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1992 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1993 | struct intel_digital_port *intel_dig_port = |
| 1994 | dp_to_dig_port(intel_dp); |
| 1995 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1996 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1997 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1998 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1999 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2000 | lockdep_assert_held(&dev_priv->pps_mutex); |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 2001 | |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 2002 | WARN_ON(intel_dp->want_panel_vdd); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2003 | |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 2004 | if (!edp_have_panel_vdd(intel_dp)) |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 2005 | return; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 2006 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2007 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
| 2008 | port_name(intel_dig_port->port)); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2009 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 2010 | pp = ironlake_get_pp_control(intel_dp); |
| 2011 | pp &= ~EDP_FORCE_VDD; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2012 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 2013 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 2014 | pp_stat_reg = _pp_stat_reg(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2015 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 2016 | I915_WRITE(pp_ctrl_reg, pp); |
| 2017 | POSTING_READ(pp_ctrl_reg); |
Paulo Zanoni | 90791a5 | 2013-12-06 17:32:42 -0200 | [diff] [blame] | 2018 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 2019 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 2020 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 2021 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 2022 | |
Imre Deak | 5a162e2 | 2016-08-10 14:07:30 +0300 | [diff] [blame] | 2023 | if ((pp & PANEL_POWER_ON) == 0) |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 2024 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 2025 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 2026 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 2027 | intel_display_power_put(dev_priv, power_domain); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2028 | } |
| 2029 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2030 | static void edp_panel_vdd_work(struct work_struct *__work) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2031 | { |
| 2032 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 2033 | struct intel_dp, panel_vdd_work); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2034 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2035 | pps_lock(intel_dp); |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 2036 | if (!intel_dp->want_panel_vdd) |
| 2037 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2038 | pps_unlock(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2039 | } |
| 2040 | |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 2041 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
| 2042 | { |
| 2043 | unsigned long delay; |
| 2044 | |
| 2045 | /* |
| 2046 | * Queue the timer to fire a long time from now (relative to the power |
| 2047 | * down delay) to keep the panel power up across a sequence of |
| 2048 | * operations. |
| 2049 | */ |
| 2050 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
| 2051 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
| 2052 | } |
| 2053 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 2054 | /* |
| 2055 | * Must be paired with edp_panel_vdd_on(). |
| 2056 | * Must hold pps_mutex around the whole on/off sequence. |
| 2057 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 2058 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2059 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2060 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2061 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2062 | |
| 2063 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2064 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2065 | if (!is_edp(intel_dp)) |
| 2066 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2067 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 2068 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2069 | port_name(dp_to_dig_port(intel_dp)->port)); |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 2070 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2071 | intel_dp->want_panel_vdd = false; |
| 2072 | |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 2073 | if (sync) |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2074 | edp_panel_vdd_off_sync(intel_dp); |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 2075 | else |
| 2076 | edp_panel_vdd_schedule_off(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2077 | } |
| 2078 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2079 | static void edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2080 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2081 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2082 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2083 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2084 | i915_reg_t pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2085 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2086 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2087 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2088 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2089 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2090 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2091 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
| 2092 | port_name(dp_to_dig_port(intel_dp)->port)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2093 | |
Ville Syrjälä | e7a89ac | 2014-10-16 21:30:07 +0300 | [diff] [blame] | 2094 | if (WARN(edp_have_panel_power(intel_dp), |
| 2095 | "eDP port %c panel power already on\n", |
| 2096 | port_name(dp_to_dig_port(intel_dp)->port))) |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2097 | return; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2098 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2099 | wait_panel_power_cycle(intel_dp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2100 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2101 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2102 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2103 | if (IS_GEN5(dev)) { |
| 2104 | /* ILK workaround: disable reset around power sequence */ |
| 2105 | pp &= ~PANEL_POWER_RESET; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2106 | I915_WRITE(pp_ctrl_reg, pp); |
| 2107 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2108 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2109 | |
Imre Deak | 5a162e2 | 2016-08-10 14:07:30 +0300 | [diff] [blame] | 2110 | pp |= PANEL_POWER_ON; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2111 | if (!IS_GEN5(dev)) |
| 2112 | pp |= PANEL_POWER_RESET; |
| 2113 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2114 | I915_WRITE(pp_ctrl_reg, pp); |
| 2115 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2116 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2117 | wait_panel_on(intel_dp); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2118 | intel_dp->last_power_on = jiffies; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2119 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2120 | if (IS_GEN5(dev)) { |
| 2121 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2122 | I915_WRITE(pp_ctrl_reg, pp); |
| 2123 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2124 | } |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2125 | } |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2126 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2127 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
| 2128 | { |
| 2129 | if (!is_edp(intel_dp)) |
| 2130 | return; |
| 2131 | |
| 2132 | pps_lock(intel_dp); |
| 2133 | edp_panel_on(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2134 | pps_unlock(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2135 | } |
| 2136 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2137 | |
| 2138 | static void edp_panel_off(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2139 | { |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2140 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2141 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2142 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2143 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2144 | enum intel_display_power_domain power_domain; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2145 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2146 | i915_reg_t pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2147 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2148 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2149 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2150 | if (!is_edp(intel_dp)) |
| 2151 | return; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2152 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2153 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
| 2154 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2155 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2156 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
| 2157 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2158 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2159 | pp = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 2160 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 2161 | * panels get very unhappy and cease to work. */ |
Imre Deak | 5a162e2 | 2016-08-10 14:07:30 +0300 | [diff] [blame] | 2162 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
Patrik Jakobsson | b306415 | 2014-03-04 00:42:44 +0100 | [diff] [blame] | 2163 | EDP_BLC_ENABLE); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2164 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2165 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2166 | |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 2167 | intel_dp->want_panel_vdd = false; |
| 2168 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2169 | I915_WRITE(pp_ctrl_reg, pp); |
| 2170 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2171 | |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 2172 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2173 | wait_panel_off(intel_dp); |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 2174 | |
| 2175 | /* We got a reference when we enabled the VDD. */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 2176 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2177 | intel_display_power_put(dev_priv, power_domain); |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2178 | } |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2179 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2180 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
| 2181 | { |
| 2182 | if (!is_edp(intel_dp)) |
| 2183 | return; |
| 2184 | |
| 2185 | pps_lock(intel_dp); |
| 2186 | edp_panel_off(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2187 | pps_unlock(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2188 | } |
| 2189 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2190 | /* Enable backlight in the panel power control. */ |
| 2191 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2192 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2193 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2194 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2195 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2196 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2197 | i915_reg_t pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2198 | |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 2199 | /* |
| 2200 | * If we enable the backlight right away following a panel power |
| 2201 | * on, we may see slight flicker as the panel syncs with the eDP |
| 2202 | * link. So delay a bit to make sure the image is solid before |
| 2203 | * allowing it to appear. |
| 2204 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2205 | wait_backlight_on(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2206 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2207 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2208 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2209 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2210 | pp |= EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2211 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2212 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2213 | |
| 2214 | I915_WRITE(pp_ctrl_reg, pp); |
| 2215 | POSTING_READ(pp_ctrl_reg); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2216 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2217 | pps_unlock(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2218 | } |
| 2219 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2220 | /* Enable backlight PWM and backlight PP control. */ |
| 2221 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 2222 | { |
| 2223 | if (!is_edp(intel_dp)) |
| 2224 | return; |
| 2225 | |
| 2226 | DRM_DEBUG_KMS("\n"); |
| 2227 | |
| 2228 | intel_panel_enable_backlight(intel_dp->attached_connector); |
| 2229 | _intel_edp_backlight_on(intel_dp); |
| 2230 | } |
| 2231 | |
| 2232 | /* Disable backlight in the panel power control. */ |
| 2233 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2234 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2235 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2236 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2237 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2238 | i915_reg_t pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2239 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2240 | if (!is_edp(intel_dp)) |
| 2241 | return; |
| 2242 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2243 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2244 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2245 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2246 | pp &= ~EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2247 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2248 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2249 | |
| 2250 | I915_WRITE(pp_ctrl_reg, pp); |
| 2251 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2252 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2253 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2254 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2255 | intel_dp->last_backlight_off = jiffies; |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2256 | edp_wait_backlight_off(intel_dp); |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2257 | } |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2258 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2259 | /* Disable backlight PP control and backlight PWM. */ |
| 2260 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 2261 | { |
| 2262 | if (!is_edp(intel_dp)) |
| 2263 | return; |
| 2264 | |
| 2265 | DRM_DEBUG_KMS("\n"); |
| 2266 | |
| 2267 | _intel_edp_backlight_off(intel_dp); |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2268 | intel_panel_disable_backlight(intel_dp->attached_connector); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2269 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2270 | |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2271 | /* |
| 2272 | * Hook for controlling the panel power control backlight through the bl_power |
| 2273 | * sysfs attribute. Take care to handle multiple calls. |
| 2274 | */ |
| 2275 | static void intel_edp_backlight_power(struct intel_connector *connector, |
| 2276 | bool enable) |
| 2277 | { |
| 2278 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2279 | bool is_enabled; |
| 2280 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2281 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2282 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2283 | pps_unlock(intel_dp); |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2284 | |
| 2285 | if (is_enabled == enable) |
| 2286 | return; |
| 2287 | |
Jani Nikula | 23ba937 | 2014-08-27 14:08:43 +0300 | [diff] [blame] | 2288 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
| 2289 | enable ? "enable" : "disable"); |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2290 | |
| 2291 | if (enable) |
| 2292 | _intel_edp_backlight_on(intel_dp); |
| 2293 | else |
| 2294 | _intel_edp_backlight_off(intel_dp); |
| 2295 | } |
| 2296 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2297 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
| 2298 | { |
| 2299 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2300 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| 2301 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; |
| 2302 | |
| 2303 | I915_STATE_WARN(cur_state != state, |
| 2304 | "DP port %c state assertion failure (expected %s, current %s)\n", |
| 2305 | port_name(dig_port->port), |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 2306 | onoff(state), onoff(cur_state)); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2307 | } |
| 2308 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) |
| 2309 | |
| 2310 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) |
| 2311 | { |
| 2312 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; |
| 2313 | |
| 2314 | I915_STATE_WARN(cur_state != state, |
| 2315 | "eDP PLL state assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 2316 | onoff(state), onoff(cur_state)); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2317 | } |
| 2318 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) |
| 2319 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) |
| 2320 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2321 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
| 2322 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2323 | { |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2324 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2325 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2326 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2327 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2328 | assert_dp_port_disabled(intel_dp); |
| 2329 | assert_edp_pll_disabled(dev_priv); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2330 | |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2331 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2332 | pipe_config->port_clock); |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2333 | |
| 2334 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; |
| 2335 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2336 | if (pipe_config->port_clock == 162000) |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2337 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
| 2338 | else |
| 2339 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 2340 | |
| 2341 | I915_WRITE(DP_A, intel_dp->DP); |
| 2342 | POSTING_READ(DP_A); |
| 2343 | udelay(500); |
| 2344 | |
Ville Syrjälä | 6b23f3e | 2016-04-01 21:53:19 +0300 | [diff] [blame] | 2345 | /* |
| 2346 | * [DevILK] Work around required when enabling DP PLL |
| 2347 | * while a pipe is enabled going to FDI: |
| 2348 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI |
| 2349 | * 2. Program DP PLL enable |
| 2350 | */ |
| 2351 | if (IS_GEN5(dev_priv)) |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 2352 | intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe); |
Ville Syrjälä | 6b23f3e | 2016-04-01 21:53:19 +0300 | [diff] [blame] | 2353 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2354 | intel_dp->DP |= DP_PLL_ENABLE; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2355 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2356 | I915_WRITE(DP_A, intel_dp->DP); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 2357 | POSTING_READ(DP_A); |
| 2358 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2359 | } |
| 2360 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2361 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2362 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2363 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2364 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2365 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2366 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2367 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2368 | assert_dp_port_disabled(intel_dp); |
| 2369 | assert_edp_pll_enabled(dev_priv); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2370 | |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2371 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
| 2372 | |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2373 | intel_dp->DP &= ~DP_PLL_ENABLE; |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2374 | |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2375 | I915_WRITE(DP_A, intel_dp->DP); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 2376 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2377 | udelay(200); |
| 2378 | } |
| 2379 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2380 | /* If the sink supports it, try to set the power state appropriately */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2381 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2382 | { |
| 2383 | int ret, i; |
| 2384 | |
| 2385 | /* Should have a valid DPCD by this point */ |
| 2386 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 2387 | return; |
| 2388 | |
| 2389 | if (mode != DRM_MODE_DPMS_ON) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2390 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2391 | DP_SET_POWER_D3); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2392 | } else { |
| 2393 | /* |
| 2394 | * When turning on, we need to retry for 1ms to give the sink |
| 2395 | * time to wake up. |
| 2396 | */ |
| 2397 | for (i = 0; i < 3; i++) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2398 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2399 | DP_SET_POWER_D0); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2400 | if (ret == 1) |
| 2401 | break; |
| 2402 | msleep(1); |
| 2403 | } |
| 2404 | } |
Jani Nikula | f9cac72 | 2014-09-02 16:33:52 +0300 | [diff] [blame] | 2405 | |
| 2406 | if (ret != 1) |
| 2407 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
| 2408 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2409 | } |
| 2410 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2411 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 2412 | enum pipe *pipe) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2413 | { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2414 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2415 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2416 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2417 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2418 | enum intel_display_power_domain power_domain; |
| 2419 | u32 tmp; |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2420 | bool ret; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2421 | |
| 2422 | power_domain = intel_display_port_power_domain(encoder); |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2423 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2424 | return false; |
| 2425 | |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2426 | ret = false; |
| 2427 | |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2428 | tmp = I915_READ(intel_dp->output_reg); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2429 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2430 | if (!(tmp & DP_PORT_EN)) |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2431 | goto out; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2432 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2433 | if (IS_GEN7(dev) && port == PORT_A) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2434 | *pipe = PORT_TO_PIPE_CPT(tmp); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2435 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | adc289d | 2015-05-05 17:17:30 +0300 | [diff] [blame] | 2436 | enum pipe p; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2437 | |
Ville Syrjälä | adc289d | 2015-05-05 17:17:30 +0300 | [diff] [blame] | 2438 | for_each_pipe(dev_priv, p) { |
| 2439 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
| 2440 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
| 2441 | *pipe = p; |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2442 | ret = true; |
| 2443 | |
| 2444 | goto out; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2445 | } |
| 2446 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2447 | |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 2448 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2449 | i915_mmio_reg_offset(intel_dp->output_reg)); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2450 | } else if (IS_CHERRYVIEW(dev)) { |
| 2451 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
| 2452 | } else { |
| 2453 | *pipe = PORT_TO_PIPE(tmp); |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 2454 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2455 | |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2456 | ret = true; |
| 2457 | |
| 2458 | out: |
| 2459 | intel_display_power_put(dev_priv, power_domain); |
| 2460 | |
| 2461 | return ret; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2462 | } |
| 2463 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2464 | static void intel_dp_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 2465 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2466 | { |
| 2467 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2468 | u32 tmp, flags = 0; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2469 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2470 | struct drm_i915_private *dev_priv = to_i915(dev); |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2471 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2472 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2473 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2474 | tmp = I915_READ(intel_dp->output_reg); |
Jani Nikula | 9fcb170 | 2015-05-05 16:32:12 +0300 | [diff] [blame] | 2475 | |
| 2476 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2477 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2478 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | b81e34c | 2015-07-06 15:10:03 +0300 | [diff] [blame] | 2479 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 2480 | |
| 2481 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2482 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2483 | else |
| 2484 | flags |= DRM_MODE_FLAG_NHSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2485 | |
Ville Syrjälä | b81e34c | 2015-07-06 15:10:03 +0300 | [diff] [blame] | 2486 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2487 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2488 | else |
| 2489 | flags |= DRM_MODE_FLAG_NVSYNC; |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2490 | } else { |
| 2491 | if (tmp & DP_SYNC_HS_HIGH) |
| 2492 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2493 | else |
| 2494 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 2495 | |
| 2496 | if (tmp & DP_SYNC_VS_HIGH) |
| 2497 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2498 | else |
| 2499 | flags |= DRM_MODE_FLAG_NVSYNC; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2500 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2501 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 2502 | pipe_config->base.adjusted_mode.flags |= flags; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 2503 | |
Ville Syrjälä | 8c875fc | 2014-09-12 15:46:29 +0300 | [diff] [blame] | 2504 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2505 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
Ville Syrjälä | 8c875fc | 2014-09-12 15:46:29 +0300 | [diff] [blame] | 2506 | pipe_config->limited_color_range = true; |
| 2507 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 2508 | pipe_config->lane_count = |
| 2509 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
| 2510 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2511 | intel_dp_get_m_n(crtc, pipe_config); |
| 2512 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2513 | if (port == PORT_A) { |
Ville Syrjälä | b377e0d | 2015-10-29 21:25:59 +0200 | [diff] [blame] | 2514 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 2515 | pipe_config->port_clock = 162000; |
| 2516 | else |
| 2517 | pipe_config->port_clock = 270000; |
| 2518 | } |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2519 | |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 2520 | pipe_config->base.adjusted_mode.crtc_clock = |
| 2521 | intel_dotclock_calculate(pipe_config->port_clock, |
| 2522 | &pipe_config->dp_m_n); |
Daniel Vetter | 7f16e5c | 2013-11-04 16:28:47 +0100 | [diff] [blame] | 2523 | |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 2524 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
| 2525 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 2526 | /* |
| 2527 | * This is a big fat ugly hack. |
| 2528 | * |
| 2529 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 2530 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 2531 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 2532 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 2533 | * max, not what it tells us to use. |
| 2534 | * |
| 2535 | * Note: This will still be broken if the eDP panel is not lit |
| 2536 | * up by the BIOS, and thus we can't get the mode at module |
| 2537 | * load. |
| 2538 | */ |
| 2539 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 2540 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
| 2541 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 2542 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2543 | } |
| 2544 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2545 | static void intel_disable_dp(struct intel_encoder *encoder, |
| 2546 | struct intel_crtc_state *old_crtc_state, |
| 2547 | struct drm_connector_state *old_conn_state) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2548 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2549 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2550 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Jani Nikula | 495a5bb | 2014-10-27 16:26:55 +0200 | [diff] [blame] | 2551 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2552 | if (old_crtc_state->has_audio) |
Jani Nikula | 495a5bb | 2014-10-27 16:26:55 +0200 | [diff] [blame] | 2553 | intel_audio_codec_disable(encoder); |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 2554 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2555 | if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2556 | intel_psr_disable(intel_dp); |
| 2557 | |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 2558 | /* Make sure the panel is off before trying to change the mode. But also |
| 2559 | * ensure that we have vdd while we switch off the panel. */ |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2560 | intel_edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2561 | intel_edp_backlight_off(intel_dp); |
Jani Nikula | fdbc3b1 | 2013-11-12 17:10:13 +0200 | [diff] [blame] | 2562 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2563 | intel_edp_panel_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 2564 | |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2565 | /* disable the port before the pipe on g4x */ |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2566 | if (INTEL_GEN(dev_priv) < 5) |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 2567 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2568 | } |
| 2569 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2570 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
| 2571 | struct intel_crtc_state *old_crtc_state, |
| 2572 | struct drm_connector_state *old_conn_state) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2573 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2574 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 2575 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2576 | |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2577 | intel_dp_link_down(intel_dp); |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2578 | |
| 2579 | /* Only ilk+ has port A */ |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2580 | if (port == PORT_A) |
| 2581 | ironlake_edp_pll_off(intel_dp); |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2582 | } |
| 2583 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2584 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
| 2585 | struct intel_crtc_state *old_crtc_state, |
| 2586 | struct drm_connector_state *old_conn_state) |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2587 | { |
| 2588 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2589 | |
| 2590 | intel_dp_link_down(intel_dp); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2591 | } |
| 2592 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2593 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
| 2594 | struct intel_crtc_state *old_crtc_state, |
| 2595 | struct drm_connector_state *old_conn_state) |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2596 | { |
| 2597 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2598 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2599 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2600 | |
| 2601 | intel_dp_link_down(intel_dp); |
| 2602 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2603 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2604 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 2605 | /* Assert data lane reset */ |
| 2606 | chv_data_lane_soft_reset(encoder, true); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2607 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2608 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2609 | } |
| 2610 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2611 | static void |
| 2612 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
| 2613 | uint32_t *DP, |
| 2614 | uint8_t dp_train_pat) |
| 2615 | { |
| 2616 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2617 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2618 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2619 | enum port port = intel_dig_port->port; |
| 2620 | |
Pandiyan, Dhinakaran | 8b0878a | 2016-08-04 13:48:35 -0700 | [diff] [blame] | 2621 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
| 2622 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", |
| 2623 | dp_train_pat & DP_TRAINING_PATTERN_MASK); |
| 2624 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2625 | if (HAS_DDI(dev)) { |
| 2626 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
| 2627 | |
| 2628 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 2629 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2630 | else |
| 2631 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2632 | |
| 2633 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2634 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2635 | case DP_TRAINING_PATTERN_DISABLE: |
| 2636 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 2637 | |
| 2638 | break; |
| 2639 | case DP_TRAINING_PATTERN_1: |
| 2640 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2641 | break; |
| 2642 | case DP_TRAINING_PATTERN_2: |
| 2643 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 2644 | break; |
| 2645 | case DP_TRAINING_PATTERN_3: |
| 2646 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 2647 | break; |
| 2648 | } |
| 2649 | I915_WRITE(DP_TP_CTL(port), temp); |
| 2650 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2651 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
| 2652 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2653 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 2654 | |
| 2655 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2656 | case DP_TRAINING_PATTERN_DISABLE: |
| 2657 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
| 2658 | break; |
| 2659 | case DP_TRAINING_PATTERN_1: |
| 2660 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
| 2661 | break; |
| 2662 | case DP_TRAINING_PATTERN_2: |
| 2663 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2664 | break; |
| 2665 | case DP_TRAINING_PATTERN_3: |
Pandiyan, Dhinakaran | 8b0878a | 2016-08-04 13:48:35 -0700 | [diff] [blame] | 2666 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2667 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2668 | break; |
| 2669 | } |
| 2670 | |
| 2671 | } else { |
| 2672 | if (IS_CHERRYVIEW(dev)) |
| 2673 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 2674 | else |
| 2675 | *DP &= ~DP_LINK_TRAIN_MASK; |
| 2676 | |
| 2677 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2678 | case DP_TRAINING_PATTERN_DISABLE: |
| 2679 | *DP |= DP_LINK_TRAIN_OFF; |
| 2680 | break; |
| 2681 | case DP_TRAINING_PATTERN_1: |
| 2682 | *DP |= DP_LINK_TRAIN_PAT_1; |
| 2683 | break; |
| 2684 | case DP_TRAINING_PATTERN_2: |
| 2685 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2686 | break; |
| 2687 | case DP_TRAINING_PATTERN_3: |
| 2688 | if (IS_CHERRYVIEW(dev)) { |
| 2689 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
| 2690 | } else { |
Pandiyan, Dhinakaran | 8b0878a | 2016-08-04 13:48:35 -0700 | [diff] [blame] | 2691 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2692 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2693 | } |
| 2694 | break; |
| 2695 | } |
| 2696 | } |
| 2697 | } |
| 2698 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2699 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
| 2700 | struct intel_crtc_state *old_crtc_state) |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2701 | { |
| 2702 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2703 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2704 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2705 | /* enable with pattern 1 (as per spec) */ |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2706 | |
Pandiyan, Dhinakaran | 8b0878a | 2016-08-04 13:48:35 -0700 | [diff] [blame] | 2707 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
Ville Syrjälä | 7b713f5 | 2014-10-16 21:27:35 +0300 | [diff] [blame] | 2708 | |
| 2709 | /* |
| 2710 | * Magic for VLV/CHV. We _must_ first set up the register |
| 2711 | * without actually enabling the port, and then do another |
| 2712 | * write to enable the port. Otherwise link training will |
| 2713 | * fail when the power sequencer is freshly used for this port. |
| 2714 | */ |
| 2715 | intel_dp->DP |= DP_PORT_EN; |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2716 | if (old_crtc_state->has_audio) |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2717 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Ville Syrjälä | 7b713f5 | 2014-10-16 21:27:35 +0300 | [diff] [blame] | 2718 | |
| 2719 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2720 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2721 | } |
| 2722 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2723 | static void intel_enable_dp(struct intel_encoder *encoder, |
| 2724 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2725 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2726 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2727 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2728 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2729 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2730 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2731 | enum pipe pipe = crtc->pipe; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2732 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 2733 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 2734 | return; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2735 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2736 | pps_lock(intel_dp); |
| 2737 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2738 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2739 | vlv_init_panel_power_sequencer(intel_dp); |
| 2740 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2741 | intel_dp_enable_port(intel_dp, pipe_config); |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2742 | |
| 2743 | edp_panel_vdd_on(intel_dp); |
| 2744 | edp_panel_on(intel_dp); |
| 2745 | edp_panel_vdd_off(intel_dp, true); |
| 2746 | |
| 2747 | pps_unlock(intel_dp); |
| 2748 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2749 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2750 | unsigned int lane_mask = 0x0; |
| 2751 | |
| 2752 | if (IS_CHERRYVIEW(dev)) |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2753 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2754 | |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 2755 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
| 2756 | lane_mask); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2757 | } |
Ville Syrjälä | 61234fa | 2014-10-16 21:27:34 +0300 | [diff] [blame] | 2758 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2759 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 2760 | intel_dp_start_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2761 | intel_dp_stop_link_train(intel_dp); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2762 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2763 | if (pipe_config->has_audio) { |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2764 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2765 | pipe_name(pipe)); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2766 | intel_audio_codec_enable(encoder); |
| 2767 | } |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2768 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2769 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2770 | static void g4x_enable_dp(struct intel_encoder *encoder, |
| 2771 | struct intel_crtc_state *pipe_config, |
| 2772 | struct drm_connector_state *conn_state) |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2773 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 2774 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2775 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2776 | intel_enable_dp(encoder, pipe_config); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2777 | intel_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2778 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2779 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2780 | static void vlv_enable_dp(struct intel_encoder *encoder, |
| 2781 | struct intel_crtc_state *pipe_config, |
| 2782 | struct drm_connector_state *conn_state) |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2783 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 2784 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2785 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2786 | intel_edp_backlight_on(intel_dp); |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2787 | intel_psr_enable(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2788 | } |
| 2789 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2790 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
| 2791 | struct intel_crtc_state *pipe_config, |
| 2792 | struct drm_connector_state *conn_state) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2793 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2794 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2795 | enum port port = dp_to_dig_port(intel_dp)->port; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2796 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2797 | intel_dp_prepare(encoder, pipe_config); |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 2798 | |
Daniel Vetter | d41f1ef | 2014-04-24 23:54:53 +0200 | [diff] [blame] | 2799 | /* Only ilk+ has port A */ |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2800 | if (port == PORT_A) |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2801 | ironlake_edp_pll_on(intel_dp, pipe_config); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2802 | } |
| 2803 | |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2804 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
| 2805 | { |
| 2806 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2807 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2808 | enum pipe pipe = intel_dp->pps_pipe; |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame] | 2809 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2810 | |
| 2811 | edp_panel_vdd_off_sync(intel_dp); |
| 2812 | |
| 2813 | /* |
| 2814 | * VLV seems to get confused when multiple power seqeuencers |
| 2815 | * have the same port selected (even if only one has power/vdd |
| 2816 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
| 2817 | * CHV on the other hand doesn't seem to mind having the same port |
| 2818 | * selected in multiple power seqeuencers, but let's clear the |
| 2819 | * port select always when logically disconnecting a power sequencer |
| 2820 | * from a port. |
| 2821 | */ |
| 2822 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
| 2823 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 2824 | I915_WRITE(pp_on_reg, 0); |
| 2825 | POSTING_READ(pp_on_reg); |
| 2826 | |
| 2827 | intel_dp->pps_pipe = INVALID_PIPE; |
| 2828 | } |
| 2829 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2830 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 2831 | enum pipe pipe) |
| 2832 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2833 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2834 | struct intel_encoder *encoder; |
| 2835 | |
| 2836 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2837 | |
Ville Syrjälä | ac3c12e | 2014-10-16 21:29:56 +0300 | [diff] [blame] | 2838 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
| 2839 | return; |
| 2840 | |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 2841 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2842 | struct intel_dp *intel_dp; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2843 | enum port port; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2844 | |
| 2845 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2846 | continue; |
| 2847 | |
| 2848 | intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2849 | port = dp_to_dig_port(intel_dp)->port; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2850 | |
| 2851 | if (intel_dp->pps_pipe != pipe) |
| 2852 | continue; |
| 2853 | |
| 2854 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2855 | pipe_name(pipe), port_name(port)); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2856 | |
Maarten Lankhorst | e02f9a0 | 2015-08-05 12:37:08 +0200 | [diff] [blame] | 2857 | WARN(encoder->base.crtc, |
Ville Syrjälä | 034e43c | 2014-10-16 21:27:28 +0300 | [diff] [blame] | 2858 | "stealing pipe %c power sequencer from active eDP port %c\n", |
| 2859 | pipe_name(pipe), port_name(port)); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2860 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2861 | /* make sure vdd is off before we steal it */ |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2862 | vlv_detach_power_sequencer(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2863 | } |
| 2864 | } |
| 2865 | |
| 2866 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
| 2867 | { |
| 2868 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2869 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 2870 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2871 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2872 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2873 | |
| 2874 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2875 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2876 | if (!is_edp(intel_dp)) |
| 2877 | return; |
| 2878 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2879 | if (intel_dp->pps_pipe == crtc->pipe) |
| 2880 | return; |
| 2881 | |
| 2882 | /* |
| 2883 | * If another power sequencer was being used on this |
| 2884 | * port previously make sure to turn off vdd there while |
| 2885 | * we still have control of it. |
| 2886 | */ |
| 2887 | if (intel_dp->pps_pipe != INVALID_PIPE) |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2888 | vlv_detach_power_sequencer(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2889 | |
| 2890 | /* |
| 2891 | * We may be stealing the power |
| 2892 | * sequencer from another port. |
| 2893 | */ |
| 2894 | vlv_steal_power_sequencer(dev, crtc->pipe); |
| 2895 | |
| 2896 | /* now it's all ours */ |
| 2897 | intel_dp->pps_pipe = crtc->pipe; |
| 2898 | |
| 2899 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
| 2900 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
| 2901 | |
| 2902 | /* init power sequencer on this pipe and port */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 2903 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 2904 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2905 | } |
| 2906 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2907 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
| 2908 | struct intel_crtc_state *pipe_config, |
| 2909 | struct drm_connector_state *conn_state) |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2910 | { |
Ander Conselvan de Oliveira | 5f68c27 | 2016-04-27 15:44:24 +0300 | [diff] [blame] | 2911 | vlv_phy_pre_encoder_enable(encoder); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2912 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2913 | intel_enable_dp(encoder, pipe_config); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2914 | } |
| 2915 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2916 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
| 2917 | struct intel_crtc_state *pipe_config, |
| 2918 | struct drm_connector_state *conn_state) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2919 | { |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2920 | intel_dp_prepare(encoder, pipe_config); |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 2921 | |
Ander Conselvan de Oliveira | 6da2e61 | 2016-04-27 15:44:23 +0300 | [diff] [blame] | 2922 | vlv_phy_pre_pll_enable(encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2923 | } |
| 2924 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2925 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
| 2926 | struct intel_crtc_state *pipe_config, |
| 2927 | struct drm_connector_state *conn_state) |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2928 | { |
Ander Conselvan de Oliveira | e7d2a717 | 2016-04-27 15:44:20 +0300 | [diff] [blame] | 2929 | chv_phy_pre_encoder_enable(encoder); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2930 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2931 | intel_enable_dp(encoder, pipe_config); |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 2932 | |
| 2933 | /* Second common lane will stay alive on its own now */ |
Ander Conselvan de Oliveira | e7d2a717 | 2016-04-27 15:44:20 +0300 | [diff] [blame] | 2934 | chv_phy_release_cl2_override(encoder); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2935 | } |
| 2936 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2937 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
| 2938 | struct intel_crtc_state *pipe_config, |
| 2939 | struct drm_connector_state *conn_state) |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2940 | { |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 2941 | intel_dp_prepare(encoder, pipe_config); |
Ville Syrjälä | 625695f | 2014-06-28 02:04:02 +0300 | [diff] [blame] | 2942 | |
Ander Conselvan de Oliveira | 419b1b7 | 2016-04-27 15:44:19 +0300 | [diff] [blame] | 2943 | chv_phy_pre_pll_enable(encoder); |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2944 | } |
| 2945 | |
Maarten Lankhorst | fd6bbda | 2016-08-09 17:04:04 +0200 | [diff] [blame] | 2946 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
| 2947 | struct intel_crtc_state *pipe_config, |
| 2948 | struct drm_connector_state *conn_state) |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 2949 | { |
Ander Conselvan de Oliveira | 204970b | 2016-04-27 15:44:21 +0300 | [diff] [blame] | 2950 | chv_phy_post_pll_disable(encoder); |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 2951 | } |
| 2952 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2953 | /* |
| 2954 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 2955 | * link status information |
| 2956 | */ |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 2957 | bool |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2958 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2959 | { |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 2960 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
| 2961 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2962 | } |
| 2963 | |
Paulo Zanoni | 1100244 | 2014-06-13 18:45:41 -0300 | [diff] [blame] | 2964 | /* These are source-specific values. */ |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 2965 | uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2966 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2967 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2968 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2969 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2970 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2971 | |
Vandana Kannan | 9314726 | 2014-11-18 15:45:29 +0530 | [diff] [blame] | 2972 | if (IS_BROXTON(dev)) |
| 2973 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 2974 | else if (INTEL_INFO(dev)->gen >= 9) { |
Jani Nikula | 06411f0 | 2016-03-24 17:50:21 +0200 | [diff] [blame] | 2975 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 2976 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 2977 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2978 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2979 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2980 | else if (IS_GEN7(dev) && port == PORT_A) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2981 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2982 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2983 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2984 | else |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2985 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2986 | } |
| 2987 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 2988 | uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2989 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 2990 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2991 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2992 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2993 | |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 2994 | if (INTEL_INFO(dev)->gen >= 9) { |
| 2995 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2996 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2997 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 2998 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2999 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3000 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3001 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 3002 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3003 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 3004 | default: |
| 3005 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3006 | } |
| 3007 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3008 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3009 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3010 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3011 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3012 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3013 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3014 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3015 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3016 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3017 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3018 | } |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 3019 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3020 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3021 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3022 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3023 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3024 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3025 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3026 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3027 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3028 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3029 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3030 | } |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3031 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3032 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3033 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3034 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3035 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3036 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3037 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3038 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3039 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3040 | } |
| 3041 | } else { |
| 3042 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3043 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3044 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3045 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3046 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3047 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3048 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3049 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3050 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3051 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3052 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3053 | } |
| 3054 | } |
| 3055 | |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3056 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3057 | { |
Ander Conselvan de Oliveira | 53d9872 | 2016-04-27 15:44:22 +0300 | [diff] [blame] | 3058 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3059 | unsigned long demph_reg_value, preemph_reg_value, |
| 3060 | uniqtranscale_reg_value; |
| 3061 | uint8_t train_set = intel_dp->train_set[0]; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3062 | |
| 3063 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3064 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3065 | preemph_reg_value = 0x0004000; |
| 3066 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3067 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3068 | demph_reg_value = 0x2B405555; |
| 3069 | uniqtranscale_reg_value = 0x552AB83A; |
| 3070 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3071 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3072 | demph_reg_value = 0x2B404040; |
| 3073 | uniqtranscale_reg_value = 0x5548B83A; |
| 3074 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3075 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3076 | demph_reg_value = 0x2B245555; |
| 3077 | uniqtranscale_reg_value = 0x5560B83A; |
| 3078 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3079 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3080 | demph_reg_value = 0x2B405555; |
| 3081 | uniqtranscale_reg_value = 0x5598DA3A; |
| 3082 | break; |
| 3083 | default: |
| 3084 | return 0; |
| 3085 | } |
| 3086 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3087 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3088 | preemph_reg_value = 0x0002000; |
| 3089 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3090 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3091 | demph_reg_value = 0x2B404040; |
| 3092 | uniqtranscale_reg_value = 0x5552B83A; |
| 3093 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3094 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3095 | demph_reg_value = 0x2B404848; |
| 3096 | uniqtranscale_reg_value = 0x5580B83A; |
| 3097 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3098 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3099 | demph_reg_value = 0x2B404040; |
| 3100 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3101 | break; |
| 3102 | default: |
| 3103 | return 0; |
| 3104 | } |
| 3105 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3106 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3107 | preemph_reg_value = 0x0000000; |
| 3108 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3109 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3110 | demph_reg_value = 0x2B305555; |
| 3111 | uniqtranscale_reg_value = 0x5570B83A; |
| 3112 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3113 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3114 | demph_reg_value = 0x2B2B4040; |
| 3115 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3116 | break; |
| 3117 | default: |
| 3118 | return 0; |
| 3119 | } |
| 3120 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3121 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3122 | preemph_reg_value = 0x0006000; |
| 3123 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3124 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3125 | demph_reg_value = 0x1B405555; |
| 3126 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3127 | break; |
| 3128 | default: |
| 3129 | return 0; |
| 3130 | } |
| 3131 | break; |
| 3132 | default: |
| 3133 | return 0; |
| 3134 | } |
| 3135 | |
Ander Conselvan de Oliveira | 53d9872 | 2016-04-27 15:44:22 +0300 | [diff] [blame] | 3136 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
| 3137 | uniqtranscale_reg_value, 0); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3138 | |
| 3139 | return 0; |
| 3140 | } |
| 3141 | |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3142 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3143 | { |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3144 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
| 3145 | u32 deemph_reg_value, margin_reg_value; |
| 3146 | bool uniq_trans_scale = false; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3147 | uint8_t train_set = intel_dp->train_set[0]; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3148 | |
| 3149 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3150 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3151 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3152 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3153 | deemph_reg_value = 128; |
| 3154 | margin_reg_value = 52; |
| 3155 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3156 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3157 | deemph_reg_value = 128; |
| 3158 | margin_reg_value = 77; |
| 3159 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3160 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3161 | deemph_reg_value = 128; |
| 3162 | margin_reg_value = 102; |
| 3163 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3164 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3165 | deemph_reg_value = 128; |
| 3166 | margin_reg_value = 154; |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3167 | uniq_trans_scale = true; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3168 | break; |
| 3169 | default: |
| 3170 | return 0; |
| 3171 | } |
| 3172 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3173 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3174 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3175 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3176 | deemph_reg_value = 85; |
| 3177 | margin_reg_value = 78; |
| 3178 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3179 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3180 | deemph_reg_value = 85; |
| 3181 | margin_reg_value = 116; |
| 3182 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3183 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3184 | deemph_reg_value = 85; |
| 3185 | margin_reg_value = 154; |
| 3186 | break; |
| 3187 | default: |
| 3188 | return 0; |
| 3189 | } |
| 3190 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3191 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3192 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3193 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3194 | deemph_reg_value = 64; |
| 3195 | margin_reg_value = 104; |
| 3196 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3197 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3198 | deemph_reg_value = 64; |
| 3199 | margin_reg_value = 154; |
| 3200 | break; |
| 3201 | default: |
| 3202 | return 0; |
| 3203 | } |
| 3204 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3205 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3206 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3207 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3208 | deemph_reg_value = 43; |
| 3209 | margin_reg_value = 154; |
| 3210 | break; |
| 3211 | default: |
| 3212 | return 0; |
| 3213 | } |
| 3214 | break; |
| 3215 | default: |
| 3216 | return 0; |
| 3217 | } |
| 3218 | |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3219 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
| 3220 | margin_reg_value, uniq_trans_scale); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3221 | |
| 3222 | return 0; |
| 3223 | } |
| 3224 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3225 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3226 | gen4_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3227 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3228 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3229 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3230 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3231 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3232 | default: |
| 3233 | signal_levels |= DP_VOLTAGE_0_4; |
| 3234 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3235 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3236 | signal_levels |= DP_VOLTAGE_0_6; |
| 3237 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3238 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3239 | signal_levels |= DP_VOLTAGE_0_8; |
| 3240 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3241 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3242 | signal_levels |= DP_VOLTAGE_1_2; |
| 3243 | break; |
| 3244 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3245 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3246 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3247 | default: |
| 3248 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 3249 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3250 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3251 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 3252 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3253 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3254 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 3255 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3256 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3257 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 3258 | break; |
| 3259 | } |
| 3260 | return signal_levels; |
| 3261 | } |
| 3262 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3263 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 3264 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3265 | gen6_edp_signal_levels(uint8_t train_set) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3266 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3267 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3268 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3269 | switch (signal_levels) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3270 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3271 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3272 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3273 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3274 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3275 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3276 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3277 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3278 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3279 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3280 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3281 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3282 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3283 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3284 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3285 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3286 | "0x%x\n", signal_levels); |
| 3287 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3288 | } |
| 3289 | } |
| 3290 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3291 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 3292 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3293 | gen7_edp_signal_levels(uint8_t train_set) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3294 | { |
| 3295 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3296 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3297 | switch (signal_levels) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3298 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3299 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3300 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3301 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3302 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3303 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 3304 | |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3305 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3306 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3307 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3308 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 3309 | |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3310 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3311 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3312 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3313 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 3314 | |
| 3315 | default: |
| 3316 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3317 | "0x%x\n", signal_levels); |
| 3318 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 3319 | } |
| 3320 | } |
| 3321 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3322 | void |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3323 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3324 | { |
| 3325 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3326 | enum port port = intel_dig_port->port; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3327 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Ander Conselvan de Oliveira | b905a91 | 2015-10-23 13:01:47 +0300 | [diff] [blame] | 3328 | struct drm_i915_private *dev_priv = to_i915(dev); |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 3329 | uint32_t signal_levels, mask = 0; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3330 | uint8_t train_set = intel_dp->train_set[0]; |
| 3331 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 3332 | if (HAS_DDI(dev)) { |
| 3333 | signal_levels = ddi_signal_levels(intel_dp); |
| 3334 | |
| 3335 | if (IS_BROXTON(dev)) |
| 3336 | signal_levels = 0; |
| 3337 | else |
| 3338 | mask = DDI_BUF_EMP_MASK; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3339 | } else if (IS_CHERRYVIEW(dev)) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3340 | signal_levels = chv_signal_levels(intel_dp); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3341 | } else if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3342 | signal_levels = vlv_signal_levels(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3343 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3344 | signal_levels = gen7_edp_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3345 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3346 | } else if (IS_GEN6(dev) && port == PORT_A) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3347 | signal_levels = gen6_edp_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3348 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 3349 | } else { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3350 | signal_levels = gen4_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3351 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 3352 | } |
| 3353 | |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 3354 | if (mask) |
| 3355 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 3356 | |
| 3357 | DRM_DEBUG_KMS("Using vswing level %d\n", |
| 3358 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
| 3359 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
| 3360 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 3361 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3362 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3363 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
Ander Conselvan de Oliveira | b905a91 | 2015-10-23 13:01:47 +0300 | [diff] [blame] | 3364 | |
| 3365 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 3366 | POSTING_READ(intel_dp->output_reg); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3367 | } |
| 3368 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3369 | void |
Ander Conselvan de Oliveira | e9c176d | 2015-10-23 13:01:45 +0300 | [diff] [blame] | 3370 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
| 3371 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3372 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 3373 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 3374 | struct drm_i915_private *dev_priv = |
| 3375 | to_i915(intel_dig_port->base.base.dev); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3376 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3377 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 3378 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3379 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3380 | POSTING_READ(intel_dp->output_reg); |
Ander Conselvan de Oliveira | e9c176d | 2015-10-23 13:01:45 +0300 | [diff] [blame] | 3381 | } |
| 3382 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3383 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3384 | { |
| 3385 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3386 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3387 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3388 | enum port port = intel_dig_port->port; |
| 3389 | uint32_t val; |
| 3390 | |
| 3391 | if (!HAS_DDI(dev)) |
| 3392 | return; |
| 3393 | |
| 3394 | val = I915_READ(DP_TP_CTL(port)); |
| 3395 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 3396 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 3397 | I915_WRITE(DP_TP_CTL(port), val); |
| 3398 | |
| 3399 | /* |
| 3400 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 3401 | * we need to set idle transmission mode is to work around a HW issue |
| 3402 | * where we enable the pipe while not in idle link-training mode. |
| 3403 | * In this case there is requirement to wait for a minimum number of |
| 3404 | * idle patterns to be sent. |
| 3405 | */ |
| 3406 | if (port == PORT_A) |
| 3407 | return; |
| 3408 | |
Chris Wilson | a767017 | 2016-06-30 15:33:10 +0100 | [diff] [blame] | 3409 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
| 3410 | DP_TP_STATUS_IDLE_DONE, |
| 3411 | DP_TP_STATUS_IDLE_DONE, |
| 3412 | 1)) |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3413 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 3414 | } |
| 3415 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3416 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3417 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3418 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3419 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3420 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3421 | enum port port = intel_dig_port->port; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3422 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3423 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3424 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3425 | |
Daniel Vetter | bc76e320 | 2014-05-20 22:46:50 +0200 | [diff] [blame] | 3426 | if (WARN_ON(HAS_DDI(dev))) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 3427 | return; |
| 3428 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 3429 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 3430 | return; |
| 3431 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3432 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3433 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 3434 | if ((IS_GEN7(dev) && port == PORT_A) || |
| 3435 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3436 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3437 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3438 | } else { |
Ville Syrjälä | aad3d14 | 2014-06-28 02:04:25 +0300 | [diff] [blame] | 3439 | if (IS_CHERRYVIEW(dev)) |
| 3440 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 3441 | else |
| 3442 | DP &= ~DP_LINK_TRAIN_MASK; |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3443 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3444 | } |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3445 | I915_WRITE(intel_dp->output_reg, DP); |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 3446 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3447 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3448 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 3449 | I915_WRITE(intel_dp->output_reg, DP); |
| 3450 | POSTING_READ(intel_dp->output_reg); |
| 3451 | |
| 3452 | /* |
| 3453 | * HW workaround for IBX, we need to move the port |
| 3454 | * to transcoder A after disabling it to allow the |
| 3455 | * matching HDMI port to be enabled on transcoder A. |
| 3456 | */ |
| 3457 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3458 | /* |
| 3459 | * We get CPU/PCH FIFO underruns on the other pipe when |
| 3460 | * doing the workaround. Sweep them under the rug. |
| 3461 | */ |
| 3462 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3463 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3464 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3465 | /* always enable with pattern 1 (as per spec) */ |
| 3466 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
| 3467 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
| 3468 | I915_WRITE(intel_dp->output_reg, DP); |
| 3469 | POSTING_READ(intel_dp->output_reg); |
| 3470 | |
| 3471 | DP &= ~DP_PORT_EN; |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3472 | I915_WRITE(intel_dp->output_reg, DP); |
Daniel Vetter | 0ca0968 | 2014-11-24 16:54:11 +0100 | [diff] [blame] | 3473 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3474 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 3475 | intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3476 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
| 3477 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3478 | } |
| 3479 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 3480 | msleep(intel_dp->panel_power_down_delay); |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 3481 | |
| 3482 | intel_dp->DP = DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3483 | } |
| 3484 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3485 | static bool |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 3486 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3487 | { |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3488 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
| 3489 | sizeof(intel_dp->dpcd)) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3490 | return false; /* aux transfer failed */ |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3491 | |
Andy Shevchenko | a8e9815 | 2014-09-01 14:12:01 +0300 | [diff] [blame] | 3492 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 3493 | |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 3494 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
| 3495 | } |
| 3496 | |
| 3497 | static bool |
| 3498 | intel_edp_init_dpcd(struct intel_dp *intel_dp) |
| 3499 | { |
| 3500 | struct drm_i915_private *dev_priv = |
| 3501 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
| 3502 | |
| 3503 | /* this function is meant to be called only once */ |
| 3504 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); |
| 3505 | |
| 3506 | if (!intel_dp_read_dpcd(intel_dp)) |
| 3507 | return false; |
| 3508 | |
| 3509 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 3510 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
| 3511 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 3512 | |
| 3513 | /* Check if the panel supports PSR */ |
| 3514 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, |
| 3515 | intel_dp->psr_dpcd, |
| 3516 | sizeof(intel_dp->psr_dpcd)); |
| 3517 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
| 3518 | dev_priv->psr.sink_support = true; |
| 3519 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
| 3520 | } |
| 3521 | |
| 3522 | if (INTEL_GEN(dev_priv) >= 9 && |
| 3523 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
| 3524 | uint8_t frame_sync_cap; |
| 3525 | |
| 3526 | dev_priv->psr.sink_support = true; |
| 3527 | drm_dp_dpcd_read(&intel_dp->aux, |
| 3528 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
| 3529 | &frame_sync_cap, 1); |
| 3530 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
| 3531 | /* PSR2 needs frame sync as well */ |
| 3532 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
| 3533 | DRM_DEBUG_KMS("PSR2 %s on sink", |
| 3534 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
| 3535 | } |
| 3536 | |
| 3537 | /* Read the eDP Display control capabilities registers */ |
| 3538 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
| 3539 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, |
| 3540 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) == |
| 3541 | sizeof(intel_dp->edp_dpcd))) |
| 3542 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
| 3543 | intel_dp->edp_dpcd); |
| 3544 | |
| 3545 | /* Intermediate frequency support */ |
| 3546 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
| 3547 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
| 3548 | int i; |
| 3549 | |
| 3550 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
| 3551 | sink_rates, sizeof(sink_rates)); |
| 3552 | |
| 3553 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
| 3554 | int val = le16_to_cpu(sink_rates[i]); |
| 3555 | |
| 3556 | if (val == 0) |
| 3557 | break; |
| 3558 | |
| 3559 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
| 3560 | intel_dp->sink_rates[i] = (val * 200) / 10; |
| 3561 | } |
| 3562 | intel_dp->num_sink_rates = i; |
| 3563 | } |
| 3564 | |
| 3565 | return true; |
| 3566 | } |
| 3567 | |
| 3568 | |
| 3569 | static bool |
| 3570 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
| 3571 | { |
| 3572 | if (!intel_dp_read_dpcd(intel_dp)) |
| 3573 | return false; |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3574 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3575 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, |
| 3576 | &intel_dp->sink_count, 1) < 0) |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 3577 | return false; |
| 3578 | |
| 3579 | /* |
| 3580 | * Sink count can change between short pulse hpd hence |
| 3581 | * a member variable in intel_dp will track any changes |
| 3582 | * between short pulse interrupts. |
| 3583 | */ |
| 3584 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); |
| 3585 | |
| 3586 | /* |
| 3587 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that |
| 3588 | * a dongle is present but no display. Unless we require to know |
| 3589 | * if a dongle is present or not, we don't need to update |
| 3590 | * downstream port information. So, an early return here saves |
| 3591 | * time from performing other operations which are not required. |
| 3592 | */ |
Shubhangi Shrivastava | 1034ce7 | 2016-04-12 12:23:54 +0530 | [diff] [blame] | 3593 | if (!is_edp(intel_dp) && !intel_dp->sink_count) |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 3594 | return false; |
| 3595 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3596 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3597 | DP_DWN_STRM_PORT_PRESENT)) |
| 3598 | return true; /* native DP sink */ |
| 3599 | |
| 3600 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 3601 | return true; /* no per-port downstream info */ |
| 3602 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3603 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
| 3604 | intel_dp->downstream_ports, |
| 3605 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3606 | return false; /* downstream port status fetch failed */ |
| 3607 | |
| 3608 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3609 | } |
| 3610 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3611 | static void |
| 3612 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 3613 | { |
| 3614 | u8 buf[3]; |
| 3615 | |
| 3616 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 3617 | return; |
| 3618 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3619 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3620 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 3621 | buf[0], buf[1], buf[2]); |
| 3622 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3623 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3624 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 3625 | buf[0], buf[1], buf[2]); |
| 3626 | } |
| 3627 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3628 | static bool |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 3629 | intel_dp_can_mst(struct intel_dp *intel_dp) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3630 | { |
| 3631 | u8 buf[1]; |
| 3632 | |
Nathan Schulte | 7cc9613 | 2016-03-15 10:14:05 -0500 | [diff] [blame] | 3633 | if (!i915.enable_dp_mst) |
| 3634 | return false; |
| 3635 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3636 | if (!intel_dp->can_mst) |
| 3637 | return false; |
| 3638 | |
| 3639 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
| 3640 | return false; |
| 3641 | |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 3642 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) |
| 3643 | return false; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3644 | |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 3645 | return buf[0] & DP_MST_CAP; |
| 3646 | } |
| 3647 | |
| 3648 | static void |
| 3649 | intel_dp_configure_mst(struct intel_dp *intel_dp) |
| 3650 | { |
| 3651 | if (!i915.enable_dp_mst) |
| 3652 | return; |
| 3653 | |
| 3654 | if (!intel_dp->can_mst) |
| 3655 | return; |
| 3656 | |
| 3657 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); |
| 3658 | |
| 3659 | if (intel_dp->is_mst) |
| 3660 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
| 3661 | else |
| 3662 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
| 3663 | |
| 3664 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 3665 | intel_dp->is_mst); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3666 | } |
| 3667 | |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3668 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3669 | { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3670 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3671 | struct drm_device *dev = dig_port->base.base.dev; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3672 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3673 | u8 buf; |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3674 | int ret = 0; |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3675 | int count = 0; |
| 3676 | int attempts = 10; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3677 | |
| 3678 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3679 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3680 | ret = -EIO; |
| 3681 | goto out; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3682 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3683 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3684 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3685 | buf & ~DP_TEST_SINK_START) < 0) { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3686 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3687 | ret = -EIO; |
| 3688 | goto out; |
| 3689 | } |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3690 | |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3691 | do { |
| 3692 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3693 | |
| 3694 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
| 3695 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 3696 | ret = -EIO; |
| 3697 | goto out; |
| 3698 | } |
| 3699 | count = buf & DP_TEST_COUNT_MASK; |
| 3700 | } while (--attempts && count); |
| 3701 | |
| 3702 | if (attempts == 0) { |
Rodrigo Vivi | dc5a903 | 2016-01-29 14:44:59 -0800 | [diff] [blame] | 3703 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3704 | ret = -ETIMEDOUT; |
| 3705 | } |
| 3706 | |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3707 | out: |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3708 | hsw_enable_ips(intel_crtc); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3709 | return ret; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3710 | } |
| 3711 | |
| 3712 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
| 3713 | { |
| 3714 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3715 | struct drm_device *dev = dig_port->base.base.dev; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3716 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3717 | u8 buf; |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3718 | int ret; |
| 3719 | |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3720 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
| 3721 | return -EIO; |
| 3722 | |
| 3723 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
| 3724 | return -ENOTTY; |
| 3725 | |
| 3726 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
| 3727 | return -EIO; |
| 3728 | |
Rodrigo Vivi | 6d8175d | 2015-11-05 10:50:22 -0800 | [diff] [blame] | 3729 | if (buf & DP_TEST_SINK_START) { |
| 3730 | ret = intel_dp_sink_crc_stop(intel_dp); |
| 3731 | if (ret) |
| 3732 | return ret; |
| 3733 | } |
| 3734 | |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3735 | hsw_disable_ips(intel_crtc); |
| 3736 | |
| 3737 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 3738 | buf | DP_TEST_SINK_START) < 0) { |
| 3739 | hsw_enable_ips(intel_crtc); |
| 3740 | return -EIO; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3741 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3742 | |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3743 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3744 | return 0; |
| 3745 | } |
| 3746 | |
| 3747 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
| 3748 | { |
| 3749 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3750 | struct drm_device *dev = dig_port->base.base.dev; |
| 3751 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3752 | u8 buf; |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3753 | int count, ret; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3754 | int attempts = 6; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3755 | |
| 3756 | ret = intel_dp_sink_crc_start(intel_dp); |
| 3757 | if (ret) |
| 3758 | return ret; |
| 3759 | |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3760 | do { |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3761 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3762 | |
Rodrigo Vivi | 1dda5f9 | 2014-10-01 07:32:37 -0700 | [diff] [blame] | 3763 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3764 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 3765 | ret = -EIO; |
Rodrigo Vivi | afe0d67 | 2015-07-23 16:35:45 -0700 | [diff] [blame] | 3766 | goto stop; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3767 | } |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3768 | count = buf & DP_TEST_COUNT_MASK; |
Rodrigo Vivi | aabc95d | 2015-07-23 16:35:50 -0700 | [diff] [blame] | 3769 | |
Rodrigo Vivi | 7e38eef | 2015-11-05 10:50:21 -0800 | [diff] [blame] | 3770 | } while (--attempts && count == 0); |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3771 | |
| 3772 | if (attempts == 0) { |
Rodrigo Vivi | 7e38eef | 2015-11-05 10:50:21 -0800 | [diff] [blame] | 3773 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
| 3774 | ret = -ETIMEDOUT; |
| 3775 | goto stop; |
| 3776 | } |
| 3777 | |
| 3778 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
| 3779 | ret = -EIO; |
| 3780 | goto stop; |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3781 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3782 | |
Rodrigo Vivi | afe0d67 | 2015-07-23 16:35:45 -0700 | [diff] [blame] | 3783 | stop: |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3784 | intel_dp_sink_crc_stop(intel_dp); |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3785 | return ret; |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3786 | } |
| 3787 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3788 | static bool |
| 3789 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3790 | { |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3791 | return drm_dp_dpcd_read(&intel_dp->aux, |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3792 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3793 | sink_irq_vector, 1) == 1; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3794 | } |
| 3795 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3796 | static bool |
| 3797 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3798 | { |
| 3799 | int ret; |
| 3800 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3801 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3802 | DP_SINK_COUNT_ESI, |
| 3803 | sink_irq_vector, 14); |
| 3804 | if (ret != 14) |
| 3805 | return false; |
| 3806 | |
| 3807 | return true; |
| 3808 | } |
| 3809 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3810 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3811 | { |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3812 | uint8_t test_result = DP_TEST_ACK; |
| 3813 | return test_result; |
| 3814 | } |
| 3815 | |
| 3816 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
| 3817 | { |
| 3818 | uint8_t test_result = DP_TEST_NAK; |
| 3819 | return test_result; |
| 3820 | } |
| 3821 | |
| 3822 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
| 3823 | { |
| 3824 | uint8_t test_result = DP_TEST_NAK; |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3825 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 3826 | struct drm_connector *connector = &intel_connector->base; |
| 3827 | |
| 3828 | if (intel_connector->detect_edid == NULL || |
Daniel Vetter | ac6f2e2 | 2015-05-08 16:15:41 +0200 | [diff] [blame] | 3829 | connector->edid_corrupt || |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3830 | intel_dp->aux.i2c_defer_count > 6) { |
| 3831 | /* Check EDID read for NACKs, DEFERs and corruption |
| 3832 | * (DP CTS 1.2 Core r1.1) |
| 3833 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
| 3834 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
| 3835 | * 4.2.2.6 : EDID corruption detected |
| 3836 | * Use failsafe mode for all cases |
| 3837 | */ |
| 3838 | if (intel_dp->aux.i2c_nack_count > 0 || |
| 3839 | intel_dp->aux.i2c_defer_count > 0) |
| 3840 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
| 3841 | intel_dp->aux.i2c_nack_count, |
| 3842 | intel_dp->aux.i2c_defer_count); |
| 3843 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
| 3844 | } else { |
Thulasimani,Sivakumar | f79b468e | 2015-08-07 15:14:30 +0530 | [diff] [blame] | 3845 | struct edid *block = intel_connector->detect_edid; |
| 3846 | |
| 3847 | /* We have to write the checksum |
| 3848 | * of the last block read |
| 3849 | */ |
| 3850 | block += intel_connector->detect_edid->extensions; |
| 3851 | |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3852 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
| 3853 | DP_TEST_EDID_CHECKSUM, |
Thulasimani,Sivakumar | f79b468e | 2015-08-07 15:14:30 +0530 | [diff] [blame] | 3854 | &block->checksum, |
Dan Carpenter | 5a1cc65 | 2015-05-12 21:07:37 +0300 | [diff] [blame] | 3855 | 1)) |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3856 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
| 3857 | |
| 3858 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
| 3859 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
| 3860 | } |
| 3861 | |
| 3862 | /* Set test active flag here so userspace doesn't interrupt things */ |
| 3863 | intel_dp->compliance_test_active = 1; |
| 3864 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3865 | return test_result; |
| 3866 | } |
| 3867 | |
| 3868 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
| 3869 | { |
| 3870 | uint8_t test_result = DP_TEST_NAK; |
| 3871 | return test_result; |
| 3872 | } |
| 3873 | |
| 3874 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 3875 | { |
| 3876 | uint8_t response = DP_TEST_NAK; |
| 3877 | uint8_t rxdata = 0; |
| 3878 | int status = 0; |
| 3879 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3880 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
| 3881 | if (status <= 0) { |
| 3882 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
| 3883 | goto update_status; |
| 3884 | } |
| 3885 | |
| 3886 | switch (rxdata) { |
| 3887 | case DP_TEST_LINK_TRAINING: |
| 3888 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
| 3889 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
| 3890 | response = intel_dp_autotest_link_training(intel_dp); |
| 3891 | break; |
| 3892 | case DP_TEST_LINK_VIDEO_PATTERN: |
| 3893 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
| 3894 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
| 3895 | response = intel_dp_autotest_video_pattern(intel_dp); |
| 3896 | break; |
| 3897 | case DP_TEST_LINK_EDID_READ: |
| 3898 | DRM_DEBUG_KMS("EDID test requested\n"); |
| 3899 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
| 3900 | response = intel_dp_autotest_edid(intel_dp); |
| 3901 | break; |
| 3902 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
| 3903 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
| 3904 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
| 3905 | response = intel_dp_autotest_phy_pattern(intel_dp); |
| 3906 | break; |
| 3907 | default: |
| 3908 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
| 3909 | break; |
| 3910 | } |
| 3911 | |
| 3912 | update_status: |
| 3913 | status = drm_dp_dpcd_write(&intel_dp->aux, |
| 3914 | DP_TEST_RESPONSE, |
| 3915 | &response, 1); |
| 3916 | if (status <= 0) |
| 3917 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3918 | } |
| 3919 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3920 | static int |
| 3921 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
| 3922 | { |
| 3923 | bool bret; |
| 3924 | |
| 3925 | if (intel_dp->is_mst) { |
| 3926 | u8 esi[16] = { 0 }; |
| 3927 | int ret = 0; |
| 3928 | int retry; |
| 3929 | bool handled; |
| 3930 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 3931 | go_again: |
| 3932 | if (bret == true) { |
| 3933 | |
| 3934 | /* check link status - esi[10] = 0x200c */ |
Ville Syrjälä | 19e0b4c | 2016-08-05 19:05:42 +0300 | [diff] [blame] | 3935 | if (intel_dp->active_mst_links && |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 3936 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3937 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
| 3938 | intel_dp_start_link_train(intel_dp); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3939 | intel_dp_stop_link_train(intel_dp); |
| 3940 | } |
| 3941 | |
Andy Shevchenko | 6f34cc3 | 2015-01-15 13:45:09 +0200 | [diff] [blame] | 3942 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3943 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
| 3944 | |
| 3945 | if (handled) { |
| 3946 | for (retry = 0; retry < 3; retry++) { |
| 3947 | int wret; |
| 3948 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
| 3949 | DP_SINK_COUNT_ESI+1, |
| 3950 | &esi[1], 3); |
| 3951 | if (wret == 3) { |
| 3952 | break; |
| 3953 | } |
| 3954 | } |
| 3955 | |
| 3956 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 3957 | if (bret == true) { |
Andy Shevchenko | 6f34cc3 | 2015-01-15 13:45:09 +0200 | [diff] [blame] | 3958 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3959 | goto go_again; |
| 3960 | } |
| 3961 | } else |
| 3962 | ret = 0; |
| 3963 | |
| 3964 | return ret; |
| 3965 | } else { |
| 3966 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3967 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
| 3968 | intel_dp->is_mst = false; |
| 3969 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 3970 | /* send a hotplug event */ |
| 3971 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
| 3972 | } |
| 3973 | } |
| 3974 | return -EINVAL; |
| 3975 | } |
| 3976 | |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 3977 | static void |
| 3978 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
| 3979 | { |
| 3980 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 3981 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3982 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 3983 | |
| 3984 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 3985 | |
| 3986 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 3987 | DRM_ERROR("Failed to get link status\n"); |
| 3988 | return; |
| 3989 | } |
| 3990 | |
| 3991 | if (!intel_encoder->base.crtc) |
| 3992 | return; |
| 3993 | |
| 3994 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
| 3995 | return; |
| 3996 | |
| 3997 | /* if link training is requested we should perform it always */ |
| 3998 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || |
| 3999 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { |
| 4000 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
| 4001 | intel_encoder->base.name); |
| 4002 | intel_dp_start_link_train(intel_dp); |
| 4003 | intel_dp_stop_link_train(intel_dp); |
| 4004 | } |
| 4005 | } |
| 4006 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4007 | /* |
| 4008 | * According to DP spec |
| 4009 | * 5.1.2: |
| 4010 | * 1. Read DPCD |
| 4011 | * 2. Configure link according to Receiver Capabilities |
| 4012 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 4013 | * 4. Check link status on receipt of hot-plug interrupt |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4014 | * |
| 4015 | * intel_dp_short_pulse - handles short pulse interrupts |
| 4016 | * when full detection is not required. |
| 4017 | * Returns %true if short pulse is handled and full detection |
| 4018 | * is NOT required and %false otherwise. |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4019 | */ |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4020 | static bool |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 4021 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4022 | { |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 4023 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Ville Syrjälä | 65fbb4e | 2016-07-28 17:50:47 +0300 | [diff] [blame] | 4024 | u8 sink_irq_vector = 0; |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4025 | u8 old_sink_count = intel_dp->sink_count; |
| 4026 | bool ret; |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 4027 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4028 | /* |
| 4029 | * Clearing compliance test variables to allow capturing |
| 4030 | * of values for next automated test request. |
| 4031 | */ |
| 4032 | intel_dp->compliance_test_active = 0; |
| 4033 | intel_dp->compliance_test_type = 0; |
| 4034 | intel_dp->compliance_test_data = 0; |
| 4035 | |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4036 | /* |
| 4037 | * Now read the DPCD to see if it's actually running |
| 4038 | * If the current value of sink count doesn't match with |
| 4039 | * the value that was stored earlier or dpcd read failed |
| 4040 | * we need to do full detection |
| 4041 | */ |
| 4042 | ret = intel_dp_get_dpcd(intel_dp); |
| 4043 | |
| 4044 | if ((old_sink_count != intel_dp->sink_count) || !ret) { |
| 4045 | /* No need to proceed if we are going to do full detect */ |
| 4046 | return false; |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 4047 | } |
| 4048 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4049 | /* Try to read the source of the interrupt */ |
| 4050 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
Ville Syrjälä | 65fbb4e | 2016-07-28 17:50:47 +0300 | [diff] [blame] | 4051 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
| 4052 | sink_irq_vector != 0) { |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4053 | /* Clear interrupt source */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4054 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4055 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4056 | sink_irq_vector); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4057 | |
| 4058 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4059 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4060 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4061 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4062 | } |
| 4063 | |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 4064 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 4065 | intel_dp_check_link_status(intel_dp); |
| 4066 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4067 | |
| 4068 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4069 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4070 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4071 | /* XXX this is probably wrong for multiple downstream ports */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4072 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4073 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 4074 | { |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4075 | uint8_t *dpcd = intel_dp->dpcd; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4076 | uint8_t type; |
| 4077 | |
| 4078 | if (!intel_dp_get_dpcd(intel_dp)) |
| 4079 | return connector_status_disconnected; |
| 4080 | |
Shubhangi Shrivastava | 1034ce7 | 2016-04-12 12:23:54 +0530 | [diff] [blame] | 4081 | if (is_edp(intel_dp)) |
| 4082 | return connector_status_connected; |
| 4083 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4084 | /* if there's no downstream port, we're done */ |
| 4085 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4086 | return connector_status_connected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4087 | |
| 4088 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 4089 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4090 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4091 | |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 4092 | return intel_dp->sink_count ? |
| 4093 | connector_status_connected : connector_status_disconnected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4094 | } |
| 4095 | |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 4096 | if (intel_dp_can_mst(intel_dp)) |
| 4097 | return connector_status_connected; |
| 4098 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4099 | /* If no HPD, poke DDC gently */ |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 4100 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4101 | return connector_status_connected; |
| 4102 | |
| 4103 | /* Well we tried, say unknown for unreliable port types */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 4104 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 4105 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 4106 | if (type == DP_DS_PORT_TYPE_VGA || |
| 4107 | type == DP_DS_PORT_TYPE_NON_EDID) |
| 4108 | return connector_status_unknown; |
| 4109 | } else { |
| 4110 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 4111 | DP_DWN_STRM_PORT_TYPE_MASK; |
| 4112 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
| 4113 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
| 4114 | return connector_status_unknown; |
| 4115 | } |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4116 | |
| 4117 | /* Anything else is out of spec, warn and ignore */ |
| 4118 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4119 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 4120 | } |
| 4121 | |
| 4122 | static enum drm_connector_status |
Chris Wilson | d410b56 | 2014-09-02 20:03:59 +0100 | [diff] [blame] | 4123 | edp_detect(struct intel_dp *intel_dp) |
| 4124 | { |
| 4125 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4126 | enum drm_connector_status status; |
| 4127 | |
| 4128 | status = intel_panel_detect(dev); |
| 4129 | if (status == connector_status_unknown) |
| 4130 | status = connector_status_connected; |
| 4131 | |
| 4132 | return status; |
| 4133 | } |
| 4134 | |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4135 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4136 | struct intel_digital_port *port) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4137 | { |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4138 | u32 bit; |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 4139 | |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4140 | switch (port->port) { |
| 4141 | case PORT_A: |
| 4142 | return true; |
| 4143 | case PORT_B: |
| 4144 | bit = SDE_PORTB_HOTPLUG; |
| 4145 | break; |
| 4146 | case PORT_C: |
| 4147 | bit = SDE_PORTC_HOTPLUG; |
| 4148 | break; |
| 4149 | case PORT_D: |
| 4150 | bit = SDE_PORTD_HOTPLUG; |
| 4151 | break; |
| 4152 | default: |
| 4153 | MISSING_CASE(port->port); |
| 4154 | return false; |
| 4155 | } |
| 4156 | |
| 4157 | return I915_READ(SDEISR) & bit; |
| 4158 | } |
| 4159 | |
| 4160 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4161 | struct intel_digital_port *port) |
| 4162 | { |
| 4163 | u32 bit; |
| 4164 | |
| 4165 | switch (port->port) { |
| 4166 | case PORT_A: |
| 4167 | return true; |
| 4168 | case PORT_B: |
| 4169 | bit = SDE_PORTB_HOTPLUG_CPT; |
| 4170 | break; |
| 4171 | case PORT_C: |
| 4172 | bit = SDE_PORTC_HOTPLUG_CPT; |
| 4173 | break; |
| 4174 | case PORT_D: |
| 4175 | bit = SDE_PORTD_HOTPLUG_CPT; |
| 4176 | break; |
Jani Nikula | a78695d | 2015-09-18 15:54:50 +0300 | [diff] [blame] | 4177 | case PORT_E: |
| 4178 | bit = SDE_PORTE_HOTPLUG_SPT; |
| 4179 | break; |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4180 | default: |
| 4181 | MISSING_CASE(port->port); |
| 4182 | return false; |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4183 | } |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 4184 | |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4185 | return I915_READ(SDEISR) & bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4186 | } |
| 4187 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4188 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
Jani Nikula | 1d24598 | 2015-08-20 10:47:37 +0300 | [diff] [blame] | 4189 | struct intel_digital_port *port) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4190 | { |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4191 | u32 bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4192 | |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4193 | switch (port->port) { |
| 4194 | case PORT_B: |
| 4195 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
| 4196 | break; |
| 4197 | case PORT_C: |
| 4198 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
| 4199 | break; |
| 4200 | case PORT_D: |
| 4201 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
| 4202 | break; |
| 4203 | default: |
| 4204 | MISSING_CASE(port->port); |
| 4205 | return false; |
| 4206 | } |
| 4207 | |
| 4208 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
| 4209 | } |
| 4210 | |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4211 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4212 | struct intel_digital_port *port) |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4213 | { |
| 4214 | u32 bit; |
| 4215 | |
| 4216 | switch (port->port) { |
| 4217 | case PORT_B: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4218 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4219 | break; |
| 4220 | case PORT_C: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4221 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4222 | break; |
| 4223 | case PORT_D: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4224 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4225 | break; |
| 4226 | default: |
| 4227 | MISSING_CASE(port->port); |
| 4228 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4229 | } |
| 4230 | |
Jani Nikula | 1d24598 | 2015-08-20 10:47:37 +0300 | [diff] [blame] | 4231 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
Dave Airlie | 2a592be | 2014-09-01 16:58:12 +1000 | [diff] [blame] | 4232 | } |
| 4233 | |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4234 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4235 | struct intel_digital_port *intel_dig_port) |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4236 | { |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4237 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4238 | enum port port; |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4239 | u32 bit; |
| 4240 | |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4241 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
| 4242 | switch (port) { |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4243 | case PORT_A: |
| 4244 | bit = BXT_DE_PORT_HP_DDIA; |
| 4245 | break; |
| 4246 | case PORT_B: |
| 4247 | bit = BXT_DE_PORT_HP_DDIB; |
| 4248 | break; |
| 4249 | case PORT_C: |
| 4250 | bit = BXT_DE_PORT_HP_DDIC; |
| 4251 | break; |
| 4252 | default: |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4253 | MISSING_CASE(port); |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4254 | return false; |
| 4255 | } |
| 4256 | |
| 4257 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
| 4258 | } |
| 4259 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4260 | /* |
| 4261 | * intel_digital_port_connected - is the specified port connected? |
| 4262 | * @dev_priv: i915 private structure |
| 4263 | * @port: the port to test |
| 4264 | * |
| 4265 | * Return %true if @port is connected, %false otherwise. |
| 4266 | */ |
David Weinehall | 23f889b | 2016-08-17 15:47:48 +0300 | [diff] [blame] | 4267 | static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4268 | struct intel_digital_port *port) |
| 4269 | { |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4270 | if (HAS_PCH_IBX(dev_priv)) |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4271 | return ibx_digital_port_connected(dev_priv, port); |
Ville Syrjälä | 22824fa | 2016-02-11 16:44:28 +0200 | [diff] [blame] | 4272 | else if (HAS_PCH_SPLIT(dev_priv)) |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4273 | return cpt_digital_port_connected(dev_priv, port); |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4274 | else if (IS_BROXTON(dev_priv)) |
| 4275 | return bxt_digital_port_connected(dev_priv, port); |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4276 | else if (IS_GM45(dev_priv)) |
| 4277 | return gm45_digital_port_connected(dev_priv, port); |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4278 | else |
| 4279 | return g4x_digital_port_connected(dev_priv, port); |
| 4280 | } |
| 4281 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4282 | static struct edid * |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4283 | intel_dp_get_edid(struct intel_dp *intel_dp) |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4284 | { |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4285 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4286 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4287 | /* use cached edid if we have one */ |
| 4288 | if (intel_connector->edid) { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4289 | /* invalid edid */ |
| 4290 | if (IS_ERR(intel_connector->edid)) |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 4291 | return NULL; |
| 4292 | |
Jani Nikula | 55e9ede | 2013-10-01 10:38:54 +0300 | [diff] [blame] | 4293 | return drm_edid_duplicate(intel_connector->edid); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4294 | } else |
| 4295 | return drm_get_edid(&intel_connector->base, |
| 4296 | &intel_dp->aux.ddc); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4297 | } |
| 4298 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4299 | static void |
| 4300 | intel_dp_set_edid(struct intel_dp *intel_dp) |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4301 | { |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4302 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4303 | struct edid *edid; |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4304 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4305 | intel_dp_unset_edid(intel_dp); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4306 | edid = intel_dp_get_edid(intel_dp); |
| 4307 | intel_connector->detect_edid = edid; |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4308 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4309 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
| 4310 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
| 4311 | else |
| 4312 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
| 4313 | } |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 4314 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4315 | static void |
| 4316 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
| 4317 | { |
| 4318 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4319 | |
| 4320 | kfree(intel_connector->detect_edid); |
| 4321 | intel_connector->detect_edid = NULL; |
| 4322 | |
| 4323 | intel_dp->has_audio = false; |
| 4324 | } |
| 4325 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4326 | static void |
| 4327 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4328 | { |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4329 | struct drm_connector *connector = &intel_connector->base; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4330 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 4331 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4332 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 4333 | struct drm_device *dev = connector->dev; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4334 | enum drm_connector_status status; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 4335 | enum intel_display_power_domain power_domain; |
Ville Syrjälä | 65fbb4e | 2016-07-28 17:50:47 +0300 | [diff] [blame] | 4336 | u8 sink_irq_vector = 0; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4337 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4338 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4339 | intel_display_power_get(to_i915(dev), power_domain); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4340 | |
Chris Wilson | d410b56 | 2014-09-02 20:03:59 +0100 | [diff] [blame] | 4341 | /* Can't disconnect eDP, but you can close the lid... */ |
| 4342 | if (is_edp(intel_dp)) |
| 4343 | status = edp_detect(intel_dp); |
Ander Conselvan de Oliveira | c555a81 | 2015-11-18 17:19:30 +0200 | [diff] [blame] | 4344 | else if (intel_digital_port_connected(to_i915(dev), |
| 4345 | dp_to_dig_port(intel_dp))) |
| 4346 | status = intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4347 | else |
Ander Conselvan de Oliveira | c555a81 | 2015-11-18 17:19:30 +0200 | [diff] [blame] | 4348 | status = connector_status_disconnected; |
| 4349 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4350 | if (status != connector_status_connected) { |
| 4351 | intel_dp->compliance_test_active = 0; |
| 4352 | intel_dp->compliance_test_type = 0; |
| 4353 | intel_dp->compliance_test_data = 0; |
| 4354 | |
jim.bride@linux.intel.com | 0e505a0 | 2016-04-11 10:11:24 -0700 | [diff] [blame] | 4355 | if (intel_dp->is_mst) { |
| 4356 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", |
| 4357 | intel_dp->is_mst, |
| 4358 | intel_dp->mst_mgr.mst_state); |
| 4359 | intel_dp->is_mst = false; |
| 4360 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 4361 | intel_dp->is_mst); |
| 4362 | } |
| 4363 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4364 | goto out; |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4365 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4366 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4367 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4368 | intel_encoder->type = INTEL_OUTPUT_DP; |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4369 | |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 4370 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
| 4371 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
| 4372 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
| 4373 | |
| 4374 | intel_dp_print_rates(intel_dp); |
| 4375 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 4376 | intel_dp_probe_oui(intel_dp); |
| 4377 | |
Mika Kahola | 0e390a3 | 2016-09-09 14:10:53 +0300 | [diff] [blame] | 4378 | intel_dp_print_hw_revision(intel_dp); |
Mika Kahola | 1a2724f | 2016-09-09 14:10:54 +0300 | [diff] [blame] | 4379 | intel_dp_print_sw_revision(intel_dp); |
Mika Kahola | 0e390a3 | 2016-09-09 14:10:53 +0300 | [diff] [blame] | 4380 | |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 4381 | intel_dp_configure_mst(intel_dp); |
| 4382 | |
| 4383 | if (intel_dp->is_mst) { |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4384 | /* |
| 4385 | * If we are in MST mode then this connector |
| 4386 | * won't appear connected or have anything |
| 4387 | * with EDID on it |
| 4388 | */ |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4389 | status = connector_status_disconnected; |
| 4390 | goto out; |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4391 | } else if (connector->status == connector_status_connected) { |
| 4392 | /* |
| 4393 | * If display was connected already and is still connected |
| 4394 | * check links status, there has been known issues of |
| 4395 | * link loss triggerring long pulse!!!! |
| 4396 | */ |
| 4397 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 4398 | intel_dp_check_link_status(intel_dp); |
| 4399 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 4400 | goto out; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4401 | } |
| 4402 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4403 | /* |
| 4404 | * Clearing NACK and defer counts to get their exact values |
| 4405 | * while reading EDID which are required by Compliance tests |
| 4406 | * 4.2.2.4 and 4.2.2.5 |
| 4407 | */ |
| 4408 | intel_dp->aux.i2c_nack_count = 0; |
| 4409 | intel_dp->aux.i2c_defer_count = 0; |
| 4410 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4411 | intel_dp_set_edid(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4412 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4413 | status = connector_status_connected; |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4414 | intel_dp->detect_done = true; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4415 | |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4416 | /* Try to read the source of the interrupt */ |
| 4417 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
Ville Syrjälä | 65fbb4e | 2016-07-28 17:50:47 +0300 | [diff] [blame] | 4418 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
| 4419 | sink_irq_vector != 0) { |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4420 | /* Clear interrupt source */ |
| 4421 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4422 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4423 | sink_irq_vector); |
| 4424 | |
| 4425 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 4426 | intel_dp_handle_test_request(intel_dp); |
| 4427 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4428 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4429 | } |
| 4430 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4431 | out: |
jim.bride@linux.intel.com | 0e505a0 | 2016-04-11 10:11:24 -0700 | [diff] [blame] | 4432 | if ((status != connector_status_connected) && |
| 4433 | (intel_dp->is_mst == false)) |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4434 | intel_dp_unset_edid(intel_dp); |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4435 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4436 | intel_display_power_put(to_i915(dev), power_domain); |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4437 | return; |
| 4438 | } |
| 4439 | |
| 4440 | static enum drm_connector_status |
| 4441 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 4442 | { |
| 4443 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4444 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4445 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4446 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4447 | |
| 4448 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4449 | connector->base.id, connector->name); |
| 4450 | |
| 4451 | if (intel_dp->is_mst) { |
| 4452 | /* MST devices are disconnected from a monitor POV */ |
| 4453 | intel_dp_unset_edid(intel_dp); |
| 4454 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4455 | intel_encoder->type = INTEL_OUTPUT_DP; |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4456 | return connector_status_disconnected; |
| 4457 | } |
| 4458 | |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4459 | /* If full detect is not performed yet, do a full detect */ |
| 4460 | if (!intel_dp->detect_done) |
| 4461 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4462 | |
| 4463 | intel_dp->detect_done = false; |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4464 | |
Ville Syrjälä | 1b7f2c8 | 2016-07-18 13:15:14 +0300 | [diff] [blame] | 4465 | if (is_edp(intel_dp) || intel_connector->detect_edid) |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4466 | return connector_status_connected; |
| 4467 | else |
| 4468 | return connector_status_disconnected; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4469 | } |
| 4470 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4471 | static void |
| 4472 | intel_dp_force(struct drm_connector *connector) |
| 4473 | { |
| 4474 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4475 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4476 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4477 | enum intel_display_power_domain power_domain; |
| 4478 | |
| 4479 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4480 | connector->base.id, connector->name); |
| 4481 | intel_dp_unset_edid(intel_dp); |
| 4482 | |
| 4483 | if (connector->status != connector_status_connected) |
| 4484 | return; |
| 4485 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4486 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4487 | intel_display_power_get(dev_priv, power_domain); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4488 | |
| 4489 | intel_dp_set_edid(intel_dp); |
| 4490 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4491 | intel_display_power_put(dev_priv, power_domain); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4492 | |
| 4493 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4494 | intel_encoder->type = INTEL_OUTPUT_DP; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4495 | } |
| 4496 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4497 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 4498 | { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4499 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4500 | struct edid *edid; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4501 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4502 | edid = intel_connector->detect_edid; |
| 4503 | if (edid) { |
| 4504 | int ret = intel_connector_update_modes(connector, edid); |
| 4505 | if (ret) |
| 4506 | return ret; |
| 4507 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4508 | |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4509 | /* if eDP has no EDID, fall back to fixed mode */ |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4510 | if (is_edp(intel_attached_dp(connector)) && |
| 4511 | intel_connector->panel.fixed_mode) { |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4512 | struct drm_display_mode *mode; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4513 | |
| 4514 | mode = drm_mode_duplicate(connector->dev, |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4515 | intel_connector->panel.fixed_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4516 | if (mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4517 | drm_mode_probed_add(connector, mode); |
| 4518 | return 1; |
| 4519 | } |
| 4520 | } |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4521 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4522 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4523 | } |
| 4524 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4525 | static bool |
| 4526 | intel_dp_detect_audio(struct drm_connector *connector) |
| 4527 | { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4528 | bool has_audio = false; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4529 | struct edid *edid; |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4530 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4531 | edid = to_intel_connector(connector)->detect_edid; |
| 4532 | if (edid) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4533 | has_audio = drm_detect_monitor_audio(edid); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 4534 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4535 | return has_audio; |
| 4536 | } |
| 4537 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4538 | static int |
| 4539 | intel_dp_set_property(struct drm_connector *connector, |
| 4540 | struct drm_property *property, |
| 4541 | uint64_t val) |
| 4542 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4543 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4544 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4545 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 4546 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4547 | int ret; |
| 4548 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 4549 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4550 | if (ret) |
| 4551 | return ret; |
| 4552 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 4553 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4554 | int i = val; |
| 4555 | bool has_audio; |
| 4556 | |
| 4557 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4558 | return 0; |
| 4559 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4560 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4561 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 4562 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4563 | has_audio = intel_dp_detect_audio(connector); |
| 4564 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 4565 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4566 | |
| 4567 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4568 | return 0; |
| 4569 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4570 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4571 | goto done; |
| 4572 | } |
| 4573 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4574 | if (property == dev_priv->broadcast_rgb_property) { |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4575 | bool old_auto = intel_dp->color_range_auto; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4576 | bool old_range = intel_dp->limited_color_range; |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4577 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4578 | switch (val) { |
| 4579 | case INTEL_BROADCAST_RGB_AUTO: |
| 4580 | intel_dp->color_range_auto = true; |
| 4581 | break; |
| 4582 | case INTEL_BROADCAST_RGB_FULL: |
| 4583 | intel_dp->color_range_auto = false; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4584 | intel_dp->limited_color_range = false; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4585 | break; |
| 4586 | case INTEL_BROADCAST_RGB_LIMITED: |
| 4587 | intel_dp->color_range_auto = false; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4588 | intel_dp->limited_color_range = true; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4589 | break; |
| 4590 | default: |
| 4591 | return -EINVAL; |
| 4592 | } |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4593 | |
| 4594 | if (old_auto == intel_dp->color_range_auto && |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4595 | old_range == intel_dp->limited_color_range) |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4596 | return 0; |
| 4597 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4598 | goto done; |
| 4599 | } |
| 4600 | |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4601 | if (is_edp(intel_dp) && |
| 4602 | property == connector->dev->mode_config.scaling_mode_property) { |
| 4603 | if (val == DRM_MODE_SCALE_NONE) { |
| 4604 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 4605 | return -EINVAL; |
| 4606 | } |
Ville Syrjälä | 234126c | 2016-04-12 22:14:38 +0300 | [diff] [blame] | 4607 | if (HAS_GMCH_DISPLAY(dev_priv) && |
| 4608 | val == DRM_MODE_SCALE_CENTER) { |
| 4609 | DRM_DEBUG_KMS("centering not supported\n"); |
| 4610 | return -EINVAL; |
| 4611 | } |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4612 | |
| 4613 | if (intel_connector->panel.fitting_mode == val) { |
| 4614 | /* the eDP scaling property is not changed */ |
| 4615 | return 0; |
| 4616 | } |
| 4617 | intel_connector->panel.fitting_mode = val; |
| 4618 | |
| 4619 | goto done; |
| 4620 | } |
| 4621 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4622 | return -EINVAL; |
| 4623 | |
| 4624 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 4625 | if (intel_encoder->base.crtc) |
| 4626 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4627 | |
| 4628 | return 0; |
| 4629 | } |
| 4630 | |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 4631 | static int |
| 4632 | intel_dp_connector_register(struct drm_connector *connector) |
| 4633 | { |
| 4634 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Chris Wilson | 1ebaa0b | 2016-06-24 14:00:15 +0100 | [diff] [blame] | 4635 | int ret; |
| 4636 | |
| 4637 | ret = intel_connector_register(connector); |
| 4638 | if (ret) |
| 4639 | return ret; |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 4640 | |
| 4641 | i915_debugfs_connector_add(connector); |
| 4642 | |
| 4643 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
| 4644 | intel_dp->aux.name, connector->kdev->kobj.name); |
| 4645 | |
| 4646 | intel_dp->aux.dev = connector->kdev; |
| 4647 | return drm_dp_aux_register(&intel_dp->aux); |
| 4648 | } |
| 4649 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4650 | static void |
Chris Wilson | c191eca | 2016-06-17 11:40:33 +0100 | [diff] [blame] | 4651 | intel_dp_connector_unregister(struct drm_connector *connector) |
| 4652 | { |
| 4653 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); |
| 4654 | intel_connector_unregister(connector); |
| 4655 | } |
| 4656 | |
| 4657 | static void |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 4658 | intel_dp_connector_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4659 | { |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 4660 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 4661 | |
Chris Wilson | 10e972d | 2014-09-04 21:43:45 +0100 | [diff] [blame] | 4662 | kfree(intel_connector->detect_edid); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4663 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4664 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 4665 | kfree(intel_connector->edid); |
| 4666 | |
Paulo Zanoni | acd8db10 | 2013-06-12 17:27:23 -0300 | [diff] [blame] | 4667 | /* Can't call is_edp() since the encoder may have been destroyed |
| 4668 | * already. */ |
| 4669 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 4670 | intel_panel_fini(&intel_connector->panel); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 4671 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4672 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 4673 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4674 | } |
| 4675 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 4676 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4677 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4678 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 4679 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4680 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4681 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 4682 | if (is_edp(intel_dp)) { |
| 4683 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 4684 | /* |
| 4685 | * vdd might still be enabled do to the delayed vdd off. |
| 4686 | * Make sure vdd is actually turned off here. |
| 4687 | */ |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4688 | pps_lock(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 4689 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4690 | pps_unlock(intel_dp); |
| 4691 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 4692 | if (intel_dp->edp_notifier.notifier_call) { |
| 4693 | unregister_reboot_notifier(&intel_dp->edp_notifier); |
| 4694 | intel_dp->edp_notifier.notifier_call = NULL; |
| 4695 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 4696 | } |
Chris Wilson | 9968188 | 2016-06-20 09:29:17 +0100 | [diff] [blame] | 4697 | |
| 4698 | intel_dp_aux_fini(intel_dp); |
| 4699 | |
Imre Deak | c8bd0e4 | 2014-12-12 17:57:38 +0200 | [diff] [blame] | 4700 | drm_encoder_cleanup(encoder); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4701 | kfree(intel_dig_port); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4702 | } |
| 4703 | |
Imre Deak | bf93ba6 | 2016-04-18 10:04:21 +0300 | [diff] [blame] | 4704 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4705 | { |
| 4706 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4707 | |
| 4708 | if (!is_edp(intel_dp)) |
| 4709 | return; |
| 4710 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 4711 | /* |
| 4712 | * vdd might still be enabled do to the delayed vdd off. |
| 4713 | * Make sure vdd is actually turned off here. |
| 4714 | */ |
Ville Syrjälä | afa4e53 | 2014-11-25 15:43:48 +0200 | [diff] [blame] | 4715 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4716 | pps_lock(intel_dp); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4717 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4718 | pps_unlock(intel_dp); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4719 | } |
| 4720 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4721 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
| 4722 | { |
| 4723 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4724 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4725 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4726 | enum intel_display_power_domain power_domain; |
| 4727 | |
| 4728 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4729 | |
| 4730 | if (!edp_have_panel_vdd(intel_dp)) |
| 4731 | return; |
| 4732 | |
| 4733 | /* |
| 4734 | * The VDD bit needs a power domain reference, so if the bit is |
| 4735 | * already enabled when we boot or resume, grab this reference and |
| 4736 | * schedule a vdd off, so we don't hold on to the reference |
| 4737 | * indefinitely. |
| 4738 | */ |
| 4739 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4740 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4741 | intel_display_power_get(dev_priv, power_domain); |
| 4742 | |
| 4743 | edp_panel_vdd_schedule_off(intel_dp); |
| 4744 | } |
| 4745 | |
Imre Deak | bf93ba6 | 2016-04-18 10:04:21 +0300 | [diff] [blame] | 4746 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4747 | { |
Ville Syrjälä | 64989ca4 | 2016-05-13 20:53:56 +0300 | [diff] [blame] | 4748 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
| 4749 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 4750 | |
| 4751 | if (!HAS_DDI(dev_priv)) |
| 4752 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4753 | |
| 4754 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
| 4755 | return; |
| 4756 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4757 | pps_lock(intel_dp); |
| 4758 | |
Imre Deak | 335f752 | 2016-08-10 14:07:32 +0300 | [diff] [blame] | 4759 | /* Reinit the power sequencer, in case BIOS did something with it. */ |
| 4760 | intel_dp_pps_init(encoder->dev, intel_dp); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4761 | intel_edp_panel_vdd_sanitize(intel_dp); |
| 4762 | |
| 4763 | pps_unlock(intel_dp); |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4764 | } |
| 4765 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4766 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 4767 | .dpms = drm_atomic_helper_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4768 | .detect = intel_dp_detect, |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4769 | .force = intel_dp_force, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4770 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4771 | .set_property = intel_dp_set_property, |
Matt Roper | 2545e4a | 2015-01-22 16:51:27 -0800 | [diff] [blame] | 4772 | .atomic_get_property = intel_connector_atomic_get_property, |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 4773 | .late_register = intel_dp_connector_register, |
Chris Wilson | c191eca | 2016-06-17 11:40:33 +0100 | [diff] [blame] | 4774 | .early_unregister = intel_dp_connector_unregister, |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 4775 | .destroy = intel_dp_connector_destroy, |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 4776 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Ander Conselvan de Oliveira | 9896972 | 2015-03-20 16:18:06 +0200 | [diff] [blame] | 4777 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4778 | }; |
| 4779 | |
| 4780 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 4781 | .get_modes = intel_dp_get_modes, |
| 4782 | .mode_valid = intel_dp_mode_valid, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4783 | }; |
| 4784 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4785 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4786 | .reset = intel_dp_encoder_reset, |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4787 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4788 | }; |
| 4789 | |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4790 | enum irqreturn |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4791 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
| 4792 | { |
| 4793 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4794 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4795 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4796 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4797 | enum intel_display_power_domain power_domain; |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4798 | enum irqreturn ret = IRQ_NONE; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4799 | |
Takashi Iwai | 2540058 | 2015-11-19 12:09:56 +0100 | [diff] [blame] | 4800 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
| 4801 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4802 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4803 | |
Ville Syrjälä | 7a7f84c | 2014-10-16 20:46:10 +0300 | [diff] [blame] | 4804 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
| 4805 | /* |
| 4806 | * vdd off can generate a long pulse on eDP which |
| 4807 | * would require vdd on to handle it, and thus we |
| 4808 | * would end up in an endless cycle of |
| 4809 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
| 4810 | */ |
| 4811 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
| 4812 | port_name(intel_dig_port->port)); |
Ville Syrjälä | a8b3d52 | 2015-02-10 14:11:46 +0200 | [diff] [blame] | 4813 | return IRQ_HANDLED; |
Ville Syrjälä | 7a7f84c | 2014-10-16 20:46:10 +0300 | [diff] [blame] | 4814 | } |
| 4815 | |
Ville Syrjälä | 26fbb77 | 2014-08-11 18:37:37 +0300 | [diff] [blame] | 4816 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
| 4817 | port_name(intel_dig_port->port), |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4818 | long_hpd ? "long" : "short"); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4819 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4820 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4821 | intel_display_power_get(dev_priv, power_domain); |
| 4822 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4823 | if (long_hpd) { |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4824 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4825 | if (intel_dp->is_mst) |
| 4826 | ret = IRQ_HANDLED; |
| 4827 | goto put_power; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4828 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4829 | } else { |
| 4830 | if (intel_dp->is_mst) { |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4831 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { |
| 4832 | /* |
| 4833 | * If we were in MST mode, and device is not |
| 4834 | * there, get out of MST mode |
| 4835 | */ |
| 4836 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", |
| 4837 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
| 4838 | intel_dp->is_mst = false; |
| 4839 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 4840 | intel_dp->is_mst); |
| 4841 | goto put_power; |
| 4842 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4843 | } |
| 4844 | |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4845 | if (!intel_dp->is_mst) { |
| 4846 | if (!intel_dp_short_pulse(intel_dp)) { |
| 4847 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4848 | goto put_power; |
| 4849 | } |
| 4850 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4851 | } |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4852 | |
| 4853 | ret = IRQ_HANDLED; |
| 4854 | |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4855 | put_power: |
| 4856 | intel_display_power_put(dev_priv, power_domain); |
| 4857 | |
| 4858 | return ret; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4859 | } |
| 4860 | |
Rodrigo Vivi | 477ec32 | 2015-08-06 15:51:39 +0800 | [diff] [blame] | 4861 | /* check the VBT to see whether the eDP is on another port */ |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 4862 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4863 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4864 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4865 | |
Ville Syrjälä | 53ce81a | 2015-09-11 21:04:38 +0300 | [diff] [blame] | 4866 | /* |
| 4867 | * eDP not supported on g4x. so bail out early just |
| 4868 | * for a bit extra safety in case the VBT is bonkers. |
| 4869 | */ |
| 4870 | if (INTEL_INFO(dev)->gen < 5) |
| 4871 | return false; |
| 4872 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 4873 | if (port == PORT_A) |
| 4874 | return true; |
| 4875 | |
Jani Nikula | 951d9ef | 2016-03-16 12:43:31 +0200 | [diff] [blame] | 4876 | return intel_bios_is_port_edp(dev_priv, port); |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4877 | } |
| 4878 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4879 | void |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4880 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 4881 | { |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4882 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4883 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 4884 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4885 | intel_attach_broadcast_rgb_property(connector); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4886 | intel_dp->color_range_auto = true; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4887 | |
| 4888 | if (is_edp(intel_dp)) { |
| 4889 | drm_mode_create_scaling_mode_property(connector->dev); |
Rob Clark | 6de6d84 | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 4890 | drm_object_attach_property( |
| 4891 | &connector->base, |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4892 | connector->dev->mode_config.scaling_mode_property, |
Yuly Novikov | 8e740cd | 2012-10-26 12:04:01 +0300 | [diff] [blame] | 4893 | DRM_MODE_SCALE_ASPECT); |
| 4894 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4895 | } |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4896 | } |
| 4897 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 4898 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
| 4899 | { |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 4900 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 4901 | intel_dp->last_power_on = jiffies; |
| 4902 | intel_dp->last_backlight_off = jiffies; |
| 4903 | } |
| 4904 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4905 | static void |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4906 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
| 4907 | struct intel_dp *intel_dp, struct edp_power_seq *seq) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4908 | { |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4909 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4910 | struct pps_registers regs; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4911 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4912 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4913 | |
| 4914 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 4915 | * the very first thing. */ |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4916 | pp_ctl = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4917 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4918 | pp_on = I915_READ(regs.pp_on); |
| 4919 | pp_off = I915_READ(regs.pp_off); |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4920 | if (!IS_BROXTON(dev_priv)) { |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4921 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
| 4922 | pp_div = I915_READ(regs.pp_div); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4923 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4924 | |
| 4925 | /* Pull timing values out of registers */ |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4926 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 4927 | PANEL_POWER_UP_DELAY_SHIFT; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4928 | |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4929 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 4930 | PANEL_LIGHT_ON_DELAY_SHIFT; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4931 | |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4932 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 4933 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4934 | |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4935 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 4936 | PANEL_POWER_DOWN_DELAY_SHIFT; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4937 | |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4938 | if (IS_BROXTON(dev_priv)) { |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4939 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
| 4940 | BXT_POWER_CYCLE_DELAY_SHIFT; |
| 4941 | if (tmp > 0) |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4942 | seq->t11_t12 = (tmp - 1) * 1000; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4943 | else |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4944 | seq->t11_t12 = 0; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4945 | } else { |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4946 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4947 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4948 | } |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4949 | } |
| 4950 | |
| 4951 | static void |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 4952 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) |
| 4953 | { |
| 4954 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 4955 | state_name, |
| 4956 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); |
| 4957 | } |
| 4958 | |
| 4959 | static void |
| 4960 | intel_pps_verify_state(struct drm_i915_private *dev_priv, |
| 4961 | struct intel_dp *intel_dp) |
| 4962 | { |
| 4963 | struct edp_power_seq hw; |
| 4964 | struct edp_power_seq *sw = &intel_dp->pps_delays; |
| 4965 | |
| 4966 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); |
| 4967 | |
| 4968 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || |
| 4969 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { |
| 4970 | DRM_ERROR("PPS state mismatch\n"); |
| 4971 | intel_pps_dump_state("sw", sw); |
| 4972 | intel_pps_dump_state("hw", &hw); |
| 4973 | } |
| 4974 | } |
| 4975 | |
| 4976 | static void |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4977 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
| 4978 | struct intel_dp *intel_dp) |
| 4979 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4980 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4981 | struct edp_power_seq cur, vbt, spec, |
| 4982 | *final = &intel_dp->pps_delays; |
| 4983 | |
| 4984 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4985 | |
| 4986 | /* already initialized? */ |
| 4987 | if (final->t11_t12 != 0) |
| 4988 | return; |
| 4989 | |
| 4990 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4991 | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 4992 | intel_pps_dump_state("cur", &cur); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4993 | |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 4994 | vbt = dev_priv->vbt.edp.pps; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4995 | |
| 4996 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 4997 | * our hw here, which are all in 100usec. */ |
| 4998 | spec.t1_t3 = 210 * 10; |
| 4999 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 5000 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 5001 | spec.t10 = 500 * 10; |
| 5002 | /* This one is special and actually in units of 100ms, but zero |
| 5003 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 5004 | * table multiplies it with 1000 to make it in units of 100usec, |
| 5005 | * too. */ |
| 5006 | spec.t11_t12 = (510 + 100) * 10; |
| 5007 | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 5008 | intel_pps_dump_state("vbt", &vbt); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5009 | |
| 5010 | /* Use the max of the register settings and vbt. If both are |
| 5011 | * unset, fall back to the spec limits. */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5012 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5013 | spec.field : \ |
| 5014 | max(cur.field, vbt.field)) |
| 5015 | assign_final(t1_t3); |
| 5016 | assign_final(t8); |
| 5017 | assign_final(t9); |
| 5018 | assign_final(t10); |
| 5019 | assign_final(t11_t12); |
| 5020 | #undef assign_final |
| 5021 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5022 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5023 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 5024 | intel_dp->backlight_on_delay = get_delay(t8); |
| 5025 | intel_dp->backlight_off_delay = get_delay(t9); |
| 5026 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 5027 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 5028 | #undef get_delay |
| 5029 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5030 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 5031 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 5032 | intel_dp->panel_power_cycle_delay); |
| 5033 | |
| 5034 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 5035 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 5036 | |
| 5037 | /* |
| 5038 | * We override the HW backlight delays to 1 because we do manual waits |
| 5039 | * on them. For T8, even BSpec recommends doing it. For T9, if we |
| 5040 | * don't do this, we'll end up waiting for the backlight off delay |
| 5041 | * twice: once when we do the manual sleep, and once when we disable |
| 5042 | * the panel and wait for the PP_STATUS bit to become zero. |
| 5043 | */ |
| 5044 | final->t8 = 1; |
| 5045 | final->t9 = 1; |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5046 | } |
| 5047 | |
| 5048 | static void |
| 5049 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5050 | struct intel_dp *intel_dp) |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5051 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5052 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5053 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 5054 | int div = dev_priv->rawclk_freq / 1000; |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5055 | struct pps_registers regs; |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5056 | enum port port = dp_to_dig_port(intel_dp)->port; |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5057 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5058 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 5059 | lockdep_assert_held(&dev_priv->pps_mutex); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5060 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5061 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5062 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5063 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 5064 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 5065 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5066 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5067 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 5068 | * formula. */ |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5069 | if (IS_BROXTON(dev)) { |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5070 | pp_div = I915_READ(regs.pp_ctrl); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5071 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
| 5072 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
| 5073 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
| 5074 | } else { |
| 5075 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
| 5076 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
| 5077 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 5078 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5079 | |
| 5080 | /* Haswell doesn't have any port selection bits for the panel |
| 5081 | * power sequencer any more. */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5082 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5083 | port_sel = PANEL_PORT_SELECT_VLV(port); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 5084 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5085 | if (port == PORT_A) |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 5086 | port_sel = PANEL_PORT_SELECT_DPA; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5087 | else |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 5088 | port_sel = PANEL_PORT_SELECT_DPD; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5089 | } |
| 5090 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5091 | pp_on |= port_sel; |
| 5092 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5093 | I915_WRITE(regs.pp_on, pp_on); |
| 5094 | I915_WRITE(regs.pp_off, pp_off); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5095 | if (IS_BROXTON(dev)) |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5096 | I915_WRITE(regs.pp_ctrl, pp_div); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5097 | else |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5098 | I915_WRITE(regs.pp_div, pp_div); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5099 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5100 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5101 | I915_READ(regs.pp_on), |
| 5102 | I915_READ(regs.pp_off), |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5103 | IS_BROXTON(dev) ? |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5104 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
| 5105 | I915_READ(regs.pp_div)); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 5106 | } |
| 5107 | |
Imre Deak | 335f752 | 2016-08-10 14:07:32 +0300 | [diff] [blame] | 5108 | static void intel_dp_pps_init(struct drm_device *dev, |
| 5109 | struct intel_dp *intel_dp) |
| 5110 | { |
| 5111 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 5112 | vlv_initial_power_sequencer_setup(intel_dp); |
| 5113 | } else { |
| 5114 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 5115 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
| 5116 | } |
| 5117 | } |
| 5118 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5119 | /** |
| 5120 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
Maarten Lankhorst | 5423adf | 2016-08-31 11:01:36 +0200 | [diff] [blame] | 5121 | * @dev_priv: i915 device |
Maarten Lankhorst | e896402 | 2016-08-25 11:07:02 +0200 | [diff] [blame] | 5122 | * @crtc_state: a pointer to the active intel_crtc_state |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5123 | * @refresh_rate: RR to be programmed |
| 5124 | * |
| 5125 | * This function gets called when refresh rate (RR) has to be changed from |
| 5126 | * one frequency to another. Switches can be between high and low RR |
| 5127 | * supported by the panel or to any other RR based on media playback (in |
| 5128 | * this case, RR value needs to be passed from user space). |
| 5129 | * |
| 5130 | * The caller of this function needs to take a lock on dev_priv->drrs. |
| 5131 | */ |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5132 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
| 5133 | struct intel_crtc_state *crtc_state, |
| 5134 | int refresh_rate) |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5135 | { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5136 | struct intel_encoder *encoder; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5137 | struct intel_digital_port *dig_port = NULL; |
| 5138 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5140 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5141 | |
| 5142 | if (refresh_rate <= 0) { |
| 5143 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
| 5144 | return; |
| 5145 | } |
| 5146 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5147 | if (intel_dp == NULL) { |
| 5148 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5149 | return; |
| 5150 | } |
| 5151 | |
Daniel Vetter | 1fcc9d1 | 2014-07-11 10:30:10 -0700 | [diff] [blame] | 5152 | /* |
Rodrigo Vivi | e4d59f6 | 2014-11-20 02:22:08 -0800 | [diff] [blame] | 5153 | * FIXME: This needs proper synchronization with psr state for some |
| 5154 | * platforms that cannot have PSR and DRRS enabled at the same time. |
Daniel Vetter | 1fcc9d1 | 2014-07-11 10:30:10 -0700 | [diff] [blame] | 5155 | */ |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5156 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5157 | dig_port = dp_to_dig_port(intel_dp); |
| 5158 | encoder = &dig_port->base; |
Ander Conselvan de Oliveira | 723f9aa | 2015-03-20 16:18:18 +0200 | [diff] [blame] | 5159 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5160 | |
| 5161 | if (!intel_crtc) { |
| 5162 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
| 5163 | return; |
| 5164 | } |
| 5165 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5166 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5167 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
| 5168 | return; |
| 5169 | } |
| 5170 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5171 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
| 5172 | refresh_rate) |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5173 | index = DRRS_LOW_RR; |
| 5174 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5175 | if (index == dev_priv->drrs.refresh_rate_type) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5176 | DRM_DEBUG_KMS( |
| 5177 | "DRRS requested for previously set RR...ignoring\n"); |
| 5178 | return; |
| 5179 | } |
| 5180 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5181 | if (!crtc_state->base.active) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5182 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
| 5183 | return; |
| 5184 | } |
| 5185 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5186 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
Vandana Kannan | a4c30b1 | 2015-02-13 15:33:00 +0530 | [diff] [blame] | 5187 | switch (index) { |
| 5188 | case DRRS_HIGH_RR: |
| 5189 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 5190 | break; |
| 5191 | case DRRS_LOW_RR: |
| 5192 | intel_dp_set_m_n(intel_crtc, M2_N2); |
| 5193 | break; |
| 5194 | case DRRS_MAX_RR: |
| 5195 | default: |
| 5196 | DRM_ERROR("Unsupported refreshrate type\n"); |
| 5197 | } |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5198 | } else if (INTEL_GEN(dev_priv) > 6) { |
| 5199 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 5200 | u32 val; |
Vandana Kannan | a4c30b1 | 2015-02-13 15:33:00 +0530 | [diff] [blame] | 5201 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 5202 | val = I915_READ(reg); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5203 | if (index > DRRS_HIGH_RR) { |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5204 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
Vandana Kannan | 6fa7aec | 2015-02-13 15:33:01 +0530 | [diff] [blame] | 5205 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5206 | else |
| 5207 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5208 | } else { |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5209 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
Vandana Kannan | 6fa7aec | 2015-02-13 15:33:01 +0530 | [diff] [blame] | 5210 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5211 | else |
| 5212 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5213 | } |
| 5214 | I915_WRITE(reg, val); |
| 5215 | } |
| 5216 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5217 | dev_priv->drrs.refresh_rate_type = index; |
| 5218 | |
| 5219 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
| 5220 | } |
| 5221 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5222 | /** |
| 5223 | * intel_edp_drrs_enable - init drrs struct if supported |
| 5224 | * @intel_dp: DP struct |
Maarten Lankhorst | 5423adf | 2016-08-31 11:01:36 +0200 | [diff] [blame] | 5225 | * @crtc_state: A pointer to the active crtc state. |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5226 | * |
| 5227 | * Initializes frontbuffer_bits and drrs.dp |
| 5228 | */ |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5229 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
| 5230 | struct intel_crtc_state *crtc_state) |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5231 | { |
| 5232 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5233 | struct drm_i915_private *dev_priv = to_i915(dev); |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5234 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5235 | if (!crtc_state->has_drrs) { |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5236 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
| 5237 | return; |
| 5238 | } |
| 5239 | |
| 5240 | mutex_lock(&dev_priv->drrs.mutex); |
| 5241 | if (WARN_ON(dev_priv->drrs.dp)) { |
| 5242 | DRM_ERROR("DRRS already enabled\n"); |
| 5243 | goto unlock; |
| 5244 | } |
| 5245 | |
| 5246 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
| 5247 | |
| 5248 | dev_priv->drrs.dp = intel_dp; |
| 5249 | |
| 5250 | unlock: |
| 5251 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5252 | } |
| 5253 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5254 | /** |
| 5255 | * intel_edp_drrs_disable - Disable DRRS |
| 5256 | * @intel_dp: DP struct |
Maarten Lankhorst | 5423adf | 2016-08-31 11:01:36 +0200 | [diff] [blame] | 5257 | * @old_crtc_state: Pointer to old crtc_state. |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5258 | * |
| 5259 | */ |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5260 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
| 5261 | struct intel_crtc_state *old_crtc_state) |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5262 | { |
| 5263 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5264 | struct drm_i915_private *dev_priv = to_i915(dev); |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5265 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5266 | if (!old_crtc_state->has_drrs) |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5267 | return; |
| 5268 | |
| 5269 | mutex_lock(&dev_priv->drrs.mutex); |
| 5270 | if (!dev_priv->drrs.dp) { |
| 5271 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5272 | return; |
| 5273 | } |
| 5274 | |
| 5275 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5276 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
| 5277 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5278 | |
| 5279 | dev_priv->drrs.dp = NULL; |
| 5280 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5281 | |
| 5282 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
| 5283 | } |
| 5284 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5285 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
| 5286 | { |
| 5287 | struct drm_i915_private *dev_priv = |
| 5288 | container_of(work, typeof(*dev_priv), drrs.work.work); |
| 5289 | struct intel_dp *intel_dp; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5290 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5291 | mutex_lock(&dev_priv->drrs.mutex); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5292 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5293 | intel_dp = dev_priv->drrs.dp; |
| 5294 | |
| 5295 | if (!intel_dp) |
| 5296 | goto unlock; |
| 5297 | |
| 5298 | /* |
| 5299 | * The delayed work can race with an invalidate hence we need to |
| 5300 | * recheck. |
| 5301 | */ |
| 5302 | |
| 5303 | if (dev_priv->drrs.busy_frontbuffer_bits) |
| 5304 | goto unlock; |
| 5305 | |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5306 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
| 5307 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; |
| 5308 | |
| 5309 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
| 5310 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); |
| 5311 | } |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5312 | |
| 5313 | unlock: |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5314 | mutex_unlock(&dev_priv->drrs.mutex); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5315 | } |
| 5316 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5317 | /** |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5318 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5319 | * @dev_priv: i915 device |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5320 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5321 | * |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5322 | * This function gets called everytime rendering on the given planes start. |
| 5323 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5324 | * |
| 5325 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5326 | */ |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5327 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
| 5328 | unsigned int frontbuffer_bits) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5329 | { |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5330 | struct drm_crtc *crtc; |
| 5331 | enum pipe pipe; |
| 5332 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5333 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5334 | return; |
| 5335 | |
Daniel Vetter | 88f933a | 2015-04-09 16:44:16 +0200 | [diff] [blame] | 5336 | cancel_delayed_work(&dev_priv->drrs.work); |
Ramalingam C | 3954e73 | 2015-03-03 12:11:46 +0530 | [diff] [blame] | 5337 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5338 | mutex_lock(&dev_priv->drrs.mutex); |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5339 | if (!dev_priv->drrs.dp) { |
| 5340 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5341 | return; |
| 5342 | } |
| 5343 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5344 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5345 | pipe = to_intel_crtc(crtc)->pipe; |
| 5346 | |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5347 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
| 5348 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
| 5349 | |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5350 | /* invalidate means busy screen hence upclock */ |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5351 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5352 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
| 5353 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5354 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5355 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5356 | } |
| 5357 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5358 | /** |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5359 | * intel_edp_drrs_flush - Restart Idleness DRRS |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5360 | * @dev_priv: i915 device |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5361 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5362 | * |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5363 | * This function gets called every time rendering on the given planes has |
| 5364 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
| 5365 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
| 5366 | * if no other planes are dirty. |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5367 | * |
| 5368 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5369 | */ |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5370 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
| 5371 | unsigned int frontbuffer_bits) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5372 | { |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5373 | struct drm_crtc *crtc; |
| 5374 | enum pipe pipe; |
| 5375 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5376 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5377 | return; |
| 5378 | |
Daniel Vetter | 88f933a | 2015-04-09 16:44:16 +0200 | [diff] [blame] | 5379 | cancel_delayed_work(&dev_priv->drrs.work); |
Ramalingam C | 3954e73 | 2015-03-03 12:11:46 +0530 | [diff] [blame] | 5380 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5381 | mutex_lock(&dev_priv->drrs.mutex); |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5382 | if (!dev_priv->drrs.dp) { |
| 5383 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5384 | return; |
| 5385 | } |
| 5386 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5387 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5388 | pipe = to_intel_crtc(crtc)->pipe; |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5389 | |
| 5390 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5391 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
| 5392 | |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5393 | /* flush means busy screen hence upclock */ |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5394 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Maarten Lankhorst | 85cb48a | 2016-08-09 17:04:13 +0200 | [diff] [blame] | 5395 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
| 5396 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5397 | |
| 5398 | /* |
| 5399 | * flush also means no more activity hence schedule downclock, if all |
| 5400 | * other fbs are quiescent too |
| 5401 | */ |
| 5402 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5403 | schedule_delayed_work(&dev_priv->drrs.work, |
| 5404 | msecs_to_jiffies(1000)); |
| 5405 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5406 | } |
| 5407 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5408 | /** |
| 5409 | * DOC: Display Refresh Rate Switching (DRRS) |
| 5410 | * |
| 5411 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
| 5412 | * which enables swtching between low and high refresh rates, |
| 5413 | * dynamically, based on the usage scenario. This feature is applicable |
| 5414 | * for internal panels. |
| 5415 | * |
| 5416 | * Indication that the panel supports DRRS is given by the panel EDID, which |
| 5417 | * would list multiple refresh rates for one resolution. |
| 5418 | * |
| 5419 | * DRRS is of 2 types - static and seamless. |
| 5420 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
| 5421 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
| 5422 | * Seamless DRRS involves changing RR without any visual effect to the user |
| 5423 | * and can be used during normal system usage. This is done by programming |
| 5424 | * certain registers. |
| 5425 | * |
| 5426 | * Support for static/seamless DRRS may be indicated in the VBT based on |
| 5427 | * inputs from the panel spec. |
| 5428 | * |
| 5429 | * DRRS saves power by switching to low RR based on usage scenarios. |
| 5430 | * |
Daniel Vetter | 2e7a570 | 2016-06-01 23:40:36 +0200 | [diff] [blame] | 5431 | * The implementation is based on frontbuffer tracking implementation. When |
| 5432 | * there is a disturbance on the screen triggered by user activity or a periodic |
| 5433 | * system activity, DRRS is disabled (RR is changed to high RR). When there is |
| 5434 | * no movement on screen, after a timeout of 1 second, a switch to low RR is |
| 5435 | * made. |
| 5436 | * |
| 5437 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() |
| 5438 | * and intel_edp_drrs_flush() are called. |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5439 | * |
| 5440 | * DRRS can be further extended to support other internal panels and also |
| 5441 | * the scenario of video playback wherein RR is set based on the rate |
| 5442 | * requested by userspace. |
| 5443 | */ |
| 5444 | |
| 5445 | /** |
| 5446 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
| 5447 | * @intel_connector: eDP connector |
| 5448 | * @fixed_mode: preferred mode of panel |
| 5449 | * |
| 5450 | * This function is called only once at driver load to initialize basic |
| 5451 | * DRRS stuff. |
| 5452 | * |
| 5453 | * Returns: |
| 5454 | * Downclock mode if panel supports it, else return NULL. |
| 5455 | * DRRS support is determined by the presence of downclock mode (apart |
| 5456 | * from VBT setting). |
| 5457 | */ |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5458 | static struct drm_display_mode * |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5459 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
| 5460 | struct drm_display_mode *fixed_mode) |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5461 | { |
| 5462 | struct drm_connector *connector = &intel_connector->base; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5463 | struct drm_device *dev = connector->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5464 | struct drm_i915_private *dev_priv = to_i915(dev); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5465 | struct drm_display_mode *downclock_mode = NULL; |
| 5466 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5467 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
| 5468 | mutex_init(&dev_priv->drrs.mutex); |
| 5469 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5470 | if (INTEL_INFO(dev)->gen <= 6) { |
| 5471 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
| 5472 | return NULL; |
| 5473 | } |
| 5474 | |
| 5475 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
Damien Lespiau | 4079b8d | 2014-08-05 10:39:42 +0100 | [diff] [blame] | 5476 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5477 | return NULL; |
| 5478 | } |
| 5479 | |
| 5480 | downclock_mode = intel_find_panel_downclock |
| 5481 | (dev, fixed_mode, connector); |
| 5482 | |
| 5483 | if (!downclock_mode) { |
Ramalingam C | a1d2634 | 2015-02-23 17:38:33 +0530 | [diff] [blame] | 5484 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5485 | return NULL; |
| 5486 | } |
| 5487 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5488 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5489 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5490 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
Damien Lespiau | 4079b8d | 2014-08-05 10:39:42 +0100 | [diff] [blame] | 5491 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5492 | return downclock_mode; |
| 5493 | } |
| 5494 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5495 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5496 | struct intel_connector *intel_connector) |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5497 | { |
| 5498 | struct drm_connector *connector = &intel_connector->base; |
| 5499 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 5500 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5501 | struct drm_device *dev = intel_encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5502 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5503 | struct drm_display_mode *fixed_mode = NULL; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5504 | struct drm_display_mode *downclock_mode = NULL; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5505 | bool has_dpcd; |
| 5506 | struct drm_display_mode *scan; |
| 5507 | struct edid *edid; |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5508 | enum pipe pipe = INVALID_PIPE; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5509 | |
| 5510 | if (!is_edp(intel_dp)) |
| 5511 | return true; |
| 5512 | |
Imre Deak | 97a824e1 | 2016-06-21 11:51:47 +0300 | [diff] [blame] | 5513 | /* |
| 5514 | * On IBX/CPT we may get here with LVDS already registered. Since the |
| 5515 | * driver uses the only internal power sequencer available for both |
| 5516 | * eDP and LVDS bail out early in this case to prevent interfering |
| 5517 | * with an already powered-on LVDS power sequencer. |
| 5518 | */ |
| 5519 | if (intel_get_lvds_encoder(dev)) { |
| 5520 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); |
| 5521 | DRM_INFO("LVDS was detected, not registering eDP\n"); |
| 5522 | |
| 5523 | return false; |
| 5524 | } |
| 5525 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 5526 | pps_lock(intel_dp); |
Imre Deak | b4d06ed | 2016-06-21 11:51:49 +0300 | [diff] [blame] | 5527 | |
| 5528 | intel_dp_init_panel_power_timestamps(intel_dp); |
Imre Deak | 335f752 | 2016-08-10 14:07:32 +0300 | [diff] [blame] | 5529 | intel_dp_pps_init(dev, intel_dp); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 5530 | intel_edp_panel_vdd_sanitize(intel_dp); |
Imre Deak | b4d06ed | 2016-06-21 11:51:49 +0300 | [diff] [blame] | 5531 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 5532 | pps_unlock(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 5533 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5534 | /* Cache DPCD and EDID for edp. */ |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 5535 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5536 | |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 5537 | if (!has_dpcd) { |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5538 | /* if this fails, presume the device is a ghost */ |
| 5539 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Imre Deak | b4d06ed | 2016-06-21 11:51:49 +0300 | [diff] [blame] | 5540 | goto out_vdd_off; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5541 | } |
| 5542 | |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 5543 | mutex_lock(&dev->mode_config.mutex); |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 5544 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5545 | if (edid) { |
| 5546 | if (drm_add_edid_modes(connector, edid)) { |
| 5547 | drm_mode_connector_update_edid_property(connector, |
| 5548 | edid); |
| 5549 | drm_edid_to_eld(connector, edid); |
| 5550 | } else { |
| 5551 | kfree(edid); |
| 5552 | edid = ERR_PTR(-EINVAL); |
| 5553 | } |
| 5554 | } else { |
| 5555 | edid = ERR_PTR(-ENOENT); |
| 5556 | } |
| 5557 | intel_connector->edid = edid; |
| 5558 | |
| 5559 | /* prefer fixed mode from EDID if available */ |
| 5560 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 5561 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 5562 | fixed_mode = drm_mode_duplicate(dev, scan); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5563 | downclock_mode = intel_dp_drrs_init( |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5564 | intel_connector, fixed_mode); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5565 | break; |
| 5566 | } |
| 5567 | } |
| 5568 | |
| 5569 | /* fallback to VBT if available for eDP */ |
| 5570 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 5571 | fixed_mode = drm_mode_duplicate(dev, |
| 5572 | dev_priv->vbt.lfp_lvds_vbt_mode); |
Ville Syrjälä | df45724 | 2016-05-31 12:08:34 +0300 | [diff] [blame] | 5573 | if (fixed_mode) { |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5574 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
Ville Syrjälä | df45724 | 2016-05-31 12:08:34 +0300 | [diff] [blame] | 5575 | connector->display_info.width_mm = fixed_mode->width_mm; |
| 5576 | connector->display_info.height_mm = fixed_mode->height_mm; |
| 5577 | } |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5578 | } |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 5579 | mutex_unlock(&dev->mode_config.mutex); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5580 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5581 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 5582 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
| 5583 | register_reboot_notifier(&intel_dp->edp_notifier); |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5584 | |
| 5585 | /* |
| 5586 | * Figure out the current pipe for the initial backlight setup. |
| 5587 | * If the current pipe isn't valid, try the PPS pipe, and if that |
| 5588 | * fails just assume pipe A. |
| 5589 | */ |
| 5590 | if (IS_CHERRYVIEW(dev)) |
| 5591 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
| 5592 | else |
| 5593 | pipe = PORT_TO_PIPE(intel_dp->DP); |
| 5594 | |
| 5595 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5596 | pipe = intel_dp->pps_pipe; |
| 5597 | |
| 5598 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5599 | pipe = PIPE_A; |
| 5600 | |
| 5601 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
| 5602 | pipe_name(pipe)); |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 5603 | } |
| 5604 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5605 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
Jani Nikula | 5507fae | 2015-09-14 14:03:48 +0300 | [diff] [blame] | 5606 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5607 | intel_panel_setup_backlight(connector, pipe); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5608 | |
| 5609 | return true; |
Imre Deak | b4d06ed | 2016-06-21 11:51:49 +0300 | [diff] [blame] | 5610 | |
| 5611 | out_vdd_off: |
| 5612 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 5613 | /* |
| 5614 | * vdd might still be enabled do to the delayed vdd off. |
| 5615 | * Make sure vdd is actually turned off here. |
| 5616 | */ |
| 5617 | pps_lock(intel_dp); |
| 5618 | edp_panel_vdd_off_sync(intel_dp); |
| 5619 | pps_unlock(intel_dp); |
| 5620 | |
| 5621 | return false; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5622 | } |
| 5623 | |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5624 | bool |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5625 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 5626 | struct intel_connector *intel_connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5627 | { |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5628 | struct drm_connector *connector = &intel_connector->base; |
| 5629 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 5630 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5631 | struct drm_device *dev = intel_encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5632 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 5633 | enum port port = intel_dig_port->port; |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 5634 | int type; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5635 | |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 5636 | if (WARN(intel_dig_port->max_lanes < 1, |
| 5637 | "Not enough lanes (%d) for DP on port %c\n", |
| 5638 | intel_dig_port->max_lanes, port_name(port))) |
| 5639 | return false; |
| 5640 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 5641 | intel_dp->pps_pipe = INVALID_PIPE; |
| 5642 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5643 | /* intel_dp vfuncs */ |
Damien Lespiau | b6b5e38 | 2014-01-20 16:00:59 +0000 | [diff] [blame] | 5644 | if (INTEL_INFO(dev)->gen >= 9) |
| 5645 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5646 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 5647 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 5648 | else if (HAS_PCH_SPLIT(dev)) |
| 5649 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 5650 | else |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 5651 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5652 | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 5653 | if (INTEL_INFO(dev)->gen >= 9) |
| 5654 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
| 5655 | else |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 5656 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 5657 | |
Ander Conselvan de Oliveira | ad64217 | 2015-10-23 13:01:49 +0300 | [diff] [blame] | 5658 | if (HAS_DDI(dev)) |
| 5659 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
| 5660 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 5661 | /* Preserve the current hw state. */ |
| 5662 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 5663 | intel_dp->attached_connector = intel_connector; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 5664 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5665 | if (intel_dp_is_edp(dev, port)) |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 5666 | type = DRM_MODE_CONNECTOR_eDP; |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5667 | else |
| 5668 | type = DRM_MODE_CONNECTOR_DisplayPort; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 5669 | |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 5670 | /* |
| 5671 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 5672 | * for DP the encoder type can be set by the caller to |
| 5673 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 5674 | */ |
| 5675 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 5676 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 5677 | |
Ville Syrjälä | c17ed5b | 2014-10-16 21:27:27 +0300 | [diff] [blame] | 5678 | /* eDP only on port B and/or C on vlv/chv */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5679 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 5680 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
Ville Syrjälä | c17ed5b | 2014-10-16 21:27:27 +0300 | [diff] [blame] | 5681 | return false; |
| 5682 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 5683 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 5684 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 5685 | port_name(port)); |
| 5686 | |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 5687 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5688 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 5689 | |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5690 | connector->interlace_allowed = true; |
| 5691 | connector->doublescan_allowed = 0; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 5692 | |
Mika Kahola | b633958 | 2016-09-09 14:10:52 +0300 | [diff] [blame] | 5693 | intel_dp_aux_init(intel_dp); |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 5694 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 5695 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 5696 | edp_panel_vdd_work); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 5697 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 5698 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5699 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 5700 | if (HAS_DDI(dev)) |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 5701 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 5702 | else |
| 5703 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
| 5704 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 5705 | /* Set up the hotplug pin. */ |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5706 | switch (port) { |
| 5707 | case PORT_A: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5708 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5709 | break; |
| 5710 | case PORT_B: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5711 | intel_encoder->hpd_pin = HPD_PORT_B; |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 5712 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
Sonika Jindal | cf1d588 | 2015-08-10 10:35:36 +0530 | [diff] [blame] | 5713 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5714 | break; |
| 5715 | case PORT_C: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5716 | intel_encoder->hpd_pin = HPD_PORT_C; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5717 | break; |
| 5718 | case PORT_D: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5719 | intel_encoder->hpd_pin = HPD_PORT_D; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5720 | break; |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 5721 | case PORT_E: |
| 5722 | intel_encoder->hpd_pin = HPD_PORT_E; |
| 5723 | break; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5724 | default: |
Damien Lespiau | ad1c0b1 | 2013-03-07 15:30:28 +0000 | [diff] [blame] | 5725 | BUG(); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5726 | } |
| 5727 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5728 | /* init MST on ports that can support it */ |
Ville Syrjälä | f8e58dd | 2016-06-22 21:56:59 +0300 | [diff] [blame] | 5729 | if (HAS_DP_MST(dev) && !is_edp(intel_dp) && |
Jani Nikula | 0c9b371 | 2015-05-18 17:10:01 +0300 | [diff] [blame] | 5730 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
| 5731 | intel_dp_mst_encoder_init(intel_dig_port, |
| 5732 | intel_connector->base.base.id); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5733 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5734 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5735 | intel_dp_aux_fini(intel_dp); |
| 5736 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
| 5737 | goto fail; |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 5738 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 5739 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 5740 | intel_dp_add_properties(intel_dp, connector); |
| 5741 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5742 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 5743 | * 0xd. Failure to do so will result in spurious interrupts being |
| 5744 | * generated on the port when a cable is not attached. |
| 5745 | */ |
| 5746 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 5747 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 5748 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 5749 | } |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5750 | |
| 5751 | return true; |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5752 | |
| 5753 | fail: |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5754 | drm_connector_cleanup(connector); |
| 5755 | |
| 5756 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5757 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5758 | |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 5759 | bool intel_dp_init(struct drm_device *dev, |
| 5760 | i915_reg_t output_reg, |
| 5761 | enum port port) |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5762 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5763 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5764 | struct intel_digital_port *intel_dig_port; |
| 5765 | struct intel_encoder *intel_encoder; |
| 5766 | struct drm_encoder *encoder; |
| 5767 | struct intel_connector *intel_connector; |
| 5768 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 5769 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5770 | if (!intel_dig_port) |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 5771 | return false; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5772 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 5773 | intel_connector = intel_connector_alloc(); |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5774 | if (!intel_connector) |
| 5775 | goto err_connector_alloc; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5776 | |
| 5777 | intel_encoder = &intel_dig_port->base; |
| 5778 | encoder = &intel_encoder->base; |
| 5779 | |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5780 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
Ville Syrjälä | 580d8ed | 2016-05-27 20:59:24 +0300 | [diff] [blame] | 5781 | DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5782 | goto err_encoder_init; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5783 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 5784 | intel_encoder->compute_config = intel_dp_compute_config; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 5785 | intel_encoder->disable = intel_disable_dp; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 5786 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 5787 | intel_encoder->get_config = intel_dp_get_config; |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 5788 | intel_encoder->suspend = intel_dp_encoder_suspend; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5789 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 5790 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5791 | intel_encoder->pre_enable = chv_pre_enable_dp; |
| 5792 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 5793 | intel_encoder->post_disable = chv_post_disable_dp; |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 5794 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5795 | } else if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 5796 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5797 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
| 5798 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 5799 | intel_encoder->post_disable = vlv_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5800 | } else { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 5801 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
| 5802 | intel_encoder->enable = g4x_enable_dp; |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 5803 | if (INTEL_INFO(dev)->gen >= 5) |
| 5804 | intel_encoder->post_disable = ilk_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5805 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5806 | |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 5807 | intel_dig_port->port = port; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5808 | intel_dig_port->dp.output_reg = output_reg; |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 5809 | intel_dig_port->max_lanes = 4; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5810 | |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 5811 | intel_encoder->type = INTEL_OUTPUT_DP; |
Ville Syrjälä | 882ec38 | 2014-04-28 14:07:43 +0300 | [diff] [blame] | 5812 | if (IS_CHERRYVIEW(dev)) { |
| 5813 | if (port == PORT_D) |
| 5814 | intel_encoder->crtc_mask = 1 << 2; |
| 5815 | else |
| 5816 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
| 5817 | } else { |
| 5818 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 5819 | } |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 5820 | intel_encoder->cloneable = 0; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5821 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5822 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5823 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5824 | |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5825 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
| 5826 | goto err_init_connector; |
| 5827 | |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 5828 | return true; |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5829 | |
| 5830 | err_init_connector: |
| 5831 | drm_encoder_cleanup(encoder); |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5832 | err_encoder_init: |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5833 | kfree(intel_connector); |
| 5834 | err_connector_alloc: |
| 5835 | kfree(intel_dig_port); |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 5836 | return false; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5837 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5838 | |
| 5839 | void intel_dp_mst_suspend(struct drm_device *dev) |
| 5840 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5841 | struct drm_i915_private *dev_priv = to_i915(dev); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5842 | int i; |
| 5843 | |
| 5844 | /* disable MST */ |
| 5845 | for (i = 0; i < I915_MAX_PORTS; i++) { |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5846 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
Ville Syrjälä | 5aa5696 | 2016-06-22 21:57:00 +0300 | [diff] [blame] | 5847 | |
| 5848 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5849 | continue; |
| 5850 | |
Ville Syrjälä | 5aa5696 | 2016-06-22 21:57:00 +0300 | [diff] [blame] | 5851 | if (intel_dig_port->dp.is_mst) |
| 5852 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5853 | } |
| 5854 | } |
| 5855 | |
| 5856 | void intel_dp_mst_resume(struct drm_device *dev) |
| 5857 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5858 | struct drm_i915_private *dev_priv = to_i915(dev); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5859 | int i; |
| 5860 | |
| 5861 | for (i = 0; i < I915_MAX_PORTS; i++) { |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5862 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
Ville Syrjälä | 5aa5696 | 2016-06-22 21:57:00 +0300 | [diff] [blame] | 5863 | int ret; |
| 5864 | |
| 5865 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5866 | continue; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5867 | |
Ville Syrjälä | 5aa5696 | 2016-06-22 21:57:00 +0300 | [diff] [blame] | 5868 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
| 5869 | if (ret) |
| 5870 | intel_dp_check_mst_status(&intel_dig_port->dp); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5871 | } |
| 5872 | } |