Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | /* TODO: Here are things that needs to be done : |
| 32 | * - surface allocator & initializer : (bit like scratch reg) should |
| 33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 34 | * related to surface |
| 35 | * - WB : write back stuff (do it bit like scratch reg things) |
| 36 | * - Vblank : look at Jesse's rework and what we should do |
| 37 | * - r600/r700: gart & cp |
| 38 | * - cs : clean cs ioctl use bitmap & things like that. |
| 39 | * - power management stuff |
| 40 | * - Barrier in gart code |
| 41 | * - Unmappabled vram ? |
| 42 | * - TESTING, TESTING, TESTING |
| 43 | */ |
| 44 | |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 45 | /* Initialization path: |
| 46 | * We expect that acceleration initialization might fail for various |
| 47 | * reasons even thought we work hard to make it works on most |
| 48 | * configurations. In order to still have a working userspace in such |
| 49 | * situation the init path must succeed up to the memory controller |
| 50 | * initialization point. Failure before this point are considered as |
| 51 | * fatal error. Here is the init callchain : |
| 52 | * radeon_device_init perform common structure, mutex initialization |
| 53 | * asic_init setup the GPU memory layout and perform all |
| 54 | * one time initialization (failure in this |
| 55 | * function are considered fatal) |
| 56 | * asic_startup setup the GPU acceleration, in order to |
| 57 | * follow guideline the first thing this |
| 58 | * function should do is setting the GPU |
| 59 | * memory controller (only MC setup failure |
| 60 | * are considered as fatal) |
| 61 | */ |
| 62 | |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 63 | #include <linux/atomic.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 64 | #include <linux/wait.h> |
| 65 | #include <linux/list.h> |
| 66 | #include <linux/kref.h> |
| 67 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 68 | #include <ttm/ttm_bo_api.h> |
| 69 | #include <ttm/ttm_bo_driver.h> |
| 70 | #include <ttm/ttm_placement.h> |
| 71 | #include <ttm/ttm_module.h> |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 72 | #include <ttm/ttm_execbuf_util.h> |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 73 | |
Dave Airlie | c214271 | 2009-09-22 08:50:10 +1000 | [diff] [blame] | 74 | #include "radeon_family.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | #include "radeon_mode.h" |
| 76 | #include "radeon_reg.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Modules parameters. |
| 80 | */ |
| 81 | extern int radeon_no_wb; |
| 82 | extern int radeon_modeset; |
| 83 | extern int radeon_dynclks; |
| 84 | extern int radeon_r4xx_atom; |
| 85 | extern int radeon_agpmode; |
| 86 | extern int radeon_vram_limit; |
| 87 | extern int radeon_gart_size; |
| 88 | extern int radeon_benchmarking; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 89 | extern int radeon_testing; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 90 | extern int radeon_connector_table; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 91 | extern int radeon_tv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 92 | extern int radeon_audio; |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 93 | extern int radeon_disp_priority; |
Alex Deucher | e2b0a8e | 2010-03-17 02:07:37 -0400 | [diff] [blame] | 94 | extern int radeon_hw_i2c; |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 95 | extern int radeon_pcie_gen2; |
Alex Deucher | a18cee1 | 2011-11-01 14:20:30 -0400 | [diff] [blame] | 96 | extern int radeon_msi; |
Christian König | 3368ff0 | 2012-05-02 15:11:21 +0200 | [diff] [blame] | 97 | extern int radeon_lockup_timeout; |
Samuel Li | a0a53aa | 2013-04-08 17:25:47 -0400 | [diff] [blame] | 98 | extern int radeon_fastfb; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 99 | extern int radeon_dpm; |
Alex Deucher | 1294d4a | 2013-07-16 15:58:50 -0400 | [diff] [blame] | 100 | extern int radeon_aspm; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 101 | extern int radeon_runtime_pm; |
Alex Deucher | 363eb0b | 2014-01-08 17:55:08 -0500 | [diff] [blame] | 102 | extern int radeon_hard_reset; |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame] | 103 | extern int radeon_vm_size; |
Christian König | 4510fb9 | 2014-06-05 23:56:50 -0400 | [diff] [blame] | 104 | extern int radeon_vm_block_size; |
Alex Deucher | a624f42 | 2014-07-01 11:23:03 -0400 | [diff] [blame] | 105 | extern int radeon_deep_color; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 106 | |
| 107 | /* |
| 108 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 109 | * symbol; |
| 110 | */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 111 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 112 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 113 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 114 | #define RADEON_IB_POOL_SIZE 16 |
| 115 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
| 116 | #define RADEONFB_CONN_LIMIT 4 |
| 117 | #define RADEON_BIOS_NUM_SCRATCH 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 118 | |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 119 | /* fence seq are set to this number when signaled */ |
| 120 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 121 | |
| 122 | /* internal ring indices */ |
| 123 | /* r1xx+ has gfx CP ring */ |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 124 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 125 | |
| 126 | /* cayman has 2 compute CP rings */ |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 127 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
| 128 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 129 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 130 | /* R600+ has an async dma ring */ |
| 131 | #define R600_RING_TYPE_DMA_INDEX 3 |
Alex Deucher | f60cbd1 | 2012-12-04 15:27:33 -0500 | [diff] [blame] | 132 | /* cayman add a second async dma ring */ |
| 133 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 134 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 135 | /* R600+ */ |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 136 | #define R600_RING_TYPE_UVD_INDEX 5 |
| 137 | |
| 138 | /* TN+ */ |
| 139 | #define TN_RING_TYPE_VCE1_INDEX 6 |
| 140 | #define TN_RING_TYPE_VCE2_INDEX 7 |
| 141 | |
| 142 | /* max number of rings */ |
| 143 | #define RADEON_NUM_RINGS 8 |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 144 | |
Christian König | 1c61eae | 2014-02-18 01:50:22 -0700 | [diff] [blame] | 145 | /* number of hw syncs before falling back on blocking */ |
| 146 | #define RADEON_NUM_SYNCS 4 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 147 | |
Christian König | 8f53492 | 2014-02-18 11:37:20 +0100 | [diff] [blame] | 148 | /* number of hw syncs before falling back on blocking */ |
| 149 | #define RADEON_NUM_SYNCS 4 |
| 150 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 151 | /* hardcode those limit for now */ |
Christian König | ca19f21 | 2012-09-11 16:09:59 +0200 | [diff] [blame] | 152 | #define RADEON_VA_IB_OFFSET (1 << 20) |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 153 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
| 154 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 155 | |
Alex Deucher | 1a0041b | 2013-10-02 13:01:36 -0400 | [diff] [blame] | 156 | /* hard reset data */ |
| 157 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b |
| 158 | |
Alex Deucher | ec46c76 | 2013-01-03 12:07:30 -0500 | [diff] [blame] | 159 | /* reset flags */ |
| 160 | #define RADEON_RESET_GFX (1 << 0) |
| 161 | #define RADEON_RESET_COMPUTE (1 << 1) |
| 162 | #define RADEON_RESET_DMA (1 << 2) |
Alex Deucher | 9ff0744 | 2013-01-18 12:18:17 -0500 | [diff] [blame] | 163 | #define RADEON_RESET_CP (1 << 3) |
| 164 | #define RADEON_RESET_GRBM (1 << 4) |
| 165 | #define RADEON_RESET_DMA1 (1 << 5) |
| 166 | #define RADEON_RESET_RLC (1 << 6) |
| 167 | #define RADEON_RESET_SEM (1 << 7) |
| 168 | #define RADEON_RESET_IH (1 << 8) |
| 169 | #define RADEON_RESET_VMC (1 << 9) |
| 170 | #define RADEON_RESET_MC (1 << 10) |
| 171 | #define RADEON_RESET_DISPLAY (1 << 11) |
Alex Deucher | ec46c76 | 2013-01-03 12:07:30 -0500 | [diff] [blame] | 172 | |
Alex Deucher | 22c775c | 2013-07-23 09:41:05 -0400 | [diff] [blame] | 173 | /* CG block flags */ |
| 174 | #define RADEON_CG_BLOCK_GFX (1 << 0) |
| 175 | #define RADEON_CG_BLOCK_MC (1 << 1) |
| 176 | #define RADEON_CG_BLOCK_SDMA (1 << 2) |
| 177 | #define RADEON_CG_BLOCK_UVD (1 << 3) |
| 178 | #define RADEON_CG_BLOCK_VCE (1 << 4) |
| 179 | #define RADEON_CG_BLOCK_HDP (1 << 5) |
Alex Deucher | e16866e | 2013-08-08 19:34:07 -0400 | [diff] [blame] | 180 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
Alex Deucher | 22c775c | 2013-07-23 09:41:05 -0400 | [diff] [blame] | 181 | |
Alex Deucher | 64d8a72 | 2013-08-08 16:31:25 -0400 | [diff] [blame] | 182 | /* CG flags */ |
| 183 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) |
| 184 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) |
| 185 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) |
| 186 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) |
| 187 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) |
| 188 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) |
| 189 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) |
| 190 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) |
| 191 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) |
| 192 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) |
| 193 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) |
| 194 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) |
| 195 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) |
| 196 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) |
| 197 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) |
| 198 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) |
| 199 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) |
| 200 | |
| 201 | /* PG flags */ |
Alex Deucher | 2b19d17 | 2013-09-04 16:58:29 -0400 | [diff] [blame] | 202 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
Alex Deucher | 64d8a72 | 2013-08-08 16:31:25 -0400 | [diff] [blame] | 203 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
| 204 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) |
| 205 | #define RADEON_PG_SUPPORT_UVD (1 << 3) |
| 206 | #define RADEON_PG_SUPPORT_VCE (1 << 4) |
| 207 | #define RADEON_PG_SUPPORT_CP (1 << 5) |
| 208 | #define RADEON_PG_SUPPORT_GDS (1 << 6) |
| 209 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) |
| 210 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) |
| 211 | #define RADEON_PG_SUPPORT_ACP (1 << 9) |
| 212 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) |
| 213 | |
Alex Deucher | 9e05fa1 | 2013-01-24 10:06:33 -0500 | [diff] [blame] | 214 | /* max cursor sizes (in pixels) */ |
| 215 | #define CURSOR_WIDTH 64 |
| 216 | #define CURSOR_HEIGHT 64 |
| 217 | |
| 218 | #define CIK_CURSOR_WIDTH 128 |
| 219 | #define CIK_CURSOR_HEIGHT 128 |
| 220 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 221 | /* |
| 222 | * Errata workarounds. |
| 223 | */ |
| 224 | enum radeon_pll_errata { |
| 225 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 226 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 227 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 228 | }; |
| 229 | |
| 230 | |
| 231 | struct radeon_device; |
| 232 | |
| 233 | |
| 234 | /* |
| 235 | * BIOS. |
| 236 | */ |
| 237 | bool radeon_get_bios(struct radeon_device *rdev); |
| 238 | |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 239 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 240 | * Dummy page |
| 241 | */ |
| 242 | struct radeon_dummy_page { |
| 243 | struct page *page; |
| 244 | dma_addr_t addr; |
| 245 | }; |
| 246 | int radeon_dummy_page_init(struct radeon_device *rdev); |
| 247 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
| 248 | |
| 249 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | /* |
| 251 | * Clocks |
| 252 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 253 | struct radeon_clock { |
| 254 | struct radeon_pll p1pll; |
| 255 | struct radeon_pll p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 256 | struct radeon_pll dcpll; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 257 | struct radeon_pll spll; |
| 258 | struct radeon_pll mpll; |
| 259 | /* 10 Khz units */ |
| 260 | uint32_t default_mclk; |
| 261 | uint32_t default_sclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 262 | uint32_t default_dispclk; |
Alex Deucher | 4489cd62 | 2013-03-22 15:59:10 -0400 | [diff] [blame] | 263 | uint32_t current_dispclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 264 | uint32_t dp_extclk; |
Alex Deucher | b20f9be | 2011-06-08 13:01:11 -0400 | [diff] [blame] | 265 | uint32_t max_pixel_clock; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 266 | }; |
| 267 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 268 | /* |
| 269 | * Power management |
| 270 | */ |
| 271 | int radeon_pm_init(struct radeon_device *rdev); |
Alex Deucher | 914a898 | 2013-12-19 11:37:22 -0500 | [diff] [blame] | 272 | int radeon_pm_late_init(struct radeon_device *rdev); |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 273 | void radeon_pm_fini(struct radeon_device *rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 274 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 275 | void radeon_pm_suspend(struct radeon_device *rdev); |
| 276 | void radeon_pm_resume(struct radeon_device *rdev); |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 277 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
| 278 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
Christian König | 7062ab6 | 2013-04-08 12:41:31 +0200 | [diff] [blame] | 279 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
| 280 | u8 clock_type, |
| 281 | u32 clock, |
| 282 | bool strobe_mode, |
| 283 | struct atom_clock_dividers *dividers); |
Alex Deucher | eaa778a | 2013-02-13 16:38:25 -0500 | [diff] [blame] | 284 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
| 285 | u32 clock, |
| 286 | bool strobe_mode, |
| 287 | struct atom_mpll_param *mpll_param); |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 288 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
Alex Deucher | ae5b0ab | 2013-06-24 10:50:34 -0400 | [diff] [blame] | 289 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
| 290 | u16 voltage_level, u8 voltage_type, |
| 291 | u32 *gpio_value, u32 *gpio_mask); |
| 292 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
| 293 | u32 eng_clock, u32 mem_clock); |
| 294 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, |
| 295 | u8 voltage_type, u16 *voltage_step); |
Alex Deucher | 4a6369e | 2013-04-12 14:04:10 -0400 | [diff] [blame] | 296 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
| 297 | u16 voltage_id, u16 *voltage); |
Alex Deucher | beb79f4 | 2013-02-19 17:14:43 -0500 | [diff] [blame] | 298 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
| 299 | u16 *voltage, |
| 300 | u16 leakage_idx); |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 301 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
| 302 | u16 *leakage_id); |
| 303 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, |
| 304 | u16 *vddc, u16 *vddci, |
| 305 | u16 virtual_voltage_id, |
| 306 | u16 vbios_voltage_id); |
Alex Deucher | ae5b0ab | 2013-06-24 10:50:34 -0400 | [diff] [blame] | 307 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
| 308 | u8 voltage_type, |
| 309 | u16 nominal_voltage, |
| 310 | u16 *true_voltage); |
| 311 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, |
| 312 | u8 voltage_type, u16 *min_voltage); |
| 313 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
| 314 | u8 voltage_type, u16 *max_voltage); |
| 315 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, |
Alex Deucher | 6517194 | 2013-02-13 17:29:54 -0500 | [diff] [blame] | 316 | u8 voltage_type, u8 voltage_mode, |
Alex Deucher | ae5b0ab | 2013-06-24 10:50:34 -0400 | [diff] [blame] | 317 | struct atom_voltage_table *voltage_table); |
Alex Deucher | 58653ab | 2013-02-13 17:04:59 -0500 | [diff] [blame] | 318 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
| 319 | u8 voltage_type, u8 voltage_mode); |
Alex Deucher | 636e258 | 2014-06-06 18:43:45 -0400 | [diff] [blame] | 320 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
| 321 | u8 voltage_type, |
| 322 | u8 *svd_gpio_id, u8 *svc_gpio_id); |
Alex Deucher | ae5b0ab | 2013-06-24 10:50:34 -0400 | [diff] [blame] | 323 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
| 324 | u32 mem_clock); |
| 325 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, |
| 326 | u32 mem_clock); |
| 327 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, |
| 328 | u8 module_index, |
| 329 | struct atom_mc_reg_table *reg_table); |
| 330 | int radeon_atom_get_memory_info(struct radeon_device *rdev, |
| 331 | u8 module_index, struct atom_memory_info *mem_info); |
| 332 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, |
| 333 | bool gddr5, u8 module_index, |
| 334 | struct atom_memory_clock_range_table *mclk_range_table); |
| 335 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
| 336 | u16 voltage_id, u16 *voltage); |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 337 | void rs690_pm_info(struct radeon_device *rdev); |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 338 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
| 339 | unsigned *bankh, unsigned *mtaspect, |
| 340 | unsigned *tile_split); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 341 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 342 | /* |
| 343 | * Fences. |
| 344 | */ |
| 345 | struct radeon_fence_driver { |
| 346 | uint32_t scratch_reg; |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 347 | uint64_t gpu_addr; |
| 348 | volatile uint32_t *cpu_addr; |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 349 | /* sync_seq is protected by ring emission lock */ |
| 350 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 351 | atomic64_t last_seq; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 352 | bool initialized; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | struct radeon_fence { |
| 356 | struct radeon_device *rdev; |
| 357 | struct kref kref; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 358 | /* protected by radeon_fence.lock */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 359 | uint64_t seq; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 360 | /* RB, DMA, etc. */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 361 | unsigned ring; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 362 | }; |
| 363 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 364 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
| 365 | int radeon_fence_driver_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 366 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
Jerome Glisse | 76903b9 | 2012-12-17 10:29:06 -0500 | [diff] [blame] | 367 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 368 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 369 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 370 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 371 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
Christian König | 3761552 | 2014-02-18 15:58:31 +0100 | [diff] [blame] | 372 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
| 373 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 374 | int radeon_fence_wait_any(struct radeon_device *rdev, |
| 375 | struct radeon_fence **fences, |
| 376 | bool intr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 377 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 378 | void radeon_fence_unref(struct radeon_fence **fence); |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 379 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 380 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
| 381 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
| 382 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
| 383 | struct radeon_fence *b) |
| 384 | { |
| 385 | if (!a) { |
| 386 | return b; |
| 387 | } |
| 388 | |
| 389 | if (!b) { |
| 390 | return a; |
| 391 | } |
| 392 | |
| 393 | BUG_ON(a->ring != b->ring); |
| 394 | |
| 395 | if (a->seq > b->seq) { |
| 396 | return a; |
| 397 | } else { |
| 398 | return b; |
| 399 | } |
| 400 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 401 | |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 402 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
| 403 | struct radeon_fence *b) |
| 404 | { |
| 405 | if (!a) { |
| 406 | return false; |
| 407 | } |
| 408 | |
| 409 | if (!b) { |
| 410 | return true; |
| 411 | } |
| 412 | |
| 413 | BUG_ON(a->ring != b->ring); |
| 414 | |
| 415 | return a->seq < b->seq; |
| 416 | } |
| 417 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 418 | /* |
| 419 | * Tiling registers |
| 420 | */ |
| 421 | struct radeon_surface_reg { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 422 | struct radeon_bo *bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 423 | }; |
| 424 | |
| 425 | #define RADEON_GEM_MAX_SURFACES 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 426 | |
| 427 | /* |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 428 | * TTM. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 429 | */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 430 | struct radeon_mman { |
| 431 | struct ttm_bo_global_ref bo_global_ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 432 | struct drm_global_reference mem_global_ref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 433 | struct ttm_bo_device bdev; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 434 | bool mem_global_referenced; |
| 435 | bool initialized; |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 436 | |
| 437 | #if defined(CONFIG_DEBUG_FS) |
| 438 | struct dentry *vram; |
Christian König | dd66d20 | 2013-12-18 21:07:40 +0100 | [diff] [blame] | 439 | struct dentry *gtt; |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 440 | #endif |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 441 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 442 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 443 | /* bo virtual address in a specific vm */ |
| 444 | struct radeon_bo_va { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 445 | /* protected by bo being reserved */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 446 | struct list_head bo_list; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 447 | uint64_t soffset; |
| 448 | uint64_t eoffset; |
| 449 | uint32_t flags; |
| 450 | bool valid; |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 451 | unsigned ref_count; |
| 452 | |
| 453 | /* protected by vm mutex */ |
| 454 | struct list_head vm_list; |
Christian König | 036bf46 | 2014-07-18 08:56:40 +0200 | [diff] [blame] | 455 | struct list_head vm_status; |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 456 | |
| 457 | /* constant after initialization */ |
| 458 | struct radeon_vm *vm; |
| 459 | struct radeon_bo *bo; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 460 | }; |
| 461 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 462 | struct radeon_bo { |
| 463 | /* Protected by gem.mutex */ |
| 464 | struct list_head list; |
| 465 | /* Protected by tbo.reserved */ |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame] | 466 | u32 initial_domain; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 467 | u32 placements[3]; |
| 468 | struct ttm_placement placement; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 469 | struct ttm_buffer_object tbo; |
| 470 | struct ttm_bo_kmap_obj kmap; |
Michel Dänzer | 02376d8 | 2014-07-17 19:01:08 +0900 | [diff] [blame] | 471 | u32 flags; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 472 | unsigned pin_count; |
| 473 | void *kptr; |
| 474 | u32 tiling_flags; |
| 475 | u32 pitch; |
| 476 | int surface_reg; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 477 | /* list of all virtual address to which this bo |
| 478 | * is associated to |
| 479 | */ |
| 480 | struct list_head va; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 481 | /* Constant after initialization */ |
| 482 | struct radeon_device *rdev; |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 483 | struct drm_gem_object gem_base; |
Dave Airlie | 63bc620 | 2012-05-31 13:52:53 +0100 | [diff] [blame] | 484 | |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 485 | struct ttm_bo_kmap_obj dma_buf_vmap; |
| 486 | pid_t pid; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 487 | }; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 488 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 489 | |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 490 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
| 491 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 492 | /* sub-allocation manager, it has to be protected by another lock. |
| 493 | * By conception this is an helper for other part of the driver |
| 494 | * like the indirect buffer or semaphore, which both have their |
| 495 | * locking. |
| 496 | * |
| 497 | * Principe is simple, we keep a list of sub allocation in offset |
| 498 | * order (first entry has offset == 0, last entry has the highest |
| 499 | * offset). |
| 500 | * |
| 501 | * When allocating new object we first check if there is room at |
| 502 | * the end total_size - (last_object_offset + last_object_size) >= |
| 503 | * alloc_size. If so we allocate new object there. |
| 504 | * |
| 505 | * When there is not enough room at the end, we start waiting for |
| 506 | * each sub object until we reach object_offset+object_size >= |
| 507 | * alloc_size, this object then become the sub object we return. |
| 508 | * |
| 509 | * Alignment can't be bigger than page size. |
| 510 | * |
| 511 | * Hole are not considered for allocation to keep things simple. |
| 512 | * Assumption is that there won't be hole (all object on same |
| 513 | * alignment). |
| 514 | */ |
| 515 | struct radeon_sa_manager { |
Christian König | bfb38d3 | 2012-07-11 21:07:57 +0200 | [diff] [blame] | 516 | wait_queue_head_t wq; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 517 | struct radeon_bo *bo; |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 518 | struct list_head *hole; |
| 519 | struct list_head flist[RADEON_NUM_RINGS]; |
| 520 | struct list_head olist; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 521 | unsigned size; |
| 522 | uint64_t gpu_addr; |
| 523 | void *cpu_ptr; |
| 524 | uint32_t domain; |
Alex Deucher | 6c4f978 | 2013-07-12 15:46:09 -0400 | [diff] [blame] | 525 | uint32_t align; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 526 | }; |
| 527 | |
| 528 | struct radeon_sa_bo; |
| 529 | |
| 530 | /* sub-allocation buffer */ |
| 531 | struct radeon_sa_bo { |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 532 | struct list_head olist; |
| 533 | struct list_head flist; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 534 | struct radeon_sa_manager *manager; |
Christian König | e6661a9 | 2012-05-09 15:34:52 +0200 | [diff] [blame] | 535 | unsigned soffset; |
| 536 | unsigned eoffset; |
Christian König | 557017a | 2012-05-09 15:34:54 +0200 | [diff] [blame] | 537 | struct radeon_fence *fence; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 538 | }; |
| 539 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 540 | /* |
| 541 | * GEM objects. |
| 542 | */ |
| 543 | struct radeon_gem { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 544 | struct mutex mutex; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 545 | struct list_head objects; |
| 546 | }; |
| 547 | |
| 548 | int radeon_gem_init(struct radeon_device *rdev); |
| 549 | void radeon_gem_fini(struct radeon_device *rdev); |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 550 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 551 | int alignment, int initial_domain, |
Christian König | ed5cb43 | 2014-07-21 13:27:27 +0200 | [diff] [blame] | 552 | u32 flags, bool kernel, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 553 | struct drm_gem_object **obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 554 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 555 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
| 556 | struct drm_device *dev, |
| 557 | struct drm_mode_create_dumb *args); |
| 558 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
| 559 | struct drm_device *dev, |
| 560 | uint32_t handle, uint64_t *offset_p); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 561 | |
| 562 | /* |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 563 | * Semaphores. |
| 564 | */ |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 565 | struct radeon_semaphore { |
Jerome Glisse | a8c0594 | 2012-05-09 15:34:57 +0200 | [diff] [blame] | 566 | struct radeon_sa_bo *sa_bo; |
| 567 | signed waiters; |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 568 | uint64_t gpu_addr; |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 569 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 570 | }; |
| 571 | |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 572 | int radeon_semaphore_create(struct radeon_device *rdev, |
| 573 | struct radeon_semaphore **semaphore); |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 574 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 575 | struct radeon_semaphore *semaphore); |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 576 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 577 | struct radeon_semaphore *semaphore); |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 578 | void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, |
| 579 | struct radeon_fence *fence); |
Christian König | 8f676c4 | 2012-05-02 15:11:18 +0200 | [diff] [blame] | 580 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
| 581 | struct radeon_semaphore *semaphore, |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 582 | int waiting_ring); |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 583 | void radeon_semaphore_free(struct radeon_device *rdev, |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 584 | struct radeon_semaphore **semaphore, |
Jerome Glisse | a8c0594 | 2012-05-09 15:34:57 +0200 | [diff] [blame] | 585 | struct radeon_fence *fence); |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 586 | |
| 587 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 588 | * GART structures, functions & helpers |
| 589 | */ |
| 590 | struct radeon_mc; |
| 591 | |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 592 | #define RADEON_GPU_PAGE_SIZE 4096 |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 593 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 594 | #define RADEON_GPU_PAGE_SHIFT 12 |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 595 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 596 | |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 597 | #define RADEON_GART_PAGE_DUMMY 0 |
| 598 | #define RADEON_GART_PAGE_VALID (1 << 0) |
| 599 | #define RADEON_GART_PAGE_READ (1 << 1) |
| 600 | #define RADEON_GART_PAGE_WRITE (1 << 2) |
| 601 | #define RADEON_GART_PAGE_SNOOP (1 << 3) |
| 602 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 603 | struct radeon_gart { |
| 604 | dma_addr_t table_addr; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 605 | struct radeon_bo *robj; |
| 606 | void *ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 607 | unsigned num_gpu_pages; |
| 608 | unsigned num_cpu_pages; |
| 609 | unsigned table_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 610 | struct page **pages; |
| 611 | dma_addr_t *pages_addr; |
| 612 | bool ready; |
| 613 | }; |
| 614 | |
| 615 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 616 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 617 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 618 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 619 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
| 620 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 621 | int radeon_gart_init(struct radeon_device *rdev); |
| 622 | void radeon_gart_fini(struct radeon_device *rdev); |
| 623 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 624 | int pages); |
| 625 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 626 | int pages, struct page **pagelist, |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 627 | dma_addr_t *dma_addr, uint32_t flags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 628 | |
| 629 | |
| 630 | /* |
| 631 | * GPU MC structures, functions & helpers |
| 632 | */ |
| 633 | struct radeon_mc { |
| 634 | resource_size_t aper_size; |
| 635 | resource_size_t aper_base; |
| 636 | resource_size_t agp_base; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 637 | /* for some chips with <= 32MB we need to lie |
| 638 | * about vram size near mc fb location */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 639 | u64 mc_vram_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 640 | u64 visible_vram_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 641 | u64 gtt_size; |
| 642 | u64 gtt_start; |
| 643 | u64 gtt_end; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 644 | u64 vram_start; |
| 645 | u64 vram_end; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 646 | unsigned vram_width; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 647 | u64 real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 648 | int vram_mtrr; |
| 649 | bool vram_is_ddr; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 650 | bool igp_sideport_enabled; |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 651 | u64 gtt_base_align; |
Alex Deucher | 9ed8b1f | 2013-04-08 11:13:01 -0400 | [diff] [blame] | 652 | u64 mc_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 653 | }; |
| 654 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 655 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
| 656 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 657 | |
| 658 | /* |
| 659 | * GPU scratch registers structures, functions & helpers |
| 660 | */ |
| 661 | struct radeon_scratch { |
| 662 | unsigned num_reg; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 663 | uint32_t reg_base; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 664 | bool free[32]; |
| 665 | uint32_t reg[32]; |
| 666 | }; |
| 667 | |
| 668 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 669 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 670 | |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 671 | /* |
| 672 | * GPU doorbell structures, functions & helpers |
| 673 | */ |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 674 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
| 675 | |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 676 | struct radeon_doorbell { |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 677 | /* doorbell mmio */ |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 678 | resource_size_t base; |
| 679 | resource_size_t size; |
| 680 | u32 __iomem *ptr; |
| 681 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ |
| 682 | unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 683 | }; |
| 684 | |
| 685 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); |
| 686 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 687 | |
| 688 | /* |
| 689 | * IRQS. |
| 690 | */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 691 | |
Christian König | fa7f517 | 2014-06-03 18:13:21 -0400 | [diff] [blame] | 692 | struct radeon_flip_work { |
| 693 | struct work_struct flip_work; |
| 694 | struct work_struct unpin_work; |
| 695 | struct radeon_device *rdev; |
| 696 | int crtc_id; |
Michel Dänzer | c60381b | 2014-07-14 15:48:42 +0900 | [diff] [blame] | 697 | uint64_t base; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 698 | struct drm_pending_vblank_event *event; |
Christian König | fa7f517 | 2014-06-03 18:13:21 -0400 | [diff] [blame] | 699 | struct radeon_bo *old_rbo; |
Christian König | fa7f517 | 2014-06-03 18:13:21 -0400 | [diff] [blame] | 700 | struct radeon_fence *fence; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 701 | }; |
| 702 | |
| 703 | struct r500_irq_stat_regs { |
| 704 | u32 disp_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 705 | u32 hdmi0_status; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 706 | }; |
| 707 | |
| 708 | struct r600_irq_stat_regs { |
| 709 | u32 disp_int; |
| 710 | u32 disp_int_cont; |
| 711 | u32 disp_int_cont2; |
| 712 | u32 d1grph_int; |
| 713 | u32 d2grph_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 714 | u32 hdmi0_status; |
| 715 | u32 hdmi1_status; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 716 | }; |
| 717 | |
| 718 | struct evergreen_irq_stat_regs { |
| 719 | u32 disp_int; |
| 720 | u32 disp_int_cont; |
| 721 | u32 disp_int_cont2; |
| 722 | u32 disp_int_cont3; |
| 723 | u32 disp_int_cont4; |
| 724 | u32 disp_int_cont5; |
| 725 | u32 d1grph_int; |
| 726 | u32 d2grph_int; |
| 727 | u32 d3grph_int; |
| 728 | u32 d4grph_int; |
| 729 | u32 d5grph_int; |
| 730 | u32 d6grph_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 731 | u32 afmt_status1; |
| 732 | u32 afmt_status2; |
| 733 | u32 afmt_status3; |
| 734 | u32 afmt_status4; |
| 735 | u32 afmt_status5; |
| 736 | u32 afmt_status6; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 737 | }; |
| 738 | |
Alex Deucher | a59781b | 2012-11-09 10:45:57 -0500 | [diff] [blame] | 739 | struct cik_irq_stat_regs { |
| 740 | u32 disp_int; |
| 741 | u32 disp_int_cont; |
| 742 | u32 disp_int_cont2; |
| 743 | u32 disp_int_cont3; |
| 744 | u32 disp_int_cont4; |
| 745 | u32 disp_int_cont5; |
| 746 | u32 disp_int_cont6; |
Christian König | f5d636d | 2014-04-23 20:46:06 +0200 | [diff] [blame] | 747 | u32 d1grph_int; |
| 748 | u32 d2grph_int; |
| 749 | u32 d3grph_int; |
| 750 | u32 d4grph_int; |
| 751 | u32 d5grph_int; |
| 752 | u32 d6grph_int; |
Alex Deucher | a59781b | 2012-11-09 10:45:57 -0500 | [diff] [blame] | 753 | }; |
| 754 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 755 | union radeon_irq_stat_regs { |
| 756 | struct r500_irq_stat_regs r500; |
| 757 | struct r600_irq_stat_regs r600; |
| 758 | struct evergreen_irq_stat_regs evergreen; |
Alex Deucher | a59781b | 2012-11-09 10:45:57 -0500 | [diff] [blame] | 759 | struct cik_irq_stat_regs cik; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 760 | }; |
| 761 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 762 | struct radeon_irq { |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 763 | bool installed; |
| 764 | spinlock_t lock; |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 765 | atomic_t ring_int[RADEON_NUM_RINGS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 766 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 767 | atomic_t pflip[RADEON_MAX_CRTCS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 768 | wait_queue_head_t vblank_queue; |
| 769 | bool hpd[RADEON_MAX_HPD_PINS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 770 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
| 771 | union radeon_irq_stat_regs stat_regs; |
Alex Deucher | 4a6369e | 2013-04-12 14:04:10 -0400 | [diff] [blame] | 772 | bool dpm_thermal; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 773 | }; |
| 774 | |
| 775 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 776 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 777 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
| 778 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 779 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
| 780 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 781 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
| 782 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
| 783 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
| 784 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 785 | |
| 786 | /* |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 787 | * CP & rings. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 788 | */ |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 789 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 790 | struct radeon_ib { |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 791 | struct radeon_sa_bo *sa_bo; |
| 792 | uint32_t length_dw; |
| 793 | uint64_t gpu_addr; |
| 794 | uint32_t *ptr; |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 795 | int ring; |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 796 | struct radeon_fence *fence; |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 797 | struct radeon_vm *vm; |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 798 | bool is_const_ib; |
| 799 | struct radeon_semaphore *semaphore; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 800 | }; |
| 801 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 802 | struct radeon_ring { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 803 | struct radeon_bo *ring_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 804 | volatile uint32_t *ring; |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 805 | unsigned rptr_offs; |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 806 | unsigned rptr_save_reg; |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 807 | u64 next_rptr_gpu_addr; |
| 808 | volatile u32 *next_rptr_cpu_addr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 809 | unsigned wptr; |
| 810 | unsigned wptr_old; |
| 811 | unsigned ring_size; |
| 812 | unsigned ring_free_dw; |
| 813 | int count_dw; |
Christian König | aee4aa7 | 2014-02-18 15:24:06 +0100 | [diff] [blame] | 814 | atomic_t last_rptr; |
| 815 | atomic64_t last_activity; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 816 | uint64_t gpu_addr; |
| 817 | uint32_t align_mask; |
| 818 | uint32_t ptr_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 819 | bool ready; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 820 | u32 nop; |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 821 | u32 idx; |
Jerome Glisse | 5f0839c | 2013-01-11 15:19:43 -0500 | [diff] [blame] | 822 | u64 last_semaphore_signal_addr; |
| 823 | u64 last_semaphore_wait_addr; |
Alex Deucher | 963e81f | 2013-06-26 17:37:11 -0400 | [diff] [blame] | 824 | /* for CIK queues */ |
| 825 | u32 me; |
| 826 | u32 pipe; |
| 827 | u32 queue; |
| 828 | struct radeon_bo *mqd_obj; |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 829 | u32 doorbell_index; |
Alex Deucher | 963e81f | 2013-06-26 17:37:11 -0400 | [diff] [blame] | 830 | unsigned wptr_offs; |
| 831 | }; |
| 832 | |
| 833 | struct radeon_mec { |
| 834 | struct radeon_bo *hpd_eop_obj; |
| 835 | u64 hpd_eop_gpu_addr; |
| 836 | u32 num_pipe; |
| 837 | u32 num_mec; |
| 838 | u32 num_queue; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 839 | }; |
| 840 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 841 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 842 | * VM |
| 843 | */ |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 844 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 845 | /* maximum number of VMIDs */ |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 846 | #define RADEON_NUM_VM 16 |
| 847 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 848 | /* number of entries in page table */ |
Christian König | 4510fb9 | 2014-06-05 23:56:50 -0400 | [diff] [blame] | 849 | #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 850 | |
Alex Deucher | 1c01103 | 2013-07-12 15:56:02 -0400 | [diff] [blame] | 851 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
| 852 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 |
| 853 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) |
| 854 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) |
| 855 | |
Christian König | 24c1643 | 2013-10-30 11:51:09 -0400 | [diff] [blame] | 856 | #define R600_PTE_VALID (1 << 0) |
| 857 | #define R600_PTE_SYSTEM (1 << 1) |
| 858 | #define R600_PTE_SNOOPED (1 << 2) |
| 859 | #define R600_PTE_READABLE (1 << 5) |
| 860 | #define R600_PTE_WRITEABLE (1 << 6) |
| 861 | |
Christian König | ec3dbbc | 2014-05-10 12:17:55 +0200 | [diff] [blame] | 862 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
| 863 | #define R600_PTE_FRAG_4KB (0 << 7) |
| 864 | #define R600_PTE_FRAG_64KB (4 << 7) |
| 865 | #define R600_PTE_FRAG_256KB (6 << 7) |
| 866 | |
Christian König | 33fa9fe | 2014-07-22 17:42:20 +0200 | [diff] [blame] | 867 | /* flags needed to be set so we can copy directly from the GART table */ |
| 868 | #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ |
| 869 | R600_PTE_SYSTEM | R600_PTE_VALID ) |
Christian König | 0e97703 | 2014-05-27 16:47:37 +0200 | [diff] [blame] | 870 | |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 871 | struct radeon_vm_pt { |
| 872 | struct radeon_bo *bo; |
| 873 | uint64_t addr; |
| 874 | }; |
| 875 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 876 | struct radeon_vm { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 877 | struct list_head va; |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 878 | unsigned id; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 879 | |
Christian König | 036bf46 | 2014-07-18 08:56:40 +0200 | [diff] [blame] | 880 | /* BOs freed, but not yet updated in the PT */ |
| 881 | struct list_head freed; |
| 882 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 883 | /* contains the page directory */ |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 884 | struct radeon_bo *page_directory; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 885 | uint64_t pd_gpu_addr; |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 886 | unsigned max_pde_used; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 887 | |
| 888 | /* array of page tables, one for each page directory entry */ |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 889 | struct radeon_vm_pt *page_tables; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 890 | |
Christian König | cc9e67e | 2014-07-18 13:48:10 +0200 | [diff] [blame] | 891 | struct radeon_bo_va *ib_bo_va; |
| 892 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 893 | struct mutex mutex; |
| 894 | /* last fence for cs using this vm */ |
| 895 | struct radeon_fence *fence; |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 896 | /* last flush or NULL if we still need to flush */ |
| 897 | struct radeon_fence *last_flush; |
Christian König | 593b263 | 2014-01-23 14:24:15 +0100 | [diff] [blame] | 898 | /* last use of vmid */ |
| 899 | struct radeon_fence *last_id_use; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 900 | }; |
| 901 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 902 | struct radeon_vm_manager { |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 903 | struct radeon_fence *active[RADEON_NUM_VM]; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 904 | uint32_t max_pfn; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 905 | /* number of VMIDs */ |
| 906 | unsigned nvm; |
| 907 | /* vram base address for page table entry */ |
| 908 | u64 vram_base_offset; |
Alex Deucher | 67e915e | 2012-01-06 09:38:15 -0500 | [diff] [blame] | 909 | /* is vm enabled? */ |
| 910 | bool enabled; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 911 | }; |
| 912 | |
| 913 | /* |
| 914 | * file private structure |
| 915 | */ |
| 916 | struct radeon_fpriv { |
| 917 | struct radeon_vm vm; |
| 918 | }; |
| 919 | |
| 920 | /* |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 921 | * R6xx+ IH ring |
| 922 | */ |
| 923 | struct r600_ih { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 924 | struct radeon_bo *ring_obj; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 925 | volatile uint32_t *ring; |
| 926 | unsigned rptr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 927 | unsigned ring_size; |
| 928 | uint64_t gpu_addr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 929 | uint32_t ptr_mask; |
Christian Koenig | c20dc36 | 2012-05-16 21:45:24 +0200 | [diff] [blame] | 930 | atomic_t lock; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 931 | bool enabled; |
| 932 | }; |
| 933 | |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 934 | /* |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 935 | * RLC stuff |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 936 | */ |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 937 | #include "clearstate_defs.h" |
| 938 | |
| 939 | struct radeon_rlc { |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 940 | /* for power gating */ |
| 941 | struct radeon_bo *save_restore_obj; |
| 942 | uint64_t save_restore_gpu_addr; |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 943 | volatile uint32_t *sr_ptr; |
Alex Deucher | 1fd1177 | 2013-04-17 17:53:50 -0400 | [diff] [blame] | 944 | const u32 *reg_list; |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 945 | u32 reg_list_size; |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 946 | /* for clear state */ |
| 947 | struct radeon_bo *clear_state_obj; |
| 948 | uint64_t clear_state_gpu_addr; |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 949 | volatile uint32_t *cs_ptr; |
Alex Deucher | 1fd1177 | 2013-04-17 17:53:50 -0400 | [diff] [blame] | 950 | const struct cs_section_def *cs_data; |
Alex Deucher | 22c775c | 2013-07-23 09:41:05 -0400 | [diff] [blame] | 951 | u32 clear_state_size; |
| 952 | /* for cp tables */ |
| 953 | struct radeon_bo *cp_table_obj; |
| 954 | uint64_t cp_table_gpu_addr; |
| 955 | volatile uint32_t *cp_table_ptr; |
| 956 | u32 cp_table_size; |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 957 | }; |
| 958 | |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 959 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 960 | struct radeon_ib *ib, struct radeon_vm *vm, |
| 961 | unsigned size); |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 962 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 963 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
| 964 | struct radeon_ib *const_ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 965 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 966 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 967 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 968 | /* Ring access between begin & end cannot sleep */ |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 969 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
| 970 | struct radeon_ring *ring); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 971 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
| 972 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 973 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 974 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
| 975 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 976 | void radeon_ring_undo(struct radeon_ring *ring); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 977 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
| 978 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
Christian König | ff212f2 | 2014-02-18 14:52:33 +0100 | [diff] [blame] | 979 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
| 980 | struct radeon_ring *ring); |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 981 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 982 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
| 983 | uint32_t **data); |
| 984 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
| 985 | unsigned size, uint32_t *data); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 986 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
Alex Deucher | ea31bf6 | 2013-12-09 19:44:30 -0500 | [diff] [blame] | 987 | unsigned rptr_offs, u32 nop); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 988 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 989 | |
| 990 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 991 | /* r600 async dma */ |
| 992 | void r600_dma_stop(struct radeon_device *rdev); |
| 993 | int r600_dma_resume(struct radeon_device *rdev); |
| 994 | void r600_dma_fini(struct radeon_device *rdev); |
| 995 | |
Alex Deucher | 8c5fd7e | 2012-12-04 15:28:18 -0500 | [diff] [blame] | 996 | void cayman_dma_stop(struct radeon_device *rdev); |
| 997 | int cayman_dma_resume(struct radeon_device *rdev); |
| 998 | void cayman_dma_fini(struct radeon_device *rdev); |
| 999 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1000 | /* |
| 1001 | * CS. |
| 1002 | */ |
| 1003 | struct radeon_cs_reloc { |
| 1004 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1005 | struct radeon_bo *robj; |
Christian König | df0af44 | 2014-03-03 12:38:08 +0100 | [diff] [blame] | 1006 | struct ttm_validate_buffer tv; |
| 1007 | uint64_t gpu_offset; |
Christian König | ce6758c | 2014-06-02 17:33:07 +0200 | [diff] [blame] | 1008 | unsigned prefered_domains; |
| 1009 | unsigned allowed_domains; |
Christian König | df0af44 | 2014-03-03 12:38:08 +0100 | [diff] [blame] | 1010 | uint32_t tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1011 | uint32_t handle; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1012 | }; |
| 1013 | |
| 1014 | struct radeon_cs_chunk { |
| 1015 | uint32_t chunk_id; |
| 1016 | uint32_t length_dw; |
| 1017 | uint32_t *kdata; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1018 | void __user *user_ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1019 | }; |
| 1020 | |
| 1021 | struct radeon_cs_parser { |
Jerome Glisse | c8c15ff | 2010-01-18 13:01:36 +0100 | [diff] [blame] | 1022 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1023 | struct radeon_device *rdev; |
| 1024 | struct drm_file *filp; |
| 1025 | /* chunks */ |
| 1026 | unsigned nchunks; |
| 1027 | struct radeon_cs_chunk *chunks; |
| 1028 | uint64_t *chunks_array; |
| 1029 | /* IB */ |
| 1030 | unsigned idx; |
| 1031 | /* relocations */ |
| 1032 | unsigned nrelocs; |
| 1033 | struct radeon_cs_reloc *relocs; |
| 1034 | struct radeon_cs_reloc **relocs_ptr; |
Christian König | df0af44 | 2014-03-03 12:38:08 +0100 | [diff] [blame] | 1035 | struct radeon_cs_reloc *vm_bos; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1036 | struct list_head validated; |
Alex Deucher | cf4ccd0 | 2011-11-18 10:19:47 -0500 | [diff] [blame] | 1037 | unsigned dma_reloc_idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1038 | /* indices of various chunks */ |
| 1039 | int chunk_ib_idx; |
| 1040 | int chunk_relocs_idx; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1041 | int chunk_flags_idx; |
Alex Deucher | dfcf5f3 | 2012-03-20 17:18:14 -0400 | [diff] [blame] | 1042 | int chunk_const_ib_idx; |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 1043 | struct radeon_ib ib; |
| 1044 | struct radeon_ib const_ib; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1045 | void *track; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1046 | unsigned family; |
Marek Olšák | e70f224 | 2011-10-25 01:38:45 +0200 | [diff] [blame] | 1047 | int parser_error; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1048 | u32 cs_flags; |
| 1049 | u32 ring; |
| 1050 | s32 priority; |
Maarten Lankhorst | ecff665 | 2013-06-27 13:48:17 +0200 | [diff] [blame] | 1051 | struct ww_acquire_ctx ticket; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1052 | }; |
| 1053 | |
Maarten Lankhorst | 28a326c | 2013-10-09 14:36:57 +0200 | [diff] [blame] | 1054 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
| 1055 | { |
| 1056 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
| 1057 | |
| 1058 | if (ibc->kdata) |
| 1059 | return ibc->kdata[idx]; |
| 1060 | return p->ib.ptr[idx]; |
| 1061 | } |
| 1062 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1063 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1064 | struct radeon_cs_packet { |
| 1065 | unsigned idx; |
| 1066 | unsigned type; |
| 1067 | unsigned reg; |
| 1068 | unsigned opcode; |
| 1069 | int count; |
| 1070 | unsigned one_reg_wr; |
| 1071 | }; |
| 1072 | |
| 1073 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 1074 | struct radeon_cs_packet *pkt, |
| 1075 | unsigned idx, unsigned reg); |
| 1076 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 1077 | struct radeon_cs_packet *pkt); |
| 1078 | |
| 1079 | |
| 1080 | /* |
| 1081 | * AGP |
| 1082 | */ |
| 1083 | int radeon_agp_init(struct radeon_device *rdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 1084 | void radeon_agp_resume(struct radeon_device *rdev); |
Jerome Glisse | 10b0612 | 2010-05-21 18:48:54 +0200 | [diff] [blame] | 1085 | void radeon_agp_suspend(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1086 | void radeon_agp_fini(struct radeon_device *rdev); |
| 1087 | |
| 1088 | |
| 1089 | /* |
| 1090 | * Writeback |
| 1091 | */ |
| 1092 | struct radeon_wb { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1093 | struct radeon_bo *wb_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1094 | volatile uint32_t *wb; |
| 1095 | uint64_t gpu_addr; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1096 | bool enabled; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 1097 | bool use_event; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1098 | }; |
| 1099 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1100 | #define RADEON_WB_SCRATCH_OFFSET 0 |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 1101 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1102 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
Alex Deucher | 0c88a02 | 2011-03-02 20:07:31 -0500 | [diff] [blame] | 1103 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
| 1104 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1105 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1106 | #define R600_WB_IH_WPTR_OFFSET 2048 |
Alex Deucher | f60cbd1 | 2012-12-04 15:27:33 -0500 | [diff] [blame] | 1107 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 1108 | #define R600_WB_EVENT_OFFSET 3072 |
Alex Deucher | 963e81f | 2013-06-26 17:37:11 -0400 | [diff] [blame] | 1109 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
| 1110 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1111 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1112 | /** |
| 1113 | * struct radeon_pm - power management datas |
| 1114 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
| 1115 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
| 1116 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
| 1117 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
| 1118 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
| 1119 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
| 1120 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
| 1121 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
| 1122 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1123 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1124 | * @needed_bandwidth: current bandwidth needs |
| 1125 | * |
| 1126 | * It keeps track of various data needed to take powermanagement decision. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1127 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1128 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
| 1129 | * (type of memory, bus size, efficiency, ...) |
| 1130 | */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1131 | |
| 1132 | enum radeon_pm_method { |
| 1133 | PM_METHOD_PROFILE, |
| 1134 | PM_METHOD_DYNPM, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1135 | PM_METHOD_DPM, |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1136 | }; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1137 | |
| 1138 | enum radeon_dynpm_state { |
| 1139 | DYNPM_STATE_DISABLED, |
| 1140 | DYNPM_STATE_MINIMUM, |
| 1141 | DYNPM_STATE_PAUSED, |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 1142 | DYNPM_STATE_ACTIVE, |
| 1143 | DYNPM_STATE_SUSPENDED, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1144 | }; |
| 1145 | enum radeon_dynpm_action { |
| 1146 | DYNPM_ACTION_NONE, |
| 1147 | DYNPM_ACTION_MINIMUM, |
| 1148 | DYNPM_ACTION_DOWNCLOCK, |
| 1149 | DYNPM_ACTION_UPCLOCK, |
| 1150 | DYNPM_ACTION_DEFAULT |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1151 | }; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1152 | |
| 1153 | enum radeon_voltage_type { |
| 1154 | VOLTAGE_NONE = 0, |
| 1155 | VOLTAGE_GPIO, |
| 1156 | VOLTAGE_VDDC, |
| 1157 | VOLTAGE_SW |
| 1158 | }; |
| 1159 | |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1160 | enum radeon_pm_state_type { |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1161 | /* not used for dpm */ |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1162 | POWER_STATE_TYPE_DEFAULT, |
| 1163 | POWER_STATE_TYPE_POWERSAVE, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1164 | /* user selectable states */ |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1165 | POWER_STATE_TYPE_BATTERY, |
| 1166 | POWER_STATE_TYPE_BALANCED, |
| 1167 | POWER_STATE_TYPE_PERFORMANCE, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1168 | /* internal states */ |
| 1169 | POWER_STATE_TYPE_INTERNAL_UVD, |
| 1170 | POWER_STATE_TYPE_INTERNAL_UVD_SD, |
| 1171 | POWER_STATE_TYPE_INTERNAL_UVD_HD, |
| 1172 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, |
| 1173 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, |
| 1174 | POWER_STATE_TYPE_INTERNAL_BOOT, |
| 1175 | POWER_STATE_TYPE_INTERNAL_THERMAL, |
| 1176 | POWER_STATE_TYPE_INTERNAL_ACPI, |
| 1177 | POWER_STATE_TYPE_INTERNAL_ULV, |
Alex Deucher | edcaa5b | 2013-07-05 11:48:31 -0400 | [diff] [blame] | 1178 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1179 | }; |
| 1180 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1181 | enum radeon_pm_profile_type { |
| 1182 | PM_PROFILE_DEFAULT, |
| 1183 | PM_PROFILE_AUTO, |
| 1184 | PM_PROFILE_LOW, |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 1185 | PM_PROFILE_MID, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1186 | PM_PROFILE_HIGH, |
| 1187 | }; |
| 1188 | |
| 1189 | #define PM_PROFILE_DEFAULT_IDX 0 |
| 1190 | #define PM_PROFILE_LOW_SH_IDX 1 |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 1191 | #define PM_PROFILE_MID_SH_IDX 2 |
| 1192 | #define PM_PROFILE_HIGH_SH_IDX 3 |
| 1193 | #define PM_PROFILE_LOW_MH_IDX 4 |
| 1194 | #define PM_PROFILE_MID_MH_IDX 5 |
| 1195 | #define PM_PROFILE_HIGH_MH_IDX 6 |
| 1196 | #define PM_PROFILE_MAX 7 |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1197 | |
| 1198 | struct radeon_pm_profile { |
| 1199 | int dpms_off_ps_idx; |
| 1200 | int dpms_on_ps_idx; |
| 1201 | int dpms_off_cm_idx; |
| 1202 | int dpms_on_cm_idx; |
Alex Deucher | 516d0e4 | 2009-12-23 14:28:05 -0500 | [diff] [blame] | 1203 | }; |
| 1204 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1205 | enum radeon_int_thermal_type { |
| 1206 | THERMAL_TYPE_NONE, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1207 | THERMAL_TYPE_EXTERNAL, |
| 1208 | THERMAL_TYPE_EXTERNAL_GPIO, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1209 | THERMAL_TYPE_RV6XX, |
| 1210 | THERMAL_TYPE_RV770, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1211 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1212 | THERMAL_TYPE_EVERGREEN, |
Alex Deucher | e33df25 | 2010-11-22 17:56:32 -0500 | [diff] [blame] | 1213 | THERMAL_TYPE_SUMO, |
Alex Deucher | 4fddba1 | 2011-01-06 21:19:22 -0500 | [diff] [blame] | 1214 | THERMAL_TYPE_NI, |
Alex Deucher | 14607d0 | 2012-03-20 17:18:09 -0400 | [diff] [blame] | 1215 | THERMAL_TYPE_SI, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1216 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
Alex Deucher | 5115020 | 2012-12-18 22:07:14 -0500 | [diff] [blame] | 1217 | THERMAL_TYPE_CI, |
Alex Deucher | 16fbe00 | 2013-04-22 21:41:26 -0400 | [diff] [blame] | 1218 | THERMAL_TYPE_KV, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1219 | }; |
| 1220 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1221 | struct radeon_voltage { |
| 1222 | enum radeon_voltage_type type; |
| 1223 | /* gpio voltage */ |
| 1224 | struct radeon_gpio_rec gpio; |
| 1225 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
| 1226 | bool active_high; /* voltage drop is active when bit is high */ |
| 1227 | /* VDDC voltage */ |
| 1228 | u8 vddc_id; /* index into vddc voltage table */ |
| 1229 | u8 vddci_id; /* index into vddci voltage table */ |
| 1230 | bool vddci_enabled; |
| 1231 | /* r6xx+ sw */ |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1232 | u16 voltage; |
| 1233 | /* evergreen+ vddci */ |
| 1234 | u16 vddci; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1235 | }; |
| 1236 | |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1237 | /* clock mode flags */ |
| 1238 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
| 1239 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1240 | struct radeon_pm_clock_info { |
| 1241 | /* memory clock */ |
| 1242 | u32 mclk; |
| 1243 | /* engine clock */ |
| 1244 | u32 sclk; |
| 1245 | /* voltage info */ |
| 1246 | struct radeon_voltage voltage; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1247 | /* standardized clock flags */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1248 | u32 flags; |
| 1249 | }; |
| 1250 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1251 | /* state flags */ |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1252 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1253 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1254 | struct radeon_power_state { |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1255 | enum radeon_pm_state_type type; |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 1256 | struct radeon_pm_clock_info *clock_info; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1257 | /* number of valid clock modes in this power state */ |
| 1258 | int num_clock_modes; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1259 | struct radeon_pm_clock_info *default_clock_mode; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1260 | /* standardized state flags */ |
| 1261 | u32 flags; |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 1262 | u32 misc; /* vbios specific flags */ |
| 1263 | u32 misc2; /* vbios specific flags */ |
| 1264 | int pcie_lanes; /* pcie lanes */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1265 | }; |
| 1266 | |
Rafał Miłecki | 2745932 | 2010-02-11 22:16:36 +0000 | [diff] [blame] | 1267 | /* |
| 1268 | * Some modes are overclocked by very low value, accept them |
| 1269 | */ |
| 1270 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
| 1271 | |
Alex Deucher | 2e9d4c0 | 2013-04-12 13:58:03 -0400 | [diff] [blame] | 1272 | enum radeon_dpm_auto_throttle_src { |
| 1273 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, |
| 1274 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL |
| 1275 | }; |
| 1276 | |
| 1277 | enum radeon_dpm_event_src { |
| 1278 | RADEON_DPM_EVENT_SRC_ANALOG = 0, |
| 1279 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, |
| 1280 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, |
| 1281 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, |
| 1282 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 |
| 1283 | }; |
| 1284 | |
Alex Deucher | 58bd2a8 | 2013-09-04 16:13:56 -0400 | [diff] [blame] | 1285 | #define RADEON_MAX_VCE_LEVELS 6 |
| 1286 | |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1287 | enum radeon_vce_level { |
| 1288 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
| 1289 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
| 1290 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
| 1291 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
| 1292 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
| 1293 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
| 1294 | }; |
| 1295 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1296 | struct radeon_ps { |
| 1297 | u32 caps; /* vbios flags */ |
| 1298 | u32 class; /* vbios flags */ |
| 1299 | u32 class2; /* vbios flags */ |
| 1300 | /* UVD clocks */ |
| 1301 | u32 vclk; |
| 1302 | u32 dclk; |
Alex Deucher | c4453e6 | 2013-05-15 15:53:57 -0400 | [diff] [blame] | 1303 | /* VCE clocks */ |
| 1304 | u32 evclk; |
| 1305 | u32 ecclk; |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1306 | bool vce_active; |
| 1307 | enum radeon_vce_level vce_level; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1308 | /* asic priv */ |
| 1309 | void *ps_priv; |
| 1310 | }; |
| 1311 | |
| 1312 | struct radeon_dpm_thermal { |
| 1313 | /* thermal interrupt work */ |
| 1314 | struct work_struct work; |
| 1315 | /* low temperature threshold */ |
| 1316 | int min_temp; |
| 1317 | /* high temperature threshold */ |
| 1318 | int max_temp; |
| 1319 | /* was interrupt low to high or high to low */ |
| 1320 | bool high_to_low; |
| 1321 | }; |
| 1322 | |
Alex Deucher | d22b7e4 | 2012-11-29 19:27:56 -0500 | [diff] [blame] | 1323 | enum radeon_clk_action |
| 1324 | { |
| 1325 | RADEON_SCLK_UP = 1, |
| 1326 | RADEON_SCLK_DOWN |
| 1327 | }; |
| 1328 | |
| 1329 | struct radeon_blacklist_clocks |
| 1330 | { |
| 1331 | u32 sclk; |
| 1332 | u32 mclk; |
| 1333 | enum radeon_clk_action action; |
| 1334 | }; |
| 1335 | |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1336 | struct radeon_clock_and_voltage_limits { |
| 1337 | u32 sclk; |
| 1338 | u32 mclk; |
Alex Deucher | cdf6e80 | 2013-10-23 16:13:42 -0400 | [diff] [blame] | 1339 | u16 vddc; |
| 1340 | u16 vddci; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1341 | }; |
| 1342 | |
| 1343 | struct radeon_clock_array { |
| 1344 | u32 count; |
| 1345 | u32 *values; |
| 1346 | }; |
| 1347 | |
| 1348 | struct radeon_clock_voltage_dependency_entry { |
| 1349 | u32 clk; |
| 1350 | u16 v; |
| 1351 | }; |
| 1352 | |
| 1353 | struct radeon_clock_voltage_dependency_table { |
| 1354 | u32 count; |
| 1355 | struct radeon_clock_voltage_dependency_entry *entries; |
| 1356 | }; |
| 1357 | |
Alex Deucher | ef976ec | 2013-05-06 11:31:04 -0400 | [diff] [blame] | 1358 | union radeon_cac_leakage_entry { |
| 1359 | struct { |
| 1360 | u16 vddc; |
| 1361 | u32 leakage; |
| 1362 | }; |
| 1363 | struct { |
| 1364 | u16 vddc1; |
| 1365 | u16 vddc2; |
| 1366 | u16 vddc3; |
| 1367 | }; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1368 | }; |
| 1369 | |
| 1370 | struct radeon_cac_leakage_table { |
| 1371 | u32 count; |
Alex Deucher | ef976ec | 2013-05-06 11:31:04 -0400 | [diff] [blame] | 1372 | union radeon_cac_leakage_entry *entries; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1373 | }; |
| 1374 | |
Alex Deucher | 929ee7a | 2013-03-20 12:30:25 -0400 | [diff] [blame] | 1375 | struct radeon_phase_shedding_limits_entry { |
| 1376 | u16 voltage; |
| 1377 | u32 sclk; |
| 1378 | u32 mclk; |
| 1379 | }; |
| 1380 | |
| 1381 | struct radeon_phase_shedding_limits_table { |
| 1382 | u32 count; |
| 1383 | struct radeon_phase_shedding_limits_entry *entries; |
| 1384 | }; |
| 1385 | |
Alex Deucher | 84a9d9e | 2013-04-19 19:11:37 -0400 | [diff] [blame] | 1386 | struct radeon_uvd_clock_voltage_dependency_entry { |
| 1387 | u32 vclk; |
| 1388 | u32 dclk; |
| 1389 | u16 v; |
| 1390 | }; |
| 1391 | |
| 1392 | struct radeon_uvd_clock_voltage_dependency_table { |
| 1393 | u8 count; |
| 1394 | struct radeon_uvd_clock_voltage_dependency_entry *entries; |
| 1395 | }; |
| 1396 | |
Alex Deucher | d29f013 | 2013-05-09 16:37:28 -0400 | [diff] [blame] | 1397 | struct radeon_vce_clock_voltage_dependency_entry { |
| 1398 | u32 ecclk; |
| 1399 | u32 evclk; |
| 1400 | u16 v; |
| 1401 | }; |
| 1402 | |
| 1403 | struct radeon_vce_clock_voltage_dependency_table { |
| 1404 | u8 count; |
| 1405 | struct radeon_vce_clock_voltage_dependency_entry *entries; |
| 1406 | }; |
| 1407 | |
Alex Deucher | a5cb318 | 2013-03-20 13:00:18 -0400 | [diff] [blame] | 1408 | struct radeon_ppm_table { |
| 1409 | u8 ppm_design; |
| 1410 | u16 cpu_core_number; |
| 1411 | u32 platform_tdp; |
| 1412 | u32 small_ac_platform_tdp; |
| 1413 | u32 platform_tdc; |
| 1414 | u32 small_ac_platform_tdc; |
| 1415 | u32 apu_tdp; |
| 1416 | u32 dgpu_tdp; |
| 1417 | u32 dgpu_ulv_power; |
| 1418 | u32 tj_max; |
| 1419 | }; |
| 1420 | |
Alex Deucher | 58cb763 | 2013-05-06 12:15:33 -0400 | [diff] [blame] | 1421 | struct radeon_cac_tdp_table { |
| 1422 | u16 tdp; |
| 1423 | u16 configurable_tdp; |
| 1424 | u16 tdc; |
| 1425 | u16 battery_power_limit; |
| 1426 | u16 small_power_limit; |
| 1427 | u16 low_cac_leakage; |
| 1428 | u16 high_cac_leakage; |
| 1429 | u16 maximum_power_delivery_limit; |
| 1430 | }; |
| 1431 | |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1432 | struct radeon_dpm_dynamic_state { |
| 1433 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; |
| 1434 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; |
| 1435 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; |
Alex Deucher | dd621a2 | 2013-05-06 14:37:56 -0400 | [diff] [blame] | 1436 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
Alex Deucher | 4489cd62 | 2013-03-22 15:59:10 -0400 | [diff] [blame] | 1437 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
Alex Deucher | 84a9d9e | 2013-04-19 19:11:37 -0400 | [diff] [blame] | 1438 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
Alex Deucher | d29f013 | 2013-05-09 16:37:28 -0400 | [diff] [blame] | 1439 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
Alex Deucher | 94a914f | 2013-05-09 16:42:33 -0400 | [diff] [blame] | 1440 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
| 1441 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1442 | struct radeon_clock_array valid_sclk_values; |
| 1443 | struct radeon_clock_array valid_mclk_values; |
| 1444 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; |
| 1445 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; |
| 1446 | u32 mclk_sclk_ratio; |
| 1447 | u32 sclk_mclk_delta; |
| 1448 | u16 vddc_vddci_delta; |
| 1449 | u16 min_vddc_for_pcie_gen2; |
| 1450 | struct radeon_cac_leakage_table cac_leakage_table; |
Alex Deucher | 929ee7a | 2013-03-20 12:30:25 -0400 | [diff] [blame] | 1451 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
Alex Deucher | a5cb318 | 2013-03-20 13:00:18 -0400 | [diff] [blame] | 1452 | struct radeon_ppm_table *ppm_table; |
Alex Deucher | 58cb763 | 2013-05-06 12:15:33 -0400 | [diff] [blame] | 1453 | struct radeon_cac_tdp_table *cac_tdp_table; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1454 | }; |
| 1455 | |
| 1456 | struct radeon_dpm_fan { |
| 1457 | u16 t_min; |
| 1458 | u16 t_med; |
| 1459 | u16 t_high; |
| 1460 | u16 pwm_min; |
| 1461 | u16 pwm_med; |
| 1462 | u16 pwm_high; |
| 1463 | u8 t_hyst; |
| 1464 | u32 cycle_delay; |
| 1465 | u16 t_max; |
| 1466 | bool ucode_fan_control; |
| 1467 | }; |
| 1468 | |
Alex Deucher | 32ce465 | 2013-03-18 17:03:01 -0400 | [diff] [blame] | 1469 | enum radeon_pcie_gen { |
| 1470 | RADEON_PCIE_GEN1 = 0, |
| 1471 | RADEON_PCIE_GEN2 = 1, |
| 1472 | RADEON_PCIE_GEN3 = 2, |
| 1473 | RADEON_PCIE_GEN_INVALID = 0xffff |
| 1474 | }; |
| 1475 | |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 1476 | enum radeon_dpm_forced_level { |
| 1477 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, |
| 1478 | RADEON_DPM_FORCED_LEVEL_LOW = 1, |
| 1479 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, |
| 1480 | }; |
| 1481 | |
Alex Deucher | 58bd2a8 | 2013-09-04 16:13:56 -0400 | [diff] [blame] | 1482 | struct radeon_vce_state { |
| 1483 | /* vce clocks */ |
| 1484 | u32 evclk; |
| 1485 | u32 ecclk; |
| 1486 | /* gpu clocks */ |
| 1487 | u32 sclk; |
| 1488 | u32 mclk; |
| 1489 | u8 clk_idx; |
| 1490 | u8 pstate; |
| 1491 | }; |
| 1492 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1493 | struct radeon_dpm { |
| 1494 | struct radeon_ps *ps; |
| 1495 | /* number of valid power states */ |
| 1496 | int num_ps; |
| 1497 | /* current power state that is active */ |
| 1498 | struct radeon_ps *current_ps; |
| 1499 | /* requested power state */ |
| 1500 | struct radeon_ps *requested_ps; |
| 1501 | /* boot up power state */ |
| 1502 | struct radeon_ps *boot_ps; |
| 1503 | /* default uvd power state */ |
| 1504 | struct radeon_ps *uvd_ps; |
Alex Deucher | 58bd2a8 | 2013-09-04 16:13:56 -0400 | [diff] [blame] | 1505 | /* vce requirements */ |
| 1506 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; |
| 1507 | enum radeon_vce_level vce_level; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1508 | enum radeon_pm_state_type state; |
| 1509 | enum radeon_pm_state_type user_state; |
| 1510 | u32 platform_caps; |
| 1511 | u32 voltage_response_time; |
| 1512 | u32 backbias_response_time; |
| 1513 | void *priv; |
| 1514 | u32 new_active_crtcs; |
| 1515 | int new_active_crtc_count; |
| 1516 | u32 current_active_crtcs; |
| 1517 | int current_active_crtc_count; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1518 | struct radeon_dpm_dynamic_state dyn_state; |
| 1519 | struct radeon_dpm_fan fan; |
| 1520 | u32 tdp_limit; |
| 1521 | u32 near_tdp_limit; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1522 | u32 near_tdp_limit_adjusted; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1523 | u32 sq_ramping_threshold; |
| 1524 | u32 cac_leakage; |
| 1525 | u16 tdp_od_limit; |
| 1526 | u32 tdp_adjustment; |
| 1527 | u16 load_line_slope; |
| 1528 | bool power_control; |
Alex Deucher | 5ca302f | 2012-11-30 10:56:57 -0500 | [diff] [blame] | 1529 | bool ac_power; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1530 | /* special states active */ |
| 1531 | bool thermal_active; |
Alex Deucher | 8a22755 | 2013-06-21 15:12:57 -0400 | [diff] [blame] | 1532 | bool uvd_active; |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1533 | bool vce_active; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1534 | /* thermal handling */ |
| 1535 | struct radeon_dpm_thermal thermal; |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 1536 | /* forced levels */ |
| 1537 | enum radeon_dpm_forced_level forced_level; |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1538 | /* track UVD streams */ |
| 1539 | unsigned sd; |
| 1540 | unsigned hd; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1541 | }; |
| 1542 | |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1543 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
Alex Deucher | 03afe6f | 2013-08-23 11:56:26 -0400 | [diff] [blame] | 1544 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1545 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1546 | struct radeon_pm { |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1547 | struct mutex mutex; |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 1548 | /* write locked while reprogramming mclk */ |
| 1549 | struct rw_semaphore mclk_lock; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1550 | u32 active_crtcs; |
| 1551 | int active_crtc_count; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1552 | int req_vblank; |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 1553 | bool vblank_sync; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1554 | fixed20_12 max_bandwidth; |
| 1555 | fixed20_12 igp_sideport_mclk; |
| 1556 | fixed20_12 igp_system_mclk; |
| 1557 | fixed20_12 igp_ht_link_clk; |
| 1558 | fixed20_12 igp_ht_link_width; |
| 1559 | fixed20_12 k8_bandwidth; |
| 1560 | fixed20_12 sideport_bandwidth; |
| 1561 | fixed20_12 ht_bandwidth; |
| 1562 | fixed20_12 core_bandwidth; |
| 1563 | fixed20_12 sclk; |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1564 | fixed20_12 mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1565 | fixed20_12 needed_bandwidth; |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 1566 | struct radeon_power_state *power_state; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1567 | /* number of valid power states */ |
| 1568 | int num_power_states; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1569 | int current_power_state_index; |
| 1570 | int current_clock_mode_index; |
| 1571 | int requested_power_state_index; |
| 1572 | int requested_clock_mode_index; |
| 1573 | int default_power_state_index; |
| 1574 | u32 current_sclk; |
| 1575 | u32 current_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1576 | u16 current_vddc; |
| 1577 | u16 current_vddci; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 1578 | u32 default_sclk; |
| 1579 | u32 default_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1580 | u16 default_vddc; |
| 1581 | u16 default_vddci; |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1582 | struct radeon_i2c_chan *i2c_bus; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1583 | /* selected pm method */ |
| 1584 | enum radeon_pm_method pm_method; |
| 1585 | /* dynpm power management */ |
| 1586 | struct delayed_work dynpm_idle_work; |
| 1587 | enum radeon_dynpm_state dynpm_state; |
| 1588 | enum radeon_dynpm_action dynpm_planned_action; |
| 1589 | unsigned long dynpm_action_timeout; |
| 1590 | bool dynpm_can_upclock; |
| 1591 | bool dynpm_can_downclock; |
| 1592 | /* profile-based power management */ |
| 1593 | enum radeon_pm_profile_type profile; |
| 1594 | int profile_index; |
| 1595 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1596 | /* internal thermal controller on rv6xx+ */ |
| 1597 | enum radeon_int_thermal_type int_thermal_type; |
| 1598 | struct device *int_hwmon_dev; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1599 | /* dpm */ |
| 1600 | bool dpm_enabled; |
| 1601 | struct radeon_dpm dpm; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1602 | }; |
| 1603 | |
Alex Deucher | a4c9e2e | 2011-11-04 10:09:41 -0400 | [diff] [blame] | 1604 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
| 1605 | enum radeon_pm_state_type ps_type, |
| 1606 | int instance); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1607 | /* |
| 1608 | * UVD |
| 1609 | */ |
| 1610 | #define RADEON_MAX_UVD_HANDLES 10 |
| 1611 | #define RADEON_UVD_STACK_SIZE (1024*1024) |
| 1612 | #define RADEON_UVD_HEAP_SIZE (1024*1024) |
| 1613 | |
| 1614 | struct radeon_uvd { |
| 1615 | struct radeon_bo *vcpu_bo; |
| 1616 | void *cpu_addr; |
| 1617 | uint64_t gpu_addr; |
Christian König | 9cc2e0e | 2013-07-12 10:18:09 -0400 | [diff] [blame] | 1618 | void *saved_bo; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1619 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
| 1620 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; |
Alex Deucher | 85a129c | 2013-08-05 12:41:20 -0400 | [diff] [blame] | 1621 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
Christian König | 55b51c8 | 2013-04-18 15:25:59 +0200 | [diff] [blame] | 1622 | struct delayed_work idle_work; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1623 | }; |
| 1624 | |
| 1625 | int radeon_uvd_init(struct radeon_device *rdev); |
| 1626 | void radeon_uvd_fini(struct radeon_device *rdev); |
| 1627 | int radeon_uvd_suspend(struct radeon_device *rdev); |
| 1628 | int radeon_uvd_resume(struct radeon_device *rdev); |
| 1629 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
| 1630 | uint32_t handle, struct radeon_fence **fence); |
| 1631 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
| 1632 | uint32_t handle, struct radeon_fence **fence); |
| 1633 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); |
| 1634 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
| 1635 | struct drm_file *filp); |
| 1636 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); |
Christian König | 55b51c8 | 2013-04-18 15:25:59 +0200 | [diff] [blame] | 1637 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 1638 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
| 1639 | unsigned vclk, unsigned dclk, |
| 1640 | unsigned vco_min, unsigned vco_max, |
| 1641 | unsigned fb_factor, unsigned fb_mask, |
| 1642 | unsigned pd_min, unsigned pd_max, |
| 1643 | unsigned pd_even, |
| 1644 | unsigned *optimal_fb_div, |
| 1645 | unsigned *optimal_vclk_div, |
| 1646 | unsigned *optimal_dclk_div); |
| 1647 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
| 1648 | unsigned cg_upll_func_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1649 | |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1650 | /* |
| 1651 | * VCE |
| 1652 | */ |
| 1653 | #define RADEON_MAX_VCE_HANDLES 16 |
| 1654 | #define RADEON_VCE_STACK_SIZE (1024*1024) |
| 1655 | #define RADEON_VCE_HEAP_SIZE (4*1024*1024) |
| 1656 | |
| 1657 | struct radeon_vce { |
| 1658 | struct radeon_bo *vcpu_bo; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1659 | uint64_t gpu_addr; |
Christian König | 98ccc29 | 2014-01-23 09:50:49 -0700 | [diff] [blame] | 1660 | unsigned fw_version; |
| 1661 | unsigned fb_version; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1662 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
| 1663 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; |
Leo Liu | 2fc5703 | 2014-05-05 15:42:18 -0400 | [diff] [blame] | 1664 | unsigned img_size[RADEON_MAX_VCE_HANDLES]; |
Alex Deucher | 03afe6f | 2013-08-23 11:56:26 -0400 | [diff] [blame] | 1665 | struct delayed_work idle_work; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1666 | }; |
| 1667 | |
| 1668 | int radeon_vce_init(struct radeon_device *rdev); |
| 1669 | void radeon_vce_fini(struct radeon_device *rdev); |
| 1670 | int radeon_vce_suspend(struct radeon_device *rdev); |
| 1671 | int radeon_vce_resume(struct radeon_device *rdev); |
| 1672 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, |
| 1673 | uint32_t handle, struct radeon_fence **fence); |
| 1674 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, |
| 1675 | uint32_t handle, struct radeon_fence **fence); |
| 1676 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); |
Alex Deucher | 03afe6f | 2013-08-23 11:56:26 -0400 | [diff] [blame] | 1677 | void radeon_vce_note_usage(struct radeon_device *rdev); |
Leo Liu | 2fc5703 | 2014-05-05 15:42:18 -0400 | [diff] [blame] | 1678 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1679 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); |
| 1680 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, |
| 1681 | struct radeon_ring *ring, |
| 1682 | struct radeon_semaphore *semaphore, |
| 1683 | bool emit_wait); |
| 1684 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 1685 | void radeon_vce_fence_emit(struct radeon_device *rdev, |
| 1686 | struct radeon_fence *fence); |
| 1687 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1688 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1689 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 1690 | struct r600_audio_pin { |
Rafał Miłecki | a92553a | 2012-04-28 23:35:20 +0200 | [diff] [blame] | 1691 | int channels; |
| 1692 | int rate; |
| 1693 | int bits_per_sample; |
| 1694 | u8 status_bits; |
| 1695 | u8 category_code; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 1696 | u32 offset; |
| 1697 | bool connected; |
| 1698 | u32 id; |
| 1699 | }; |
| 1700 | |
| 1701 | struct r600_audio { |
| 1702 | bool enabled; |
| 1703 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; |
| 1704 | int num_pins; |
Rafał Miłecki | a92553a | 2012-04-28 23:35:20 +0200 | [diff] [blame] | 1705 | }; |
| 1706 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1707 | /* |
| 1708 | * Benchmarking |
| 1709 | */ |
Ilija Hadzic | 638dd7d | 2011-10-12 23:29:39 -0400 | [diff] [blame] | 1710 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1711 | |
| 1712 | |
| 1713 | /* |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1714 | * Testing |
| 1715 | */ |
| 1716 | void radeon_test_moves(struct radeon_device *rdev); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1717 | void radeon_test_ring_sync(struct radeon_device *rdev, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1718 | struct radeon_ring *cpA, |
| 1719 | struct radeon_ring *cpB); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1720 | void radeon_test_syncing(struct radeon_device *rdev); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1721 | |
| 1722 | |
| 1723 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1724 | * Debugfs |
| 1725 | */ |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1726 | struct radeon_debugfs { |
| 1727 | struct drm_info_list *files; |
| 1728 | unsigned num_files; |
| 1729 | }; |
| 1730 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1731 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 1732 | struct drm_info_list *files, |
| 1733 | unsigned nfiles); |
| 1734 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1735 | |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 1736 | /* |
| 1737 | * ASIC ring specific functions. |
| 1738 | */ |
| 1739 | struct radeon_asic_ring { |
| 1740 | /* ring read/write ptr handling */ |
| 1741 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1742 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1743 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1744 | |
| 1745 | /* validating and patching of IBs */ |
| 1746 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
| 1747 | int (*cs_parse)(struct radeon_cs_parser *p); |
| 1748 | |
| 1749 | /* command emmit functions */ |
| 1750 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
| 1751 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
Michel Dänzer | 72a9987 | 2014-07-31 18:43:49 +0900 | [diff] [blame^] | 1752 | void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 1753 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 1754 | struct radeon_semaphore *semaphore, bool emit_wait); |
| 1755 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 1756 | |
| 1757 | /* testing functions */ |
| 1758 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1759 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1760 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1761 | |
| 1762 | /* deprecated */ |
| 1763 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1764 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1765 | |
| 1766 | /* |
| 1767 | * ASIC specific functions. |
| 1768 | */ |
| 1769 | struct radeon_asic { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1770 | int (*init)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1771 | void (*fini)(struct radeon_device *rdev); |
| 1772 | int (*resume)(struct radeon_device *rdev); |
| 1773 | int (*suspend)(struct radeon_device *rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1774 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1775 | int (*asic_reset)(struct radeon_device *rdev); |
Michel Dänzer | 124764f | 2014-07-31 18:43:48 +0900 | [diff] [blame] | 1776 | /* Flush the HDP cache via MMIO */ |
| 1777 | void (*mmio_hdp_flush)(struct radeon_device *rdev); |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1778 | /* check if 3D engine is idle */ |
| 1779 | bool (*gui_idle)(struct radeon_device *rdev); |
| 1780 | /* wait for mc_idle */ |
| 1781 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 1782 | /* get the reference clock */ |
| 1783 | u32 (*get_xclk)(struct radeon_device *rdev); |
Alex Deucher | d041889 | 2013-01-24 10:35:23 -0500 | [diff] [blame] | 1784 | /* get the gpu clock counter */ |
| 1785 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1786 | /* gart */ |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1787 | struct { |
| 1788 | void (*tlb_flush)(struct radeon_device *rdev); |
Christian König | 7f90fc9 | 2014-06-04 15:29:57 +0200 | [diff] [blame] | 1789 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 1790 | uint64_t addr, uint32_t flags); |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1791 | } gart; |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1792 | struct { |
| 1793 | int (*init)(struct radeon_device *rdev); |
| 1794 | void (*fini)(struct radeon_device *rdev); |
Alex Deucher | 43f1214 | 2013-02-01 17:32:42 +0100 | [diff] [blame] | 1795 | void (*set_page)(struct radeon_device *rdev, |
| 1796 | struct radeon_ib *ib, |
| 1797 | uint64_t pe, |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 1798 | uint64_t addr, unsigned count, |
| 1799 | uint32_t incr, uint32_t flags); |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1800 | } vm; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1801 | /* ring specific callbacks */ |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 1802 | struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1803 | /* irqs */ |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1804 | struct { |
| 1805 | int (*set)(struct radeon_device *rdev); |
| 1806 | int (*process)(struct radeon_device *rdev); |
| 1807 | } irq; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1808 | /* displays */ |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1809 | struct { |
| 1810 | /* display watermarks */ |
| 1811 | void (*bandwidth_update)(struct radeon_device *rdev); |
| 1812 | /* get frame count */ |
| 1813 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
| 1814 | /* wait for vblank */ |
| 1815 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1816 | /* set backlight level */ |
| 1817 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1818 | /* get backlight level */ |
| 1819 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 1820 | /* audio callbacks */ |
| 1821 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); |
| 1822 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1823 | } display; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1824 | /* copy functions for bo handling */ |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1825 | struct { |
| 1826 | int (*blit)(struct radeon_device *rdev, |
| 1827 | uint64_t src_offset, |
| 1828 | uint64_t dst_offset, |
| 1829 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1830 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1831 | u32 blit_ring_index; |
| 1832 | int (*dma)(struct radeon_device *rdev, |
| 1833 | uint64_t src_offset, |
| 1834 | uint64_t dst_offset, |
| 1835 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1836 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1837 | u32 dma_ring_index; |
| 1838 | /* method used for bo copy */ |
| 1839 | int (*copy)(struct radeon_device *rdev, |
| 1840 | uint64_t src_offset, |
| 1841 | uint64_t dst_offset, |
| 1842 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1843 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1844 | /* ring used for bo copies */ |
| 1845 | u32 copy_ring_index; |
| 1846 | } copy; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1847 | /* surfaces */ |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1848 | struct { |
| 1849 | int (*set_reg)(struct radeon_device *rdev, int reg, |
| 1850 | uint32_t tiling_flags, uint32_t pitch, |
| 1851 | uint32_t offset, uint32_t obj_size); |
| 1852 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
| 1853 | } surface; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1854 | /* hotplug detect */ |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1855 | struct { |
| 1856 | void (*init)(struct radeon_device *rdev); |
| 1857 | void (*fini)(struct radeon_device *rdev); |
| 1858 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 1859 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 1860 | } hpd; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1861 | /* static power management */ |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1862 | struct { |
| 1863 | void (*misc)(struct radeon_device *rdev); |
| 1864 | void (*prepare)(struct radeon_device *rdev); |
| 1865 | void (*finish)(struct radeon_device *rdev); |
| 1866 | void (*init_profile)(struct radeon_device *rdev); |
| 1867 | void (*get_dynpm_state)(struct radeon_device *rdev); |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1868 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
| 1869 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
| 1870 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
| 1871 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
| 1872 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
| 1873 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 1874 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
Alex Deucher | 73afc70 | 2013-04-08 12:41:30 +0200 | [diff] [blame] | 1875 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
Alex Deucher | b59b733 | 2013-08-20 20:01:18 -0400 | [diff] [blame] | 1876 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
Alex Deucher | 6bd1c38 | 2013-06-21 14:38:03 -0400 | [diff] [blame] | 1877 | int (*get_temperature)(struct radeon_device *rdev); |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1878 | } pm; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1879 | /* dynamic power management */ |
| 1880 | struct { |
| 1881 | int (*init)(struct radeon_device *rdev); |
| 1882 | void (*setup_asic)(struct radeon_device *rdev); |
| 1883 | int (*enable)(struct radeon_device *rdev); |
Alex Deucher | 914a898 | 2013-12-19 11:37:22 -0500 | [diff] [blame] | 1884 | int (*late_enable)(struct radeon_device *rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1885 | void (*disable)(struct radeon_device *rdev); |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 1886 | int (*pre_set_power_state)(struct radeon_device *rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1887 | int (*set_power_state)(struct radeon_device *rdev); |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 1888 | void (*post_set_power_state)(struct radeon_device *rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1889 | void (*display_configuration_changed)(struct radeon_device *rdev); |
| 1890 | void (*fini)(struct radeon_device *rdev); |
| 1891 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); |
| 1892 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); |
| 1893 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); |
Alex Deucher | 1316b79 | 2013-06-28 09:28:39 -0400 | [diff] [blame] | 1894 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 1895 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
Alex Deucher | 4878306 | 2013-07-08 11:35:06 -0400 | [diff] [blame] | 1896 | bool (*vblank_too_short)(struct radeon_device *rdev); |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 1897 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
Alex Deucher | 1c71bda | 2013-09-09 19:11:52 -0400 | [diff] [blame] | 1898 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1899 | } dpm; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 1900 | /* pageflipping */ |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1901 | struct { |
Christian König | 157fa14 | 2014-05-27 16:49:20 +0200 | [diff] [blame] | 1902 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 1903 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1904 | } pflip; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1905 | }; |
| 1906 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1907 | /* |
| 1908 | * Asic structures |
| 1909 | */ |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1910 | struct r100_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1911 | const unsigned *reg_safe_bm; |
| 1912 | unsigned reg_safe_bm_size; |
| 1913 | u32 hdp_cntl; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1914 | }; |
| 1915 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1916 | struct r300_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1917 | const unsigned *reg_safe_bm; |
| 1918 | unsigned reg_safe_bm_size; |
| 1919 | u32 resync_scratch; |
| 1920 | u32 hdp_cntl; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1921 | }; |
| 1922 | |
| 1923 | struct r600_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1924 | unsigned max_pipes; |
| 1925 | unsigned max_tile_pipes; |
| 1926 | unsigned max_simds; |
| 1927 | unsigned max_backends; |
| 1928 | unsigned max_gprs; |
| 1929 | unsigned max_threads; |
| 1930 | unsigned max_stack_entries; |
| 1931 | unsigned max_hw_contexts; |
| 1932 | unsigned max_gs_threads; |
| 1933 | unsigned sx_max_export_size; |
| 1934 | unsigned sx_max_export_pos_size; |
| 1935 | unsigned sx_max_export_smx_size; |
| 1936 | unsigned sq_num_cf_insts; |
| 1937 | unsigned tiling_nbanks; |
| 1938 | unsigned tiling_npipes; |
| 1939 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1940 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1941 | unsigned backend_map; |
Alex Deucher | 65fcf66 | 2014-06-02 16:13:21 -0400 | [diff] [blame] | 1942 | unsigned active_simds; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1943 | }; |
| 1944 | |
| 1945 | struct rv770_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1946 | unsigned max_pipes; |
| 1947 | unsigned max_tile_pipes; |
| 1948 | unsigned max_simds; |
| 1949 | unsigned max_backends; |
| 1950 | unsigned max_gprs; |
| 1951 | unsigned max_threads; |
| 1952 | unsigned max_stack_entries; |
| 1953 | unsigned max_hw_contexts; |
| 1954 | unsigned max_gs_threads; |
| 1955 | unsigned sx_max_export_size; |
| 1956 | unsigned sx_max_export_pos_size; |
| 1957 | unsigned sx_max_export_smx_size; |
| 1958 | unsigned sq_num_cf_insts; |
| 1959 | unsigned sx_num_of_sets; |
| 1960 | unsigned sc_prim_fifo_size; |
| 1961 | unsigned sc_hiz_tile_fifo_size; |
| 1962 | unsigned sc_earlyz_tile_fifo_fize; |
| 1963 | unsigned tiling_nbanks; |
| 1964 | unsigned tiling_npipes; |
| 1965 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1966 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1967 | unsigned backend_map; |
Alex Deucher | 65fcf66 | 2014-06-02 16:13:21 -0400 | [diff] [blame] | 1968 | unsigned active_simds; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1969 | }; |
| 1970 | |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1971 | struct evergreen_asic { |
| 1972 | unsigned num_ses; |
| 1973 | unsigned max_pipes; |
| 1974 | unsigned max_tile_pipes; |
| 1975 | unsigned max_simds; |
| 1976 | unsigned max_backends; |
| 1977 | unsigned max_gprs; |
| 1978 | unsigned max_threads; |
| 1979 | unsigned max_stack_entries; |
| 1980 | unsigned max_hw_contexts; |
| 1981 | unsigned max_gs_threads; |
| 1982 | unsigned sx_max_export_size; |
| 1983 | unsigned sx_max_export_pos_size; |
| 1984 | unsigned sx_max_export_smx_size; |
| 1985 | unsigned sq_num_cf_insts; |
| 1986 | unsigned sx_num_of_sets; |
| 1987 | unsigned sc_prim_fifo_size; |
| 1988 | unsigned sc_hiz_tile_fifo_size; |
| 1989 | unsigned sc_earlyz_tile_fifo_size; |
| 1990 | unsigned tiling_nbanks; |
| 1991 | unsigned tiling_npipes; |
| 1992 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1993 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1994 | unsigned backend_map; |
Alex Deucher | 65fcf66 | 2014-06-02 16:13:21 -0400 | [diff] [blame] | 1995 | unsigned active_simds; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1996 | }; |
| 1997 | |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1998 | struct cayman_asic { |
| 1999 | unsigned max_shader_engines; |
| 2000 | unsigned max_pipes_per_simd; |
| 2001 | unsigned max_tile_pipes; |
| 2002 | unsigned max_simds_per_se; |
| 2003 | unsigned max_backends_per_se; |
| 2004 | unsigned max_texture_channel_caches; |
| 2005 | unsigned max_gprs; |
| 2006 | unsigned max_threads; |
| 2007 | unsigned max_gs_threads; |
| 2008 | unsigned max_stack_entries; |
| 2009 | unsigned sx_num_of_sets; |
| 2010 | unsigned sx_max_export_size; |
| 2011 | unsigned sx_max_export_pos_size; |
| 2012 | unsigned sx_max_export_smx_size; |
| 2013 | unsigned max_hw_contexts; |
| 2014 | unsigned sq_num_cf_insts; |
| 2015 | unsigned sc_prim_fifo_size; |
| 2016 | unsigned sc_hiz_tile_fifo_size; |
| 2017 | unsigned sc_earlyz_tile_fifo_size; |
| 2018 | |
| 2019 | unsigned num_shader_engines; |
| 2020 | unsigned num_shader_pipes_per_simd; |
| 2021 | unsigned num_tile_pipes; |
| 2022 | unsigned num_simds_per_se; |
| 2023 | unsigned num_backends_per_se; |
| 2024 | unsigned backend_disable_mask_per_asic; |
| 2025 | unsigned backend_map; |
| 2026 | unsigned num_texture_channel_caches; |
| 2027 | unsigned mem_max_burst_length_bytes; |
| 2028 | unsigned mem_row_size_in_kb; |
| 2029 | unsigned shader_engine_tile_size; |
| 2030 | unsigned num_gpus; |
| 2031 | unsigned multi_gpu_tile_size; |
| 2032 | |
| 2033 | unsigned tile_config; |
Alex Deucher | 65fcf66 | 2014-06-02 16:13:21 -0400 | [diff] [blame] | 2034 | unsigned active_simds; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 2035 | }; |
| 2036 | |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2037 | struct si_asic { |
| 2038 | unsigned max_shader_engines; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2039 | unsigned max_tile_pipes; |
Alex Deucher | 1a8ca75 | 2012-06-01 18:58:22 -0400 | [diff] [blame] | 2040 | unsigned max_cu_per_sh; |
| 2041 | unsigned max_sh_per_se; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2042 | unsigned max_backends_per_se; |
| 2043 | unsigned max_texture_channel_caches; |
| 2044 | unsigned max_gprs; |
| 2045 | unsigned max_gs_threads; |
| 2046 | unsigned max_hw_contexts; |
| 2047 | unsigned sc_prim_fifo_size_frontend; |
| 2048 | unsigned sc_prim_fifo_size_backend; |
| 2049 | unsigned sc_hiz_tile_fifo_size; |
| 2050 | unsigned sc_earlyz_tile_fifo_size; |
| 2051 | |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2052 | unsigned num_tile_pipes; |
Marek Olšák | 439a1cf | 2013-12-22 02:18:01 +0100 | [diff] [blame] | 2053 | unsigned backend_enable_mask; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2054 | unsigned backend_disable_mask_per_asic; |
| 2055 | unsigned backend_map; |
| 2056 | unsigned num_texture_channel_caches; |
| 2057 | unsigned mem_max_burst_length_bytes; |
| 2058 | unsigned mem_row_size_in_kb; |
| 2059 | unsigned shader_engine_tile_size; |
| 2060 | unsigned num_gpus; |
| 2061 | unsigned multi_gpu_tile_size; |
| 2062 | |
| 2063 | unsigned tile_config; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 2064 | uint32_t tile_mode_array[32]; |
Alex Deucher | 65fcf66 | 2014-06-02 16:13:21 -0400 | [diff] [blame] | 2065 | uint32_t active_cus; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2066 | }; |
| 2067 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 2068 | struct cik_asic { |
| 2069 | unsigned max_shader_engines; |
| 2070 | unsigned max_tile_pipes; |
| 2071 | unsigned max_cu_per_sh; |
| 2072 | unsigned max_sh_per_se; |
| 2073 | unsigned max_backends_per_se; |
| 2074 | unsigned max_texture_channel_caches; |
| 2075 | unsigned max_gprs; |
| 2076 | unsigned max_gs_threads; |
| 2077 | unsigned max_hw_contexts; |
| 2078 | unsigned sc_prim_fifo_size_frontend; |
| 2079 | unsigned sc_prim_fifo_size_backend; |
| 2080 | unsigned sc_hiz_tile_fifo_size; |
| 2081 | unsigned sc_earlyz_tile_fifo_size; |
| 2082 | |
| 2083 | unsigned num_tile_pipes; |
Marek Olšák | 439a1cf | 2013-12-22 02:18:01 +0100 | [diff] [blame] | 2084 | unsigned backend_enable_mask; |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 2085 | unsigned backend_disable_mask_per_asic; |
| 2086 | unsigned backend_map; |
| 2087 | unsigned num_texture_channel_caches; |
| 2088 | unsigned mem_max_burst_length_bytes; |
| 2089 | unsigned mem_row_size_in_kb; |
| 2090 | unsigned shader_engine_tile_size; |
| 2091 | unsigned num_gpus; |
| 2092 | unsigned multi_gpu_tile_size; |
| 2093 | |
| 2094 | unsigned tile_config; |
Alex Deucher | 39aee49 | 2013-04-10 13:41:25 -0400 | [diff] [blame] | 2095 | uint32_t tile_mode_array[32]; |
Michel Dänzer | 32f79a8 | 2013-11-18 18:26:00 +0900 | [diff] [blame] | 2096 | uint32_t macrotile_mode_array[16]; |
Alex Deucher | 65fcf66 | 2014-06-02 16:13:21 -0400 | [diff] [blame] | 2097 | uint32_t active_cus; |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 2098 | }; |
| 2099 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2100 | union radeon_asic_config { |
| 2101 | struct r300_asic r300; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2102 | struct r100_asic r100; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2103 | struct r600_asic r600; |
| 2104 | struct rv770_asic rv770; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 2105 | struct evergreen_asic evergreen; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 2106 | struct cayman_asic cayman; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2107 | struct si_asic si; |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 2108 | struct cik_asic cik; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2109 | }; |
| 2110 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 2111 | /* |
| 2112 | * asic initizalization from radeon_asic.c |
| 2113 | */ |
| 2114 | void radeon_agp_disable(struct radeon_device *rdev); |
| 2115 | int radeon_asic_init(struct radeon_device *rdev); |
| 2116 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2117 | |
| 2118 | /* |
| 2119 | * IOCTL. |
| 2120 | */ |
| 2121 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 2122 | struct drm_file *filp); |
| 2123 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 2124 | struct drm_file *filp); |
| 2125 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 2126 | struct drm_file *file_priv); |
| 2127 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 2128 | struct drm_file *file_priv); |
| 2129 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 2130 | struct drm_file *file_priv); |
| 2131 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 2132 | struct drm_file *file_priv); |
| 2133 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 2134 | struct drm_file *filp); |
| 2135 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 2136 | struct drm_file *filp); |
| 2137 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 2138 | struct drm_file *filp); |
| 2139 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 2140 | struct drm_file *filp); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2141 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
| 2142 | struct drm_file *filp); |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame] | 2143 | int radeon_gem_op_ioctl(struct drm_device *dev, void *data, |
| 2144 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2145 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2146 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 2147 | struct drm_file *filp); |
| 2148 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 2149 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2150 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2151 | /* VRAM scratch page for HDP bug, default vram page */ |
| 2152 | struct r600_vram_scratch { |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 2153 | struct radeon_bo *robj; |
| 2154 | volatile uint32_t *ptr; |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2155 | u64 gpu_addr; |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 2156 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2157 | |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 2158 | /* |
| 2159 | * ACPI |
| 2160 | */ |
| 2161 | struct radeon_atif_notification_cfg { |
| 2162 | bool enabled; |
| 2163 | int command_code; |
| 2164 | }; |
| 2165 | |
| 2166 | struct radeon_atif_notifications { |
| 2167 | bool display_switch; |
| 2168 | bool expansion_mode_change; |
| 2169 | bool thermal_state; |
| 2170 | bool forced_power_state; |
| 2171 | bool system_power_state; |
| 2172 | bool display_conf_change; |
| 2173 | bool px_gfx_switch; |
| 2174 | bool brightness_change; |
| 2175 | bool dgpu_display_event; |
| 2176 | }; |
| 2177 | |
| 2178 | struct radeon_atif_functions { |
| 2179 | bool system_params; |
| 2180 | bool sbios_requests; |
| 2181 | bool select_active_disp; |
| 2182 | bool lid_state; |
| 2183 | bool get_tv_standard; |
| 2184 | bool set_tv_standard; |
| 2185 | bool get_panel_expansion_mode; |
| 2186 | bool set_panel_expansion_mode; |
| 2187 | bool temperature_change; |
| 2188 | bool graphics_device_types; |
| 2189 | }; |
| 2190 | |
| 2191 | struct radeon_atif { |
| 2192 | struct radeon_atif_notifications notifications; |
| 2193 | struct radeon_atif_functions functions; |
| 2194 | struct radeon_atif_notification_cfg notification_cfg; |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 2195 | struct radeon_encoder *encoder_for_bl; |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 2196 | }; |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 2197 | |
Alex Deucher | e3a1592 | 2012-08-16 11:13:43 -0400 | [diff] [blame] | 2198 | struct radeon_atcs_functions { |
| 2199 | bool get_ext_state; |
| 2200 | bool pcie_perf_req; |
| 2201 | bool pcie_dev_rdy; |
| 2202 | bool pcie_bus_width; |
| 2203 | }; |
| 2204 | |
| 2205 | struct radeon_atcs { |
| 2206 | struct radeon_atcs_functions functions; |
| 2207 | }; |
| 2208 | |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 2209 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2210 | * Core structure, functions and helpers. |
| 2211 | */ |
| 2212 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 2213 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 2214 | |
| 2215 | struct radeon_device { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 2216 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2217 | struct drm_device *ddev; |
| 2218 | struct pci_dev *pdev; |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 2219 | struct rw_semaphore exclusive_lock; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2220 | /* ASIC */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2221 | union radeon_asic_config config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2222 | enum radeon_family family; |
| 2223 | unsigned long flags; |
| 2224 | int usec_timeout; |
| 2225 | enum radeon_pll_errata pll_errata; |
| 2226 | int num_gb_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 2227 | int num_z_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2228 | int disp_priority; |
| 2229 | /* BIOS */ |
| 2230 | uint8_t *bios; |
| 2231 | bool is_atom_bios; |
| 2232 | uint16_t bios_header_start; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2233 | struct radeon_bo *stollen_vga_memory; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2234 | /* Register mmio */ |
Dave Airlie | 4c9bc75 | 2009-06-29 18:29:12 +1000 | [diff] [blame] | 2235 | resource_size_t rmmio_base; |
| 2236 | resource_size_t rmmio_size; |
Daniel Vetter | 2c38515 | 2012-12-02 14:06:15 +0100 | [diff] [blame] | 2237 | /* protects concurrent MM_INDEX/DATA based register access */ |
| 2238 | spinlock_t mmio_idx_lock; |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2239 | /* protects concurrent SMC based register access */ |
| 2240 | spinlock_t smc_idx_lock; |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2241 | /* protects concurrent PLL register access */ |
| 2242 | spinlock_t pll_idx_lock; |
| 2243 | /* protects concurrent MC register access */ |
| 2244 | spinlock_t mc_idx_lock; |
| 2245 | /* protects concurrent PCIE register access */ |
| 2246 | spinlock_t pcie_idx_lock; |
| 2247 | /* protects concurrent PCIE_PORT register access */ |
| 2248 | spinlock_t pciep_idx_lock; |
| 2249 | /* protects concurrent PIF register access */ |
| 2250 | spinlock_t pif_idx_lock; |
| 2251 | /* protects concurrent CG register access */ |
| 2252 | spinlock_t cg_idx_lock; |
| 2253 | /* protects concurrent UVD register access */ |
| 2254 | spinlock_t uvd_idx_lock; |
| 2255 | /* protects concurrent RCU register access */ |
| 2256 | spinlock_t rcu_idx_lock; |
| 2257 | /* protects concurrent DIDT register access */ |
| 2258 | spinlock_t didt_idx_lock; |
| 2259 | /* protects concurrent ENDPOINT (audio) register access */ |
| 2260 | spinlock_t end_idx_lock; |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 2261 | void __iomem *rmmio; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2262 | radeon_rreg_t mc_rreg; |
| 2263 | radeon_wreg_t mc_wreg; |
| 2264 | radeon_rreg_t pll_rreg; |
| 2265 | radeon_wreg_t pll_wreg; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2266 | uint32_t pcie_reg_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2267 | radeon_rreg_t pciep_rreg; |
| 2268 | radeon_wreg_t pciep_wreg; |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 2269 | /* io port */ |
| 2270 | void __iomem *rio_mem; |
| 2271 | resource_size_t rio_mem_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2272 | struct radeon_clock clock; |
| 2273 | struct radeon_mc mc; |
| 2274 | struct radeon_gart gart; |
| 2275 | struct radeon_mode_info mode_info; |
| 2276 | struct radeon_scratch scratch; |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 2277 | struct radeon_doorbell doorbell; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2278 | struct radeon_mman mman; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 2279 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 2280 | wait_queue_head_t fence_queue; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 2281 | struct mutex ring_lock; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2282 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 2283 | bool ib_pool_ready; |
| 2284 | struct radeon_sa_manager ring_tmp_bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2285 | struct radeon_irq irq; |
| 2286 | struct radeon_asic *asic; |
| 2287 | struct radeon_gem gem; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2288 | struct radeon_pm pm; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 2289 | struct radeon_uvd uvd; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 2290 | struct radeon_vce vce; |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 2291 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2292 | struct radeon_wb wb; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2293 | struct radeon_dummy_page dummy_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2294 | bool shutdown; |
| 2295 | bool suspend; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 2296 | bool need_dma32; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 2297 | bool accel_working; |
Samuel Li | a0a53aa | 2013-04-08 17:25:47 -0400 | [diff] [blame] | 2298 | bool fastfb_working; /* IGP feature*/ |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 2299 | bool needs_reset; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2300 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2301 | const struct firmware *me_fw; /* all family ME firmware */ |
| 2302 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2303 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 2304 | const struct firmware *mc_fw; /* NI MC firmware */ |
Alex Deucher | 0f0de06 | 2012-03-20 17:18:17 -0400 | [diff] [blame] | 2305 | const struct firmware *ce_fw; /* SI CE firmware */ |
Alex Deucher | 02c8132 | 2012-12-18 21:43:07 -0500 | [diff] [blame] | 2306 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
Alex Deucher | f2c6b0f | 2014-06-25 19:32:36 -0400 | [diff] [blame] | 2307 | const struct firmware *mec2_fw; /* KV MEC2 firmware */ |
Alex Deucher | 21a93e1 | 2013-04-09 12:47:11 -0400 | [diff] [blame] | 2308 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 2309 | const struct firmware *smc_fw; /* SMC firmware */ |
Christian König | 4ad9c1c | 2013-08-05 14:10:55 +0200 | [diff] [blame] | 2310 | const struct firmware *uvd_fw; /* UVD firmware */ |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 2311 | const struct firmware *vce_fw; /* VCE firmware */ |
Alex Deucher | 629bd33 | 2014-06-25 18:41:34 -0400 | [diff] [blame] | 2312 | bool new_fw; |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2313 | struct r600_vram_scratch vram_scratch; |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 2314 | int msi_enabled; /* msi enabled */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2315 | struct r600_ih ih; /* r6/700 interrupt ring */ |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 2316 | struct radeon_rlc rlc; |
Alex Deucher | 963e81f | 2013-06-26 17:37:11 -0400 | [diff] [blame] | 2317 | struct radeon_mec mec; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 2318 | struct work_struct hotplug_work; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 2319 | struct work_struct audio_work; |
Alex Deucher | 8f61b34 | 2013-06-14 09:13:52 -0400 | [diff] [blame] | 2320 | struct work_struct reset_work; |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 2321 | int num_crtc; /* number of crtcs */ |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 2322 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
Alex Deucher | 948bee3 | 2013-05-14 12:08:35 -0400 | [diff] [blame] | 2323 | bool has_uvd; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 2324 | struct r600_audio audio; /* audio stuff */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 2325 | struct notifier_block acpi_nb; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 2326 | /* only one userspace can use Hyperz features or CMASK at a time */ |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 2327 | struct drm_file *hyperz_filp; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 2328 | struct drm_file *cmask_filp; |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 2329 | /* i2c buses */ |
| 2330 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 2331 | /* debugfs */ |
| 2332 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
| 2333 | unsigned debugfs_count; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2334 | /* virtual memory */ |
| 2335 | struct radeon_vm_manager vm_manager; |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 2336 | struct mutex gpu_clock_mutex; |
Marek Olšák | 67e8e3f | 2014-03-02 00:56:18 +0100 | [diff] [blame] | 2337 | /* memory stats */ |
| 2338 | atomic64_t vram_usage; |
| 2339 | atomic64_t gtt_usage; |
| 2340 | atomic64_t num_bytes_moved; |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 2341 | /* ACPI interface */ |
| 2342 | struct radeon_atif atif; |
Alex Deucher | e3a1592 | 2012-08-16 11:13:43 -0400 | [diff] [blame] | 2343 | struct radeon_atcs atcs; |
Alex Deucher | f61d5b46 | 2013-08-06 12:40:16 -0400 | [diff] [blame] | 2344 | /* srbm instance registers */ |
| 2345 | struct mutex srbm_mutex; |
Alex Deucher | 64d8a72 | 2013-08-08 16:31:25 -0400 | [diff] [blame] | 2346 | /* clock, powergating flags */ |
| 2347 | u32 cg_flags; |
| 2348 | u32 pg_flags; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 2349 | |
| 2350 | struct dev_pm_domain vga_pm_domain; |
| 2351 | bool have_disp_power_ref; |
Alex Deucher | 4807c5a | 2014-07-18 11:54:20 -0400 | [diff] [blame] | 2352 | u32 px_quirk_flags; |
Alex Deucher | 71ecc97 | 2014-07-17 12:09:25 -0400 | [diff] [blame] | 2353 | |
| 2354 | /* tracking pinned memory */ |
| 2355 | u64 vram_pin_size; |
| 2356 | u64 gart_pin_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2357 | }; |
| 2358 | |
Alex Deucher | 90c4cde | 2014-04-10 22:29:01 -0400 | [diff] [blame] | 2359 | bool radeon_is_px(struct drm_device *dev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2360 | int radeon_device_init(struct radeon_device *rdev, |
| 2361 | struct drm_device *ddev, |
| 2362 | struct pci_dev *pdev, |
| 2363 | uint32_t flags); |
| 2364 | void radeon_device_fini(struct radeon_device *rdev); |
| 2365 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 2366 | |
Lauri Kasanen | 59bc1d8 | 2014-04-20 20:29:33 +0300 | [diff] [blame] | 2367 | #define RADEON_MIN_MMIO_SIZE 0x10000 |
| 2368 | |
| 2369 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
| 2370 | bool always_indirect) |
| 2371 | { |
| 2372 | /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ |
| 2373 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
| 2374 | return readl(((void __iomem *)rdev->rmmio) + reg); |
| 2375 | else { |
| 2376 | unsigned long flags; |
| 2377 | uint32_t ret; |
| 2378 | |
| 2379 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); |
| 2380 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 2381 | ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 2382 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
| 2383 | |
| 2384 | return ret; |
| 2385 | } |
| 2386 | } |
| 2387 | |
| 2388 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
| 2389 | bool always_indirect) |
| 2390 | { |
| 2391 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
| 2392 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
| 2393 | else { |
| 2394 | unsigned long flags; |
| 2395 | |
| 2396 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); |
| 2397 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 2398 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 2399 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); |
| 2400 | } |
| 2401 | } |
| 2402 | |
Andi Kleen | 6fcbef7 | 2011-10-13 16:08:42 -0700 | [diff] [blame] | 2403 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
| 2404 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 2405 | |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 2406 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
| 2407 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 2408 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2409 | /* |
| 2410 | * Cast helper |
| 2411 | */ |
| 2412 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2413 | |
| 2414 | /* |
| 2415 | * Registers read & write functions. |
| 2416 | */ |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 2417 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
| 2418 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
| 2419 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
| 2420 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
Daniel Vetter | 2ef9bdf | 2012-12-02 14:02:51 +0100 | [diff] [blame] | 2421 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
| 2422 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
| 2423 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) |
| 2424 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
| 2425 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2426 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 2427 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 2428 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 2429 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 2430 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 2431 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2432 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
| 2433 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 2434 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
| 2435 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2436 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
| 2437 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2438 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
| 2439 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2440 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
| 2441 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2442 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
| 2443 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) |
| 2444 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) |
| 2445 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2446 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
| 2447 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2448 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
| 2449 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2450 | #define WREG32_P(reg, val, mask) \ |
| 2451 | do { \ |
| 2452 | uint32_t tmp_ = RREG32(reg); \ |
| 2453 | tmp_ &= (mask); \ |
| 2454 | tmp_ |= ((val) & ~(mask)); \ |
| 2455 | WREG32(reg, tmp_); \ |
| 2456 | } while (0) |
Rafał Miłecki | d5169fc | 2013-04-14 01:26:19 +0200 | [diff] [blame] | 2457 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
Rafał Miłecki | d43a93c | 2013-08-15 18:55:22 +0200 | [diff] [blame] | 2458 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2459 | #define WREG32_PLL_P(reg, val, mask) \ |
| 2460 | do { \ |
| 2461 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 2462 | tmp_ &= (mask); \ |
| 2463 | tmp_ |= ((val) & ~(mask)); \ |
| 2464 | WREG32_PLL(reg, tmp_); \ |
| 2465 | } while (0) |
Daniel Vetter | 2ef9bdf | 2012-12-02 14:02:51 +0100 | [diff] [blame] | 2466 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 2467 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
| 2468 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2469 | |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 2470 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
| 2471 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 2472 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2473 | /* |
| 2474 | * Indirect registers accessor |
| 2475 | */ |
| 2476 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| 2477 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2478 | unsigned long flags; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2479 | uint32_t r; |
| 2480 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2481 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2482 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 2483 | r = RREG32(RADEON_PCIE_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2484 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2485 | return r; |
| 2486 | } |
| 2487 | |
| 2488 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 2489 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2490 | unsigned long flags; |
| 2491 | |
| 2492 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2493 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 2494 | WREG32(RADEON_PCIE_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2495 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2496 | } |
| 2497 | |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2498 | static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) |
| 2499 | { |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2500 | unsigned long flags; |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2501 | u32 r; |
| 2502 | |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2503 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2504 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
| 2505 | r = RREG32(TN_SMC_IND_DATA_0); |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2506 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2507 | return r; |
| 2508 | } |
| 2509 | |
| 2510 | static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2511 | { |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2512 | unsigned long flags; |
| 2513 | |
| 2514 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2515 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
| 2516 | WREG32(TN_SMC_IND_DATA_0, (v)); |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2517 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2518 | } |
| 2519 | |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2520 | static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) |
| 2521 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2522 | unsigned long flags; |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2523 | u32 r; |
| 2524 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2525 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2526 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
| 2527 | r = RREG32(R600_RCU_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2528 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2529 | return r; |
| 2530 | } |
| 2531 | |
| 2532 | static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2533 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2534 | unsigned long flags; |
| 2535 | |
| 2536 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2537 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
| 2538 | WREG32(R600_RCU_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2539 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2540 | } |
| 2541 | |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2542 | static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) |
| 2543 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2544 | unsigned long flags; |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2545 | u32 r; |
| 2546 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2547 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2548 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
| 2549 | r = RREG32(EVERGREEN_CG_IND_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2550 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2551 | return r; |
| 2552 | } |
| 2553 | |
| 2554 | static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2555 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2556 | unsigned long flags; |
| 2557 | |
| 2558 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2559 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
| 2560 | WREG32(EVERGREEN_CG_IND_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2561 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2562 | } |
| 2563 | |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2564 | static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) |
| 2565 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2566 | unsigned long flags; |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2567 | u32 r; |
| 2568 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2569 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2570 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
| 2571 | r = RREG32(EVERGREEN_PIF_PHY0_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2572 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2573 | return r; |
| 2574 | } |
| 2575 | |
| 2576 | static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2577 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2578 | unsigned long flags; |
| 2579 | |
| 2580 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2581 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
| 2582 | WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2583 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2584 | } |
| 2585 | |
| 2586 | static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) |
| 2587 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2588 | unsigned long flags; |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2589 | u32 r; |
| 2590 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2591 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2592 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
| 2593 | r = RREG32(EVERGREEN_PIF_PHY1_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2594 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2595 | return r; |
| 2596 | } |
| 2597 | |
| 2598 | static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2599 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2600 | unsigned long flags; |
| 2601 | |
| 2602 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2603 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
| 2604 | WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2605 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2606 | } |
| 2607 | |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2608 | static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) |
| 2609 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2610 | unsigned long flags; |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2611 | u32 r; |
| 2612 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2613 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2614 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
| 2615 | r = RREG32(R600_UVD_CTX_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2616 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2617 | return r; |
| 2618 | } |
| 2619 | |
| 2620 | static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2621 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2622 | unsigned long flags; |
| 2623 | |
| 2624 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2625 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
| 2626 | WREG32(R600_UVD_CTX_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2627 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2628 | } |
| 2629 | |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2630 | |
| 2631 | static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) |
| 2632 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2633 | unsigned long flags; |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2634 | u32 r; |
| 2635 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2636 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2637 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
| 2638 | r = RREG32(CIK_DIDT_IND_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2639 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2640 | return r; |
| 2641 | } |
| 2642 | |
| 2643 | static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2644 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2645 | unsigned long flags; |
| 2646 | |
| 2647 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2648 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
| 2649 | WREG32(CIK_DIDT_IND_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2650 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2651 | } |
| 2652 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2653 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 2654 | |
| 2655 | |
| 2656 | /* |
| 2657 | * ASICs helpers. |
| 2658 | */ |
Dave Airlie | b995e43 | 2009-07-14 02:02:32 +1000 | [diff] [blame] | 2659 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
| 2660 | (rdev->pdev->device == 0x5969)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2661 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 2662 | (rdev->family == CHIP_RV200) || \ |
| 2663 | (rdev->family == CHIP_RS100) || \ |
| 2664 | (rdev->family == CHIP_RS200) || \ |
| 2665 | (rdev->family == CHIP_RV250) || \ |
| 2666 | (rdev->family == CHIP_RV280) || \ |
| 2667 | (rdev->family == CHIP_RS300)) |
| 2668 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 2669 | (rdev->family == CHIP_RV350) || \ |
| 2670 | (rdev->family == CHIP_R350) || \ |
| 2671 | (rdev->family == CHIP_RV380) || \ |
| 2672 | (rdev->family == CHIP_R420) || \ |
| 2673 | (rdev->family == CHIP_R423) || \ |
| 2674 | (rdev->family == CHIP_RV410) || \ |
| 2675 | (rdev->family == CHIP_RS400) || \ |
| 2676 | (rdev->family == CHIP_RS480)) |
Alex Deucher | 3313e3d | 2011-01-06 18:49:34 -0500 | [diff] [blame] | 2677 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
| 2678 | (rdev->ddev->pdev->device == 0x9443) || \ |
| 2679 | (rdev->ddev->pdev->device == 0x944B) || \ |
| 2680 | (rdev->ddev->pdev->device == 0x9506) || \ |
| 2681 | (rdev->ddev->pdev->device == 0x9509) || \ |
| 2682 | (rdev->ddev->pdev->device == 0x950F) || \ |
| 2683 | (rdev->ddev->pdev->device == 0x689C) || \ |
| 2684 | (rdev->ddev->pdev->device == 0x689D)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2685 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
Alex Deucher | 99999aa | 2010-11-16 12:09:41 -0500 | [diff] [blame] | 2686 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
| 2687 | (rdev->family == CHIP_RS690) || \ |
| 2688 | (rdev->family == CHIP_RS740) || \ |
| 2689 | (rdev->family >= CHIP_R600)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2690 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 2691 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 2692 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
Alex Deucher | 633b916 | 2011-01-06 21:19:11 -0500 | [diff] [blame] | 2693 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
| 2694 | (rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | 1fe1830 | 2011-01-06 21:19:12 -0500 | [diff] [blame] | 2695 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
Alex Deucher | 8848f75 | 2012-03-20 17:18:28 -0400 | [diff] [blame] | 2696 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
| 2697 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
| 2698 | (rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | 624d352 | 2012-12-18 17:01:35 -0500 | [diff] [blame] | 2699 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
Alex Deucher | b5d9d72 | 2012-07-26 18:53:55 -0400 | [diff] [blame] | 2700 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
Alex Deucher | e282917 | 2013-06-07 11:37:11 -0400 | [diff] [blame] | 2701 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
Alex Deucher | be0949f | 2014-04-08 11:28:54 -0400 | [diff] [blame] | 2702 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
| 2703 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) |
Alex Deucher | 89d2618 | 2014-05-08 18:26:23 -0400 | [diff] [blame] | 2704 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ |
| 2705 | (rdev->family == CHIP_MULLINS)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2706 | |
Alex Deucher | dc50ba7 | 2013-06-26 00:33:35 -0400 | [diff] [blame] | 2707 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
| 2708 | (rdev->ddev->pdev->device == 0x6850) || \ |
| 2709 | (rdev->ddev->pdev->device == 0x6858) || \ |
| 2710 | (rdev->ddev->pdev->device == 0x6859) || \ |
| 2711 | (rdev->ddev->pdev->device == 0x6840) || \ |
| 2712 | (rdev->ddev->pdev->device == 0x6841) || \ |
| 2713 | (rdev->ddev->pdev->device == 0x6842) || \ |
| 2714 | (rdev->ddev->pdev->device == 0x6843)) |
| 2715 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2716 | /* |
| 2717 | * BIOS helpers. |
| 2718 | */ |
| 2719 | #define RBIOS8(i) (rdev->bios[i]) |
| 2720 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 2721 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 2722 | |
| 2723 | int radeon_combios_init(struct radeon_device *rdev); |
| 2724 | void radeon_combios_fini(struct radeon_device *rdev); |
| 2725 | int radeon_atombios_init(struct radeon_device *rdev); |
| 2726 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 2727 | |
| 2728 | |
| 2729 | /* |
| 2730 | * RING helpers. |
| 2731 | */ |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 2732 | #if DRM_DEBUG_CODE == 0 |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2733 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2734 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2735 | ring->ring[ring->wptr++] = v; |
| 2736 | ring->wptr &= ring->ptr_mask; |
| 2737 | ring->count_dw--; |
| 2738 | ring->ring_free_dw--; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2739 | } |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 2740 | #else |
| 2741 | /* With debugging this is just too big to inline */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2742 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 2743 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2744 | |
| 2745 | /* |
| 2746 | * ASICs macro. |
| 2747 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2748 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2749 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 2750 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 2751 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 2752 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2753 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 2754 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 2755 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 2756 | #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 2757 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
| 2758 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
Alex Deucher | 43f1214 | 2013-02-01 17:32:42 +0100 | [diff] [blame] | 2759 | #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 2760 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
| 2761 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) |
| 2762 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) |
| 2763 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) |
| 2764 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) |
| 2765 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) |
| 2766 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) |
| 2767 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) |
| 2768 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) |
| 2769 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 2770 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
| 2771 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 2772 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 2773 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 2774 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 2775 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
| 2776 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 2777 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
| 2778 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 2779 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
| 2780 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
| 2781 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
| 2782 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
| 2783 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
| 2784 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 2785 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
| 2786 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
| 2787 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
| 2788 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
| 2789 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
| 2790 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
| 2791 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
Alex Deucher | 73afc70 | 2013-04-08 12:41:30 +0200 | [diff] [blame] | 2792 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
Alex Deucher | b59b733 | 2013-08-20 20:01:18 -0400 | [diff] [blame] | 2793 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
Alex Deucher | 6bd1c38 | 2013-06-21 14:38:03 -0400 | [diff] [blame] | 2794 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 2795 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
| 2796 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 2797 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 2798 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
| 2799 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
| 2800 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
| 2801 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 2802 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 2803 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
| 2804 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
| 2805 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
| 2806 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
| 2807 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
Alex Deucher | 69b62ad | 2012-08-03 11:50:54 -0400 | [diff] [blame] | 2808 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
Christian König | 157fa14 | 2014-05-27 16:49:20 +0200 | [diff] [blame] | 2809 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
Alex Deucher | 69b62ad | 2012-08-03 11:50:54 -0400 | [diff] [blame] | 2810 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
| 2811 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 2812 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
Alex Deucher | d041889 | 2013-01-24 10:35:23 -0500 | [diff] [blame] | 2813 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 2814 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
| 2815 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) |
| 2816 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) |
Alex Deucher | 914a898 | 2013-12-19 11:37:22 -0500 | [diff] [blame] | 2817 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 2818 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 2819 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 2820 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 2821 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 2822 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
| 2823 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) |
| 2824 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) |
| 2825 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) |
| 2826 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) |
Alex Deucher | 1316b79 | 2013-06-28 09:28:39 -0400 | [diff] [blame] | 2827 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 2828 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
Alex Deucher | 4878306 | 2013-07-08 11:35:06 -0400 | [diff] [blame] | 2829 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 2830 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
Alex Deucher | 1c71bda | 2013-09-09 19:11:52 -0400 | [diff] [blame] | 2831 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2832 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 2833 | /* Common functions */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 2834 | /* AGP */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2835 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
Alex Deucher | 1a0041b | 2013-10-02 13:01:36 -0400 | [diff] [blame] | 2836 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
Alex Deucher | 410a341 | 2013-01-18 13:05:39 -0500 | [diff] [blame] | 2837 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 2838 | extern void radeon_agp_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 2839 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 2840 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 2841 | extern bool radeon_card_posted(struct radeon_device *rdev); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 2842 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 2843 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 2844 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 2845 | extern void radeon_scratch_init(struct radeon_device *rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2846 | extern void radeon_wb_fini(struct radeon_device *rdev); |
| 2847 | extern int radeon_wb_init(struct radeon_device *rdev); |
| 2848 | extern void radeon_wb_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 2849 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 2850 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 2851 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 2852 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 2853 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 2854 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2855 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
| 2856 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 2857 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
| 2858 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 2859 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
Alex Deucher | 2e1b65f | 2013-02-26 11:26:51 -0500 | [diff] [blame] | 2860 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
| 2861 | const u32 *registers, |
| 2862 | const u32 array_size); |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 2863 | |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 2864 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2865 | * vm |
| 2866 | */ |
| 2867 | int radeon_vm_manager_init(struct radeon_device *rdev); |
| 2868 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 2869 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2870 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
Christian König | df0af44 | 2014-03-03 12:38:08 +0100 | [diff] [blame] | 2871 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
| 2872 | struct radeon_vm *vm, |
| 2873 | struct list_head *head); |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 2874 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
| 2875 | struct radeon_vm *vm, int ring); |
Christian König | fa68834 | 2014-02-20 10:47:05 +0100 | [diff] [blame] | 2876 | void radeon_vm_flush(struct radeon_device *rdev, |
| 2877 | struct radeon_vm *vm, |
| 2878 | int ring); |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 2879 | void radeon_vm_fence(struct radeon_device *rdev, |
| 2880 | struct radeon_vm *vm, |
| 2881 | struct radeon_fence *fence); |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 2882 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 2883 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
| 2884 | struct radeon_vm *vm); |
Christian König | 036bf46 | 2014-07-18 08:56:40 +0200 | [diff] [blame] | 2885 | int radeon_vm_clear_freed(struct radeon_device *rdev, |
| 2886 | struct radeon_vm *vm); |
Christian König | 9c57a6b | 2013-11-25 15:42:11 +0100 | [diff] [blame] | 2887 | int radeon_vm_bo_update(struct radeon_device *rdev, |
Christian König | 036bf46 | 2014-07-18 08:56:40 +0200 | [diff] [blame] | 2888 | struct radeon_bo_va *bo_va, |
Christian König | 9c57a6b | 2013-11-25 15:42:11 +0100 | [diff] [blame] | 2889 | struct ttm_mem_reg *mem); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2890 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
| 2891 | struct radeon_bo *bo); |
Christian König | 421ca7a | 2012-09-11 16:10:00 +0200 | [diff] [blame] | 2892 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
| 2893 | struct radeon_bo *bo); |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 2894 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
| 2895 | struct radeon_vm *vm, |
| 2896 | struct radeon_bo *bo); |
| 2897 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
| 2898 | struct radeon_bo_va *bo_va, |
| 2899 | uint64_t offset, |
| 2900 | uint32_t flags); |
Christian König | 036bf46 | 2014-07-18 08:56:40 +0200 | [diff] [blame] | 2901 | void radeon_vm_bo_rmv(struct radeon_device *rdev, |
| 2902 | struct radeon_bo_va *bo_va); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2903 | |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 2904 | /* audio */ |
| 2905 | void r600_audio_update_hdmi(struct work_struct *work); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 2906 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
| 2907 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
Alex Deucher | 832eafa | 2014-02-18 11:07:55 -0500 | [diff] [blame] | 2908 | void r600_audio_enable(struct radeon_device *rdev, |
| 2909 | struct r600_audio_pin *pin, |
| 2910 | bool enable); |
| 2911 | void dce6_audio_enable(struct radeon_device *rdev, |
| 2912 | struct r600_audio_pin *pin, |
| 2913 | bool enable); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2914 | |
| 2915 | /* |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2916 | * R600 vram scratch functions |
| 2917 | */ |
| 2918 | int r600_vram_scratch_init(struct radeon_device *rdev); |
| 2919 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
| 2920 | |
| 2921 | /* |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 2922 | * r600 cs checking helper |
| 2923 | */ |
| 2924 | unsigned r600_mip_minify(unsigned size, unsigned level); |
| 2925 | bool r600_fmt_is_valid_color(u32 format); |
| 2926 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
| 2927 | int r600_fmt_get_blocksize(u32 format); |
| 2928 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
| 2929 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
| 2930 | |
| 2931 | /* |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 2932 | * r600 functions used by radeon_encoder.c |
| 2933 | */ |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 2934 | struct radeon_hdmi_acr { |
| 2935 | u32 clock; |
| 2936 | |
| 2937 | int n_32khz; |
| 2938 | int cts_32khz; |
| 2939 | |
| 2940 | int n_44_1khz; |
| 2941 | int cts_44_1khz; |
| 2942 | |
| 2943 | int n_48khz; |
| 2944 | int cts_48khz; |
| 2945 | |
| 2946 | }; |
| 2947 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 2948 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
| 2949 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 2950 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
| 2951 | u32 tiling_pipe_num, |
| 2952 | u32 max_rb_num, |
| 2953 | u32 total_max_rb_num, |
| 2954 | u32 enabled_rb_mask); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2955 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 2956 | /* |
| 2957 | * evergreen functions used by radeon_encoder.c |
| 2958 | */ |
| 2959 | |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 2960 | extern int ni_init_microcode(struct radeon_device *rdev); |
Alex Deucher | 755d819 | 2011-03-02 20:07:34 -0500 | [diff] [blame] | 2961 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 2962 | |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 2963 | /* radeon_acpi.c */ |
| 2964 | #if defined(CONFIG_ACPI) |
| 2965 | extern int radeon_acpi_init(struct radeon_device *rdev); |
| 2966 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
Alex Deucher | dc50ba7 | 2013-06-26 00:33:35 -0400 | [diff] [blame] | 2967 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
| 2968 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, |
Alex Deucher | e37e6a0 | 2013-02-13 15:47:24 -0500 | [diff] [blame] | 2969 | u8 perf_req, bool advertise); |
Alex Deucher | dc50ba7 | 2013-06-26 00:33:35 -0400 | [diff] [blame] | 2970 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 2971 | #else |
| 2972 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
| 2973 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
| 2974 | #endif |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 2975 | |
Ilija Hadzic | c38f34b | 2013-01-02 18:27:41 -0500 | [diff] [blame] | 2976 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
| 2977 | struct radeon_cs_packet *pkt, |
| 2978 | unsigned idx); |
Ilija Hadzic | 9ffb7a6 | 2013-01-02 18:27:42 -0500 | [diff] [blame] | 2979 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
Ilija Hadzic | c3ad63a | 2013-01-02 18:27:45 -0500 | [diff] [blame] | 2980 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
| 2981 | struct radeon_cs_packet *pkt); |
Ilija Hadzic | e971699 | 2013-01-02 18:27:46 -0500 | [diff] [blame] | 2982 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
| 2983 | struct radeon_cs_reloc **cs_reloc, |
| 2984 | int nomm); |
Ilija Hadzic | 40592a1 | 2013-01-02 18:27:43 -0500 | [diff] [blame] | 2985 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
| 2986 | uint32_t *vline_start_end, |
| 2987 | uint32_t *vline_status); |
Ilija Hadzic | c38f34b | 2013-01-02 18:27:41 -0500 | [diff] [blame] | 2988 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2989 | #include "radeon_object.h" |
| 2990 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2991 | #endif |