blob: c2976ade823fa1b8e0d3d381e09342c02f90843a [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Chon Ming Leeef9348c2014-04-09 13:28:18 +030044#define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
46
Daniel Vetter3dec0092010-08-20 21:40:52 +020047static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010048static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080049
Jesse Barnesf1f644d2013-06-27 00:39:25 +030050static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030052static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030054
Damien Lespiaue7457a92013-08-08 22:28:59 +010055static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080057static int intel_framebuffer_init(struct drm_device *dev,
58 struct intel_framebuffer *ifb,
59 struct drm_mode_fb_cmd2 *mode_cmd,
60 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020061static void intel_dp_set_m_n(struct intel_crtc *crtc);
62static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
63static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020064static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
65 struct intel_link_m_n *m_n);
66static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +020067static void haswell_set_pipeconf(struct drm_crtc *crtc);
68static void intel_set_pipe_csc(struct drm_crtc *crtc);
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +020069static void vlv_prepare_pll(struct intel_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +010070
Jesse Barnes79e53942008-11-07 14:24:08 -080071typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040072 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080073} intel_range_t;
74
75typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040076 int dot_limit;
77 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080078} intel_p2_t;
79
Ma Lingd4906092009-03-18 20:13:27 +080080typedef struct intel_limit intel_limit_t;
81struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040082 intel_range_t dot, vco, n, m, m1, m2, p, p1;
83 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080084};
Jesse Barnes79e53942008-11-07 14:24:08 -080085
Daniel Vetterd2acd212012-10-20 20:57:43 +020086int
87intel_pch_rawclk(struct drm_device *dev)
88{
89 struct drm_i915_private *dev_priv = dev->dev_private;
90
91 WARN_ON(!HAS_PCH_SPLIT(dev));
92
93 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94}
95
Chris Wilson021357a2010-09-07 20:54:59 +010096static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
Chris Wilson8b99e682010-10-13 09:59:17 +010099 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100104}
105
Daniel Vetter5d536e22013-07-06 12:52:06 +0200106static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400107 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200108 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200109 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700117};
118
Daniel Vetter5d536e22013-07-06 12:52:06 +0200119static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200121 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200122 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 4 },
130};
131
Keith Packarde4b36692009-06-05 19:22:17 -0700132static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400133 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200134 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200135 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400136 .m = { .min = 96, .max = 140 },
137 .m1 = { .min = 18, .max = 26 },
138 .m2 = { .min = 6, .max = 16 },
139 .p = { .min = 4, .max = 128 },
140 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700141 .p2 = { .dot_limit = 165000,
142 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700143};
Eric Anholt273e27c2011-03-30 13:01:10 -0700144
Keith Packarde4b36692009-06-05 19:22:17 -0700145static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400146 .dot = { .min = 20000, .max = 400000 },
147 .vco = { .min = 1400000, .max = 2800000 },
148 .n = { .min = 1, .max = 6 },
149 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100150 .m1 = { .min = 8, .max = 18 },
151 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400152 .p = { .min = 5, .max = 80 },
153 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700154 .p2 = { .dot_limit = 200000,
155 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100163 .m1 = { .min = 8, .max = 18 },
164 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700169};
170
Eric Anholt273e27c2011-03-30 13:01:10 -0700171
Keith Packarde4b36692009-06-05 19:22:17 -0700172static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700173 .dot = { .min = 25000, .max = 270000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 17, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 10, .max = 30 },
180 .p1 = { .min = 1, .max = 3},
181 .p2 = { .dot_limit = 270000,
182 .p2_slow = 10,
183 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800184 },
Keith Packarde4b36692009-06-05 19:22:17 -0700185};
186
187static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700188 .dot = { .min = 22000, .max = 400000 },
189 .vco = { .min = 1750000, .max = 3500000},
190 .n = { .min = 1, .max = 4 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 16, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8},
196 .p2 = { .dot_limit = 165000,
197 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700198};
199
200static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700201 .dot = { .min = 20000, .max = 115000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 28, .max = 112 },
208 .p1 = { .min = 2, .max = 8 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800211 },
Keith Packarde4b36692009-06-05 19:22:17 -0700212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800225 },
Keith Packarde4b36692009-06-05 19:22:17 -0700226};
227
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500228static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400229 .dot = { .min = 20000, .max = 400000},
230 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700231 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700234 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400235 .m1 = { .min = 0, .max = 0 },
236 .m2 = { .min = 0, .max = 254 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700239 .p2 = { .dot_limit = 200000,
240 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700241};
242
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500243static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1700000, .max = 3500000 },
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 .m1 = { .min = 0, .max = 0 },
249 .m2 = { .min = 0, .max = 254 },
250 .p = { .min = 7, .max = 112 },
251 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700252 .p2 = { .dot_limit = 112000,
253 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700254};
255
Eric Anholt273e27c2011-03-30 13:01:10 -0700256/* Ironlake / Sandybridge
257 *
258 * We calculate clock using (register_value + 2) for N/M1/M2, so here
259 * the range value for them is (actual_value - 2).
260 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800261static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 1760000, .max = 3510000 },
264 .n = { .min = 1, .max = 5 },
265 .m = { .min = 79, .max = 127 },
266 .m1 = { .min = 12, .max = 22 },
267 .m2 = { .min = 5, .max = 9 },
268 .p = { .min = 5, .max = 80 },
269 .p1 = { .min = 1, .max = 8 },
270 .p2 = { .dot_limit = 225000,
271 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700272};
273
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800274static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 3 },
278 .m = { .min = 79, .max = 118 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
282 .p1 = { .min = 2, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800285};
286
287static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 127 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 56 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800298};
299
Eric Anholt273e27c2011-03-30 13:01:10 -0700300/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800301static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 2 },
305 .m = { .min = 79, .max = 126 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400309 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800312};
313
314static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 3 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400322 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800325};
326
Ville Syrjälädc730512013-09-24 21:26:30 +0300327static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300328 /*
329 * These are the data rate limits (measured in fast clocks)
330 * since those are the strictest limits we have. The fast
331 * clock and actual rate limits are more relaxed, so checking
332 * them would make no difference.
333 */
334 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200335 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700336 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700337 .m1 = { .min = 2, .max = 3 },
338 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300339 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300340 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700341};
342
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300343static const intel_limit_t intel_limits_chv = {
344 /*
345 * These are the data rate limits (measured in fast clocks)
346 * since those are the strictest limits we have. The fast
347 * clock and actual rate limits are more relaxed, so checking
348 * them would make no difference.
349 */
350 .dot = { .min = 25000 * 5, .max = 540000 * 5},
351 .vco = { .min = 4860000, .max = 6700000 },
352 .n = { .min = 1, .max = 1 },
353 .m1 = { .min = 2, .max = 2 },
354 .m2 = { .min = 24 << 22, .max = 175 << 22 },
355 .p1 = { .min = 2, .max = 4 },
356 .p2 = { .p2_slow = 1, .p2_fast = 14 },
357};
358
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300359static void vlv_clock(int refclk, intel_clock_t *clock)
360{
361 clock->m = clock->m1 * clock->m2;
362 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200363 if (WARN_ON(clock->n == 0 || clock->p == 0))
364 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300365 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
366 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300367}
368
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300369/**
370 * Returns whether any output on the specified pipe is of the specified type
371 */
372static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
373{
374 struct drm_device *dev = crtc->dev;
375 struct intel_encoder *encoder;
376
377 for_each_encoder_on_crtc(dev, crtc, encoder)
378 if (encoder->type == type)
379 return true;
380
381 return false;
382}
383
Chris Wilson1b894b52010-12-14 20:04:54 +0000384static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800386{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800387 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800388 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100391 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000392 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000397 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200402 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800403 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800404
405 return limit;
406}
407
Ma Ling044c7c42009-03-18 20:13:23 +0800408static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409{
410 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100414 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700415 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800416 else
Keith Packarde4b36692009-06-05 19:22:17 -0700417 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700420 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700422 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800423 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700424 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800425
426 return limit;
427}
428
Chris Wilson1b894b52010-12-14 20:04:54 +0000429static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800430{
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
Eric Anholtbad720f2009-10-22 16:11:14 -0700434 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000435 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800436 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800437 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500438 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500440 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800441 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500442 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300443 } else if (IS_CHERRYVIEW(dev)) {
444 limit = &intel_limits_chv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700445 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300446 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100447 } else if (!IS_GEN2(dev)) {
448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
449 limit = &intel_limits_i9xx_lvds;
450 else
451 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800452 } else {
453 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700454 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200455 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700456 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200457 else
458 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800459 }
460 return limit;
461}
462
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500463/* m1 is reserved as 0 in Pineview, n is a ring counter */
464static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800465{
Shaohua Li21778322009-02-23 15:19:16 +0800466 clock->m = clock->m2 + 2;
467 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200468 if (WARN_ON(clock->n == 0 || clock->p == 0))
469 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300470 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
471 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800472}
473
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200474static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
475{
476 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
477}
478
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200479static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800480{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200481 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800482 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200483 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
484 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300485 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
486 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800487}
488
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300489static void chv_clock(int refclk, intel_clock_t *clock)
490{
491 clock->m = clock->m1 * clock->m2;
492 clock->p = clock->p1 * clock->p2;
493 if (WARN_ON(clock->n == 0 || clock->p == 0))
494 return;
495 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
496 clock->n << 22);
497 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
498}
499
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800500#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800501/**
502 * Returns whether the given set of divisors are valid for a given refclk with
503 * the given connectors.
504 */
505
Chris Wilson1b894b52010-12-14 20:04:54 +0000506static bool intel_PLL_is_valid(struct drm_device *dev,
507 const intel_limit_t *limit,
508 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800509{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300510 if (clock->n < limit->n.min || limit->n.max < clock->n)
511 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800512 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400513 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800514 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400515 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800516 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400517 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300518
519 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
520 if (clock->m1 <= clock->m2)
521 INTELPllInvalid("m1 <= m2\n");
522
523 if (!IS_VALLEYVIEW(dev)) {
524 if (clock->p < limit->p.min || limit->p.max < clock->p)
525 INTELPllInvalid("p out of range\n");
526 if (clock->m < limit->m.min || limit->m.max < clock->m)
527 INTELPllInvalid("m out of range\n");
528 }
529
Jesse Barnes79e53942008-11-07 14:24:08 -0800530 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400531 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800532 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
533 * connector, etc., rather than just a single range.
534 */
535 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400536 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800537
538 return true;
539}
540
Ma Lingd4906092009-03-18 20:13:27 +0800541static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200542i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800543 int target, int refclk, intel_clock_t *match_clock,
544 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800545{
546 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800547 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800548 int err = target;
549
Daniel Vettera210b022012-11-26 17:22:08 +0100550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800551 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800555 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100556 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
Akshay Joshi0206e352011-08-16 15:34:10 -0400567 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800568
Zhao Yakui42158662009-11-20 11:24:18 +0800569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200573 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800574 break;
575 for (clock.n = limit->n.min;
576 clock.n <= limit->n.max; clock.n++) {
577 for (clock.p1 = limit->p1.min;
578 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800579 int this_err;
580
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200581 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000582 if (!intel_PLL_is_valid(dev, limit,
583 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800584 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800585 if (match_clock &&
586 clock.p != match_clock->p)
587 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800588
589 this_err = abs(clock.dot - target);
590 if (this_err < err) {
591 *best_clock = clock;
592 err = this_err;
593 }
594 }
595 }
596 }
597 }
598
599 return (err != target);
600}
601
Ma Lingd4906092009-03-18 20:13:27 +0800602static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200603pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200606{
607 struct drm_device *dev = crtc->dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659}
660
Ma Lingd4906092009-03-18 20:13:27 +0800661static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200662g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800665{
666 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800667 intel_clock_t clock;
668 int max_n;
669 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400670 /* approximately equals target * 0.00585 */
671 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800672 found = false;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100675 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800676 clock.p2 = limit->p2.p2_fast;
677 else
678 clock.p2 = limit->p2.p2_slow;
679 } else {
680 if (target < limit->p2.dot_limit)
681 clock.p2 = limit->p2.p2_slow;
682 else
683 clock.p2 = limit->p2.p2_fast;
684 }
685
686 memset(best_clock, 0, sizeof(*best_clock));
687 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200688 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800689 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200690 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800691 for (clock.m1 = limit->m1.max;
692 clock.m1 >= limit->m1.min; clock.m1--) {
693 for (clock.m2 = limit->m2.max;
694 clock.m2 >= limit->m2.min; clock.m2--) {
695 for (clock.p1 = limit->p1.max;
696 clock.p1 >= limit->p1.min; clock.p1--) {
697 int this_err;
698
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200699 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800702 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000703
704 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800705 if (this_err < err_most) {
706 *best_clock = clock;
707 err_most = this_err;
708 max_n = clock.n;
709 found = true;
710 }
711 }
712 }
713 }
714 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800715 return found;
716}
Ma Lingd4906092009-03-18 20:13:27 +0800717
Zhenyu Wang2c072452009-06-05 15:38:42 +0800718static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200719vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700722{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300723 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300724 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300725 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300726 /* min update 19.2 MHz */
727 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300728 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700729
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300730 target *= 5; /* fast clock */
731
732 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700733
734 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300736 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300737 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300738 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300739 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700740 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300741 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300742 unsigned int ppm, diff;
743
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300744 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
745 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300746
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300747 vlv_clock(refclk, &clock);
748
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300751 continue;
752
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300753 diff = abs(clock.dot - target);
754 ppm = div_u64(1000000ULL * diff, target);
755
756 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300757 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300758 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300759 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300760 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300761
Ville Syrjäläc6861222013-09-24 21:26:21 +0300762 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300763 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300764 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300765 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700766 }
767 }
768 }
769 }
770 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700771
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300772 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700773}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700774
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300775static bool
776chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779{
780 struct drm_device *dev = crtc->dev;
781 intel_clock_t clock;
782 uint64_t m2;
783 int found = false;
784
785 memset(best_clock, 0, sizeof(*best_clock));
786
787 /*
788 * Based on hardware doc, the n always set to 1, and m1 always
789 * set to 2. If requires to support 200Mhz refclk, we need to
790 * revisit this because n may not 1 anymore.
791 */
792 clock.n = 1, clock.m1 = 2;
793 target *= 5; /* fast clock */
794
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast;
797 clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799
800 clock.p = clock.p1 * clock.p2;
801
802 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
803 clock.n) << 22, refclk * clock.m1);
804
805 if (m2 > INT_MAX/clock.m1)
806 continue;
807
808 clock.m2 = m2;
809
810 chv_clock(refclk, &clock);
811
812 if (!intel_PLL_is_valid(dev, limit, &clock))
813 continue;
814
815 /* based on hardware requirement, prefer bigger p
816 */
817 if (clock.p > best_clock->p) {
818 *best_clock = clock;
819 found = true;
820 }
821 }
822 }
823
824 return found;
825}
826
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300827bool intel_crtc_active(struct drm_crtc *crtc)
828{
829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830
831 /* Be paranoid as we can arrive here with only partial
832 * state retrieved from the hardware during setup.
833 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100834 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300835 * as Haswell has gained clock readout/fastboot support.
836 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000837 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300838 * properly reconstruct framebuffers.
839 */
Matt Roperf4510a22014-04-01 15:22:40 -0700840 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100841 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300842}
843
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200844enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
845 enum pipe pipe)
846{
847 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
849
Daniel Vetter3b117c82013-04-17 20:15:07 +0200850 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200851}
852
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200853static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
Paulo Zanonia928d532012-05-04 17:18:15 -0300854{
855 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200856 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300857
858 frame = I915_READ(frame_reg);
859
860 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
Jesse Barnes93937072014-04-04 16:12:09 -0700861 WARN(1, "vblank wait timed out\n");
Paulo Zanonia928d532012-05-04 17:18:15 -0300862}
863
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700864/**
865 * intel_wait_for_vblank - wait for vblank on a given pipe
866 * @dev: drm device
867 * @pipe: pipe to wait for
868 *
869 * Wait for vblank to occur on a given pipe. Needed for various bits of
870 * mode setting code.
871 */
872void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800873{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700874 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800875 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700876
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200877 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
878 g4x_wait_for_vblank(dev, pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300879 return;
880 }
881
Chris Wilson300387c2010-09-05 20:25:43 +0100882 /* Clear existing vblank status. Note this will clear any other
883 * sticky status fields as well.
884 *
885 * This races with i915_driver_irq_handler() with the result
886 * that either function could miss a vblank event. Here it is not
887 * fatal, as we will either wait upon the next vblank interrupt or
888 * timeout. Generally speaking intel_wait_for_vblank() is only
889 * called during modeset at which time the GPU should be idle and
890 * should *not* be performing page flips and thus not waiting on
891 * vblanks...
892 * Currently, the result of us stealing a vblank from the irq
893 * handler is that a single frame will be skipped during swapbuffers.
894 */
895 I915_WRITE(pipestat_reg,
896 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
897
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700898 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100899 if (wait_for(I915_READ(pipestat_reg) &
900 PIPE_VBLANK_INTERRUPT_STATUS,
901 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700902 DRM_DEBUG_KMS("vblank wait timed out\n");
903}
904
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300905static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
906{
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 u32 reg = PIPEDSL(pipe);
909 u32 line1, line2;
910 u32 line_mask;
911
912 if (IS_GEN2(dev))
913 line_mask = DSL_LINEMASK_GEN2;
914 else
915 line_mask = DSL_LINEMASK_GEN3;
916
917 line1 = I915_READ(reg) & line_mask;
918 mdelay(5);
919 line2 = I915_READ(reg) & line_mask;
920
921 return line1 == line2;
922}
923
Keith Packardab7ad7f2010-10-03 00:33:06 -0700924/*
925 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700926 * @dev: drm device
927 * @pipe: pipe to wait for
928 *
929 * After disabling a pipe, we can't wait for vblank in the usual way,
930 * spinning on the vblank interrupt status bit, since we won't actually
931 * see an interrupt when the pipe is disabled.
932 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700933 * On Gen4 and above:
934 * wait for the pipe register state bit to turn off
935 *
936 * Otherwise:
937 * wait for the display line value to settle (it usually
938 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100939 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700940 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100941void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700942{
943 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200944 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
945 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700946
Keith Packardab7ad7f2010-10-03 00:33:06 -0700947 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200948 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700949
Keith Packardab7ad7f2010-10-03 00:33:06 -0700950 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100951 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
952 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200953 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700954 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700955 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300956 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200957 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700958 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800959}
960
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000961/*
962 * ibx_digital_port_connected - is the specified port connected?
963 * @dev_priv: i915 private structure
964 * @port: the port to test
965 *
966 * Returns true if @port is connected, false otherwise.
967 */
968bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
969 struct intel_digital_port *port)
970{
971 u32 bit;
972
Damien Lespiauc36346e2012-12-13 16:09:03 +0000973 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +0200974 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000975 case PORT_B:
976 bit = SDE_PORTB_HOTPLUG;
977 break;
978 case PORT_C:
979 bit = SDE_PORTC_HOTPLUG;
980 break;
981 case PORT_D:
982 bit = SDE_PORTD_HOTPLUG;
983 break;
984 default:
985 return true;
986 }
987 } else {
Robin Schroereba905b2014-05-18 02:24:50 +0200988 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000989 case PORT_B:
990 bit = SDE_PORTB_HOTPLUG_CPT;
991 break;
992 case PORT_C:
993 bit = SDE_PORTC_HOTPLUG_CPT;
994 break;
995 case PORT_D:
996 bit = SDE_PORTD_HOTPLUG_CPT;
997 break;
998 default:
999 return true;
1000 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001001 }
1002
1003 return I915_READ(SDEISR) & bit;
1004}
1005
Jesse Barnesb24e7172011-01-04 15:09:30 -08001006static const char *state_string(bool enabled)
1007{
1008 return enabled ? "on" : "off";
1009}
1010
1011/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001012void assert_pll(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001014{
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = DPLL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & DPLL_VCO_ENABLE);
1022 WARN(cur_state != state,
1023 "PLL state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001026
Jani Nikula23538ef2013-08-27 15:12:22 +03001027/* XXX: the dsi pll is shared between MIPI DSI ports */
1028static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029{
1030 u32 val;
1031 bool cur_state;
1032
1033 mutex_lock(&dev_priv->dpio_lock);
1034 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035 mutex_unlock(&dev_priv->dpio_lock);
1036
1037 cur_state = val & DSI_PLL_VCO_EN;
1038 WARN(cur_state != state,
1039 "DSI PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1041}
1042#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
Daniel Vetter55607e82013-06-16 21:42:39 +02001045struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001046intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001047{
Daniel Vettere2b78262013-06-07 23:10:03 +02001048 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
Daniel Vettera43f6e02013-06-07 23:10:32 +02001050 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001051 return NULL;
1052
Daniel Vettera43f6e02013-06-07 23:10:32 +02001053 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001054}
1055
Jesse Barnesb24e7172011-01-04 15:09:30 -08001056/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001057void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058 struct intel_shared_dpll *pll,
1059 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001060{
Jesse Barnes040484a2011-01-03 12:14:26 -08001061 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001062 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001063
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001064 if (HAS_PCH_LPT(dev_priv->dev)) {
1065 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066 return;
1067 }
1068
Chris Wilson92b27b02012-05-20 18:10:50 +01001069 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001070 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001072
Daniel Vetter53589012013-06-05 13:34:16 +02001073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001074 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001077}
Jesse Barnes040484a2011-01-03 12:14:26 -08001078
1079static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081{
1082 int reg;
1083 u32 val;
1084 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001087
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001091 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101}
1102#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107{
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118}
1119#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001130 return;
1131
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001133 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001134 return;
1135
Jesse Barnes040484a2011-01-03 12:14:26 -08001136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139}
1140
Daniel Vetter55607e82013-06-16 21:42:39 +02001141void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001143{
1144 int reg;
1145 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001146 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001154}
1155
Jesse Barnesea0760c2011-01-04 15:09:32 -08001156static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158{
1159 int pp_reg, lvds_reg;
1160 u32 val;
1161 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001162 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001163
1164 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165 pp_reg = PCH_PP_CONTROL;
1166 lvds_reg = PCH_LVDS;
1167 } else {
1168 pp_reg = PP_CONTROL;
1169 lvds_reg = LVDS;
1170 }
1171
1172 val = I915_READ(pp_reg);
1173 if (!(val & PANEL_POWER_ON) ||
1174 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175 locked = false;
1176
1177 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179
1180 WARN(panel_pipe == pipe && locked,
1181 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001182 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001183}
1184
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001185static void assert_cursor(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187{
1188 struct drm_device *dev = dev_priv->dev;
1189 bool cur_state;
1190
Paulo Zanonid9d82082014-02-27 16:30:56 -03001191 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001192 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001193 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001194 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001195
1196 WARN(cur_state != state,
1197 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198 pipe_name(pipe), state_string(state), state_string(cur_state));
1199}
1200#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001203void assert_pipe(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001205{
1206 int reg;
1207 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001208 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001209 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001211
Daniel Vetter8e636782012-01-22 01:36:48 +01001212 /* if we need the pipe A quirk it must be always on */
1213 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214 state = true;
1215
Imre Deakda7e29b2014-02-18 00:02:02 +02001216 if (!intel_display_power_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001217 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001218 cur_state = false;
1219 } else {
1220 reg = PIPECONF(cpu_transcoder);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 }
1224
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001225 WARN(cur_state != state,
1226 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001227 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001228}
1229
Chris Wilson931872f2012-01-16 23:01:13 +00001230static void assert_plane(struct drm_i915_private *dev_priv,
1231 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001232{
1233 int reg;
1234 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001235 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001236
1237 reg = DSPCNTR(plane);
1238 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001239 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240 WARN(cur_state != state,
1241 "plane %c assertion failure (expected %s, current %s)\n",
1242 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001243}
1244
Chris Wilson931872f2012-01-16 23:01:13 +00001245#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
Jesse Barnesb24e7172011-01-04 15:09:30 -08001248static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249 enum pipe pipe)
1250{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001251 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
Ville Syrjälä653e1022013-06-04 13:49:05 +03001256 /* Primary planes are fixed to pipes on gen4+ */
1257 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001260 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001263 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001264 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001265
Jesse Barnesb24e7172011-01-04 15:09:30 -08001266 /* Need to check both planes against the pipe */
Damien Lespiau08e2a7d2013-07-11 20:10:54 +01001267 for_each_pipe(i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001275 }
1276}
1277
Jesse Barnes19332d72013-03-28 09:55:38 -07001278static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe)
1280{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001281 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001282 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001283 u32 val;
1284
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001285 if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001286 for_each_sprite(pipe, sprite) {
1287 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001288 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001289 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001291 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001292 }
1293 } else if (INTEL_INFO(dev)->gen >= 7) {
1294 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001295 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001296 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001297 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001298 plane_name(pipe), pipe_name(pipe));
1299 } else if (INTEL_INFO(dev)->gen >= 5) {
1300 reg = DVSCNTR(pipe);
1301 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001302 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001303 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001305 }
1306}
1307
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001308static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001309{
1310 u32 val;
1311 bool enabled;
1312
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001313 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001314
Jesse Barnes92f25842011-01-04 15:09:34 -08001315 val = I915_READ(PCH_DREF_CONTROL);
1316 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317 DREF_SUPERSPREAD_SOURCE_MASK));
1318 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319}
1320
Daniel Vetterab9412b2013-05-03 11:49:46 +02001321static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001323{
1324 int reg;
1325 u32 val;
1326 bool enabled;
1327
Daniel Vetterab9412b2013-05-03 11:49:46 +02001328 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001329 val = I915_READ(reg);
1330 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001331 WARN(enabled,
1332 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001334}
1335
Keith Packard4e634382011-08-06 10:39:45 -07001336static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001338{
1339 if ((val & DP_PORT_EN) == 0)
1340 return false;
1341
1342 if (HAS_PCH_CPT(dev_priv->dev)) {
1343 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001347 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001350 } else {
1351 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352 return false;
1353 }
1354 return true;
1355}
1356
Keith Packard1519b992011-08-06 10:35:34 -07001357static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, u32 val)
1359{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001360 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001361 return false;
1362
1363 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001364 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001365 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001366 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001369 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001370 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001371 return false;
1372 }
1373 return true;
1374}
1375
1376static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377 enum pipe pipe, u32 val)
1378{
1379 if ((val & LVDS_PORT_EN) == 0)
1380 return false;
1381
1382 if (HAS_PCH_CPT(dev_priv->dev)) {
1383 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384 return false;
1385 } else {
1386 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387 return false;
1388 }
1389 return true;
1390}
1391
1392static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394{
1395 if ((val & ADPA_DAC_ENABLE) == 0)
1396 return false;
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399 return false;
1400 } else {
1401 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402 return false;
1403 }
1404 return true;
1405}
1406
Jesse Barnes291906f2011-02-02 12:28:03 -08001407static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001408 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001409{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001410 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001411 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001412 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001413 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001414
Daniel Vetter75c5da22012-09-10 21:58:29 +02001415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001417 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001418}
1419
1420static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, int reg)
1422{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001423 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001424 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001425 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001426 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001427
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001428 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001429 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001430 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001431}
1432
1433static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001438
Keith Packardf0575e92011-07-25 22:12:43 -07001439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001442
1443 reg = PCH_ADPA;
1444 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001445 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001446 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001447 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001448
1449 reg = PCH_LVDS;
1450 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001451 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001452 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001453 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001454
Paulo Zanonie2debe92013-02-18 19:00:27 -03001455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001458}
1459
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001460static void intel_init_dpio(struct drm_device *dev)
1461{
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 if (!IS_VALLEYVIEW(dev))
1465 return;
1466
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001467 /*
1468 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469 * CHV x1 PHY (DP/HDMI D)
1470 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471 */
1472 if (IS_CHERRYVIEW(dev)) {
1473 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475 } else {
1476 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001478}
1479
1480static void intel_reset_dpio(struct drm_device *dev)
1481{
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484 if (!IS_VALLEYVIEW(dev))
1485 return;
1486
Imre Deake5cbfbf2014-01-09 17:08:16 +02001487 /*
1488 * Enable the CRI clock source so we can get at the display and the
1489 * reference clock for VGA hotplug / manual detection.
1490 */
Imre Deak404faab2014-01-09 17:08:15 +02001491 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
Imre Deake5cbfbf2014-01-09 17:08:16 +02001492 DPLL_REFA_CLK_ENABLE_VLV |
Imre Deak404faab2014-01-09 17:08:15 +02001493 DPLL_INTEGRATED_CRI_CLK_VLV);
1494
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001495 if (IS_CHERRYVIEW(dev)) {
1496 enum dpio_phy phy;
1497 u32 val;
1498
1499 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1500 /* Poll for phypwrgood signal */
1501 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1502 PHY_POWERGOOD(phy), 1))
1503 DRM_ERROR("Display PHY %d is not power up\n", phy);
1504
1505 /*
1506 * Deassert common lane reset for PHY.
1507 *
1508 * This should only be done on init and resume from S3
1509 * with both PLLs disabled, or we risk losing DPIO and
1510 * PLL synchronization.
1511 */
1512 val = I915_READ(DISPLAY_PHY_CONTROL);
1513 I915_WRITE(DISPLAY_PHY_CONTROL,
1514 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1515 }
1516
1517 } else {
1518 /*
1519 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1520 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1521 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1522 * b. The other bits such as sfr settings / modesel may all
1523 * be set to 0.
1524 *
1525 * This should only be done on init and resume from S3 with
1526 * both PLLs disabled, or we risk losing DPIO and PLL
1527 * synchronization.
1528 */
1529 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1530 }
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001531}
1532
Daniel Vetter426115c2013-07-11 22:13:42 +02001533static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001534{
Daniel Vetter426115c2013-07-11 22:13:42 +02001535 struct drm_device *dev = crtc->base.dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 int reg = DPLL(crtc->pipe);
1538 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001539
Daniel Vetter426115c2013-07-11 22:13:42 +02001540 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001541
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001542 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001543 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1544
1545 /* PLL is protected by panel, make sure we can write it */
1546 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001547 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001548
Daniel Vetter426115c2013-07-11 22:13:42 +02001549 I915_WRITE(reg, dpll);
1550 POSTING_READ(reg);
1551 udelay(150);
1552
1553 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1555
1556 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1557 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001558
1559 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001560 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001561 POSTING_READ(reg);
1562 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001563 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001564 POSTING_READ(reg);
1565 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001566 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569}
1570
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001571static void chv_enable_pll(struct intel_crtc *crtc)
1572{
1573 struct drm_device *dev = crtc->base.dev;
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 int pipe = crtc->pipe;
1576 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001577 u32 tmp;
1578
1579 assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1582
1583 mutex_lock(&dev_priv->dpio_lock);
1584
1585 /* Enable back the 10bit clock to display controller */
1586 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587 tmp |= DPIO_DCLKP_EN;
1588 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590 /*
1591 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1592 */
1593 udelay(1);
1594
1595 /* Enable PLL */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001596 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001597
1598 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001599 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001600 DRM_ERROR("PLL %d failed to lock\n", pipe);
1601
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001602 /* not sure when this should be written */
1603 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1604 POSTING_READ(DPLL_MD(pipe));
1605
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001606 mutex_unlock(&dev_priv->dpio_lock);
1607}
1608
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001609static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001610{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001615
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001616 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001617
1618 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001619 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001620
1621 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001624
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001625 I915_WRITE(reg, dpll);
1626
1627 /* Wait for the clocks to stabilize. */
1628 POSTING_READ(reg);
1629 udelay(150);
1630
1631 if (INTEL_INFO(dev)->gen >= 4) {
1632 I915_WRITE(DPLL_MD(crtc->pipe),
1633 crtc->config.dpll_hw_state.dpll_md);
1634 } else {
1635 /* The pixel multiplier can only be updated once the
1636 * DPLL is enabled and the clocks are stable.
1637 *
1638 * So write it again.
1639 */
1640 I915_WRITE(reg, dpll);
1641 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001642
1643 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001644 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001647 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001650 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653}
1654
1655/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001656 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001657 * @dev_priv: i915 private structure
1658 * @pipe: pipe PLL to disable
1659 *
1660 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 *
1662 * Note! This is for pre-ILK only.
1663 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001664static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001665{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001666 /* Don't disable pipe A or pipe A PLLs if needed */
1667 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1668 return;
1669
1670 /* Make sure the pipe isn't still relying on us */
1671 assert_pipe_disabled(dev_priv, pipe);
1672
Daniel Vetter50b44a42013-06-05 13:34:33 +02001673 I915_WRITE(DPLL(pipe), 0);
1674 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001675}
1676
Jesse Barnesf6071162013-10-01 10:41:38 -07001677static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1678{
1679 u32 val = 0;
1680
1681 /* Make sure the pipe isn't still relying on us */
1682 assert_pipe_disabled(dev_priv, pipe);
1683
Imre Deake5cbfbf2014-01-09 17:08:16 +02001684 /*
1685 * Leave integrated clock source and reference clock enabled for pipe B.
1686 * The latter is needed for VGA hotplug / manual detection.
1687 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001688 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001689 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001690 I915_WRITE(DPLL(pipe), val);
1691 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001692
1693}
1694
1695static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001697 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001698 u32 val;
1699
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001700 /* Make sure the pipe isn't still relying on us */
1701 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001702
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001703 /* Set PLL en = 0 */
1704 val = DPLL_SSC_REF_CLOCK_CHV;
1705 if (pipe != PIPE_A)
1706 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001709
1710 mutex_lock(&dev_priv->dpio_lock);
1711
1712 /* Disable 10bit clock to display controller */
1713 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1714 val &= ~DPIO_DCLKP_EN;
1715 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1716
1717 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001718}
1719
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001720void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1721 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001722{
1723 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001724 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001725
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001726 switch (dport->port) {
1727 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001728 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001729 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001730 break;
1731 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001732 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001733 dpll_reg = DPLL(0);
1734 break;
1735 case PORT_D:
1736 port_mask = DPLL_PORTD_READY_MASK;
1737 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001738 break;
1739 default:
1740 BUG();
1741 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001742
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001743 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001744 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001745 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001746}
1747
Daniel Vetterb14b1052014-04-24 23:55:13 +02001748static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1749{
1750 struct drm_device *dev = crtc->base.dev;
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1753
1754 WARN_ON(!pll->refcount);
1755 if (pll->active == 0) {
1756 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1757 WARN_ON(pll->on);
1758 assert_shared_dpll_disabled(dev_priv, pll);
1759
1760 pll->mode_set(dev_priv, pll);
1761 }
1762}
1763
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001764/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001765 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to enable
1768 *
1769 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1770 * drives the transcoder clock.
1771 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001772static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001773{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001774 struct drm_device *dev = crtc->base.dev;
1775 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001776 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001777
Daniel Vetter87a875b2013-06-05 13:34:19 +02001778 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001779 return;
1780
1781 if (WARN_ON(pll->refcount == 0))
1782 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001783
Daniel Vetter46edb022013-06-05 13:34:12 +02001784 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1785 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001786 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001787
Daniel Vettercdbd2312013-06-05 13:34:03 +02001788 if (pll->active++) {
1789 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001790 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001791 return;
1792 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001793 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001794
Daniel Vetter46edb022013-06-05 13:34:12 +02001795 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001796 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001797 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001798}
1799
Daniel Vettere2b78262013-06-07 23:10:03 +02001800static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001801{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001805
Jesse Barnes92f25842011-01-04 15:09:34 -08001806 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001807 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001808 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001809 return;
1810
Chris Wilson48da64a2012-05-13 20:16:12 +01001811 if (WARN_ON(pll->refcount == 0))
1812 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001813
Daniel Vetter46edb022013-06-05 13:34:12 +02001814 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001816 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001817
Chris Wilson48da64a2012-05-13 20:16:12 +01001818 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001819 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001820 return;
1821 }
1822
Daniel Vettere9d69442013-06-05 13:34:15 +02001823 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001824 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001825 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001826 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001827
Daniel Vetter46edb022013-06-05 13:34:12 +02001828 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001829 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001830 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001831}
1832
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001833static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1834 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001835{
Daniel Vetter23670b322012-11-01 09:15:30 +01001836 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001837 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001839 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001840
1841 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001842 BUG_ON(INTEL_INFO(dev)->gen < 5);
Jesse Barnes040484a2011-01-03 12:14:26 -08001843
1844 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001845 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001846 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001847
1848 /* FDI must be feeding us bits for PCH ports */
1849 assert_fdi_tx_enabled(dev_priv, pipe);
1850 assert_fdi_rx_enabled(dev_priv, pipe);
1851
Daniel Vetter23670b322012-11-01 09:15:30 +01001852 if (HAS_PCH_CPT(dev)) {
1853 /* Workaround: Set the timing override bit before enabling the
1854 * pch transcoder. */
1855 reg = TRANS_CHICKEN2(pipe);
1856 val = I915_READ(reg);
1857 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001859 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001860
Daniel Vetterab9412b2013-05-03 11:49:46 +02001861 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001862 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001863 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001864
1865 if (HAS_PCH_IBX(dev_priv->dev)) {
1866 /*
1867 * make the BPC in transcoder be consistent with
1868 * that in pipeconf reg.
1869 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001870 val &= ~PIPECONF_BPC_MASK;
1871 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001872 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001873
1874 val &= ~TRANS_INTERLACE_MASK;
1875 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001876 if (HAS_PCH_IBX(dev_priv->dev) &&
1877 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1878 val |= TRANS_LEGACY_INTERLACED_ILK;
1879 else
1880 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001881 else
1882 val |= TRANS_PROGRESSIVE;
1883
Jesse Barnes040484a2011-01-03 12:14:26 -08001884 I915_WRITE(reg, val | TRANS_ENABLE);
1885 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001886 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001887}
1888
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001889static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001890 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001891{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001892 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001893
1894 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001895 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001896
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001897 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001898 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001899 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001900
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001901 /* Workaround: set timing override bit. */
1902 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001903 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001904 I915_WRITE(_TRANSA_CHICKEN2, val);
1905
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001906 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001907 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001908
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001909 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1910 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001911 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001912 else
1913 val |= TRANS_PROGRESSIVE;
1914
Daniel Vetterab9412b2013-05-03 11:49:46 +02001915 I915_WRITE(LPT_TRANSCONF, val);
1916 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001917 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001918}
1919
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001920static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1921 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001922{
Daniel Vetter23670b322012-11-01 09:15:30 +01001923 struct drm_device *dev = dev_priv->dev;
1924 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001925
1926 /* FDI relies on the transcoder */
1927 assert_fdi_tx_disabled(dev_priv, pipe);
1928 assert_fdi_rx_disabled(dev_priv, pipe);
1929
Jesse Barnes291906f2011-02-02 12:28:03 -08001930 /* Ports must be off as well */
1931 assert_pch_ports_disabled(dev_priv, pipe);
1932
Daniel Vetterab9412b2013-05-03 11:49:46 +02001933 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001934 val = I915_READ(reg);
1935 val &= ~TRANS_ENABLE;
1936 I915_WRITE(reg, val);
1937 /* wait for PCH transcoder off, transcoder state */
1938 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001939 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001940
1941 if (!HAS_PCH_IBX(dev)) {
1942 /* Workaround: Clear the timing override chicken bit again. */
1943 reg = TRANS_CHICKEN2(pipe);
1944 val = I915_READ(reg);
1945 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1946 I915_WRITE(reg, val);
1947 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001948}
1949
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001950static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001951{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001952 u32 val;
1953
Daniel Vetterab9412b2013-05-03 11:49:46 +02001954 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001955 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001956 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001957 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001958 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001959 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001960
1961 /* Workaround: clear timing override bit. */
1962 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001963 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001964 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001965}
1966
1967/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001968 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02001969 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001970 *
Paulo Zanoni03722642014-01-17 13:51:09 -02001971 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001972 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08001973 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02001974static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001975{
Paulo Zanoni03722642014-01-17 13:51:09 -02001976 struct drm_device *dev = crtc->base.dev;
1977 struct drm_i915_private *dev_priv = dev->dev_private;
1978 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001979 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1980 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001981 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001982 int reg;
1983 u32 val;
1984
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001985 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001986 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001987 assert_sprites_disabled(dev_priv, pipe);
1988
Paulo Zanoni681e5812012-12-06 11:12:38 -02001989 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001990 pch_transcoder = TRANSCODER_A;
1991 else
1992 pch_transcoder = pipe;
1993
Jesse Barnesb24e7172011-01-04 15:09:30 -08001994 /*
1995 * A pipe without a PLL won't actually be able to drive bits from
1996 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1997 * need the check.
1998 */
1999 if (!HAS_PCH_SPLIT(dev_priv->dev))
Paulo Zanonifbf32182014-01-17 13:51:11 -02002000 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002001 assert_dsi_pll_enabled(dev_priv);
2002 else
2003 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002004 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002005 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002006 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002007 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002008 assert_fdi_tx_pll_enabled(dev_priv,
2009 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002010 }
2011 /* FIXME: assert CPU port conditions for SNB+ */
2012 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002013
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002014 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002015 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002016 if (val & PIPECONF_ENABLE) {
2017 WARN_ON(!(pipe == PIPE_A &&
2018 dev_priv->quirks & QUIRK_PIPEA_FORCE));
Chris Wilson00d70b12011-03-17 07:18:29 +00002019 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002020 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002021
2022 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002023 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002024}
2025
2026/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002027 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002028 * @dev_priv: i915 private structure
2029 * @pipe: pipe to disable
2030 *
2031 * Disable @pipe, making sure that various hardware specific requirements
2032 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2033 *
2034 * @pipe should be %PIPE_A or %PIPE_B.
2035 *
2036 * Will wait until the pipe has shut down before returning.
2037 */
2038static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2039 enum pipe pipe)
2040{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002041 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2042 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002043 int reg;
2044 u32 val;
2045
2046 /*
2047 * Make sure planes won't keep trying to pump pixels to us,
2048 * or we might hang the display.
2049 */
2050 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002051 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002052 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002053
2054 /* Don't disable pipe A or pipe A PLLs if needed */
2055 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2056 return;
2057
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002058 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002059 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002060 if ((val & PIPECONF_ENABLE) == 0)
2061 return;
2062
2063 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002064 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2065}
2066
Keith Packardd74362c2011-07-28 14:47:14 -07002067/*
2068 * Plane regs are double buffered, going from enabled->disabled needs a
2069 * trigger in order to latch. The display address reg provides this.
2070 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002071void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2072 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002073{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002074 struct drm_device *dev = dev_priv->dev;
2075 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002076
2077 I915_WRITE(reg, I915_READ(reg));
2078 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002079}
2080
Jesse Barnesb24e7172011-01-04 15:09:30 -08002081/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002082 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002083 * @dev_priv: i915 private structure
2084 * @plane: plane to enable
2085 * @pipe: pipe being fed
2086 *
2087 * Enable @plane on @pipe, making sure that @pipe is running first.
2088 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002089static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2090 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002091{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002092 struct intel_crtc *intel_crtc =
2093 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002094 int reg;
2095 u32 val;
2096
2097 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2098 assert_pipe_enabled(dev_priv, pipe);
2099
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002100 if (intel_crtc->primary_enabled)
2101 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002102
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002103 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002104
Jesse Barnesb24e7172011-01-04 15:09:30 -08002105 reg = DSPCNTR(plane);
2106 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002107 WARN_ON(val & DISPLAY_PLANE_ENABLE);
Chris Wilson00d70b12011-03-17 07:18:29 +00002108
2109 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002110 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002111}
2112
Jesse Barnesb24e7172011-01-04 15:09:30 -08002113/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002114 * intel_disable_primary_hw_plane - disable the primary hardware plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002115 * @dev_priv: i915 private structure
2116 * @plane: plane to disable
2117 * @pipe: pipe consuming the data
2118 *
2119 * Disable @plane; should be an independent operation.
2120 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002121static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2122 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002123{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002124 struct intel_crtc *intel_crtc =
2125 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002126 int reg;
2127 u32 val;
2128
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002129 if (!intel_crtc->primary_enabled)
2130 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002131
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002132 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002133
Jesse Barnesb24e7172011-01-04 15:09:30 -08002134 reg = DSPCNTR(plane);
2135 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002136 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
Chris Wilson00d70b12011-03-17 07:18:29 +00002137
2138 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002139 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002140}
2141
Chris Wilson693db182013-03-05 14:52:39 +00002142static bool need_vtd_wa(struct drm_device *dev)
2143{
2144#ifdef CONFIG_INTEL_IOMMU
2145 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2146 return true;
2147#endif
2148 return false;
2149}
2150
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002151static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2152{
2153 int tile_height;
2154
2155 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2156 return ALIGN(height, tile_height);
2157}
2158
Chris Wilson127bd2a2010-07-23 23:32:05 +01002159int
Chris Wilson48b956c2010-09-14 12:50:34 +01002160intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002161 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002162 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002163{
Chris Wilsonce453d82011-02-21 14:43:56 +00002164 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002165 u32 alignment;
2166 int ret;
2167
Chris Wilson05394f32010-11-08 19:18:58 +00002168 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002169 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002170 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2171 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002172 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002173 alignment = 4 * 1024;
2174 else
2175 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002176 break;
2177 case I915_TILING_X:
2178 /* pin() will align the object as required by fence */
2179 alignment = 0;
2180 break;
2181 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002182 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002183 return -EINVAL;
2184 default:
2185 BUG();
2186 }
2187
Chris Wilson693db182013-03-05 14:52:39 +00002188 /* Note that the w/a also requires 64 PTE of padding following the
2189 * bo. We currently fill all unused PTE with the shadow page and so
2190 * we should always have valid PTE following the scanout preventing
2191 * the VT-d warning.
2192 */
2193 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2194 alignment = 256 * 1024;
2195
Chris Wilsonce453d82011-02-21 14:43:56 +00002196 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002197 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002198 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002199 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002200
2201 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2202 * fence, whereas 965+ only requires a fence if using
2203 * framebuffer compression. For simplicity, we always install
2204 * a fence as the cost is not that onerous.
2205 */
Chris Wilson06d98132012-04-17 15:31:24 +01002206 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002207 if (ret)
2208 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002209
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002210 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002211
Chris Wilsonce453d82011-02-21 14:43:56 +00002212 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002213 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002214
2215err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002216 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002217err_interruptible:
2218 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002219 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002220}
2221
Chris Wilson1690e1e2011-12-14 13:57:08 +01002222void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2223{
2224 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002225 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002226}
2227
Daniel Vetterc2c75132012-07-05 12:17:30 +02002228/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2229 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002230unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2231 unsigned int tiling_mode,
2232 unsigned int cpp,
2233 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002234{
Chris Wilsonbc752862013-02-21 20:04:31 +00002235 if (tiling_mode != I915_TILING_NONE) {
2236 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002237
Chris Wilsonbc752862013-02-21 20:04:31 +00002238 tile_rows = *y / 8;
2239 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002240
Chris Wilsonbc752862013-02-21 20:04:31 +00002241 tiles = *x / (512/cpp);
2242 *x %= 512/cpp;
2243
2244 return tile_rows * pitch * 8 + tiles * 4096;
2245 } else {
2246 unsigned int offset;
2247
2248 offset = *y * pitch + *x * cpp;
2249 *y = 0;
2250 *x = (offset & 4095) / cpp;
2251 return offset & -4096;
2252 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002253}
2254
Jesse Barnes46f297f2014-03-07 08:57:48 -08002255int intel_format_to_fourcc(int format)
2256{
2257 switch (format) {
2258 case DISPPLANE_8BPP:
2259 return DRM_FORMAT_C8;
2260 case DISPPLANE_BGRX555:
2261 return DRM_FORMAT_XRGB1555;
2262 case DISPPLANE_BGRX565:
2263 return DRM_FORMAT_RGB565;
2264 default:
2265 case DISPPLANE_BGRX888:
2266 return DRM_FORMAT_XRGB8888;
2267 case DISPPLANE_RGBX888:
2268 return DRM_FORMAT_XBGR8888;
2269 case DISPPLANE_BGRX101010:
2270 return DRM_FORMAT_XRGB2101010;
2271 case DISPPLANE_RGBX101010:
2272 return DRM_FORMAT_XBGR2101010;
2273 }
2274}
2275
Jesse Barnes484b41d2014-03-07 08:57:55 -08002276static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002277 struct intel_plane_config *plane_config)
2278{
2279 struct drm_device *dev = crtc->base.dev;
2280 struct drm_i915_gem_object *obj = NULL;
2281 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2282 u32 base = plane_config->base;
2283
Chris Wilsonff2652e2014-03-10 08:07:02 +00002284 if (plane_config->size == 0)
2285 return false;
2286
Jesse Barnes46f297f2014-03-07 08:57:48 -08002287 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2288 plane_config->size);
2289 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002290 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002291
2292 if (plane_config->tiled) {
2293 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002294 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002295 }
2296
Dave Airlie66e514c2014-04-03 07:51:54 +10002297 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2298 mode_cmd.width = crtc->base.primary->fb->width;
2299 mode_cmd.height = crtc->base.primary->fb->height;
2300 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002301
2302 mutex_lock(&dev->struct_mutex);
2303
Dave Airlie66e514c2014-04-03 07:51:54 +10002304 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002305 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002306 DRM_DEBUG_KMS("intel fb init failed\n");
2307 goto out_unref_obj;
2308 }
2309
2310 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002311
2312 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2313 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002314
2315out_unref_obj:
2316 drm_gem_object_unreference(&obj->base);
2317 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002318 return false;
2319}
2320
2321static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2322 struct intel_plane_config *plane_config)
2323{
2324 struct drm_device *dev = intel_crtc->base.dev;
2325 struct drm_crtc *c;
2326 struct intel_crtc *i;
2327 struct intel_framebuffer *fb;
2328
Dave Airlie66e514c2014-04-03 07:51:54 +10002329 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002330 return;
2331
2332 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2333 return;
2334
Dave Airlie66e514c2014-04-03 07:51:54 +10002335 kfree(intel_crtc->base.primary->fb);
2336 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002337
2338 /*
2339 * Failed to alloc the obj, check to see if we should share
2340 * an fb with another CRTC instead
2341 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002342 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002343 i = to_intel_crtc(c);
2344
2345 if (c == &intel_crtc->base)
2346 continue;
2347
Dave Airlie66e514c2014-04-03 07:51:54 +10002348 if (!i->active || !c->primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002349 continue;
2350
Dave Airlie66e514c2014-04-03 07:51:54 +10002351 fb = to_intel_framebuffer(c->primary->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002352 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
Dave Airlie66e514c2014-04-03 07:51:54 +10002353 drm_framebuffer_reference(c->primary->fb);
2354 intel_crtc->base.primary->fb = c->primary->fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002355 break;
2356 }
2357 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002358}
2359
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002360static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2361 struct drm_framebuffer *fb,
2362 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002363{
2364 struct drm_device *dev = crtc->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002368 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002369 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002370 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002371 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002372 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002373
Jesse Barnes81255562010-08-02 12:07:50 -07002374 intel_fb = to_intel_framebuffer(fb);
2375 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002376
Chris Wilson5eddb702010-09-11 13:48:45 +01002377 reg = DSPCNTR(plane);
2378 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002379 /* Mask out pixel format bits in case we change it */
2380 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002381 switch (fb->pixel_format) {
2382 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002383 dspcntr |= DISPPLANE_8BPP;
2384 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002385 case DRM_FORMAT_XRGB1555:
2386 case DRM_FORMAT_ARGB1555:
2387 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002388 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002389 case DRM_FORMAT_RGB565:
2390 dspcntr |= DISPPLANE_BGRX565;
2391 break;
2392 case DRM_FORMAT_XRGB8888:
2393 case DRM_FORMAT_ARGB8888:
2394 dspcntr |= DISPPLANE_BGRX888;
2395 break;
2396 case DRM_FORMAT_XBGR8888:
2397 case DRM_FORMAT_ABGR8888:
2398 dspcntr |= DISPPLANE_RGBX888;
2399 break;
2400 case DRM_FORMAT_XRGB2101010:
2401 case DRM_FORMAT_ARGB2101010:
2402 dspcntr |= DISPPLANE_BGRX101010;
2403 break;
2404 case DRM_FORMAT_XBGR2101010:
2405 case DRM_FORMAT_ABGR2101010:
2406 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002407 break;
2408 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002409 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002410 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002411
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002412 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002413 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002414 dspcntr |= DISPPLANE_TILED;
2415 else
2416 dspcntr &= ~DISPPLANE_TILED;
2417 }
2418
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002419 if (IS_G4X(dev))
2420 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2421
Chris Wilson5eddb702010-09-11 13:48:45 +01002422 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002423
Daniel Vettere506a0c2012-07-05 12:17:29 +02002424 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002425
Daniel Vetterc2c75132012-07-05 12:17:30 +02002426 if (INTEL_INFO(dev)->gen >= 4) {
2427 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002428 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2429 fb->bits_per_pixel / 8,
2430 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002431 linear_offset -= intel_crtc->dspaddr_offset;
2432 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002433 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002434 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002435
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002436 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2437 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2438 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002439 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002440 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002441 I915_WRITE(DSPSURF(plane),
2442 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002443 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002444 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002445 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002446 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002447 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002448}
2449
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002450static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2451 struct drm_framebuffer *fb,
2452 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002453{
2454 struct drm_device *dev = crtc->dev;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457 struct intel_framebuffer *intel_fb;
2458 struct drm_i915_gem_object *obj;
2459 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002460 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002461 u32 dspcntr;
2462 u32 reg;
2463
Jesse Barnes17638cd2011-06-24 12:19:23 -07002464 intel_fb = to_intel_framebuffer(fb);
2465 obj = intel_fb->obj;
2466
2467 reg = DSPCNTR(plane);
2468 dspcntr = I915_READ(reg);
2469 /* Mask out pixel format bits in case we change it */
2470 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002471 switch (fb->pixel_format) {
2472 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002473 dspcntr |= DISPPLANE_8BPP;
2474 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002475 case DRM_FORMAT_RGB565:
2476 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002477 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002478 case DRM_FORMAT_XRGB8888:
2479 case DRM_FORMAT_ARGB8888:
2480 dspcntr |= DISPPLANE_BGRX888;
2481 break;
2482 case DRM_FORMAT_XBGR8888:
2483 case DRM_FORMAT_ABGR8888:
2484 dspcntr |= DISPPLANE_RGBX888;
2485 break;
2486 case DRM_FORMAT_XRGB2101010:
2487 case DRM_FORMAT_ARGB2101010:
2488 dspcntr |= DISPPLANE_BGRX101010;
2489 break;
2490 case DRM_FORMAT_XBGR2101010:
2491 case DRM_FORMAT_ABGR2101010:
2492 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002493 break;
2494 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002495 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002496 }
2497
2498 if (obj->tiling_mode != I915_TILING_NONE)
2499 dspcntr |= DISPPLANE_TILED;
2500 else
2501 dspcntr &= ~DISPPLANE_TILED;
2502
Ville Syrjäläb42c6002013-11-03 13:47:27 +02002503 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002504 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2505 else
2506 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002507
2508 I915_WRITE(reg, dspcntr);
2509
Daniel Vettere506a0c2012-07-05 12:17:29 +02002510 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002511 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002512 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2513 fb->bits_per_pixel / 8,
2514 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002515 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002516
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002517 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2518 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2519 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002520 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002521 I915_WRITE(DSPSURF(plane),
2522 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002523 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002524 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2525 } else {
2526 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2527 I915_WRITE(DSPLINOFF(plane), linear_offset);
2528 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002529 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002530}
2531
2532/* Assume fb object is pinned & idle & fenced and just update base pointers */
2533static int
2534intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2535 int x, int y, enum mode_set_atomic state)
2536{
2537 struct drm_device *dev = crtc->dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002539
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002540 if (dev_priv->display.disable_fbc)
2541 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002542 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002543
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002544 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2545
2546 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002547}
2548
Ville Syrjälä96a02912013-02-18 19:08:49 +02002549void intel_display_handle_reset(struct drm_device *dev)
2550{
2551 struct drm_i915_private *dev_priv = dev->dev_private;
2552 struct drm_crtc *crtc;
2553
2554 /*
2555 * Flips in the rings have been nuked by the reset,
2556 * so complete all pending flips so that user space
2557 * will get its events and not get stuck.
2558 *
2559 * Also update the base address of all primary
2560 * planes to the the last fb to make sure we're
2561 * showing the correct fb after a reset.
2562 *
2563 * Need to make two loops over the crtcs so that we
2564 * don't try to grab a crtc mutex before the
2565 * pending_flip_queue really got woken up.
2566 */
2567
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002568 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570 enum plane plane = intel_crtc->plane;
2571
2572 intel_prepare_page_flip(dev, plane);
2573 intel_finish_page_flip_plane(dev, plane);
2574 }
2575
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002576 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2578
2579 mutex_lock(&crtc->mutex);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002580 /*
2581 * FIXME: Once we have proper support for primary planes (and
2582 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002583 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002584 */
Matt Roperf4510a22014-04-01 15:22:40 -07002585 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002586 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002587 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002588 crtc->x,
2589 crtc->y);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002590 mutex_unlock(&crtc->mutex);
2591 }
2592}
2593
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002594static int
Chris Wilson14667a42012-04-03 17:58:35 +01002595intel_finish_fb(struct drm_framebuffer *old_fb)
2596{
2597 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2598 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2599 bool was_interruptible = dev_priv->mm.interruptible;
2600 int ret;
2601
Chris Wilson14667a42012-04-03 17:58:35 +01002602 /* Big Hammer, we also need to ensure that any pending
2603 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2604 * current scanout is retired before unpinning the old
2605 * framebuffer.
2606 *
2607 * This should only fail upon a hung GPU, in which case we
2608 * can safely continue.
2609 */
2610 dev_priv->mm.interruptible = false;
2611 ret = i915_gem_object_finish_gpu(obj);
2612 dev_priv->mm.interruptible = was_interruptible;
2613
2614 return ret;
2615}
2616
Chris Wilson7d5e3792014-03-04 13:15:08 +00002617static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2618{
2619 struct drm_device *dev = crtc->dev;
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622 unsigned long flags;
2623 bool pending;
2624
2625 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2626 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2627 return false;
2628
2629 spin_lock_irqsave(&dev->event_lock, flags);
2630 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2631 spin_unlock_irqrestore(&dev->event_lock, flags);
2632
2633 return pending;
2634}
2635
Chris Wilson14667a42012-04-03 17:58:35 +01002636static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002637intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002638 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002639{
2640 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002641 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002643 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002644 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002645
Chris Wilson7d5e3792014-03-04 13:15:08 +00002646 if (intel_crtc_has_pending_flip(crtc)) {
2647 DRM_ERROR("pipe is still busy with an old pageflip\n");
2648 return -EBUSY;
2649 }
2650
Jesse Barnes79e53942008-11-07 14:24:08 -08002651 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002652 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002653 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002654 return 0;
2655 }
2656
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002657 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002658 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2659 plane_name(intel_crtc->plane),
2660 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002661 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002662 }
2663
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002664 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002665 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002666 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002667 NULL);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002668 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002669 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002670 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002671 return ret;
2672 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002673
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002674 /*
2675 * Update pipe size and adjust fitter if needed: the reason for this is
2676 * that in compute_mode_changes we check the native mode (not the pfit
2677 * mode) to see if we can flip rather than do a full mode set. In the
2678 * fastboot case, we'll flip, but if we don't update the pipesrc and
2679 * pfit state, we'll end up with a big fb scanned out into the wrong
2680 * sized surface.
2681 *
2682 * To fix this properly, we need to hoist the checks up into
2683 * compute_mode_changes (or above), check the actual pfit state and
2684 * whether the platform allows pfit disable with pipe active, and only
2685 * then update the pipesrc and pfit state, even on the flip path.
2686 */
Jani Nikulad330a952014-01-21 11:24:25 +02002687 if (i915.fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002688 const struct drm_display_mode *adjusted_mode =
2689 &intel_crtc->config.adjusted_mode;
2690
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002691 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002692 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2693 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002694 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002695 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2696 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2697 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2698 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2699 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2700 }
Jesse Barnes0637d602013-12-19 10:48:01 -08002701 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2702 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002703 }
2704
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002705 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002706
Matt Roperf4510a22014-04-01 15:22:40 -07002707 old_fb = crtc->primary->fb;
2708 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002709 crtc->x = x;
2710 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002711
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002712 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002713 if (intel_crtc->active && old_fb != fb)
2714 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002715 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002716 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002717 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002718 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002719
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002720 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002721 intel_update_fbc(dev);
Rodrigo Vivi49065572013-07-11 18:45:05 -03002722 intel_edp_psr_update(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002723 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002724
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002725 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002726}
2727
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002728static void intel_fdi_normal_train(struct drm_crtc *crtc)
2729{
2730 struct drm_device *dev = crtc->dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733 int pipe = intel_crtc->pipe;
2734 u32 reg, temp;
2735
2736 /* enable normal train */
2737 reg = FDI_TX_CTL(pipe);
2738 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002739 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002740 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2741 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002745 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002746 I915_WRITE(reg, temp);
2747
2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 if (HAS_PCH_CPT(dev)) {
2751 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2752 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2753 } else {
2754 temp &= ~FDI_LINK_TRAIN_NONE;
2755 temp |= FDI_LINK_TRAIN_NONE;
2756 }
2757 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2758
2759 /* wait one idle pattern time */
2760 POSTING_READ(reg);
2761 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002762
2763 /* IVB wants error correction enabled */
2764 if (IS_IVYBRIDGE(dev))
2765 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2766 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002767}
2768
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002769static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002770{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002771 return crtc->base.enabled && crtc->active &&
2772 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002773}
2774
Daniel Vetter01a415f2012-10-27 15:58:40 +02002775static void ivb_modeset_global_resources(struct drm_device *dev)
2776{
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 struct intel_crtc *pipe_B_crtc =
2779 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2780 struct intel_crtc *pipe_C_crtc =
2781 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2782 uint32_t temp;
2783
Daniel Vetter1e833f42013-02-19 22:31:57 +01002784 /*
2785 * When everything is off disable fdi C so that we could enable fdi B
2786 * with all lanes. Note that we don't care about enabled pipes without
2787 * an enabled pch encoder.
2788 */
2789 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2790 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002791 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2792 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2793
2794 temp = I915_READ(SOUTH_CHICKEN1);
2795 temp &= ~FDI_BC_BIFURCATION_SELECT;
2796 DRM_DEBUG_KMS("disabling fdi C rx\n");
2797 I915_WRITE(SOUTH_CHICKEN1, temp);
2798 }
2799}
2800
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002801/* The FDI link training functions for ILK/Ibexpeak. */
2802static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2803{
2804 struct drm_device *dev = crtc->dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002808 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002809
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03002810 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002811 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002812
Adam Jacksone1a44742010-06-25 15:32:14 -04002813 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2814 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002815 reg = FDI_RX_IMR(pipe);
2816 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002817 temp &= ~FDI_RX_SYMBOL_LOCK;
2818 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002819 I915_WRITE(reg, temp);
2820 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002821 udelay(150);
2822
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002823 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002826 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2827 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002828 temp &= ~FDI_LINK_TRAIN_NONE;
2829 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002830 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002831
Chris Wilson5eddb702010-09-11 13:48:45 +01002832 reg = FDI_RX_CTL(pipe);
2833 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002834 temp &= ~FDI_LINK_TRAIN_NONE;
2835 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002836 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2837
2838 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002839 udelay(150);
2840
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002841 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002842 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2843 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2844 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002845
Chris Wilson5eddb702010-09-11 13:48:45 +01002846 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002847 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002848 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002849 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2850
2851 if ((temp & FDI_RX_BIT_LOCK)) {
2852 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002853 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002854 break;
2855 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002856 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002857 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002858 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002859
2860 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002861 reg = FDI_TX_CTL(pipe);
2862 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002865 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002866
Chris Wilson5eddb702010-09-11 13:48:45 +01002867 reg = FDI_RX_CTL(pipe);
2868 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002869 temp &= ~FDI_LINK_TRAIN_NONE;
2870 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002871 I915_WRITE(reg, temp);
2872
2873 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002874 udelay(150);
2875
Chris Wilson5eddb702010-09-11 13:48:45 +01002876 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002877 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002878 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002879 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2880
2881 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002882 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002883 DRM_DEBUG_KMS("FDI train 2 done.\n");
2884 break;
2885 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002886 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002887 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002888 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002889
2890 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002891
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002892}
2893
Akshay Joshi0206e352011-08-16 15:34:10 -04002894static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002895 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2896 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2897 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2898 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2899};
2900
2901/* The FDI link training functions for SNB/Cougarpoint. */
2902static void gen6_fdi_link_train(struct drm_crtc *crtc)
2903{
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_i915_private *dev_priv = dev->dev_private;
2906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002908 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002909
Adam Jacksone1a44742010-06-25 15:32:14 -04002910 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2911 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002912 reg = FDI_RX_IMR(pipe);
2913 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002914 temp &= ~FDI_RX_SYMBOL_LOCK;
2915 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002916 I915_WRITE(reg, temp);
2917
2918 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002919 udelay(150);
2920
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002921 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002922 reg = FDI_TX_CTL(pipe);
2923 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002924 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2925 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002926 temp &= ~FDI_LINK_TRAIN_NONE;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1;
2928 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2929 /* SNB-B */
2930 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002931 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002932
Daniel Vetterd74cf322012-10-26 10:58:13 +02002933 I915_WRITE(FDI_RX_MISC(pipe),
2934 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2935
Chris Wilson5eddb702010-09-11 13:48:45 +01002936 reg = FDI_RX_CTL(pipe);
2937 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002938 if (HAS_PCH_CPT(dev)) {
2939 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2941 } else {
2942 temp &= ~FDI_LINK_TRAIN_NONE;
2943 temp |= FDI_LINK_TRAIN_PATTERN_1;
2944 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002945 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2946
2947 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002948 udelay(150);
2949
Akshay Joshi0206e352011-08-16 15:34:10 -04002950 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002951 reg = FDI_TX_CTL(pipe);
2952 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002953 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2954 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002958 udelay(500);
2959
Sean Paulfa37d392012-03-02 12:53:39 -05002960 for (retry = 0; retry < 5; retry++) {
2961 reg = FDI_RX_IIR(pipe);
2962 temp = I915_READ(reg);
2963 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2964 if (temp & FDI_RX_BIT_LOCK) {
2965 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2966 DRM_DEBUG_KMS("FDI train 1 done.\n");
2967 break;
2968 }
2969 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002970 }
Sean Paulfa37d392012-03-02 12:53:39 -05002971 if (retry < 5)
2972 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002973 }
2974 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002975 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002976
2977 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002978 reg = FDI_TX_CTL(pipe);
2979 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002980 temp &= ~FDI_LINK_TRAIN_NONE;
2981 temp |= FDI_LINK_TRAIN_PATTERN_2;
2982 if (IS_GEN6(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2984 /* SNB-B */
2985 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2986 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002987 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002988
Chris Wilson5eddb702010-09-11 13:48:45 +01002989 reg = FDI_RX_CTL(pipe);
2990 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002991 if (HAS_PCH_CPT(dev)) {
2992 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2993 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2994 } else {
2995 temp &= ~FDI_LINK_TRAIN_NONE;
2996 temp |= FDI_LINK_TRAIN_PATTERN_2;
2997 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002998 I915_WRITE(reg, temp);
2999
3000 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003001 udelay(150);
3002
Akshay Joshi0206e352011-08-16 15:34:10 -04003003 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003004 reg = FDI_TX_CTL(pipe);
3005 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003006 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3007 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003008 I915_WRITE(reg, temp);
3009
3010 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003011 udelay(500);
3012
Sean Paulfa37d392012-03-02 12:53:39 -05003013 for (retry = 0; retry < 5; retry++) {
3014 reg = FDI_RX_IIR(pipe);
3015 temp = I915_READ(reg);
3016 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3017 if (temp & FDI_RX_SYMBOL_LOCK) {
3018 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3019 DRM_DEBUG_KMS("FDI train 2 done.\n");
3020 break;
3021 }
3022 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003023 }
Sean Paulfa37d392012-03-02 12:53:39 -05003024 if (retry < 5)
3025 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003026 }
3027 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003028 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003029
3030 DRM_DEBUG_KMS("FDI train done.\n");
3031}
3032
Jesse Barnes357555c2011-04-28 15:09:55 -07003033/* Manual link training for Ivy Bridge A0 parts */
3034static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3035{
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003040 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003041
3042 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3043 for train result */
3044 reg = FDI_RX_IMR(pipe);
3045 temp = I915_READ(reg);
3046 temp &= ~FDI_RX_SYMBOL_LOCK;
3047 temp &= ~FDI_RX_BIT_LOCK;
3048 I915_WRITE(reg, temp);
3049
3050 POSTING_READ(reg);
3051 udelay(150);
3052
Daniel Vetter01a415f2012-10-27 15:58:40 +02003053 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3054 I915_READ(FDI_RX_IIR(pipe)));
3055
Jesse Barnes139ccd32013-08-19 11:04:55 -07003056 /* Try each vswing and preemphasis setting twice before moving on */
3057 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3058 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003059 reg = FDI_TX_CTL(pipe);
3060 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003061 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3062 temp &= ~FDI_TX_ENABLE;
3063 I915_WRITE(reg, temp);
3064
3065 reg = FDI_RX_CTL(pipe);
3066 temp = I915_READ(reg);
3067 temp &= ~FDI_LINK_TRAIN_AUTO;
3068 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3069 temp &= ~FDI_RX_ENABLE;
3070 I915_WRITE(reg, temp);
3071
3072 /* enable CPU FDI TX and PCH FDI RX */
3073 reg = FDI_TX_CTL(pipe);
3074 temp = I915_READ(reg);
3075 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3076 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3077 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003078 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003079 temp |= snb_b_fdi_train_param[j/2];
3080 temp |= FDI_COMPOSITE_SYNC;
3081 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3082
3083 I915_WRITE(FDI_RX_MISC(pipe),
3084 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3085
3086 reg = FDI_RX_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3089 temp |= FDI_COMPOSITE_SYNC;
3090 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3091
3092 POSTING_READ(reg);
3093 udelay(1); /* should be 0.5us */
3094
3095 for (i = 0; i < 4; i++) {
3096 reg = FDI_RX_IIR(pipe);
3097 temp = I915_READ(reg);
3098 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3099
3100 if (temp & FDI_RX_BIT_LOCK ||
3101 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3102 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3103 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3104 i);
3105 break;
3106 }
3107 udelay(1); /* should be 0.5us */
3108 }
3109 if (i == 4) {
3110 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3111 continue;
3112 }
3113
3114 /* Train 2 */
3115 reg = FDI_TX_CTL(pipe);
3116 temp = I915_READ(reg);
3117 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3118 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3119 I915_WRITE(reg, temp);
3120
3121 reg = FDI_RX_CTL(pipe);
3122 temp = I915_READ(reg);
3123 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3124 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003125 I915_WRITE(reg, temp);
3126
3127 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003128 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003129
Jesse Barnes139ccd32013-08-19 11:04:55 -07003130 for (i = 0; i < 4; i++) {
3131 reg = FDI_RX_IIR(pipe);
3132 temp = I915_READ(reg);
3133 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003134
Jesse Barnes139ccd32013-08-19 11:04:55 -07003135 if (temp & FDI_RX_SYMBOL_LOCK ||
3136 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3137 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3138 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3139 i);
3140 goto train_done;
3141 }
3142 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003143 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003144 if (i == 4)
3145 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003146 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003147
Jesse Barnes139ccd32013-08-19 11:04:55 -07003148train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003149 DRM_DEBUG_KMS("FDI train done.\n");
3150}
3151
Daniel Vetter88cefb62012-08-12 19:27:14 +02003152static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003153{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003154 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003155 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003156 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003157 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003158
Jesse Barnesc64e3112010-09-10 11:27:03 -07003159
Jesse Barnes0e23b992010-09-10 11:10:00 -07003160 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003161 reg = FDI_RX_CTL(pipe);
3162 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003163 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3164 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003165 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003166 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3167
3168 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003169 udelay(200);
3170
3171 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003172 temp = I915_READ(reg);
3173 I915_WRITE(reg, temp | FDI_PCDCLK);
3174
3175 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003176 udelay(200);
3177
Paulo Zanoni20749732012-11-23 15:30:38 -02003178 /* Enable CPU FDI TX PLL, always on for Ironlake */
3179 reg = FDI_TX_CTL(pipe);
3180 temp = I915_READ(reg);
3181 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3182 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003183
Paulo Zanoni20749732012-11-23 15:30:38 -02003184 POSTING_READ(reg);
3185 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003186 }
3187}
3188
Daniel Vetter88cefb62012-08-12 19:27:14 +02003189static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3190{
3191 struct drm_device *dev = intel_crtc->base.dev;
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3193 int pipe = intel_crtc->pipe;
3194 u32 reg, temp;
3195
3196 /* Switch from PCDclk to Rawclk */
3197 reg = FDI_RX_CTL(pipe);
3198 temp = I915_READ(reg);
3199 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3200
3201 /* Disable CPU FDI TX PLL */
3202 reg = FDI_TX_CTL(pipe);
3203 temp = I915_READ(reg);
3204 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3205
3206 POSTING_READ(reg);
3207 udelay(100);
3208
3209 reg = FDI_RX_CTL(pipe);
3210 temp = I915_READ(reg);
3211 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3212
3213 /* Wait for the clocks to turn off. */
3214 POSTING_READ(reg);
3215 udelay(100);
3216}
3217
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003218static void ironlake_fdi_disable(struct drm_crtc *crtc)
3219{
3220 struct drm_device *dev = crtc->dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3223 int pipe = intel_crtc->pipe;
3224 u32 reg, temp;
3225
3226 /* disable CPU FDI tx and PCH FDI rx */
3227 reg = FDI_TX_CTL(pipe);
3228 temp = I915_READ(reg);
3229 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3230 POSTING_READ(reg);
3231
3232 reg = FDI_RX_CTL(pipe);
3233 temp = I915_READ(reg);
3234 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003235 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003236 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3237
3238 POSTING_READ(reg);
3239 udelay(100);
3240
3241 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003242 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003243 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003244
3245 /* still set train pattern 1 */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 temp &= ~FDI_LINK_TRAIN_NONE;
3249 temp |= FDI_LINK_TRAIN_PATTERN_1;
3250 I915_WRITE(reg, temp);
3251
3252 reg = FDI_RX_CTL(pipe);
3253 temp = I915_READ(reg);
3254 if (HAS_PCH_CPT(dev)) {
3255 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3256 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3257 } else {
3258 temp &= ~FDI_LINK_TRAIN_NONE;
3259 temp |= FDI_LINK_TRAIN_PATTERN_1;
3260 }
3261 /* BPC in FDI rx is consistent with that in PIPECONF */
3262 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003263 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003264 I915_WRITE(reg, temp);
3265
3266 POSTING_READ(reg);
3267 udelay(100);
3268}
3269
Chris Wilson5dce5b932014-01-20 10:17:36 +00003270bool intel_has_pending_fb_unpin(struct drm_device *dev)
3271{
3272 struct intel_crtc *crtc;
3273
3274 /* Note that we don't need to be called with mode_config.lock here
3275 * as our list of CRTC objects is static for the lifetime of the
3276 * device and so cannot disappear as we iterate. Similarly, we can
3277 * happily treat the predicates as racy, atomic checks as userspace
3278 * cannot claim and pin a new fb without at least acquring the
3279 * struct_mutex and so serialising with us.
3280 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003281 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003282 if (atomic_read(&crtc->unpin_work_count) == 0)
3283 continue;
3284
3285 if (crtc->unpin_work)
3286 intel_wait_for_vblank(dev, crtc->pipe);
3287
3288 return true;
3289 }
3290
3291 return false;
3292}
3293
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003294void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003295{
Chris Wilson0f911282012-04-17 10:05:38 +01003296 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003297 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003298
Matt Roperf4510a22014-04-01 15:22:40 -07003299 if (crtc->primary->fb == NULL)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003300 return;
3301
Daniel Vetter2c10d572012-12-20 21:24:07 +01003302 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3303
Daniel Vettereed6d672014-05-19 16:09:35 +02003304 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3305 !intel_crtc_has_pending_flip(crtc),
3306 60*HZ) == 0);
Chris Wilson5bb61642012-09-27 21:25:58 +01003307
Chris Wilson0f911282012-04-17 10:05:38 +01003308 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07003309 intel_finish_fb(crtc->primary->fb);
Chris Wilson0f911282012-04-17 10:05:38 +01003310 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003311}
3312
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003313/* Program iCLKIP clock to the desired frequency */
3314static void lpt_program_iclkip(struct drm_crtc *crtc)
3315{
3316 struct drm_device *dev = crtc->dev;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003318 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003319 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3320 u32 temp;
3321
Daniel Vetter09153002012-12-12 14:06:44 +01003322 mutex_lock(&dev_priv->dpio_lock);
3323
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003324 /* It is necessary to ungate the pixclk gate prior to programming
3325 * the divisors, and gate it back when it is done.
3326 */
3327 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3328
3329 /* Disable SSCCTL */
3330 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003331 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3332 SBI_SSCCTL_DISABLE,
3333 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003334
3335 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003336 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003337 auxdiv = 1;
3338 divsel = 0x41;
3339 phaseinc = 0x20;
3340 } else {
3341 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003342 * but the adjusted_mode->crtc_clock in in KHz. To get the
3343 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003344 * convert the virtual clock precision to KHz here for higher
3345 * precision.
3346 */
3347 u32 iclk_virtual_root_freq = 172800 * 1000;
3348 u32 iclk_pi_range = 64;
3349 u32 desired_divisor, msb_divisor_value, pi_value;
3350
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003351 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003352 msb_divisor_value = desired_divisor / iclk_pi_range;
3353 pi_value = desired_divisor % iclk_pi_range;
3354
3355 auxdiv = 0;
3356 divsel = msb_divisor_value - 2;
3357 phaseinc = pi_value;
3358 }
3359
3360 /* This should not happen with any sane values */
3361 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3362 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3363 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3364 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3365
3366 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003367 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003368 auxdiv,
3369 divsel,
3370 phasedir,
3371 phaseinc);
3372
3373 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003374 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003375 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3376 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3377 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3378 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3379 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3380 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003381 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003382
3383 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003384 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003385 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3386 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003387 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003388
3389 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003390 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003391 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003392 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003393
3394 /* Wait for initialization time */
3395 udelay(24);
3396
3397 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003398
3399 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003400}
3401
Daniel Vetter275f01b22013-05-03 11:49:47 +02003402static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3403 enum pipe pch_transcoder)
3404{
3405 struct drm_device *dev = crtc->base.dev;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3408
3409 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3410 I915_READ(HTOTAL(cpu_transcoder)));
3411 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3412 I915_READ(HBLANK(cpu_transcoder)));
3413 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3414 I915_READ(HSYNC(cpu_transcoder)));
3415
3416 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3417 I915_READ(VTOTAL(cpu_transcoder)));
3418 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3419 I915_READ(VBLANK(cpu_transcoder)));
3420 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3421 I915_READ(VSYNC(cpu_transcoder)));
3422 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3423 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3424}
3425
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003426static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3427{
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 uint32_t temp;
3430
3431 temp = I915_READ(SOUTH_CHICKEN1);
3432 if (temp & FDI_BC_BIFURCATION_SELECT)
3433 return;
3434
3435 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3436 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3437
3438 temp |= FDI_BC_BIFURCATION_SELECT;
3439 DRM_DEBUG_KMS("enabling fdi C rx\n");
3440 I915_WRITE(SOUTH_CHICKEN1, temp);
3441 POSTING_READ(SOUTH_CHICKEN1);
3442}
3443
3444static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3445{
3446 struct drm_device *dev = intel_crtc->base.dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448
3449 switch (intel_crtc->pipe) {
3450 case PIPE_A:
3451 break;
3452 case PIPE_B:
3453 if (intel_crtc->config.fdi_lanes > 2)
3454 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3455 else
3456 cpt_enable_fdi_bc_bifurcation(dev);
3457
3458 break;
3459 case PIPE_C:
3460 cpt_enable_fdi_bc_bifurcation(dev);
3461
3462 break;
3463 default:
3464 BUG();
3465 }
3466}
3467
Jesse Barnesf67a5592011-01-05 10:31:48 -08003468/*
3469 * Enable PCH resources required for PCH ports:
3470 * - PCH PLLs
3471 * - FDI training & RX/TX
3472 * - update transcoder timings
3473 * - DP transcoding bits
3474 * - transcoder
3475 */
3476static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003477{
3478 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003479 struct drm_i915_private *dev_priv = dev->dev_private;
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3481 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003482 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003483
Daniel Vetterab9412b2013-05-03 11:49:46 +02003484 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003485
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003486 if (IS_IVYBRIDGE(dev))
3487 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3488
Daniel Vettercd986ab2012-10-26 10:58:12 +02003489 /* Write the TU size bits before fdi link training, so that error
3490 * detection works. */
3491 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3492 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3493
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003494 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003495 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003496
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003497 /* We need to program the right clock selection before writing the pixel
3498 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003499 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003500 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003501
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003502 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003503 temp |= TRANS_DPLL_ENABLE(pipe);
3504 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003505 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003506 temp |= sel;
3507 else
3508 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003509 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003510 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003511
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003512 /* XXX: pch pll's can be enabled any time before we enable the PCH
3513 * transcoder, and we actually should do this to not upset any PCH
3514 * transcoder that already use the clock when we share it.
3515 *
3516 * Note that enable_shared_dpll tries to do the right thing, but
3517 * get_shared_dpll unconditionally resets the pll - we need that to have
3518 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003519 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003520
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003521 /* set transcoder timing, panel must allow it */
3522 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003523 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003524
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003525 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003526
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003527 /* For PCH DP, enable TRANS_DP_CTL */
3528 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003529 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3530 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003531 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003532 reg = TRANS_DP_CTL(pipe);
3533 temp = I915_READ(reg);
3534 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003535 TRANS_DP_SYNC_MASK |
3536 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003537 temp |= (TRANS_DP_OUTPUT_ENABLE |
3538 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003539 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003540
3541 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003542 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003543 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003544 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003545
3546 switch (intel_trans_dp_port_sel(crtc)) {
3547 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003548 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003549 break;
3550 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003551 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003552 break;
3553 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003554 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003555 break;
3556 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003557 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003558 }
3559
Chris Wilson5eddb702010-09-11 13:48:45 +01003560 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003561 }
3562
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003563 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003564}
3565
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003566static void lpt_pch_enable(struct drm_crtc *crtc)
3567{
3568 struct drm_device *dev = crtc->dev;
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003571 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003572
Daniel Vetterab9412b2013-05-03 11:49:46 +02003573 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003574
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003575 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003576
Paulo Zanoni0540e482012-10-31 18:12:40 -02003577 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003578 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003579
Paulo Zanoni937bb612012-10-31 18:12:47 -02003580 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003581}
3582
Daniel Vettere2b78262013-06-07 23:10:03 +02003583static void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003584{
Daniel Vettere2b78262013-06-07 23:10:03 +02003585 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003586
3587 if (pll == NULL)
3588 return;
3589
3590 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003591 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003592 return;
3593 }
3594
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003595 if (--pll->refcount == 0) {
3596 WARN_ON(pll->on);
3597 WARN_ON(pll->active);
3598 }
3599
Daniel Vettera43f6e02013-06-07 23:10:32 +02003600 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003601}
3602
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003603static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003604{
Daniel Vettere2b78262013-06-07 23:10:03 +02003605 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3606 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3607 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003608
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003609 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003610 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3611 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003612 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003613 }
3614
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003615 if (HAS_PCH_IBX(dev_priv->dev)) {
3616 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003617 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003618 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003619
Daniel Vetter46edb022013-06-05 13:34:12 +02003620 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3621 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003622
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003623 WARN_ON(pll->refcount);
3624
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003625 goto found;
3626 }
3627
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003628 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3629 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003630
3631 /* Only want to check enabled timings first */
3632 if (pll->refcount == 0)
3633 continue;
3634
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003635 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3636 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003637 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003638 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003639 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003640
3641 goto found;
3642 }
3643 }
3644
3645 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003646 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3647 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003648 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003649 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3650 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003651 goto found;
3652 }
3653 }
3654
3655 return NULL;
3656
3657found:
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003658 if (pll->refcount == 0)
3659 pll->hw_state = crtc->config.dpll_hw_state;
3660
Daniel Vettera43f6e02013-06-07 23:10:32 +02003661 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003662 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3663 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003664
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003665 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003666
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003667 return pll;
3668}
3669
Daniel Vettera1520312013-05-03 11:49:50 +02003670static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003671{
3672 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003673 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003674 u32 temp;
3675
3676 temp = I915_READ(dslreg);
3677 udelay(500);
3678 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003679 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003680 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003681 }
3682}
3683
Jesse Barnesb074cec2013-04-25 12:55:02 -07003684static void ironlake_pfit_enable(struct intel_crtc *crtc)
3685{
3686 struct drm_device *dev = crtc->base.dev;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 int pipe = crtc->pipe;
3689
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003690 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003691 /* Force use of hard-coded filter coefficients
3692 * as some pre-programmed values are broken,
3693 * e.g. x201.
3694 */
3695 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3696 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3697 PF_PIPE_SEL_IVB(pipe));
3698 else
3699 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3700 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3701 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003702 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003703}
3704
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003705static void intel_enable_planes(struct drm_crtc *crtc)
3706{
3707 struct drm_device *dev = crtc->dev;
3708 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003709 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003710 struct intel_plane *intel_plane;
3711
Matt Roperaf2b6532014-04-01 15:22:32 -07003712 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3713 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003714 if (intel_plane->pipe == pipe)
3715 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003716 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003717}
3718
3719static void intel_disable_planes(struct drm_crtc *crtc)
3720{
3721 struct drm_device *dev = crtc->dev;
3722 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003723 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003724 struct intel_plane *intel_plane;
3725
Matt Roperaf2b6532014-04-01 15:22:32 -07003726 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3727 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003728 if (intel_plane->pipe == pipe)
3729 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003730 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003731}
3732
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003733void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003734{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003735 struct drm_device *dev = crtc->base.dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03003737
3738 if (!crtc->config.ips_enabled)
3739 return;
3740
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003741 /* We can only enable IPS after we enable a plane and wait for a vblank */
3742 intel_wait_for_vblank(dev, crtc->pipe);
3743
Paulo Zanonid77e4532013-09-24 13:52:55 -03003744 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003745 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003746 mutex_lock(&dev_priv->rps.hw_lock);
3747 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3748 mutex_unlock(&dev_priv->rps.hw_lock);
3749 /* Quoting Art Runyan: "its not safe to expect any particular
3750 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08003751 * mailbox." Moreover, the mailbox may return a bogus state,
3752 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003753 */
3754 } else {
3755 I915_WRITE(IPS_CTL, IPS_ENABLE);
3756 /* The bit only becomes 1 in the next vblank, so this wait here
3757 * is essentially intel_wait_for_vblank. If we don't have this
3758 * and don't wait for vblanks until the end of crtc_enable, then
3759 * the HW state readout code will complain that the expected
3760 * IPS_CTL value is not the one we read. */
3761 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3762 DRM_ERROR("Timed out waiting for IPS enable\n");
3763 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003764}
3765
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003766void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003767{
3768 struct drm_device *dev = crtc->base.dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
3770
3771 if (!crtc->config.ips_enabled)
3772 return;
3773
3774 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003775 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003776 mutex_lock(&dev_priv->rps.hw_lock);
3777 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3778 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003779 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3780 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3781 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08003782 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003783 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08003784 POSTING_READ(IPS_CTL);
3785 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003786
3787 /* We need to wait for a vblank before we can disable the plane. */
3788 intel_wait_for_vblank(dev, crtc->pipe);
3789}
3790
3791/** Loads the palette/gamma unit for the CRTC with the prepared values */
3792static void intel_crtc_load_lut(struct drm_crtc *crtc)
3793{
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797 enum pipe pipe = intel_crtc->pipe;
3798 int palreg = PALETTE(pipe);
3799 int i;
3800 bool reenable_ips = false;
3801
3802 /* The clocks have to be on to load the palette. */
3803 if (!crtc->enabled || !intel_crtc->active)
3804 return;
3805
3806 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3807 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3808 assert_dsi_pll_enabled(dev_priv);
3809 else
3810 assert_pll_enabled(dev_priv, pipe);
3811 }
3812
3813 /* use legacy palette for Ironlake */
3814 if (HAS_PCH_SPLIT(dev))
3815 palreg = LGC_PALETTE(pipe);
3816
3817 /* Workaround : Do not read or write the pipe palette/gamma data while
3818 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3819 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02003820 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03003821 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3822 GAMMA_MODE_MODE_SPLIT)) {
3823 hsw_disable_ips(intel_crtc);
3824 reenable_ips = true;
3825 }
3826
3827 for (i = 0; i < 256; i++) {
3828 I915_WRITE(palreg + 4 * i,
3829 (intel_crtc->lut_r[i] << 16) |
3830 (intel_crtc->lut_g[i] << 8) |
3831 intel_crtc->lut_b[i]);
3832 }
3833
3834 if (reenable_ips)
3835 hsw_enable_ips(intel_crtc);
3836}
3837
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003838static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3839{
3840 if (!enable && intel_crtc->overlay) {
3841 struct drm_device *dev = intel_crtc->base.dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843
3844 mutex_lock(&dev->struct_mutex);
3845 dev_priv->mm.interruptible = false;
3846 (void) intel_overlay_switch_off(intel_crtc->overlay);
3847 dev_priv->mm.interruptible = true;
3848 mutex_unlock(&dev->struct_mutex);
3849 }
3850
3851 /* Let userspace switch the overlay on again. In most cases userspace
3852 * has to recompute where to put it anyway.
3853 */
3854}
3855
3856/**
3857 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3858 * cursor plane briefly if not already running after enabling the display
3859 * plane.
3860 * This workaround avoids occasional blank screens when self refresh is
3861 * enabled.
3862 */
3863static void
3864g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3865{
3866 u32 cntl = I915_READ(CURCNTR(pipe));
3867
3868 if ((cntl & CURSOR_MODE) == 0) {
3869 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3870
3871 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3872 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3873 intel_wait_for_vblank(dev_priv->dev, pipe);
3874 I915_WRITE(CURCNTR(pipe), cntl);
3875 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3876 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3877 }
3878}
3879
3880static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003881{
3882 struct drm_device *dev = crtc->dev;
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3885 int pipe = intel_crtc->pipe;
3886 int plane = intel_crtc->plane;
3887
3888 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3889 intel_enable_planes(crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003890 /* The fixup needs to happen before cursor is enabled */
3891 if (IS_G4X(dev))
3892 g4x_fixup_plane(dev_priv, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003893 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003894 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003895
3896 hsw_enable_ips(intel_crtc);
3897
3898 mutex_lock(&dev->struct_mutex);
3899 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02003900 intel_edp_psr_update(dev);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003901 mutex_unlock(&dev->struct_mutex);
3902}
3903
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003904static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003905{
3906 struct drm_device *dev = crtc->dev;
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3909 int pipe = intel_crtc->pipe;
3910 int plane = intel_crtc->plane;
3911
3912 intel_crtc_wait_for_pending_flips(crtc);
Daniel Vetter87b6b102014-05-15 15:33:46 +02003913 drm_crtc_vblank_off(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003914
3915 if (dev_priv->fbc.plane == plane)
3916 intel_disable_fbc(dev);
3917
3918 hsw_disable_ips(intel_crtc);
3919
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003920 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003921 intel_crtc_update_cursor(crtc, false);
3922 intel_disable_planes(crtc);
3923 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3924}
3925
Jesse Barnesf67a5592011-01-05 10:31:48 -08003926static void ironlake_crtc_enable(struct drm_crtc *crtc)
3927{
3928 struct drm_device *dev = crtc->dev;
3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003931 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003932 int pipe = intel_crtc->pipe;
Daniel Vetter29407aa2014-04-24 23:55:08 +02003933 enum plane plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003934
Daniel Vetter08a48462012-07-02 11:43:47 +02003935 WARN_ON(!crtc->enabled);
3936
Jesse Barnesf67a5592011-01-05 10:31:48 -08003937 if (intel_crtc->active)
3938 return;
3939
Daniel Vetterb14b1052014-04-24 23:55:13 +02003940 if (intel_crtc->config.has_pch_encoder)
3941 intel_prepare_shared_dpll(intel_crtc);
3942
Daniel Vetter29407aa2014-04-24 23:55:08 +02003943 if (intel_crtc->config.has_dp_encoder)
3944 intel_dp_set_m_n(intel_crtc);
3945
3946 intel_set_pipe_timings(intel_crtc);
3947
3948 if (intel_crtc->config.has_pch_encoder) {
3949 intel_cpu_transcoder_set_m_n(intel_crtc,
3950 &intel_crtc->config.fdi_m_n);
3951 }
3952
3953 ironlake_set_pipeconf(crtc);
3954
3955 /* Set up the display plane register */
3956 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3957 POSTING_READ(DSPCNTR(plane));
3958
3959 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3960 crtc->x, crtc->y);
3961
Jesse Barnesf67a5592011-01-05 10:31:48 -08003962 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003963
3964 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3965 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3966
Daniel Vetterf6736a12013-06-05 13:34:30 +02003967 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003968 if (encoder->pre_enable)
3969 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003970
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003971 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003972 /* Note: FDI PLL enabling _must_ be done before we enable the
3973 * cpu pipes, hence this is separate from all the other fdi/pch
3974 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003975 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003976 } else {
3977 assert_fdi_tx_disabled(dev_priv, pipe);
3978 assert_fdi_rx_disabled(dev_priv, pipe);
3979 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003980
Jesse Barnesb074cec2013-04-25 12:55:02 -07003981 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003982
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003983 /*
3984 * On ILK+ LUT must be loaded before the pipe is running but with
3985 * clocks enabled
3986 */
3987 intel_crtc_load_lut(crtc);
3988
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03003989 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02003990 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003991
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003992 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08003993 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003994
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003995 for_each_encoder_on_crtc(dev, crtc, encoder)
3996 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003997
3998 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02003999 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004000
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004001 intel_crtc_enable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004002
Daniel Vetter87b6b102014-05-15 15:33:46 +02004003 drm_crtc_vblank_on(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004004}
4005
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004006/* IPS only exists on ULT machines and is tied to pipe A. */
4007static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4008{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004009 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004010}
4011
Paulo Zanonie4916942013-09-20 16:21:19 -03004012/*
4013 * This implements the workaround described in the "notes" section of the mode
4014 * set sequence documentation. When going from no pipes or single pipe to
4015 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4016 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4017 */
4018static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4019{
4020 struct drm_device *dev = crtc->base.dev;
4021 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4022
4023 /* We want to get the other_active_crtc only if there's only 1 other
4024 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004025 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004026 if (!crtc_it->active || crtc_it == crtc)
4027 continue;
4028
4029 if (other_active_crtc)
4030 return;
4031
4032 other_active_crtc = crtc_it;
4033 }
4034 if (!other_active_crtc)
4035 return;
4036
4037 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4038 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4039}
4040
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004041static void haswell_crtc_enable(struct drm_crtc *crtc)
4042{
4043 struct drm_device *dev = crtc->dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4046 struct intel_encoder *encoder;
4047 int pipe = intel_crtc->pipe;
Daniel Vetter229fca92014-04-24 23:55:09 +02004048 enum plane plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004049
4050 WARN_ON(!crtc->enabled);
4051
4052 if (intel_crtc->active)
4053 return;
4054
Daniel Vetter229fca92014-04-24 23:55:09 +02004055 if (intel_crtc->config.has_dp_encoder)
4056 intel_dp_set_m_n(intel_crtc);
4057
4058 intel_set_pipe_timings(intel_crtc);
4059
4060 if (intel_crtc->config.has_pch_encoder) {
4061 intel_cpu_transcoder_set_m_n(intel_crtc,
4062 &intel_crtc->config.fdi_m_n);
4063 }
4064
4065 haswell_set_pipeconf(crtc);
4066
4067 intel_set_pipe_csc(crtc);
4068
4069 /* Set up the display plane register */
4070 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4071 POSTING_READ(DSPCNTR(plane));
4072
4073 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4074 crtc->x, crtc->y);
4075
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004076 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004077
4078 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4079 if (intel_crtc->config.has_pch_encoder)
4080 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4081
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004082 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni04945642012-11-01 21:00:59 -02004083 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004084
4085 for_each_encoder_on_crtc(dev, crtc, encoder)
4086 if (encoder->pre_enable)
4087 encoder->pre_enable(encoder);
4088
Paulo Zanoni1f544382012-10-24 11:32:00 -02004089 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004090
Jesse Barnesb074cec2013-04-25 12:55:02 -07004091 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004092
4093 /*
4094 * On ILK+ LUT must be loaded before the pipe is running but with
4095 * clocks enabled
4096 */
4097 intel_crtc_load_lut(crtc);
4098
Paulo Zanoni1f544382012-10-24 11:32:00 -02004099 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004100 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004101
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004102 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004103 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004104
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004105 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004106 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004107
Jani Nikula8807e552013-08-30 19:40:32 +03004108 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004109 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004110 intel_opregion_notify_encoder(encoder, true);
4111 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004112
Paulo Zanonie4916942013-09-20 16:21:19 -03004113 /* If we change the relative order between pipe/planes enabling, we need
4114 * to change the workaround. */
4115 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004116 intel_crtc_enable_planes(crtc);
Ville Syrjäläf2752282014-02-19 21:29:49 +02004117
Daniel Vetter87b6b102014-05-15 15:33:46 +02004118 drm_crtc_vblank_on(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004119}
4120
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004121static void ironlake_pfit_disable(struct intel_crtc *crtc)
4122{
4123 struct drm_device *dev = crtc->base.dev;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125 int pipe = crtc->pipe;
4126
4127 /* To avoid upsetting the power well on haswell only disable the pfit if
4128 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004129 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004130 I915_WRITE(PF_CTL(pipe), 0);
4131 I915_WRITE(PF_WIN_POS(pipe), 0);
4132 I915_WRITE(PF_WIN_SZ(pipe), 0);
4133 }
4134}
4135
Jesse Barnes6be4a602010-09-10 10:26:01 -07004136static void ironlake_crtc_disable(struct drm_crtc *crtc)
4137{
4138 struct drm_device *dev = crtc->dev;
4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004141 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004142 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004143 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004144
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004145 if (!intel_crtc->active)
4146 return;
4147
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004148 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004149
Daniel Vetterea9d7582012-07-10 10:42:52 +02004150 for_each_encoder_on_crtc(dev, crtc, encoder)
4151 encoder->disable(encoder);
4152
Daniel Vetterd925c592013-06-05 13:34:04 +02004153 if (intel_crtc->config.has_pch_encoder)
4154 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4155
Jesse Barnesb24e7172011-01-04 15:09:30 -08004156 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004157
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004158 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004159
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004160 for_each_encoder_on_crtc(dev, crtc, encoder)
4161 if (encoder->post_disable)
4162 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004163
Daniel Vetterd925c592013-06-05 13:34:04 +02004164 if (intel_crtc->config.has_pch_encoder) {
4165 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004166
Daniel Vetterd925c592013-06-05 13:34:04 +02004167 ironlake_disable_pch_transcoder(dev_priv, pipe);
4168 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004169
Daniel Vetterd925c592013-06-05 13:34:04 +02004170 if (HAS_PCH_CPT(dev)) {
4171 /* disable TRANS_DP_CTL */
4172 reg = TRANS_DP_CTL(pipe);
4173 temp = I915_READ(reg);
4174 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4175 TRANS_DP_PORT_SEL_MASK);
4176 temp |= TRANS_DP_PORT_SEL_NONE;
4177 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004178
Daniel Vetterd925c592013-06-05 13:34:04 +02004179 /* disable DPLL_SEL */
4180 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004181 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004182 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004183 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004184
4185 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004186 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004187
4188 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004189 }
4190
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004191 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004192 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004193
4194 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004195 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004196 intel_edp_psr_update(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004197 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004198}
4199
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004200static void haswell_crtc_disable(struct drm_crtc *crtc)
4201{
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4205 struct intel_encoder *encoder;
4206 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004207 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004208
4209 if (!intel_crtc->active)
4210 return;
4211
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004212 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004213
Jani Nikula8807e552013-08-30 19:40:32 +03004214 for_each_encoder_on_crtc(dev, crtc, encoder) {
4215 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004216 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004217 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004218
Paulo Zanoni86642812013-04-12 17:57:57 -03004219 if (intel_crtc->config.has_pch_encoder)
4220 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004221 intel_disable_pipe(dev_priv, pipe);
4222
Paulo Zanoniad80a812012-10-24 16:06:19 -02004223 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004224
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004225 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004226
Paulo Zanoni1f544382012-10-24 11:32:00 -02004227 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004228
4229 for_each_encoder_on_crtc(dev, crtc, encoder)
4230 if (encoder->post_disable)
4231 encoder->post_disable(encoder);
4232
Daniel Vetter88adfff2013-03-28 10:42:01 +01004233 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004234 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03004235 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004236 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004237 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004238
4239 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004240 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004241
4242 mutex_lock(&dev->struct_mutex);
4243 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004244 intel_edp_psr_update(dev);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004245 mutex_unlock(&dev->struct_mutex);
4246}
4247
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004248static void ironlake_crtc_off(struct drm_crtc *crtc)
4249{
4250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004251 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004252}
4253
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004254static void haswell_crtc_off(struct drm_crtc *crtc)
4255{
4256 intel_ddi_put_crtc_pll(crtc);
4257}
4258
Jesse Barnes2dd24552013-04-25 12:55:01 -07004259static void i9xx_pfit_enable(struct intel_crtc *crtc)
4260{
4261 struct drm_device *dev = crtc->base.dev;
4262 struct drm_i915_private *dev_priv = dev->dev_private;
4263 struct intel_crtc_config *pipe_config = &crtc->config;
4264
Daniel Vetter328d8e82013-05-08 10:36:31 +02004265 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004266 return;
4267
Daniel Vetterc0b03412013-05-28 12:05:54 +02004268 /*
4269 * The panel fitter should only be adjusted whilst the pipe is disabled,
4270 * according to register description and PRM.
4271 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004272 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4273 assert_pipe_disabled(dev_priv, crtc->pipe);
4274
Jesse Barnesb074cec2013-04-25 12:55:02 -07004275 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4276 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004277
4278 /* Border color in case we don't scale up to the full screen. Black by
4279 * default, change to something else for debugging. */
4280 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004281}
4282
Imre Deak77d22dc2014-03-05 16:20:52 +02004283#define for_each_power_domain(domain, mask) \
4284 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4285 if ((1 << (domain)) & (mask))
4286
Imre Deak319be8a2014-03-04 19:22:57 +02004287enum intel_display_power_domain
4288intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004289{
Imre Deak319be8a2014-03-04 19:22:57 +02004290 struct drm_device *dev = intel_encoder->base.dev;
4291 struct intel_digital_port *intel_dig_port;
4292
4293 switch (intel_encoder->type) {
4294 case INTEL_OUTPUT_UNKNOWN:
4295 /* Only DDI platforms should ever use this output type */
4296 WARN_ON_ONCE(!HAS_DDI(dev));
4297 case INTEL_OUTPUT_DISPLAYPORT:
4298 case INTEL_OUTPUT_HDMI:
4299 case INTEL_OUTPUT_EDP:
4300 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4301 switch (intel_dig_port->port) {
4302 case PORT_A:
4303 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4304 case PORT_B:
4305 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4306 case PORT_C:
4307 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4308 case PORT_D:
4309 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4310 default:
4311 WARN_ON_ONCE(1);
4312 return POWER_DOMAIN_PORT_OTHER;
4313 }
4314 case INTEL_OUTPUT_ANALOG:
4315 return POWER_DOMAIN_PORT_CRT;
4316 case INTEL_OUTPUT_DSI:
4317 return POWER_DOMAIN_PORT_DSI;
4318 default:
4319 return POWER_DOMAIN_PORT_OTHER;
4320 }
4321}
4322
4323static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4324{
4325 struct drm_device *dev = crtc->dev;
4326 struct intel_encoder *intel_encoder;
4327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4328 enum pipe pipe = intel_crtc->pipe;
4329 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
Imre Deak77d22dc2014-03-05 16:20:52 +02004330 unsigned long mask;
4331 enum transcoder transcoder;
4332
4333 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4334
4335 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4336 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4337 if (pfit_enabled)
4338 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4339
Imre Deak319be8a2014-03-04 19:22:57 +02004340 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4341 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4342
Imre Deak77d22dc2014-03-05 16:20:52 +02004343 return mask;
4344}
4345
4346void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4347 bool enable)
4348{
4349 if (dev_priv->power_domains.init_power_on == enable)
4350 return;
4351
4352 if (enable)
4353 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4354 else
4355 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4356
4357 dev_priv->power_domains.init_power_on = enable;
4358}
4359
4360static void modeset_update_crtc_power_domains(struct drm_device *dev)
4361{
4362 struct drm_i915_private *dev_priv = dev->dev_private;
4363 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4364 struct intel_crtc *crtc;
4365
4366 /*
4367 * First get all needed power domains, then put all unneeded, to avoid
4368 * any unnecessary toggling of the power wells.
4369 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004370 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004371 enum intel_display_power_domain domain;
4372
4373 if (!crtc->base.enabled)
4374 continue;
4375
Imre Deak319be8a2014-03-04 19:22:57 +02004376 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004377
4378 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4379 intel_display_power_get(dev_priv, domain);
4380 }
4381
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004382 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004383 enum intel_display_power_domain domain;
4384
4385 for_each_power_domain(domain, crtc->enabled_power_domains)
4386 intel_display_power_put(dev_priv, domain);
4387
4388 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4389 }
4390
4391 intel_display_set_init_power(dev_priv, false);
4392}
4393
Jesse Barnes586f49d2013-11-04 16:06:59 -08004394int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004395{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004396 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004397
Jesse Barnes586f49d2013-11-04 16:06:59 -08004398 /* Obtain SKU information */
4399 mutex_lock(&dev_priv->dpio_lock);
4400 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4401 CCK_FUSE_HPLL_FREQ_MASK;
4402 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004403
Jesse Barnes586f49d2013-11-04 16:06:59 -08004404 return vco_freq[hpll_freq];
Jesse Barnes30a970c2013-11-04 13:48:12 -08004405}
4406
4407/* Adjust CDclk dividers to allow high res or save power if possible */
4408static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4409{
4410 struct drm_i915_private *dev_priv = dev->dev_private;
4411 u32 val, cmd;
4412
Imre Deakd60c4472014-03-27 17:45:10 +02004413 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4414 dev_priv->vlv_cdclk_freq = cdclk;
4415
Jesse Barnes30a970c2013-11-04 13:48:12 -08004416 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4417 cmd = 2;
4418 else if (cdclk == 266)
4419 cmd = 1;
4420 else
4421 cmd = 0;
4422
4423 mutex_lock(&dev_priv->rps.hw_lock);
4424 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4425 val &= ~DSPFREQGUAR_MASK;
4426 val |= (cmd << DSPFREQGUAR_SHIFT);
4427 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4428 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4429 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4430 50)) {
4431 DRM_ERROR("timed out waiting for CDclk change\n");
4432 }
4433 mutex_unlock(&dev_priv->rps.hw_lock);
4434
4435 if (cdclk == 400) {
4436 u32 divider, vco;
4437
4438 vco = valleyview_get_vco(dev_priv);
4439 divider = ((vco << 1) / cdclk) - 1;
4440
4441 mutex_lock(&dev_priv->dpio_lock);
4442 /* adjust cdclk divider */
4443 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4444 val &= ~0xf;
4445 val |= divider;
4446 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4447 mutex_unlock(&dev_priv->dpio_lock);
4448 }
4449
4450 mutex_lock(&dev_priv->dpio_lock);
4451 /* adjust self-refresh exit latency value */
4452 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4453 val &= ~0x7f;
4454
4455 /*
4456 * For high bandwidth configs, we set a higher latency in the bunit
4457 * so that the core display fetch happens in time to avoid underruns.
4458 */
4459 if (cdclk == 400)
4460 val |= 4500 / 250; /* 4.5 usec */
4461 else
4462 val |= 3000 / 250; /* 3.0 usec */
4463 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4464 mutex_unlock(&dev_priv->dpio_lock);
4465
4466 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4467 intel_i2c_reset(dev);
4468}
4469
Imre Deakd60c4472014-03-27 17:45:10 +02004470int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004471{
4472 int cur_cdclk, vco;
4473 int divider;
4474
4475 vco = valleyview_get_vco(dev_priv);
4476
4477 mutex_lock(&dev_priv->dpio_lock);
4478 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4479 mutex_unlock(&dev_priv->dpio_lock);
4480
4481 divider &= 0xf;
4482
4483 cur_cdclk = (vco << 1) / (divider + 1);
4484
4485 return cur_cdclk;
4486}
4487
4488static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4489 int max_pixclk)
4490{
Jesse Barnes30a970c2013-11-04 13:48:12 -08004491 /*
4492 * Really only a few cases to deal with, as only 4 CDclks are supported:
4493 * 200MHz
4494 * 267MHz
4495 * 320MHz
4496 * 400MHz
4497 * So we check to see whether we're above 90% of the lower bin and
4498 * adjust if needed.
4499 */
4500 if (max_pixclk > 288000) {
4501 return 400;
4502 } else if (max_pixclk > 240000) {
4503 return 320;
4504 } else
4505 return 266;
4506 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4507}
4508
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004509/* compute the max pixel clock for new configuration */
4510static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004511{
4512 struct drm_device *dev = dev_priv->dev;
4513 struct intel_crtc *intel_crtc;
4514 int max_pixclk = 0;
4515
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004516 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004517 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004518 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004519 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004520 }
4521
4522 return max_pixclk;
4523}
4524
4525static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004526 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004527{
4528 struct drm_i915_private *dev_priv = dev->dev_private;
4529 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004530 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004531
Imre Deakd60c4472014-03-27 17:45:10 +02004532 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4533 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004534 return;
4535
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004536 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004537 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004538 if (intel_crtc->base.enabled)
4539 *prepare_pipes |= (1 << intel_crtc->pipe);
4540}
4541
4542static void valleyview_modeset_global_resources(struct drm_device *dev)
4543{
4544 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004545 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004546 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4547
Imre Deakd60c4472014-03-27 17:45:10 +02004548 if (req_cdclk != dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004549 valleyview_set_cdclk(dev, req_cdclk);
Imre Deak77961eb2014-03-05 16:20:56 +02004550 modeset_update_crtc_power_domains(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004551}
4552
Jesse Barnes89b667f2013-04-18 14:51:36 -07004553static void valleyview_crtc_enable(struct drm_crtc *crtc)
4554{
4555 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004556 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4558 struct intel_encoder *encoder;
4559 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004560 int plane = intel_crtc->plane;
Jani Nikula23538ef2013-08-27 15:12:22 +03004561 bool is_dsi;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004562 u32 dspcntr;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004563
4564 WARN_ON(!crtc->enabled);
4565
4566 if (intel_crtc->active)
4567 return;
4568
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02004569 vlv_prepare_pll(intel_crtc);
4570
Daniel Vetter5b18e572014-04-24 23:55:06 +02004571 /* Set up the display plane register */
4572 dspcntr = DISPPLANE_GAMMA_ENABLE;
4573
4574 if (intel_crtc->config.has_dp_encoder)
4575 intel_dp_set_m_n(intel_crtc);
4576
4577 intel_set_pipe_timings(intel_crtc);
4578
4579 /* pipesrc and dspsize control the size that is scaled from,
4580 * which should always be the user's requested size.
4581 */
4582 I915_WRITE(DSPSIZE(plane),
4583 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4584 (intel_crtc->config.pipe_src_w - 1));
4585 I915_WRITE(DSPPOS(plane), 0);
4586
4587 i9xx_set_pipeconf(intel_crtc);
4588
4589 I915_WRITE(DSPCNTR(plane), dspcntr);
4590 POSTING_READ(DSPCNTR(plane));
4591
4592 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4593 crtc->x, crtc->y);
4594
Jesse Barnes89b667f2013-04-18 14:51:36 -07004595 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004596
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004597 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4598
Jesse Barnes89b667f2013-04-18 14:51:36 -07004599 for_each_encoder_on_crtc(dev, crtc, encoder)
4600 if (encoder->pre_pll_enable)
4601 encoder->pre_pll_enable(encoder);
4602
Jani Nikula23538ef2013-08-27 15:12:22 +03004603 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4604
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004605 if (!is_dsi) {
4606 if (IS_CHERRYVIEW(dev))
4607 chv_enable_pll(intel_crtc);
4608 else
4609 vlv_enable_pll(intel_crtc);
4610 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004611
4612 for_each_encoder_on_crtc(dev, crtc, encoder)
4613 if (encoder->pre_enable)
4614 encoder->pre_enable(encoder);
4615
Jesse Barnes2dd24552013-04-25 12:55:01 -07004616 i9xx_pfit_enable(intel_crtc);
4617
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004618 intel_crtc_load_lut(crtc);
4619
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004620 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004621 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004622
Jani Nikula50049452013-07-30 12:20:32 +03004623 for_each_encoder_on_crtc(dev, crtc, encoder)
4624 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004625
4626 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004627
Daniel Vetter87b6b102014-05-15 15:33:46 +02004628 drm_crtc_vblank_on(crtc);
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004629
4630 /* Underruns don't raise interrupts, so check manually. */
4631 i9xx_check_fifo_underruns(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004632}
4633
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004634static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4635{
4636 struct drm_device *dev = crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4640 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4641}
4642
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004643static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004644{
4645 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004646 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08004647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004648 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004649 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004650 int plane = intel_crtc->plane;
4651 u32 dspcntr;
Jesse Barnes79e53942008-11-07 14:24:08 -08004652
Daniel Vetter08a48462012-07-02 11:43:47 +02004653 WARN_ON(!crtc->enabled);
4654
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004655 if (intel_crtc->active)
4656 return;
4657
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004658 i9xx_set_pll_dividers(intel_crtc);
4659
Daniel Vetter5b18e572014-04-24 23:55:06 +02004660 /* Set up the display plane register */
4661 dspcntr = DISPPLANE_GAMMA_ENABLE;
4662
4663 if (pipe == 0)
4664 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4665 else
4666 dspcntr |= DISPPLANE_SEL_PIPE_B;
4667
4668 if (intel_crtc->config.has_dp_encoder)
4669 intel_dp_set_m_n(intel_crtc);
4670
4671 intel_set_pipe_timings(intel_crtc);
4672
4673 /* pipesrc and dspsize control the size that is scaled from,
4674 * which should always be the user's requested size.
4675 */
4676 I915_WRITE(DSPSIZE(plane),
4677 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4678 (intel_crtc->config.pipe_src_w - 1));
4679 I915_WRITE(DSPPOS(plane), 0);
4680
4681 i9xx_set_pipeconf(intel_crtc);
4682
4683 I915_WRITE(DSPCNTR(plane), dspcntr);
4684 POSTING_READ(DSPCNTR(plane));
4685
4686 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4687 crtc->x, crtc->y);
4688
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004689 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004690
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004691 if (!IS_GEN2(dev))
4692 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4693
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004694 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004695 if (encoder->pre_enable)
4696 encoder->pre_enable(encoder);
4697
Daniel Vetterf6736a12013-06-05 13:34:30 +02004698 i9xx_enable_pll(intel_crtc);
4699
Jesse Barnes2dd24552013-04-25 12:55:01 -07004700 i9xx_pfit_enable(intel_crtc);
4701
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004702 intel_crtc_load_lut(crtc);
4703
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004704 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004705 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004706
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004707 for_each_encoder_on_crtc(dev, crtc, encoder)
4708 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004709
4710 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004711
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004712 /*
4713 * Gen2 reports pipe underruns whenever all planes are disabled.
4714 * So don't enable underrun reporting before at least some planes
4715 * are enabled.
4716 * FIXME: Need to fix the logic to work when we turn off all planes
4717 * but leave the pipe running.
4718 */
4719 if (IS_GEN2(dev))
4720 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4721
Daniel Vetter87b6b102014-05-15 15:33:46 +02004722 drm_crtc_vblank_on(crtc);
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004723
4724 /* Underruns don't raise interrupts, so check manually. */
4725 i9xx_check_fifo_underruns(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004726}
4727
Daniel Vetter87476d62013-04-11 16:29:06 +02004728static void i9xx_pfit_disable(struct intel_crtc *crtc)
4729{
4730 struct drm_device *dev = crtc->base.dev;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004732
4733 if (!crtc->config.gmch_pfit.control)
4734 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004735
4736 assert_pipe_disabled(dev_priv, crtc->pipe);
4737
Daniel Vetter328d8e82013-05-08 10:36:31 +02004738 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4739 I915_READ(PFIT_CONTROL));
4740 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004741}
4742
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004743static void i9xx_crtc_disable(struct drm_crtc *crtc)
4744{
4745 struct drm_device *dev = crtc->dev;
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004748 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004749 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004750
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004751 if (!intel_crtc->active)
4752 return;
4753
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004754 /*
4755 * Gen2 reports pipe underruns whenever all planes are disabled.
4756 * So diasble underrun reporting before all the planes get disabled.
4757 * FIXME: Need to fix the logic to work when we turn off all planes
4758 * but leave the pipe running.
4759 */
4760 if (IS_GEN2(dev))
4761 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4762
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004763 intel_crtc_disable_planes(crtc);
4764
Daniel Vetterea9d7582012-07-10 10:42:52 +02004765 for_each_encoder_on_crtc(dev, crtc, encoder)
4766 encoder->disable(encoder);
4767
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004768 /*
4769 * On gen2 planes are double buffered but the pipe isn't, so we must
4770 * wait for planes to fully turn off before disabling the pipe.
4771 */
4772 if (IS_GEN2(dev))
4773 intel_wait_for_vblank(dev, pipe);
4774
Jesse Barnesb24e7172011-01-04 15:09:30 -08004775 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004776
Daniel Vetter87476d62013-04-11 16:29:06 +02004777 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004778
Jesse Barnes89b667f2013-04-18 14:51:36 -07004779 for_each_encoder_on_crtc(dev, crtc, encoder)
4780 if (encoder->post_disable)
4781 encoder->post_disable(encoder);
4782
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03004783 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4784 if (IS_CHERRYVIEW(dev))
4785 chv_disable_pll(dev_priv, pipe);
4786 else if (IS_VALLEYVIEW(dev))
4787 vlv_disable_pll(dev_priv, pipe);
4788 else
4789 i9xx_disable_pll(dev_priv, pipe);
4790 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004791
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004792 if (!IS_GEN2(dev))
4793 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4794
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004795 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004796 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004797
Daniel Vetterefa96242014-04-24 23:55:02 +02004798 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004799 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004800 intel_edp_psr_update(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02004801 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004802}
4803
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004804static void i9xx_crtc_off(struct drm_crtc *crtc)
4805{
4806}
4807
Daniel Vetter976f8a22012-07-08 22:34:21 +02004808static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4809 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004810{
4811 struct drm_device *dev = crtc->dev;
4812 struct drm_i915_master_private *master_priv;
4813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004815
4816 if (!dev->primary->master)
4817 return;
4818
4819 master_priv = dev->primary->master->driver_priv;
4820 if (!master_priv->sarea_priv)
4821 return;
4822
Jesse Barnes79e53942008-11-07 14:24:08 -08004823 switch (pipe) {
4824 case 0:
4825 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4826 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4827 break;
4828 case 1:
4829 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4830 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4831 break;
4832 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004833 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004834 break;
4835 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004836}
4837
Daniel Vetter976f8a22012-07-08 22:34:21 +02004838/**
4839 * Sets the power management mode of the pipe and plane.
4840 */
4841void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004842{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004843 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004844 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004845 struct intel_encoder *intel_encoder;
4846 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004847
Daniel Vetter976f8a22012-07-08 22:34:21 +02004848 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4849 enable |= intel_encoder->connectors_active;
4850
4851 if (enable)
4852 dev_priv->display.crtc_enable(crtc);
4853 else
4854 dev_priv->display.crtc_disable(crtc);
4855
4856 intel_crtc_update_sarea(crtc, enable);
4857}
4858
Daniel Vetter976f8a22012-07-08 22:34:21 +02004859static void intel_crtc_disable(struct drm_crtc *crtc)
4860{
4861 struct drm_device *dev = crtc->dev;
4862 struct drm_connector *connector;
4863 struct drm_i915_private *dev_priv = dev->dev_private;
4864
4865 /* crtc should still be enabled when we disable it. */
4866 WARN_ON(!crtc->enabled);
4867
4868 dev_priv->display.crtc_disable(crtc);
4869 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004870 dev_priv->display.off(crtc);
4871
Chris Wilson931872f2012-01-16 23:01:13 +00004872 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03004873 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Chris Wilson931872f2012-01-16 23:01:13 +00004874 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004875
Matt Roperf4510a22014-04-01 15:22:40 -07004876 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01004877 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004878 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004879 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004880 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004881 }
4882
4883 /* Update computed state. */
4884 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4885 if (!connector->encoder || !connector->encoder->crtc)
4886 continue;
4887
4888 if (connector->encoder->crtc != crtc)
4889 continue;
4890
4891 connector->dpms = DRM_MODE_DPMS_OFF;
4892 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004893 }
4894}
4895
Chris Wilsonea5b2132010-08-04 13:50:23 +01004896void intel_encoder_destroy(struct drm_encoder *encoder)
4897{
Chris Wilson4ef69c72010-09-09 15:14:28 +01004898 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01004899
Chris Wilsonea5b2132010-08-04 13:50:23 +01004900 drm_encoder_cleanup(encoder);
4901 kfree(intel_encoder);
4902}
4903
Damien Lespiau92373292013-08-08 22:28:57 +01004904/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004905 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4906 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01004907static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004908{
4909 if (mode == DRM_MODE_DPMS_ON) {
4910 encoder->connectors_active = true;
4911
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004912 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004913 } else {
4914 encoder->connectors_active = false;
4915
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004916 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004917 }
4918}
4919
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004920/* Cross check the actual hw state with our own modeset state tracking (and it's
4921 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02004922static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004923{
4924 if (connector->get_hw_state(connector)) {
4925 struct intel_encoder *encoder = connector->encoder;
4926 struct drm_crtc *crtc;
4927 bool encoder_enabled;
4928 enum pipe pipe;
4929
4930 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4931 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03004932 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004933
4934 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4935 "wrong connector dpms state\n");
4936 WARN(connector->base.encoder != &encoder->base,
4937 "active connector not linked to encoder\n");
4938 WARN(!encoder->connectors_active,
4939 "encoder->connectors_active not set\n");
4940
4941 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4942 WARN(!encoder_enabled, "encoder not enabled\n");
4943 if (WARN_ON(!encoder->base.crtc))
4944 return;
4945
4946 crtc = encoder->base.crtc;
4947
4948 WARN(!crtc->enabled, "crtc not enabled\n");
4949 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4950 WARN(pipe != to_intel_crtc(crtc)->pipe,
4951 "encoder active on the wrong pipe\n");
4952 }
4953}
4954
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004955/* Even simpler default implementation, if there's really no special case to
4956 * consider. */
4957void intel_connector_dpms(struct drm_connector *connector, int mode)
4958{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004959 /* All the simple cases only support two dpms states. */
4960 if (mode != DRM_MODE_DPMS_ON)
4961 mode = DRM_MODE_DPMS_OFF;
4962
4963 if (mode == connector->dpms)
4964 return;
4965
4966 connector->dpms = mode;
4967
4968 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01004969 if (connector->encoder)
4970 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004971
Daniel Vetterb9805142012-08-31 17:37:33 +02004972 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004973}
4974
Daniel Vetterf0947c32012-07-02 13:10:34 +02004975/* Simple connector->get_hw_state implementation for encoders that support only
4976 * one connector and no cloning and hence the encoder state determines the state
4977 * of the connector. */
4978bool intel_connector_get_hw_state(struct intel_connector *connector)
4979{
Daniel Vetter24929352012-07-02 20:28:59 +02004980 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02004981 struct intel_encoder *encoder = connector->encoder;
4982
4983 return encoder->get_hw_state(encoder, &pipe);
4984}
4985
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004986static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4987 struct intel_crtc_config *pipe_config)
4988{
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 struct intel_crtc *pipe_B_crtc =
4991 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4992
4993 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4994 pipe_name(pipe), pipe_config->fdi_lanes);
4995 if (pipe_config->fdi_lanes > 4) {
4996 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4997 pipe_name(pipe), pipe_config->fdi_lanes);
4998 return false;
4999 }
5000
Paulo Zanonibafb6552013-11-02 21:07:44 -07005001 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005002 if (pipe_config->fdi_lanes > 2) {
5003 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5004 pipe_config->fdi_lanes);
5005 return false;
5006 } else {
5007 return true;
5008 }
5009 }
5010
5011 if (INTEL_INFO(dev)->num_pipes == 2)
5012 return true;
5013
5014 /* Ivybridge 3 pipe is really complicated */
5015 switch (pipe) {
5016 case PIPE_A:
5017 return true;
5018 case PIPE_B:
5019 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5020 pipe_config->fdi_lanes > 2) {
5021 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5022 pipe_name(pipe), pipe_config->fdi_lanes);
5023 return false;
5024 }
5025 return true;
5026 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005027 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005028 pipe_B_crtc->config.fdi_lanes <= 2) {
5029 if (pipe_config->fdi_lanes > 2) {
5030 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5031 pipe_name(pipe), pipe_config->fdi_lanes);
5032 return false;
5033 }
5034 } else {
5035 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5036 return false;
5037 }
5038 return true;
5039 default:
5040 BUG();
5041 }
5042}
5043
Daniel Vettere29c22c2013-02-21 00:00:16 +01005044#define RETRY 1
5045static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5046 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005047{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005048 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005049 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005050 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005051 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005052
Daniel Vettere29c22c2013-02-21 00:00:16 +01005053retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005054 /* FDI is a binary signal running at ~2.7GHz, encoding
5055 * each output octet as 10 bits. The actual frequency
5056 * is stored as a divider into a 100MHz clock, and the
5057 * mode pixel clock is stored in units of 1KHz.
5058 * Hence the bw of each lane in terms of the mode signal
5059 * is:
5060 */
5061 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5062
Damien Lespiau241bfc32013-09-25 16:45:37 +01005063 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005064
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005065 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005066 pipe_config->pipe_bpp);
5067
5068 pipe_config->fdi_lanes = lane;
5069
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005070 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005071 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005072
Daniel Vettere29c22c2013-02-21 00:00:16 +01005073 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5074 intel_crtc->pipe, pipe_config);
5075 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5076 pipe_config->pipe_bpp -= 2*3;
5077 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5078 pipe_config->pipe_bpp);
5079 needs_recompute = true;
5080 pipe_config->bw_constrained = true;
5081
5082 goto retry;
5083 }
5084
5085 if (needs_recompute)
5086 return RETRY;
5087
5088 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005089}
5090
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005091static void hsw_compute_ips_config(struct intel_crtc *crtc,
5092 struct intel_crtc_config *pipe_config)
5093{
Jani Nikulad330a952014-01-21 11:24:25 +02005094 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005095 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005096 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005097}
5098
Daniel Vettera43f6e02013-06-07 23:10:32 +02005099static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005100 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005101{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005102 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005103 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005104
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005105 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005106 if (INTEL_INFO(dev)->gen < 4) {
5107 struct drm_i915_private *dev_priv = dev->dev_private;
5108 int clock_limit =
5109 dev_priv->display.get_display_clock_speed(dev);
5110
5111 /*
5112 * Enable pixel doubling when the dot clock
5113 * is > 90% of the (display) core speed.
5114 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005115 * GDG double wide on either pipe,
5116 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005117 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005118 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005119 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005120 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005121 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005122 }
5123
Damien Lespiau241bfc32013-09-25 16:45:37 +01005124 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005125 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005126 }
Chris Wilson89749352010-09-12 18:25:19 +01005127
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005128 /*
5129 * Pipe horizontal size must be even in:
5130 * - DVO ganged mode
5131 * - LVDS dual channel mode
5132 * - Double wide pipe
5133 */
5134 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5135 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5136 pipe_config->pipe_src_w &= ~1;
5137
Damien Lespiau8693a822013-05-03 18:48:11 +01005138 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5139 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005140 */
5141 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5142 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005143 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005144
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005145 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005146 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005147 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005148 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5149 * for lvds. */
5150 pipe_config->pipe_bpp = 8*3;
5151 }
5152
Damien Lespiauf5adf942013-06-24 18:29:34 +01005153 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005154 hsw_compute_ips_config(crtc, pipe_config);
5155
5156 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5157 * clock survives for now. */
5158 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5159 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005160
Daniel Vetter877d48d2013-04-19 11:24:43 +02005161 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005162 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005163
Daniel Vettere29c22c2013-02-21 00:00:16 +01005164 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005165}
5166
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005167static int valleyview_get_display_clock_speed(struct drm_device *dev)
5168{
5169 return 400000; /* FIXME */
5170}
5171
Jesse Barnese70236a2009-09-21 10:42:27 -07005172static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005173{
Jesse Barnese70236a2009-09-21 10:42:27 -07005174 return 400000;
5175}
Jesse Barnes79e53942008-11-07 14:24:08 -08005176
Jesse Barnese70236a2009-09-21 10:42:27 -07005177static int i915_get_display_clock_speed(struct drm_device *dev)
5178{
5179 return 333000;
5180}
Jesse Barnes79e53942008-11-07 14:24:08 -08005181
Jesse Barnese70236a2009-09-21 10:42:27 -07005182static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5183{
5184 return 200000;
5185}
Jesse Barnes79e53942008-11-07 14:24:08 -08005186
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005187static int pnv_get_display_clock_speed(struct drm_device *dev)
5188{
5189 u16 gcfgc = 0;
5190
5191 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5192
5193 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5194 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5195 return 267000;
5196 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5197 return 333000;
5198 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5199 return 444000;
5200 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5201 return 200000;
5202 default:
5203 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5204 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5205 return 133000;
5206 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5207 return 167000;
5208 }
5209}
5210
Jesse Barnese70236a2009-09-21 10:42:27 -07005211static int i915gm_get_display_clock_speed(struct drm_device *dev)
5212{
5213 u16 gcfgc = 0;
5214
5215 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5216
5217 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005218 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005219 else {
5220 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5221 case GC_DISPLAY_CLOCK_333_MHZ:
5222 return 333000;
5223 default:
5224 case GC_DISPLAY_CLOCK_190_200_MHZ:
5225 return 190000;
5226 }
5227 }
5228}
Jesse Barnes79e53942008-11-07 14:24:08 -08005229
Jesse Barnese70236a2009-09-21 10:42:27 -07005230static int i865_get_display_clock_speed(struct drm_device *dev)
5231{
5232 return 266000;
5233}
5234
5235static int i855_get_display_clock_speed(struct drm_device *dev)
5236{
5237 u16 hpllcc = 0;
5238 /* Assume that the hardware is in the high speed state. This
5239 * should be the default.
5240 */
5241 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5242 case GC_CLOCK_133_200:
5243 case GC_CLOCK_100_200:
5244 return 200000;
5245 case GC_CLOCK_166_250:
5246 return 250000;
5247 case GC_CLOCK_100_133:
5248 return 133000;
5249 }
5250
5251 /* Shouldn't happen */
5252 return 0;
5253}
5254
5255static int i830_get_display_clock_speed(struct drm_device *dev)
5256{
5257 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005258}
5259
Zhenyu Wang2c072452009-06-05 15:38:42 +08005260static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005261intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005262{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005263 while (*num > DATA_LINK_M_N_MASK ||
5264 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005265 *num >>= 1;
5266 *den >>= 1;
5267 }
5268}
5269
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005270static void compute_m_n(unsigned int m, unsigned int n,
5271 uint32_t *ret_m, uint32_t *ret_n)
5272{
5273 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5274 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5275 intel_reduce_m_n_ratio(ret_m, ret_n);
5276}
5277
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005278void
5279intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5280 int pixel_clock, int link_clock,
5281 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005282{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005283 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005284
5285 compute_m_n(bits_per_pixel * pixel_clock,
5286 link_clock * nlanes * 8,
5287 &m_n->gmch_m, &m_n->gmch_n);
5288
5289 compute_m_n(pixel_clock, link_clock,
5290 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005291}
5292
Chris Wilsona7615032011-01-12 17:04:08 +00005293static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5294{
Jani Nikulad330a952014-01-21 11:24:25 +02005295 if (i915.panel_use_ssc >= 0)
5296 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005297 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005298 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005299}
5300
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005301static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5302{
5303 struct drm_device *dev = crtc->dev;
5304 struct drm_i915_private *dev_priv = dev->dev_private;
5305 int refclk;
5306
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005307 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005308 refclk = 100000;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005309 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005310 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005311 refclk = dev_priv->vbt.lvds_ssc_freq;
5312 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005313 } else if (!IS_GEN2(dev)) {
5314 refclk = 96000;
5315 } else {
5316 refclk = 48000;
5317 }
5318
5319 return refclk;
5320}
5321
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005322static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005323{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005324 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005325}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005326
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005327static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5328{
5329 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005330}
5331
Daniel Vetterf47709a2013-03-28 10:42:02 +01005332static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005333 intel_clock_t *reduced_clock)
5334{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005335 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005336 u32 fp, fp2 = 0;
5337
5338 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005339 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005340 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005341 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005342 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005343 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005344 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005345 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005346 }
5347
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005348 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005349
Daniel Vetterf47709a2013-03-28 10:42:02 +01005350 crtc->lowfreq_avail = false;
5351 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005352 reduced_clock && i915.powersave) {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005353 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005354 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005355 } else {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005356 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005357 }
5358}
5359
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005360static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5361 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005362{
5363 u32 reg_val;
5364
5365 /*
5366 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5367 * and set it to a reasonable value instead.
5368 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005369 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005370 reg_val &= 0xffffff00;
5371 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005373
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005374 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005375 reg_val &= 0x8cffffff;
5376 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005377 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005378
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005379 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005380 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005382
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005383 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005384 reg_val &= 0x00ffffff;
5385 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005386 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005387}
5388
Daniel Vetterb5518422013-05-03 11:49:48 +02005389static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5390 struct intel_link_m_n *m_n)
5391{
5392 struct drm_device *dev = crtc->base.dev;
5393 struct drm_i915_private *dev_priv = dev->dev_private;
5394 int pipe = crtc->pipe;
5395
Daniel Vettere3b95f12013-05-03 11:49:49 +02005396 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5397 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5398 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5399 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005400}
5401
5402static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5403 struct intel_link_m_n *m_n)
5404{
5405 struct drm_device *dev = crtc->base.dev;
5406 struct drm_i915_private *dev_priv = dev->dev_private;
5407 int pipe = crtc->pipe;
5408 enum transcoder transcoder = crtc->config.cpu_transcoder;
5409
5410 if (INTEL_INFO(dev)->gen >= 5) {
5411 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5412 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5413 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5414 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5415 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005416 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5417 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5418 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5419 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005420 }
5421}
5422
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005423static void intel_dp_set_m_n(struct intel_crtc *crtc)
5424{
5425 if (crtc->config.has_pch_encoder)
5426 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5427 else
5428 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5429}
5430
Daniel Vetterf47709a2013-03-28 10:42:02 +01005431static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005432{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005433 u32 dpll, dpll_md;
5434
5435 /*
5436 * Enable DPIO clock input. We should never disable the reference
5437 * clock for pipe B, since VGA hotplug / manual detection depends
5438 * on it.
5439 */
5440 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5441 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5442 /* We should never disable this, set it here for state tracking */
5443 if (crtc->pipe == PIPE_B)
5444 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5445 dpll |= DPLL_VCO_ENABLE;
5446 crtc->config.dpll_hw_state.dpll = dpll;
5447
5448 dpll_md = (crtc->config.pixel_multiplier - 1)
5449 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5450 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5451}
5452
5453static void vlv_prepare_pll(struct intel_crtc *crtc)
5454{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005455 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005456 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005457 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005458 u32 mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005459 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005460 u32 coreclk, reg_val;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005461
Daniel Vetter09153002012-12-12 14:06:44 +01005462 mutex_lock(&dev_priv->dpio_lock);
5463
Daniel Vetterf47709a2013-03-28 10:42:02 +01005464 bestn = crtc->config.dpll.n;
5465 bestm1 = crtc->config.dpll.m1;
5466 bestm2 = crtc->config.dpll.m2;
5467 bestp1 = crtc->config.dpll.p1;
5468 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005469
Jesse Barnes89b667f2013-04-18 14:51:36 -07005470 /* See eDP HDMI DPIO driver vbios notes doc */
5471
5472 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005473 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005474 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005475
5476 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005477 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005478
5479 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005480 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005481 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005482 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005483
5484 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005485 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005486
5487 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005488 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5489 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5490 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005491 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005492
5493 /*
5494 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5495 * but we don't support that).
5496 * Note: don't use the DAC post divider as it seems unstable.
5497 */
5498 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005499 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005500
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005501 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005502 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005503
Jesse Barnes89b667f2013-04-18 14:51:36 -07005504 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02005505 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03005506 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07005507 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005508 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03005509 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005510 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005511 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005512 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005513
Jesse Barnes89b667f2013-04-18 14:51:36 -07005514 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5515 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5516 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005517 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005518 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005519 0x0df40000);
5520 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005521 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005522 0x0df70000);
5523 } else { /* HDMI or VGA */
5524 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005525 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005526 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005527 0x0df70000);
5528 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005529 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005530 0x0df40000);
5531 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005532
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005533 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005534 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5535 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5536 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5537 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005538 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005539
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005540 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005541 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005542}
5543
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005544static void chv_update_pll(struct intel_crtc *crtc)
5545{
5546 struct drm_device *dev = crtc->base.dev;
5547 struct drm_i915_private *dev_priv = dev->dev_private;
5548 int pipe = crtc->pipe;
5549 int dpll_reg = DPLL(crtc->pipe);
5550 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005551 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005552 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5553 int refclk;
5554
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005555 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5556 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5557 DPLL_VCO_ENABLE;
5558 if (pipe != PIPE_A)
5559 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5560
5561 crtc->config.dpll_hw_state.dpll_md =
5562 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005563
5564 bestn = crtc->config.dpll.n;
5565 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5566 bestm1 = crtc->config.dpll.m1;
5567 bestm2 = crtc->config.dpll.m2 >> 22;
5568 bestp1 = crtc->config.dpll.p1;
5569 bestp2 = crtc->config.dpll.p2;
5570
5571 /*
5572 * Enable Refclk and SSC
5573 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005574 I915_WRITE(dpll_reg,
5575 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5576
5577 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005578
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005579 /* p1 and p2 divider */
5580 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5581 5 << DPIO_CHV_S1_DIV_SHIFT |
5582 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5583 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5584 1 << DPIO_CHV_K_DIV_SHIFT);
5585
5586 /* Feedback post-divider - m2 */
5587 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5588
5589 /* Feedback refclk divider - n and m1 */
5590 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5591 DPIO_CHV_M1_DIV_BY_2 |
5592 1 << DPIO_CHV_N_DIV_SHIFT);
5593
5594 /* M2 fraction division */
5595 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5596
5597 /* M2 fraction division enable */
5598 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5599 DPIO_CHV_FRAC_DIV_EN |
5600 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5601
5602 /* Loop filter */
5603 refclk = i9xx_get_refclk(&crtc->base, 0);
5604 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5605 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5606 if (refclk == 100000)
5607 intcoeff = 11;
5608 else if (refclk == 38400)
5609 intcoeff = 10;
5610 else
5611 intcoeff = 9;
5612 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5613 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5614
5615 /* AFC Recal */
5616 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5617 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5618 DPIO_AFC_RECAL);
5619
5620 mutex_unlock(&dev_priv->dpio_lock);
5621}
5622
Daniel Vetterf47709a2013-03-28 10:42:02 +01005623static void i9xx_update_pll(struct intel_crtc *crtc,
5624 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005625 int num_connectors)
5626{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005627 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005628 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005629 u32 dpll;
5630 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005631 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005632
Daniel Vetterf47709a2013-03-28 10:42:02 +01005633 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305634
Daniel Vetterf47709a2013-03-28 10:42:02 +01005635 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5636 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005637
5638 dpll = DPLL_VGA_MODE_DIS;
5639
Daniel Vetterf47709a2013-03-28 10:42:02 +01005640 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005641 dpll |= DPLLB_MODE_LVDS;
5642 else
5643 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005644
Daniel Vetteref1b4602013-06-01 17:17:04 +02005645 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02005646 dpll |= (crtc->config.pixel_multiplier - 1)
5647 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005648 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02005649
5650 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02005651 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005652
Daniel Vetterf47709a2013-03-28 10:42:02 +01005653 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02005654 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005655
5656 /* compute bitmask from p1 value */
5657 if (IS_PINEVIEW(dev))
5658 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5659 else {
5660 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5661 if (IS_G4X(dev) && reduced_clock)
5662 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5663 }
5664 switch (clock->p2) {
5665 case 5:
5666 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5667 break;
5668 case 7:
5669 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5670 break;
5671 case 10:
5672 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5673 break;
5674 case 14:
5675 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5676 break;
5677 }
5678 if (INTEL_INFO(dev)->gen >= 4)
5679 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5680
Daniel Vetter09ede542013-04-30 14:01:45 +02005681 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005682 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005683 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005684 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5685 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5686 else
5687 dpll |= PLL_REF_INPUT_DREFCLK;
5688
5689 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005690 crtc->config.dpll_hw_state.dpll = dpll;
5691
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005692 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005693 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5694 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005695 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005696 }
5697}
5698
Daniel Vetterf47709a2013-03-28 10:42:02 +01005699static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005700 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005701 int num_connectors)
5702{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005703 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005704 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005705 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005706 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005707
Daniel Vetterf47709a2013-03-28 10:42:02 +01005708 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305709
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005710 dpll = DPLL_VGA_MODE_DIS;
5711
Daniel Vetterf47709a2013-03-28 10:42:02 +01005712 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005713 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5714 } else {
5715 if (clock->p1 == 2)
5716 dpll |= PLL_P1_DIVIDE_BY_TWO;
5717 else
5718 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5719 if (clock->p2 == 4)
5720 dpll |= PLL_P2_DIVIDE_BY_4;
5721 }
5722
Daniel Vetter4a33e482013-07-06 12:52:05 +02005723 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5724 dpll |= DPLL_DVO_2X_MODE;
5725
Daniel Vetterf47709a2013-03-28 10:42:02 +01005726 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005727 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5728 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5729 else
5730 dpll |= PLL_REF_INPUT_DREFCLK;
5731
5732 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005733 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005734}
5735
Daniel Vetter8a654f32013-06-01 17:16:22 +02005736static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005737{
5738 struct drm_device *dev = intel_crtc->base.dev;
5739 struct drm_i915_private *dev_priv = dev->dev_private;
5740 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005741 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005742 struct drm_display_mode *adjusted_mode =
5743 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005744 uint32_t crtc_vtotal, crtc_vblank_end;
5745 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005746
5747 /* We need to be careful not to changed the adjusted mode, for otherwise
5748 * the hw state checker will get angry at the mismatch. */
5749 crtc_vtotal = adjusted_mode->crtc_vtotal;
5750 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005751
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005752 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005753 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005754 crtc_vtotal -= 1;
5755 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005756
5757 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5758 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5759 else
5760 vsyncshift = adjusted_mode->crtc_hsync_start -
5761 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005762 if (vsyncshift < 0)
5763 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005764 }
5765
5766 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005767 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005768
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005769 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005770 (adjusted_mode->crtc_hdisplay - 1) |
5771 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005772 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005773 (adjusted_mode->crtc_hblank_start - 1) |
5774 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005775 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005776 (adjusted_mode->crtc_hsync_start - 1) |
5777 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5778
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005779 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005780 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005781 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005782 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005783 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005784 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005785 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005786 (adjusted_mode->crtc_vsync_start - 1) |
5787 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5788
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005789 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5790 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5791 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5792 * bits. */
5793 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5794 (pipe == PIPE_B || pipe == PIPE_C))
5795 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5796
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005797 /* pipesrc controls the size that is scaled from, which should
5798 * always be the user's requested size.
5799 */
5800 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005801 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5802 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005803}
5804
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005805static void intel_get_pipe_timings(struct intel_crtc *crtc,
5806 struct intel_crtc_config *pipe_config)
5807{
5808 struct drm_device *dev = crtc->base.dev;
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5811 uint32_t tmp;
5812
5813 tmp = I915_READ(HTOTAL(cpu_transcoder));
5814 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5815 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5816 tmp = I915_READ(HBLANK(cpu_transcoder));
5817 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5818 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5819 tmp = I915_READ(HSYNC(cpu_transcoder));
5820 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5821 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5822
5823 tmp = I915_READ(VTOTAL(cpu_transcoder));
5824 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5825 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5826 tmp = I915_READ(VBLANK(cpu_transcoder));
5827 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5828 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5829 tmp = I915_READ(VSYNC(cpu_transcoder));
5830 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5831 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5832
5833 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5834 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5835 pipe_config->adjusted_mode.crtc_vtotal += 1;
5836 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5837 }
5838
5839 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005840 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5841 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5842
5843 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5844 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005845}
5846
Daniel Vetterf6a83282014-02-11 15:28:57 -08005847void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5848 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03005849{
Daniel Vetterf6a83282014-02-11 15:28:57 -08005850 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5851 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5852 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5853 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005854
Daniel Vetterf6a83282014-02-11 15:28:57 -08005855 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5856 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5857 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5858 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005859
Daniel Vetterf6a83282014-02-11 15:28:57 -08005860 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03005861
Daniel Vetterf6a83282014-02-11 15:28:57 -08005862 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5863 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03005864}
5865
Daniel Vetter84b046f2013-02-19 18:48:54 +01005866static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5867{
5868 struct drm_device *dev = intel_crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 uint32_t pipeconf;
5871
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005872 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005873
Daniel Vetter67c72a12013-09-24 11:46:14 +02005874 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5875 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5876 pipeconf |= PIPECONF_ENABLE;
5877
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005878 if (intel_crtc->config.double_wide)
5879 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005880
Daniel Vetterff9ce462013-04-24 14:57:17 +02005881 /* only g4x and later have fancy bpc/dither controls */
5882 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02005883 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5884 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5885 pipeconf |= PIPECONF_DITHER_EN |
5886 PIPECONF_DITHER_TYPE_SP;
5887
5888 switch (intel_crtc->config.pipe_bpp) {
5889 case 18:
5890 pipeconf |= PIPECONF_6BPC;
5891 break;
5892 case 24:
5893 pipeconf |= PIPECONF_8BPC;
5894 break;
5895 case 30:
5896 pipeconf |= PIPECONF_10BPC;
5897 break;
5898 default:
5899 /* Case prevented by intel_choose_pipe_bpp_dither. */
5900 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01005901 }
5902 }
5903
5904 if (HAS_PIPE_CXSR(dev)) {
5905 if (intel_crtc->lowfreq_avail) {
5906 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5907 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5908 } else {
5909 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01005910 }
5911 }
5912
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02005913 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5914 if (INTEL_INFO(dev)->gen < 4 ||
5915 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5916 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5917 else
5918 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5919 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01005920 pipeconf |= PIPECONF_PROGRESSIVE;
5921
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005922 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5923 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03005924
Daniel Vetter84b046f2013-02-19 18:48:54 +01005925 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5926 POSTING_READ(PIPECONF(intel_crtc->pipe));
5927}
5928
Eric Anholtf564048e2011-03-30 13:01:02 -07005929static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07005930 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005931 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005932{
5933 struct drm_device *dev = crtc->dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Eric Anholtc751ce42010-03-25 11:48:48 -07005936 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07005937 intel_clock_t clock, reduced_clock;
Daniel Vettera16af7212013-04-30 14:01:44 +02005938 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005939 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01005940 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08005941 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08005942
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005943 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005944 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005945 case INTEL_OUTPUT_LVDS:
5946 is_lvds = true;
5947 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005948 case INTEL_OUTPUT_DSI:
5949 is_dsi = true;
5950 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005951 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005952
Eric Anholtc751ce42010-03-25 11:48:48 -07005953 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08005954 }
5955
Jani Nikulaf2335332013-09-13 11:03:09 +03005956 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02005957 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005958
Jani Nikulaf2335332013-09-13 11:03:09 +03005959 if (!intel_crtc->config.clock_set) {
5960 refclk = i9xx_get_refclk(crtc, num_connectors);
5961
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005962 /*
5963 * Returns a set of divisors for the desired target clock with
5964 * the given refclk, or FALSE. The returned values represent
5965 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5966 * 2) / p1 / p2.
5967 */
5968 limit = intel_limit(crtc, refclk);
5969 ok = dev_priv->display.find_dpll(limit, crtc,
5970 intel_crtc->config.port_clock,
5971 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03005972 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005973 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5974 return -EINVAL;
5975 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005976
Jani Nikulaf2335332013-09-13 11:03:09 +03005977 if (is_lvds && dev_priv->lvds_downclock_avail) {
5978 /*
5979 * Ensure we match the reduced clock's P to the target
5980 * clock. If the clocks don't match, we can't switch
5981 * the display clock by using the FP0/FP1. In such case
5982 * we will disable the LVDS downclock feature.
5983 */
5984 has_reduced_clock =
5985 dev_priv->display.find_dpll(limit, crtc,
5986 dev_priv->lvds_downclock,
5987 refclk, &clock,
5988 &reduced_clock);
5989 }
5990 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01005991 intel_crtc->config.dpll.n = clock.n;
5992 intel_crtc->config.dpll.m1 = clock.m1;
5993 intel_crtc->config.dpll.m2 = clock.m2;
5994 intel_crtc->config.dpll.p1 = clock.p1;
5995 intel_crtc->config.dpll.p2 = clock.p2;
5996 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005997
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005998 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02005999 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306000 has_reduced_clock ? &reduced_clock : NULL,
6001 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006002 } else if (IS_CHERRYVIEW(dev)) {
6003 chv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006004 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03006005 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006006 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01006007 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006008 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006009 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006010 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006011
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006012 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006013}
6014
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006015static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6016 struct intel_crtc_config *pipe_config)
6017{
6018 struct drm_device *dev = crtc->base.dev;
6019 struct drm_i915_private *dev_priv = dev->dev_private;
6020 uint32_t tmp;
6021
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006022 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6023 return;
6024
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006025 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006026 if (!(tmp & PFIT_ENABLE))
6027 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006028
Daniel Vetter06922822013-07-11 13:35:40 +02006029 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006030 if (INTEL_INFO(dev)->gen < 4) {
6031 if (crtc->pipe != PIPE_B)
6032 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006033 } else {
6034 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6035 return;
6036 }
6037
Daniel Vetter06922822013-07-11 13:35:40 +02006038 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006039 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6040 if (INTEL_INFO(dev)->gen < 5)
6041 pipe_config->gmch_pfit.lvds_border_bits =
6042 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6043}
6044
Jesse Barnesacbec812013-09-20 11:29:32 -07006045static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6046 struct intel_crtc_config *pipe_config)
6047{
6048 struct drm_device *dev = crtc->base.dev;
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050 int pipe = pipe_config->cpu_transcoder;
6051 intel_clock_t clock;
6052 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006053 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006054
6055 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006056 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006057 mutex_unlock(&dev_priv->dpio_lock);
6058
6059 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6060 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6061 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6062 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6063 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6064
Ville Syrjäläf6466282013-10-14 14:50:31 +03006065 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006066
Ville Syrjäläf6466282013-10-14 14:50:31 +03006067 /* clock.dot is the fast clock */
6068 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006069}
6070
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006071static void i9xx_get_plane_config(struct intel_crtc *crtc,
6072 struct intel_plane_config *plane_config)
6073{
6074 struct drm_device *dev = crtc->base.dev;
6075 struct drm_i915_private *dev_priv = dev->dev_private;
6076 u32 val, base, offset;
6077 int pipe = crtc->pipe, plane = crtc->plane;
6078 int fourcc, pixel_format;
6079 int aligned_height;
6080
Dave Airlie66e514c2014-04-03 07:51:54 +10006081 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6082 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006083 DRM_DEBUG_KMS("failed to alloc fb\n");
6084 return;
6085 }
6086
6087 val = I915_READ(DSPCNTR(plane));
6088
6089 if (INTEL_INFO(dev)->gen >= 4)
6090 if (val & DISPPLANE_TILED)
6091 plane_config->tiled = true;
6092
6093 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6094 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006095 crtc->base.primary->fb->pixel_format = fourcc;
6096 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006097 drm_format_plane_cpp(fourcc, 0) * 8;
6098
6099 if (INTEL_INFO(dev)->gen >= 4) {
6100 if (plane_config->tiled)
6101 offset = I915_READ(DSPTILEOFF(plane));
6102 else
6103 offset = I915_READ(DSPLINOFF(plane));
6104 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6105 } else {
6106 base = I915_READ(DSPADDR(plane));
6107 }
6108 plane_config->base = base;
6109
6110 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006111 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6112 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006113
6114 val = I915_READ(DSPSTRIDE(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006115 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006116
Dave Airlie66e514c2014-04-03 07:51:54 +10006117 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006118 plane_config->tiled);
6119
Dave Airlie66e514c2014-04-03 07:51:54 +10006120 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006121 aligned_height, PAGE_SIZE);
6122
6123 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006124 pipe, plane, crtc->base.primary->fb->width,
6125 crtc->base.primary->fb->height,
6126 crtc->base.primary->fb->bits_per_pixel, base,
6127 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006128 plane_config->size);
6129
6130}
6131
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006132static void chv_crtc_clock_get(struct intel_crtc *crtc,
6133 struct intel_crtc_config *pipe_config)
6134{
6135 struct drm_device *dev = crtc->base.dev;
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 int pipe = pipe_config->cpu_transcoder;
6138 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6139 intel_clock_t clock;
6140 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6141 int refclk = 100000;
6142
6143 mutex_lock(&dev_priv->dpio_lock);
6144 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6145 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6146 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6147 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6148 mutex_unlock(&dev_priv->dpio_lock);
6149
6150 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6151 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6152 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6153 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6154 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6155
6156 chv_clock(refclk, &clock);
6157
6158 /* clock.dot is the fast clock */
6159 pipe_config->port_clock = clock.dot / 5;
6160}
6161
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006162static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6163 struct intel_crtc_config *pipe_config)
6164{
6165 struct drm_device *dev = crtc->base.dev;
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167 uint32_t tmp;
6168
Imre Deakb5482bd2014-03-05 16:20:55 +02006169 if (!intel_display_power_enabled(dev_priv,
6170 POWER_DOMAIN_PIPE(crtc->pipe)))
6171 return false;
6172
Daniel Vettere143a212013-07-04 12:01:15 +02006173 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006174 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006175
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006176 tmp = I915_READ(PIPECONF(crtc->pipe));
6177 if (!(tmp & PIPECONF_ENABLE))
6178 return false;
6179
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006180 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6181 switch (tmp & PIPECONF_BPC_MASK) {
6182 case PIPECONF_6BPC:
6183 pipe_config->pipe_bpp = 18;
6184 break;
6185 case PIPECONF_8BPC:
6186 pipe_config->pipe_bpp = 24;
6187 break;
6188 case PIPECONF_10BPC:
6189 pipe_config->pipe_bpp = 30;
6190 break;
6191 default:
6192 break;
6193 }
6194 }
6195
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006196 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6197 pipe_config->limited_color_range = true;
6198
Ville Syrjälä282740f2013-09-04 18:30:03 +03006199 if (INTEL_INFO(dev)->gen < 4)
6200 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6201
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006202 intel_get_pipe_timings(crtc, pipe_config);
6203
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006204 i9xx_get_pfit_config(crtc, pipe_config);
6205
Daniel Vetter6c49f242013-06-06 12:45:25 +02006206 if (INTEL_INFO(dev)->gen >= 4) {
6207 tmp = I915_READ(DPLL_MD(crtc->pipe));
6208 pipe_config->pixel_multiplier =
6209 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6210 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006211 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006212 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6213 tmp = I915_READ(DPLL(crtc->pipe));
6214 pipe_config->pixel_multiplier =
6215 ((tmp & SDVO_MULTIPLIER_MASK)
6216 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6217 } else {
6218 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6219 * port and will be fixed up in the encoder->get_config
6220 * function. */
6221 pipe_config->pixel_multiplier = 1;
6222 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006223 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6224 if (!IS_VALLEYVIEW(dev)) {
6225 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6226 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006227 } else {
6228 /* Mask out read-only status bits. */
6229 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6230 DPLL_PORTC_READY_MASK |
6231 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006232 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006233
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006234 if (IS_CHERRYVIEW(dev))
6235 chv_crtc_clock_get(crtc, pipe_config);
6236 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006237 vlv_crtc_clock_get(crtc, pipe_config);
6238 else
6239 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006240
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006241 return true;
6242}
6243
Paulo Zanonidde86e22012-12-01 12:04:25 -02006244static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006245{
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6247 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006248 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006249 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006250 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006251 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006252 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006253 bool has_ck505 = false;
6254 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006255
6256 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07006257 list_for_each_entry(encoder, &mode_config->encoder_list,
6258 base.head) {
6259 switch (encoder->type) {
6260 case INTEL_OUTPUT_LVDS:
6261 has_panel = true;
6262 has_lvds = true;
6263 break;
6264 case INTEL_OUTPUT_EDP:
6265 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006266 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006267 has_cpu_edp = true;
6268 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006269 }
6270 }
6271
Keith Packard99eb6a02011-09-26 14:29:12 -07006272 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006273 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006274 can_ssc = has_ck505;
6275 } else {
6276 has_ck505 = false;
6277 can_ssc = true;
6278 }
6279
Imre Deak2de69052013-05-08 13:14:04 +03006280 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6281 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006282
6283 /* Ironlake: try to setup display ref clock before DPLL
6284 * enabling. This is only under driver's control after
6285 * PCH B stepping, previous chipset stepping should be
6286 * ignoring this setting.
6287 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006288 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006289
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006290 /* As we must carefully and slowly disable/enable each source in turn,
6291 * compute the final state we want first and check if we need to
6292 * make any changes at all.
6293 */
6294 final = val;
6295 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006296 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006297 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006298 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006299 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6300
6301 final &= ~DREF_SSC_SOURCE_MASK;
6302 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6303 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006304
Keith Packard199e5d72011-09-22 12:01:57 -07006305 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006306 final |= DREF_SSC_SOURCE_ENABLE;
6307
6308 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6309 final |= DREF_SSC1_ENABLE;
6310
6311 if (has_cpu_edp) {
6312 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6313 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6314 else
6315 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6316 } else
6317 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6318 } else {
6319 final |= DREF_SSC_SOURCE_DISABLE;
6320 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6321 }
6322
6323 if (final == val)
6324 return;
6325
6326 /* Always enable nonspread source */
6327 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6328
6329 if (has_ck505)
6330 val |= DREF_NONSPREAD_CK505_ENABLE;
6331 else
6332 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6333
6334 if (has_panel) {
6335 val &= ~DREF_SSC_SOURCE_MASK;
6336 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006337
Keith Packard199e5d72011-09-22 12:01:57 -07006338 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006339 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006340 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006341 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006342 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006343 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006344
6345 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006346 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006347 POSTING_READ(PCH_DREF_CONTROL);
6348 udelay(200);
6349
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006350 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006351
6352 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006353 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006354 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006355 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006356 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006357 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006358 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006359 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006360 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006361
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006362 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006363 POSTING_READ(PCH_DREF_CONTROL);
6364 udelay(200);
6365 } else {
6366 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6367
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006368 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006369
6370 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006371 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006372
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006373 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006374 POSTING_READ(PCH_DREF_CONTROL);
6375 udelay(200);
6376
6377 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006378 val &= ~DREF_SSC_SOURCE_MASK;
6379 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006380
6381 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006382 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006383
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006384 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006385 POSTING_READ(PCH_DREF_CONTROL);
6386 udelay(200);
6387 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006388
6389 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006390}
6391
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006392static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006393{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006394 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006395
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006396 tmp = I915_READ(SOUTH_CHICKEN2);
6397 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6398 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006399
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006400 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6401 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6402 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006403
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006404 tmp = I915_READ(SOUTH_CHICKEN2);
6405 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6406 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006407
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006408 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6409 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6410 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006411}
6412
6413/* WaMPhyProgramming:hsw */
6414static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6415{
6416 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006417
6418 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6419 tmp &= ~(0xFF << 24);
6420 tmp |= (0x12 << 24);
6421 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6422
Paulo Zanonidde86e22012-12-01 12:04:25 -02006423 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6424 tmp |= (1 << 11);
6425 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6426
6427 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6428 tmp |= (1 << 11);
6429 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6430
Paulo Zanonidde86e22012-12-01 12:04:25 -02006431 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6432 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6433 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6434
6435 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6436 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6437 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6438
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006439 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6440 tmp &= ~(7 << 13);
6441 tmp |= (5 << 13);
6442 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006443
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006444 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6445 tmp &= ~(7 << 13);
6446 tmp |= (5 << 13);
6447 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006448
6449 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6450 tmp &= ~0xFF;
6451 tmp |= 0x1C;
6452 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6453
6454 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6455 tmp &= ~0xFF;
6456 tmp |= 0x1C;
6457 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6458
6459 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6460 tmp &= ~(0xFF << 16);
6461 tmp |= (0x1C << 16);
6462 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6463
6464 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6465 tmp &= ~(0xFF << 16);
6466 tmp |= (0x1C << 16);
6467 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6468
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006469 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6470 tmp |= (1 << 27);
6471 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006472
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006473 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6474 tmp |= (1 << 27);
6475 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006476
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006477 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6478 tmp &= ~(0xF << 28);
6479 tmp |= (4 << 28);
6480 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006481
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006482 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6483 tmp &= ~(0xF << 28);
6484 tmp |= (4 << 28);
6485 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006486}
6487
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006488/* Implements 3 different sequences from BSpec chapter "Display iCLK
6489 * Programming" based on the parameters passed:
6490 * - Sequence to enable CLKOUT_DP
6491 * - Sequence to enable CLKOUT_DP without spread
6492 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6493 */
6494static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6495 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006496{
6497 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006498 uint32_t reg, tmp;
6499
6500 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6501 with_spread = true;
6502 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6503 with_fdi, "LP PCH doesn't have FDI\n"))
6504 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006505
6506 mutex_lock(&dev_priv->dpio_lock);
6507
6508 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6509 tmp &= ~SBI_SSCCTL_DISABLE;
6510 tmp |= SBI_SSCCTL_PATHALT;
6511 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6512
6513 udelay(24);
6514
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006515 if (with_spread) {
6516 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6517 tmp &= ~SBI_SSCCTL_PATHALT;
6518 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006519
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006520 if (with_fdi) {
6521 lpt_reset_fdi_mphy(dev_priv);
6522 lpt_program_fdi_mphy(dev_priv);
6523 }
6524 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02006525
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006526 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6527 SBI_GEN0 : SBI_DBUFF0;
6528 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6529 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6530 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01006531
6532 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006533}
6534
Paulo Zanoni47701c32013-07-23 11:19:25 -03006535/* Sequence to disable CLKOUT_DP */
6536static void lpt_disable_clkout_dp(struct drm_device *dev)
6537{
6538 struct drm_i915_private *dev_priv = dev->dev_private;
6539 uint32_t reg, tmp;
6540
6541 mutex_lock(&dev_priv->dpio_lock);
6542
6543 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6544 SBI_GEN0 : SBI_DBUFF0;
6545 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6546 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6547 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6548
6549 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6550 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6551 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6552 tmp |= SBI_SSCCTL_PATHALT;
6553 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6554 udelay(32);
6555 }
6556 tmp |= SBI_SSCCTL_DISABLE;
6557 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6558 }
6559
6560 mutex_unlock(&dev_priv->dpio_lock);
6561}
6562
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006563static void lpt_init_pch_refclk(struct drm_device *dev)
6564{
6565 struct drm_mode_config *mode_config = &dev->mode_config;
6566 struct intel_encoder *encoder;
6567 bool has_vga = false;
6568
6569 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6570 switch (encoder->type) {
6571 case INTEL_OUTPUT_ANALOG:
6572 has_vga = true;
6573 break;
6574 }
6575 }
6576
Paulo Zanoni47701c32013-07-23 11:19:25 -03006577 if (has_vga)
6578 lpt_enable_clkout_dp(dev, true, true);
6579 else
6580 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006581}
6582
Paulo Zanonidde86e22012-12-01 12:04:25 -02006583/*
6584 * Initialize reference clocks when the driver loads
6585 */
6586void intel_init_pch_refclk(struct drm_device *dev)
6587{
6588 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6589 ironlake_init_pch_refclk(dev);
6590 else if (HAS_PCH_LPT(dev))
6591 lpt_init_pch_refclk(dev);
6592}
6593
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006594static int ironlake_get_refclk(struct drm_crtc *crtc)
6595{
6596 struct drm_device *dev = crtc->dev;
6597 struct drm_i915_private *dev_priv = dev->dev_private;
6598 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006599 int num_connectors = 0;
6600 bool is_lvds = false;
6601
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02006602 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006603 switch (encoder->type) {
6604 case INTEL_OUTPUT_LVDS:
6605 is_lvds = true;
6606 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006607 }
6608 num_connectors++;
6609 }
6610
6611 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006612 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006613 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006614 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006615 }
6616
6617 return 120000;
6618}
6619
Daniel Vetter6ff93602013-04-19 11:24:36 +02006620static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03006621{
6622 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6624 int pipe = intel_crtc->pipe;
6625 uint32_t val;
6626
Daniel Vetter78114072013-06-13 00:54:57 +02006627 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03006628
Daniel Vetter965e0c42013-03-27 00:44:57 +01006629 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03006630 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006631 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006632 break;
6633 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006634 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006635 break;
6636 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006637 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006638 break;
6639 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006640 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006641 break;
6642 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03006643 /* Case prevented by intel_choose_pipe_bpp_dither. */
6644 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03006645 }
6646
Daniel Vetterd8b32242013-04-25 17:54:44 +02006647 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03006648 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6649
Daniel Vetter6ff93602013-04-19 11:24:36 +02006650 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03006651 val |= PIPECONF_INTERLACED_ILK;
6652 else
6653 val |= PIPECONF_PROGRESSIVE;
6654
Daniel Vetter50f3b012013-03-27 00:44:56 +01006655 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006656 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006657
Paulo Zanonic8203562012-09-12 10:06:29 -03006658 I915_WRITE(PIPECONF(pipe), val);
6659 POSTING_READ(PIPECONF(pipe));
6660}
6661
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006662/*
6663 * Set up the pipe CSC unit.
6664 *
6665 * Currently only full range RGB to limited range RGB conversion
6666 * is supported, but eventually this should handle various
6667 * RGB<->YCbCr scenarios as well.
6668 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01006669static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006670{
6671 struct drm_device *dev = crtc->dev;
6672 struct drm_i915_private *dev_priv = dev->dev_private;
6673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6674 int pipe = intel_crtc->pipe;
6675 uint16_t coeff = 0x7800; /* 1.0 */
6676
6677 /*
6678 * TODO: Check what kind of values actually come out of the pipe
6679 * with these coeff/postoff values and adjust to get the best
6680 * accuracy. Perhaps we even need to take the bpc value into
6681 * consideration.
6682 */
6683
Daniel Vetter50f3b012013-03-27 00:44:56 +01006684 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006685 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6686
6687 /*
6688 * GY/GU and RY/RU should be the other way around according
6689 * to BSpec, but reality doesn't agree. Just set them up in
6690 * a way that results in the correct picture.
6691 */
6692 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6693 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6694
6695 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6696 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6697
6698 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6699 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6700
6701 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6702 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6703 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6704
6705 if (INTEL_INFO(dev)->gen > 6) {
6706 uint16_t postoff = 0;
6707
Daniel Vetter50f3b012013-03-27 00:44:56 +01006708 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02006709 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006710
6711 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6712 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6713 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6714
6715 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6716 } else {
6717 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6718
Daniel Vetter50f3b012013-03-27 00:44:56 +01006719 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006720 mode |= CSC_BLACK_SCREEN_OFFSET;
6721
6722 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6723 }
6724}
6725
Daniel Vetter6ff93602013-04-19 11:24:36 +02006726static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006727{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006728 struct drm_device *dev = crtc->dev;
6729 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006731 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006732 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006733 uint32_t val;
6734
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006735 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006736
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006737 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006738 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6739
Daniel Vetter6ff93602013-04-19 11:24:36 +02006740 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006741 val |= PIPECONF_INTERLACED_ILK;
6742 else
6743 val |= PIPECONF_PROGRESSIVE;
6744
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006745 I915_WRITE(PIPECONF(cpu_transcoder), val);
6746 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006747
6748 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6749 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006750
6751 if (IS_BROADWELL(dev)) {
6752 val = 0;
6753
6754 switch (intel_crtc->config.pipe_bpp) {
6755 case 18:
6756 val |= PIPEMISC_DITHER_6_BPC;
6757 break;
6758 case 24:
6759 val |= PIPEMISC_DITHER_8_BPC;
6760 break;
6761 case 30:
6762 val |= PIPEMISC_DITHER_10_BPC;
6763 break;
6764 case 36:
6765 val |= PIPEMISC_DITHER_12_BPC;
6766 break;
6767 default:
6768 /* Case prevented by pipe_config_set_bpp. */
6769 BUG();
6770 }
6771
6772 if (intel_crtc->config.dither)
6773 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6774
6775 I915_WRITE(PIPEMISC(pipe), val);
6776 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006777}
6778
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006779static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006780 intel_clock_t *clock,
6781 bool *has_reduced_clock,
6782 intel_clock_t *reduced_clock)
6783{
6784 struct drm_device *dev = crtc->dev;
6785 struct drm_i915_private *dev_priv = dev->dev_private;
6786 struct intel_encoder *intel_encoder;
6787 int refclk;
6788 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02006789 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006790
6791 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6792 switch (intel_encoder->type) {
6793 case INTEL_OUTPUT_LVDS:
6794 is_lvds = true;
6795 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006796 }
6797 }
6798
6799 refclk = ironlake_get_refclk(crtc);
6800
6801 /*
6802 * Returns a set of divisors for the desired target clock with the given
6803 * refclk, or FALSE. The returned values represent the clock equation:
6804 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6805 */
6806 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006807 ret = dev_priv->display.find_dpll(limit, crtc,
6808 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006809 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006810 if (!ret)
6811 return false;
6812
6813 if (is_lvds && dev_priv->lvds_downclock_avail) {
6814 /*
6815 * Ensure we match the reduced clock's P to the target clock.
6816 * If the clocks don't match, we can't switch the display clock
6817 * by using the FP0/FP1. In such case we will disable the LVDS
6818 * downclock feature.
6819 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006820 *has_reduced_clock =
6821 dev_priv->display.find_dpll(limit, crtc,
6822 dev_priv->lvds_downclock,
6823 refclk, clock,
6824 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006825 }
6826
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006827 return true;
6828}
6829
Paulo Zanonid4b19312012-11-29 11:29:32 -02006830int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6831{
6832 /*
6833 * Account for spread spectrum to avoid
6834 * oversubscribing the link. Max center spread
6835 * is 2.5%; use 5% for safety's sake.
6836 */
6837 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02006838 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02006839}
6840
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006841static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02006842{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006843 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006844}
6845
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006846static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006847 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006848 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006849{
6850 struct drm_crtc *crtc = &intel_crtc->base;
6851 struct drm_device *dev = crtc->dev;
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853 struct intel_encoder *intel_encoder;
6854 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006855 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02006856 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006857
6858 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6859 switch (intel_encoder->type) {
6860 case INTEL_OUTPUT_LVDS:
6861 is_lvds = true;
6862 break;
6863 case INTEL_OUTPUT_SDVO:
6864 case INTEL_OUTPUT_HDMI:
6865 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006866 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006867 }
6868
6869 num_connectors++;
6870 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006871
Chris Wilsonc1858122010-12-03 21:35:48 +00006872 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07006873 factor = 21;
6874 if (is_lvds) {
6875 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006876 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02006877 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07006878 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02006879 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07006880 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00006881
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006882 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02006883 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00006884
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006885 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6886 *fp2 |= FP_CB_TUNE;
6887
Chris Wilson5eddb702010-09-11 13:48:45 +01006888 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08006889
Eric Anholta07d6782011-03-30 13:01:08 -07006890 if (is_lvds)
6891 dpll |= DPLLB_MODE_LVDS;
6892 else
6893 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006894
Daniel Vetteref1b4602013-06-01 17:17:04 +02006895 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6896 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006897
6898 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006899 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02006900 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006901 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08006902
Eric Anholta07d6782011-03-30 13:01:08 -07006903 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006904 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006905 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006906 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006907
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006908 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07006909 case 5:
6910 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6911 break;
6912 case 7:
6913 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6914 break;
6915 case 10:
6916 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6917 break;
6918 case 14:
6919 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6920 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006921 }
6922
Daniel Vetterb4c09f32013-04-30 14:01:42 +02006923 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006924 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08006925 else
6926 dpll |= PLL_REF_INPUT_DREFCLK;
6927
Daniel Vetter959e16d2013-06-05 13:34:21 +02006928 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006929}
6930
Jesse Barnes79e53942008-11-07 14:24:08 -08006931static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08006932 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006933 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006934{
6935 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08006936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006937 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006938 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006939 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03006940 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01006941 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006942 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02006943 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08006944
6945 for_each_encoder_on_crtc(dev, crtc, encoder) {
6946 switch (encoder->type) {
6947 case INTEL_OUTPUT_LVDS:
6948 is_lvds = true;
6949 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006950 }
6951
6952 num_connectors++;
6953 }
6954
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006955 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6956 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6957
Daniel Vetterff9a6752013-06-01 17:16:21 +02006958 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006959 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02006960 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006961 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6962 return -EINVAL;
6963 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01006964 /* Compat-code for transition, will disappear. */
6965 if (!intel_crtc->config.clock_set) {
6966 intel_crtc->config.dpll.n = clock.n;
6967 intel_crtc->config.dpll.m1 = clock.m1;
6968 intel_crtc->config.dpll.m2 = clock.m2;
6969 intel_crtc->config.dpll.p1 = clock.p1;
6970 intel_crtc->config.dpll.p2 = clock.p2;
6971 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006972
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006973 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01006974 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006975 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006976 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006977 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006978
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006979 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006980 &fp, &reduced_clock,
6981 has_reduced_clock ? &fp2 : NULL);
6982
Daniel Vetter959e16d2013-06-05 13:34:21 +02006983 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02006984 intel_crtc->config.dpll_hw_state.fp0 = fp;
6985 if (has_reduced_clock)
6986 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6987 else
6988 intel_crtc->config.dpll_hw_state.fp1 = fp;
6989
Daniel Vetterb89a1d32013-06-05 13:34:24 +02006990 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006991 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03006992 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Daniel Vetter29407aa2014-04-24 23:55:08 +02006993 pipe_name(intel_crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07006994 return -EINVAL;
6995 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006996 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02006997 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006998
Jani Nikulad330a952014-01-21 11:24:25 +02006999 if (is_lvds && has_reduced_clock && i915.powersave)
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007000 intel_crtc->lowfreq_avail = true;
7001 else
7002 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007003
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007004 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007005}
7006
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007007static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7008 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007009{
7010 struct drm_device *dev = crtc->base.dev;
7011 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007012 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007013
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007014 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7015 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7016 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7017 & ~TU_SIZE_MASK;
7018 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7019 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7020 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7021}
7022
7023static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7024 enum transcoder transcoder,
7025 struct intel_link_m_n *m_n)
7026{
7027 struct drm_device *dev = crtc->base.dev;
7028 struct drm_i915_private *dev_priv = dev->dev_private;
7029 enum pipe pipe = crtc->pipe;
7030
7031 if (INTEL_INFO(dev)->gen >= 5) {
7032 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7033 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7034 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7035 & ~TU_SIZE_MASK;
7036 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7037 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7038 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7039 } else {
7040 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7041 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7042 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7043 & ~TU_SIZE_MASK;
7044 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7045 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7046 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7047 }
7048}
7049
7050void intel_dp_get_m_n(struct intel_crtc *crtc,
7051 struct intel_crtc_config *pipe_config)
7052{
7053 if (crtc->config.has_pch_encoder)
7054 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7055 else
7056 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7057 &pipe_config->dp_m_n);
7058}
7059
Daniel Vetter72419202013-04-04 13:28:53 +02007060static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7061 struct intel_crtc_config *pipe_config)
7062{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007063 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7064 &pipe_config->fdi_m_n);
Daniel Vetter72419202013-04-04 13:28:53 +02007065}
7066
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007067static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7068 struct intel_crtc_config *pipe_config)
7069{
7070 struct drm_device *dev = crtc->base.dev;
7071 struct drm_i915_private *dev_priv = dev->dev_private;
7072 uint32_t tmp;
7073
7074 tmp = I915_READ(PF_CTL(crtc->pipe));
7075
7076 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007077 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007078 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7079 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007080
7081 /* We currently do not free assignements of panel fitters on
7082 * ivb/hsw (since we don't use the higher upscaling modes which
7083 * differentiates them) so just WARN about this case for now. */
7084 if (IS_GEN7(dev)) {
7085 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7086 PF_PIPE_SEL_IVB(crtc->pipe));
7087 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007088 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007089}
7090
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007091static void ironlake_get_plane_config(struct intel_crtc *crtc,
7092 struct intel_plane_config *plane_config)
7093{
7094 struct drm_device *dev = crtc->base.dev;
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096 u32 val, base, offset;
7097 int pipe = crtc->pipe, plane = crtc->plane;
7098 int fourcc, pixel_format;
7099 int aligned_height;
7100
Dave Airlie66e514c2014-04-03 07:51:54 +10007101 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7102 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007103 DRM_DEBUG_KMS("failed to alloc fb\n");
7104 return;
7105 }
7106
7107 val = I915_READ(DSPCNTR(plane));
7108
7109 if (INTEL_INFO(dev)->gen >= 4)
7110 if (val & DISPPLANE_TILED)
7111 plane_config->tiled = true;
7112
7113 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7114 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007115 crtc->base.primary->fb->pixel_format = fourcc;
7116 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007117 drm_format_plane_cpp(fourcc, 0) * 8;
7118
7119 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7120 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7121 offset = I915_READ(DSPOFFSET(plane));
7122 } else {
7123 if (plane_config->tiled)
7124 offset = I915_READ(DSPTILEOFF(plane));
7125 else
7126 offset = I915_READ(DSPLINOFF(plane));
7127 }
7128 plane_config->base = base;
7129
7130 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007131 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7132 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007133
7134 val = I915_READ(DSPSTRIDE(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007135 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007136
Dave Airlie66e514c2014-04-03 07:51:54 +10007137 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007138 plane_config->tiled);
7139
Dave Airlie66e514c2014-04-03 07:51:54 +10007140 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007141 aligned_height, PAGE_SIZE);
7142
7143 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007144 pipe, plane, crtc->base.primary->fb->width,
7145 crtc->base.primary->fb->height,
7146 crtc->base.primary->fb->bits_per_pixel, base,
7147 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007148 plane_config->size);
7149}
7150
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007151static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7152 struct intel_crtc_config *pipe_config)
7153{
7154 struct drm_device *dev = crtc->base.dev;
7155 struct drm_i915_private *dev_priv = dev->dev_private;
7156 uint32_t tmp;
7157
Daniel Vettere143a212013-07-04 12:01:15 +02007158 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007159 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007160
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007161 tmp = I915_READ(PIPECONF(crtc->pipe));
7162 if (!(tmp & PIPECONF_ENABLE))
7163 return false;
7164
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007165 switch (tmp & PIPECONF_BPC_MASK) {
7166 case PIPECONF_6BPC:
7167 pipe_config->pipe_bpp = 18;
7168 break;
7169 case PIPECONF_8BPC:
7170 pipe_config->pipe_bpp = 24;
7171 break;
7172 case PIPECONF_10BPC:
7173 pipe_config->pipe_bpp = 30;
7174 break;
7175 case PIPECONF_12BPC:
7176 pipe_config->pipe_bpp = 36;
7177 break;
7178 default:
7179 break;
7180 }
7181
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007182 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7183 pipe_config->limited_color_range = true;
7184
Daniel Vetterab9412b2013-05-03 11:49:46 +02007185 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007186 struct intel_shared_dpll *pll;
7187
Daniel Vetter88adfff2013-03-28 10:42:01 +01007188 pipe_config->has_pch_encoder = true;
7189
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007190 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7191 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7192 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007193
7194 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007195
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007196 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007197 pipe_config->shared_dpll =
7198 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007199 } else {
7200 tmp = I915_READ(PCH_DPLL_SEL);
7201 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7202 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7203 else
7204 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7205 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007206
7207 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7208
7209 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7210 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007211
7212 tmp = pipe_config->dpll_hw_state.dpll;
7213 pipe_config->pixel_multiplier =
7214 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7215 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007216
7217 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007218 } else {
7219 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007220 }
7221
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007222 intel_get_pipe_timings(crtc, pipe_config);
7223
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007224 ironlake_get_pfit_config(crtc, pipe_config);
7225
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007226 return true;
7227}
7228
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007229static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7230{
7231 struct drm_device *dev = dev_priv->dev;
7232 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7233 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007234
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007235 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007236 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007237 pipe_name(crtc->pipe));
7238
7239 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7240 WARN(plls->spll_refcount, "SPLL enabled\n");
7241 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7242 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7243 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7244 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7245 "CPU PWM1 enabled\n");
7246 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7247 "CPU PWM2 enabled\n");
7248 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7249 "PCH PWM1 enabled\n");
7250 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7251 "Utility pin enabled\n");
7252 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7253
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007254 /*
7255 * In theory we can still leave IRQs enabled, as long as only the HPD
7256 * interrupts remain enabled. We used to check for that, but since it's
7257 * gen-specific and since we only disable LCPLL after we fully disable
7258 * the interrupts, the check below should be enough.
7259 */
7260 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007261}
7262
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007263static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7264{
7265 struct drm_device *dev = dev_priv->dev;
7266
7267 if (IS_HASWELL(dev)) {
7268 mutex_lock(&dev_priv->rps.hw_lock);
7269 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7270 val))
7271 DRM_ERROR("Failed to disable D_COMP\n");
7272 mutex_unlock(&dev_priv->rps.hw_lock);
7273 } else {
7274 I915_WRITE(D_COMP, val);
7275 }
7276 POSTING_READ(D_COMP);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007277}
7278
7279/*
7280 * This function implements pieces of two sequences from BSpec:
7281 * - Sequence for display software to disable LCPLL
7282 * - Sequence for display software to allow package C8+
7283 * The steps implemented here are just the steps that actually touch the LCPLL
7284 * register. Callers should take care of disabling all the display engine
7285 * functions, doing the mode unset, fixing interrupts, etc.
7286 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007287static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7288 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007289{
7290 uint32_t val;
7291
7292 assert_can_disable_lcpll(dev_priv);
7293
7294 val = I915_READ(LCPLL_CTL);
7295
7296 if (switch_to_fclk) {
7297 val |= LCPLL_CD_SOURCE_FCLK;
7298 I915_WRITE(LCPLL_CTL, val);
7299
7300 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7301 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7302 DRM_ERROR("Switching to FCLK failed\n");
7303
7304 val = I915_READ(LCPLL_CTL);
7305 }
7306
7307 val |= LCPLL_PLL_DISABLE;
7308 I915_WRITE(LCPLL_CTL, val);
7309 POSTING_READ(LCPLL_CTL);
7310
7311 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7312 DRM_ERROR("LCPLL still locked\n");
7313
7314 val = I915_READ(D_COMP);
7315 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007316 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007317 ndelay(100);
7318
7319 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7320 DRM_ERROR("D_COMP RCOMP still in progress\n");
7321
7322 if (allow_power_down) {
7323 val = I915_READ(LCPLL_CTL);
7324 val |= LCPLL_POWER_DOWN_ALLOW;
7325 I915_WRITE(LCPLL_CTL, val);
7326 POSTING_READ(LCPLL_CTL);
7327 }
7328}
7329
7330/*
7331 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7332 * source.
7333 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007334static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007335{
7336 uint32_t val;
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007337 unsigned long irqflags;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007338
7339 val = I915_READ(LCPLL_CTL);
7340
7341 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7342 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7343 return;
7344
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007345 /*
7346 * Make sure we're not on PC8 state before disabling PC8, otherwise
7347 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7348 *
7349 * The other problem is that hsw_restore_lcpll() is called as part of
7350 * the runtime PM resume sequence, so we can't just call
7351 * gen6_gt_force_wake_get() because that function calls
7352 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7353 * while we are on the resume sequence. So to solve this problem we have
7354 * to call special forcewake code that doesn't touch runtime PM and
7355 * doesn't enable the forcewake delayed work.
7356 */
7357 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7358 if (dev_priv->uncore.forcewake_count++ == 0)
7359 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7360 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007361
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007362 if (val & LCPLL_POWER_DOWN_ALLOW) {
7363 val &= ~LCPLL_POWER_DOWN_ALLOW;
7364 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007365 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007366 }
7367
7368 val = I915_READ(D_COMP);
7369 val |= D_COMP_COMP_FORCE;
7370 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007371 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007372
7373 val = I915_READ(LCPLL_CTL);
7374 val &= ~LCPLL_PLL_DISABLE;
7375 I915_WRITE(LCPLL_CTL, val);
7376
7377 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7378 DRM_ERROR("LCPLL not locked yet\n");
7379
7380 if (val & LCPLL_CD_SOURCE_FCLK) {
7381 val = I915_READ(LCPLL_CTL);
7382 val &= ~LCPLL_CD_SOURCE_FCLK;
7383 I915_WRITE(LCPLL_CTL, val);
7384
7385 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7386 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7387 DRM_ERROR("Switching back to LCPLL failed\n");
7388 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007389
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007390 /* See the big comment above. */
7391 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7392 if (--dev_priv->uncore.forcewake_count == 0)
7393 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7394 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007395}
7396
Paulo Zanoni765dab62014-03-07 20:08:18 -03007397/*
7398 * Package states C8 and deeper are really deep PC states that can only be
7399 * reached when all the devices on the system allow it, so even if the graphics
7400 * device allows PC8+, it doesn't mean the system will actually get to these
7401 * states. Our driver only allows PC8+ when going into runtime PM.
7402 *
7403 * The requirements for PC8+ are that all the outputs are disabled, the power
7404 * well is disabled and most interrupts are disabled, and these are also
7405 * requirements for runtime PM. When these conditions are met, we manually do
7406 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7407 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7408 * hang the machine.
7409 *
7410 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7411 * the state of some registers, so when we come back from PC8+ we need to
7412 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7413 * need to take care of the registers kept by RC6. Notice that this happens even
7414 * if we don't put the device in PCI D3 state (which is what currently happens
7415 * because of the runtime PM support).
7416 *
7417 * For more, read "Display Sequences for Package C8" on the hardware
7418 * documentation.
7419 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007420void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007421{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007422 struct drm_device *dev = dev_priv->dev;
7423 uint32_t val;
7424
Paulo Zanonic67a4702013-08-19 13:18:09 -03007425 DRM_DEBUG_KMS("Enabling package C8+\n");
7426
Paulo Zanonic67a4702013-08-19 13:18:09 -03007427 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7428 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7429 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7430 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7431 }
7432
7433 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007434 hsw_disable_lcpll(dev_priv, true, true);
7435}
7436
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007437void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007438{
7439 struct drm_device *dev = dev_priv->dev;
7440 uint32_t val;
7441
Paulo Zanonic67a4702013-08-19 13:18:09 -03007442 DRM_DEBUG_KMS("Disabling package C8+\n");
7443
7444 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007445 lpt_init_pch_refclk(dev);
7446
7447 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7448 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7449 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7450 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7451 }
7452
7453 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007454}
7455
Paulo Zanoni9a952a02014-03-07 20:12:34 -03007456static void snb_modeset_global_resources(struct drm_device *dev)
7457{
7458 modeset_update_crtc_power_domains(dev);
7459}
7460
Imre Deak4f074122013-10-16 17:25:51 +03007461static void haswell_modeset_global_resources(struct drm_device *dev)
7462{
Paulo Zanonida723562013-12-19 11:54:51 -02007463 modeset_update_crtc_power_domains(dev);
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02007464}
7465
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007466static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007467 int x, int y,
7468 struct drm_framebuffer *fb)
7469{
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007471
Paulo Zanoni566b7342013-11-25 15:27:08 -02007472 if (!intel_ddi_pll_select(intel_crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007473 return -EINVAL;
Paulo Zanoni566b7342013-11-25 15:27:08 -02007474 intel_ddi_pll_enable(intel_crtc);
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007475
Daniel Vetter644cef32014-04-24 23:55:07 +02007476 intel_crtc->lowfreq_avail = false;
7477
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007478 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007479}
7480
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007481static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7482 struct intel_crtc_config *pipe_config)
7483{
7484 struct drm_device *dev = crtc->base.dev;
7485 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007486 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007487 uint32_t tmp;
7488
Imre Deakb5482bd2014-03-05 16:20:55 +02007489 if (!intel_display_power_enabled(dev_priv,
7490 POWER_DOMAIN_PIPE(crtc->pipe)))
7491 return false;
7492
Daniel Vettere143a212013-07-04 12:01:15 +02007493 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007494 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7495
Daniel Vettereccb1402013-05-22 00:50:22 +02007496 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7497 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7498 enum pipe trans_edp_pipe;
7499 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7500 default:
7501 WARN(1, "unknown pipe linked to edp transcoder\n");
7502 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7503 case TRANS_DDI_EDP_INPUT_A_ON:
7504 trans_edp_pipe = PIPE_A;
7505 break;
7506 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7507 trans_edp_pipe = PIPE_B;
7508 break;
7509 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7510 trans_edp_pipe = PIPE_C;
7511 break;
7512 }
7513
7514 if (trans_edp_pipe == crtc->pipe)
7515 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7516 }
7517
Imre Deakda7e29b2014-02-18 00:02:02 +02007518 if (!intel_display_power_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02007519 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03007520 return false;
7521
Daniel Vettereccb1402013-05-22 00:50:22 +02007522 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007523 if (!(tmp & PIPECONF_ENABLE))
7524 return false;
7525
Daniel Vetter88adfff2013-03-28 10:42:01 +01007526 /*
Paulo Zanonif196e6b2013-04-18 16:35:41 -03007527 * Haswell has only FDI/PCH transcoder A. It is which is connected to
Daniel Vetter88adfff2013-03-28 10:42:01 +01007528 * DDI E. So just check whether this pipe is wired to DDI E and whether
7529 * the PCH transcoder is on.
7530 */
Daniel Vettereccb1402013-05-22 00:50:22 +02007531 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
Daniel Vetter88adfff2013-03-28 10:42:01 +01007532 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
Daniel Vetterab9412b2013-05-03 11:49:46 +02007533 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter88adfff2013-03-28 10:42:01 +01007534 pipe_config->has_pch_encoder = true;
7535
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007536 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7537 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7538 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007539
7540 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007541 }
7542
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007543 intel_get_pipe_timings(crtc, pipe_config);
7544
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007545 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Imre Deakda7e29b2014-02-18 00:02:02 +02007546 if (intel_display_power_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007547 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01007548
Jesse Barnese59150d2014-01-07 13:30:45 -08007549 if (IS_HASWELL(dev))
7550 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7551 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007552
Daniel Vetter6c49f242013-06-06 12:45:25 +02007553 pipe_config->pixel_multiplier = 1;
7554
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007555 return true;
7556}
7557
Jani Nikula1a915102013-10-16 12:34:48 +03007558static struct {
7559 int clock;
7560 u32 config;
7561} hdmi_audio_clock[] = {
7562 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7563 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7564 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7565 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7566 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7567 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7568 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7569 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7570 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7571 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7572};
7573
7574/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7575static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7576{
7577 int i;
7578
7579 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7580 if (mode->clock == hdmi_audio_clock[i].clock)
7581 break;
7582 }
7583
7584 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7585 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7586 i = 1;
7587 }
7588
7589 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7590 hdmi_audio_clock[i].clock,
7591 hdmi_audio_clock[i].config);
7592
7593 return hdmi_audio_clock[i].config;
7594}
7595
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007596static bool intel_eld_uptodate(struct drm_connector *connector,
7597 int reg_eldv, uint32_t bits_eldv,
7598 int reg_elda, uint32_t bits_elda,
7599 int reg_edid)
7600{
7601 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7602 uint8_t *eld = connector->eld;
7603 uint32_t i;
7604
7605 i = I915_READ(reg_eldv);
7606 i &= bits_eldv;
7607
7608 if (!eld[0])
7609 return !i;
7610
7611 if (!i)
7612 return false;
7613
7614 i = I915_READ(reg_elda);
7615 i &= ~bits_elda;
7616 I915_WRITE(reg_elda, i);
7617
7618 for (i = 0; i < eld[2]; i++)
7619 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7620 return false;
7621
7622 return true;
7623}
7624
Wu Fengguange0dac652011-09-05 14:25:34 +08007625static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007626 struct drm_crtc *crtc,
7627 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007628{
7629 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7630 uint8_t *eld = connector->eld;
7631 uint32_t eldv;
7632 uint32_t len;
7633 uint32_t i;
7634
7635 i = I915_READ(G4X_AUD_VID_DID);
7636
7637 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7638 eldv = G4X_ELDV_DEVCL_DEVBLC;
7639 else
7640 eldv = G4X_ELDV_DEVCTG;
7641
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007642 if (intel_eld_uptodate(connector,
7643 G4X_AUD_CNTL_ST, eldv,
7644 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7645 G4X_HDMIW_HDMIEDID))
7646 return;
7647
Wu Fengguange0dac652011-09-05 14:25:34 +08007648 i = I915_READ(G4X_AUD_CNTL_ST);
7649 i &= ~(eldv | G4X_ELD_ADDR);
7650 len = (i >> 9) & 0x1f; /* ELD buffer size */
7651 I915_WRITE(G4X_AUD_CNTL_ST, i);
7652
7653 if (!eld[0])
7654 return;
7655
7656 len = min_t(uint8_t, eld[2], len);
7657 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7658 for (i = 0; i < len; i++)
7659 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7660
7661 i = I915_READ(G4X_AUD_CNTL_ST);
7662 i |= eldv;
7663 I915_WRITE(G4X_AUD_CNTL_ST, i);
7664}
7665
Wang Xingchao83358c852012-08-16 22:43:37 +08007666static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007667 struct drm_crtc *crtc,
7668 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007669{
7670 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7671 uint8_t *eld = connector->eld;
Wang Xingchao83358c852012-08-16 22:43:37 +08007672 uint32_t eldv;
7673 uint32_t i;
7674 int len;
7675 int pipe = to_intel_crtc(crtc)->pipe;
7676 int tmp;
7677
7678 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7679 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7680 int aud_config = HSW_AUD_CFG(pipe);
7681 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7682
Wang Xingchao83358c852012-08-16 22:43:37 +08007683 /* Audio output enable */
7684 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7685 tmp = I915_READ(aud_cntrl_st2);
7686 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7687 I915_WRITE(aud_cntrl_st2, tmp);
Daniel Vetterc7905792014-04-16 16:56:09 +02007688 POSTING_READ(aud_cntrl_st2);
Wang Xingchao83358c852012-08-16 22:43:37 +08007689
Daniel Vetterc7905792014-04-16 16:56:09 +02007690 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Wang Xingchao83358c852012-08-16 22:43:37 +08007691
7692 /* Set ELD valid state */
7693 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007694 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007695 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7696 I915_WRITE(aud_cntrl_st2, tmp);
7697 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007698 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007699
7700 /* Enable HDMI mode */
7701 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007702 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007703 /* clear N_programing_enable and N_value_index */
7704 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7705 I915_WRITE(aud_config, tmp);
7706
7707 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7708
7709 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7710
7711 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7712 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7713 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7714 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007715 } else {
7716 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7717 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007718
7719 if (intel_eld_uptodate(connector,
7720 aud_cntrl_st2, eldv,
7721 aud_cntl_st, IBX_ELD_ADDRESS,
7722 hdmiw_hdmiedid))
7723 return;
7724
7725 i = I915_READ(aud_cntrl_st2);
7726 i &= ~eldv;
7727 I915_WRITE(aud_cntrl_st2, i);
7728
7729 if (!eld[0])
7730 return;
7731
7732 i = I915_READ(aud_cntl_st);
7733 i &= ~IBX_ELD_ADDRESS;
7734 I915_WRITE(aud_cntl_st, i);
7735 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7736 DRM_DEBUG_DRIVER("port num:%d\n", i);
7737
7738 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7739 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7740 for (i = 0; i < len; i++)
7741 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7742
7743 i = I915_READ(aud_cntrl_st2);
7744 i |= eldv;
7745 I915_WRITE(aud_cntrl_st2, i);
7746
7747}
7748
Wu Fengguange0dac652011-09-05 14:25:34 +08007749static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007750 struct drm_crtc *crtc,
7751 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007752{
7753 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7754 uint8_t *eld = connector->eld;
7755 uint32_t eldv;
7756 uint32_t i;
7757 int len;
7758 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007759 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007760 int aud_cntl_st;
7761 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007762 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007763
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007764 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007765 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7766 aud_config = IBX_AUD_CFG(pipe);
7767 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007768 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007769 } else if (IS_VALLEYVIEW(connector->dev)) {
7770 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7771 aud_config = VLV_AUD_CFG(pipe);
7772 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7773 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007774 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007775 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7776 aud_config = CPT_AUD_CFG(pipe);
7777 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007778 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007779 }
7780
Wang Xingchao9b138a82012-08-09 16:52:18 +08007781 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08007782
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007783 if (IS_VALLEYVIEW(connector->dev)) {
7784 struct intel_encoder *intel_encoder;
7785 struct intel_digital_port *intel_dig_port;
7786
7787 intel_encoder = intel_attached_encoder(connector);
7788 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7789 i = intel_dig_port->port;
7790 } else {
7791 i = I915_READ(aud_cntl_st);
7792 i = (i >> 29) & DIP_PORT_SEL_MASK;
7793 /* DIP_Port_Select, 0x1 = PortB */
7794 }
7795
Wu Fengguange0dac652011-09-05 14:25:34 +08007796 if (!i) {
7797 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7798 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007799 eldv = IBX_ELD_VALIDB;
7800 eldv |= IBX_ELD_VALIDB << 4;
7801 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08007802 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03007803 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007804 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08007805 }
7806
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007807 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7808 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7809 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06007810 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007811 } else {
7812 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7813 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007814
7815 if (intel_eld_uptodate(connector,
7816 aud_cntrl_st2, eldv,
7817 aud_cntl_st, IBX_ELD_ADDRESS,
7818 hdmiw_hdmiedid))
7819 return;
7820
Wu Fengguange0dac652011-09-05 14:25:34 +08007821 i = I915_READ(aud_cntrl_st2);
7822 i &= ~eldv;
7823 I915_WRITE(aud_cntrl_st2, i);
7824
7825 if (!eld[0])
7826 return;
7827
Wu Fengguange0dac652011-09-05 14:25:34 +08007828 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007829 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08007830 I915_WRITE(aud_cntl_st, i);
7831
7832 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7833 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7834 for (i = 0; i < len; i++)
7835 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7836
7837 i = I915_READ(aud_cntrl_st2);
7838 i |= eldv;
7839 I915_WRITE(aud_cntrl_st2, i);
7840}
7841
7842void intel_write_eld(struct drm_encoder *encoder,
7843 struct drm_display_mode *mode)
7844{
7845 struct drm_crtc *crtc = encoder->crtc;
7846 struct drm_connector *connector;
7847 struct drm_device *dev = encoder->dev;
7848 struct drm_i915_private *dev_priv = dev->dev_private;
7849
7850 connector = drm_select_eld(encoder, mode);
7851 if (!connector)
7852 return;
7853
7854 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7855 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03007856 connector->name,
Wu Fengguange0dac652011-09-05 14:25:34 +08007857 connector->encoder->base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +03007858 connector->encoder->name);
Wu Fengguange0dac652011-09-05 14:25:34 +08007859
7860 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7861
7862 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03007863 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08007864}
7865
Chris Wilson560b85b2010-08-07 11:01:38 +01007866static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7867{
7868 struct drm_device *dev = crtc->dev;
7869 struct drm_i915_private *dev_priv = dev->dev_private;
7870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7871 bool visible = base != 0;
7872 u32 cntl;
7873
7874 if (intel_crtc->cursor_visible == visible)
7875 return;
7876
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007877 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01007878 if (visible) {
7879 /* On these chipsets we can only modify the base whilst
7880 * the cursor is disabled.
7881 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007882 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01007883
7884 cntl &= ~(CURSOR_FORMAT_MASK);
7885 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7886 cntl |= CURSOR_ENABLE |
7887 CURSOR_GAMMA_ENABLE |
7888 CURSOR_FORMAT_ARGB;
7889 } else
7890 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007891 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01007892
7893 intel_crtc->cursor_visible = visible;
7894}
7895
7896static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7897{
7898 struct drm_device *dev = crtc->dev;
7899 struct drm_i915_private *dev_priv = dev->dev_private;
7900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7901 int pipe = intel_crtc->pipe;
7902 bool visible = base != 0;
7903
7904 if (intel_crtc->cursor_visible != visible) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307905 int16_t width = intel_crtc->cursor_width;
Jesse Barnes548f2452011-02-17 10:40:53 -08007906 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01007907 if (base) {
7908 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307909 cntl |= MCURSOR_GAMMA_ENABLE;
7910
7911 switch (width) {
7912 case 64:
7913 cntl |= CURSOR_MODE_64_ARGB_AX;
7914 break;
7915 case 128:
7916 cntl |= CURSOR_MODE_128_ARGB_AX;
7917 break;
7918 case 256:
7919 cntl |= CURSOR_MODE_256_ARGB_AX;
7920 break;
7921 default:
7922 WARN_ON(1);
7923 return;
7924 }
Chris Wilson560b85b2010-08-07 11:01:38 +01007925 cntl |= pipe << 28; /* Connect to correct pipe */
7926 } else {
7927 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7928 cntl |= CURSOR_MODE_DISABLE;
7929 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007930 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01007931
7932 intel_crtc->cursor_visible = visible;
7933 }
7934 /* and commit changes on next vblank */
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007935 POSTING_READ(CURCNTR(pipe));
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007936 I915_WRITE(CURBASE(pipe), base);
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007937 POSTING_READ(CURBASE(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01007938}
7939
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007940static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7941{
7942 struct drm_device *dev = crtc->dev;
7943 struct drm_i915_private *dev_priv = dev->dev_private;
7944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7945 int pipe = intel_crtc->pipe;
7946 bool visible = base != 0;
7947
7948 if (intel_crtc->cursor_visible != visible) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307949 int16_t width = intel_crtc->cursor_width;
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03007950 uint32_t cntl = I915_READ(CURCNTR(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007951 if (base) {
7952 cntl &= ~CURSOR_MODE;
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307953 cntl |= MCURSOR_GAMMA_ENABLE;
7954 switch (width) {
7955 case 64:
7956 cntl |= CURSOR_MODE_64_ARGB_AX;
7957 break;
7958 case 128:
7959 cntl |= CURSOR_MODE_128_ARGB_AX;
7960 break;
7961 case 256:
7962 cntl |= CURSOR_MODE_256_ARGB_AX;
7963 break;
7964 default:
7965 WARN_ON(1);
7966 return;
7967 }
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007968 } else {
7969 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7970 cntl |= CURSOR_MODE_DISABLE;
7971 }
Ville Syrjälä6bbfa1c2013-11-02 21:07:39 -07007972 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007973 cntl |= CURSOR_PIPE_CSC_ENABLE;
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03007974 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7975 }
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03007976 I915_WRITE(CURCNTR(pipe), cntl);
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007977
7978 intel_crtc->cursor_visible = visible;
7979 }
7980 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03007981 POSTING_READ(CURCNTR(pipe));
7982 I915_WRITE(CURBASE(pipe), base);
7983 POSTING_READ(CURBASE(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007984}
7985
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007986/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01007987static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7988 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007989{
7990 struct drm_device *dev = crtc->dev;
7991 struct drm_i915_private *dev_priv = dev->dev_private;
7992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7993 int pipe = intel_crtc->pipe;
7994 int x = intel_crtc->cursor_x;
7995 int y = intel_crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007996 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007997 bool visible;
7998
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007999 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008000 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008001
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008002 if (x >= intel_crtc->config.pipe_src_w)
8003 base = 0;
8004
8005 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008006 base = 0;
8007
8008 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008009 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008010 base = 0;
8011
8012 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8013 x = -x;
8014 }
8015 pos |= x << CURSOR_X_SHIFT;
8016
8017 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008018 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008019 base = 0;
8020
8021 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8022 y = -y;
8023 }
8024 pos |= y << CURSOR_Y_SHIFT;
8025
8026 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01008027 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008028 return;
8029
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008030 I915_WRITE(CURPOS(pipe), pos);
8031
8032 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008033 ivb_update_cursor(crtc, base);
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008034 else if (IS_845G(dev) || IS_I865G(dev))
8035 i845_update_cursor(crtc, base);
8036 else
8037 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008038}
8039
Jesse Barnes79e53942008-11-07 14:24:08 -08008040static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00008041 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08008042 uint32_t handle,
8043 uint32_t width, uint32_t height)
8044{
8045 struct drm_device *dev = crtc->dev;
8046 struct drm_i915_private *dev_priv = dev->dev_private;
8047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00008048 struct drm_i915_gem_object *obj;
Chris Wilson64f962e2014-03-26 12:38:15 +00008049 unsigned old_width;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008050 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008051 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008052
Jesse Barnes79e53942008-11-07 14:24:08 -08008053 /* if we want to turn off the cursor ignore width and height */
8054 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008055 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008056 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00008057 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008058 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008059 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008060 }
8061
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308062 /* Check for which cursor types we support */
8063 if (!((width == 64 && height == 64) ||
8064 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8065 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8066 DRM_DEBUG("Cursor dimension not supported\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08008067 return -EINVAL;
8068 }
8069
Chris Wilson05394f32010-11-08 19:18:58 +00008070 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00008071 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08008072 return -ENOENT;
8073
Chris Wilson05394f32010-11-08 19:18:58 +00008074 if (obj->base.size < width * height * 4) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008075 DRM_DEBUG_KMS("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10008076 ret = -ENOMEM;
8077 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008078 }
8079
Dave Airlie71acb5e2008-12-30 20:31:46 +10008080 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008081 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008082 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008083 unsigned alignment;
8084
Chris Wilsond9e86c02010-11-10 16:40:20 +00008085 if (obj->tiling_mode) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008086 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008087 ret = -EINVAL;
8088 goto fail_locked;
8089 }
8090
Chris Wilson693db182013-03-05 14:52:39 +00008091 /* Note that the w/a also requires 2 PTE of padding following
8092 * the bo. We currently fill all unused PTE with the shadow
8093 * page and so we should always have valid PTE following the
8094 * cursor preventing the VT-d warning.
8095 */
8096 alignment = 0;
8097 if (need_vtd_wa(dev))
8098 alignment = 64*1024;
8099
8100 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008101 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008102 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008103 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008104 }
8105
Chris Wilsond9e86c02010-11-10 16:40:20 +00008106 ret = i915_gem_object_put_fence(obj);
8107 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008108 DRM_DEBUG_KMS("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008109 goto fail_unpin;
8110 }
8111
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008112 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008113 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008114 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00008115 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008116 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8117 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008118 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008119 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008120 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008121 }
Chris Wilson05394f32010-11-08 19:18:58 +00008122 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008123 }
8124
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008125 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04008126 I915_WRITE(CURSIZE, (height << 12) | width);
8127
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008128 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008129 if (intel_crtc->cursor_bo) {
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008130 if (INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00008131 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10008132 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8133 } else
Chris Wilsoncc98b412013-08-09 12:25:09 +01008134 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00008135 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008136 }
Jesse Barnes80824002009-09-10 15:28:06 -07008137
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008138 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008139
Chris Wilson64f962e2014-03-26 12:38:15 +00008140 old_width = intel_crtc->cursor_width;
8141
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008142 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008143 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008144 intel_crtc->cursor_width = width;
8145 intel_crtc->cursor_height = height;
8146
Chris Wilson64f962e2014-03-26 12:38:15 +00008147 if (intel_crtc->active) {
8148 if (old_width != width)
8149 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008150 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Chris Wilson64f962e2014-03-26 12:38:15 +00008151 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008152
Jesse Barnes79e53942008-11-07 14:24:08 -08008153 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008154fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008155 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008156fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008157 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00008158fail:
Chris Wilson05394f32010-11-08 19:18:58 +00008159 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10008160 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008161}
8162
8163static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8164{
Jesse Barnes79e53942008-11-07 14:24:08 -08008165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008166
Ville Syrjälä92e76c82013-10-21 19:01:58 +03008167 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8168 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
Jesse Barnes652c3932009-08-17 13:31:43 -07008169
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008170 if (intel_crtc->active)
8171 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Jesse Barnes79e53942008-11-07 14:24:08 -08008172
8173 return 0;
8174}
8175
Jesse Barnes79e53942008-11-07 14:24:08 -08008176static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008177 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008178{
James Simmons72034252010-08-03 01:33:19 +01008179 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008181
James Simmons72034252010-08-03 01:33:19 +01008182 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008183 intel_crtc->lut_r[i] = red[i] >> 8;
8184 intel_crtc->lut_g[i] = green[i] >> 8;
8185 intel_crtc->lut_b[i] = blue[i] >> 8;
8186 }
8187
8188 intel_crtc_load_lut(crtc);
8189}
8190
Jesse Barnes79e53942008-11-07 14:24:08 -08008191/* VESA 640x480x72Hz mode to set on the pipe */
8192static struct drm_display_mode load_detect_mode = {
8193 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8194 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8195};
8196
Daniel Vettera8bb6812014-02-10 18:00:39 +01008197struct drm_framebuffer *
8198__intel_framebuffer_create(struct drm_device *dev,
8199 struct drm_mode_fb_cmd2 *mode_cmd,
8200 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008201{
8202 struct intel_framebuffer *intel_fb;
8203 int ret;
8204
8205 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8206 if (!intel_fb) {
8207 drm_gem_object_unreference_unlocked(&obj->base);
8208 return ERR_PTR(-ENOMEM);
8209 }
8210
8211 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008212 if (ret)
8213 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008214
8215 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008216err:
8217 drm_gem_object_unreference_unlocked(&obj->base);
8218 kfree(intel_fb);
8219
8220 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008221}
8222
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008223static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008224intel_framebuffer_create(struct drm_device *dev,
8225 struct drm_mode_fb_cmd2 *mode_cmd,
8226 struct drm_i915_gem_object *obj)
8227{
8228 struct drm_framebuffer *fb;
8229 int ret;
8230
8231 ret = i915_mutex_lock_interruptible(dev);
8232 if (ret)
8233 return ERR_PTR(ret);
8234 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8235 mutex_unlock(&dev->struct_mutex);
8236
8237 return fb;
8238}
8239
Chris Wilsond2dff872011-04-19 08:36:26 +01008240static u32
8241intel_framebuffer_pitch_for_width(int width, int bpp)
8242{
8243 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8244 return ALIGN(pitch, 64);
8245}
8246
8247static u32
8248intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8249{
8250 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8251 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8252}
8253
8254static struct drm_framebuffer *
8255intel_framebuffer_create_for_mode(struct drm_device *dev,
8256 struct drm_display_mode *mode,
8257 int depth, int bpp)
8258{
8259 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008260 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008261
8262 obj = i915_gem_alloc_object(dev,
8263 intel_framebuffer_size_for_mode(mode, bpp));
8264 if (obj == NULL)
8265 return ERR_PTR(-ENOMEM);
8266
8267 mode_cmd.width = mode->hdisplay;
8268 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008269 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8270 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008271 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008272
8273 return intel_framebuffer_create(dev, &mode_cmd, obj);
8274}
8275
8276static struct drm_framebuffer *
8277mode_fits_in_fbdev(struct drm_device *dev,
8278 struct drm_display_mode *mode)
8279{
Daniel Vetter4520f532013-10-09 09:18:51 +02008280#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008281 struct drm_i915_private *dev_priv = dev->dev_private;
8282 struct drm_i915_gem_object *obj;
8283 struct drm_framebuffer *fb;
8284
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008285 if (!dev_priv->fbdev)
8286 return NULL;
8287
8288 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008289 return NULL;
8290
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008291 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008292 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008293
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008294 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008295 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8296 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008297 return NULL;
8298
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008299 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008300 return NULL;
8301
8302 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008303#else
8304 return NULL;
8305#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008306}
8307
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008308bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008309 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01008310 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008311{
8312 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008313 struct intel_encoder *intel_encoder =
8314 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008315 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008316 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008317 struct drm_crtc *crtc = NULL;
8318 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008319 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08008320 int i = -1;
8321
Chris Wilsond2dff872011-04-19 08:36:26 +01008322 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008323 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008324 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008325
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008326 mutex_lock(&dev->mode_config.connection_mutex);
8327
Jesse Barnes79e53942008-11-07 14:24:08 -08008328 /*
8329 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008330 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008331 * - if the connector already has an assigned crtc, use it (but make
8332 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008333 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008334 * - try to find the first unused crtc that can drive this connector,
8335 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008336 */
8337
8338 /* See if we already have a CRTC for this connector */
8339 if (encoder->crtc) {
8340 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008341
Daniel Vetter7b240562012-12-12 00:35:33 +01008342 mutex_lock(&crtc->mutex);
8343
Daniel Vetter24218aa2012-08-12 19:27:11 +02008344 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008345 old->load_detect_temp = false;
8346
8347 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008348 if (connector->dpms != DRM_MODE_DPMS_ON)
8349 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008350
Chris Wilson71731882011-04-19 23:10:58 +01008351 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008352 }
8353
8354 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008355 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008356 i++;
8357 if (!(encoder->possible_crtcs & (1 << i)))
8358 continue;
8359 if (!possible_crtc->enabled) {
8360 crtc = possible_crtc;
8361 break;
8362 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008363 }
8364
8365 /*
8366 * If we didn't find an unused CRTC, don't use any.
8367 */
8368 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008369 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008370 goto fail_unlock_connector;
Jesse Barnes79e53942008-11-07 14:24:08 -08008371 }
8372
Daniel Vetter7b240562012-12-12 00:35:33 +01008373 mutex_lock(&crtc->mutex);
Daniel Vetterfc303102012-07-09 10:40:58 +02008374 intel_encoder->new_crtc = to_intel_crtc(crtc);
8375 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008376
8377 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008378 intel_crtc->new_enabled = true;
8379 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008380 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008381 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008382 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008383
Chris Wilson64927112011-04-20 07:25:26 +01008384 if (!mode)
8385 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008386
Chris Wilsond2dff872011-04-19 08:36:26 +01008387 /* We need a framebuffer large enough to accommodate all accesses
8388 * that the plane may generate whilst we perform load detection.
8389 * We can not rely on the fbcon either being present (we get called
8390 * during its initialisation to detect all boot displays, or it may
8391 * not even exist) or that it is large enough to satisfy the
8392 * requested mode.
8393 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008394 fb = mode_fits_in_fbdev(dev, mode);
8395 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008396 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008397 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8398 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008399 } else
8400 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008401 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008402 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008403 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008404 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008405
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008406 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008407 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008408 if (old->release_fb)
8409 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008410 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008411 }
Chris Wilson71731882011-04-19 23:10:58 +01008412
Jesse Barnes79e53942008-11-07 14:24:08 -08008413 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008414 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008415 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008416
8417 fail:
8418 intel_crtc->new_enabled = crtc->enabled;
8419 if (intel_crtc->new_enabled)
8420 intel_crtc->new_config = &intel_crtc->config;
8421 else
8422 intel_crtc->new_config = NULL;
8423 mutex_unlock(&crtc->mutex);
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008424fail_unlock_connector:
8425 mutex_unlock(&dev->mode_config.connection_mutex);
8426
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008427 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008428}
8429
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008430void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01008431 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008432{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008433 struct intel_encoder *intel_encoder =
8434 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008435 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008436 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008438
Chris Wilsond2dff872011-04-19 08:36:26 +01008439 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008440 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008441 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008442
Chris Wilson8261b192011-04-19 23:18:09 +01008443 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008444 to_intel_connector(connector)->new_encoder = NULL;
8445 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008446 intel_crtc->new_enabled = false;
8447 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008448 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008449
Daniel Vetter36206362012-12-10 20:42:17 +01008450 if (old->release_fb) {
8451 drm_framebuffer_unregister_private(old->release_fb);
8452 drm_framebuffer_unreference(old->release_fb);
8453 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008454
Daniel Vetter67c96402013-01-23 16:25:09 +00008455 mutex_unlock(&crtc->mutex);
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008456 mutex_unlock(&connector->dev->mode_config.connection_mutex);
Chris Wilson0622a532011-04-21 09:32:11 +01008457 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008458 }
8459
Eric Anholtc751ce42010-03-25 11:48:48 -07008460 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008461 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8462 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01008463
8464 mutex_unlock(&crtc->mutex);
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008465 mutex_unlock(&connector->dev->mode_config.connection_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08008466}
8467
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008468static int i9xx_pll_refclk(struct drm_device *dev,
8469 const struct intel_crtc_config *pipe_config)
8470{
8471 struct drm_i915_private *dev_priv = dev->dev_private;
8472 u32 dpll = pipe_config->dpll_hw_state.dpll;
8473
8474 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008475 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008476 else if (HAS_PCH_SPLIT(dev))
8477 return 120000;
8478 else if (!IS_GEN2(dev))
8479 return 96000;
8480 else
8481 return 48000;
8482}
8483
Jesse Barnes79e53942008-11-07 14:24:08 -08008484/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008485static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8486 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008487{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008488 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008489 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008490 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008491 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008492 u32 fp;
8493 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008494 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008495
8496 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008497 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008498 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008499 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008500
8501 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008502 if (IS_PINEVIEW(dev)) {
8503 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8504 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008505 } else {
8506 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8507 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8508 }
8509
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008510 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008511 if (IS_PINEVIEW(dev))
8512 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8513 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008514 else
8515 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008516 DPLL_FPA01_P1_POST_DIV_SHIFT);
8517
8518 switch (dpll & DPLL_MODE_MASK) {
8519 case DPLLB_MODE_DAC_SERIAL:
8520 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8521 5 : 10;
8522 break;
8523 case DPLLB_MODE_LVDS:
8524 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8525 7 : 14;
8526 break;
8527 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008528 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008529 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008530 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008531 }
8532
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008533 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008534 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008535 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008536 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008537 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008538 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008539 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008540
8541 if (is_lvds) {
8542 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8543 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008544
8545 if (lvds & LVDS_CLKB_POWER_UP)
8546 clock.p2 = 7;
8547 else
8548 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008549 } else {
8550 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8551 clock.p1 = 2;
8552 else {
8553 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8554 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8555 }
8556 if (dpll & PLL_P2_DIVIDE_BY_4)
8557 clock.p2 = 4;
8558 else
8559 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008560 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008561
8562 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008563 }
8564
Ville Syrjälä18442d02013-09-13 16:00:08 +03008565 /*
8566 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008567 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008568 * encoder's get_config() function.
8569 */
8570 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008571}
8572
Ville Syrjälä6878da02013-09-13 15:59:11 +03008573int intel_dotclock_calculate(int link_freq,
8574 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008575{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008576 /*
8577 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008578 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008579 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008580 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008581 *
8582 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008583 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008584 */
8585
Ville Syrjälä6878da02013-09-13 15:59:11 +03008586 if (!m_n->link_n)
8587 return 0;
8588
8589 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8590}
8591
Ville Syrjälä18442d02013-09-13 16:00:08 +03008592static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8593 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008594{
8595 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008596
8597 /* read out port_clock from the DPLL */
8598 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008599
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008600 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008601 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008602 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008603 * agree once we know their relationship in the encoder's
8604 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008605 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008606 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008607 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8608 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008609}
8610
8611/** Returns the currently programmed mode of the given pipe. */
8612struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8613 struct drm_crtc *crtc)
8614{
Jesse Barnes548f2452011-02-17 10:40:53 -08008615 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008617 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008618 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008619 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008620 int htot = I915_READ(HTOTAL(cpu_transcoder));
8621 int hsync = I915_READ(HSYNC(cpu_transcoder));
8622 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8623 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008624 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008625
8626 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8627 if (!mode)
8628 return NULL;
8629
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008630 /*
8631 * Construct a pipe_config sufficient for getting the clock info
8632 * back out of crtc_clock_get.
8633 *
8634 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8635 * to use a real value here instead.
8636 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008637 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008638 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008639 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8640 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8641 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008642 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8643
Ville Syrjälä773ae032013-09-23 17:48:20 +03008644 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008645 mode->hdisplay = (htot & 0xffff) + 1;
8646 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8647 mode->hsync_start = (hsync & 0xffff) + 1;
8648 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8649 mode->vdisplay = (vtot & 0xffff) + 1;
8650 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8651 mode->vsync_start = (vsync & 0xffff) + 1;
8652 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8653
8654 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008655
8656 return mode;
8657}
8658
Daniel Vetter3dec0092010-08-20 21:40:52 +02008659static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07008660{
8661 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008662 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008665 int dpll_reg = DPLL(pipe);
8666 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07008667
Eric Anholtbad720f2009-10-22 16:11:14 -07008668 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008669 return;
8670
8671 if (!dev_priv->lvds_downclock_avail)
8672 return;
8673
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008674 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008675 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08008676 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008677
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008678 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008679
8680 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8681 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008682 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008683
Jesse Barnes652c3932009-08-17 13:31:43 -07008684 dpll = I915_READ(dpll_reg);
8685 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08008686 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008687 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008688}
8689
8690static void intel_decrease_pllclock(struct drm_crtc *crtc)
8691{
8692 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008693 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008695
Eric Anholtbad720f2009-10-22 16:11:14 -07008696 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008697 return;
8698
8699 if (!dev_priv->lvds_downclock_avail)
8700 return;
8701
8702 /*
8703 * Since this is called by a timer, we should never get here in
8704 * the manual case.
8705 */
8706 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008707 int pipe = intel_crtc->pipe;
8708 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008709 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008710
Zhao Yakui44d98a62009-10-09 11:39:40 +08008711 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008712
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008713 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008714
Chris Wilson074b5e12012-05-02 12:07:06 +01008715 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008716 dpll |= DISPLAY_RATE_SELECT_FPA1;
8717 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008718 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008719 dpll = I915_READ(dpll_reg);
8720 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008721 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008722 }
8723
8724}
8725
Chris Wilsonf047e392012-07-21 12:31:41 +01008726void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008727{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008728 struct drm_i915_private *dev_priv = dev->dev_private;
8729
Chris Wilsonf62a0072014-02-21 17:55:39 +00008730 if (dev_priv->mm.busy)
8731 return;
8732
Paulo Zanoni43694d62014-03-07 20:08:08 -03008733 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008734 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008735 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008736}
8737
8738void intel_mark_idle(struct drm_device *dev)
8739{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008740 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008741 struct drm_crtc *crtc;
8742
Chris Wilsonf62a0072014-02-21 17:55:39 +00008743 if (!dev_priv->mm.busy)
8744 return;
8745
8746 dev_priv->mm.busy = false;
8747
Jani Nikulad330a952014-01-21 11:24:25 +02008748 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008749 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008750
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008751 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008752 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008753 continue;
8754
8755 intel_decrease_pllclock(crtc);
8756 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008757
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008758 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008759 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008760
8761out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03008762 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008763}
8764
Chris Wilsonc65355b2013-06-06 16:53:41 -03008765void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01008766 struct intel_engine_cs *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01008767{
8768 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07008769 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07008770
Jani Nikulad330a952014-01-21 11:24:25 +02008771 if (!i915.powersave)
Jesse Barnes652c3932009-08-17 13:31:43 -07008772 return;
8773
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008774 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008775 if (!crtc->primary->fb)
Jesse Barnes652c3932009-08-17 13:31:43 -07008776 continue;
8777
Matt Roperf4510a22014-04-01 15:22:40 -07008778 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
Chris Wilsonc65355b2013-06-06 16:53:41 -03008779 continue;
8780
8781 intel_increase_pllclock(crtc);
8782 if (ring && intel_fbc_enabled(dev))
8783 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07008784 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008785}
8786
Jesse Barnes79e53942008-11-07 14:24:08 -08008787static void intel_crtc_destroy(struct drm_crtc *crtc)
8788{
8789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008790 struct drm_device *dev = crtc->dev;
8791 struct intel_unpin_work *work;
8792 unsigned long flags;
8793
8794 spin_lock_irqsave(&dev->event_lock, flags);
8795 work = intel_crtc->unpin_work;
8796 intel_crtc->unpin_work = NULL;
8797 spin_unlock_irqrestore(&dev->event_lock, flags);
8798
8799 if (work) {
8800 cancel_work_sync(&work->work);
8801 kfree(work);
8802 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008803
Mika Kuoppala40ccc722013-04-23 17:27:08 +03008804 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8805
Jesse Barnes79e53942008-11-07 14:24:08 -08008806 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008807
Jesse Barnes79e53942008-11-07 14:24:08 -08008808 kfree(intel_crtc);
8809}
8810
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008811static void intel_unpin_work_fn(struct work_struct *__work)
8812{
8813 struct intel_unpin_work *work =
8814 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008815 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008816
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008817 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01008818 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00008819 drm_gem_object_unreference(&work->pending_flip_obj->base);
8820 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008821
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008822 intel_update_fbc(dev);
8823 mutex_unlock(&dev->struct_mutex);
8824
8825 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8826 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8827
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008828 kfree(work);
8829}
8830
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008831static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01008832 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008833{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008834 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8836 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008837 unsigned long flags;
8838
8839 /* Ignore early vblank irqs */
8840 if (intel_crtc == NULL)
8841 return;
8842
8843 spin_lock_irqsave(&dev->event_lock, flags);
8844 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00008845
8846 /* Ensure we don't miss a work->pending update ... */
8847 smp_rmb();
8848
8849 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008850 spin_unlock_irqrestore(&dev->event_lock, flags);
8851 return;
8852 }
8853
Chris Wilsone7d841c2012-12-03 11:36:30 +00008854 /* and that the unpin work is consistent wrt ->pending. */
8855 smp_rmb();
8856
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008857 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008858
Rob Clark45a066e2012-10-08 14:50:40 -05008859 if (work->event)
8860 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008861
Daniel Vetter87b6b102014-05-15 15:33:46 +02008862 drm_crtc_vblank_put(crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01008863
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008864 spin_unlock_irqrestore(&dev->event_lock, flags);
8865
Daniel Vetter2c10d572012-12-20 21:24:07 +01008866 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008867
8868 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07008869
8870 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008871}
8872
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008873void intel_finish_page_flip(struct drm_device *dev, int pipe)
8874{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008875 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008876 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8877
Mario Kleiner49b14a52010-12-09 07:00:07 +01008878 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008879}
8880
8881void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8882{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008883 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008884 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8885
Mario Kleiner49b14a52010-12-09 07:00:07 +01008886 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008887}
8888
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008889/* Is 'a' after or equal to 'b'? */
8890static bool g4x_flip_count_after_eq(u32 a, u32 b)
8891{
8892 return !((a - b) & 0x80000000);
8893}
8894
8895static bool page_flip_finished(struct intel_crtc *crtc)
8896{
8897 struct drm_device *dev = crtc->base.dev;
8898 struct drm_i915_private *dev_priv = dev->dev_private;
8899
8900 /*
8901 * The relevant registers doen't exist on pre-ctg.
8902 * As the flip done interrupt doesn't trigger for mmio
8903 * flips on gmch platforms, a flip count check isn't
8904 * really needed there. But since ctg has the registers,
8905 * include it in the check anyway.
8906 */
8907 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8908 return true;
8909
8910 /*
8911 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8912 * used the same base address. In that case the mmio flip might
8913 * have completed, but the CS hasn't even executed the flip yet.
8914 *
8915 * A flip count check isn't enough as the CS might have updated
8916 * the base address just after start of vblank, but before we
8917 * managed to process the interrupt. This means we'd complete the
8918 * CS flip too soon.
8919 *
8920 * Combining both checks should get us a good enough result. It may
8921 * still happen that the CS flip has been executed, but has not
8922 * yet actually completed. But in case the base address is the same
8923 * anyway, we don't really care.
8924 */
8925 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8926 crtc->unpin_work->gtt_offset &&
8927 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8928 crtc->unpin_work->flip_count);
8929}
8930
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008931void intel_prepare_page_flip(struct drm_device *dev, int plane)
8932{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008933 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008934 struct intel_crtc *intel_crtc =
8935 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8936 unsigned long flags;
8937
Chris Wilsone7d841c2012-12-03 11:36:30 +00008938 /* NB: An MMIO update of the plane base pointer will also
8939 * generate a page-flip completion irq, i.e. every modeset
8940 * is also accompanied by a spurious intel_prepare_page_flip().
8941 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008942 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008943 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00008944 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008945 spin_unlock_irqrestore(&dev->event_lock, flags);
8946}
8947
Robin Schroereba905b2014-05-18 02:24:50 +02008948static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00008949{
8950 /* Ensure that the work item is consistent when activating it ... */
8951 smp_wmb();
8952 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8953 /* and that it is marked active as soon as the irq could fire. */
8954 smp_wmb();
8955}
8956
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008957static int intel_gen2_queue_flip(struct drm_device *dev,
8958 struct drm_crtc *crtc,
8959 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008960 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01008961 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07008962 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008963{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008965 u32 flip_mask;
8966 int ret;
8967
Daniel Vetter6d90c952012-04-26 23:28:05 +02008968 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008969 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03008970 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008971
8972 /* Can't queue multiple flips, so wait for the previous
8973 * one to finish before executing the next.
8974 */
8975 if (intel_crtc->plane)
8976 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8977 else
8978 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008979 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8980 intel_ring_emit(ring, MI_NOOP);
8981 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8982 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8983 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008984 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008985 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00008986
8987 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008988 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008989 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008990}
8991
8992static int intel_gen3_queue_flip(struct drm_device *dev,
8993 struct drm_crtc *crtc,
8994 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008995 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01008996 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07008997 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008998{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009000 u32 flip_mask;
9001 int ret;
9002
Daniel Vetter6d90c952012-04-26 23:28:05 +02009003 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009004 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009005 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009006
9007 if (intel_crtc->plane)
9008 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9009 else
9010 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009011 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9012 intel_ring_emit(ring, MI_NOOP);
9013 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9014 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9015 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009016 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009017 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009018
Chris Wilsone7d841c2012-12-03 11:36:30 +00009019 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009020 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009021 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009022}
9023
9024static int intel_gen4_queue_flip(struct drm_device *dev,
9025 struct drm_crtc *crtc,
9026 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009027 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009028 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009029 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009030{
9031 struct drm_i915_private *dev_priv = dev->dev_private;
9032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9033 uint32_t pf, pipesrc;
9034 int ret;
9035
Daniel Vetter6d90c952012-04-26 23:28:05 +02009036 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009037 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009038 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009039
9040 /* i965+ uses the linear or tiled offsets from the
9041 * Display Registers (which do not change across a page-flip)
9042 * so we need only reprogram the base address.
9043 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009044 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9045 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9046 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009047 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009048 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009049
9050 /* XXX Enabling the panel-fitter across page-flip is so far
9051 * untested on non-native modes, so ignore it for now.
9052 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9053 */
9054 pf = 0;
9055 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009056 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009057
9058 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009059 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009060 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009061}
9062
9063static int intel_gen6_queue_flip(struct drm_device *dev,
9064 struct drm_crtc *crtc,
9065 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009066 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009067 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009068 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009069{
9070 struct drm_i915_private *dev_priv = dev->dev_private;
9071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9072 uint32_t pf, pipesrc;
9073 int ret;
9074
Daniel Vetter6d90c952012-04-26 23:28:05 +02009075 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009076 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009077 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009078
Daniel Vetter6d90c952012-04-26 23:28:05 +02009079 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9080 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9081 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009082 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009083
Chris Wilson99d9acd2012-04-17 20:37:00 +01009084 /* Contrary to the suggestions in the documentation,
9085 * "Enable Panel Fitter" does not seem to be required when page
9086 * flipping with a non-native mode, and worse causes a normal
9087 * modeset to fail.
9088 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9089 */
9090 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009091 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009092 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009093
9094 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009095 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009096 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009097}
9098
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009099static int intel_gen7_queue_flip(struct drm_device *dev,
9100 struct drm_crtc *crtc,
9101 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009102 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009103 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009104 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009105{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009107 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009108 int len, ret;
9109
Robin Schroereba905b2014-05-18 02:24:50 +02009110 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009111 case PLANE_A:
9112 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9113 break;
9114 case PLANE_B:
9115 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9116 break;
9117 case PLANE_C:
9118 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9119 break;
9120 default:
9121 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009122 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009123 }
9124
Chris Wilsonffe74d72013-08-26 20:58:12 +01009125 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009126 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009127 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009128 /*
9129 * On Gen 8, SRM is now taking an extra dword to accommodate
9130 * 48bits addresses, and we need a NOOP for the batch size to
9131 * stay even.
9132 */
9133 if (IS_GEN8(dev))
9134 len += 2;
9135 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009136
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009137 /*
9138 * BSpec MI_DISPLAY_FLIP for IVB:
9139 * "The full packet must be contained within the same cache line."
9140 *
9141 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9142 * cacheline, if we ever start emitting more commands before
9143 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9144 * then do the cacheline alignment, and finally emit the
9145 * MI_DISPLAY_FLIP.
9146 */
9147 ret = intel_ring_cacheline_align(ring);
9148 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009149 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009150
Chris Wilsonffe74d72013-08-26 20:58:12 +01009151 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009152 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009153 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009154
Chris Wilsonffe74d72013-08-26 20:58:12 +01009155 /* Unmask the flip-done completion message. Note that the bspec says that
9156 * we should do this for both the BCS and RCS, and that we must not unmask
9157 * more than one flip event at any time (or ensure that one flip message
9158 * can be sent by waiting for flip-done prior to queueing new flips).
9159 * Experimentation says that BCS works despite DERRMR masking all
9160 * flip-done completion events and that unmasking all planes at once
9161 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9162 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9163 */
9164 if (ring->id == RCS) {
9165 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9166 intel_ring_emit(ring, DERRMR);
9167 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9168 DERRMR_PIPEB_PRI_FLIP_DONE |
9169 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009170 if (IS_GEN8(dev))
9171 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9172 MI_SRM_LRM_GLOBAL_GTT);
9173 else
9174 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9175 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009176 intel_ring_emit(ring, DERRMR);
9177 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009178 if (IS_GEN8(dev)) {
9179 intel_ring_emit(ring, 0);
9180 intel_ring_emit(ring, MI_NOOP);
9181 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009182 }
9183
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009184 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009185 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009186 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009187 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009188
9189 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009190 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009191 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009192}
9193
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009194static int intel_default_queue_flip(struct drm_device *dev,
9195 struct drm_crtc *crtc,
9196 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009197 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009198 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009199 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009200{
9201 return -ENODEV;
9202}
9203
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009204static int intel_crtc_page_flip(struct drm_crtc *crtc,
9205 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009206 struct drm_pending_vblank_event *event,
9207 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009208{
9209 struct drm_device *dev = crtc->dev;
9210 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009211 struct drm_framebuffer *old_fb = crtc->primary->fb;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02009212 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9214 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009215 struct intel_engine_cs *ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009216 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01009217 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009218
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009219 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009220 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009221 return -EINVAL;
9222
9223 /*
9224 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9225 * Note that pitch changes could also affect these register.
9226 */
9227 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009228 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9229 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009230 return -EINVAL;
9231
Chris Wilsonf900db42014-02-20 09:26:13 +00009232 if (i915_terminally_wedged(&dev_priv->gpu_error))
9233 goto out_hang;
9234
Daniel Vetterb14c5672013-09-19 12:18:32 +02009235 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009236 if (work == NULL)
9237 return -ENOMEM;
9238
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009239 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009240 work->crtc = crtc;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02009241 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009242 INIT_WORK(&work->work, intel_unpin_work_fn);
9243
Daniel Vetter87b6b102014-05-15 15:33:46 +02009244 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009245 if (ret)
9246 goto free_work;
9247
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009248 /* We borrow the event spin lock for protecting unpin_work */
9249 spin_lock_irqsave(&dev->event_lock, flags);
9250 if (intel_crtc->unpin_work) {
9251 spin_unlock_irqrestore(&dev->event_lock, flags);
9252 kfree(work);
Daniel Vetter87b6b102014-05-15 15:33:46 +02009253 drm_crtc_vblank_put(crtc);
Chris Wilson468f0b42010-05-27 13:18:13 +01009254
9255 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009256 return -EBUSY;
9257 }
9258 intel_crtc->unpin_work = work;
9259 spin_unlock_irqrestore(&dev->event_lock, flags);
9260
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009261 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9262 flush_workqueue(dev_priv->wq);
9263
Chris Wilson79158102012-05-23 11:13:58 +01009264 ret = i915_mutex_lock_interruptible(dev);
9265 if (ret)
9266 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009267
Jesse Barnes75dfca82010-02-10 15:09:44 -08009268 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009269 drm_gem_object_reference(&work->old_fb_obj->base);
9270 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009271
Matt Roperf4510a22014-04-01 15:22:40 -07009272 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009273
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009274 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009275
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01009276 work->enable_stall_check = true;
9277
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009278 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009279 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009280
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009281 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9282 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9283
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009284 if (IS_VALLEYVIEW(dev)) {
9285 ring = &dev_priv->ring[BCS];
9286 } else if (INTEL_INFO(dev)->gen >= 7) {
9287 ring = obj->ring;
9288 if (ring == NULL || ring->id != RCS)
9289 ring = &dev_priv->ring[BCS];
9290 } else {
9291 ring = &dev_priv->ring[RCS];
9292 }
9293
9294 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009295 if (ret)
9296 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009297
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009298 work->gtt_offset =
9299 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9300
9301 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags);
9302 if (ret)
9303 goto cleanup_unpin;
9304
Chris Wilson7782de32011-07-08 12:22:41 +01009305 intel_disable_fbc(dev);
Chris Wilsonc65355b2013-06-06 16:53:41 -03009306 intel_mark_fb_busy(obj, NULL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009307 mutex_unlock(&dev->struct_mutex);
9308
Jesse Barnese5510fa2010-07-01 16:48:37 -07009309 trace_i915_flip_request(intel_crtc->plane, obj);
9310
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009311 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009312
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009313cleanup_unpin:
9314 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009315cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009316 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009317 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009318 drm_gem_object_unreference(&work->old_fb_obj->base);
9319 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009320 mutex_unlock(&dev->struct_mutex);
9321
Chris Wilson79158102012-05-23 11:13:58 +01009322cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01009323 spin_lock_irqsave(&dev->event_lock, flags);
9324 intel_crtc->unpin_work = NULL;
9325 spin_unlock_irqrestore(&dev->event_lock, flags);
9326
Daniel Vetter87b6b102014-05-15 15:33:46 +02009327 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009328free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009329 kfree(work);
9330
Chris Wilsonf900db42014-02-20 09:26:13 +00009331 if (ret == -EIO) {
9332out_hang:
9333 intel_crtc_wait_for_pending_flips(crtc);
9334 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9335 if (ret == 0 && event)
9336 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9337 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009338 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009339}
9340
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009341static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009342 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9343 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009344};
9345
Daniel Vetter9a935852012-07-05 22:34:27 +02009346/**
9347 * intel_modeset_update_staged_output_state
9348 *
9349 * Updates the staged output configuration state, e.g. after we've read out the
9350 * current hw state.
9351 */
9352static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9353{
Ville Syrjälä76688512014-01-10 11:28:06 +02009354 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009355 struct intel_encoder *encoder;
9356 struct intel_connector *connector;
9357
9358 list_for_each_entry(connector, &dev->mode_config.connector_list,
9359 base.head) {
9360 connector->new_encoder =
9361 to_intel_encoder(connector->base.encoder);
9362 }
9363
9364 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9365 base.head) {
9366 encoder->new_crtc =
9367 to_intel_crtc(encoder->base.crtc);
9368 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009369
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009370 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009371 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009372
9373 if (crtc->new_enabled)
9374 crtc->new_config = &crtc->config;
9375 else
9376 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009377 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009378}
9379
9380/**
9381 * intel_modeset_commit_output_state
9382 *
9383 * This function copies the stage display pipe configuration to the real one.
9384 */
9385static void intel_modeset_commit_output_state(struct drm_device *dev)
9386{
Ville Syrjälä76688512014-01-10 11:28:06 +02009387 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009388 struct intel_encoder *encoder;
9389 struct intel_connector *connector;
9390
9391 list_for_each_entry(connector, &dev->mode_config.connector_list,
9392 base.head) {
9393 connector->base.encoder = &connector->new_encoder->base;
9394 }
9395
9396 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9397 base.head) {
9398 encoder->base.crtc = &encoder->new_crtc->base;
9399 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009400
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009401 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009402 crtc->base.enabled = crtc->new_enabled;
9403 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009404}
9405
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009406static void
Robin Schroereba905b2014-05-18 02:24:50 +02009407connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009408 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009409{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009410 int bpp = pipe_config->pipe_bpp;
9411
9412 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9413 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009414 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009415
9416 /* Don't use an invalid EDID bpc value */
9417 if (connector->base.display_info.bpc &&
9418 connector->base.display_info.bpc * 3 < bpp) {
9419 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9420 bpp, connector->base.display_info.bpc*3);
9421 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9422 }
9423
9424 /* Clamp bpp to 8 on screens without EDID 1.4 */
9425 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9426 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9427 bpp);
9428 pipe_config->pipe_bpp = 24;
9429 }
9430}
9431
9432static int
9433compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9434 struct drm_framebuffer *fb,
9435 struct intel_crtc_config *pipe_config)
9436{
9437 struct drm_device *dev = crtc->base.dev;
9438 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009439 int bpp;
9440
Daniel Vetterd42264b2013-03-28 16:38:08 +01009441 switch (fb->pixel_format) {
9442 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009443 bpp = 8*3; /* since we go through a colormap */
9444 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009445 case DRM_FORMAT_XRGB1555:
9446 case DRM_FORMAT_ARGB1555:
9447 /* checked in intel_framebuffer_init already */
9448 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9449 return -EINVAL;
9450 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009451 bpp = 6*3; /* min is 18bpp */
9452 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009453 case DRM_FORMAT_XBGR8888:
9454 case DRM_FORMAT_ABGR8888:
9455 /* checked in intel_framebuffer_init already */
9456 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9457 return -EINVAL;
9458 case DRM_FORMAT_XRGB8888:
9459 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009460 bpp = 8*3;
9461 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009462 case DRM_FORMAT_XRGB2101010:
9463 case DRM_FORMAT_ARGB2101010:
9464 case DRM_FORMAT_XBGR2101010:
9465 case DRM_FORMAT_ABGR2101010:
9466 /* checked in intel_framebuffer_init already */
9467 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01009468 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009469 bpp = 10*3;
9470 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01009471 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009472 default:
9473 DRM_DEBUG_KMS("unsupported depth\n");
9474 return -EINVAL;
9475 }
9476
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009477 pipe_config->pipe_bpp = bpp;
9478
9479 /* Clamp display bpp to EDID value */
9480 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009481 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02009482 if (!connector->new_encoder ||
9483 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009484 continue;
9485
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009486 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009487 }
9488
9489 return bpp;
9490}
9491
Daniel Vetter644db712013-09-19 14:53:58 +02009492static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9493{
9494 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9495 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +01009496 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +02009497 mode->crtc_hdisplay, mode->crtc_hsync_start,
9498 mode->crtc_hsync_end, mode->crtc_htotal,
9499 mode->crtc_vdisplay, mode->crtc_vsync_start,
9500 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9501}
9502
Daniel Vetterc0b03412013-05-28 12:05:54 +02009503static void intel_dump_pipe_config(struct intel_crtc *crtc,
9504 struct intel_crtc_config *pipe_config,
9505 const char *context)
9506{
9507 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9508 context, pipe_name(crtc->pipe));
9509
9510 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9511 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9512 pipe_config->pipe_bpp, pipe_config->dither);
9513 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9514 pipe_config->has_pch_encoder,
9515 pipe_config->fdi_lanes,
9516 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9517 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9518 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009519 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9520 pipe_config->has_dp_encoder,
9521 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9522 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9523 pipe_config->dp_m_n.tu);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009524 DRM_DEBUG_KMS("requested mode:\n");
9525 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9526 DRM_DEBUG_KMS("adjusted mode:\n");
9527 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +02009528 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009529 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009530 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9531 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009532 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9533 pipe_config->gmch_pfit.control,
9534 pipe_config->gmch_pfit.pgm_ratios,
9535 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009536 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +02009537 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009538 pipe_config->pch_pfit.size,
9539 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009540 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03009541 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009542}
9543
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009544static bool encoders_cloneable(const struct intel_encoder *a,
9545 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009546{
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009547 /* masks could be asymmetric, so check both ways */
9548 return a == b || (a->cloneable & (1 << b->type) &&
9549 b->cloneable & (1 << a->type));
9550}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009551
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009552static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9553 struct intel_encoder *encoder)
9554{
9555 struct drm_device *dev = crtc->base.dev;
9556 struct intel_encoder *source_encoder;
9557
9558 list_for_each_entry(source_encoder,
9559 &dev->mode_config.encoder_list, base.head) {
9560 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009561 continue;
9562
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009563 if (!encoders_cloneable(encoder, source_encoder))
9564 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009565 }
9566
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009567 return true;
9568}
9569
9570static bool check_encoder_cloning(struct intel_crtc *crtc)
9571{
9572 struct drm_device *dev = crtc->base.dev;
9573 struct intel_encoder *encoder;
9574
9575 list_for_each_entry(encoder,
9576 &dev->mode_config.encoder_list, base.head) {
9577 if (encoder->new_crtc != crtc)
9578 continue;
9579
9580 if (!check_single_encoder_cloning(crtc, encoder))
9581 return false;
9582 }
9583
9584 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009585}
9586
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009587static struct intel_crtc_config *
9588intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009589 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009590 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02009591{
9592 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02009593 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009594 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +01009595 int plane_bpp, ret = -EINVAL;
9596 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +02009597
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009598 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009599 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9600 return ERR_PTR(-EINVAL);
9601 }
9602
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009603 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9604 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02009605 return ERR_PTR(-ENOMEM);
9606
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009607 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9608 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009609
Daniel Vettere143a212013-07-04 12:01:15 +02009610 pipe_config->cpu_transcoder =
9611 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009612 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009613
Imre Deak2960bc92013-07-30 13:36:32 +03009614 /*
9615 * Sanitize sync polarity flags based on requested ones. If neither
9616 * positive or negative polarity is requested, treat this as meaning
9617 * negative polarity.
9618 */
9619 if (!(pipe_config->adjusted_mode.flags &
9620 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9621 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9622
9623 if (!(pipe_config->adjusted_mode.flags &
9624 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9625 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9626
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009627 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9628 * plane pixel format and any sink constraints into account. Returns the
9629 * source plane bpp so that dithering can be selected on mismatches
9630 * after encoders and crtc also have had their say. */
9631 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9632 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009633 if (plane_bpp < 0)
9634 goto fail;
9635
Ville Syrjäläe41a56b2013-10-01 22:52:14 +03009636 /*
9637 * Determine the real pipe dimensions. Note that stereo modes can
9638 * increase the actual pipe size due to the frame doubling and
9639 * insertion of additional space for blanks between the frame. This
9640 * is stored in the crtc timings. We use the requested mode to do this
9641 * computation to clearly distinguish it from the adjusted mode, which
9642 * can be changed by the connectors in the below retry loop.
9643 */
9644 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9645 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9646 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9647
Daniel Vettere29c22c2013-02-21 00:00:16 +01009648encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +02009649 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +02009650 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +02009651 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +02009652
Daniel Vetter135c81b2013-07-21 21:37:09 +02009653 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +01009654 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +02009655
Daniel Vetter7758a112012-07-08 19:40:39 +02009656 /* Pass our mode to the connectors and the CRTC to give them a chance to
9657 * adjust it according to limitations or connector properties, and also
9658 * a chance to reject the mode entirely.
9659 */
9660 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9661 base.head) {
9662
9663 if (&encoder->new_crtc->base != crtc)
9664 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +01009665
Daniel Vetterefea6e82013-07-21 21:36:59 +02009666 if (!(encoder->compute_config(encoder, pipe_config))) {
9667 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +02009668 goto fail;
9669 }
9670 }
9671
Daniel Vetterff9a6752013-06-01 17:16:21 +02009672 /* Set default port clock if not overwritten by the encoder. Needs to be
9673 * done afterwards in case the encoder adjusts the mode. */
9674 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +01009675 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9676 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +02009677
Daniel Vettera43f6e02013-06-07 23:10:32 +02009678 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01009679 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +02009680 DRM_DEBUG_KMS("CRTC fixup failed\n");
9681 goto fail;
9682 }
Daniel Vettere29c22c2013-02-21 00:00:16 +01009683
9684 if (ret == RETRY) {
9685 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9686 ret = -EINVAL;
9687 goto fail;
9688 }
9689
9690 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9691 retry = false;
9692 goto encoder_retry;
9693 }
9694
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009695 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9696 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9697 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9698
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009699 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +02009700fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009701 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01009702 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +02009703}
9704
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009705/* Computes which crtcs are affected and sets the relevant bits in the mask. For
9706 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9707static void
9708intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9709 unsigned *prepare_pipes, unsigned *disable_pipes)
9710{
9711 struct intel_crtc *intel_crtc;
9712 struct drm_device *dev = crtc->dev;
9713 struct intel_encoder *encoder;
9714 struct intel_connector *connector;
9715 struct drm_crtc *tmp_crtc;
9716
9717 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9718
9719 /* Check which crtcs have changed outputs connected to them, these need
9720 * to be part of the prepare_pipes mask. We don't (yet) support global
9721 * modeset across multiple crtcs, so modeset_pipes will only have one
9722 * bit set at most. */
9723 list_for_each_entry(connector, &dev->mode_config.connector_list,
9724 base.head) {
9725 if (connector->base.encoder == &connector->new_encoder->base)
9726 continue;
9727
9728 if (connector->base.encoder) {
9729 tmp_crtc = connector->base.encoder->crtc;
9730
9731 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9732 }
9733
9734 if (connector->new_encoder)
9735 *prepare_pipes |=
9736 1 << connector->new_encoder->new_crtc->pipe;
9737 }
9738
9739 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9740 base.head) {
9741 if (encoder->base.crtc == &encoder->new_crtc->base)
9742 continue;
9743
9744 if (encoder->base.crtc) {
9745 tmp_crtc = encoder->base.crtc;
9746
9747 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9748 }
9749
9750 if (encoder->new_crtc)
9751 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9752 }
9753
Ville Syrjälä76688512014-01-10 11:28:06 +02009754 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009755 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009756 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009757 continue;
9758
Ville Syrjälä76688512014-01-10 11:28:06 +02009759 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009760 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +02009761 else
9762 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009763 }
9764
9765
9766 /* set_mode is also used to update properties on life display pipes. */
9767 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +02009768 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009769 *prepare_pipes |= 1 << intel_crtc->pipe;
9770
Daniel Vetterb6c51642013-04-12 18:48:43 +02009771 /*
9772 * For simplicity do a full modeset on any pipe where the output routing
9773 * changed. We could be more clever, but that would require us to be
9774 * more careful with calling the relevant encoder->mode_set functions.
9775 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009776 if (*prepare_pipes)
9777 *modeset_pipes = *prepare_pipes;
9778
9779 /* ... and mask these out. */
9780 *modeset_pipes &= ~(*disable_pipes);
9781 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +02009782
9783 /*
9784 * HACK: We don't (yet) fully support global modesets. intel_set_config
9785 * obies this rule, but the modeset restore mode of
9786 * intel_modeset_setup_hw_state does not.
9787 */
9788 *modeset_pipes &= 1 << intel_crtc->pipe;
9789 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +02009790
9791 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9792 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009793}
9794
Daniel Vetterea9d7582012-07-10 10:42:52 +02009795static bool intel_crtc_in_use(struct drm_crtc *crtc)
9796{
9797 struct drm_encoder *encoder;
9798 struct drm_device *dev = crtc->dev;
9799
9800 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9801 if (encoder->crtc == crtc)
9802 return true;
9803
9804 return false;
9805}
9806
9807static void
9808intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9809{
9810 struct intel_encoder *intel_encoder;
9811 struct intel_crtc *intel_crtc;
9812 struct drm_connector *connector;
9813
9814 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9815 base.head) {
9816 if (!intel_encoder->base.crtc)
9817 continue;
9818
9819 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9820
9821 if (prepare_pipes & (1 << intel_crtc->pipe))
9822 intel_encoder->connectors_active = false;
9823 }
9824
9825 intel_modeset_commit_output_state(dev);
9826
Ville Syrjälä76688512014-01-10 11:28:06 +02009827 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009828 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009829 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009830 WARN_ON(intel_crtc->new_config &&
9831 intel_crtc->new_config != &intel_crtc->config);
9832 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +02009833 }
9834
9835 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9836 if (!connector->encoder || !connector->encoder->crtc)
9837 continue;
9838
9839 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9840
9841 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02009842 struct drm_property *dpms_property =
9843 dev->mode_config.dpms_property;
9844
Daniel Vetterea9d7582012-07-10 10:42:52 +02009845 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05009846 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02009847 dpms_property,
9848 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02009849
9850 intel_encoder = to_intel_encoder(connector->encoder);
9851 intel_encoder->connectors_active = true;
9852 }
9853 }
9854
9855}
9856
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009857static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009858{
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009859 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009860
9861 if (clock1 == clock2)
9862 return true;
9863
9864 if (!clock1 || !clock2)
9865 return false;
9866
9867 diff = abs(clock1 - clock2);
9868
9869 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9870 return true;
9871
9872 return false;
9873}
9874
Daniel Vetter25c5b262012-07-08 22:08:04 +02009875#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9876 list_for_each_entry((intel_crtc), \
9877 &(dev)->mode_config.crtc_list, \
9878 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +02009879 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +02009880
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009881static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009882intel_pipe_config_compare(struct drm_device *dev,
9883 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009884 struct intel_crtc_config *pipe_config)
9885{
Daniel Vetter66e985c2013-06-05 13:34:20 +02009886#define PIPE_CONF_CHECK_X(name) \
9887 if (current_config->name != pipe_config->name) { \
9888 DRM_ERROR("mismatch in " #name " " \
9889 "(expected 0x%08x, found 0x%08x)\n", \
9890 current_config->name, \
9891 pipe_config->name); \
9892 return false; \
9893 }
9894
Daniel Vetter08a24032013-04-19 11:25:34 +02009895#define PIPE_CONF_CHECK_I(name) \
9896 if (current_config->name != pipe_config->name) { \
9897 DRM_ERROR("mismatch in " #name " " \
9898 "(expected %i, found %i)\n", \
9899 current_config->name, \
9900 pipe_config->name); \
9901 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +01009902 }
9903
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009904#define PIPE_CONF_CHECK_FLAGS(name, mask) \
9905 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -07009906 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009907 "(expected %i, found %i)\n", \
9908 current_config->name & (mask), \
9909 pipe_config->name & (mask)); \
9910 return false; \
9911 }
9912
Ville Syrjälä5e550652013-09-06 23:29:07 +03009913#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9914 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9915 DRM_ERROR("mismatch in " #name " " \
9916 "(expected %i, found %i)\n", \
9917 current_config->name, \
9918 pipe_config->name); \
9919 return false; \
9920 }
9921
Daniel Vetterbb760062013-06-06 14:55:52 +02009922#define PIPE_CONF_QUIRK(quirk) \
9923 ((current_config->quirks | pipe_config->quirks) & (quirk))
9924
Daniel Vettereccb1402013-05-22 00:50:22 +02009925 PIPE_CONF_CHECK_I(cpu_transcoder);
9926
Daniel Vetter08a24032013-04-19 11:25:34 +02009927 PIPE_CONF_CHECK_I(has_pch_encoder);
9928 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +02009929 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9930 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9931 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9932 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9933 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +02009934
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009935 PIPE_CONF_CHECK_I(has_dp_encoder);
9936 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9937 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9938 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9939 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9940 PIPE_CONF_CHECK_I(dp_m_n.tu);
9941
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009942 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9943 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9944 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9945 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9946 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9947 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9948
9949 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9950 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9951 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9952 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9953 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9954 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9955
Daniel Vetterc93f54c2013-06-27 19:47:19 +02009956 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +02009957 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02009958 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9959 IS_VALLEYVIEW(dev))
9960 PIPE_CONF_CHECK_I(limited_color_range);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009961
Daniel Vetter9ed109a2014-04-24 23:54:52 +02009962 PIPE_CONF_CHECK_I(has_audio);
9963
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009964 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9965 DRM_MODE_FLAG_INTERLACE);
9966
Daniel Vetterbb760062013-06-06 14:55:52 +02009967 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9968 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9969 DRM_MODE_FLAG_PHSYNC);
9970 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9971 DRM_MODE_FLAG_NHSYNC);
9972 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9973 DRM_MODE_FLAG_PVSYNC);
9974 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9975 DRM_MODE_FLAG_NVSYNC);
9976 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009977
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009978 PIPE_CONF_CHECK_I(pipe_src_w);
9979 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009980
Daniel Vetter99535992014-04-13 12:00:33 +02009981 /*
9982 * FIXME: BIOS likes to set up a cloned config with lvds+external
9983 * screen. Since we don't yet re-compute the pipe config when moving
9984 * just the lvds port away to another pipe the sw tracking won't match.
9985 *
9986 * Proper atomic modesets with recomputed global state will fix this.
9987 * Until then just don't check gmch state for inherited modes.
9988 */
9989 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9990 PIPE_CONF_CHECK_I(gmch_pfit.control);
9991 /* pfit ratios are autocomputed by the hw on gen4+ */
9992 if (INTEL_INFO(dev)->gen < 4)
9993 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9994 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9995 }
9996
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009997 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9998 if (current_config->pch_pfit.enabled) {
9999 PIPE_CONF_CHECK_I(pch_pfit.pos);
10000 PIPE_CONF_CHECK_I(pch_pfit.size);
10001 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010002
Jesse Barnese59150d2014-01-07 13:30:45 -080010003 /* BDW+ don't expose a synchronous way to read the state */
10004 if (IS_HASWELL(dev))
10005 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010006
Ville Syrjälä282740f2013-09-04 18:30:03 +030010007 PIPE_CONF_CHECK_I(double_wide);
10008
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010009 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010010 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010011 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010012 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10013 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010014
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010015 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10016 PIPE_CONF_CHECK_I(pipe_bpp);
10017
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010018 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10019 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010020
Daniel Vetter66e985c2013-06-05 13:34:20 +020010021#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010022#undef PIPE_CONF_CHECK_I
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010023#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010024#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010025#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010026
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010027 return true;
10028}
10029
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010030static void
10031check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010032{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010033 struct intel_connector *connector;
10034
10035 list_for_each_entry(connector, &dev->mode_config.connector_list,
10036 base.head) {
10037 /* This also checks the encoder/connector hw state with the
10038 * ->get_hw_state callbacks. */
10039 intel_connector_check_state(connector);
10040
10041 WARN(&connector->new_encoder->base != connector->base.encoder,
10042 "connector's staged encoder doesn't match current encoder\n");
10043 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010044}
10045
10046static void
10047check_encoder_state(struct drm_device *dev)
10048{
10049 struct intel_encoder *encoder;
10050 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010051
10052 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10053 base.head) {
10054 bool enabled = false;
10055 bool active = false;
10056 enum pipe pipe, tracked_pipe;
10057
10058 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10059 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030010060 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010061
10062 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10063 "encoder's stage crtc doesn't match current crtc\n");
10064 WARN(encoder->connectors_active && !encoder->base.crtc,
10065 "encoder's active_connectors set, but no crtc\n");
10066
10067 list_for_each_entry(connector, &dev->mode_config.connector_list,
10068 base.head) {
10069 if (connector->base.encoder != &encoder->base)
10070 continue;
10071 enabled = true;
10072 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10073 active = true;
10074 }
10075 WARN(!!encoder->base.crtc != enabled,
10076 "encoder's enabled state mismatch "
10077 "(expected %i, found %i)\n",
10078 !!encoder->base.crtc, enabled);
10079 WARN(active && !encoder->base.crtc,
10080 "active encoder with no crtc\n");
10081
10082 WARN(encoder->connectors_active != active,
10083 "encoder's computed active state doesn't match tracked active state "
10084 "(expected %i, found %i)\n", active, encoder->connectors_active);
10085
10086 active = encoder->get_hw_state(encoder, &pipe);
10087 WARN(active != encoder->connectors_active,
10088 "encoder's hw state doesn't match sw tracking "
10089 "(expected %i, found %i)\n",
10090 encoder->connectors_active, active);
10091
10092 if (!encoder->base.crtc)
10093 continue;
10094
10095 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10096 WARN(active && pipe != tracked_pipe,
10097 "active encoder's pipe doesn't match"
10098 "(expected %i, found %i)\n",
10099 tracked_pipe, pipe);
10100
10101 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010102}
10103
10104static void
10105check_crtc_state(struct drm_device *dev)
10106{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010107 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010108 struct intel_crtc *crtc;
10109 struct intel_encoder *encoder;
10110 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010111
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010112 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010113 bool enabled = false;
10114 bool active = false;
10115
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010116 memset(&pipe_config, 0, sizeof(pipe_config));
10117
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010118 DRM_DEBUG_KMS("[CRTC:%d]\n",
10119 crtc->base.base.id);
10120
10121 WARN(crtc->active && !crtc->base.enabled,
10122 "active crtc, but not enabled in sw tracking\n");
10123
10124 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10125 base.head) {
10126 if (encoder->base.crtc != &crtc->base)
10127 continue;
10128 enabled = true;
10129 if (encoder->connectors_active)
10130 active = true;
10131 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010132
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010133 WARN(active != crtc->active,
10134 "crtc's computed active state doesn't match tracked active state "
10135 "(expected %i, found %i)\n", active, crtc->active);
10136 WARN(enabled != crtc->base.enabled,
10137 "crtc's computed enabled state doesn't match tracked enabled state "
10138 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10139
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010140 active = dev_priv->display.get_pipe_config(crtc,
10141 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010142
10143 /* hw state is inconsistent with the pipe A quirk */
10144 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10145 active = crtc->active;
10146
Daniel Vetter6c49f242013-06-06 12:45:25 +020010147 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10148 base.head) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010149 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010150 if (encoder->base.crtc != &crtc->base)
10151 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010152 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010153 encoder->get_config(encoder, &pipe_config);
10154 }
10155
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010156 WARN(crtc->active != active,
10157 "crtc active state doesn't match with hw state "
10158 "(expected %i, found %i)\n", crtc->active, active);
10159
Daniel Vetterc0b03412013-05-28 12:05:54 +020010160 if (active &&
10161 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10162 WARN(1, "pipe state doesn't match!\n");
10163 intel_dump_pipe_config(crtc, &pipe_config,
10164 "[hw state]");
10165 intel_dump_pipe_config(crtc, &crtc->config,
10166 "[sw state]");
10167 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010168 }
10169}
10170
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010171static void
10172check_shared_dpll_state(struct drm_device *dev)
10173{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010174 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010175 struct intel_crtc *crtc;
10176 struct intel_dpll_hw_state dpll_hw_state;
10177 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010178
10179 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10180 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10181 int enabled_crtcs = 0, active_crtcs = 0;
10182 bool active;
10183
10184 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10185
10186 DRM_DEBUG_KMS("%s\n", pll->name);
10187
10188 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10189
10190 WARN(pll->active > pll->refcount,
10191 "more active pll users than references: %i vs %i\n",
10192 pll->active, pll->refcount);
10193 WARN(pll->active && !pll->on,
10194 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010195 WARN(pll->on && !pll->active,
10196 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010197 WARN(pll->on != active,
10198 "pll on state mismatch (expected %i, found %i)\n",
10199 pll->on, active);
10200
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010201 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010202 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10203 enabled_crtcs++;
10204 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10205 active_crtcs++;
10206 }
10207 WARN(pll->active != active_crtcs,
10208 "pll active crtcs mismatch (expected %i, found %i)\n",
10209 pll->active, active_crtcs);
10210 WARN(pll->refcount != enabled_crtcs,
10211 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10212 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010213
10214 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10215 sizeof(dpll_hw_state)),
10216 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010217 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010218}
10219
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010220void
10221intel_modeset_check_state(struct drm_device *dev)
10222{
10223 check_connector_state(dev);
10224 check_encoder_state(dev);
10225 check_crtc_state(dev);
10226 check_shared_dpll_state(dev);
10227}
10228
Ville Syrjälä18442d02013-09-13 16:00:08 +030010229void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10230 int dotclock)
10231{
10232 /*
10233 * FDI already provided one idea for the dotclock.
10234 * Yell if the encoder disagrees.
10235 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010236 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010237 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010238 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010239}
10240
Ville Syrjälä80715b22014-05-15 20:23:23 +030010241static void update_scanline_offset(struct intel_crtc *crtc)
10242{
10243 struct drm_device *dev = crtc->base.dev;
10244
10245 /*
10246 * The scanline counter increments at the leading edge of hsync.
10247 *
10248 * On most platforms it starts counting from vtotal-1 on the
10249 * first active line. That means the scanline counter value is
10250 * always one less than what we would expect. Ie. just after
10251 * start of vblank, which also occurs at start of hsync (on the
10252 * last active line), the scanline counter will read vblank_start-1.
10253 *
10254 * On gen2 the scanline counter starts counting from 1 instead
10255 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10256 * to keep the value positive), instead of adding one.
10257 *
10258 * On HSW+ the behaviour of the scanline counter depends on the output
10259 * type. For DP ports it behaves like most other platforms, but on HDMI
10260 * there's an extra 1 line difference. So we need to add two instead of
10261 * one to the value.
10262 */
10263 if (IS_GEN2(dev)) {
10264 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10265 int vtotal;
10266
10267 vtotal = mode->crtc_vtotal;
10268 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10269 vtotal /= 2;
10270
10271 crtc->scanline_offset = vtotal - 1;
10272 } else if (HAS_DDI(dev) &&
10273 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10274 crtc->scanline_offset = 2;
10275 } else
10276 crtc->scanline_offset = 1;
10277}
10278
Daniel Vetterf30da182013-04-11 20:22:50 +020010279static int __intel_set_mode(struct drm_crtc *crtc,
10280 struct drm_display_mode *mode,
10281 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +020010282{
10283 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010284 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010285 struct drm_display_mode *saved_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010286 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010287 struct intel_crtc *intel_crtc;
10288 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010289 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010290
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010291 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010292 if (!saved_mode)
10293 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010294
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010295 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +020010296 &prepare_pipes, &disable_pipes);
10297
Tim Gardner3ac18232012-12-07 07:54:26 -070010298 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010299
Daniel Vetter25c5b262012-07-08 22:08:04 +020010300 /* Hack: Because we don't (yet) support global modeset on multiple
10301 * crtcs, we don't keep track of the new mode for more than one crtc.
10302 * Hence simply check whether any bit is set in modeset_pipes in all the
10303 * pieces of code that are not yet converted to deal with mutliple crtcs
10304 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010305 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010306 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010307 if (IS_ERR(pipe_config)) {
10308 ret = PTR_ERR(pipe_config);
10309 pipe_config = NULL;
10310
Tim Gardner3ac18232012-12-07 07:54:26 -070010311 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010312 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020010313 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10314 "[modeset]");
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010315 to_intel_crtc(crtc)->new_config = pipe_config;
Daniel Vettera6778b32012-07-02 09:56:42 +020010316 }
10317
Jesse Barnes30a970c2013-11-04 13:48:12 -080010318 /*
10319 * See if the config requires any additional preparation, e.g.
10320 * to adjust global state with pipes off. We need to do this
10321 * here so we can get the modeset_pipe updated config for the new
10322 * mode set on this crtc. For other crtcs we need to use the
10323 * adjusted_mode bits in the crtc directly.
10324 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010325 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010326 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010327
Ville Syrjäläc164f832013-11-05 22:34:12 +020010328 /* may have added more to prepare_pipes than we should */
10329 prepare_pipes &= ~disable_pipes;
10330 }
10331
Daniel Vetter460da9162013-03-27 00:44:51 +010010332 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10333 intel_crtc_disable(&intel_crtc->base);
10334
Daniel Vetterea9d7582012-07-10 10:42:52 +020010335 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10336 if (intel_crtc->base.enabled)
10337 dev_priv->display.crtc_disable(&intel_crtc->base);
10338 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010339
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010340 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10341 * to set it here already despite that we pass it down the callchain.
10342 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010343 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010344 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010345 /* mode_set/enable/disable functions rely on a correct pipe
10346 * config. */
10347 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010348 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010349
10350 /*
10351 * Calculate and store various constants which
10352 * are later needed by vblank and swap-completion
10353 * timestamping. They are derived from true hwmode.
10354 */
10355 drm_calc_timestamping_constants(crtc,
10356 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010357 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010358
Daniel Vetterea9d7582012-07-10 10:42:52 +020010359 /* Only after disabling all output pipelines that will be changed can we
10360 * update the the output configuration. */
10361 intel_modeset_update_state(dev, prepare_pipes);
10362
Daniel Vetter47fab732012-10-26 10:58:18 +020010363 if (dev_priv->display.modeset_global_resources)
10364 dev_priv->display.modeset_global_resources(dev);
10365
Daniel Vettera6778b32012-07-02 09:56:42 +020010366 /* Set up the DPLL and any encoders state that needs to adjust or depend
10367 * on the DPLL.
10368 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010369 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Daniel Vetter4c107942014-04-24 23:55:05 +020010370 struct drm_framebuffer *old_fb;
10371
10372 mutex_lock(&dev->struct_mutex);
10373 ret = intel_pin_and_fence_fb_obj(dev,
10374 to_intel_framebuffer(fb)->obj,
10375 NULL);
10376 if (ret != 0) {
10377 DRM_ERROR("pin & fence failed\n");
10378 mutex_unlock(&dev->struct_mutex);
10379 goto done;
10380 }
10381 old_fb = crtc->primary->fb;
10382 if (old_fb)
10383 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10384 mutex_unlock(&dev->struct_mutex);
10385
10386 crtc->primary->fb = fb;
10387 crtc->x = x;
10388 crtc->y = y;
10389
Daniel Vetter4271b752014-04-24 23:55:00 +020010390 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10391 x, y, fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010392 if (ret)
10393 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +020010394 }
10395
10396 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030010397 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10398 update_scanline_offset(intel_crtc);
10399
Daniel Vetter25c5b262012-07-08 22:08:04 +020010400 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030010401 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010402
Daniel Vettera6778b32012-07-02 09:56:42 +020010403 /* FIXME: add subpixel order */
10404done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010405 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070010406 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010407
Tim Gardner3ac18232012-12-07 07:54:26 -070010408out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010409 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070010410 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020010411 return ret;
10412}
10413
Damien Lespiaue7457a92013-08-08 22:28:59 +010010414static int intel_set_mode(struct drm_crtc *crtc,
10415 struct drm_display_mode *mode,
10416 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020010417{
10418 int ret;
10419
10420 ret = __intel_set_mode(crtc, mode, x, y, fb);
10421
10422 if (ret == 0)
10423 intel_modeset_check_state(crtc->dev);
10424
10425 return ret;
10426}
10427
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010428void intel_crtc_restore_mode(struct drm_crtc *crtc)
10429{
Matt Roperf4510a22014-04-01 15:22:40 -070010430 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010431}
10432
Daniel Vetter25c5b262012-07-08 22:08:04 +020010433#undef for_each_intel_crtc_masked
10434
Daniel Vetterd9e55602012-07-04 22:16:09 +020010435static void intel_set_config_free(struct intel_set_config *config)
10436{
10437 if (!config)
10438 return;
10439
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010440 kfree(config->save_connector_encoders);
10441 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020010442 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020010443 kfree(config);
10444}
10445
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010446static int intel_set_config_save_state(struct drm_device *dev,
10447 struct intel_set_config *config)
10448{
Ville Syrjälä76688512014-01-10 11:28:06 +020010449 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010450 struct drm_encoder *encoder;
10451 struct drm_connector *connector;
10452 int count;
10453
Ville Syrjälä76688512014-01-10 11:28:06 +020010454 config->save_crtc_enabled =
10455 kcalloc(dev->mode_config.num_crtc,
10456 sizeof(bool), GFP_KERNEL);
10457 if (!config->save_crtc_enabled)
10458 return -ENOMEM;
10459
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010460 config->save_encoder_crtcs =
10461 kcalloc(dev->mode_config.num_encoder,
10462 sizeof(struct drm_crtc *), GFP_KERNEL);
10463 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010464 return -ENOMEM;
10465
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010466 config->save_connector_encoders =
10467 kcalloc(dev->mode_config.num_connector,
10468 sizeof(struct drm_encoder *), GFP_KERNEL);
10469 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010470 return -ENOMEM;
10471
10472 /* Copy data. Note that driver private data is not affected.
10473 * Should anything bad happen only the expected state is
10474 * restored, not the drivers personal bookkeeping.
10475 */
10476 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010010477 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010478 config->save_crtc_enabled[count++] = crtc->enabled;
10479 }
10480
10481 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010482 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010483 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010484 }
10485
10486 count = 0;
10487 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010488 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010489 }
10490
10491 return 0;
10492}
10493
10494static void intel_set_config_restore_state(struct drm_device *dev,
10495 struct intel_set_config *config)
10496{
Ville Syrjälä76688512014-01-10 11:28:06 +020010497 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020010498 struct intel_encoder *encoder;
10499 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010500 int count;
10501
10502 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010503 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010504 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010505
10506 if (crtc->new_enabled)
10507 crtc->new_config = &crtc->config;
10508 else
10509 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020010510 }
10511
10512 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010513 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10514 encoder->new_crtc =
10515 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010516 }
10517
10518 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010519 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10520 connector->new_encoder =
10521 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010522 }
10523}
10524
Imre Deake3de42b2013-05-03 19:44:07 +020010525static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010010526is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020010527{
10528 int i;
10529
Chris Wilson2e57f472013-07-17 12:14:40 +010010530 if (set->num_connectors == 0)
10531 return false;
10532
10533 if (WARN_ON(set->connectors == NULL))
10534 return false;
10535
10536 for (i = 0; i < set->num_connectors; i++)
10537 if (set->connectors[i]->encoder &&
10538 set->connectors[i]->encoder->crtc == set->crtc &&
10539 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020010540 return true;
10541
10542 return false;
10543}
10544
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010545static void
10546intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10547 struct intel_set_config *config)
10548{
10549
10550 /* We should be able to check here if the fb has the same properties
10551 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010010552 if (is_crtc_connector_off(set)) {
10553 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070010554 } else if (set->crtc->primary->fb != set->fb) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010555 /* If we have no fb then treat it as a full mode set */
Matt Roperf4510a22014-04-01 15:22:40 -070010556 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030010557 struct intel_crtc *intel_crtc =
10558 to_intel_crtc(set->crtc);
10559
Jani Nikulad330a952014-01-21 11:24:25 +020010560 if (intel_crtc->active && i915.fastboot) {
Jesse Barnes319d9822013-06-26 01:38:19 +030010561 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10562 config->fb_changed = true;
10563 } else {
10564 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10565 config->mode_changed = true;
10566 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010567 } else if (set->fb == NULL) {
10568 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010010569 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070010570 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010571 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020010572 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010573 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020010574 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010575 }
10576
Daniel Vetter835c5872012-07-10 18:11:08 +020010577 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010578 config->fb_changed = true;
10579
10580 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10581 DRM_DEBUG_KMS("modes are different, full mode set\n");
10582 drm_mode_debug_printmodeline(&set->crtc->mode);
10583 drm_mode_debug_printmodeline(set->mode);
10584 config->mode_changed = true;
10585 }
Chris Wilsona1d95702013-08-13 18:48:47 +010010586
10587 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10588 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010589}
10590
Daniel Vetter2e431052012-07-04 22:42:15 +020010591static int
Daniel Vetter9a935852012-07-05 22:34:27 +020010592intel_modeset_stage_output_state(struct drm_device *dev,
10593 struct drm_mode_set *set,
10594 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020010595{
Daniel Vetter9a935852012-07-05 22:34:27 +020010596 struct intel_connector *connector;
10597 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020010598 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030010599 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020010600
Damien Lespiau9abdda72013-02-13 13:29:23 +000010601 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020010602 * of connectors. For paranoia, double-check this. */
10603 WARN_ON(!set->fb && (set->num_connectors != 0));
10604 WARN_ON(set->fb && (set->num_connectors == 0));
10605
Daniel Vetter9a935852012-07-05 22:34:27 +020010606 list_for_each_entry(connector, &dev->mode_config.connector_list,
10607 base.head) {
10608 /* Otherwise traverse passed in connector list and get encoders
10609 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020010610 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020010611 if (set->connectors[ro] == &connector->base) {
10612 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +020010613 break;
10614 }
10615 }
10616
Daniel Vetter9a935852012-07-05 22:34:27 +020010617 /* If we disable the crtc, disable all its connectors. Also, if
10618 * the connector is on the changing crtc but not on the new
10619 * connector list, disable it. */
10620 if ((!set->fb || ro == set->num_connectors) &&
10621 connector->base.encoder &&
10622 connector->base.encoder->crtc == set->crtc) {
10623 connector->new_encoder = NULL;
10624
10625 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10626 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030010627 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020010628 }
10629
10630
10631 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020010632 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010633 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020010634 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010635 }
10636 /* connector->new_encoder is now updated for all connectors. */
10637
10638 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020010639 list_for_each_entry(connector, &dev->mode_config.connector_list,
10640 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010641 struct drm_crtc *new_crtc;
10642
Daniel Vetter9a935852012-07-05 22:34:27 +020010643 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020010644 continue;
10645
Daniel Vetter9a935852012-07-05 22:34:27 +020010646 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020010647
10648 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020010649 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020010650 new_crtc = set->crtc;
10651 }
10652
10653 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010010654 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10655 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010656 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020010657 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010658 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10659
10660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10661 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030010662 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020010663 new_crtc->base.id);
10664 }
10665
10666 /* Check for any encoders that needs to be disabled. */
10667 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10668 base.head) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010669 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010670 list_for_each_entry(connector,
10671 &dev->mode_config.connector_list,
10672 base.head) {
10673 if (connector->new_encoder == encoder) {
10674 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010675 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020010676 }
10677 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010678
10679 if (num_connectors == 0)
10680 encoder->new_crtc = NULL;
10681 else if (num_connectors > 1)
10682 return -EINVAL;
10683
Daniel Vetter9a935852012-07-05 22:34:27 +020010684 /* Only now check for crtc changes so we don't miss encoders
10685 * that will be disabled. */
10686 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020010687 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010688 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020010689 }
10690 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010691 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +020010692
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010693 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010694 crtc->new_enabled = false;
10695
10696 list_for_each_entry(encoder,
10697 &dev->mode_config.encoder_list,
10698 base.head) {
10699 if (encoder->new_crtc == crtc) {
10700 crtc->new_enabled = true;
10701 break;
10702 }
10703 }
10704
10705 if (crtc->new_enabled != crtc->base.enabled) {
10706 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10707 crtc->new_enabled ? "en" : "dis");
10708 config->mode_changed = true;
10709 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010710
10711 if (crtc->new_enabled)
10712 crtc->new_config = &crtc->config;
10713 else
10714 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020010715 }
10716
Daniel Vetter2e431052012-07-04 22:42:15 +020010717 return 0;
10718}
10719
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010720static void disable_crtc_nofb(struct intel_crtc *crtc)
10721{
10722 struct drm_device *dev = crtc->base.dev;
10723 struct intel_encoder *encoder;
10724 struct intel_connector *connector;
10725
10726 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10727 pipe_name(crtc->pipe));
10728
10729 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10730 if (connector->new_encoder &&
10731 connector->new_encoder->new_crtc == crtc)
10732 connector->new_encoder = NULL;
10733 }
10734
10735 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10736 if (encoder->new_crtc == crtc)
10737 encoder->new_crtc = NULL;
10738 }
10739
10740 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010741 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010742}
10743
Daniel Vetter2e431052012-07-04 22:42:15 +020010744static int intel_crtc_set_config(struct drm_mode_set *set)
10745{
10746 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020010747 struct drm_mode_set save_set;
10748 struct intel_set_config *config;
10749 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020010750
Daniel Vetter8d3e3752012-07-05 16:09:09 +020010751 BUG_ON(!set);
10752 BUG_ON(!set->crtc);
10753 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020010754
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010010755 /* Enforce sane interface api - has been abused by the fb helper. */
10756 BUG_ON(!set->mode && set->fb);
10757 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020010758
Daniel Vetter2e431052012-07-04 22:42:15 +020010759 if (set->fb) {
10760 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10761 set->crtc->base.id, set->fb->base.id,
10762 (int)set->num_connectors, set->x, set->y);
10763 } else {
10764 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020010765 }
10766
10767 dev = set->crtc->dev;
10768
10769 ret = -ENOMEM;
10770 config = kzalloc(sizeof(*config), GFP_KERNEL);
10771 if (!config)
10772 goto out_config;
10773
10774 ret = intel_set_config_save_state(dev, config);
10775 if (ret)
10776 goto out_config;
10777
10778 save_set.crtc = set->crtc;
10779 save_set.mode = &set->crtc->mode;
10780 save_set.x = set->crtc->x;
10781 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070010782 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020010783
10784 /* Compute whether we need a full modeset, only an fb base update or no
10785 * change at all. In the future we might also check whether only the
10786 * mode changed, e.g. for LVDS where we only change the panel fitter in
10787 * such cases. */
10788 intel_set_config_compute_mode_changes(set, config);
10789
Daniel Vetter9a935852012-07-05 22:34:27 +020010790 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020010791 if (ret)
10792 goto fail;
10793
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010794 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010795 ret = intel_set_mode(set->crtc, set->mode,
10796 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010797 } else if (config->fb_changed) {
Ville Syrjälä4878cae2013-02-18 19:08:48 +020010798 intel_crtc_wait_for_pending_flips(set->crtc);
10799
Daniel Vetter4f660f42012-07-02 09:47:37 +020010800 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020010801 set->x, set->y, set->fb);
Jesse Barnes7ca51a32014-01-07 13:50:49 -080010802 /*
10803 * In the fastboot case this may be our only check of the
10804 * state after boot. It would be better to only do it on
10805 * the first update, but we don't have a nice way of doing that
10806 * (and really, set_config isn't used much for high freq page
10807 * flipping, so increasing its cost here shouldn't be a big
10808 * deal).
10809 */
Jani Nikulad330a952014-01-21 11:24:25 +020010810 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080010811 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020010812 }
10813
Chris Wilson2d05eae2013-05-03 17:36:25 +010010814 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020010815 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10816 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020010817fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010010818 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020010819
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010820 /*
10821 * HACK: if the pipe was on, but we didn't have a framebuffer,
10822 * force the pipe off to avoid oopsing in the modeset code
10823 * due to fb==NULL. This should only happen during boot since
10824 * we don't yet reconstruct the FB from the hardware state.
10825 */
10826 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10827 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10828
Chris Wilson2d05eae2013-05-03 17:36:25 +010010829 /* Try to restore the config */
10830 if (config->mode_changed &&
10831 intel_set_mode(save_set.crtc, save_set.mode,
10832 save_set.x, save_set.y, save_set.fb))
10833 DRM_ERROR("failed to restore config after modeset failure\n");
10834 }
Daniel Vetter50f56112012-07-02 09:35:43 +020010835
Daniel Vetterd9e55602012-07-04 22:16:09 +020010836out_config:
10837 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020010838 return ret;
10839}
10840
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010841static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010842 .cursor_set = intel_crtc_cursor_set,
10843 .cursor_move = intel_crtc_cursor_move,
10844 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020010845 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010846 .destroy = intel_crtc_destroy,
10847 .page_flip = intel_crtc_page_flip,
10848};
10849
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010850static void intel_cpu_pll_init(struct drm_device *dev)
10851{
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010852 if (HAS_DDI(dev))
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010853 intel_ddi_pll_init(dev);
10854}
10855
Daniel Vetter53589012013-06-05 13:34:16 +020010856static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10857 struct intel_shared_dpll *pll,
10858 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010859{
Daniel Vetter53589012013-06-05 13:34:16 +020010860 uint32_t val;
10861
10862 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020010863 hw_state->dpll = val;
10864 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10865 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020010866
10867 return val & DPLL_VCO_ENABLE;
10868}
10869
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010870static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10871 struct intel_shared_dpll *pll)
10872{
10873 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10874 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10875}
10876
Daniel Vettere7b903d2013-06-05 13:34:14 +020010877static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10878 struct intel_shared_dpll *pll)
10879{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010880 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020010881 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020010882
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010883 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10884
10885 /* Wait for the clocks to stabilize. */
10886 POSTING_READ(PCH_DPLL(pll->id));
10887 udelay(150);
10888
10889 /* The pixel multiplier can only be updated once the
10890 * DPLL is enabled and the clocks are stable.
10891 *
10892 * So write it again.
10893 */
10894 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10895 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020010896 udelay(200);
10897}
10898
10899static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10900 struct intel_shared_dpll *pll)
10901{
10902 struct drm_device *dev = dev_priv->dev;
10903 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020010904
10905 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010906 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020010907 if (intel_crtc_to_shared_dpll(crtc) == pll)
10908 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10909 }
10910
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010911 I915_WRITE(PCH_DPLL(pll->id), 0);
10912 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020010913 udelay(200);
10914}
10915
Daniel Vetter46edb022013-06-05 13:34:12 +020010916static char *ibx_pch_dpll_names[] = {
10917 "PCH DPLL A",
10918 "PCH DPLL B",
10919};
10920
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010921static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010922{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010923 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010924 int i;
10925
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010926 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010927
Daniel Vettere72f9fb2013-06-05 13:34:06 +020010928 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020010929 dev_priv->shared_dplls[i].id = i;
10930 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010931 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020010932 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10933 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020010934 dev_priv->shared_dplls[i].get_hw_state =
10935 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010936 }
10937}
10938
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010939static void intel_shared_dpll_init(struct drm_device *dev)
10940{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010941 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010942
10943 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10944 ibx_pch_dpll_init(dev);
10945 else
10946 dev_priv->num_shared_dpll = 0;
10947
10948 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010949}
10950
Hannes Ederb358d0a2008-12-18 21:18:47 +010010951static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080010952{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010953 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080010954 struct intel_crtc *intel_crtc;
10955 int i;
10956
Daniel Vetter955382f2013-09-19 14:05:45 +020010957 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080010958 if (intel_crtc == NULL)
10959 return;
10960
10961 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10962
10963 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080010964 for (i = 0; i < 256; i++) {
10965 intel_crtc->lut_r[i] = i;
10966 intel_crtc->lut_g[i] = i;
10967 intel_crtc->lut_b[i] = i;
10968 }
10969
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020010970 /*
10971 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10972 * is hooked to plane B. Hence we want plane A feeding pipe B.
10973 */
Jesse Barnes80824002009-09-10 15:28:06 -070010974 intel_crtc->pipe = pipe;
10975 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010010976 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080010977 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010010978 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070010979 }
10980
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030010981 init_waitqueue_head(&intel_crtc->vbl_wait);
10982
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080010983 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10984 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10985 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10986 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10987
Jesse Barnes79e53942008-11-07 14:24:08 -080010988 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020010989
10990 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -080010991}
10992
Jesse Barnes752aa882013-10-31 18:55:49 +020010993enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10994{
10995 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020010996 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020010997
Daniel Vetter6e9f7982014-05-29 23:54:47 +020010998 WARN_ON(!mutex_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020010999
11000 if (!encoder)
11001 return INVALID_PIPE;
11002
11003 return to_intel_crtc(encoder->crtc)->pipe;
11004}
11005
Carl Worth08d7b3d2009-04-29 14:43:54 -070011006int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000011007 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070011008{
Carl Worth08d7b3d2009-04-29 14:43:54 -070011009 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +020011010 struct drm_mode_object *drmmode_obj;
11011 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011012
Daniel Vetter1cff8f62012-04-24 09:55:08 +020011013 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11014 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011015
Daniel Vetterc05422d2009-08-11 16:05:30 +020011016 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11017 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -070011018
Daniel Vetterc05422d2009-08-11 16:05:30 +020011019 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070011020 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030011021 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011022 }
11023
Daniel Vetterc05422d2009-08-11 16:05:30 +020011024 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11025 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011026
Daniel Vetterc05422d2009-08-11 16:05:30 +020011027 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011028}
11029
Daniel Vetter66a92782012-07-12 20:08:18 +020011030static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080011031{
Daniel Vetter66a92782012-07-12 20:08:18 +020011032 struct drm_device *dev = encoder->base.dev;
11033 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080011034 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080011035 int entry = 0;
11036
Daniel Vetter66a92782012-07-12 20:08:18 +020011037 list_for_each_entry(source_encoder,
11038 &dev->mode_config.encoder_list, base.head) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011039 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020011040 index_mask |= (1 << entry);
11041
Jesse Barnes79e53942008-11-07 14:24:08 -080011042 entry++;
11043 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010011044
Jesse Barnes79e53942008-11-07 14:24:08 -080011045 return index_mask;
11046}
11047
Chris Wilson4d302442010-12-14 19:21:29 +000011048static bool has_edp_a(struct drm_device *dev)
11049{
11050 struct drm_i915_private *dev_priv = dev->dev_private;
11051
11052 if (!IS_MOBILE(dev))
11053 return false;
11054
11055 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11056 return false;
11057
Damien Lespiaue3589902014-02-07 19:12:50 +000011058 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000011059 return false;
11060
11061 return true;
11062}
11063
Damien Lespiauba0fbca2014-01-08 14:18:23 +000011064const char *intel_output_name(int output)
11065{
11066 static const char *names[] = {
11067 [INTEL_OUTPUT_UNUSED] = "Unused",
11068 [INTEL_OUTPUT_ANALOG] = "Analog",
11069 [INTEL_OUTPUT_DVO] = "DVO",
11070 [INTEL_OUTPUT_SDVO] = "SDVO",
11071 [INTEL_OUTPUT_LVDS] = "LVDS",
11072 [INTEL_OUTPUT_TVOUT] = "TV",
11073 [INTEL_OUTPUT_HDMI] = "HDMI",
11074 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11075 [INTEL_OUTPUT_EDP] = "eDP",
11076 [INTEL_OUTPUT_DSI] = "DSI",
11077 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11078 };
11079
11080 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11081 return "Invalid";
11082
11083 return names[output];
11084}
11085
Jesse Barnes79e53942008-11-07 14:24:08 -080011086static void intel_setup_outputs(struct drm_device *dev)
11087{
Eric Anholt725e30a2009-01-22 13:01:02 -080011088 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010011089 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011090 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080011091
Daniel Vetterc9093352013-06-06 22:22:47 +020011092 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011093
Ville Syrjälä7895a812014-04-09 13:28:23 +030011094 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020011095 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011096
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011097 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030011098 int found;
11099
11100 /* Haswell uses DDI functions to detect digital outputs */
11101 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11102 /* DDI A only supports eDP */
11103 if (found)
11104 intel_ddi_init(dev, PORT_A);
11105
11106 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11107 * register */
11108 found = I915_READ(SFUSE_STRAP);
11109
11110 if (found & SFUSE_STRAP_DDIB_DETECTED)
11111 intel_ddi_init(dev, PORT_B);
11112 if (found & SFUSE_STRAP_DDIC_DETECTED)
11113 intel_ddi_init(dev, PORT_C);
11114 if (found & SFUSE_STRAP_DDID_DETECTED)
11115 intel_ddi_init(dev, PORT_D);
11116 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011117 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020011118 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020011119
11120 if (has_edp_a(dev))
11121 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011122
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011123 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080011124 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010011125 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011126 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011127 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011128 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011129 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011130 }
11131
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011132 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011133 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011134
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011135 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011136 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011137
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011138 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011139 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011140
Daniel Vetter270b3042012-10-27 15:52:05 +020011141 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011142 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070011143 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030011144 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11145 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11146 PORT_B);
11147 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11148 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11149 }
11150
Jesse Barnes6f6005a2013-08-09 09:34:35 -070011151 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11152 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11153 PORT_C);
11154 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020011155 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Jesse Barnes6f6005a2013-08-09 09:34:35 -070011156 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053011157
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030011158 if (IS_CHERRYVIEW(dev)) {
11159 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11160 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11161 PORT_D);
11162 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11163 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11164 }
11165 }
11166
Jani Nikula3cfca972013-08-27 15:12:26 +030011167 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080011168 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080011169 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080011170
Paulo Zanonie2debe92013-02-18 19:00:27 -030011171 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011172 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011173 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011174 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11175 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011176 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011177 }
Ma Ling27185ae2009-08-24 13:50:23 +080011178
Imre Deake7281ea2013-05-08 13:14:08 +030011179 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011180 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080011181 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040011182
11183 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040011184
Paulo Zanonie2debe92013-02-18 19:00:27 -030011185 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011186 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011187 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011188 }
Ma Ling27185ae2009-08-24 13:50:23 +080011189
Paulo Zanonie2debe92013-02-18 19:00:27 -030011190 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080011191
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011192 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11193 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011194 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011195 }
Imre Deake7281ea2013-05-08 13:14:08 +030011196 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011197 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080011198 }
Ma Ling27185ae2009-08-24 13:50:23 +080011199
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011200 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030011201 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011202 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070011203 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080011204 intel_dvo_init(dev);
11205
Zhenyu Wang103a1962009-11-27 11:44:36 +080011206 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080011207 intel_tv_init(dev);
11208
Chris Wilson4ef69c72010-09-09 15:14:28 +010011209 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11210 encoder->base.possible_crtcs = encoder->crtc_mask;
11211 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020011212 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080011213 }
Chris Wilson47356eb2011-01-11 17:06:04 +000011214
Paulo Zanonidde86e22012-12-01 12:04:25 -020011215 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020011216
11217 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011218}
11219
11220static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11221{
11222 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080011223
Daniel Vetteref2d6332014-02-10 18:00:38 +010011224 drm_framebuffer_cleanup(fb);
11225 WARN_ON(!intel_fb->obj->framebuffer_references--);
11226 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080011227 kfree(intel_fb);
11228}
11229
11230static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000011231 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080011232 unsigned int *handle)
11233{
11234 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000011235 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080011236
Chris Wilson05394f32010-11-08 19:18:58 +000011237 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080011238}
11239
11240static const struct drm_framebuffer_funcs intel_fb_funcs = {
11241 .destroy = intel_user_framebuffer_destroy,
11242 .create_handle = intel_user_framebuffer_create_handle,
11243};
11244
Daniel Vetterb5ea6422014-03-02 21:18:00 +010011245static int intel_framebuffer_init(struct drm_device *dev,
11246 struct intel_framebuffer *intel_fb,
11247 struct drm_mode_fb_cmd2 *mode_cmd,
11248 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080011249{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080011250 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010011251 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080011252 int ret;
11253
Daniel Vetterdd4916c2013-10-09 21:23:51 +020011254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11255
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011256 if (obj->tiling_mode == I915_TILING_Y) {
11257 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010011258 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011259 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011260
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011261 if (mode_cmd->pitches[0] & 63) {
11262 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11263 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010011264 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011265 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011266
Chris Wilsona35cdaa2013-06-25 17:26:45 +010011267 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11268 pitch_limit = 32*1024;
11269 } else if (INTEL_INFO(dev)->gen >= 4) {
11270 if (obj->tiling_mode)
11271 pitch_limit = 16*1024;
11272 else
11273 pitch_limit = 32*1024;
11274 } else if (INTEL_INFO(dev)->gen >= 3) {
11275 if (obj->tiling_mode)
11276 pitch_limit = 8*1024;
11277 else
11278 pitch_limit = 16*1024;
11279 } else
11280 /* XXX DSPC is limited to 4k tiled */
11281 pitch_limit = 8*1024;
11282
11283 if (mode_cmd->pitches[0] > pitch_limit) {
11284 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11285 obj->tiling_mode ? "tiled" : "linear",
11286 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011287 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011288 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011289
11290 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011291 mode_cmd->pitches[0] != obj->stride) {
11292 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11293 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011294 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011295 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011296
Ville Syrjälä57779d02012-10-31 17:50:14 +020011297 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011298 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020011299 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020011300 case DRM_FORMAT_RGB565:
11301 case DRM_FORMAT_XRGB8888:
11302 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020011303 break;
11304 case DRM_FORMAT_XRGB1555:
11305 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011306 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011307 DRM_DEBUG("unsupported pixel format: %s\n",
11308 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011309 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011310 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020011311 break;
11312 case DRM_FORMAT_XBGR8888:
11313 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020011314 case DRM_FORMAT_XRGB2101010:
11315 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020011316 case DRM_FORMAT_XBGR2101010:
11317 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011318 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011319 DRM_DEBUG("unsupported pixel format: %s\n",
11320 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011321 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011322 }
Jesse Barnesb5626742011-06-24 12:19:27 -070011323 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020011324 case DRM_FORMAT_YUYV:
11325 case DRM_FORMAT_UYVY:
11326 case DRM_FORMAT_YVYU:
11327 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011328 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011329 DRM_DEBUG("unsupported pixel format: %s\n",
11330 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011331 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011332 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011333 break;
11334 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011335 DRM_DEBUG("unsupported pixel format: %s\n",
11336 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010011337 return -EINVAL;
11338 }
11339
Ville Syrjälä90f9a332012-10-31 17:50:19 +020011340 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11341 if (mode_cmd->offsets[0] != 0)
11342 return -EINVAL;
11343
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080011344 aligned_height = intel_align_height(dev, mode_cmd->height,
11345 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020011346 /* FIXME drm helper for size checks (especially planar formats)? */
11347 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11348 return -EINVAL;
11349
Daniel Vetterc7d73f62012-12-13 23:38:38 +010011350 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11351 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020011352 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010011353
Jesse Barnes79e53942008-11-07 14:24:08 -080011354 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11355 if (ret) {
11356 DRM_ERROR("framebuffer init failed %d\n", ret);
11357 return ret;
11358 }
11359
Jesse Barnes79e53942008-11-07 14:24:08 -080011360 return 0;
11361}
11362
Jesse Barnes79e53942008-11-07 14:24:08 -080011363static struct drm_framebuffer *
11364intel_user_framebuffer_create(struct drm_device *dev,
11365 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011366 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080011367{
Chris Wilson05394f32010-11-08 19:18:58 +000011368 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080011369
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011370 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11371 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000011372 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010011373 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080011374
Chris Wilsond2dff872011-04-19 08:36:26 +010011375 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080011376}
11377
Daniel Vetter4520f532013-10-09 09:18:51 +020011378#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020011379static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020011380{
11381}
11382#endif
11383
Jesse Barnes79e53942008-11-07 14:24:08 -080011384static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080011385 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020011386 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080011387};
11388
Jesse Barnese70236a2009-09-21 10:42:27 -070011389/* Set up chip specific display functions */
11390static void intel_init_display(struct drm_device *dev)
11391{
11392 struct drm_i915_private *dev_priv = dev->dev_private;
11393
Daniel Vetteree9300b2013-06-03 22:40:22 +020011394 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11395 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030011396 else if (IS_CHERRYVIEW(dev))
11397 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020011398 else if (IS_VALLEYVIEW(dev))
11399 dev_priv->display.find_dpll = vlv_find_best_dpll;
11400 else if (IS_PINEVIEW(dev))
11401 dev_priv->display.find_dpll = pnv_find_best_dpll;
11402 else
11403 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11404
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011405 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011406 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080011407 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030011408 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020011409 dev_priv->display.crtc_enable = haswell_crtc_enable;
11410 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -030011411 dev_priv->display.off = haswell_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011412 dev_priv->display.update_primary_plane =
11413 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030011414 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011415 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080011416 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070011417 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020011418 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11419 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011420 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011421 dev_priv->display.update_primary_plane =
11422 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070011423 } else if (IS_VALLEYVIEW(dev)) {
11424 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080011425 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Jesse Barnes89b667f2013-04-18 14:51:36 -070011426 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11427 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11428 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11429 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011430 dev_priv->display.update_primary_plane =
11431 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070011432 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011433 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080011434 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070011435 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020011436 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11437 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011438 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011439 dev_priv->display.update_primary_plane =
11440 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070011441 }
Jesse Barnese70236a2009-09-21 10:42:27 -070011442
Jesse Barnese70236a2009-09-21 10:42:27 -070011443 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070011444 if (IS_VALLEYVIEW(dev))
11445 dev_priv->display.get_display_clock_speed =
11446 valleyview_get_display_clock_speed;
11447 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070011448 dev_priv->display.get_display_clock_speed =
11449 i945_get_display_clock_speed;
11450 else if (IS_I915G(dev))
11451 dev_priv->display.get_display_clock_speed =
11452 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020011453 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070011454 dev_priv->display.get_display_clock_speed =
11455 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020011456 else if (IS_PINEVIEW(dev))
11457 dev_priv->display.get_display_clock_speed =
11458 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070011459 else if (IS_I915GM(dev))
11460 dev_priv->display.get_display_clock_speed =
11461 i915gm_get_display_clock_speed;
11462 else if (IS_I865G(dev))
11463 dev_priv->display.get_display_clock_speed =
11464 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020011465 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070011466 dev_priv->display.get_display_clock_speed =
11467 i855_get_display_clock_speed;
11468 else /* 852, 830 */
11469 dev_priv->display.get_display_clock_speed =
11470 i830_get_display_clock_speed;
11471
Zhenyu Wang7f8a8562010-04-01 13:07:53 +080011472 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +010011473 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070011474 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011475 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +080011476 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070011477 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011478 dev_priv->display.write_eld = ironlake_write_eld;
Paulo Zanoni9a952a02014-03-07 20:12:34 -030011479 dev_priv->display.modeset_global_resources =
11480 snb_modeset_global_resources;
Jesse Barnes357555c2011-04-28 15:09:55 -070011481 } else if (IS_IVYBRIDGE(dev)) {
11482 /* FIXME: detect B0+ stepping and use auto training */
11483 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011484 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +020011485 dev_priv->display.modeset_global_resources =
11486 ivb_modeset_global_resources;
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070011487 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -030011488 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +080011489 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -020011490 dev_priv->display.modeset_global_resources =
11491 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -020011492 }
Jesse Barnes6067aae2011-04-28 15:04:31 -070011493 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080011494 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnes30a970c2013-11-04 13:48:12 -080011495 } else if (IS_VALLEYVIEW(dev)) {
11496 dev_priv->display.modeset_global_resources =
11497 valleyview_modeset_global_resources;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -040011498 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -070011499 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011500
11501 /* Default just returns -ENODEV to indicate unsupported */
11502 dev_priv->display.queue_flip = intel_default_queue_flip;
11503
11504 switch (INTEL_INFO(dev)->gen) {
11505 case 2:
11506 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11507 break;
11508
11509 case 3:
11510 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11511 break;
11512
11513 case 4:
11514 case 5:
11515 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11516 break;
11517
11518 case 6:
11519 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11520 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011521 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070011522 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011523 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11524 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011525 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020011526
11527 intel_panel_init_backlight_funcs(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070011528}
11529
Jesse Barnesb690e962010-07-19 13:53:12 -070011530/*
11531 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11532 * resume, or other times. This quirk makes sure that's the case for
11533 * affected systems.
11534 */
Akshay Joshi0206e352011-08-16 15:34:10 -040011535static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070011536{
11537 struct drm_i915_private *dev_priv = dev->dev_private;
11538
11539 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011540 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070011541}
11542
Keith Packard435793d2011-07-12 14:56:22 -070011543/*
11544 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11545 */
11546static void quirk_ssc_force_disable(struct drm_device *dev)
11547{
11548 struct drm_i915_private *dev_priv = dev->dev_private;
11549 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011550 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070011551}
11552
Carsten Emde4dca20e2012-03-15 15:56:26 +010011553/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010011554 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11555 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010011556 */
11557static void quirk_invert_brightness(struct drm_device *dev)
11558{
11559 struct drm_i915_private *dev_priv = dev->dev_private;
11560 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011561 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070011562}
11563
11564struct intel_quirk {
11565 int device;
11566 int subsystem_vendor;
11567 int subsystem_device;
11568 void (*hook)(struct drm_device *dev);
11569};
11570
Egbert Eich5f85f1762012-10-14 15:46:38 +020011571/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11572struct intel_dmi_quirk {
11573 void (*hook)(struct drm_device *dev);
11574 const struct dmi_system_id (*dmi_id_list)[];
11575};
11576
11577static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11578{
11579 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11580 return 1;
11581}
11582
11583static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11584 {
11585 .dmi_id_list = &(const struct dmi_system_id[]) {
11586 {
11587 .callback = intel_dmi_reverse_brightness,
11588 .ident = "NCR Corporation",
11589 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11590 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11591 },
11592 },
11593 { } /* terminating entry */
11594 },
11595 .hook = quirk_invert_brightness,
11596 },
11597};
11598
Ben Widawskyc43b5632012-04-16 14:07:40 -070011599static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070011600 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040011601 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070011602
Jesse Barnesb690e962010-07-19 13:53:12 -070011603 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11604 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11605
Jesse Barnesb690e962010-07-19 13:53:12 -070011606 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11607 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11608
Chris Wilsona4945f92013-10-08 11:16:59 +010011609 /* 830 needs to leave pipe A & dpll A up */
Daniel Vetterdcdaed62012-08-12 21:19:34 +020011610 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -070011611
11612 /* Lenovo U160 cannot use SSC on LVDS */
11613 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020011614
11615 /* Sony Vaio Y cannot use SSC on LVDS */
11616 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010011617
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010011618 /* Acer Aspire 5734Z must invert backlight brightness */
11619 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11620
11621 /* Acer/eMachines G725 */
11622 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11623
11624 /* Acer/eMachines e725 */
11625 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11626
11627 /* Acer/Packard Bell NCL20 */
11628 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11629
11630 /* Acer Aspire 4736Z */
11631 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020011632
11633 /* Acer Aspire 5336 */
11634 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -070011635};
11636
11637static void intel_init_quirks(struct drm_device *dev)
11638{
11639 struct pci_dev *d = dev->pdev;
11640 int i;
11641
11642 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11643 struct intel_quirk *q = &intel_quirks[i];
11644
11645 if (d->device == q->device &&
11646 (d->subsystem_vendor == q->subsystem_vendor ||
11647 q->subsystem_vendor == PCI_ANY_ID) &&
11648 (d->subsystem_device == q->subsystem_device ||
11649 q->subsystem_device == PCI_ANY_ID))
11650 q->hook(dev);
11651 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020011652 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11653 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11654 intel_dmi_quirks[i].hook(dev);
11655 }
Jesse Barnesb690e962010-07-19 13:53:12 -070011656}
11657
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011658/* Disable the VGA plane that we never use */
11659static void i915_disable_vga(struct drm_device *dev)
11660{
11661 struct drm_i915_private *dev_priv = dev->dev_private;
11662 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020011663 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011664
Ville Syrjälä2b37c612014-01-22 21:32:38 +020011665 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011666 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070011667 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011668 sr1 = inb(VGA_SR_DATA);
11669 outb(sr1 | 1<<5, VGA_SR_DATA);
11670 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11671 udelay(300);
11672
11673 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11674 POSTING_READ(vga_reg);
11675}
11676
Daniel Vetterf8175862012-04-10 15:50:11 +020011677void intel_modeset_init_hw(struct drm_device *dev)
11678{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030011679 intel_prepare_ddi(dev);
11680
Daniel Vetterf8175862012-04-10 15:50:11 +020011681 intel_init_clock_gating(dev);
11682
Jesse Barnes5382f5f352013-12-16 16:34:24 -080011683 intel_reset_dpio(dev);
Jesse Barnes40e9cf62013-10-03 11:35:46 -070011684
Daniel Vetter8090c6b2012-06-24 16:42:32 +020011685 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020011686}
11687
Imre Deak7d708ee2013-04-17 14:04:50 +030011688void intel_modeset_suspend_hw(struct drm_device *dev)
11689{
11690 intel_suspend_hw(dev);
11691}
11692
Jesse Barnes79e53942008-11-07 14:24:08 -080011693void intel_modeset_init(struct drm_device *dev)
11694{
Jesse Barnes652c3932009-08-17 13:31:43 -070011695 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000011696 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000011697 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080011698 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080011699
11700 drm_mode_config_init(dev);
11701
11702 dev->mode_config.min_width = 0;
11703 dev->mode_config.min_height = 0;
11704
Dave Airlie019d96c2011-09-29 16:20:42 +010011705 dev->mode_config.preferred_depth = 24;
11706 dev->mode_config.prefer_shadow = 1;
11707
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020011708 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080011709
Jesse Barnesb690e962010-07-19 13:53:12 -070011710 intel_init_quirks(dev);
11711
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030011712 intel_init_pm(dev);
11713
Ben Widawskye3c74752013-04-05 13:12:39 -070011714 if (INTEL_INFO(dev)->num_pipes == 0)
11715 return;
11716
Jesse Barnese70236a2009-09-21 10:42:27 -070011717 intel_init_display(dev);
11718
Chris Wilsona6c45cf2010-09-17 00:32:17 +010011719 if (IS_GEN2(dev)) {
11720 dev->mode_config.max_width = 2048;
11721 dev->mode_config.max_height = 2048;
11722 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070011723 dev->mode_config.max_width = 4096;
11724 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080011725 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010011726 dev->mode_config.max_width = 8192;
11727 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080011728 }
Damien Lespiau068be562014-03-28 14:17:49 +000011729
11730 if (IS_GEN2(dev)) {
11731 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11732 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11733 } else {
11734 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11735 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11736 }
11737
Ben Widawsky5d4545a2013-01-17 12:45:15 -080011738 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080011739
Zhao Yakui28c97732009-10-09 11:39:41 +080011740 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011741 INTEL_INFO(dev)->num_pipes,
11742 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080011743
Damien Lespiau8cc87b72014-03-03 17:31:44 +000011744 for_each_pipe(pipe) {
11745 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000011746 for_each_sprite(pipe, sprite) {
11747 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070011748 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030011749 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000011750 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070011751 }
Jesse Barnes79e53942008-11-07 14:24:08 -080011752 }
11753
Jesse Barnesf42bb702013-12-16 16:34:23 -080011754 intel_init_dpio(dev);
Jesse Barnes5382f5f352013-12-16 16:34:24 -080011755 intel_reset_dpio(dev);
Jesse Barnesf42bb702013-12-16 16:34:23 -080011756
Paulo Zanoni79f689a2012-10-05 12:05:52 -030011757 intel_cpu_pll_init(dev);
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011758 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011759
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011760 /* Just disable it once at startup */
11761 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011762 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000011763
11764 /* Just in case the BIOS is doing something questionable. */
11765 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080011766
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011767 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080011768 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011769 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080011770
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011771 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080011772 if (!crtc->active)
11773 continue;
11774
Jesse Barnes46f297f2014-03-07 08:57:48 -080011775 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080011776 * Note that reserving the BIOS fb up front prevents us
11777 * from stuffing other stolen allocations like the ring
11778 * on top. This prevents some ugliness at boot time, and
11779 * can even allow for smooth boot transitions if the BIOS
11780 * fb is large enough for the active pipe configuration.
11781 */
11782 if (dev_priv->display.get_plane_config) {
11783 dev_priv->display.get_plane_config(crtc,
11784 &crtc->plane_config);
11785 /*
11786 * If the fb is shared between multiple heads, we'll
11787 * just get the first one.
11788 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080011789 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080011790 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080011791 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010011792}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080011793
Daniel Vetter24929352012-07-02 20:28:59 +020011794static void
11795intel_connector_break_all_links(struct intel_connector *connector)
11796{
11797 connector->base.dpms = DRM_MODE_DPMS_OFF;
11798 connector->base.encoder = NULL;
11799 connector->encoder->connectors_active = false;
11800 connector->encoder->base.crtc = NULL;
11801}
11802
Daniel Vetter7fad7982012-07-04 17:51:47 +020011803static void intel_enable_pipe_a(struct drm_device *dev)
11804{
11805 struct intel_connector *connector;
11806 struct drm_connector *crt = NULL;
11807 struct intel_load_detect_pipe load_detect_temp;
11808
11809 /* We can't just switch on the pipe A, we need to set things up with a
11810 * proper mode and output configuration. As a gross hack, enable pipe A
11811 * by enabling the load detect pipe once. */
11812 list_for_each_entry(connector,
11813 &dev->mode_config.connector_list,
11814 base.head) {
11815 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11816 crt = &connector->base;
11817 break;
11818 }
11819 }
11820
11821 if (!crt)
11822 return;
11823
11824 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11825 intel_release_load_detect_pipe(crt, &load_detect_temp);
11826
11827
11828}
11829
Daniel Vetterfa555832012-10-10 23:14:00 +020011830static bool
11831intel_check_plane_mapping(struct intel_crtc *crtc)
11832{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011833 struct drm_device *dev = crtc->base.dev;
11834 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020011835 u32 reg, val;
11836
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011837 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020011838 return true;
11839
11840 reg = DSPCNTR(!crtc->plane);
11841 val = I915_READ(reg);
11842
11843 if ((val & DISPLAY_PLANE_ENABLE) &&
11844 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11845 return false;
11846
11847 return true;
11848}
11849
Daniel Vetter24929352012-07-02 20:28:59 +020011850static void intel_sanitize_crtc(struct intel_crtc *crtc)
11851{
11852 struct drm_device *dev = crtc->base.dev;
11853 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020011854 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020011855
Daniel Vetter24929352012-07-02 20:28:59 +020011856 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020011857 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020011858 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11859
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030011860 /* restore vblank interrupts to correct state */
11861 if (crtc->active)
11862 drm_vblank_on(dev, crtc->pipe);
11863 else
11864 drm_vblank_off(dev, crtc->pipe);
11865
Daniel Vetter24929352012-07-02 20:28:59 +020011866 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020011867 * disable the crtc (and hence change the state) if it is wrong. Note
11868 * that gen4+ has a fixed plane -> pipe mapping. */
11869 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020011870 struct intel_connector *connector;
11871 bool plane;
11872
Daniel Vetter24929352012-07-02 20:28:59 +020011873 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11874 crtc->base.base.id);
11875
11876 /* Pipe has the wrong plane attached and the plane is active.
11877 * Temporarily change the plane mapping and disable everything
11878 * ... */
11879 plane = crtc->plane;
11880 crtc->plane = !plane;
11881 dev_priv->display.crtc_disable(&crtc->base);
11882 crtc->plane = plane;
11883
11884 /* ... and break all links. */
11885 list_for_each_entry(connector, &dev->mode_config.connector_list,
11886 base.head) {
11887 if (connector->encoder->base.crtc != &crtc->base)
11888 continue;
11889
11890 intel_connector_break_all_links(connector);
11891 }
11892
11893 WARN_ON(crtc->active);
11894 crtc->base.enabled = false;
11895 }
Daniel Vetter24929352012-07-02 20:28:59 +020011896
Daniel Vetter7fad7982012-07-04 17:51:47 +020011897 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11898 crtc->pipe == PIPE_A && !crtc->active) {
11899 /* BIOS forgot to enable pipe A, this mostly happens after
11900 * resume. Force-enable the pipe to fix this, the update_dpms
11901 * call below we restore the pipe to the right state, but leave
11902 * the required bits on. */
11903 intel_enable_pipe_a(dev);
11904 }
11905
Daniel Vetter24929352012-07-02 20:28:59 +020011906 /* Adjust the state of the output pipe according to whether we
11907 * have active connectors/encoders. */
11908 intel_crtc_update_dpms(&crtc->base);
11909
11910 if (crtc->active != crtc->base.enabled) {
11911 struct intel_encoder *encoder;
11912
11913 /* This can happen either due to bugs in the get_hw_state
11914 * functions or because the pipe is force-enabled due to the
11915 * pipe A quirk. */
11916 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11917 crtc->base.base.id,
11918 crtc->base.enabled ? "enabled" : "disabled",
11919 crtc->active ? "enabled" : "disabled");
11920
11921 crtc->base.enabled = crtc->active;
11922
11923 /* Because we only establish the connector -> encoder ->
11924 * crtc links if something is active, this means the
11925 * crtc is now deactivated. Break the links. connector
11926 * -> encoder links are only establish when things are
11927 * actually up, hence no need to break them. */
11928 WARN_ON(crtc->active);
11929
11930 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11931 WARN_ON(encoder->connectors_active);
11932 encoder->base.crtc = NULL;
11933 }
11934 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020011935
11936 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010011937 /*
11938 * We start out with underrun reporting disabled to avoid races.
11939 * For correct bookkeeping mark this on active crtcs.
11940 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020011941 * Also on gmch platforms we dont have any hardware bits to
11942 * disable the underrun reporting. Which means we need to start
11943 * out with underrun reporting disabled also on inactive pipes,
11944 * since otherwise we'll complain about the garbage we read when
11945 * e.g. coming up after runtime pm.
11946 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010011947 * No protection against concurrent access is required - at
11948 * worst a fifo underrun happens which also sets this to false.
11949 */
11950 crtc->cpu_fifo_underrun_disabled = true;
11951 crtc->pch_fifo_underrun_disabled = true;
Ville Syrjälä80715b22014-05-15 20:23:23 +030011952
11953 update_scanline_offset(crtc);
Daniel Vetter4cc31482014-03-24 00:01:41 +010011954 }
Daniel Vetter24929352012-07-02 20:28:59 +020011955}
11956
11957static void intel_sanitize_encoder(struct intel_encoder *encoder)
11958{
11959 struct intel_connector *connector;
11960 struct drm_device *dev = encoder->base.dev;
11961
11962 /* We need to check both for a crtc link (meaning that the
11963 * encoder is active and trying to read from a pipe) and the
11964 * pipe itself being active. */
11965 bool has_active_crtc = encoder->base.crtc &&
11966 to_intel_crtc(encoder->base.crtc)->active;
11967
11968 if (encoder->connectors_active && !has_active_crtc) {
11969 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11970 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030011971 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020011972
11973 /* Connector is active, but has no active pipe. This is
11974 * fallout from our resume register restoring. Disable
11975 * the encoder manually again. */
11976 if (encoder->base.crtc) {
11977 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11978 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030011979 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020011980 encoder->disable(encoder);
11981 }
11982
11983 /* Inconsistent output/port/pipe state happens presumably due to
11984 * a bug in one of the get_hw_state functions. Or someplace else
11985 * in our code, like the register restore mess on resume. Clamp
11986 * things to off as a safer default. */
11987 list_for_each_entry(connector,
11988 &dev->mode_config.connector_list,
11989 base.head) {
11990 if (connector->encoder != encoder)
11991 continue;
11992
11993 intel_connector_break_all_links(connector);
11994 }
11995 }
11996 /* Enabled encoders without active connectors will be fixed in
11997 * the crtc fixup. */
11998}
11999
Imre Deak04098752014-02-18 00:02:16 +020012000void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012001{
12002 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012003 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012004
Imre Deak04098752014-02-18 00:02:16 +020012005 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12006 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12007 i915_disable_vga(dev);
12008 }
12009}
12010
12011void i915_redisable_vga(struct drm_device *dev)
12012{
12013 struct drm_i915_private *dev_priv = dev->dev_private;
12014
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030012015 /* This function can be called both from intel_modeset_setup_hw_state or
12016 * at a very early point in our resume sequence, where the power well
12017 * structures are not yet restored. Since this function is at a very
12018 * paranoid "someone might have enabled VGA while we were not looking"
12019 * level, just check if the power well is enabled instead of trying to
12020 * follow the "don't touch the power well if we don't need it" policy
12021 * the rest of the driver uses. */
Imre Deak04098752014-02-18 00:02:16 +020012022 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030012023 return;
12024
Imre Deak04098752014-02-18 00:02:16 +020012025 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012026}
12027
Ville Syrjälä98ec7732014-04-30 17:43:01 +030012028static bool primary_get_hw_state(struct intel_crtc *crtc)
12029{
12030 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12031
12032 if (!crtc->active)
12033 return false;
12034
12035 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12036}
12037
Daniel Vetter30e984d2013-06-05 13:34:17 +020012038static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020012039{
12040 struct drm_i915_private *dev_priv = dev->dev_private;
12041 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020012042 struct intel_crtc *crtc;
12043 struct intel_encoder *encoder;
12044 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020012045 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020012046
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012047 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010012048 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020012049
Daniel Vetter99535992014-04-13 12:00:33 +020012050 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12051
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012052 crtc->active = dev_priv->display.get_pipe_config(crtc,
12053 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020012054
12055 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030012056 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020012057
12058 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12059 crtc->base.base.id,
12060 crtc->active ? "enabled" : "disabled");
12061 }
12062
Daniel Vetter53589012013-06-05 13:34:16 +020012063 /* FIXME: Smash this into the new shared dpll infrastructure. */
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012064 if (HAS_DDI(dev))
Paulo Zanoni6441ab52012-10-05 12:05:58 -030012065 intel_ddi_setup_hw_pll_state(dev);
12066
Daniel Vetter53589012013-06-05 13:34:16 +020012067 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12068 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12069
12070 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12071 pll->active = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012072 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020012073 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12074 pll->active++;
12075 }
12076 pll->refcount = pll->active;
12077
Daniel Vetter35c95372013-07-17 06:55:04 +020012078 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12079 pll->name, pll->refcount, pll->on);
Daniel Vetter53589012013-06-05 13:34:16 +020012080 }
12081
Daniel Vetter24929352012-07-02 20:28:59 +020012082 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12083 base.head) {
12084 pipe = 0;
12085
12086 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070012087 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12088 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010012089 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020012090 } else {
12091 encoder->base.crtc = NULL;
12092 }
12093
12094 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010012095 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020012096 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012097 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020012098 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010012099 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020012100 }
12101
12102 list_for_each_entry(connector, &dev->mode_config.connector_list,
12103 base.head) {
12104 if (connector->get_hw_state(connector)) {
12105 connector->base.dpms = DRM_MODE_DPMS_ON;
12106 connector->encoder->connectors_active = true;
12107 connector->base.encoder = &connector->encoder->base;
12108 } else {
12109 connector->base.dpms = DRM_MODE_DPMS_OFF;
12110 connector->base.encoder = NULL;
12111 }
12112 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12113 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030012114 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020012115 connector->base.encoder ? "enabled" : "disabled");
12116 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020012117}
12118
12119/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12120 * and i915 state tracking structures. */
12121void intel_modeset_setup_hw_state(struct drm_device *dev,
12122 bool force_restore)
12123{
12124 struct drm_i915_private *dev_priv = dev->dev_private;
12125 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020012126 struct intel_crtc *crtc;
12127 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020012128 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020012129
12130 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020012131
Jesse Barnesbabea612013-06-26 18:57:38 +030012132 /*
12133 * Now that we have the config, copy it to each CRTC struct
12134 * Note that this could go away if we move to using crtc_config
12135 * checking everywhere.
12136 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012137 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020012138 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080012139 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030012140 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12141 crtc->base.base.id);
12142 drm_mode_debug_printmodeline(&crtc->base.mode);
12143 }
12144 }
12145
Daniel Vetter24929352012-07-02 20:28:59 +020012146 /* HW state is read out, now we need to sanitize this mess. */
12147 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12148 base.head) {
12149 intel_sanitize_encoder(encoder);
12150 }
12151
12152 for_each_pipe(pipe) {
12153 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12154 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020012155 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020012156 }
Daniel Vetter9a935852012-07-05 22:34:27 +020012157
Daniel Vetter35c95372013-07-17 06:55:04 +020012158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12159 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12160
12161 if (!pll->on || pll->active)
12162 continue;
12163
12164 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12165
12166 pll->disable(dev_priv, pll);
12167 pll->on = false;
12168 }
12169
Ville Syrjälä96f90c52013-12-05 15:51:38 +020012170 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030012171 ilk_wm_get_hw_state(dev);
12172
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012173 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030012174 i915_redisable_vga(dev);
12175
Daniel Vetterf30da182013-04-11 20:22:50 +020012176 /*
12177 * We need to use raw interfaces for restoring state to avoid
12178 * checking (bogus) intermediate states.
12179 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012180 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070012181 struct drm_crtc *crtc =
12182 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020012183
12184 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
Matt Roperf4510a22014-04-01 15:22:40 -070012185 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012186 }
12187 } else {
12188 intel_modeset_update_staged_output_state(dev);
12189 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012190
12191 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010012192}
12193
12194void intel_modeset_gem_init(struct drm_device *dev)
12195{
Jesse Barnes484b41d2014-03-07 08:57:55 -080012196 struct drm_crtc *c;
12197 struct intel_framebuffer *fb;
12198
Imre Deakae484342014-03-31 15:10:44 +030012199 mutex_lock(&dev->struct_mutex);
12200 intel_init_gt_powersave(dev);
12201 mutex_unlock(&dev->struct_mutex);
12202
Chris Wilson1833b132012-05-09 11:56:28 +010012203 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020012204
12205 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080012206
12207 /*
12208 * Make sure any fbs we allocated at startup are properly
12209 * pinned & fenced. When we do the allocation it's too early
12210 * for this.
12211 */
12212 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010012213 for_each_crtc(dev, c) {
Dave Airlie66e514c2014-04-03 07:51:54 +100012214 if (!c->primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -080012215 continue;
12216
Dave Airlie66e514c2014-04-03 07:51:54 +100012217 fb = to_intel_framebuffer(c->primary->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -080012218 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12219 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12220 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100012221 drm_framebuffer_unreference(c->primary->fb);
12222 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080012223 }
12224 }
12225 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012226}
12227
Imre Deak4932e2c2014-02-11 17:12:48 +020012228void intel_connector_unregister(struct intel_connector *intel_connector)
12229{
12230 struct drm_connector *connector = &intel_connector->base;
12231
12232 intel_panel_destroy_backlight(connector);
12233 drm_sysfs_connector_remove(connector);
12234}
12235
Jesse Barnes79e53942008-11-07 14:24:08 -080012236void intel_modeset_cleanup(struct drm_device *dev)
12237{
Jesse Barnes652c3932009-08-17 13:31:43 -070012238 struct drm_i915_private *dev_priv = dev->dev_private;
12239 struct drm_crtc *crtc;
Paulo Zanonid9255d52013-09-26 20:05:59 -030012240 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070012241
Daniel Vetterfd0c0642013-04-24 11:13:35 +020012242 /*
12243 * Interrupts and polling as the first thing to avoid creating havoc.
12244 * Too much stuff here (turning of rps, connectors, ...) would
12245 * experience fancy races otherwise.
12246 */
12247 drm_irq_uninstall(dev);
12248 cancel_work_sync(&dev_priv->hotplug_work);
12249 /*
12250 * Due to the hpd irq storm handling the hotplug work can re-arm the
12251 * poll handlers. Hence disable polling after hpd handling is shut down.
12252 */
Keith Packardf87ea762010-10-03 19:36:26 -070012253 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020012254
Jesse Barnes652c3932009-08-17 13:31:43 -070012255 mutex_lock(&dev->struct_mutex);
12256
Jesse Barnes723bfd72010-10-07 16:01:13 -070012257 intel_unregister_dsm_handler();
12258
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010012259 for_each_crtc(dev, crtc) {
Jesse Barnes652c3932009-08-17 13:31:43 -070012260 /* Skip inactive CRTCs */
Matt Roperf4510a22014-04-01 15:22:40 -070012261 if (!crtc->primary->fb)
Jesse Barnes652c3932009-08-17 13:31:43 -070012262 continue;
12263
Daniel Vetter3dec0092010-08-20 21:40:52 +020012264 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -070012265 }
12266
Chris Wilson973d04f2011-07-08 12:22:37 +010012267 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012268
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012269 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000012270
Daniel Vetter930ebb42012-06-29 23:32:16 +020012271 ironlake_teardown_rc6(dev);
12272
Kristian Høgsberg69341a52009-11-11 12:19:17 -050012273 mutex_unlock(&dev->struct_mutex);
12274
Chris Wilson1630fe72011-07-08 12:22:42 +010012275 /* flush any delayed tasks or pending work */
12276 flush_scheduled_work();
12277
Jani Nikuladb31af12013-11-08 16:48:53 +020012278 /* destroy the backlight and sysfs files before encoders/connectors */
12279 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020012280 struct intel_connector *intel_connector;
12281
12282 intel_connector = to_intel_connector(connector);
12283 intel_connector->unregister(intel_connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020012284 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030012285
Jesse Barnes79e53942008-11-07 14:24:08 -080012286 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010012287
12288 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030012289
12290 mutex_lock(&dev->struct_mutex);
12291 intel_cleanup_gt_powersave(dev);
12292 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012293}
12294
Dave Airlie28d52042009-09-21 14:33:58 +100012295/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080012296 * Return which encoder is currently attached for connector.
12297 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010012298struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080012299{
Chris Wilsondf0e9242010-09-09 16:20:55 +010012300 return &intel_attached_encoder(connector)->base;
12301}
Jesse Barnes79e53942008-11-07 14:24:08 -080012302
Chris Wilsondf0e9242010-09-09 16:20:55 +010012303void intel_connector_attach_encoder(struct intel_connector *connector,
12304 struct intel_encoder *encoder)
12305{
12306 connector->encoder = encoder;
12307 drm_mode_connector_attach_encoder(&connector->base,
12308 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080012309}
Dave Airlie28d52042009-09-21 14:33:58 +100012310
12311/*
12312 * set vga decode state - true == enable VGA decode
12313 */
12314int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12315{
12316 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000012317 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100012318 u16 gmch_ctrl;
12319
Chris Wilson75fa0412014-02-07 18:37:02 -020012320 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12321 DRM_ERROR("failed to read control word\n");
12322 return -EIO;
12323 }
12324
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020012325 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12326 return 0;
12327
Dave Airlie28d52042009-09-21 14:33:58 +100012328 if (state)
12329 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12330 else
12331 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020012332
12333 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12334 DRM_ERROR("failed to write control word\n");
12335 return -EIO;
12336 }
12337
Dave Airlie28d52042009-09-21 14:33:58 +100012338 return 0;
12339}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012340
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012341struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012342
12343 u32 power_well_driver;
12344
Chris Wilson63b66e52013-08-08 15:12:06 +020012345 int num_transcoders;
12346
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012347 struct intel_cursor_error_state {
12348 u32 control;
12349 u32 position;
12350 u32 base;
12351 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010012352 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012353
12354 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020012355 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012356 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030012357 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010012358 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012359
12360 struct intel_plane_error_state {
12361 u32 control;
12362 u32 stride;
12363 u32 size;
12364 u32 pos;
12365 u32 addr;
12366 u32 surface;
12367 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010012368 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020012369
12370 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020012371 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020012372 enum transcoder cpu_transcoder;
12373
12374 u32 conf;
12375
12376 u32 htotal;
12377 u32 hblank;
12378 u32 hsync;
12379 u32 vtotal;
12380 u32 vblank;
12381 u32 vsync;
12382 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012383};
12384
12385struct intel_display_error_state *
12386intel_display_capture_error_state(struct drm_device *dev)
12387{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012388 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012389 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020012390 int transcoders[] = {
12391 TRANSCODER_A,
12392 TRANSCODER_B,
12393 TRANSCODER_C,
12394 TRANSCODER_EDP,
12395 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012396 int i;
12397
Chris Wilson63b66e52013-08-08 15:12:06 +020012398 if (INTEL_INFO(dev)->num_pipes == 0)
12399 return NULL;
12400
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012401 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012402 if (error == NULL)
12403 return NULL;
12404
Imre Deak190be112013-11-25 17:15:31 +020012405 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012406 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12407
Damien Lespiau52331302012-08-15 19:23:25 +010012408 for_each_pipe(i) {
Imre Deakddf9c532013-11-27 22:02:02 +020012409 error->pipe[i].power_domain_on =
Imre Deakda7e29b2014-02-18 00:02:02 +020012410 intel_display_power_enabled_sw(dev_priv,
12411 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020012412 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012413 continue;
12414
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030012415 error->cursor[i].control = I915_READ(CURCNTR(i));
12416 error->cursor[i].position = I915_READ(CURPOS(i));
12417 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012418
12419 error->plane[i].control = I915_READ(DSPCNTR(i));
12420 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012421 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030012422 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012423 error->plane[i].pos = I915_READ(DSPPOS(i));
12424 }
Paulo Zanonica291362013-03-06 20:03:14 -030012425 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12426 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012427 if (INTEL_INFO(dev)->gen >= 4) {
12428 error->plane[i].surface = I915_READ(DSPSURF(i));
12429 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12430 }
12431
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012432 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030012433
12434 if (!HAS_PCH_SPLIT(dev))
12435 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020012436 }
12437
12438 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12439 if (HAS_DDI(dev_priv->dev))
12440 error->num_transcoders++; /* Account for eDP. */
12441
12442 for (i = 0; i < error->num_transcoders; i++) {
12443 enum transcoder cpu_transcoder = transcoders[i];
12444
Imre Deakddf9c532013-11-27 22:02:02 +020012445 error->transcoder[i].power_domain_on =
Imre Deakda7e29b2014-02-18 00:02:02 +020012446 intel_display_power_enabled_sw(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020012447 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020012448 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012449 continue;
12450
Chris Wilson63b66e52013-08-08 15:12:06 +020012451 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12452
12453 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12454 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12455 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12456 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12457 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12458 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12459 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012460 }
12461
12462 return error;
12463}
12464
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012465#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12466
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012467void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012468intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012469 struct drm_device *dev,
12470 struct intel_display_error_state *error)
12471{
12472 int i;
12473
Chris Wilson63b66e52013-08-08 15:12:06 +020012474 if (!error)
12475 return;
12476
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012477 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020012478 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012479 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012480 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010012481 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012482 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020012483 err_printf(m, " Power: %s\n",
12484 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012485 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030012486 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012487
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012488 err_printf(m, "Plane [%d]:\n", i);
12489 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12490 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012491 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012492 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12493 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012494 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030012495 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012496 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012497 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012498 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12499 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012500 }
12501
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012502 err_printf(m, "Cursor [%d]:\n", i);
12503 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12504 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12505 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012506 }
Chris Wilson63b66e52013-08-08 15:12:06 +020012507
12508 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010012509 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020012510 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020012511 err_printf(m, " Power: %s\n",
12512 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020012513 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12514 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12515 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12516 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12517 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12518 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12519 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12520 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012521}