blob: e7e95c3cf6adf178febdb0619608ef3070efd81c [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Chon Ming Leeef9348c2014-04-09 13:28:18 +030044#define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
46
Daniel Vetter3dec0092010-08-20 21:40:52 +020047static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010048static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080049
Jesse Barnesf1f644d2013-06-27 00:39:25 +030050static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030052static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030054
Damien Lespiaue7457a92013-08-08 22:28:59 +010055static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080057static int intel_framebuffer_init(struct drm_device *dev,
58 struct intel_framebuffer *ifb,
59 struct drm_mode_fb_cmd2 *mode_cmd,
60 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020061static void intel_dp_set_m_n(struct intel_crtc *crtc);
62static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
63static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020064static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
65 struct intel_link_m_n *m_n);
66static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +020067static void haswell_set_pipeconf(struct drm_crtc *crtc);
68static void intel_set_pipe_csc(struct drm_crtc *crtc);
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +020069static void vlv_prepare_pll(struct intel_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +010070
Jesse Barnes79e53942008-11-07 14:24:08 -080071typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040072 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080073} intel_range_t;
74
75typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040076 int dot_limit;
77 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080078} intel_p2_t;
79
Ma Lingd4906092009-03-18 20:13:27 +080080typedef struct intel_limit intel_limit_t;
81struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040082 intel_range_t dot, vco, n, m, m1, m2, p, p1;
83 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080084};
Jesse Barnes79e53942008-11-07 14:24:08 -080085
Daniel Vetterd2acd212012-10-20 20:57:43 +020086int
87intel_pch_rawclk(struct drm_device *dev)
88{
89 struct drm_i915_private *dev_priv = dev->dev_private;
90
91 WARN_ON(!HAS_PCH_SPLIT(dev));
92
93 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94}
95
Chris Wilson021357a2010-09-07 20:54:59 +010096static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
Chris Wilson8b99e682010-10-13 09:59:17 +010099 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100104}
105
Daniel Vetter5d536e22013-07-06 12:52:06 +0200106static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400107 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200108 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200109 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700117};
118
Daniel Vetter5d536e22013-07-06 12:52:06 +0200119static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200121 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200122 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 4 },
130};
131
Keith Packarde4b36692009-06-05 19:22:17 -0700132static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400133 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200134 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200135 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400136 .m = { .min = 96, .max = 140 },
137 .m1 = { .min = 18, .max = 26 },
138 .m2 = { .min = 6, .max = 16 },
139 .p = { .min = 4, .max = 128 },
140 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700141 .p2 = { .dot_limit = 165000,
142 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700143};
Eric Anholt273e27c2011-03-30 13:01:10 -0700144
Keith Packarde4b36692009-06-05 19:22:17 -0700145static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400146 .dot = { .min = 20000, .max = 400000 },
147 .vco = { .min = 1400000, .max = 2800000 },
148 .n = { .min = 1, .max = 6 },
149 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100150 .m1 = { .min = 8, .max = 18 },
151 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400152 .p = { .min = 5, .max = 80 },
153 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700154 .p2 = { .dot_limit = 200000,
155 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100163 .m1 = { .min = 8, .max = 18 },
164 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700169};
170
Eric Anholt273e27c2011-03-30 13:01:10 -0700171
Keith Packarde4b36692009-06-05 19:22:17 -0700172static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700173 .dot = { .min = 25000, .max = 270000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 17, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 10, .max = 30 },
180 .p1 = { .min = 1, .max = 3},
181 .p2 = { .dot_limit = 270000,
182 .p2_slow = 10,
183 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800184 },
Keith Packarde4b36692009-06-05 19:22:17 -0700185};
186
187static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700188 .dot = { .min = 22000, .max = 400000 },
189 .vco = { .min = 1750000, .max = 3500000},
190 .n = { .min = 1, .max = 4 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 16, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8},
196 .p2 = { .dot_limit = 165000,
197 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700198};
199
200static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700201 .dot = { .min = 20000, .max = 115000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 28, .max = 112 },
208 .p1 = { .min = 2, .max = 8 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800211 },
Keith Packarde4b36692009-06-05 19:22:17 -0700212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800225 },
Keith Packarde4b36692009-06-05 19:22:17 -0700226};
227
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500228static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400229 .dot = { .min = 20000, .max = 400000},
230 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700231 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700234 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400235 .m1 = { .min = 0, .max = 0 },
236 .m2 = { .min = 0, .max = 254 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700239 .p2 = { .dot_limit = 200000,
240 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700241};
242
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500243static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1700000, .max = 3500000 },
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 .m1 = { .min = 0, .max = 0 },
249 .m2 = { .min = 0, .max = 254 },
250 .p = { .min = 7, .max = 112 },
251 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700252 .p2 = { .dot_limit = 112000,
253 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700254};
255
Eric Anholt273e27c2011-03-30 13:01:10 -0700256/* Ironlake / Sandybridge
257 *
258 * We calculate clock using (register_value + 2) for N/M1/M2, so here
259 * the range value for them is (actual_value - 2).
260 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800261static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 1760000, .max = 3510000 },
264 .n = { .min = 1, .max = 5 },
265 .m = { .min = 79, .max = 127 },
266 .m1 = { .min = 12, .max = 22 },
267 .m2 = { .min = 5, .max = 9 },
268 .p = { .min = 5, .max = 80 },
269 .p1 = { .min = 1, .max = 8 },
270 .p2 = { .dot_limit = 225000,
271 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700272};
273
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800274static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 3 },
278 .m = { .min = 79, .max = 118 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
282 .p1 = { .min = 2, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800285};
286
287static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 127 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 56 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800298};
299
Eric Anholt273e27c2011-03-30 13:01:10 -0700300/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800301static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 2 },
305 .m = { .min = 79, .max = 126 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400309 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800312};
313
314static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 3 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400322 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800325};
326
Ville Syrjälädc730512013-09-24 21:26:30 +0300327static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300328 /*
329 * These are the data rate limits (measured in fast clocks)
330 * since those are the strictest limits we have. The fast
331 * clock and actual rate limits are more relaxed, so checking
332 * them would make no difference.
333 */
334 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200335 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700336 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700337 .m1 = { .min = 2, .max = 3 },
338 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300339 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300340 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700341};
342
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300343static const intel_limit_t intel_limits_chv = {
344 /*
345 * These are the data rate limits (measured in fast clocks)
346 * since those are the strictest limits we have. The fast
347 * clock and actual rate limits are more relaxed, so checking
348 * them would make no difference.
349 */
350 .dot = { .min = 25000 * 5, .max = 540000 * 5},
351 .vco = { .min = 4860000, .max = 6700000 },
352 .n = { .min = 1, .max = 1 },
353 .m1 = { .min = 2, .max = 2 },
354 .m2 = { .min = 24 << 22, .max = 175 << 22 },
355 .p1 = { .min = 2, .max = 4 },
356 .p2 = { .p2_slow = 1, .p2_fast = 14 },
357};
358
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300359static void vlv_clock(int refclk, intel_clock_t *clock)
360{
361 clock->m = clock->m1 * clock->m2;
362 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200363 if (WARN_ON(clock->n == 0 || clock->p == 0))
364 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300365 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
366 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300367}
368
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300369/**
370 * Returns whether any output on the specified pipe is of the specified type
371 */
372static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
373{
374 struct drm_device *dev = crtc->dev;
375 struct intel_encoder *encoder;
376
377 for_each_encoder_on_crtc(dev, crtc, encoder)
378 if (encoder->type == type)
379 return true;
380
381 return false;
382}
383
Chris Wilson1b894b52010-12-14 20:04:54 +0000384static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800386{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800387 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800388 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100391 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000392 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000397 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200402 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800403 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800404
405 return limit;
406}
407
Ma Ling044c7c42009-03-18 20:13:23 +0800408static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409{
410 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100414 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700415 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800416 else
Keith Packarde4b36692009-06-05 19:22:17 -0700417 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700420 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700422 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800423 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700424 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800425
426 return limit;
427}
428
Chris Wilson1b894b52010-12-14 20:04:54 +0000429static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800430{
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
Eric Anholtbad720f2009-10-22 16:11:14 -0700434 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000435 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800436 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800437 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500438 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500440 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800441 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500442 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300443 } else if (IS_CHERRYVIEW(dev)) {
444 limit = &intel_limits_chv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700445 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300446 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100447 } else if (!IS_GEN2(dev)) {
448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
449 limit = &intel_limits_i9xx_lvds;
450 else
451 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800452 } else {
453 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700454 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200455 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700456 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200457 else
458 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800459 }
460 return limit;
461}
462
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500463/* m1 is reserved as 0 in Pineview, n is a ring counter */
464static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800465{
Shaohua Li21778322009-02-23 15:19:16 +0800466 clock->m = clock->m2 + 2;
467 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200468 if (WARN_ON(clock->n == 0 || clock->p == 0))
469 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300470 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
471 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800472}
473
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200474static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
475{
476 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
477}
478
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200479static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800480{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200481 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800482 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200483 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
484 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300485 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
486 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800487}
488
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300489static void chv_clock(int refclk, intel_clock_t *clock)
490{
491 clock->m = clock->m1 * clock->m2;
492 clock->p = clock->p1 * clock->p2;
493 if (WARN_ON(clock->n == 0 || clock->p == 0))
494 return;
495 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
496 clock->n << 22);
497 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
498}
499
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800500#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800501/**
502 * Returns whether the given set of divisors are valid for a given refclk with
503 * the given connectors.
504 */
505
Chris Wilson1b894b52010-12-14 20:04:54 +0000506static bool intel_PLL_is_valid(struct drm_device *dev,
507 const intel_limit_t *limit,
508 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800509{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300510 if (clock->n < limit->n.min || limit->n.max < clock->n)
511 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800512 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400513 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800514 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400515 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800516 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400517 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300518
519 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
520 if (clock->m1 <= clock->m2)
521 INTELPllInvalid("m1 <= m2\n");
522
523 if (!IS_VALLEYVIEW(dev)) {
524 if (clock->p < limit->p.min || limit->p.max < clock->p)
525 INTELPllInvalid("p out of range\n");
526 if (clock->m < limit->m.min || limit->m.max < clock->m)
527 INTELPllInvalid("m out of range\n");
528 }
529
Jesse Barnes79e53942008-11-07 14:24:08 -0800530 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400531 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800532 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
533 * connector, etc., rather than just a single range.
534 */
535 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400536 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800537
538 return true;
539}
540
Ma Lingd4906092009-03-18 20:13:27 +0800541static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200542i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800543 int target, int refclk, intel_clock_t *match_clock,
544 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800545{
546 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800547 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800548 int err = target;
549
Daniel Vettera210b022012-11-26 17:22:08 +0100550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800551 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800555 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100556 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
Akshay Joshi0206e352011-08-16 15:34:10 -0400567 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800568
Zhao Yakui42158662009-11-20 11:24:18 +0800569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200573 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800574 break;
575 for (clock.n = limit->n.min;
576 clock.n <= limit->n.max; clock.n++) {
577 for (clock.p1 = limit->p1.min;
578 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800579 int this_err;
580
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200581 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000582 if (!intel_PLL_is_valid(dev, limit,
583 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800584 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800585 if (match_clock &&
586 clock.p != match_clock->p)
587 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800588
589 this_err = abs(clock.dot - target);
590 if (this_err < err) {
591 *best_clock = clock;
592 err = this_err;
593 }
594 }
595 }
596 }
597 }
598
599 return (err != target);
600}
601
Ma Lingd4906092009-03-18 20:13:27 +0800602static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200603pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200606{
607 struct drm_device *dev = crtc->dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659}
660
Ma Lingd4906092009-03-18 20:13:27 +0800661static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200662g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800665{
666 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800667 intel_clock_t clock;
668 int max_n;
669 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400670 /* approximately equals target * 0.00585 */
671 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800672 found = false;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100675 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800676 clock.p2 = limit->p2.p2_fast;
677 else
678 clock.p2 = limit->p2.p2_slow;
679 } else {
680 if (target < limit->p2.dot_limit)
681 clock.p2 = limit->p2.p2_slow;
682 else
683 clock.p2 = limit->p2.p2_fast;
684 }
685
686 memset(best_clock, 0, sizeof(*best_clock));
687 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200688 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800689 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200690 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800691 for (clock.m1 = limit->m1.max;
692 clock.m1 >= limit->m1.min; clock.m1--) {
693 for (clock.m2 = limit->m2.max;
694 clock.m2 >= limit->m2.min; clock.m2--) {
695 for (clock.p1 = limit->p1.max;
696 clock.p1 >= limit->p1.min; clock.p1--) {
697 int this_err;
698
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200699 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800702 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000703
704 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800705 if (this_err < err_most) {
706 *best_clock = clock;
707 err_most = this_err;
708 max_n = clock.n;
709 found = true;
710 }
711 }
712 }
713 }
714 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800715 return found;
716}
Ma Lingd4906092009-03-18 20:13:27 +0800717
Zhenyu Wang2c072452009-06-05 15:38:42 +0800718static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200719vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700722{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300723 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300724 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300725 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300726 /* min update 19.2 MHz */
727 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300728 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700729
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300730 target *= 5; /* fast clock */
731
732 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700733
734 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300736 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300737 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300738 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300739 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700740 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300741 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300742 unsigned int ppm, diff;
743
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300744 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
745 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300746
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300747 vlv_clock(refclk, &clock);
748
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300751 continue;
752
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300753 diff = abs(clock.dot - target);
754 ppm = div_u64(1000000ULL * diff, target);
755
756 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300757 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300758 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300759 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300760 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300761
Ville Syrjäläc6861222013-09-24 21:26:21 +0300762 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300763 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300764 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300765 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700766 }
767 }
768 }
769 }
770 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700771
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300772 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700773}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700774
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300775static bool
776chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779{
780 struct drm_device *dev = crtc->dev;
781 intel_clock_t clock;
782 uint64_t m2;
783 int found = false;
784
785 memset(best_clock, 0, sizeof(*best_clock));
786
787 /*
788 * Based on hardware doc, the n always set to 1, and m1 always
789 * set to 2. If requires to support 200Mhz refclk, we need to
790 * revisit this because n may not 1 anymore.
791 */
792 clock.n = 1, clock.m1 = 2;
793 target *= 5; /* fast clock */
794
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast;
797 clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799
800 clock.p = clock.p1 * clock.p2;
801
802 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
803 clock.n) << 22, refclk * clock.m1);
804
805 if (m2 > INT_MAX/clock.m1)
806 continue;
807
808 clock.m2 = m2;
809
810 chv_clock(refclk, &clock);
811
812 if (!intel_PLL_is_valid(dev, limit, &clock))
813 continue;
814
815 /* based on hardware requirement, prefer bigger p
816 */
817 if (clock.p > best_clock->p) {
818 *best_clock = clock;
819 found = true;
820 }
821 }
822 }
823
824 return found;
825}
826
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300827bool intel_crtc_active(struct drm_crtc *crtc)
828{
829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830
831 /* Be paranoid as we can arrive here with only partial
832 * state retrieved from the hardware during setup.
833 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100834 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300835 * as Haswell has gained clock readout/fastboot support.
836 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000837 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300838 * properly reconstruct framebuffers.
839 */
Matt Roperf4510a22014-04-01 15:22:40 -0700840 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100841 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300842}
843
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200844enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
845 enum pipe pipe)
846{
847 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
849
Daniel Vetter3b117c82013-04-17 20:15:07 +0200850 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200851}
852
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200853static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
Paulo Zanonia928d532012-05-04 17:18:15 -0300854{
855 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200856 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300857
858 frame = I915_READ(frame_reg);
859
860 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
Jesse Barnes93937072014-04-04 16:12:09 -0700861 WARN(1, "vblank wait timed out\n");
Paulo Zanonia928d532012-05-04 17:18:15 -0300862}
863
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700864/**
865 * intel_wait_for_vblank - wait for vblank on a given pipe
866 * @dev: drm device
867 * @pipe: pipe to wait for
868 *
869 * Wait for vblank to occur on a given pipe. Needed for various bits of
870 * mode setting code.
871 */
872void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800873{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700874 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800875 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700876
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200877 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
878 g4x_wait_for_vblank(dev, pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300879 return;
880 }
881
Chris Wilson300387c2010-09-05 20:25:43 +0100882 /* Clear existing vblank status. Note this will clear any other
883 * sticky status fields as well.
884 *
885 * This races with i915_driver_irq_handler() with the result
886 * that either function could miss a vblank event. Here it is not
887 * fatal, as we will either wait upon the next vblank interrupt or
888 * timeout. Generally speaking intel_wait_for_vblank() is only
889 * called during modeset at which time the GPU should be idle and
890 * should *not* be performing page flips and thus not waiting on
891 * vblanks...
892 * Currently, the result of us stealing a vblank from the irq
893 * handler is that a single frame will be skipped during swapbuffers.
894 */
895 I915_WRITE(pipestat_reg,
896 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
897
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700898 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100899 if (wait_for(I915_READ(pipestat_reg) &
900 PIPE_VBLANK_INTERRUPT_STATUS,
901 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700902 DRM_DEBUG_KMS("vblank wait timed out\n");
903}
904
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300905static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
906{
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 u32 reg = PIPEDSL(pipe);
909 u32 line1, line2;
910 u32 line_mask;
911
912 if (IS_GEN2(dev))
913 line_mask = DSL_LINEMASK_GEN2;
914 else
915 line_mask = DSL_LINEMASK_GEN3;
916
917 line1 = I915_READ(reg) & line_mask;
918 mdelay(5);
919 line2 = I915_READ(reg) & line_mask;
920
921 return line1 == line2;
922}
923
Keith Packardab7ad7f2010-10-03 00:33:06 -0700924/*
925 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700926 * @dev: drm device
927 * @pipe: pipe to wait for
928 *
929 * After disabling a pipe, we can't wait for vblank in the usual way,
930 * spinning on the vblank interrupt status bit, since we won't actually
931 * see an interrupt when the pipe is disabled.
932 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700933 * On Gen4 and above:
934 * wait for the pipe register state bit to turn off
935 *
936 * Otherwise:
937 * wait for the display line value to settle (it usually
938 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100939 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700940 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100941void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700942{
943 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200944 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
945 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700946
Keith Packardab7ad7f2010-10-03 00:33:06 -0700947 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200948 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700949
Keith Packardab7ad7f2010-10-03 00:33:06 -0700950 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100951 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
952 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200953 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700954 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700955 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300956 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200957 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700958 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800959}
960
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000961/*
962 * ibx_digital_port_connected - is the specified port connected?
963 * @dev_priv: i915 private structure
964 * @port: the port to test
965 *
966 * Returns true if @port is connected, false otherwise.
967 */
968bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
969 struct intel_digital_port *port)
970{
971 u32 bit;
972
Damien Lespiauc36346e2012-12-13 16:09:03 +0000973 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +0200974 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000975 case PORT_B:
976 bit = SDE_PORTB_HOTPLUG;
977 break;
978 case PORT_C:
979 bit = SDE_PORTC_HOTPLUG;
980 break;
981 case PORT_D:
982 bit = SDE_PORTD_HOTPLUG;
983 break;
984 default:
985 return true;
986 }
987 } else {
Robin Schroereba905b2014-05-18 02:24:50 +0200988 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000989 case PORT_B:
990 bit = SDE_PORTB_HOTPLUG_CPT;
991 break;
992 case PORT_C:
993 bit = SDE_PORTC_HOTPLUG_CPT;
994 break;
995 case PORT_D:
996 bit = SDE_PORTD_HOTPLUG_CPT;
997 break;
998 default:
999 return true;
1000 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001001 }
1002
1003 return I915_READ(SDEISR) & bit;
1004}
1005
Jesse Barnesb24e7172011-01-04 15:09:30 -08001006static const char *state_string(bool enabled)
1007{
1008 return enabled ? "on" : "off";
1009}
1010
1011/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001012void assert_pll(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001014{
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = DPLL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & DPLL_VCO_ENABLE);
1022 WARN(cur_state != state,
1023 "PLL state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001026
Jani Nikula23538ef2013-08-27 15:12:22 +03001027/* XXX: the dsi pll is shared between MIPI DSI ports */
1028static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029{
1030 u32 val;
1031 bool cur_state;
1032
1033 mutex_lock(&dev_priv->dpio_lock);
1034 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035 mutex_unlock(&dev_priv->dpio_lock);
1036
1037 cur_state = val & DSI_PLL_VCO_EN;
1038 WARN(cur_state != state,
1039 "DSI PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1041}
1042#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
Daniel Vetter55607e82013-06-16 21:42:39 +02001045struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001046intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001047{
Daniel Vettere2b78262013-06-07 23:10:03 +02001048 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
Daniel Vettera43f6e02013-06-07 23:10:32 +02001050 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001051 return NULL;
1052
Daniel Vettera43f6e02013-06-07 23:10:32 +02001053 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001054}
1055
Jesse Barnesb24e7172011-01-04 15:09:30 -08001056/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001057void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058 struct intel_shared_dpll *pll,
1059 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001060{
Jesse Barnes040484a2011-01-03 12:14:26 -08001061 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001062 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001063
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001064 if (HAS_PCH_LPT(dev_priv->dev)) {
1065 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066 return;
1067 }
1068
Chris Wilson92b27b02012-05-20 18:10:50 +01001069 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001070 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001072
Daniel Vetter53589012013-06-05 13:34:16 +02001073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001074 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001077}
Jesse Barnes040484a2011-01-03 12:14:26 -08001078
1079static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081{
1082 int reg;
1083 u32 val;
1084 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001087
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001091 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101}
1102#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107{
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118}
1119#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001130 return;
1131
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001133 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001134 return;
1135
Jesse Barnes040484a2011-01-03 12:14:26 -08001136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139}
1140
Daniel Vetter55607e82013-06-16 21:42:39 +02001141void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001143{
1144 int reg;
1145 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001146 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001154}
1155
Jesse Barnesea0760c2011-01-04 15:09:32 -08001156static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158{
1159 int pp_reg, lvds_reg;
1160 u32 val;
1161 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001162 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001163
1164 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165 pp_reg = PCH_PP_CONTROL;
1166 lvds_reg = PCH_LVDS;
1167 } else {
1168 pp_reg = PP_CONTROL;
1169 lvds_reg = LVDS;
1170 }
1171
1172 val = I915_READ(pp_reg);
1173 if (!(val & PANEL_POWER_ON) ||
1174 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175 locked = false;
1176
1177 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179
1180 WARN(panel_pipe == pipe && locked,
1181 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001182 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001183}
1184
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001185static void assert_cursor(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187{
1188 struct drm_device *dev = dev_priv->dev;
1189 bool cur_state;
1190
Paulo Zanonid9d82082014-02-27 16:30:56 -03001191 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001192 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001193 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001194 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001195
1196 WARN(cur_state != state,
1197 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198 pipe_name(pipe), state_string(state), state_string(cur_state));
1199}
1200#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001203void assert_pipe(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001205{
1206 int reg;
1207 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001208 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001209 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001211
Daniel Vetter8e636782012-01-22 01:36:48 +01001212 /* if we need the pipe A quirk it must be always on */
1213 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214 state = true;
1215
Imre Deakda7e29b2014-02-18 00:02:02 +02001216 if (!intel_display_power_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001217 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001218 cur_state = false;
1219 } else {
1220 reg = PIPECONF(cpu_transcoder);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 }
1224
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001225 WARN(cur_state != state,
1226 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001227 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001228}
1229
Chris Wilson931872f2012-01-16 23:01:13 +00001230static void assert_plane(struct drm_i915_private *dev_priv,
1231 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001232{
1233 int reg;
1234 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001235 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001236
1237 reg = DSPCNTR(plane);
1238 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001239 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240 WARN(cur_state != state,
1241 "plane %c assertion failure (expected %s, current %s)\n",
1242 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001243}
1244
Chris Wilson931872f2012-01-16 23:01:13 +00001245#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
Jesse Barnesb24e7172011-01-04 15:09:30 -08001248static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249 enum pipe pipe)
1250{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001251 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
Ville Syrjälä653e1022013-06-04 13:49:05 +03001256 /* Primary planes are fixed to pipes on gen4+ */
1257 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001260 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001263 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001264 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001265
Jesse Barnesb24e7172011-01-04 15:09:30 -08001266 /* Need to check both planes against the pipe */
Damien Lespiau08e2a7d2013-07-11 20:10:54 +01001267 for_each_pipe(i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001275 }
1276}
1277
Jesse Barnes19332d72013-03-28 09:55:38 -07001278static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe)
1280{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001281 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001282 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001283 u32 val;
1284
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001285 if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001286 for_each_sprite(pipe, sprite) {
1287 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001288 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001289 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001291 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001292 }
1293 } else if (INTEL_INFO(dev)->gen >= 7) {
1294 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001295 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001296 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001297 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001298 plane_name(pipe), pipe_name(pipe));
1299 } else if (INTEL_INFO(dev)->gen >= 5) {
1300 reg = DVSCNTR(pipe);
1301 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001302 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001303 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001305 }
1306}
1307
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001308static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001309{
1310 u32 val;
1311 bool enabled;
1312
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001313 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001314
Jesse Barnes92f25842011-01-04 15:09:34 -08001315 val = I915_READ(PCH_DREF_CONTROL);
1316 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317 DREF_SUPERSPREAD_SOURCE_MASK));
1318 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319}
1320
Daniel Vetterab9412b2013-05-03 11:49:46 +02001321static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001323{
1324 int reg;
1325 u32 val;
1326 bool enabled;
1327
Daniel Vetterab9412b2013-05-03 11:49:46 +02001328 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001329 val = I915_READ(reg);
1330 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001331 WARN(enabled,
1332 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001334}
1335
Keith Packard4e634382011-08-06 10:39:45 -07001336static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001338{
1339 if ((val & DP_PORT_EN) == 0)
1340 return false;
1341
1342 if (HAS_PCH_CPT(dev_priv->dev)) {
1343 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001347 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001350 } else {
1351 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352 return false;
1353 }
1354 return true;
1355}
1356
Keith Packard1519b992011-08-06 10:35:34 -07001357static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, u32 val)
1359{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001360 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001361 return false;
1362
1363 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001364 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001365 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001366 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001369 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001370 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001371 return false;
1372 }
1373 return true;
1374}
1375
1376static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377 enum pipe pipe, u32 val)
1378{
1379 if ((val & LVDS_PORT_EN) == 0)
1380 return false;
1381
1382 if (HAS_PCH_CPT(dev_priv->dev)) {
1383 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384 return false;
1385 } else {
1386 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387 return false;
1388 }
1389 return true;
1390}
1391
1392static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394{
1395 if ((val & ADPA_DAC_ENABLE) == 0)
1396 return false;
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399 return false;
1400 } else {
1401 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402 return false;
1403 }
1404 return true;
1405}
1406
Jesse Barnes291906f2011-02-02 12:28:03 -08001407static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001408 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001409{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001410 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001411 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001412 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001413 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001414
Daniel Vetter75c5da22012-09-10 21:58:29 +02001415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001417 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001418}
1419
1420static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, int reg)
1422{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001423 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001424 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001425 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001426 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001427
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001428 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001429 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001430 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001431}
1432
1433static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001438
Keith Packardf0575e92011-07-25 22:12:43 -07001439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001442
1443 reg = PCH_ADPA;
1444 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001445 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001446 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001447 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001448
1449 reg = PCH_LVDS;
1450 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001451 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001452 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001453 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001454
Paulo Zanonie2debe92013-02-18 19:00:27 -03001455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001458}
1459
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001460static void intel_init_dpio(struct drm_device *dev)
1461{
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 if (!IS_VALLEYVIEW(dev))
1465 return;
1466
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001467 /*
1468 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469 * CHV x1 PHY (DP/HDMI D)
1470 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471 */
1472 if (IS_CHERRYVIEW(dev)) {
1473 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475 } else {
1476 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001478}
1479
1480static void intel_reset_dpio(struct drm_device *dev)
1481{
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484 if (!IS_VALLEYVIEW(dev))
1485 return;
1486
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001487 if (IS_CHERRYVIEW(dev)) {
1488 enum dpio_phy phy;
1489 u32 val;
1490
1491 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1492 /* Poll for phypwrgood signal */
1493 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1494 PHY_POWERGOOD(phy), 1))
1495 DRM_ERROR("Display PHY %d is not power up\n", phy);
1496
1497 /*
1498 * Deassert common lane reset for PHY.
1499 *
1500 * This should only be done on init and resume from S3
1501 * with both PLLs disabled, or we risk losing DPIO and
1502 * PLL synchronization.
1503 */
1504 val = I915_READ(DISPLAY_PHY_CONTROL);
1505 I915_WRITE(DISPLAY_PHY_CONTROL,
1506 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1507 }
1508
1509 } else {
1510 /*
Jesse Barnes57021052014-05-23 13:16:40 -07001511 * If DPIO has already been reset, e.g. by BIOS, just skip all
1512 * this.
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001513 */
Jesse Barnes57021052014-05-23 13:16:40 -07001514 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1515 return;
1516
1517 /*
1518 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1519 * Need to assert and de-assert PHY SB reset by gating the
1520 * common lane power, then un-gating it.
1521 * Simply ungating isn't enough to reset the PHY enough to get
1522 * ports and lanes running.
1523 */
1524 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1525 false);
1526 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1527 true);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001528 }
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001529}
1530
Daniel Vetter426115c2013-07-11 22:13:42 +02001531static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001532{
Daniel Vetter426115c2013-07-11 22:13:42 +02001533 struct drm_device *dev = crtc->base.dev;
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 int reg = DPLL(crtc->pipe);
1536 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001537
Daniel Vetter426115c2013-07-11 22:13:42 +02001538 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001539
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001540 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001541 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1542
1543 /* PLL is protected by panel, make sure we can write it */
1544 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001545 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001546
Daniel Vetter426115c2013-07-11 22:13:42 +02001547 I915_WRITE(reg, dpll);
1548 POSTING_READ(reg);
1549 udelay(150);
1550
1551 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1553
1554 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1555 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001556
1557 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001558 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001559 POSTING_READ(reg);
1560 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001561 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001562 POSTING_READ(reg);
1563 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001564 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001565 POSTING_READ(reg);
1566 udelay(150); /* wait for warmup */
1567}
1568
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001569static void chv_enable_pll(struct intel_crtc *crtc)
1570{
1571 struct drm_device *dev = crtc->base.dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 int pipe = crtc->pipe;
1574 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001575 u32 tmp;
1576
1577 assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1580
1581 mutex_lock(&dev_priv->dpio_lock);
1582
1583 /* Enable back the 10bit clock to display controller */
1584 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1585 tmp |= DPIO_DCLKP_EN;
1586 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1587
1588 /*
1589 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590 */
1591 udelay(1);
1592
1593 /* Enable PLL */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001594 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001595
1596 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001597 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001598 DRM_ERROR("PLL %d failed to lock\n", pipe);
1599
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001600 /* not sure when this should be written */
1601 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1602 POSTING_READ(DPLL_MD(pipe));
1603
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001604 mutex_unlock(&dev_priv->dpio_lock);
1605}
1606
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001607static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001608{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001609 struct drm_device *dev = crtc->base.dev;
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 int reg = DPLL(crtc->pipe);
1612 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001613
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001614 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001615
1616 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001617 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001618
1619 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001620 if (IS_MOBILE(dev) && !IS_I830(dev))
1621 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001622
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001623 I915_WRITE(reg, dpll);
1624
1625 /* Wait for the clocks to stabilize. */
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (INTEL_INFO(dev)->gen >= 4) {
1630 I915_WRITE(DPLL_MD(crtc->pipe),
1631 crtc->config.dpll_hw_state.dpll_md);
1632 } else {
1633 /* The pixel multiplier can only be updated once the
1634 * DPLL is enabled and the clocks are stable.
1635 *
1636 * So write it again.
1637 */
1638 I915_WRITE(reg, dpll);
1639 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001640
1641 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001642 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001645 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001648 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651}
1652
1653/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001654 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001655 * @dev_priv: i915 private structure
1656 * @pipe: pipe PLL to disable
1657 *
1658 * Disable the PLL for @pipe, making sure the pipe is off first.
1659 *
1660 * Note! This is for pre-ILK only.
1661 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001662static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001663{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001664 /* Don't disable pipe A or pipe A PLLs if needed */
1665 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666 return;
1667
1668 /* Make sure the pipe isn't still relying on us */
1669 assert_pipe_disabled(dev_priv, pipe);
1670
Daniel Vetter50b44a42013-06-05 13:34:33 +02001671 I915_WRITE(DPLL(pipe), 0);
1672 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001673}
1674
Jesse Barnesf6071162013-10-01 10:41:38 -07001675static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676{
1677 u32 val = 0;
1678
1679 /* Make sure the pipe isn't still relying on us */
1680 assert_pipe_disabled(dev_priv, pipe);
1681
Imre Deake5cbfbf2014-01-09 17:08:16 +02001682 /*
1683 * Leave integrated clock source and reference clock enabled for pipe B.
1684 * The latter is needed for VGA hotplug / manual detection.
1685 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001686 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001687 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001688 I915_WRITE(DPLL(pipe), val);
1689 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001690
1691}
1692
1693static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001695 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001696 u32 val;
1697
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001700
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001701 /* Set PLL en = 0 */
1702 val = DPLL_SSC_REF_CLOCK_CHV;
1703 if (pipe != PIPE_A)
1704 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1705 I915_WRITE(DPLL(pipe), val);
1706 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001707
1708 mutex_lock(&dev_priv->dpio_lock);
1709
1710 /* Disable 10bit clock to display controller */
1711 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1712 val &= ~DPIO_DCLKP_EN;
1713 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1714
Ville Syrjälä61407f62014-05-27 16:32:55 +03001715 /* disable left/right clock distribution */
1716 if (pipe != PIPE_B) {
1717 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1718 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1719 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1720 } else {
1721 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1722 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1723 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1724 }
1725
Ville Syrjäläd7520482014-04-09 13:28:59 +03001726 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001727}
1728
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001729void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1730 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001731{
1732 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001733 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001734
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001735 switch (dport->port) {
1736 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001737 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001738 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001739 break;
1740 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001741 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001742 dpll_reg = DPLL(0);
1743 break;
1744 case PORT_D:
1745 port_mask = DPLL_PORTD_READY_MASK;
1746 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001747 break;
1748 default:
1749 BUG();
1750 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001751
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001752 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001753 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001754 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001755}
1756
Daniel Vetterb14b1052014-04-24 23:55:13 +02001757static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1758{
1759 struct drm_device *dev = crtc->base.dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1762
1763 WARN_ON(!pll->refcount);
1764 if (pll->active == 0) {
1765 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1766 WARN_ON(pll->on);
1767 assert_shared_dpll_disabled(dev_priv, pll);
1768
1769 pll->mode_set(dev_priv, pll);
1770 }
1771}
1772
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001773/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001774 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001775 * @dev_priv: i915 private structure
1776 * @pipe: pipe PLL to enable
1777 *
1778 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1779 * drives the transcoder clock.
1780 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001781static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001782{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001783 struct drm_device *dev = crtc->base.dev;
1784 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001785 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001786
Daniel Vetter87a875b2013-06-05 13:34:19 +02001787 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001788 return;
1789
1790 if (WARN_ON(pll->refcount == 0))
1791 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001792
Daniel Vetter46edb022013-06-05 13:34:12 +02001793 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1794 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001795 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001796
Daniel Vettercdbd2312013-06-05 13:34:03 +02001797 if (pll->active++) {
1798 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001799 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001800 return;
1801 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001802 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001803
Daniel Vetter46edb022013-06-05 13:34:12 +02001804 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001805 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001806 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001807}
1808
Daniel Vettere2b78262013-06-07 23:10:03 +02001809static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001810{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001811 struct drm_device *dev = crtc->base.dev;
1812 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001813 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001814
Jesse Barnes92f25842011-01-04 15:09:34 -08001815 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001816 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001817 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001818 return;
1819
Chris Wilson48da64a2012-05-13 20:16:12 +01001820 if (WARN_ON(pll->refcount == 0))
1821 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001822
Daniel Vetter46edb022013-06-05 13:34:12 +02001823 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1824 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001825 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001826
Chris Wilson48da64a2012-05-13 20:16:12 +01001827 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001828 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001829 return;
1830 }
1831
Daniel Vettere9d69442013-06-05 13:34:15 +02001832 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001833 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001834 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001835 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001836
Daniel Vetter46edb022013-06-05 13:34:12 +02001837 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001838 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001839 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001840}
1841
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001842static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1843 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001844{
Daniel Vetter23670b322012-11-01 09:15:30 +01001845 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001846 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001848 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001849
1850 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001851 BUG_ON(INTEL_INFO(dev)->gen < 5);
Jesse Barnes040484a2011-01-03 12:14:26 -08001852
1853 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001854 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001855 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001856
1857 /* FDI must be feeding us bits for PCH ports */
1858 assert_fdi_tx_enabled(dev_priv, pipe);
1859 assert_fdi_rx_enabled(dev_priv, pipe);
1860
Daniel Vetter23670b322012-11-01 09:15:30 +01001861 if (HAS_PCH_CPT(dev)) {
1862 /* Workaround: Set the timing override bit before enabling the
1863 * pch transcoder. */
1864 reg = TRANS_CHICKEN2(pipe);
1865 val = I915_READ(reg);
1866 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1867 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001868 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001869
Daniel Vetterab9412b2013-05-03 11:49:46 +02001870 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001871 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001872 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001873
1874 if (HAS_PCH_IBX(dev_priv->dev)) {
1875 /*
1876 * make the BPC in transcoder be consistent with
1877 * that in pipeconf reg.
1878 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001879 val &= ~PIPECONF_BPC_MASK;
1880 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001881 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001882
1883 val &= ~TRANS_INTERLACE_MASK;
1884 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001885 if (HAS_PCH_IBX(dev_priv->dev) &&
1886 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1887 val |= TRANS_LEGACY_INTERLACED_ILK;
1888 else
1889 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001890 else
1891 val |= TRANS_PROGRESSIVE;
1892
Jesse Barnes040484a2011-01-03 12:14:26 -08001893 I915_WRITE(reg, val | TRANS_ENABLE);
1894 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001895 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001896}
1897
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001898static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001899 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001900{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001901 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001902
1903 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001904 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001905
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001906 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001907 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001908 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001909
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001910 /* Workaround: set timing override bit. */
1911 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001912 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001913 I915_WRITE(_TRANSA_CHICKEN2, val);
1914
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001915 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001916 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001917
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001918 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1919 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001920 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001921 else
1922 val |= TRANS_PROGRESSIVE;
1923
Daniel Vetterab9412b2013-05-03 11:49:46 +02001924 I915_WRITE(LPT_TRANSCONF, val);
1925 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001926 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001927}
1928
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001929static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1930 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001931{
Daniel Vetter23670b322012-11-01 09:15:30 +01001932 struct drm_device *dev = dev_priv->dev;
1933 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001934
1935 /* FDI relies on the transcoder */
1936 assert_fdi_tx_disabled(dev_priv, pipe);
1937 assert_fdi_rx_disabled(dev_priv, pipe);
1938
Jesse Barnes291906f2011-02-02 12:28:03 -08001939 /* Ports must be off as well */
1940 assert_pch_ports_disabled(dev_priv, pipe);
1941
Daniel Vetterab9412b2013-05-03 11:49:46 +02001942 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001943 val = I915_READ(reg);
1944 val &= ~TRANS_ENABLE;
1945 I915_WRITE(reg, val);
1946 /* wait for PCH transcoder off, transcoder state */
1947 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001948 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001949
1950 if (!HAS_PCH_IBX(dev)) {
1951 /* Workaround: Clear the timing override chicken bit again. */
1952 reg = TRANS_CHICKEN2(pipe);
1953 val = I915_READ(reg);
1954 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1955 I915_WRITE(reg, val);
1956 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001957}
1958
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001959static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001960{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001961 u32 val;
1962
Daniel Vetterab9412b2013-05-03 11:49:46 +02001963 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001964 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001965 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001966 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001967 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001968 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001969
1970 /* Workaround: clear timing override bit. */
1971 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001972 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001973 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001974}
1975
1976/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001977 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02001978 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001979 *
Paulo Zanoni03722642014-01-17 13:51:09 -02001980 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001981 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08001982 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02001983static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001984{
Paulo Zanoni03722642014-01-17 13:51:09 -02001985 struct drm_device *dev = crtc->base.dev;
1986 struct drm_i915_private *dev_priv = dev->dev_private;
1987 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001988 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1989 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001990 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001991 int reg;
1992 u32 val;
1993
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001994 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001995 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001996 assert_sprites_disabled(dev_priv, pipe);
1997
Paulo Zanoni681e5812012-12-06 11:12:38 -02001998 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001999 pch_transcoder = TRANSCODER_A;
2000 else
2001 pch_transcoder = pipe;
2002
Jesse Barnesb24e7172011-01-04 15:09:30 -08002003 /*
2004 * A pipe without a PLL won't actually be able to drive bits from
2005 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2006 * need the check.
2007 */
2008 if (!HAS_PCH_SPLIT(dev_priv->dev))
Paulo Zanonifbf32182014-01-17 13:51:11 -02002009 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002010 assert_dsi_pll_enabled(dev_priv);
2011 else
2012 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002013 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002014 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002015 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002016 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002017 assert_fdi_tx_pll_enabled(dev_priv,
2018 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002019 }
2020 /* FIXME: assert CPU port conditions for SNB+ */
2021 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002022
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002023 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002024 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002025 if (val & PIPECONF_ENABLE) {
2026 WARN_ON(!(pipe == PIPE_A &&
2027 dev_priv->quirks & QUIRK_PIPEA_FORCE));
Chris Wilson00d70b12011-03-17 07:18:29 +00002028 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002029 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002030
2031 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002032 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002033}
2034
2035/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002036 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002037 * @dev_priv: i915 private structure
2038 * @pipe: pipe to disable
2039 *
2040 * Disable @pipe, making sure that various hardware specific requirements
2041 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2042 *
2043 * @pipe should be %PIPE_A or %PIPE_B.
2044 *
2045 * Will wait until the pipe has shut down before returning.
2046 */
2047static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2048 enum pipe pipe)
2049{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002050 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2051 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002052 int reg;
2053 u32 val;
2054
2055 /*
2056 * Make sure planes won't keep trying to pump pixels to us,
2057 * or we might hang the display.
2058 */
2059 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002060 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002061 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002062
2063 /* Don't disable pipe A or pipe A PLLs if needed */
2064 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2065 return;
2066
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002067 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002068 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002069 if ((val & PIPECONF_ENABLE) == 0)
2070 return;
2071
2072 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002073 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2074}
2075
Keith Packardd74362c2011-07-28 14:47:14 -07002076/*
2077 * Plane regs are double buffered, going from enabled->disabled needs a
2078 * trigger in order to latch. The display address reg provides this.
2079 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002080void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2081 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002082{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002083 struct drm_device *dev = dev_priv->dev;
2084 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002085
2086 I915_WRITE(reg, I915_READ(reg));
2087 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002088}
2089
Jesse Barnesb24e7172011-01-04 15:09:30 -08002090/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002091 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002092 * @dev_priv: i915 private structure
2093 * @plane: plane to enable
2094 * @pipe: pipe being fed
2095 *
2096 * Enable @plane on @pipe, making sure that @pipe is running first.
2097 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002098static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2099 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002100{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002101 struct intel_crtc *intel_crtc =
2102 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002103 int reg;
2104 u32 val;
2105
2106 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2107 assert_pipe_enabled(dev_priv, pipe);
2108
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002109 if (intel_crtc->primary_enabled)
2110 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002111
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002112 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002113
Jesse Barnesb24e7172011-01-04 15:09:30 -08002114 reg = DSPCNTR(plane);
2115 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002116 WARN_ON(val & DISPLAY_PLANE_ENABLE);
Chris Wilson00d70b12011-03-17 07:18:29 +00002117
2118 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002119 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002120}
2121
Jesse Barnesb24e7172011-01-04 15:09:30 -08002122/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002123 * intel_disable_primary_hw_plane - disable the primary hardware plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002124 * @dev_priv: i915 private structure
2125 * @plane: plane to disable
2126 * @pipe: pipe consuming the data
2127 *
2128 * Disable @plane; should be an independent operation.
2129 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002130static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2131 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002132{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002133 struct intel_crtc *intel_crtc =
2134 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002135 int reg;
2136 u32 val;
2137
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002138 if (!intel_crtc->primary_enabled)
2139 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002140
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002141 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002142
Jesse Barnesb24e7172011-01-04 15:09:30 -08002143 reg = DSPCNTR(plane);
2144 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002145 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
Chris Wilson00d70b12011-03-17 07:18:29 +00002146
2147 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002148 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002149}
2150
Chris Wilson693db182013-03-05 14:52:39 +00002151static bool need_vtd_wa(struct drm_device *dev)
2152{
2153#ifdef CONFIG_INTEL_IOMMU
2154 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2155 return true;
2156#endif
2157 return false;
2158}
2159
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002160static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2161{
2162 int tile_height;
2163
2164 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2165 return ALIGN(height, tile_height);
2166}
2167
Chris Wilson127bd2a2010-07-23 23:32:05 +01002168int
Chris Wilson48b956c2010-09-14 12:50:34 +01002169intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002170 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002171 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002172{
Chris Wilsonce453d82011-02-21 14:43:56 +00002173 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002174 u32 alignment;
2175 int ret;
2176
Chris Wilson05394f32010-11-08 19:18:58 +00002177 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002178 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002179 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2180 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002181 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002182 alignment = 4 * 1024;
2183 else
2184 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002185 break;
2186 case I915_TILING_X:
2187 /* pin() will align the object as required by fence */
2188 alignment = 0;
2189 break;
2190 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002191 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002192 return -EINVAL;
2193 default:
2194 BUG();
2195 }
2196
Chris Wilson693db182013-03-05 14:52:39 +00002197 /* Note that the w/a also requires 64 PTE of padding following the
2198 * bo. We currently fill all unused PTE with the shadow page and so
2199 * we should always have valid PTE following the scanout preventing
2200 * the VT-d warning.
2201 */
2202 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2203 alignment = 256 * 1024;
2204
Chris Wilsonce453d82011-02-21 14:43:56 +00002205 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002206 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002207 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002208 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002209
2210 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2211 * fence, whereas 965+ only requires a fence if using
2212 * framebuffer compression. For simplicity, we always install
2213 * a fence as the cost is not that onerous.
2214 */
Chris Wilson06d98132012-04-17 15:31:24 +01002215 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002216 if (ret)
2217 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002218
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002219 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002220
Chris Wilsonce453d82011-02-21 14:43:56 +00002221 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002222 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002223
2224err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002225 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002226err_interruptible:
2227 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002228 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002229}
2230
Chris Wilson1690e1e2011-12-14 13:57:08 +01002231void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2232{
2233 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002234 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002235}
2236
Daniel Vetterc2c75132012-07-05 12:17:30 +02002237/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2238 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002239unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2240 unsigned int tiling_mode,
2241 unsigned int cpp,
2242 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002243{
Chris Wilsonbc752862013-02-21 20:04:31 +00002244 if (tiling_mode != I915_TILING_NONE) {
2245 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002246
Chris Wilsonbc752862013-02-21 20:04:31 +00002247 tile_rows = *y / 8;
2248 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002249
Chris Wilsonbc752862013-02-21 20:04:31 +00002250 tiles = *x / (512/cpp);
2251 *x %= 512/cpp;
2252
2253 return tile_rows * pitch * 8 + tiles * 4096;
2254 } else {
2255 unsigned int offset;
2256
2257 offset = *y * pitch + *x * cpp;
2258 *y = 0;
2259 *x = (offset & 4095) / cpp;
2260 return offset & -4096;
2261 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002262}
2263
Jesse Barnes46f297f2014-03-07 08:57:48 -08002264int intel_format_to_fourcc(int format)
2265{
2266 switch (format) {
2267 case DISPPLANE_8BPP:
2268 return DRM_FORMAT_C8;
2269 case DISPPLANE_BGRX555:
2270 return DRM_FORMAT_XRGB1555;
2271 case DISPPLANE_BGRX565:
2272 return DRM_FORMAT_RGB565;
2273 default:
2274 case DISPPLANE_BGRX888:
2275 return DRM_FORMAT_XRGB8888;
2276 case DISPPLANE_RGBX888:
2277 return DRM_FORMAT_XBGR8888;
2278 case DISPPLANE_BGRX101010:
2279 return DRM_FORMAT_XRGB2101010;
2280 case DISPPLANE_RGBX101010:
2281 return DRM_FORMAT_XBGR2101010;
2282 }
2283}
2284
Jesse Barnes484b41d2014-03-07 08:57:55 -08002285static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002286 struct intel_plane_config *plane_config)
2287{
2288 struct drm_device *dev = crtc->base.dev;
2289 struct drm_i915_gem_object *obj = NULL;
2290 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2291 u32 base = plane_config->base;
2292
Chris Wilsonff2652e2014-03-10 08:07:02 +00002293 if (plane_config->size == 0)
2294 return false;
2295
Jesse Barnes46f297f2014-03-07 08:57:48 -08002296 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2297 plane_config->size);
2298 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002299 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002300
2301 if (plane_config->tiled) {
2302 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002303 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002304 }
2305
Dave Airlie66e514c2014-04-03 07:51:54 +10002306 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2307 mode_cmd.width = crtc->base.primary->fb->width;
2308 mode_cmd.height = crtc->base.primary->fb->height;
2309 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002310
2311 mutex_lock(&dev->struct_mutex);
2312
Dave Airlie66e514c2014-04-03 07:51:54 +10002313 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002314 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002315 DRM_DEBUG_KMS("intel fb init failed\n");
2316 goto out_unref_obj;
2317 }
2318
2319 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002320
2321 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2322 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002323
2324out_unref_obj:
2325 drm_gem_object_unreference(&obj->base);
2326 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002327 return false;
2328}
2329
2330static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2331 struct intel_plane_config *plane_config)
2332{
2333 struct drm_device *dev = intel_crtc->base.dev;
2334 struct drm_crtc *c;
2335 struct intel_crtc *i;
2336 struct intel_framebuffer *fb;
2337
Dave Airlie66e514c2014-04-03 07:51:54 +10002338 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002339 return;
2340
2341 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2342 return;
2343
Dave Airlie66e514c2014-04-03 07:51:54 +10002344 kfree(intel_crtc->base.primary->fb);
2345 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002346
2347 /*
2348 * Failed to alloc the obj, check to see if we should share
2349 * an fb with another CRTC instead
2350 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002351 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002352 i = to_intel_crtc(c);
2353
2354 if (c == &intel_crtc->base)
2355 continue;
2356
Dave Airlie66e514c2014-04-03 07:51:54 +10002357 if (!i->active || !c->primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002358 continue;
2359
Dave Airlie66e514c2014-04-03 07:51:54 +10002360 fb = to_intel_framebuffer(c->primary->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002361 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
Dave Airlie66e514c2014-04-03 07:51:54 +10002362 drm_framebuffer_reference(c->primary->fb);
2363 intel_crtc->base.primary->fb = c->primary->fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002364 break;
2365 }
2366 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002367}
2368
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002369static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2370 struct drm_framebuffer *fb,
2371 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002372{
2373 struct drm_device *dev = crtc->dev;
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2376 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002377 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002378 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002379 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002380 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002381 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002382
Jesse Barnes81255562010-08-02 12:07:50 -07002383 intel_fb = to_intel_framebuffer(fb);
2384 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002385
Chris Wilson5eddb702010-09-11 13:48:45 +01002386 reg = DSPCNTR(plane);
2387 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002388 /* Mask out pixel format bits in case we change it */
2389 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002390 switch (fb->pixel_format) {
2391 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002392 dspcntr |= DISPPLANE_8BPP;
2393 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002394 case DRM_FORMAT_XRGB1555:
2395 case DRM_FORMAT_ARGB1555:
2396 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002397 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002398 case DRM_FORMAT_RGB565:
2399 dspcntr |= DISPPLANE_BGRX565;
2400 break;
2401 case DRM_FORMAT_XRGB8888:
2402 case DRM_FORMAT_ARGB8888:
2403 dspcntr |= DISPPLANE_BGRX888;
2404 break;
2405 case DRM_FORMAT_XBGR8888:
2406 case DRM_FORMAT_ABGR8888:
2407 dspcntr |= DISPPLANE_RGBX888;
2408 break;
2409 case DRM_FORMAT_XRGB2101010:
2410 case DRM_FORMAT_ARGB2101010:
2411 dspcntr |= DISPPLANE_BGRX101010;
2412 break;
2413 case DRM_FORMAT_XBGR2101010:
2414 case DRM_FORMAT_ABGR2101010:
2415 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002416 break;
2417 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002418 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002419 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002420
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002421 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002422 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002423 dspcntr |= DISPPLANE_TILED;
2424 else
2425 dspcntr &= ~DISPPLANE_TILED;
2426 }
2427
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002428 if (IS_G4X(dev))
2429 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2430
Chris Wilson5eddb702010-09-11 13:48:45 +01002431 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002432
Daniel Vettere506a0c2012-07-05 12:17:29 +02002433 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002434
Daniel Vetterc2c75132012-07-05 12:17:30 +02002435 if (INTEL_INFO(dev)->gen >= 4) {
2436 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002437 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2438 fb->bits_per_pixel / 8,
2439 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002440 linear_offset -= intel_crtc->dspaddr_offset;
2441 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002442 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002443 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002444
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002445 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2446 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2447 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002448 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002449 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002450 I915_WRITE(DSPSURF(plane),
2451 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002452 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002453 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002454 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002455 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002456 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002457}
2458
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002459static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2460 struct drm_framebuffer *fb,
2461 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002462{
2463 struct drm_device *dev = crtc->dev;
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2466 struct intel_framebuffer *intel_fb;
2467 struct drm_i915_gem_object *obj;
2468 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002469 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002470 u32 dspcntr;
2471 u32 reg;
2472
Jesse Barnes17638cd2011-06-24 12:19:23 -07002473 intel_fb = to_intel_framebuffer(fb);
2474 obj = intel_fb->obj;
2475
2476 reg = DSPCNTR(plane);
2477 dspcntr = I915_READ(reg);
2478 /* Mask out pixel format bits in case we change it */
2479 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002480 switch (fb->pixel_format) {
2481 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002482 dspcntr |= DISPPLANE_8BPP;
2483 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002484 case DRM_FORMAT_RGB565:
2485 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002486 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002487 case DRM_FORMAT_XRGB8888:
2488 case DRM_FORMAT_ARGB8888:
2489 dspcntr |= DISPPLANE_BGRX888;
2490 break;
2491 case DRM_FORMAT_XBGR8888:
2492 case DRM_FORMAT_ABGR8888:
2493 dspcntr |= DISPPLANE_RGBX888;
2494 break;
2495 case DRM_FORMAT_XRGB2101010:
2496 case DRM_FORMAT_ARGB2101010:
2497 dspcntr |= DISPPLANE_BGRX101010;
2498 break;
2499 case DRM_FORMAT_XBGR2101010:
2500 case DRM_FORMAT_ABGR2101010:
2501 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002502 break;
2503 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002504 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002505 }
2506
2507 if (obj->tiling_mode != I915_TILING_NONE)
2508 dspcntr |= DISPPLANE_TILED;
2509 else
2510 dspcntr &= ~DISPPLANE_TILED;
2511
Ville Syrjäläb42c6002013-11-03 13:47:27 +02002512 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002513 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2514 else
2515 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002516
2517 I915_WRITE(reg, dspcntr);
2518
Daniel Vettere506a0c2012-07-05 12:17:29 +02002519 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002520 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002521 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2522 fb->bits_per_pixel / 8,
2523 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002524 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002525
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002526 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2527 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2528 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002529 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002530 I915_WRITE(DSPSURF(plane),
2531 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002532 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002533 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2534 } else {
2535 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2536 I915_WRITE(DSPLINOFF(plane), linear_offset);
2537 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002538 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002539}
2540
2541/* Assume fb object is pinned & idle & fenced and just update base pointers */
2542static int
2543intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2544 int x, int y, enum mode_set_atomic state)
2545{
2546 struct drm_device *dev = crtc->dev;
2547 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002548
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002549 if (dev_priv->display.disable_fbc)
2550 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002551 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002552
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002553 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2554
2555 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002556}
2557
Ville Syrjälä96a02912013-02-18 19:08:49 +02002558void intel_display_handle_reset(struct drm_device *dev)
2559{
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct drm_crtc *crtc;
2562
2563 /*
2564 * Flips in the rings have been nuked by the reset,
2565 * so complete all pending flips so that user space
2566 * will get its events and not get stuck.
2567 *
2568 * Also update the base address of all primary
2569 * planes to the the last fb to make sure we're
2570 * showing the correct fb after a reset.
2571 *
2572 * Need to make two loops over the crtcs so that we
2573 * don't try to grab a crtc mutex before the
2574 * pending_flip_queue really got woken up.
2575 */
2576
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002577 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2579 enum plane plane = intel_crtc->plane;
2580
2581 intel_prepare_page_flip(dev, plane);
2582 intel_finish_page_flip_plane(dev, plane);
2583 }
2584
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002585 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2587
Rob Clark51fd3712013-11-19 12:10:12 -05002588 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002589 /*
2590 * FIXME: Once we have proper support for primary planes (and
2591 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002592 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002593 */
Matt Roperf4510a22014-04-01 15:22:40 -07002594 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002595 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002596 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002597 crtc->x,
2598 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05002599 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002600 }
2601}
2602
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002603static int
Chris Wilson14667a42012-04-03 17:58:35 +01002604intel_finish_fb(struct drm_framebuffer *old_fb)
2605{
2606 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2607 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2608 bool was_interruptible = dev_priv->mm.interruptible;
2609 int ret;
2610
Chris Wilson14667a42012-04-03 17:58:35 +01002611 /* Big Hammer, we also need to ensure that any pending
2612 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2613 * current scanout is retired before unpinning the old
2614 * framebuffer.
2615 *
2616 * This should only fail upon a hung GPU, in which case we
2617 * can safely continue.
2618 */
2619 dev_priv->mm.interruptible = false;
2620 ret = i915_gem_object_finish_gpu(obj);
2621 dev_priv->mm.interruptible = was_interruptible;
2622
2623 return ret;
2624}
2625
Chris Wilson7d5e3792014-03-04 13:15:08 +00002626static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2627{
2628 struct drm_device *dev = crtc->dev;
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2631 unsigned long flags;
2632 bool pending;
2633
2634 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2635 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2636 return false;
2637
2638 spin_lock_irqsave(&dev->event_lock, flags);
2639 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2640 spin_unlock_irqrestore(&dev->event_lock, flags);
2641
2642 return pending;
2643}
2644
Chris Wilson14667a42012-04-03 17:58:35 +01002645static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002646intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002647 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002648{
2649 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002650 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002652 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002653 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002654
Chris Wilson7d5e3792014-03-04 13:15:08 +00002655 if (intel_crtc_has_pending_flip(crtc)) {
2656 DRM_ERROR("pipe is still busy with an old pageflip\n");
2657 return -EBUSY;
2658 }
2659
Jesse Barnes79e53942008-11-07 14:24:08 -08002660 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002661 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002662 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002663 return 0;
2664 }
2665
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002666 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002667 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2668 plane_name(intel_crtc->plane),
2669 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002670 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002671 }
2672
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002673 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002674 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002675 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002676 NULL);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002677 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002678 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002679 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002680 return ret;
2681 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002682
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002683 /*
2684 * Update pipe size and adjust fitter if needed: the reason for this is
2685 * that in compute_mode_changes we check the native mode (not the pfit
2686 * mode) to see if we can flip rather than do a full mode set. In the
2687 * fastboot case, we'll flip, but if we don't update the pipesrc and
2688 * pfit state, we'll end up with a big fb scanned out into the wrong
2689 * sized surface.
2690 *
2691 * To fix this properly, we need to hoist the checks up into
2692 * compute_mode_changes (or above), check the actual pfit state and
2693 * whether the platform allows pfit disable with pipe active, and only
2694 * then update the pipesrc and pfit state, even on the flip path.
2695 */
Jani Nikulad330a952014-01-21 11:24:25 +02002696 if (i915.fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002697 const struct drm_display_mode *adjusted_mode =
2698 &intel_crtc->config.adjusted_mode;
2699
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002700 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002701 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2702 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002703 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002704 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2705 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2706 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2707 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2708 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2709 }
Jesse Barnes0637d602013-12-19 10:48:01 -08002710 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2711 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002712 }
2713
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002714 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002715
Matt Roperf4510a22014-04-01 15:22:40 -07002716 old_fb = crtc->primary->fb;
2717 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002718 crtc->x = x;
2719 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002720
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002721 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002722 if (intel_crtc->active && old_fb != fb)
2723 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002724 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002725 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002726 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002727 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002728
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002729 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002730 intel_update_fbc(dev);
Rodrigo Vivi49065572013-07-11 18:45:05 -03002731 intel_edp_psr_update(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002732 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002733
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002734 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002735}
2736
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002737static void intel_fdi_normal_train(struct drm_crtc *crtc)
2738{
2739 struct drm_device *dev = crtc->dev;
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742 int pipe = intel_crtc->pipe;
2743 u32 reg, temp;
2744
2745 /* enable normal train */
2746 reg = FDI_TX_CTL(pipe);
2747 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002748 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002749 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2750 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002751 } else {
2752 temp &= ~FDI_LINK_TRAIN_NONE;
2753 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002754 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002755 I915_WRITE(reg, temp);
2756
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 if (HAS_PCH_CPT(dev)) {
2760 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2761 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2762 } else {
2763 temp &= ~FDI_LINK_TRAIN_NONE;
2764 temp |= FDI_LINK_TRAIN_NONE;
2765 }
2766 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2767
2768 /* wait one idle pattern time */
2769 POSTING_READ(reg);
2770 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002771
2772 /* IVB wants error correction enabled */
2773 if (IS_IVYBRIDGE(dev))
2774 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2775 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002776}
2777
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002778static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002779{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002780 return crtc->base.enabled && crtc->active &&
2781 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002782}
2783
Daniel Vetter01a415f2012-10-27 15:58:40 +02002784static void ivb_modeset_global_resources(struct drm_device *dev)
2785{
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 struct intel_crtc *pipe_B_crtc =
2788 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2789 struct intel_crtc *pipe_C_crtc =
2790 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2791 uint32_t temp;
2792
Daniel Vetter1e833f42013-02-19 22:31:57 +01002793 /*
2794 * When everything is off disable fdi C so that we could enable fdi B
2795 * with all lanes. Note that we don't care about enabled pipes without
2796 * an enabled pch encoder.
2797 */
2798 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2799 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002800 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2801 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2802
2803 temp = I915_READ(SOUTH_CHICKEN1);
2804 temp &= ~FDI_BC_BIFURCATION_SELECT;
2805 DRM_DEBUG_KMS("disabling fdi C rx\n");
2806 I915_WRITE(SOUTH_CHICKEN1, temp);
2807 }
2808}
2809
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002810/* The FDI link training functions for ILK/Ibexpeak. */
2811static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2812{
2813 struct drm_device *dev = crtc->dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2816 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002817 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002818
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03002819 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002820 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002821
Adam Jacksone1a44742010-06-25 15:32:14 -04002822 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2823 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002824 reg = FDI_RX_IMR(pipe);
2825 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002826 temp &= ~FDI_RX_SYMBOL_LOCK;
2827 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002828 I915_WRITE(reg, temp);
2829 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002830 udelay(150);
2831
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002832 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002833 reg = FDI_TX_CTL(pipe);
2834 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002835 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2836 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002837 temp &= ~FDI_LINK_TRAIN_NONE;
2838 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002839 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002840
Chris Wilson5eddb702010-09-11 13:48:45 +01002841 reg = FDI_RX_CTL(pipe);
2842 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002843 temp &= ~FDI_LINK_TRAIN_NONE;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002845 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2846
2847 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002848 udelay(150);
2849
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002850 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002851 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2852 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2853 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002854
Chris Wilson5eddb702010-09-11 13:48:45 +01002855 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002856 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002857 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002858 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2859
2860 if ((temp & FDI_RX_BIT_LOCK)) {
2861 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002862 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002863 break;
2864 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002865 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002866 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002867 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002868
2869 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002870 reg = FDI_TX_CTL(pipe);
2871 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002872 temp &= ~FDI_LINK_TRAIN_NONE;
2873 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002874 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002875
Chris Wilson5eddb702010-09-11 13:48:45 +01002876 reg = FDI_RX_CTL(pipe);
2877 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002878 temp &= ~FDI_LINK_TRAIN_NONE;
2879 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002880 I915_WRITE(reg, temp);
2881
2882 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002883 udelay(150);
2884
Chris Wilson5eddb702010-09-11 13:48:45 +01002885 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002886 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002887 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002888 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2889
2890 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002891 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002892 DRM_DEBUG_KMS("FDI train 2 done.\n");
2893 break;
2894 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002895 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002896 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002897 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002898
2899 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002900
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002901}
2902
Akshay Joshi0206e352011-08-16 15:34:10 -04002903static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002904 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2905 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2906 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2907 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2908};
2909
2910/* The FDI link training functions for SNB/Cougarpoint. */
2911static void gen6_fdi_link_train(struct drm_crtc *crtc)
2912{
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2916 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002917 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002918
Adam Jacksone1a44742010-06-25 15:32:14 -04002919 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2920 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002921 reg = FDI_RX_IMR(pipe);
2922 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002923 temp &= ~FDI_RX_SYMBOL_LOCK;
2924 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002925 I915_WRITE(reg, temp);
2926
2927 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002928 udelay(150);
2929
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002930 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002931 reg = FDI_TX_CTL(pipe);
2932 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002933 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2934 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002935 temp &= ~FDI_LINK_TRAIN_NONE;
2936 temp |= FDI_LINK_TRAIN_PATTERN_1;
2937 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2938 /* SNB-B */
2939 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002940 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002941
Daniel Vetterd74cf322012-10-26 10:58:13 +02002942 I915_WRITE(FDI_RX_MISC(pipe),
2943 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2944
Chris Wilson5eddb702010-09-11 13:48:45 +01002945 reg = FDI_RX_CTL(pipe);
2946 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002947 if (HAS_PCH_CPT(dev)) {
2948 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2950 } else {
2951 temp &= ~FDI_LINK_TRAIN_NONE;
2952 temp |= FDI_LINK_TRAIN_PATTERN_1;
2953 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002954 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2955
2956 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002957 udelay(150);
2958
Akshay Joshi0206e352011-08-16 15:34:10 -04002959 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002960 reg = FDI_TX_CTL(pipe);
2961 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002962 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2963 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002964 I915_WRITE(reg, temp);
2965
2966 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002967 udelay(500);
2968
Sean Paulfa37d392012-03-02 12:53:39 -05002969 for (retry = 0; retry < 5; retry++) {
2970 reg = FDI_RX_IIR(pipe);
2971 temp = I915_READ(reg);
2972 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2973 if (temp & FDI_RX_BIT_LOCK) {
2974 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2975 DRM_DEBUG_KMS("FDI train 1 done.\n");
2976 break;
2977 }
2978 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002979 }
Sean Paulfa37d392012-03-02 12:53:39 -05002980 if (retry < 5)
2981 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002982 }
2983 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002984 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002985
2986 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002987 reg = FDI_TX_CTL(pipe);
2988 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002989 temp &= ~FDI_LINK_TRAIN_NONE;
2990 temp |= FDI_LINK_TRAIN_PATTERN_2;
2991 if (IS_GEN6(dev)) {
2992 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2993 /* SNB-B */
2994 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2995 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002996 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002997
Chris Wilson5eddb702010-09-11 13:48:45 +01002998 reg = FDI_RX_CTL(pipe);
2999 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003000 if (HAS_PCH_CPT(dev)) {
3001 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3002 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3003 } else {
3004 temp &= ~FDI_LINK_TRAIN_NONE;
3005 temp |= FDI_LINK_TRAIN_PATTERN_2;
3006 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003007 I915_WRITE(reg, temp);
3008
3009 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003010 udelay(150);
3011
Akshay Joshi0206e352011-08-16 15:34:10 -04003012 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003013 reg = FDI_TX_CTL(pipe);
3014 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003015 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3016 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003017 I915_WRITE(reg, temp);
3018
3019 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003020 udelay(500);
3021
Sean Paulfa37d392012-03-02 12:53:39 -05003022 for (retry = 0; retry < 5; retry++) {
3023 reg = FDI_RX_IIR(pipe);
3024 temp = I915_READ(reg);
3025 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3026 if (temp & FDI_RX_SYMBOL_LOCK) {
3027 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3028 DRM_DEBUG_KMS("FDI train 2 done.\n");
3029 break;
3030 }
3031 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003032 }
Sean Paulfa37d392012-03-02 12:53:39 -05003033 if (retry < 5)
3034 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003035 }
3036 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003037 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003038
3039 DRM_DEBUG_KMS("FDI train done.\n");
3040}
3041
Jesse Barnes357555c2011-04-28 15:09:55 -07003042/* Manual link training for Ivy Bridge A0 parts */
3043static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3044{
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3048 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003049 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003050
3051 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3052 for train result */
3053 reg = FDI_RX_IMR(pipe);
3054 temp = I915_READ(reg);
3055 temp &= ~FDI_RX_SYMBOL_LOCK;
3056 temp &= ~FDI_RX_BIT_LOCK;
3057 I915_WRITE(reg, temp);
3058
3059 POSTING_READ(reg);
3060 udelay(150);
3061
Daniel Vetter01a415f2012-10-27 15:58:40 +02003062 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3063 I915_READ(FDI_RX_IIR(pipe)));
3064
Jesse Barnes139ccd32013-08-19 11:04:55 -07003065 /* Try each vswing and preemphasis setting twice before moving on */
3066 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3067 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003068 reg = FDI_TX_CTL(pipe);
3069 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003070 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3071 temp &= ~FDI_TX_ENABLE;
3072 I915_WRITE(reg, temp);
3073
3074 reg = FDI_RX_CTL(pipe);
3075 temp = I915_READ(reg);
3076 temp &= ~FDI_LINK_TRAIN_AUTO;
3077 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3078 temp &= ~FDI_RX_ENABLE;
3079 I915_WRITE(reg, temp);
3080
3081 /* enable CPU FDI TX and PCH FDI RX */
3082 reg = FDI_TX_CTL(pipe);
3083 temp = I915_READ(reg);
3084 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3085 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3086 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003087 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003088 temp |= snb_b_fdi_train_param[j/2];
3089 temp |= FDI_COMPOSITE_SYNC;
3090 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3091
3092 I915_WRITE(FDI_RX_MISC(pipe),
3093 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3094
3095 reg = FDI_RX_CTL(pipe);
3096 temp = I915_READ(reg);
3097 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3098 temp |= FDI_COMPOSITE_SYNC;
3099 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3100
3101 POSTING_READ(reg);
3102 udelay(1); /* should be 0.5us */
3103
3104 for (i = 0; i < 4; i++) {
3105 reg = FDI_RX_IIR(pipe);
3106 temp = I915_READ(reg);
3107 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3108
3109 if (temp & FDI_RX_BIT_LOCK ||
3110 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3111 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3112 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3113 i);
3114 break;
3115 }
3116 udelay(1); /* should be 0.5us */
3117 }
3118 if (i == 4) {
3119 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3120 continue;
3121 }
3122
3123 /* Train 2 */
3124 reg = FDI_TX_CTL(pipe);
3125 temp = I915_READ(reg);
3126 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3127 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3128 I915_WRITE(reg, temp);
3129
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3133 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003134 I915_WRITE(reg, temp);
3135
3136 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003137 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003138
Jesse Barnes139ccd32013-08-19 11:04:55 -07003139 for (i = 0; i < 4; i++) {
3140 reg = FDI_RX_IIR(pipe);
3141 temp = I915_READ(reg);
3142 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003143
Jesse Barnes139ccd32013-08-19 11:04:55 -07003144 if (temp & FDI_RX_SYMBOL_LOCK ||
3145 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3146 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3147 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3148 i);
3149 goto train_done;
3150 }
3151 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003152 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003153 if (i == 4)
3154 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003155 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003156
Jesse Barnes139ccd32013-08-19 11:04:55 -07003157train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003158 DRM_DEBUG_KMS("FDI train done.\n");
3159}
3160
Daniel Vetter88cefb62012-08-12 19:27:14 +02003161static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003162{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003163 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003164 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003165 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003166 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003167
Jesse Barnesc64e3112010-09-10 11:27:03 -07003168
Jesse Barnes0e23b992010-09-10 11:10:00 -07003169 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003170 reg = FDI_RX_CTL(pipe);
3171 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003172 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3173 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003174 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003175 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3176
3177 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003178 udelay(200);
3179
3180 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003181 temp = I915_READ(reg);
3182 I915_WRITE(reg, temp | FDI_PCDCLK);
3183
3184 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003185 udelay(200);
3186
Paulo Zanoni20749732012-11-23 15:30:38 -02003187 /* Enable CPU FDI TX PLL, always on for Ironlake */
3188 reg = FDI_TX_CTL(pipe);
3189 temp = I915_READ(reg);
3190 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3191 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003192
Paulo Zanoni20749732012-11-23 15:30:38 -02003193 POSTING_READ(reg);
3194 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003195 }
3196}
3197
Daniel Vetter88cefb62012-08-12 19:27:14 +02003198static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3199{
3200 struct drm_device *dev = intel_crtc->base.dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 int pipe = intel_crtc->pipe;
3203 u32 reg, temp;
3204
3205 /* Switch from PCDclk to Rawclk */
3206 reg = FDI_RX_CTL(pipe);
3207 temp = I915_READ(reg);
3208 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3209
3210 /* Disable CPU FDI TX PLL */
3211 reg = FDI_TX_CTL(pipe);
3212 temp = I915_READ(reg);
3213 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3214
3215 POSTING_READ(reg);
3216 udelay(100);
3217
3218 reg = FDI_RX_CTL(pipe);
3219 temp = I915_READ(reg);
3220 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3221
3222 /* Wait for the clocks to turn off. */
3223 POSTING_READ(reg);
3224 udelay(100);
3225}
3226
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003227static void ironlake_fdi_disable(struct drm_crtc *crtc)
3228{
3229 struct drm_device *dev = crtc->dev;
3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3232 int pipe = intel_crtc->pipe;
3233 u32 reg, temp;
3234
3235 /* disable CPU FDI tx and PCH FDI rx */
3236 reg = FDI_TX_CTL(pipe);
3237 temp = I915_READ(reg);
3238 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3239 POSTING_READ(reg);
3240
3241 reg = FDI_RX_CTL(pipe);
3242 temp = I915_READ(reg);
3243 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003244 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003245 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3246
3247 POSTING_READ(reg);
3248 udelay(100);
3249
3250 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003251 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003252 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003253
3254 /* still set train pattern 1 */
3255 reg = FDI_TX_CTL(pipe);
3256 temp = I915_READ(reg);
3257 temp &= ~FDI_LINK_TRAIN_NONE;
3258 temp |= FDI_LINK_TRAIN_PATTERN_1;
3259 I915_WRITE(reg, temp);
3260
3261 reg = FDI_RX_CTL(pipe);
3262 temp = I915_READ(reg);
3263 if (HAS_PCH_CPT(dev)) {
3264 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3265 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3266 } else {
3267 temp &= ~FDI_LINK_TRAIN_NONE;
3268 temp |= FDI_LINK_TRAIN_PATTERN_1;
3269 }
3270 /* BPC in FDI rx is consistent with that in PIPECONF */
3271 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003272 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003273 I915_WRITE(reg, temp);
3274
3275 POSTING_READ(reg);
3276 udelay(100);
3277}
3278
Chris Wilson5dce5b932014-01-20 10:17:36 +00003279bool intel_has_pending_fb_unpin(struct drm_device *dev)
3280{
3281 struct intel_crtc *crtc;
3282
3283 /* Note that we don't need to be called with mode_config.lock here
3284 * as our list of CRTC objects is static for the lifetime of the
3285 * device and so cannot disappear as we iterate. Similarly, we can
3286 * happily treat the predicates as racy, atomic checks as userspace
3287 * cannot claim and pin a new fb without at least acquring the
3288 * struct_mutex and so serialising with us.
3289 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003290 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003291 if (atomic_read(&crtc->unpin_work_count) == 0)
3292 continue;
3293
3294 if (crtc->unpin_work)
3295 intel_wait_for_vblank(dev, crtc->pipe);
3296
3297 return true;
3298 }
3299
3300 return false;
3301}
3302
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003303void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003304{
Chris Wilson0f911282012-04-17 10:05:38 +01003305 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003306 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003307
Matt Roperf4510a22014-04-01 15:22:40 -07003308 if (crtc->primary->fb == NULL)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003309 return;
3310
Daniel Vetter2c10d572012-12-20 21:24:07 +01003311 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3312
Daniel Vettereed6d672014-05-19 16:09:35 +02003313 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3314 !intel_crtc_has_pending_flip(crtc),
3315 60*HZ) == 0);
Chris Wilson5bb61642012-09-27 21:25:58 +01003316
Chris Wilson0f911282012-04-17 10:05:38 +01003317 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07003318 intel_finish_fb(crtc->primary->fb);
Chris Wilson0f911282012-04-17 10:05:38 +01003319 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003320}
3321
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003322/* Program iCLKIP clock to the desired frequency */
3323static void lpt_program_iclkip(struct drm_crtc *crtc)
3324{
3325 struct drm_device *dev = crtc->dev;
3326 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003327 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003328 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3329 u32 temp;
3330
Daniel Vetter09153002012-12-12 14:06:44 +01003331 mutex_lock(&dev_priv->dpio_lock);
3332
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003333 /* It is necessary to ungate the pixclk gate prior to programming
3334 * the divisors, and gate it back when it is done.
3335 */
3336 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3337
3338 /* Disable SSCCTL */
3339 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003340 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3341 SBI_SSCCTL_DISABLE,
3342 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003343
3344 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003345 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003346 auxdiv = 1;
3347 divsel = 0x41;
3348 phaseinc = 0x20;
3349 } else {
3350 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003351 * but the adjusted_mode->crtc_clock in in KHz. To get the
3352 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003353 * convert the virtual clock precision to KHz here for higher
3354 * precision.
3355 */
3356 u32 iclk_virtual_root_freq = 172800 * 1000;
3357 u32 iclk_pi_range = 64;
3358 u32 desired_divisor, msb_divisor_value, pi_value;
3359
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003360 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003361 msb_divisor_value = desired_divisor / iclk_pi_range;
3362 pi_value = desired_divisor % iclk_pi_range;
3363
3364 auxdiv = 0;
3365 divsel = msb_divisor_value - 2;
3366 phaseinc = pi_value;
3367 }
3368
3369 /* This should not happen with any sane values */
3370 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3371 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3372 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3373 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3374
3375 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003376 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003377 auxdiv,
3378 divsel,
3379 phasedir,
3380 phaseinc);
3381
3382 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003383 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003384 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3385 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3386 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3387 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3388 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3389 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003390 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003391
3392 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003393 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003394 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3395 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003396 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003397
3398 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003399 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003400 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003401 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003402
3403 /* Wait for initialization time */
3404 udelay(24);
3405
3406 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003407
3408 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003409}
3410
Daniel Vetter275f01b22013-05-03 11:49:47 +02003411static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3412 enum pipe pch_transcoder)
3413{
3414 struct drm_device *dev = crtc->base.dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3417
3418 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3419 I915_READ(HTOTAL(cpu_transcoder)));
3420 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3421 I915_READ(HBLANK(cpu_transcoder)));
3422 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3423 I915_READ(HSYNC(cpu_transcoder)));
3424
3425 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3426 I915_READ(VTOTAL(cpu_transcoder)));
3427 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3428 I915_READ(VBLANK(cpu_transcoder)));
3429 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3430 I915_READ(VSYNC(cpu_transcoder)));
3431 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3432 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3433}
3434
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003435static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3436{
3437 struct drm_i915_private *dev_priv = dev->dev_private;
3438 uint32_t temp;
3439
3440 temp = I915_READ(SOUTH_CHICKEN1);
3441 if (temp & FDI_BC_BIFURCATION_SELECT)
3442 return;
3443
3444 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3445 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3446
3447 temp |= FDI_BC_BIFURCATION_SELECT;
3448 DRM_DEBUG_KMS("enabling fdi C rx\n");
3449 I915_WRITE(SOUTH_CHICKEN1, temp);
3450 POSTING_READ(SOUTH_CHICKEN1);
3451}
3452
3453static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3454{
3455 struct drm_device *dev = intel_crtc->base.dev;
3456 struct drm_i915_private *dev_priv = dev->dev_private;
3457
3458 switch (intel_crtc->pipe) {
3459 case PIPE_A:
3460 break;
3461 case PIPE_B:
3462 if (intel_crtc->config.fdi_lanes > 2)
3463 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3464 else
3465 cpt_enable_fdi_bc_bifurcation(dev);
3466
3467 break;
3468 case PIPE_C:
3469 cpt_enable_fdi_bc_bifurcation(dev);
3470
3471 break;
3472 default:
3473 BUG();
3474 }
3475}
3476
Jesse Barnesf67a5592011-01-05 10:31:48 -08003477/*
3478 * Enable PCH resources required for PCH ports:
3479 * - PCH PLLs
3480 * - FDI training & RX/TX
3481 * - update transcoder timings
3482 * - DP transcoding bits
3483 * - transcoder
3484 */
3485static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003486{
3487 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3490 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003491 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003492
Daniel Vetterab9412b2013-05-03 11:49:46 +02003493 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003494
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003495 if (IS_IVYBRIDGE(dev))
3496 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3497
Daniel Vettercd986ab2012-10-26 10:58:12 +02003498 /* Write the TU size bits before fdi link training, so that error
3499 * detection works. */
3500 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3501 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3502
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003503 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003504 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003505
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003506 /* We need to program the right clock selection before writing the pixel
3507 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003508 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003509 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003510
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003511 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003512 temp |= TRANS_DPLL_ENABLE(pipe);
3513 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003514 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003515 temp |= sel;
3516 else
3517 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003518 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003519 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003520
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003521 /* XXX: pch pll's can be enabled any time before we enable the PCH
3522 * transcoder, and we actually should do this to not upset any PCH
3523 * transcoder that already use the clock when we share it.
3524 *
3525 * Note that enable_shared_dpll tries to do the right thing, but
3526 * get_shared_dpll unconditionally resets the pll - we need that to have
3527 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003528 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003529
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003530 /* set transcoder timing, panel must allow it */
3531 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003532 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003533
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003534 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003535
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003536 /* For PCH DP, enable TRANS_DP_CTL */
3537 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003538 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3539 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003540 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003541 reg = TRANS_DP_CTL(pipe);
3542 temp = I915_READ(reg);
3543 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003544 TRANS_DP_SYNC_MASK |
3545 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003546 temp |= (TRANS_DP_OUTPUT_ENABLE |
3547 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003548 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003549
3550 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003551 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003552 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003553 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003554
3555 switch (intel_trans_dp_port_sel(crtc)) {
3556 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003557 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003558 break;
3559 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003560 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003561 break;
3562 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003563 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003564 break;
3565 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003566 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003567 }
3568
Chris Wilson5eddb702010-09-11 13:48:45 +01003569 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003570 }
3571
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003572 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003573}
3574
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003575static void lpt_pch_enable(struct drm_crtc *crtc)
3576{
3577 struct drm_device *dev = crtc->dev;
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003580 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003581
Daniel Vetterab9412b2013-05-03 11:49:46 +02003582 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003583
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003584 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003585
Paulo Zanoni0540e482012-10-31 18:12:40 -02003586 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003587 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003588
Paulo Zanoni937bb612012-10-31 18:12:47 -02003589 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003590}
3591
Daniel Vettere2b78262013-06-07 23:10:03 +02003592static void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003593{
Daniel Vettere2b78262013-06-07 23:10:03 +02003594 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003595
3596 if (pll == NULL)
3597 return;
3598
3599 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003600 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003601 return;
3602 }
3603
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003604 if (--pll->refcount == 0) {
3605 WARN_ON(pll->on);
3606 WARN_ON(pll->active);
3607 }
3608
Daniel Vettera43f6e02013-06-07 23:10:32 +02003609 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003610}
3611
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003612static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003613{
Daniel Vettere2b78262013-06-07 23:10:03 +02003614 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3615 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3616 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003617
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003618 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003619 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3620 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003621 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003622 }
3623
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003624 if (HAS_PCH_IBX(dev_priv->dev)) {
3625 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003626 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003627 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003628
Daniel Vetter46edb022013-06-05 13:34:12 +02003629 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3630 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003631
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003632 WARN_ON(pll->refcount);
3633
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003634 goto found;
3635 }
3636
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003637 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3638 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003639
3640 /* Only want to check enabled timings first */
3641 if (pll->refcount == 0)
3642 continue;
3643
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003644 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3645 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003646 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003647 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003648 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003649
3650 goto found;
3651 }
3652 }
3653
3654 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003655 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3656 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003657 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003658 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3659 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003660 goto found;
3661 }
3662 }
3663
3664 return NULL;
3665
3666found:
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003667 if (pll->refcount == 0)
3668 pll->hw_state = crtc->config.dpll_hw_state;
3669
Daniel Vettera43f6e02013-06-07 23:10:32 +02003670 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003671 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3672 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003673
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003674 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003675
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003676 return pll;
3677}
3678
Daniel Vettera1520312013-05-03 11:49:50 +02003679static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003680{
3681 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003682 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003683 u32 temp;
3684
3685 temp = I915_READ(dslreg);
3686 udelay(500);
3687 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003688 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003689 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003690 }
3691}
3692
Jesse Barnesb074cec2013-04-25 12:55:02 -07003693static void ironlake_pfit_enable(struct intel_crtc *crtc)
3694{
3695 struct drm_device *dev = crtc->base.dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 int pipe = crtc->pipe;
3698
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003699 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003700 /* Force use of hard-coded filter coefficients
3701 * as some pre-programmed values are broken,
3702 * e.g. x201.
3703 */
3704 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3705 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3706 PF_PIPE_SEL_IVB(pipe));
3707 else
3708 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3709 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3710 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003711 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003712}
3713
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003714static void intel_enable_planes(struct drm_crtc *crtc)
3715{
3716 struct drm_device *dev = crtc->dev;
3717 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003718 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003719 struct intel_plane *intel_plane;
3720
Matt Roperaf2b6532014-04-01 15:22:32 -07003721 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3722 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003723 if (intel_plane->pipe == pipe)
3724 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003725 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003726}
3727
3728static void intel_disable_planes(struct drm_crtc *crtc)
3729{
3730 struct drm_device *dev = crtc->dev;
3731 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003732 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003733 struct intel_plane *intel_plane;
3734
Matt Roperaf2b6532014-04-01 15:22:32 -07003735 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3736 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003737 if (intel_plane->pipe == pipe)
3738 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003739 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003740}
3741
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003742void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003743{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003744 struct drm_device *dev = crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03003746
3747 if (!crtc->config.ips_enabled)
3748 return;
3749
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003750 /* We can only enable IPS after we enable a plane and wait for a vblank */
3751 intel_wait_for_vblank(dev, crtc->pipe);
3752
Paulo Zanonid77e4532013-09-24 13:52:55 -03003753 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003754 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003755 mutex_lock(&dev_priv->rps.hw_lock);
3756 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3757 mutex_unlock(&dev_priv->rps.hw_lock);
3758 /* Quoting Art Runyan: "its not safe to expect any particular
3759 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08003760 * mailbox." Moreover, the mailbox may return a bogus state,
3761 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003762 */
3763 } else {
3764 I915_WRITE(IPS_CTL, IPS_ENABLE);
3765 /* The bit only becomes 1 in the next vblank, so this wait here
3766 * is essentially intel_wait_for_vblank. If we don't have this
3767 * and don't wait for vblanks until the end of crtc_enable, then
3768 * the HW state readout code will complain that the expected
3769 * IPS_CTL value is not the one we read. */
3770 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3771 DRM_ERROR("Timed out waiting for IPS enable\n");
3772 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003773}
3774
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003775void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003776{
3777 struct drm_device *dev = crtc->base.dev;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779
3780 if (!crtc->config.ips_enabled)
3781 return;
3782
3783 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003784 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003785 mutex_lock(&dev_priv->rps.hw_lock);
3786 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3787 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003788 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3789 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3790 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08003791 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003792 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08003793 POSTING_READ(IPS_CTL);
3794 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003795
3796 /* We need to wait for a vblank before we can disable the plane. */
3797 intel_wait_for_vblank(dev, crtc->pipe);
3798}
3799
3800/** Loads the palette/gamma unit for the CRTC with the prepared values */
3801static void intel_crtc_load_lut(struct drm_crtc *crtc)
3802{
3803 struct drm_device *dev = crtc->dev;
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3806 enum pipe pipe = intel_crtc->pipe;
3807 int palreg = PALETTE(pipe);
3808 int i;
3809 bool reenable_ips = false;
3810
3811 /* The clocks have to be on to load the palette. */
3812 if (!crtc->enabled || !intel_crtc->active)
3813 return;
3814
3815 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3816 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3817 assert_dsi_pll_enabled(dev_priv);
3818 else
3819 assert_pll_enabled(dev_priv, pipe);
3820 }
3821
3822 /* use legacy palette for Ironlake */
3823 if (HAS_PCH_SPLIT(dev))
3824 palreg = LGC_PALETTE(pipe);
3825
3826 /* Workaround : Do not read or write the pipe palette/gamma data while
3827 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3828 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02003829 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03003830 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3831 GAMMA_MODE_MODE_SPLIT)) {
3832 hsw_disable_ips(intel_crtc);
3833 reenable_ips = true;
3834 }
3835
3836 for (i = 0; i < 256; i++) {
3837 I915_WRITE(palreg + 4 * i,
3838 (intel_crtc->lut_r[i] << 16) |
3839 (intel_crtc->lut_g[i] << 8) |
3840 intel_crtc->lut_b[i]);
3841 }
3842
3843 if (reenable_ips)
3844 hsw_enable_ips(intel_crtc);
3845}
3846
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003847static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3848{
3849 if (!enable && intel_crtc->overlay) {
3850 struct drm_device *dev = intel_crtc->base.dev;
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3852
3853 mutex_lock(&dev->struct_mutex);
3854 dev_priv->mm.interruptible = false;
3855 (void) intel_overlay_switch_off(intel_crtc->overlay);
3856 dev_priv->mm.interruptible = true;
3857 mutex_unlock(&dev->struct_mutex);
3858 }
3859
3860 /* Let userspace switch the overlay on again. In most cases userspace
3861 * has to recompute where to put it anyway.
3862 */
3863}
3864
3865/**
3866 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3867 * cursor plane briefly if not already running after enabling the display
3868 * plane.
3869 * This workaround avoids occasional blank screens when self refresh is
3870 * enabled.
3871 */
3872static void
3873g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3874{
3875 u32 cntl = I915_READ(CURCNTR(pipe));
3876
3877 if ((cntl & CURSOR_MODE) == 0) {
3878 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3879
3880 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3881 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3882 intel_wait_for_vblank(dev_priv->dev, pipe);
3883 I915_WRITE(CURCNTR(pipe), cntl);
3884 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3885 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3886 }
3887}
3888
3889static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003890{
3891 struct drm_device *dev = crtc->dev;
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3894 int pipe = intel_crtc->pipe;
3895 int plane = intel_crtc->plane;
3896
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003897 drm_vblank_on(dev, pipe);
3898
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003899 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3900 intel_enable_planes(crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003901 /* The fixup needs to happen before cursor is enabled */
3902 if (IS_G4X(dev))
3903 g4x_fixup_plane(dev_priv, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003904 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003905 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003906
3907 hsw_enable_ips(intel_crtc);
3908
3909 mutex_lock(&dev->struct_mutex);
3910 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02003911 intel_edp_psr_update(dev);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003912 mutex_unlock(&dev->struct_mutex);
3913}
3914
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003915static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003916{
3917 struct drm_device *dev = crtc->dev;
3918 struct drm_i915_private *dev_priv = dev->dev_private;
3919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3920 int pipe = intel_crtc->pipe;
3921 int plane = intel_crtc->plane;
3922
3923 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003924
3925 if (dev_priv->fbc.plane == plane)
3926 intel_disable_fbc(dev);
3927
3928 hsw_disable_ips(intel_crtc);
3929
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003930 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003931 intel_crtc_update_cursor(crtc, false);
3932 intel_disable_planes(crtc);
3933 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003934
3935 drm_vblank_off(dev, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003936}
3937
Jesse Barnesf67a5592011-01-05 10:31:48 -08003938static void ironlake_crtc_enable(struct drm_crtc *crtc)
3939{
3940 struct drm_device *dev = crtc->dev;
3941 struct drm_i915_private *dev_priv = dev->dev_private;
3942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003943 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003944 int pipe = intel_crtc->pipe;
Daniel Vetter29407aa2014-04-24 23:55:08 +02003945 enum plane plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003946
Daniel Vetter08a48462012-07-02 11:43:47 +02003947 WARN_ON(!crtc->enabled);
3948
Jesse Barnesf67a5592011-01-05 10:31:48 -08003949 if (intel_crtc->active)
3950 return;
3951
Daniel Vetterb14b1052014-04-24 23:55:13 +02003952 if (intel_crtc->config.has_pch_encoder)
3953 intel_prepare_shared_dpll(intel_crtc);
3954
Daniel Vetter29407aa2014-04-24 23:55:08 +02003955 if (intel_crtc->config.has_dp_encoder)
3956 intel_dp_set_m_n(intel_crtc);
3957
3958 intel_set_pipe_timings(intel_crtc);
3959
3960 if (intel_crtc->config.has_pch_encoder) {
3961 intel_cpu_transcoder_set_m_n(intel_crtc,
3962 &intel_crtc->config.fdi_m_n);
3963 }
3964
3965 ironlake_set_pipeconf(crtc);
3966
3967 /* Set up the display plane register */
3968 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3969 POSTING_READ(DSPCNTR(plane));
3970
3971 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3972 crtc->x, crtc->y);
3973
Jesse Barnesf67a5592011-01-05 10:31:48 -08003974 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003975
3976 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3977 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3978
Daniel Vetterf6736a12013-06-05 13:34:30 +02003979 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003980 if (encoder->pre_enable)
3981 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003982
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003983 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003984 /* Note: FDI PLL enabling _must_ be done before we enable the
3985 * cpu pipes, hence this is separate from all the other fdi/pch
3986 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003987 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003988 } else {
3989 assert_fdi_tx_disabled(dev_priv, pipe);
3990 assert_fdi_rx_disabled(dev_priv, pipe);
3991 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003992
Jesse Barnesb074cec2013-04-25 12:55:02 -07003993 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003994
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003995 /*
3996 * On ILK+ LUT must be loaded before the pipe is running but with
3997 * clocks enabled
3998 */
3999 intel_crtc_load_lut(crtc);
4000
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004001 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004002 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004003
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004004 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004005 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004006
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004007 for_each_encoder_on_crtc(dev, crtc, encoder)
4008 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004009
4010 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004011 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004012
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004013 intel_crtc_enable_planes(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004014}
4015
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004016/* IPS only exists on ULT machines and is tied to pipe A. */
4017static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4018{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004019 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004020}
4021
Paulo Zanonie4916942013-09-20 16:21:19 -03004022/*
4023 * This implements the workaround described in the "notes" section of the mode
4024 * set sequence documentation. When going from no pipes or single pipe to
4025 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4026 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4027 */
4028static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4029{
4030 struct drm_device *dev = crtc->base.dev;
4031 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4032
4033 /* We want to get the other_active_crtc only if there's only 1 other
4034 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004035 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004036 if (!crtc_it->active || crtc_it == crtc)
4037 continue;
4038
4039 if (other_active_crtc)
4040 return;
4041
4042 other_active_crtc = crtc_it;
4043 }
4044 if (!other_active_crtc)
4045 return;
4046
4047 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4048 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4049}
4050
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004051static void haswell_crtc_enable(struct drm_crtc *crtc)
4052{
4053 struct drm_device *dev = crtc->dev;
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4056 struct intel_encoder *encoder;
4057 int pipe = intel_crtc->pipe;
Daniel Vetter229fca92014-04-24 23:55:09 +02004058 enum plane plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004059
4060 WARN_ON(!crtc->enabled);
4061
4062 if (intel_crtc->active)
4063 return;
4064
Daniel Vetter229fca92014-04-24 23:55:09 +02004065 if (intel_crtc->config.has_dp_encoder)
4066 intel_dp_set_m_n(intel_crtc);
4067
4068 intel_set_pipe_timings(intel_crtc);
4069
4070 if (intel_crtc->config.has_pch_encoder) {
4071 intel_cpu_transcoder_set_m_n(intel_crtc,
4072 &intel_crtc->config.fdi_m_n);
4073 }
4074
4075 haswell_set_pipeconf(crtc);
4076
4077 intel_set_pipe_csc(crtc);
4078
4079 /* Set up the display plane register */
4080 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4081 POSTING_READ(DSPCNTR(plane));
4082
4083 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4084 crtc->x, crtc->y);
4085
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004086 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004087
4088 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4089 if (intel_crtc->config.has_pch_encoder)
4090 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4091
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004092 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni04945642012-11-01 21:00:59 -02004093 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004094
4095 for_each_encoder_on_crtc(dev, crtc, encoder)
4096 if (encoder->pre_enable)
4097 encoder->pre_enable(encoder);
4098
Paulo Zanoni1f544382012-10-24 11:32:00 -02004099 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004100
Jesse Barnesb074cec2013-04-25 12:55:02 -07004101 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004102
4103 /*
4104 * On ILK+ LUT must be loaded before the pipe is running but with
4105 * clocks enabled
4106 */
4107 intel_crtc_load_lut(crtc);
4108
Paulo Zanoni1f544382012-10-24 11:32:00 -02004109 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004110 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004111
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004112 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004113 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004114
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004115 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004116 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004117
Jani Nikula8807e552013-08-30 19:40:32 +03004118 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004119 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004120 intel_opregion_notify_encoder(encoder, true);
4121 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004122
Paulo Zanonie4916942013-09-20 16:21:19 -03004123 /* If we change the relative order between pipe/planes enabling, we need
4124 * to change the workaround. */
4125 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004126 intel_crtc_enable_planes(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004127}
4128
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004129static void ironlake_pfit_disable(struct intel_crtc *crtc)
4130{
4131 struct drm_device *dev = crtc->base.dev;
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 int pipe = crtc->pipe;
4134
4135 /* To avoid upsetting the power well on haswell only disable the pfit if
4136 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004137 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004138 I915_WRITE(PF_CTL(pipe), 0);
4139 I915_WRITE(PF_WIN_POS(pipe), 0);
4140 I915_WRITE(PF_WIN_SZ(pipe), 0);
4141 }
4142}
4143
Jesse Barnes6be4a602010-09-10 10:26:01 -07004144static void ironlake_crtc_disable(struct drm_crtc *crtc)
4145{
4146 struct drm_device *dev = crtc->dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004149 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004150 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004151 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004152
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004153 if (!intel_crtc->active)
4154 return;
4155
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004156 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004157
Daniel Vetterea9d7582012-07-10 10:42:52 +02004158 for_each_encoder_on_crtc(dev, crtc, encoder)
4159 encoder->disable(encoder);
4160
Daniel Vetterd925c592013-06-05 13:34:04 +02004161 if (intel_crtc->config.has_pch_encoder)
4162 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4163
Jesse Barnesb24e7172011-01-04 15:09:30 -08004164 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004165
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004166 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004167
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004168 for_each_encoder_on_crtc(dev, crtc, encoder)
4169 if (encoder->post_disable)
4170 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004171
Daniel Vetterd925c592013-06-05 13:34:04 +02004172 if (intel_crtc->config.has_pch_encoder) {
4173 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004174
Daniel Vetterd925c592013-06-05 13:34:04 +02004175 ironlake_disable_pch_transcoder(dev_priv, pipe);
4176 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004177
Daniel Vetterd925c592013-06-05 13:34:04 +02004178 if (HAS_PCH_CPT(dev)) {
4179 /* disable TRANS_DP_CTL */
4180 reg = TRANS_DP_CTL(pipe);
4181 temp = I915_READ(reg);
4182 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4183 TRANS_DP_PORT_SEL_MASK);
4184 temp |= TRANS_DP_PORT_SEL_NONE;
4185 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004186
Daniel Vetterd925c592013-06-05 13:34:04 +02004187 /* disable DPLL_SEL */
4188 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004189 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004190 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004191 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004192
4193 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004194 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004195
4196 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004197 }
4198
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004199 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004200 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004201
4202 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004203 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004204 intel_edp_psr_update(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004205 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004206}
4207
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004208static void haswell_crtc_disable(struct drm_crtc *crtc)
4209{
4210 struct drm_device *dev = crtc->dev;
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4213 struct intel_encoder *encoder;
4214 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004215 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004216
4217 if (!intel_crtc->active)
4218 return;
4219
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004220 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004221
Jani Nikula8807e552013-08-30 19:40:32 +03004222 for_each_encoder_on_crtc(dev, crtc, encoder) {
4223 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004224 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004225 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004226
Paulo Zanoni86642812013-04-12 17:57:57 -03004227 if (intel_crtc->config.has_pch_encoder)
4228 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004229 intel_disable_pipe(dev_priv, pipe);
4230
Paulo Zanoniad80a812012-10-24 16:06:19 -02004231 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004232
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004233 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004234
Paulo Zanoni1f544382012-10-24 11:32:00 -02004235 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004236
4237 for_each_encoder_on_crtc(dev, crtc, encoder)
4238 if (encoder->post_disable)
4239 encoder->post_disable(encoder);
4240
Daniel Vetter88adfff2013-03-28 10:42:01 +01004241 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004242 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03004243 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004244 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004245 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004246
4247 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004248 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004249
4250 mutex_lock(&dev->struct_mutex);
4251 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004252 intel_edp_psr_update(dev);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004253 mutex_unlock(&dev->struct_mutex);
4254}
4255
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004256static void ironlake_crtc_off(struct drm_crtc *crtc)
4257{
4258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004259 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004260}
4261
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004262static void haswell_crtc_off(struct drm_crtc *crtc)
4263{
4264 intel_ddi_put_crtc_pll(crtc);
4265}
4266
Jesse Barnes2dd24552013-04-25 12:55:01 -07004267static void i9xx_pfit_enable(struct intel_crtc *crtc)
4268{
4269 struct drm_device *dev = crtc->base.dev;
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 struct intel_crtc_config *pipe_config = &crtc->config;
4272
Daniel Vetter328d8e82013-05-08 10:36:31 +02004273 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004274 return;
4275
Daniel Vetterc0b03412013-05-28 12:05:54 +02004276 /*
4277 * The panel fitter should only be adjusted whilst the pipe is disabled,
4278 * according to register description and PRM.
4279 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004280 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4281 assert_pipe_disabled(dev_priv, crtc->pipe);
4282
Jesse Barnesb074cec2013-04-25 12:55:02 -07004283 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4284 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004285
4286 /* Border color in case we don't scale up to the full screen. Black by
4287 * default, change to something else for debugging. */
4288 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004289}
4290
Imre Deak77d22dc2014-03-05 16:20:52 +02004291#define for_each_power_domain(domain, mask) \
4292 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4293 if ((1 << (domain)) & (mask))
4294
Imre Deak319be8a2014-03-04 19:22:57 +02004295enum intel_display_power_domain
4296intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004297{
Imre Deak319be8a2014-03-04 19:22:57 +02004298 struct drm_device *dev = intel_encoder->base.dev;
4299 struct intel_digital_port *intel_dig_port;
4300
4301 switch (intel_encoder->type) {
4302 case INTEL_OUTPUT_UNKNOWN:
4303 /* Only DDI platforms should ever use this output type */
4304 WARN_ON_ONCE(!HAS_DDI(dev));
4305 case INTEL_OUTPUT_DISPLAYPORT:
4306 case INTEL_OUTPUT_HDMI:
4307 case INTEL_OUTPUT_EDP:
4308 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4309 switch (intel_dig_port->port) {
4310 case PORT_A:
4311 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4312 case PORT_B:
4313 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4314 case PORT_C:
4315 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4316 case PORT_D:
4317 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4318 default:
4319 WARN_ON_ONCE(1);
4320 return POWER_DOMAIN_PORT_OTHER;
4321 }
4322 case INTEL_OUTPUT_ANALOG:
4323 return POWER_DOMAIN_PORT_CRT;
4324 case INTEL_OUTPUT_DSI:
4325 return POWER_DOMAIN_PORT_DSI;
4326 default:
4327 return POWER_DOMAIN_PORT_OTHER;
4328 }
4329}
4330
4331static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4332{
4333 struct drm_device *dev = crtc->dev;
4334 struct intel_encoder *intel_encoder;
4335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4336 enum pipe pipe = intel_crtc->pipe;
4337 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
Imre Deak77d22dc2014-03-05 16:20:52 +02004338 unsigned long mask;
4339 enum transcoder transcoder;
4340
4341 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4342
4343 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4344 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4345 if (pfit_enabled)
4346 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4347
Imre Deak319be8a2014-03-04 19:22:57 +02004348 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4349 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4350
Imre Deak77d22dc2014-03-05 16:20:52 +02004351 return mask;
4352}
4353
4354void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4355 bool enable)
4356{
4357 if (dev_priv->power_domains.init_power_on == enable)
4358 return;
4359
4360 if (enable)
4361 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4362 else
4363 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4364
4365 dev_priv->power_domains.init_power_on = enable;
4366}
4367
4368static void modeset_update_crtc_power_domains(struct drm_device *dev)
4369{
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4372 struct intel_crtc *crtc;
4373
4374 /*
4375 * First get all needed power domains, then put all unneeded, to avoid
4376 * any unnecessary toggling of the power wells.
4377 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004378 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004379 enum intel_display_power_domain domain;
4380
4381 if (!crtc->base.enabled)
4382 continue;
4383
Imre Deak319be8a2014-03-04 19:22:57 +02004384 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004385
4386 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4387 intel_display_power_get(dev_priv, domain);
4388 }
4389
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004390 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004391 enum intel_display_power_domain domain;
4392
4393 for_each_power_domain(domain, crtc->enabled_power_domains)
4394 intel_display_power_put(dev_priv, domain);
4395
4396 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4397 }
4398
4399 intel_display_set_init_power(dev_priv, false);
4400}
4401
Jesse Barnes586f49d2013-11-04 16:06:59 -08004402int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004403{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004404 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004405
Jesse Barnes586f49d2013-11-04 16:06:59 -08004406 /* Obtain SKU information */
4407 mutex_lock(&dev_priv->dpio_lock);
4408 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4409 CCK_FUSE_HPLL_FREQ_MASK;
4410 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004411
Jesse Barnes586f49d2013-11-04 16:06:59 -08004412 return vco_freq[hpll_freq];
Jesse Barnes30a970c2013-11-04 13:48:12 -08004413}
4414
4415/* Adjust CDclk dividers to allow high res or save power if possible */
4416static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4417{
4418 struct drm_i915_private *dev_priv = dev->dev_private;
4419 u32 val, cmd;
4420
Imre Deakd60c4472014-03-27 17:45:10 +02004421 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4422 dev_priv->vlv_cdclk_freq = cdclk;
4423
Jesse Barnes30a970c2013-11-04 13:48:12 -08004424 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4425 cmd = 2;
4426 else if (cdclk == 266)
4427 cmd = 1;
4428 else
4429 cmd = 0;
4430
4431 mutex_lock(&dev_priv->rps.hw_lock);
4432 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4433 val &= ~DSPFREQGUAR_MASK;
4434 val |= (cmd << DSPFREQGUAR_SHIFT);
4435 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4436 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4437 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4438 50)) {
4439 DRM_ERROR("timed out waiting for CDclk change\n");
4440 }
4441 mutex_unlock(&dev_priv->rps.hw_lock);
4442
4443 if (cdclk == 400) {
4444 u32 divider, vco;
4445
4446 vco = valleyview_get_vco(dev_priv);
4447 divider = ((vco << 1) / cdclk) - 1;
4448
4449 mutex_lock(&dev_priv->dpio_lock);
4450 /* adjust cdclk divider */
4451 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4452 val &= ~0xf;
4453 val |= divider;
4454 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4455 mutex_unlock(&dev_priv->dpio_lock);
4456 }
4457
4458 mutex_lock(&dev_priv->dpio_lock);
4459 /* adjust self-refresh exit latency value */
4460 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4461 val &= ~0x7f;
4462
4463 /*
4464 * For high bandwidth configs, we set a higher latency in the bunit
4465 * so that the core display fetch happens in time to avoid underruns.
4466 */
4467 if (cdclk == 400)
4468 val |= 4500 / 250; /* 4.5 usec */
4469 else
4470 val |= 3000 / 250; /* 3.0 usec */
4471 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4472 mutex_unlock(&dev_priv->dpio_lock);
4473
4474 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4475 intel_i2c_reset(dev);
4476}
4477
Imre Deakd60c4472014-03-27 17:45:10 +02004478int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004479{
4480 int cur_cdclk, vco;
4481 int divider;
4482
4483 vco = valleyview_get_vco(dev_priv);
4484
4485 mutex_lock(&dev_priv->dpio_lock);
4486 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4487 mutex_unlock(&dev_priv->dpio_lock);
4488
4489 divider &= 0xf;
4490
4491 cur_cdclk = (vco << 1) / (divider + 1);
4492
4493 return cur_cdclk;
4494}
4495
4496static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4497 int max_pixclk)
4498{
Jesse Barnes30a970c2013-11-04 13:48:12 -08004499 /*
4500 * Really only a few cases to deal with, as only 4 CDclks are supported:
4501 * 200MHz
4502 * 267MHz
4503 * 320MHz
4504 * 400MHz
4505 * So we check to see whether we're above 90% of the lower bin and
4506 * adjust if needed.
4507 */
4508 if (max_pixclk > 288000) {
4509 return 400;
4510 } else if (max_pixclk > 240000) {
4511 return 320;
4512 } else
4513 return 266;
4514 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4515}
4516
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004517/* compute the max pixel clock for new configuration */
4518static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004519{
4520 struct drm_device *dev = dev_priv->dev;
4521 struct intel_crtc *intel_crtc;
4522 int max_pixclk = 0;
4523
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004524 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004525 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004526 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004527 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004528 }
4529
4530 return max_pixclk;
4531}
4532
4533static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004534 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004535{
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004538 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004539
Imre Deakd60c4472014-03-27 17:45:10 +02004540 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4541 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004542 return;
4543
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004544 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004545 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004546 if (intel_crtc->base.enabled)
4547 *prepare_pipes |= (1 << intel_crtc->pipe);
4548}
4549
4550static void valleyview_modeset_global_resources(struct drm_device *dev)
4551{
4552 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004553 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004554 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4555
Imre Deakd60c4472014-03-27 17:45:10 +02004556 if (req_cdclk != dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004557 valleyview_set_cdclk(dev, req_cdclk);
Imre Deak77961eb2014-03-05 16:20:56 +02004558 modeset_update_crtc_power_domains(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004559}
4560
Jesse Barnes89b667f2013-04-18 14:51:36 -07004561static void valleyview_crtc_enable(struct drm_crtc *crtc)
4562{
4563 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004564 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4566 struct intel_encoder *encoder;
4567 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004568 int plane = intel_crtc->plane;
Jani Nikula23538ef2013-08-27 15:12:22 +03004569 bool is_dsi;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004570 u32 dspcntr;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004571
4572 WARN_ON(!crtc->enabled);
4573
4574 if (intel_crtc->active)
4575 return;
4576
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02004577 vlv_prepare_pll(intel_crtc);
4578
Daniel Vetter5b18e572014-04-24 23:55:06 +02004579 /* Set up the display plane register */
4580 dspcntr = DISPPLANE_GAMMA_ENABLE;
4581
4582 if (intel_crtc->config.has_dp_encoder)
4583 intel_dp_set_m_n(intel_crtc);
4584
4585 intel_set_pipe_timings(intel_crtc);
4586
4587 /* pipesrc and dspsize control the size that is scaled from,
4588 * which should always be the user's requested size.
4589 */
4590 I915_WRITE(DSPSIZE(plane),
4591 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4592 (intel_crtc->config.pipe_src_w - 1));
4593 I915_WRITE(DSPPOS(plane), 0);
4594
4595 i9xx_set_pipeconf(intel_crtc);
4596
4597 I915_WRITE(DSPCNTR(plane), dspcntr);
4598 POSTING_READ(DSPCNTR(plane));
4599
4600 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4601 crtc->x, crtc->y);
4602
Jesse Barnes89b667f2013-04-18 14:51:36 -07004603 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004604
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004605 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4606
Jesse Barnes89b667f2013-04-18 14:51:36 -07004607 for_each_encoder_on_crtc(dev, crtc, encoder)
4608 if (encoder->pre_pll_enable)
4609 encoder->pre_pll_enable(encoder);
4610
Jani Nikula23538ef2013-08-27 15:12:22 +03004611 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4612
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004613 if (!is_dsi) {
4614 if (IS_CHERRYVIEW(dev))
4615 chv_enable_pll(intel_crtc);
4616 else
4617 vlv_enable_pll(intel_crtc);
4618 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004619
4620 for_each_encoder_on_crtc(dev, crtc, encoder)
4621 if (encoder->pre_enable)
4622 encoder->pre_enable(encoder);
4623
Jesse Barnes2dd24552013-04-25 12:55:01 -07004624 i9xx_pfit_enable(intel_crtc);
4625
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004626 intel_crtc_load_lut(crtc);
4627
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004628 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004629 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004630
Jani Nikula50049452013-07-30 12:20:32 +03004631 for_each_encoder_on_crtc(dev, crtc, encoder)
4632 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004633
4634 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004635
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004636 /* Underruns don't raise interrupts, so check manually. */
4637 i9xx_check_fifo_underruns(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004638}
4639
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004640static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4641{
4642 struct drm_device *dev = crtc->base.dev;
4643 struct drm_i915_private *dev_priv = dev->dev_private;
4644
4645 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4646 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4647}
4648
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004649static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004650{
4651 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004652 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08004653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004654 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004655 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004656 int plane = intel_crtc->plane;
4657 u32 dspcntr;
Jesse Barnes79e53942008-11-07 14:24:08 -08004658
Daniel Vetter08a48462012-07-02 11:43:47 +02004659 WARN_ON(!crtc->enabled);
4660
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004661 if (intel_crtc->active)
4662 return;
4663
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004664 i9xx_set_pll_dividers(intel_crtc);
4665
Daniel Vetter5b18e572014-04-24 23:55:06 +02004666 /* Set up the display plane register */
4667 dspcntr = DISPPLANE_GAMMA_ENABLE;
4668
4669 if (pipe == 0)
4670 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4671 else
4672 dspcntr |= DISPPLANE_SEL_PIPE_B;
4673
4674 if (intel_crtc->config.has_dp_encoder)
4675 intel_dp_set_m_n(intel_crtc);
4676
4677 intel_set_pipe_timings(intel_crtc);
4678
4679 /* pipesrc and dspsize control the size that is scaled from,
4680 * which should always be the user's requested size.
4681 */
4682 I915_WRITE(DSPSIZE(plane),
4683 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4684 (intel_crtc->config.pipe_src_w - 1));
4685 I915_WRITE(DSPPOS(plane), 0);
4686
4687 i9xx_set_pipeconf(intel_crtc);
4688
4689 I915_WRITE(DSPCNTR(plane), dspcntr);
4690 POSTING_READ(DSPCNTR(plane));
4691
4692 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4693 crtc->x, crtc->y);
4694
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004695 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004696
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004697 if (!IS_GEN2(dev))
4698 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4699
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004700 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004701 if (encoder->pre_enable)
4702 encoder->pre_enable(encoder);
4703
Daniel Vetterf6736a12013-06-05 13:34:30 +02004704 i9xx_enable_pll(intel_crtc);
4705
Jesse Barnes2dd24552013-04-25 12:55:01 -07004706 i9xx_pfit_enable(intel_crtc);
4707
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004708 intel_crtc_load_lut(crtc);
4709
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004710 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004711 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004712
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004713 for_each_encoder_on_crtc(dev, crtc, encoder)
4714 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004715
4716 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004717
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004718 /*
4719 * Gen2 reports pipe underruns whenever all planes are disabled.
4720 * So don't enable underrun reporting before at least some planes
4721 * are enabled.
4722 * FIXME: Need to fix the logic to work when we turn off all planes
4723 * but leave the pipe running.
4724 */
4725 if (IS_GEN2(dev))
4726 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4727
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004728 /* Underruns don't raise interrupts, so check manually. */
4729 i9xx_check_fifo_underruns(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004730}
4731
Daniel Vetter87476d62013-04-11 16:29:06 +02004732static void i9xx_pfit_disable(struct intel_crtc *crtc)
4733{
4734 struct drm_device *dev = crtc->base.dev;
4735 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004736
4737 if (!crtc->config.gmch_pfit.control)
4738 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004739
4740 assert_pipe_disabled(dev_priv, crtc->pipe);
4741
Daniel Vetter328d8e82013-05-08 10:36:31 +02004742 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4743 I915_READ(PFIT_CONTROL));
4744 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004745}
4746
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004747static void i9xx_crtc_disable(struct drm_crtc *crtc)
4748{
4749 struct drm_device *dev = crtc->dev;
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004752 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004753 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004754
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004755 if (!intel_crtc->active)
4756 return;
4757
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004758 /*
4759 * Gen2 reports pipe underruns whenever all planes are disabled.
4760 * So diasble underrun reporting before all the planes get disabled.
4761 * FIXME: Need to fix the logic to work when we turn off all planes
4762 * but leave the pipe running.
4763 */
4764 if (IS_GEN2(dev))
4765 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4766
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004767 intel_crtc_disable_planes(crtc);
4768
Daniel Vetterea9d7582012-07-10 10:42:52 +02004769 for_each_encoder_on_crtc(dev, crtc, encoder)
4770 encoder->disable(encoder);
4771
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004772 /*
4773 * On gen2 planes are double buffered but the pipe isn't, so we must
4774 * wait for planes to fully turn off before disabling the pipe.
4775 */
4776 if (IS_GEN2(dev))
4777 intel_wait_for_vblank(dev, pipe);
4778
Jesse Barnesb24e7172011-01-04 15:09:30 -08004779 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004780
Daniel Vetter87476d62013-04-11 16:29:06 +02004781 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004782
Jesse Barnes89b667f2013-04-18 14:51:36 -07004783 for_each_encoder_on_crtc(dev, crtc, encoder)
4784 if (encoder->post_disable)
4785 encoder->post_disable(encoder);
4786
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03004787 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4788 if (IS_CHERRYVIEW(dev))
4789 chv_disable_pll(dev_priv, pipe);
4790 else if (IS_VALLEYVIEW(dev))
4791 vlv_disable_pll(dev_priv, pipe);
4792 else
4793 i9xx_disable_pll(dev_priv, pipe);
4794 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004795
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004796 if (!IS_GEN2(dev))
4797 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4798
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004799 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004800 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004801
Daniel Vetterefa96242014-04-24 23:55:02 +02004802 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004803 intel_update_fbc(dev);
Daniel Vetter71b1c372014-04-24 23:55:03 +02004804 intel_edp_psr_update(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02004805 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004806}
4807
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004808static void i9xx_crtc_off(struct drm_crtc *crtc)
4809{
4810}
4811
Daniel Vetter976f8a22012-07-08 22:34:21 +02004812static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4813 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004814{
4815 struct drm_device *dev = crtc->dev;
4816 struct drm_i915_master_private *master_priv;
4817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4818 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004819
4820 if (!dev->primary->master)
4821 return;
4822
4823 master_priv = dev->primary->master->driver_priv;
4824 if (!master_priv->sarea_priv)
4825 return;
4826
Jesse Barnes79e53942008-11-07 14:24:08 -08004827 switch (pipe) {
4828 case 0:
4829 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4830 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4831 break;
4832 case 1:
4833 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4834 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4835 break;
4836 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004837 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004838 break;
4839 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004840}
4841
Daniel Vetter976f8a22012-07-08 22:34:21 +02004842/**
4843 * Sets the power management mode of the pipe and plane.
4844 */
4845void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004846{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004847 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004848 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004849 struct intel_encoder *intel_encoder;
4850 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004851
Daniel Vetter976f8a22012-07-08 22:34:21 +02004852 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4853 enable |= intel_encoder->connectors_active;
4854
4855 if (enable)
4856 dev_priv->display.crtc_enable(crtc);
4857 else
4858 dev_priv->display.crtc_disable(crtc);
4859
4860 intel_crtc_update_sarea(crtc, enable);
4861}
4862
Daniel Vetter976f8a22012-07-08 22:34:21 +02004863static void intel_crtc_disable(struct drm_crtc *crtc)
4864{
4865 struct drm_device *dev = crtc->dev;
4866 struct drm_connector *connector;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868
4869 /* crtc should still be enabled when we disable it. */
4870 WARN_ON(!crtc->enabled);
4871
4872 dev_priv->display.crtc_disable(crtc);
4873 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004874 dev_priv->display.off(crtc);
4875
Chris Wilson931872f2012-01-16 23:01:13 +00004876 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03004877 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Chris Wilson931872f2012-01-16 23:01:13 +00004878 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004879
Matt Roperf4510a22014-04-01 15:22:40 -07004880 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01004881 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004882 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004883 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004884 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004885 }
4886
4887 /* Update computed state. */
4888 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4889 if (!connector->encoder || !connector->encoder->crtc)
4890 continue;
4891
4892 if (connector->encoder->crtc != crtc)
4893 continue;
4894
4895 connector->dpms = DRM_MODE_DPMS_OFF;
4896 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004897 }
4898}
4899
Chris Wilsonea5b2132010-08-04 13:50:23 +01004900void intel_encoder_destroy(struct drm_encoder *encoder)
4901{
Chris Wilson4ef69c72010-09-09 15:14:28 +01004902 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01004903
Chris Wilsonea5b2132010-08-04 13:50:23 +01004904 drm_encoder_cleanup(encoder);
4905 kfree(intel_encoder);
4906}
4907
Damien Lespiau92373292013-08-08 22:28:57 +01004908/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004909 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4910 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01004911static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004912{
4913 if (mode == DRM_MODE_DPMS_ON) {
4914 encoder->connectors_active = true;
4915
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004916 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004917 } else {
4918 encoder->connectors_active = false;
4919
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004920 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004921 }
4922}
4923
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004924/* Cross check the actual hw state with our own modeset state tracking (and it's
4925 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02004926static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004927{
4928 if (connector->get_hw_state(connector)) {
4929 struct intel_encoder *encoder = connector->encoder;
4930 struct drm_crtc *crtc;
4931 bool encoder_enabled;
4932 enum pipe pipe;
4933
4934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4935 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03004936 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004937
4938 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4939 "wrong connector dpms state\n");
4940 WARN(connector->base.encoder != &encoder->base,
4941 "active connector not linked to encoder\n");
4942 WARN(!encoder->connectors_active,
4943 "encoder->connectors_active not set\n");
4944
4945 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4946 WARN(!encoder_enabled, "encoder not enabled\n");
4947 if (WARN_ON(!encoder->base.crtc))
4948 return;
4949
4950 crtc = encoder->base.crtc;
4951
4952 WARN(!crtc->enabled, "crtc not enabled\n");
4953 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4954 WARN(pipe != to_intel_crtc(crtc)->pipe,
4955 "encoder active on the wrong pipe\n");
4956 }
4957}
4958
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004959/* Even simpler default implementation, if there's really no special case to
4960 * consider. */
4961void intel_connector_dpms(struct drm_connector *connector, int mode)
4962{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004963 /* All the simple cases only support two dpms states. */
4964 if (mode != DRM_MODE_DPMS_ON)
4965 mode = DRM_MODE_DPMS_OFF;
4966
4967 if (mode == connector->dpms)
4968 return;
4969
4970 connector->dpms = mode;
4971
4972 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01004973 if (connector->encoder)
4974 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004975
Daniel Vetterb9805142012-08-31 17:37:33 +02004976 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004977}
4978
Daniel Vetterf0947c32012-07-02 13:10:34 +02004979/* Simple connector->get_hw_state implementation for encoders that support only
4980 * one connector and no cloning and hence the encoder state determines the state
4981 * of the connector. */
4982bool intel_connector_get_hw_state(struct intel_connector *connector)
4983{
Daniel Vetter24929352012-07-02 20:28:59 +02004984 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02004985 struct intel_encoder *encoder = connector->encoder;
4986
4987 return encoder->get_hw_state(encoder, &pipe);
4988}
4989
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004990static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4991 struct intel_crtc_config *pipe_config)
4992{
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 struct intel_crtc *pipe_B_crtc =
4995 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4996
4997 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4998 pipe_name(pipe), pipe_config->fdi_lanes);
4999 if (pipe_config->fdi_lanes > 4) {
5000 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5001 pipe_name(pipe), pipe_config->fdi_lanes);
5002 return false;
5003 }
5004
Paulo Zanonibafb6552013-11-02 21:07:44 -07005005 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005006 if (pipe_config->fdi_lanes > 2) {
5007 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5008 pipe_config->fdi_lanes);
5009 return false;
5010 } else {
5011 return true;
5012 }
5013 }
5014
5015 if (INTEL_INFO(dev)->num_pipes == 2)
5016 return true;
5017
5018 /* Ivybridge 3 pipe is really complicated */
5019 switch (pipe) {
5020 case PIPE_A:
5021 return true;
5022 case PIPE_B:
5023 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5024 pipe_config->fdi_lanes > 2) {
5025 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5026 pipe_name(pipe), pipe_config->fdi_lanes);
5027 return false;
5028 }
5029 return true;
5030 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005031 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005032 pipe_B_crtc->config.fdi_lanes <= 2) {
5033 if (pipe_config->fdi_lanes > 2) {
5034 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5035 pipe_name(pipe), pipe_config->fdi_lanes);
5036 return false;
5037 }
5038 } else {
5039 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5040 return false;
5041 }
5042 return true;
5043 default:
5044 BUG();
5045 }
5046}
5047
Daniel Vettere29c22c2013-02-21 00:00:16 +01005048#define RETRY 1
5049static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5050 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005051{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005052 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005053 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005054 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005055 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005056
Daniel Vettere29c22c2013-02-21 00:00:16 +01005057retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005058 /* FDI is a binary signal running at ~2.7GHz, encoding
5059 * each output octet as 10 bits. The actual frequency
5060 * is stored as a divider into a 100MHz clock, and the
5061 * mode pixel clock is stored in units of 1KHz.
5062 * Hence the bw of each lane in terms of the mode signal
5063 * is:
5064 */
5065 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5066
Damien Lespiau241bfc32013-09-25 16:45:37 +01005067 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005068
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005069 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005070 pipe_config->pipe_bpp);
5071
5072 pipe_config->fdi_lanes = lane;
5073
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005074 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005075 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005076
Daniel Vettere29c22c2013-02-21 00:00:16 +01005077 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5078 intel_crtc->pipe, pipe_config);
5079 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5080 pipe_config->pipe_bpp -= 2*3;
5081 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5082 pipe_config->pipe_bpp);
5083 needs_recompute = true;
5084 pipe_config->bw_constrained = true;
5085
5086 goto retry;
5087 }
5088
5089 if (needs_recompute)
5090 return RETRY;
5091
5092 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005093}
5094
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005095static void hsw_compute_ips_config(struct intel_crtc *crtc,
5096 struct intel_crtc_config *pipe_config)
5097{
Jani Nikulad330a952014-01-21 11:24:25 +02005098 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005099 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005100 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005101}
5102
Daniel Vettera43f6e02013-06-07 23:10:32 +02005103static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005104 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005105{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005106 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005107 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005108
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005109 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005110 if (INTEL_INFO(dev)->gen < 4) {
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112 int clock_limit =
5113 dev_priv->display.get_display_clock_speed(dev);
5114
5115 /*
5116 * Enable pixel doubling when the dot clock
5117 * is > 90% of the (display) core speed.
5118 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005119 * GDG double wide on either pipe,
5120 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005121 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005122 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005123 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005124 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005125 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005126 }
5127
Damien Lespiau241bfc32013-09-25 16:45:37 +01005128 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005129 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005130 }
Chris Wilson89749352010-09-12 18:25:19 +01005131
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005132 /*
5133 * Pipe horizontal size must be even in:
5134 * - DVO ganged mode
5135 * - LVDS dual channel mode
5136 * - Double wide pipe
5137 */
5138 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5139 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5140 pipe_config->pipe_src_w &= ~1;
5141
Damien Lespiau8693a822013-05-03 18:48:11 +01005142 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5143 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005144 */
5145 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5146 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005147 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005148
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005149 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005150 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005151 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005152 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5153 * for lvds. */
5154 pipe_config->pipe_bpp = 8*3;
5155 }
5156
Damien Lespiauf5adf942013-06-24 18:29:34 +01005157 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005158 hsw_compute_ips_config(crtc, pipe_config);
5159
5160 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5161 * clock survives for now. */
5162 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5163 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005164
Daniel Vetter877d48d2013-04-19 11:24:43 +02005165 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005166 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005167
Daniel Vettere29c22c2013-02-21 00:00:16 +01005168 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005169}
5170
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005171static int valleyview_get_display_clock_speed(struct drm_device *dev)
5172{
5173 return 400000; /* FIXME */
5174}
5175
Jesse Barnese70236a2009-09-21 10:42:27 -07005176static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005177{
Jesse Barnese70236a2009-09-21 10:42:27 -07005178 return 400000;
5179}
Jesse Barnes79e53942008-11-07 14:24:08 -08005180
Jesse Barnese70236a2009-09-21 10:42:27 -07005181static int i915_get_display_clock_speed(struct drm_device *dev)
5182{
5183 return 333000;
5184}
Jesse Barnes79e53942008-11-07 14:24:08 -08005185
Jesse Barnese70236a2009-09-21 10:42:27 -07005186static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5187{
5188 return 200000;
5189}
Jesse Barnes79e53942008-11-07 14:24:08 -08005190
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005191static int pnv_get_display_clock_speed(struct drm_device *dev)
5192{
5193 u16 gcfgc = 0;
5194
5195 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5196
5197 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5198 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5199 return 267000;
5200 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5201 return 333000;
5202 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5203 return 444000;
5204 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5205 return 200000;
5206 default:
5207 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5208 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5209 return 133000;
5210 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5211 return 167000;
5212 }
5213}
5214
Jesse Barnese70236a2009-09-21 10:42:27 -07005215static int i915gm_get_display_clock_speed(struct drm_device *dev)
5216{
5217 u16 gcfgc = 0;
5218
5219 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5220
5221 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005222 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005223 else {
5224 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5225 case GC_DISPLAY_CLOCK_333_MHZ:
5226 return 333000;
5227 default:
5228 case GC_DISPLAY_CLOCK_190_200_MHZ:
5229 return 190000;
5230 }
5231 }
5232}
Jesse Barnes79e53942008-11-07 14:24:08 -08005233
Jesse Barnese70236a2009-09-21 10:42:27 -07005234static int i865_get_display_clock_speed(struct drm_device *dev)
5235{
5236 return 266000;
5237}
5238
5239static int i855_get_display_clock_speed(struct drm_device *dev)
5240{
5241 u16 hpllcc = 0;
5242 /* Assume that the hardware is in the high speed state. This
5243 * should be the default.
5244 */
5245 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5246 case GC_CLOCK_133_200:
5247 case GC_CLOCK_100_200:
5248 return 200000;
5249 case GC_CLOCK_166_250:
5250 return 250000;
5251 case GC_CLOCK_100_133:
5252 return 133000;
5253 }
5254
5255 /* Shouldn't happen */
5256 return 0;
5257}
5258
5259static int i830_get_display_clock_speed(struct drm_device *dev)
5260{
5261 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005262}
5263
Zhenyu Wang2c072452009-06-05 15:38:42 +08005264static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005265intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005266{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005267 while (*num > DATA_LINK_M_N_MASK ||
5268 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005269 *num >>= 1;
5270 *den >>= 1;
5271 }
5272}
5273
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005274static void compute_m_n(unsigned int m, unsigned int n,
5275 uint32_t *ret_m, uint32_t *ret_n)
5276{
5277 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5278 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5279 intel_reduce_m_n_ratio(ret_m, ret_n);
5280}
5281
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005282void
5283intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5284 int pixel_clock, int link_clock,
5285 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005286{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005287 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005288
5289 compute_m_n(bits_per_pixel * pixel_clock,
5290 link_clock * nlanes * 8,
5291 &m_n->gmch_m, &m_n->gmch_n);
5292
5293 compute_m_n(pixel_clock, link_clock,
5294 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005295}
5296
Chris Wilsona7615032011-01-12 17:04:08 +00005297static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5298{
Jani Nikulad330a952014-01-21 11:24:25 +02005299 if (i915.panel_use_ssc >= 0)
5300 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005301 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005302 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005303}
5304
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005305static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5306{
5307 struct drm_device *dev = crtc->dev;
5308 struct drm_i915_private *dev_priv = dev->dev_private;
5309 int refclk;
5310
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005311 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005312 refclk = 100000;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005313 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005314 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005315 refclk = dev_priv->vbt.lvds_ssc_freq;
5316 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005317 } else if (!IS_GEN2(dev)) {
5318 refclk = 96000;
5319 } else {
5320 refclk = 48000;
5321 }
5322
5323 return refclk;
5324}
5325
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005326static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005327{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005328 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005329}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005330
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005331static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5332{
5333 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005334}
5335
Daniel Vetterf47709a2013-03-28 10:42:02 +01005336static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005337 intel_clock_t *reduced_clock)
5338{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005339 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005340 u32 fp, fp2 = 0;
5341
5342 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005343 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005344 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005345 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005346 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005347 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005348 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005349 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005350 }
5351
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005352 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005353
Daniel Vetterf47709a2013-03-28 10:42:02 +01005354 crtc->lowfreq_avail = false;
5355 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005356 reduced_clock && i915.powersave) {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005357 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005358 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005359 } else {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005360 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005361 }
5362}
5363
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005364static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5365 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005366{
5367 u32 reg_val;
5368
5369 /*
5370 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5371 * and set it to a reasonable value instead.
5372 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005373 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005374 reg_val &= 0xffffff00;
5375 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005376 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005377
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005378 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005379 reg_val &= 0x8cffffff;
5380 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005381 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005382
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005383 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005384 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005386
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005387 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005388 reg_val &= 0x00ffffff;
5389 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005390 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005391}
5392
Daniel Vetterb5518422013-05-03 11:49:48 +02005393static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5394 struct intel_link_m_n *m_n)
5395{
5396 struct drm_device *dev = crtc->base.dev;
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398 int pipe = crtc->pipe;
5399
Daniel Vettere3b95f12013-05-03 11:49:49 +02005400 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5401 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5402 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5403 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005404}
5405
5406static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5407 struct intel_link_m_n *m_n)
5408{
5409 struct drm_device *dev = crtc->base.dev;
5410 struct drm_i915_private *dev_priv = dev->dev_private;
5411 int pipe = crtc->pipe;
5412 enum transcoder transcoder = crtc->config.cpu_transcoder;
5413
5414 if (INTEL_INFO(dev)->gen >= 5) {
5415 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5416 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5417 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5418 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5419 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005420 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5421 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5422 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5423 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005424 }
5425}
5426
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005427static void intel_dp_set_m_n(struct intel_crtc *crtc)
5428{
5429 if (crtc->config.has_pch_encoder)
5430 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5431 else
5432 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5433}
5434
Daniel Vetterf47709a2013-03-28 10:42:02 +01005435static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005436{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005437 u32 dpll, dpll_md;
5438
5439 /*
5440 * Enable DPIO clock input. We should never disable the reference
5441 * clock for pipe B, since VGA hotplug / manual detection depends
5442 * on it.
5443 */
5444 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5445 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5446 /* We should never disable this, set it here for state tracking */
5447 if (crtc->pipe == PIPE_B)
5448 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5449 dpll |= DPLL_VCO_ENABLE;
5450 crtc->config.dpll_hw_state.dpll = dpll;
5451
5452 dpll_md = (crtc->config.pixel_multiplier - 1)
5453 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5454 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5455}
5456
5457static void vlv_prepare_pll(struct intel_crtc *crtc)
5458{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005459 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005460 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005461 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005462 u32 mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005463 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005464 u32 coreclk, reg_val;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005465
Daniel Vetter09153002012-12-12 14:06:44 +01005466 mutex_lock(&dev_priv->dpio_lock);
5467
Daniel Vetterf47709a2013-03-28 10:42:02 +01005468 bestn = crtc->config.dpll.n;
5469 bestm1 = crtc->config.dpll.m1;
5470 bestm2 = crtc->config.dpll.m2;
5471 bestp1 = crtc->config.dpll.p1;
5472 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005473
Jesse Barnes89b667f2013-04-18 14:51:36 -07005474 /* See eDP HDMI DPIO driver vbios notes doc */
5475
5476 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005477 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005478 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005479
5480 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005481 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005482
5483 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005484 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005485 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005486 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005487
5488 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005489 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005490
5491 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005492 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5493 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5494 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005495 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005496
5497 /*
5498 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5499 * but we don't support that).
5500 * Note: don't use the DAC post divider as it seems unstable.
5501 */
5502 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005503 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005504
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005505 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005506 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005507
Jesse Barnes89b667f2013-04-18 14:51:36 -07005508 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02005509 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03005510 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07005511 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005512 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03005513 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005514 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005515 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005516 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005517
Jesse Barnes89b667f2013-04-18 14:51:36 -07005518 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5519 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5520 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005521 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005522 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005523 0x0df40000);
5524 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005525 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005526 0x0df70000);
5527 } else { /* HDMI or VGA */
5528 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005529 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005530 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005531 0x0df70000);
5532 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005533 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005534 0x0df40000);
5535 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005536
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005537 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005538 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5539 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5540 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5541 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005542 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005543
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005544 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005545 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005546}
5547
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005548static void chv_update_pll(struct intel_crtc *crtc)
5549{
5550 struct drm_device *dev = crtc->base.dev;
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552 int pipe = crtc->pipe;
5553 int dpll_reg = DPLL(crtc->pipe);
5554 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005555 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005556 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5557 int refclk;
5558
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005559 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5560 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5561 DPLL_VCO_ENABLE;
5562 if (pipe != PIPE_A)
5563 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5564
5565 crtc->config.dpll_hw_state.dpll_md =
5566 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005567
5568 bestn = crtc->config.dpll.n;
5569 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5570 bestm1 = crtc->config.dpll.m1;
5571 bestm2 = crtc->config.dpll.m2 >> 22;
5572 bestp1 = crtc->config.dpll.p1;
5573 bestp2 = crtc->config.dpll.p2;
5574
5575 /*
5576 * Enable Refclk and SSC
5577 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005578 I915_WRITE(dpll_reg,
5579 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5580
5581 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005582
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005583 /* p1 and p2 divider */
5584 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5585 5 << DPIO_CHV_S1_DIV_SHIFT |
5586 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5587 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5588 1 << DPIO_CHV_K_DIV_SHIFT);
5589
5590 /* Feedback post-divider - m2 */
5591 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5592
5593 /* Feedback refclk divider - n and m1 */
5594 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5595 DPIO_CHV_M1_DIV_BY_2 |
5596 1 << DPIO_CHV_N_DIV_SHIFT);
5597
5598 /* M2 fraction division */
5599 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5600
5601 /* M2 fraction division enable */
5602 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5603 DPIO_CHV_FRAC_DIV_EN |
5604 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5605
5606 /* Loop filter */
5607 refclk = i9xx_get_refclk(&crtc->base, 0);
5608 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5609 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5610 if (refclk == 100000)
5611 intcoeff = 11;
5612 else if (refclk == 38400)
5613 intcoeff = 10;
5614 else
5615 intcoeff = 9;
5616 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5617 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5618
5619 /* AFC Recal */
5620 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5621 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5622 DPIO_AFC_RECAL);
5623
5624 mutex_unlock(&dev_priv->dpio_lock);
5625}
5626
Daniel Vetterf47709a2013-03-28 10:42:02 +01005627static void i9xx_update_pll(struct intel_crtc *crtc,
5628 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005629 int num_connectors)
5630{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005631 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005632 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005633 u32 dpll;
5634 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005635 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005636
Daniel Vetterf47709a2013-03-28 10:42:02 +01005637 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305638
Daniel Vetterf47709a2013-03-28 10:42:02 +01005639 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5640 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005641
5642 dpll = DPLL_VGA_MODE_DIS;
5643
Daniel Vetterf47709a2013-03-28 10:42:02 +01005644 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005645 dpll |= DPLLB_MODE_LVDS;
5646 else
5647 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005648
Daniel Vetteref1b4602013-06-01 17:17:04 +02005649 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02005650 dpll |= (crtc->config.pixel_multiplier - 1)
5651 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005652 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02005653
5654 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02005655 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005656
Daniel Vetterf47709a2013-03-28 10:42:02 +01005657 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02005658 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005659
5660 /* compute bitmask from p1 value */
5661 if (IS_PINEVIEW(dev))
5662 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5663 else {
5664 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5665 if (IS_G4X(dev) && reduced_clock)
5666 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5667 }
5668 switch (clock->p2) {
5669 case 5:
5670 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5671 break;
5672 case 7:
5673 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5674 break;
5675 case 10:
5676 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5677 break;
5678 case 14:
5679 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5680 break;
5681 }
5682 if (INTEL_INFO(dev)->gen >= 4)
5683 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5684
Daniel Vetter09ede542013-04-30 14:01:45 +02005685 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005686 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005687 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005688 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5689 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5690 else
5691 dpll |= PLL_REF_INPUT_DREFCLK;
5692
5693 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005694 crtc->config.dpll_hw_state.dpll = dpll;
5695
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005696 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005697 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5698 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005699 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005700 }
5701}
5702
Daniel Vetterf47709a2013-03-28 10:42:02 +01005703static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005704 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005705 int num_connectors)
5706{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005707 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005708 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005709 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005710 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005711
Daniel Vetterf47709a2013-03-28 10:42:02 +01005712 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305713
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005714 dpll = DPLL_VGA_MODE_DIS;
5715
Daniel Vetterf47709a2013-03-28 10:42:02 +01005716 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005717 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5718 } else {
5719 if (clock->p1 == 2)
5720 dpll |= PLL_P1_DIVIDE_BY_TWO;
5721 else
5722 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5723 if (clock->p2 == 4)
5724 dpll |= PLL_P2_DIVIDE_BY_4;
5725 }
5726
Daniel Vetter4a33e482013-07-06 12:52:05 +02005727 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5728 dpll |= DPLL_DVO_2X_MODE;
5729
Daniel Vetterf47709a2013-03-28 10:42:02 +01005730 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005731 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5732 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5733 else
5734 dpll |= PLL_REF_INPUT_DREFCLK;
5735
5736 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005737 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005738}
5739
Daniel Vetter8a654f32013-06-01 17:16:22 +02005740static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005741{
5742 struct drm_device *dev = intel_crtc->base.dev;
5743 struct drm_i915_private *dev_priv = dev->dev_private;
5744 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005745 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005746 struct drm_display_mode *adjusted_mode =
5747 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005748 uint32_t crtc_vtotal, crtc_vblank_end;
5749 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005750
5751 /* We need to be careful not to changed the adjusted mode, for otherwise
5752 * the hw state checker will get angry at the mismatch. */
5753 crtc_vtotal = adjusted_mode->crtc_vtotal;
5754 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005755
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005756 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005757 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005758 crtc_vtotal -= 1;
5759 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005760
5761 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5762 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5763 else
5764 vsyncshift = adjusted_mode->crtc_hsync_start -
5765 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005766 if (vsyncshift < 0)
5767 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005768 }
5769
5770 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005771 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005772
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005773 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005774 (adjusted_mode->crtc_hdisplay - 1) |
5775 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005776 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005777 (adjusted_mode->crtc_hblank_start - 1) |
5778 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005779 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005780 (adjusted_mode->crtc_hsync_start - 1) |
5781 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5782
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005783 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005784 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005785 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005786 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005787 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005788 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005789 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005790 (adjusted_mode->crtc_vsync_start - 1) |
5791 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5792
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005793 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5794 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5795 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5796 * bits. */
5797 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5798 (pipe == PIPE_B || pipe == PIPE_C))
5799 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5800
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005801 /* pipesrc controls the size that is scaled from, which should
5802 * always be the user's requested size.
5803 */
5804 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005805 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5806 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005807}
5808
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005809static void intel_get_pipe_timings(struct intel_crtc *crtc,
5810 struct intel_crtc_config *pipe_config)
5811{
5812 struct drm_device *dev = crtc->base.dev;
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5814 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5815 uint32_t tmp;
5816
5817 tmp = I915_READ(HTOTAL(cpu_transcoder));
5818 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5819 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5820 tmp = I915_READ(HBLANK(cpu_transcoder));
5821 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5822 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5823 tmp = I915_READ(HSYNC(cpu_transcoder));
5824 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5825 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5826
5827 tmp = I915_READ(VTOTAL(cpu_transcoder));
5828 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5829 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5830 tmp = I915_READ(VBLANK(cpu_transcoder));
5831 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5832 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5833 tmp = I915_READ(VSYNC(cpu_transcoder));
5834 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5835 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5836
5837 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5838 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5839 pipe_config->adjusted_mode.crtc_vtotal += 1;
5840 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5841 }
5842
5843 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005844 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5845 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5846
5847 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5848 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005849}
5850
Daniel Vetterf6a83282014-02-11 15:28:57 -08005851void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5852 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03005853{
Daniel Vetterf6a83282014-02-11 15:28:57 -08005854 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5855 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5856 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5857 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005858
Daniel Vetterf6a83282014-02-11 15:28:57 -08005859 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5860 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5861 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5862 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005863
Daniel Vetterf6a83282014-02-11 15:28:57 -08005864 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03005865
Daniel Vetterf6a83282014-02-11 15:28:57 -08005866 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5867 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03005868}
5869
Daniel Vetter84b046f2013-02-19 18:48:54 +01005870static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5871{
5872 struct drm_device *dev = intel_crtc->base.dev;
5873 struct drm_i915_private *dev_priv = dev->dev_private;
5874 uint32_t pipeconf;
5875
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005876 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005877
Daniel Vetter67c72a12013-09-24 11:46:14 +02005878 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5879 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5880 pipeconf |= PIPECONF_ENABLE;
5881
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005882 if (intel_crtc->config.double_wide)
5883 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005884
Daniel Vetterff9ce462013-04-24 14:57:17 +02005885 /* only g4x and later have fancy bpc/dither controls */
5886 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02005887 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5888 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5889 pipeconf |= PIPECONF_DITHER_EN |
5890 PIPECONF_DITHER_TYPE_SP;
5891
5892 switch (intel_crtc->config.pipe_bpp) {
5893 case 18:
5894 pipeconf |= PIPECONF_6BPC;
5895 break;
5896 case 24:
5897 pipeconf |= PIPECONF_8BPC;
5898 break;
5899 case 30:
5900 pipeconf |= PIPECONF_10BPC;
5901 break;
5902 default:
5903 /* Case prevented by intel_choose_pipe_bpp_dither. */
5904 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01005905 }
5906 }
5907
5908 if (HAS_PIPE_CXSR(dev)) {
5909 if (intel_crtc->lowfreq_avail) {
5910 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5911 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5912 } else {
5913 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01005914 }
5915 }
5916
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02005917 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5918 if (INTEL_INFO(dev)->gen < 4 ||
5919 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5920 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5921 else
5922 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5923 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01005924 pipeconf |= PIPECONF_PROGRESSIVE;
5925
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005926 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5927 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03005928
Daniel Vetter84b046f2013-02-19 18:48:54 +01005929 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5930 POSTING_READ(PIPECONF(intel_crtc->pipe));
5931}
5932
Eric Anholtf564048e2011-03-30 13:01:02 -07005933static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07005934 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005935 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005936{
5937 struct drm_device *dev = crtc->dev;
5938 struct drm_i915_private *dev_priv = dev->dev_private;
5939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Eric Anholtc751ce42010-03-25 11:48:48 -07005940 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07005941 intel_clock_t clock, reduced_clock;
Daniel Vettera16af7212013-04-30 14:01:44 +02005942 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005943 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01005944 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08005945 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08005946
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005947 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005948 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005949 case INTEL_OUTPUT_LVDS:
5950 is_lvds = true;
5951 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005952 case INTEL_OUTPUT_DSI:
5953 is_dsi = true;
5954 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005955 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005956
Eric Anholtc751ce42010-03-25 11:48:48 -07005957 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08005958 }
5959
Jani Nikulaf2335332013-09-13 11:03:09 +03005960 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02005961 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005962
Jani Nikulaf2335332013-09-13 11:03:09 +03005963 if (!intel_crtc->config.clock_set) {
5964 refclk = i9xx_get_refclk(crtc, num_connectors);
5965
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005966 /*
5967 * Returns a set of divisors for the desired target clock with
5968 * the given refclk, or FALSE. The returned values represent
5969 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5970 * 2) / p1 / p2.
5971 */
5972 limit = intel_limit(crtc, refclk);
5973 ok = dev_priv->display.find_dpll(limit, crtc,
5974 intel_crtc->config.port_clock,
5975 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03005976 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005977 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5978 return -EINVAL;
5979 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005980
Jani Nikulaf2335332013-09-13 11:03:09 +03005981 if (is_lvds && dev_priv->lvds_downclock_avail) {
5982 /*
5983 * Ensure we match the reduced clock's P to the target
5984 * clock. If the clocks don't match, we can't switch
5985 * the display clock by using the FP0/FP1. In such case
5986 * we will disable the LVDS downclock feature.
5987 */
5988 has_reduced_clock =
5989 dev_priv->display.find_dpll(limit, crtc,
5990 dev_priv->lvds_downclock,
5991 refclk, &clock,
5992 &reduced_clock);
5993 }
5994 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01005995 intel_crtc->config.dpll.n = clock.n;
5996 intel_crtc->config.dpll.m1 = clock.m1;
5997 intel_crtc->config.dpll.m2 = clock.m2;
5998 intel_crtc->config.dpll.p1 = clock.p1;
5999 intel_crtc->config.dpll.p2 = clock.p2;
6000 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006001
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006002 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02006003 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306004 has_reduced_clock ? &reduced_clock : NULL,
6005 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006006 } else if (IS_CHERRYVIEW(dev)) {
6007 chv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006008 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03006009 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006010 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01006011 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006012 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006013 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006014 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006015
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006016 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006017}
6018
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006019static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6020 struct intel_crtc_config *pipe_config)
6021{
6022 struct drm_device *dev = crtc->base.dev;
6023 struct drm_i915_private *dev_priv = dev->dev_private;
6024 uint32_t tmp;
6025
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006026 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6027 return;
6028
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006029 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006030 if (!(tmp & PFIT_ENABLE))
6031 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006032
Daniel Vetter06922822013-07-11 13:35:40 +02006033 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006034 if (INTEL_INFO(dev)->gen < 4) {
6035 if (crtc->pipe != PIPE_B)
6036 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006037 } else {
6038 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6039 return;
6040 }
6041
Daniel Vetter06922822013-07-11 13:35:40 +02006042 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006043 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6044 if (INTEL_INFO(dev)->gen < 5)
6045 pipe_config->gmch_pfit.lvds_border_bits =
6046 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6047}
6048
Jesse Barnesacbec812013-09-20 11:29:32 -07006049static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6050 struct intel_crtc_config *pipe_config)
6051{
6052 struct drm_device *dev = crtc->base.dev;
6053 struct drm_i915_private *dev_priv = dev->dev_private;
6054 int pipe = pipe_config->cpu_transcoder;
6055 intel_clock_t clock;
6056 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006057 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006058
6059 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006060 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006061 mutex_unlock(&dev_priv->dpio_lock);
6062
6063 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6064 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6065 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6066 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6067 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6068
Ville Syrjäläf6466282013-10-14 14:50:31 +03006069 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006070
Ville Syrjäläf6466282013-10-14 14:50:31 +03006071 /* clock.dot is the fast clock */
6072 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006073}
6074
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006075static void i9xx_get_plane_config(struct intel_crtc *crtc,
6076 struct intel_plane_config *plane_config)
6077{
6078 struct drm_device *dev = crtc->base.dev;
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080 u32 val, base, offset;
6081 int pipe = crtc->pipe, plane = crtc->plane;
6082 int fourcc, pixel_format;
6083 int aligned_height;
6084
Dave Airlie66e514c2014-04-03 07:51:54 +10006085 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6086 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006087 DRM_DEBUG_KMS("failed to alloc fb\n");
6088 return;
6089 }
6090
6091 val = I915_READ(DSPCNTR(plane));
6092
6093 if (INTEL_INFO(dev)->gen >= 4)
6094 if (val & DISPPLANE_TILED)
6095 plane_config->tiled = true;
6096
6097 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6098 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006099 crtc->base.primary->fb->pixel_format = fourcc;
6100 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006101 drm_format_plane_cpp(fourcc, 0) * 8;
6102
6103 if (INTEL_INFO(dev)->gen >= 4) {
6104 if (plane_config->tiled)
6105 offset = I915_READ(DSPTILEOFF(plane));
6106 else
6107 offset = I915_READ(DSPLINOFF(plane));
6108 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6109 } else {
6110 base = I915_READ(DSPADDR(plane));
6111 }
6112 plane_config->base = base;
6113
6114 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006115 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6116 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006117
6118 val = I915_READ(DSPSTRIDE(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006119 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006120
Dave Airlie66e514c2014-04-03 07:51:54 +10006121 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006122 plane_config->tiled);
6123
Dave Airlie66e514c2014-04-03 07:51:54 +10006124 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006125 aligned_height, PAGE_SIZE);
6126
6127 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006128 pipe, plane, crtc->base.primary->fb->width,
6129 crtc->base.primary->fb->height,
6130 crtc->base.primary->fb->bits_per_pixel, base,
6131 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006132 plane_config->size);
6133
6134}
6135
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006136static void chv_crtc_clock_get(struct intel_crtc *crtc,
6137 struct intel_crtc_config *pipe_config)
6138{
6139 struct drm_device *dev = crtc->base.dev;
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141 int pipe = pipe_config->cpu_transcoder;
6142 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6143 intel_clock_t clock;
6144 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6145 int refclk = 100000;
6146
6147 mutex_lock(&dev_priv->dpio_lock);
6148 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6149 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6150 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6151 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6152 mutex_unlock(&dev_priv->dpio_lock);
6153
6154 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6155 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6156 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6157 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6158 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6159
6160 chv_clock(refclk, &clock);
6161
6162 /* clock.dot is the fast clock */
6163 pipe_config->port_clock = clock.dot / 5;
6164}
6165
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006166static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6167 struct intel_crtc_config *pipe_config)
6168{
6169 struct drm_device *dev = crtc->base.dev;
6170 struct drm_i915_private *dev_priv = dev->dev_private;
6171 uint32_t tmp;
6172
Imre Deakb5482bd2014-03-05 16:20:55 +02006173 if (!intel_display_power_enabled(dev_priv,
6174 POWER_DOMAIN_PIPE(crtc->pipe)))
6175 return false;
6176
Daniel Vettere143a212013-07-04 12:01:15 +02006177 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006178 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006179
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006180 tmp = I915_READ(PIPECONF(crtc->pipe));
6181 if (!(tmp & PIPECONF_ENABLE))
6182 return false;
6183
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006184 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6185 switch (tmp & PIPECONF_BPC_MASK) {
6186 case PIPECONF_6BPC:
6187 pipe_config->pipe_bpp = 18;
6188 break;
6189 case PIPECONF_8BPC:
6190 pipe_config->pipe_bpp = 24;
6191 break;
6192 case PIPECONF_10BPC:
6193 pipe_config->pipe_bpp = 30;
6194 break;
6195 default:
6196 break;
6197 }
6198 }
6199
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006200 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6201 pipe_config->limited_color_range = true;
6202
Ville Syrjälä282740f2013-09-04 18:30:03 +03006203 if (INTEL_INFO(dev)->gen < 4)
6204 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6205
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006206 intel_get_pipe_timings(crtc, pipe_config);
6207
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006208 i9xx_get_pfit_config(crtc, pipe_config);
6209
Daniel Vetter6c49f242013-06-06 12:45:25 +02006210 if (INTEL_INFO(dev)->gen >= 4) {
6211 tmp = I915_READ(DPLL_MD(crtc->pipe));
6212 pipe_config->pixel_multiplier =
6213 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6214 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006215 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006216 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6217 tmp = I915_READ(DPLL(crtc->pipe));
6218 pipe_config->pixel_multiplier =
6219 ((tmp & SDVO_MULTIPLIER_MASK)
6220 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6221 } else {
6222 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6223 * port and will be fixed up in the encoder->get_config
6224 * function. */
6225 pipe_config->pixel_multiplier = 1;
6226 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006227 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6228 if (!IS_VALLEYVIEW(dev)) {
6229 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6230 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006231 } else {
6232 /* Mask out read-only status bits. */
6233 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6234 DPLL_PORTC_READY_MASK |
6235 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006236 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006237
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006238 if (IS_CHERRYVIEW(dev))
6239 chv_crtc_clock_get(crtc, pipe_config);
6240 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006241 vlv_crtc_clock_get(crtc, pipe_config);
6242 else
6243 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006244
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006245 return true;
6246}
6247
Paulo Zanonidde86e22012-12-01 12:04:25 -02006248static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006249{
6250 struct drm_i915_private *dev_priv = dev->dev_private;
6251 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006252 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006253 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006254 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006255 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006256 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006257 bool has_ck505 = false;
6258 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006259
6260 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07006261 list_for_each_entry(encoder, &mode_config->encoder_list,
6262 base.head) {
6263 switch (encoder->type) {
6264 case INTEL_OUTPUT_LVDS:
6265 has_panel = true;
6266 has_lvds = true;
6267 break;
6268 case INTEL_OUTPUT_EDP:
6269 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006270 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006271 has_cpu_edp = true;
6272 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006273 }
6274 }
6275
Keith Packard99eb6a02011-09-26 14:29:12 -07006276 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006277 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006278 can_ssc = has_ck505;
6279 } else {
6280 has_ck505 = false;
6281 can_ssc = true;
6282 }
6283
Imre Deak2de69052013-05-08 13:14:04 +03006284 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6285 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006286
6287 /* Ironlake: try to setup display ref clock before DPLL
6288 * enabling. This is only under driver's control after
6289 * PCH B stepping, previous chipset stepping should be
6290 * ignoring this setting.
6291 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006292 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006293
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006294 /* As we must carefully and slowly disable/enable each source in turn,
6295 * compute the final state we want first and check if we need to
6296 * make any changes at all.
6297 */
6298 final = val;
6299 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006300 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006301 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006302 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006303 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6304
6305 final &= ~DREF_SSC_SOURCE_MASK;
6306 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6307 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006308
Keith Packard199e5d72011-09-22 12:01:57 -07006309 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006310 final |= DREF_SSC_SOURCE_ENABLE;
6311
6312 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6313 final |= DREF_SSC1_ENABLE;
6314
6315 if (has_cpu_edp) {
6316 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6317 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6318 else
6319 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6320 } else
6321 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6322 } else {
6323 final |= DREF_SSC_SOURCE_DISABLE;
6324 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6325 }
6326
6327 if (final == val)
6328 return;
6329
6330 /* Always enable nonspread source */
6331 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6332
6333 if (has_ck505)
6334 val |= DREF_NONSPREAD_CK505_ENABLE;
6335 else
6336 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6337
6338 if (has_panel) {
6339 val &= ~DREF_SSC_SOURCE_MASK;
6340 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006341
Keith Packard199e5d72011-09-22 12:01:57 -07006342 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006343 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006344 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006345 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006346 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006347 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006348
6349 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006350 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006351 POSTING_READ(PCH_DREF_CONTROL);
6352 udelay(200);
6353
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006354 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006355
6356 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006357 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006358 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006359 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006360 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006361 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006362 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006363 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006364 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006365
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006366 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006367 POSTING_READ(PCH_DREF_CONTROL);
6368 udelay(200);
6369 } else {
6370 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6371
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006372 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006373
6374 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006375 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006376
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006377 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006378 POSTING_READ(PCH_DREF_CONTROL);
6379 udelay(200);
6380
6381 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006382 val &= ~DREF_SSC_SOURCE_MASK;
6383 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006384
6385 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006386 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006387
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006388 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006389 POSTING_READ(PCH_DREF_CONTROL);
6390 udelay(200);
6391 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006392
6393 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006394}
6395
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006396static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006397{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006398 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006399
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006400 tmp = I915_READ(SOUTH_CHICKEN2);
6401 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6402 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006403
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006404 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6405 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6406 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006407
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006408 tmp = I915_READ(SOUTH_CHICKEN2);
6409 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6410 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006411
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006412 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6413 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6414 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006415}
6416
6417/* WaMPhyProgramming:hsw */
6418static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6419{
6420 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006421
6422 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6423 tmp &= ~(0xFF << 24);
6424 tmp |= (0x12 << 24);
6425 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6426
Paulo Zanonidde86e22012-12-01 12:04:25 -02006427 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6428 tmp |= (1 << 11);
6429 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6430
6431 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6432 tmp |= (1 << 11);
6433 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6434
Paulo Zanonidde86e22012-12-01 12:04:25 -02006435 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6436 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6437 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6438
6439 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6440 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6441 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6442
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006443 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6444 tmp &= ~(7 << 13);
6445 tmp |= (5 << 13);
6446 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006447
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006448 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6449 tmp &= ~(7 << 13);
6450 tmp |= (5 << 13);
6451 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006452
6453 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6454 tmp &= ~0xFF;
6455 tmp |= 0x1C;
6456 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6457
6458 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6459 tmp &= ~0xFF;
6460 tmp |= 0x1C;
6461 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6462
6463 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6464 tmp &= ~(0xFF << 16);
6465 tmp |= (0x1C << 16);
6466 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6467
6468 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6469 tmp &= ~(0xFF << 16);
6470 tmp |= (0x1C << 16);
6471 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6472
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006473 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6474 tmp |= (1 << 27);
6475 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006476
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006477 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6478 tmp |= (1 << 27);
6479 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006480
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006481 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6482 tmp &= ~(0xF << 28);
6483 tmp |= (4 << 28);
6484 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006485
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006486 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6487 tmp &= ~(0xF << 28);
6488 tmp |= (4 << 28);
6489 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006490}
6491
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006492/* Implements 3 different sequences from BSpec chapter "Display iCLK
6493 * Programming" based on the parameters passed:
6494 * - Sequence to enable CLKOUT_DP
6495 * - Sequence to enable CLKOUT_DP without spread
6496 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6497 */
6498static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6499 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006500{
6501 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006502 uint32_t reg, tmp;
6503
6504 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6505 with_spread = true;
6506 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6507 with_fdi, "LP PCH doesn't have FDI\n"))
6508 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006509
6510 mutex_lock(&dev_priv->dpio_lock);
6511
6512 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6513 tmp &= ~SBI_SSCCTL_DISABLE;
6514 tmp |= SBI_SSCCTL_PATHALT;
6515 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6516
6517 udelay(24);
6518
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006519 if (with_spread) {
6520 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6521 tmp &= ~SBI_SSCCTL_PATHALT;
6522 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006523
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006524 if (with_fdi) {
6525 lpt_reset_fdi_mphy(dev_priv);
6526 lpt_program_fdi_mphy(dev_priv);
6527 }
6528 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02006529
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006530 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6531 SBI_GEN0 : SBI_DBUFF0;
6532 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6533 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6534 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01006535
6536 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006537}
6538
Paulo Zanoni47701c32013-07-23 11:19:25 -03006539/* Sequence to disable CLKOUT_DP */
6540static void lpt_disable_clkout_dp(struct drm_device *dev)
6541{
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543 uint32_t reg, tmp;
6544
6545 mutex_lock(&dev_priv->dpio_lock);
6546
6547 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6548 SBI_GEN0 : SBI_DBUFF0;
6549 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6550 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6551 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6552
6553 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6554 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6555 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6556 tmp |= SBI_SSCCTL_PATHALT;
6557 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6558 udelay(32);
6559 }
6560 tmp |= SBI_SSCCTL_DISABLE;
6561 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6562 }
6563
6564 mutex_unlock(&dev_priv->dpio_lock);
6565}
6566
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006567static void lpt_init_pch_refclk(struct drm_device *dev)
6568{
6569 struct drm_mode_config *mode_config = &dev->mode_config;
6570 struct intel_encoder *encoder;
6571 bool has_vga = false;
6572
6573 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6574 switch (encoder->type) {
6575 case INTEL_OUTPUT_ANALOG:
6576 has_vga = true;
6577 break;
6578 }
6579 }
6580
Paulo Zanoni47701c32013-07-23 11:19:25 -03006581 if (has_vga)
6582 lpt_enable_clkout_dp(dev, true, true);
6583 else
6584 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006585}
6586
Paulo Zanonidde86e22012-12-01 12:04:25 -02006587/*
6588 * Initialize reference clocks when the driver loads
6589 */
6590void intel_init_pch_refclk(struct drm_device *dev)
6591{
6592 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6593 ironlake_init_pch_refclk(dev);
6594 else if (HAS_PCH_LPT(dev))
6595 lpt_init_pch_refclk(dev);
6596}
6597
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006598static int ironlake_get_refclk(struct drm_crtc *crtc)
6599{
6600 struct drm_device *dev = crtc->dev;
6601 struct drm_i915_private *dev_priv = dev->dev_private;
6602 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006603 int num_connectors = 0;
6604 bool is_lvds = false;
6605
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02006606 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006607 switch (encoder->type) {
6608 case INTEL_OUTPUT_LVDS:
6609 is_lvds = true;
6610 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006611 }
6612 num_connectors++;
6613 }
6614
6615 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006616 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006617 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006618 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006619 }
6620
6621 return 120000;
6622}
6623
Daniel Vetter6ff93602013-04-19 11:24:36 +02006624static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03006625{
6626 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6628 int pipe = intel_crtc->pipe;
6629 uint32_t val;
6630
Daniel Vetter78114072013-06-13 00:54:57 +02006631 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03006632
Daniel Vetter965e0c42013-03-27 00:44:57 +01006633 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03006634 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006635 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006636 break;
6637 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006638 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006639 break;
6640 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006641 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006642 break;
6643 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006644 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006645 break;
6646 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03006647 /* Case prevented by intel_choose_pipe_bpp_dither. */
6648 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03006649 }
6650
Daniel Vetterd8b32242013-04-25 17:54:44 +02006651 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03006652 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6653
Daniel Vetter6ff93602013-04-19 11:24:36 +02006654 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03006655 val |= PIPECONF_INTERLACED_ILK;
6656 else
6657 val |= PIPECONF_PROGRESSIVE;
6658
Daniel Vetter50f3b012013-03-27 00:44:56 +01006659 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006660 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006661
Paulo Zanonic8203562012-09-12 10:06:29 -03006662 I915_WRITE(PIPECONF(pipe), val);
6663 POSTING_READ(PIPECONF(pipe));
6664}
6665
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006666/*
6667 * Set up the pipe CSC unit.
6668 *
6669 * Currently only full range RGB to limited range RGB conversion
6670 * is supported, but eventually this should handle various
6671 * RGB<->YCbCr scenarios as well.
6672 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01006673static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006674{
6675 struct drm_device *dev = crtc->dev;
6676 struct drm_i915_private *dev_priv = dev->dev_private;
6677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6678 int pipe = intel_crtc->pipe;
6679 uint16_t coeff = 0x7800; /* 1.0 */
6680
6681 /*
6682 * TODO: Check what kind of values actually come out of the pipe
6683 * with these coeff/postoff values and adjust to get the best
6684 * accuracy. Perhaps we even need to take the bpc value into
6685 * consideration.
6686 */
6687
Daniel Vetter50f3b012013-03-27 00:44:56 +01006688 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006689 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6690
6691 /*
6692 * GY/GU and RY/RU should be the other way around according
6693 * to BSpec, but reality doesn't agree. Just set them up in
6694 * a way that results in the correct picture.
6695 */
6696 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6697 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6698
6699 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6700 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6701
6702 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6703 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6704
6705 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6706 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6707 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6708
6709 if (INTEL_INFO(dev)->gen > 6) {
6710 uint16_t postoff = 0;
6711
Daniel Vetter50f3b012013-03-27 00:44:56 +01006712 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02006713 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006714
6715 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6716 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6717 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6718
6719 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6720 } else {
6721 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6722
Daniel Vetter50f3b012013-03-27 00:44:56 +01006723 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006724 mode |= CSC_BLACK_SCREEN_OFFSET;
6725
6726 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6727 }
6728}
6729
Daniel Vetter6ff93602013-04-19 11:24:36 +02006730static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006731{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006732 struct drm_device *dev = crtc->dev;
6733 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006735 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006736 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006737 uint32_t val;
6738
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006739 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006740
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006741 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006742 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6743
Daniel Vetter6ff93602013-04-19 11:24:36 +02006744 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006745 val |= PIPECONF_INTERLACED_ILK;
6746 else
6747 val |= PIPECONF_PROGRESSIVE;
6748
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006749 I915_WRITE(PIPECONF(cpu_transcoder), val);
6750 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006751
6752 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6753 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006754
6755 if (IS_BROADWELL(dev)) {
6756 val = 0;
6757
6758 switch (intel_crtc->config.pipe_bpp) {
6759 case 18:
6760 val |= PIPEMISC_DITHER_6_BPC;
6761 break;
6762 case 24:
6763 val |= PIPEMISC_DITHER_8_BPC;
6764 break;
6765 case 30:
6766 val |= PIPEMISC_DITHER_10_BPC;
6767 break;
6768 case 36:
6769 val |= PIPEMISC_DITHER_12_BPC;
6770 break;
6771 default:
6772 /* Case prevented by pipe_config_set_bpp. */
6773 BUG();
6774 }
6775
6776 if (intel_crtc->config.dither)
6777 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6778
6779 I915_WRITE(PIPEMISC(pipe), val);
6780 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006781}
6782
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006783static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006784 intel_clock_t *clock,
6785 bool *has_reduced_clock,
6786 intel_clock_t *reduced_clock)
6787{
6788 struct drm_device *dev = crtc->dev;
6789 struct drm_i915_private *dev_priv = dev->dev_private;
6790 struct intel_encoder *intel_encoder;
6791 int refclk;
6792 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02006793 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006794
6795 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6796 switch (intel_encoder->type) {
6797 case INTEL_OUTPUT_LVDS:
6798 is_lvds = true;
6799 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006800 }
6801 }
6802
6803 refclk = ironlake_get_refclk(crtc);
6804
6805 /*
6806 * Returns a set of divisors for the desired target clock with the given
6807 * refclk, or FALSE. The returned values represent the clock equation:
6808 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6809 */
6810 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006811 ret = dev_priv->display.find_dpll(limit, crtc,
6812 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006813 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006814 if (!ret)
6815 return false;
6816
6817 if (is_lvds && dev_priv->lvds_downclock_avail) {
6818 /*
6819 * Ensure we match the reduced clock's P to the target clock.
6820 * If the clocks don't match, we can't switch the display clock
6821 * by using the FP0/FP1. In such case we will disable the LVDS
6822 * downclock feature.
6823 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006824 *has_reduced_clock =
6825 dev_priv->display.find_dpll(limit, crtc,
6826 dev_priv->lvds_downclock,
6827 refclk, clock,
6828 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006829 }
6830
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006831 return true;
6832}
6833
Paulo Zanonid4b19312012-11-29 11:29:32 -02006834int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6835{
6836 /*
6837 * Account for spread spectrum to avoid
6838 * oversubscribing the link. Max center spread
6839 * is 2.5%; use 5% for safety's sake.
6840 */
6841 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02006842 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02006843}
6844
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006845static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02006846{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006847 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006848}
6849
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006850static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006851 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006852 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006853{
6854 struct drm_crtc *crtc = &intel_crtc->base;
6855 struct drm_device *dev = crtc->dev;
6856 struct drm_i915_private *dev_priv = dev->dev_private;
6857 struct intel_encoder *intel_encoder;
6858 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006859 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02006860 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006861
6862 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6863 switch (intel_encoder->type) {
6864 case INTEL_OUTPUT_LVDS:
6865 is_lvds = true;
6866 break;
6867 case INTEL_OUTPUT_SDVO:
6868 case INTEL_OUTPUT_HDMI:
6869 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006870 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006871 }
6872
6873 num_connectors++;
6874 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006875
Chris Wilsonc1858122010-12-03 21:35:48 +00006876 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07006877 factor = 21;
6878 if (is_lvds) {
6879 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006880 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02006881 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07006882 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02006883 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07006884 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00006885
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006886 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02006887 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00006888
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006889 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6890 *fp2 |= FP_CB_TUNE;
6891
Chris Wilson5eddb702010-09-11 13:48:45 +01006892 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08006893
Eric Anholta07d6782011-03-30 13:01:08 -07006894 if (is_lvds)
6895 dpll |= DPLLB_MODE_LVDS;
6896 else
6897 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006898
Daniel Vetteref1b4602013-06-01 17:17:04 +02006899 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6900 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006901
6902 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006903 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02006904 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006905 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08006906
Eric Anholta07d6782011-03-30 13:01:08 -07006907 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006908 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006909 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006910 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006911
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006912 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07006913 case 5:
6914 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6915 break;
6916 case 7:
6917 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6918 break;
6919 case 10:
6920 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6921 break;
6922 case 14:
6923 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6924 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006925 }
6926
Daniel Vetterb4c09f32013-04-30 14:01:42 +02006927 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006928 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08006929 else
6930 dpll |= PLL_REF_INPUT_DREFCLK;
6931
Daniel Vetter959e16d2013-06-05 13:34:21 +02006932 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006933}
6934
Jesse Barnes79e53942008-11-07 14:24:08 -08006935static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08006936 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006937 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006938{
6939 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08006940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006941 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006942 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006943 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03006944 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01006945 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006946 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02006947 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08006948
6949 for_each_encoder_on_crtc(dev, crtc, encoder) {
6950 switch (encoder->type) {
6951 case INTEL_OUTPUT_LVDS:
6952 is_lvds = true;
6953 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006954 }
6955
6956 num_connectors++;
6957 }
6958
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006959 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6960 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6961
Daniel Vetterff9a6752013-06-01 17:16:21 +02006962 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006963 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02006964 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006965 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6966 return -EINVAL;
6967 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01006968 /* Compat-code for transition, will disappear. */
6969 if (!intel_crtc->config.clock_set) {
6970 intel_crtc->config.dpll.n = clock.n;
6971 intel_crtc->config.dpll.m1 = clock.m1;
6972 intel_crtc->config.dpll.m2 = clock.m2;
6973 intel_crtc->config.dpll.p1 = clock.p1;
6974 intel_crtc->config.dpll.p2 = clock.p2;
6975 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006976
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006977 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01006978 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006979 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006980 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006981 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006982
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006983 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006984 &fp, &reduced_clock,
6985 has_reduced_clock ? &fp2 : NULL);
6986
Daniel Vetter959e16d2013-06-05 13:34:21 +02006987 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02006988 intel_crtc->config.dpll_hw_state.fp0 = fp;
6989 if (has_reduced_clock)
6990 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6991 else
6992 intel_crtc->config.dpll_hw_state.fp1 = fp;
6993
Daniel Vetterb89a1d32013-06-05 13:34:24 +02006994 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006995 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03006996 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Daniel Vetter29407aa2014-04-24 23:55:08 +02006997 pipe_name(intel_crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07006998 return -EINVAL;
6999 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007000 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02007001 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007002
Jani Nikulad330a952014-01-21 11:24:25 +02007003 if (is_lvds && has_reduced_clock && i915.powersave)
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007004 intel_crtc->lowfreq_avail = true;
7005 else
7006 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007007
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007008 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007009}
7010
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007011static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7012 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007013{
7014 struct drm_device *dev = crtc->base.dev;
7015 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007016 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007017
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007018 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7019 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7020 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7021 & ~TU_SIZE_MASK;
7022 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7023 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7024 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7025}
7026
7027static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7028 enum transcoder transcoder,
7029 struct intel_link_m_n *m_n)
7030{
7031 struct drm_device *dev = crtc->base.dev;
7032 struct drm_i915_private *dev_priv = dev->dev_private;
7033 enum pipe pipe = crtc->pipe;
7034
7035 if (INTEL_INFO(dev)->gen >= 5) {
7036 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7037 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7038 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7039 & ~TU_SIZE_MASK;
7040 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7041 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7042 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7043 } else {
7044 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7045 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7046 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7047 & ~TU_SIZE_MASK;
7048 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7049 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7050 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7051 }
7052}
7053
7054void intel_dp_get_m_n(struct intel_crtc *crtc,
7055 struct intel_crtc_config *pipe_config)
7056{
7057 if (crtc->config.has_pch_encoder)
7058 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7059 else
7060 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7061 &pipe_config->dp_m_n);
7062}
7063
Daniel Vetter72419202013-04-04 13:28:53 +02007064static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7065 struct intel_crtc_config *pipe_config)
7066{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007067 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7068 &pipe_config->fdi_m_n);
Daniel Vetter72419202013-04-04 13:28:53 +02007069}
7070
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007071static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7072 struct intel_crtc_config *pipe_config)
7073{
7074 struct drm_device *dev = crtc->base.dev;
7075 struct drm_i915_private *dev_priv = dev->dev_private;
7076 uint32_t tmp;
7077
7078 tmp = I915_READ(PF_CTL(crtc->pipe));
7079
7080 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007081 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007082 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7083 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007084
7085 /* We currently do not free assignements of panel fitters on
7086 * ivb/hsw (since we don't use the higher upscaling modes which
7087 * differentiates them) so just WARN about this case for now. */
7088 if (IS_GEN7(dev)) {
7089 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7090 PF_PIPE_SEL_IVB(crtc->pipe));
7091 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007092 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007093}
7094
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007095static void ironlake_get_plane_config(struct intel_crtc *crtc,
7096 struct intel_plane_config *plane_config)
7097{
7098 struct drm_device *dev = crtc->base.dev;
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 u32 val, base, offset;
7101 int pipe = crtc->pipe, plane = crtc->plane;
7102 int fourcc, pixel_format;
7103 int aligned_height;
7104
Dave Airlie66e514c2014-04-03 07:51:54 +10007105 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7106 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007107 DRM_DEBUG_KMS("failed to alloc fb\n");
7108 return;
7109 }
7110
7111 val = I915_READ(DSPCNTR(plane));
7112
7113 if (INTEL_INFO(dev)->gen >= 4)
7114 if (val & DISPPLANE_TILED)
7115 plane_config->tiled = true;
7116
7117 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7118 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007119 crtc->base.primary->fb->pixel_format = fourcc;
7120 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007121 drm_format_plane_cpp(fourcc, 0) * 8;
7122
7123 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7124 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7125 offset = I915_READ(DSPOFFSET(plane));
7126 } else {
7127 if (plane_config->tiled)
7128 offset = I915_READ(DSPTILEOFF(plane));
7129 else
7130 offset = I915_READ(DSPLINOFF(plane));
7131 }
7132 plane_config->base = base;
7133
7134 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007135 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7136 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007137
7138 val = I915_READ(DSPSTRIDE(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007139 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007140
Dave Airlie66e514c2014-04-03 07:51:54 +10007141 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007142 plane_config->tiled);
7143
Dave Airlie66e514c2014-04-03 07:51:54 +10007144 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007145 aligned_height, PAGE_SIZE);
7146
7147 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007148 pipe, plane, crtc->base.primary->fb->width,
7149 crtc->base.primary->fb->height,
7150 crtc->base.primary->fb->bits_per_pixel, base,
7151 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007152 plane_config->size);
7153}
7154
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007155static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7156 struct intel_crtc_config *pipe_config)
7157{
7158 struct drm_device *dev = crtc->base.dev;
7159 struct drm_i915_private *dev_priv = dev->dev_private;
7160 uint32_t tmp;
7161
Daniel Vettere143a212013-07-04 12:01:15 +02007162 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007163 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007164
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007165 tmp = I915_READ(PIPECONF(crtc->pipe));
7166 if (!(tmp & PIPECONF_ENABLE))
7167 return false;
7168
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007169 switch (tmp & PIPECONF_BPC_MASK) {
7170 case PIPECONF_6BPC:
7171 pipe_config->pipe_bpp = 18;
7172 break;
7173 case PIPECONF_8BPC:
7174 pipe_config->pipe_bpp = 24;
7175 break;
7176 case PIPECONF_10BPC:
7177 pipe_config->pipe_bpp = 30;
7178 break;
7179 case PIPECONF_12BPC:
7180 pipe_config->pipe_bpp = 36;
7181 break;
7182 default:
7183 break;
7184 }
7185
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007186 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7187 pipe_config->limited_color_range = true;
7188
Daniel Vetterab9412b2013-05-03 11:49:46 +02007189 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007190 struct intel_shared_dpll *pll;
7191
Daniel Vetter88adfff2013-03-28 10:42:01 +01007192 pipe_config->has_pch_encoder = true;
7193
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007194 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7195 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7196 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007197
7198 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007199
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007200 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007201 pipe_config->shared_dpll =
7202 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007203 } else {
7204 tmp = I915_READ(PCH_DPLL_SEL);
7205 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7206 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7207 else
7208 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7209 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007210
7211 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7212
7213 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7214 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007215
7216 tmp = pipe_config->dpll_hw_state.dpll;
7217 pipe_config->pixel_multiplier =
7218 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7219 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007220
7221 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007222 } else {
7223 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007224 }
7225
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007226 intel_get_pipe_timings(crtc, pipe_config);
7227
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007228 ironlake_get_pfit_config(crtc, pipe_config);
7229
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007230 return true;
7231}
7232
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007233static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7234{
7235 struct drm_device *dev = dev_priv->dev;
7236 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7237 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007238
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007239 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007240 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007241 pipe_name(crtc->pipe));
7242
7243 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7244 WARN(plls->spll_refcount, "SPLL enabled\n");
7245 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7246 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7247 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7248 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7249 "CPU PWM1 enabled\n");
7250 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7251 "CPU PWM2 enabled\n");
7252 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7253 "PCH PWM1 enabled\n");
7254 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7255 "Utility pin enabled\n");
7256 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7257
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007258 /*
7259 * In theory we can still leave IRQs enabled, as long as only the HPD
7260 * interrupts remain enabled. We used to check for that, but since it's
7261 * gen-specific and since we only disable LCPLL after we fully disable
7262 * the interrupts, the check below should be enough.
7263 */
7264 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007265}
7266
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007267static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7268{
7269 struct drm_device *dev = dev_priv->dev;
7270
7271 if (IS_HASWELL(dev)) {
7272 mutex_lock(&dev_priv->rps.hw_lock);
7273 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7274 val))
7275 DRM_ERROR("Failed to disable D_COMP\n");
7276 mutex_unlock(&dev_priv->rps.hw_lock);
7277 } else {
7278 I915_WRITE(D_COMP, val);
7279 }
7280 POSTING_READ(D_COMP);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007281}
7282
7283/*
7284 * This function implements pieces of two sequences from BSpec:
7285 * - Sequence for display software to disable LCPLL
7286 * - Sequence for display software to allow package C8+
7287 * The steps implemented here are just the steps that actually touch the LCPLL
7288 * register. Callers should take care of disabling all the display engine
7289 * functions, doing the mode unset, fixing interrupts, etc.
7290 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007291static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7292 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007293{
7294 uint32_t val;
7295
7296 assert_can_disable_lcpll(dev_priv);
7297
7298 val = I915_READ(LCPLL_CTL);
7299
7300 if (switch_to_fclk) {
7301 val |= LCPLL_CD_SOURCE_FCLK;
7302 I915_WRITE(LCPLL_CTL, val);
7303
7304 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7305 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7306 DRM_ERROR("Switching to FCLK failed\n");
7307
7308 val = I915_READ(LCPLL_CTL);
7309 }
7310
7311 val |= LCPLL_PLL_DISABLE;
7312 I915_WRITE(LCPLL_CTL, val);
7313 POSTING_READ(LCPLL_CTL);
7314
7315 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7316 DRM_ERROR("LCPLL still locked\n");
7317
7318 val = I915_READ(D_COMP);
7319 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007320 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007321 ndelay(100);
7322
7323 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7324 DRM_ERROR("D_COMP RCOMP still in progress\n");
7325
7326 if (allow_power_down) {
7327 val = I915_READ(LCPLL_CTL);
7328 val |= LCPLL_POWER_DOWN_ALLOW;
7329 I915_WRITE(LCPLL_CTL, val);
7330 POSTING_READ(LCPLL_CTL);
7331 }
7332}
7333
7334/*
7335 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7336 * source.
7337 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007338static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007339{
7340 uint32_t val;
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007341 unsigned long irqflags;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007342
7343 val = I915_READ(LCPLL_CTL);
7344
7345 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7346 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7347 return;
7348
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007349 /*
7350 * Make sure we're not on PC8 state before disabling PC8, otherwise
7351 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7352 *
7353 * The other problem is that hsw_restore_lcpll() is called as part of
7354 * the runtime PM resume sequence, so we can't just call
7355 * gen6_gt_force_wake_get() because that function calls
7356 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7357 * while we are on the resume sequence. So to solve this problem we have
7358 * to call special forcewake code that doesn't touch runtime PM and
7359 * doesn't enable the forcewake delayed work.
7360 */
7361 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7362 if (dev_priv->uncore.forcewake_count++ == 0)
7363 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7364 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007365
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007366 if (val & LCPLL_POWER_DOWN_ALLOW) {
7367 val &= ~LCPLL_POWER_DOWN_ALLOW;
7368 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007369 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007370 }
7371
7372 val = I915_READ(D_COMP);
7373 val |= D_COMP_COMP_FORCE;
7374 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007375 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007376
7377 val = I915_READ(LCPLL_CTL);
7378 val &= ~LCPLL_PLL_DISABLE;
7379 I915_WRITE(LCPLL_CTL, val);
7380
7381 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7382 DRM_ERROR("LCPLL not locked yet\n");
7383
7384 if (val & LCPLL_CD_SOURCE_FCLK) {
7385 val = I915_READ(LCPLL_CTL);
7386 val &= ~LCPLL_CD_SOURCE_FCLK;
7387 I915_WRITE(LCPLL_CTL, val);
7388
7389 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7390 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7391 DRM_ERROR("Switching back to LCPLL failed\n");
7392 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007393
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007394 /* See the big comment above. */
7395 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7396 if (--dev_priv->uncore.forcewake_count == 0)
7397 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7398 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007399}
7400
Paulo Zanoni765dab62014-03-07 20:08:18 -03007401/*
7402 * Package states C8 and deeper are really deep PC states that can only be
7403 * reached when all the devices on the system allow it, so even if the graphics
7404 * device allows PC8+, it doesn't mean the system will actually get to these
7405 * states. Our driver only allows PC8+ when going into runtime PM.
7406 *
7407 * The requirements for PC8+ are that all the outputs are disabled, the power
7408 * well is disabled and most interrupts are disabled, and these are also
7409 * requirements for runtime PM. When these conditions are met, we manually do
7410 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7411 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7412 * hang the machine.
7413 *
7414 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7415 * the state of some registers, so when we come back from PC8+ we need to
7416 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7417 * need to take care of the registers kept by RC6. Notice that this happens even
7418 * if we don't put the device in PCI D3 state (which is what currently happens
7419 * because of the runtime PM support).
7420 *
7421 * For more, read "Display Sequences for Package C8" on the hardware
7422 * documentation.
7423 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007424void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007425{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007426 struct drm_device *dev = dev_priv->dev;
7427 uint32_t val;
7428
Paulo Zanonic67a4702013-08-19 13:18:09 -03007429 DRM_DEBUG_KMS("Enabling package C8+\n");
7430
Paulo Zanonic67a4702013-08-19 13:18:09 -03007431 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7432 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7433 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7434 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7435 }
7436
7437 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007438 hsw_disable_lcpll(dev_priv, true, true);
7439}
7440
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007441void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007442{
7443 struct drm_device *dev = dev_priv->dev;
7444 uint32_t val;
7445
Paulo Zanonic67a4702013-08-19 13:18:09 -03007446 DRM_DEBUG_KMS("Disabling package C8+\n");
7447
7448 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007449 lpt_init_pch_refclk(dev);
7450
7451 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7452 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7453 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7454 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7455 }
7456
7457 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007458}
7459
Paulo Zanoni9a952a02014-03-07 20:12:34 -03007460static void snb_modeset_global_resources(struct drm_device *dev)
7461{
7462 modeset_update_crtc_power_domains(dev);
7463}
7464
Imre Deak4f074122013-10-16 17:25:51 +03007465static void haswell_modeset_global_resources(struct drm_device *dev)
7466{
Paulo Zanonida723562013-12-19 11:54:51 -02007467 modeset_update_crtc_power_domains(dev);
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02007468}
7469
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007470static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007471 int x, int y,
7472 struct drm_framebuffer *fb)
7473{
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007475
Paulo Zanoni566b7342013-11-25 15:27:08 -02007476 if (!intel_ddi_pll_select(intel_crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007477 return -EINVAL;
Paulo Zanoni566b7342013-11-25 15:27:08 -02007478 intel_ddi_pll_enable(intel_crtc);
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007479
Daniel Vetter644cef32014-04-24 23:55:07 +02007480 intel_crtc->lowfreq_avail = false;
7481
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007482 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007483}
7484
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007485static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7486 struct intel_crtc_config *pipe_config)
7487{
7488 struct drm_device *dev = crtc->base.dev;
7489 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007490 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007491 uint32_t tmp;
7492
Imre Deakb5482bd2014-03-05 16:20:55 +02007493 if (!intel_display_power_enabled(dev_priv,
7494 POWER_DOMAIN_PIPE(crtc->pipe)))
7495 return false;
7496
Daniel Vettere143a212013-07-04 12:01:15 +02007497 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007498 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7499
Daniel Vettereccb1402013-05-22 00:50:22 +02007500 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7501 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7502 enum pipe trans_edp_pipe;
7503 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7504 default:
7505 WARN(1, "unknown pipe linked to edp transcoder\n");
7506 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7507 case TRANS_DDI_EDP_INPUT_A_ON:
7508 trans_edp_pipe = PIPE_A;
7509 break;
7510 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7511 trans_edp_pipe = PIPE_B;
7512 break;
7513 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7514 trans_edp_pipe = PIPE_C;
7515 break;
7516 }
7517
7518 if (trans_edp_pipe == crtc->pipe)
7519 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7520 }
7521
Imre Deakda7e29b2014-02-18 00:02:02 +02007522 if (!intel_display_power_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02007523 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03007524 return false;
7525
Daniel Vettereccb1402013-05-22 00:50:22 +02007526 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007527 if (!(tmp & PIPECONF_ENABLE))
7528 return false;
7529
Daniel Vetter88adfff2013-03-28 10:42:01 +01007530 /*
Paulo Zanonif196e6b2013-04-18 16:35:41 -03007531 * Haswell has only FDI/PCH transcoder A. It is which is connected to
Daniel Vetter88adfff2013-03-28 10:42:01 +01007532 * DDI E. So just check whether this pipe is wired to DDI E and whether
7533 * the PCH transcoder is on.
7534 */
Daniel Vettereccb1402013-05-22 00:50:22 +02007535 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
Daniel Vetter88adfff2013-03-28 10:42:01 +01007536 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
Daniel Vetterab9412b2013-05-03 11:49:46 +02007537 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter88adfff2013-03-28 10:42:01 +01007538 pipe_config->has_pch_encoder = true;
7539
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007540 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7541 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7542 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007543
7544 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007545 }
7546
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007547 intel_get_pipe_timings(crtc, pipe_config);
7548
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007549 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Imre Deakda7e29b2014-02-18 00:02:02 +02007550 if (intel_display_power_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007551 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01007552
Jesse Barnese59150d2014-01-07 13:30:45 -08007553 if (IS_HASWELL(dev))
7554 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7555 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007556
Daniel Vetter6c49f242013-06-06 12:45:25 +02007557 pipe_config->pixel_multiplier = 1;
7558
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007559 return true;
7560}
7561
Jani Nikula1a915102013-10-16 12:34:48 +03007562static struct {
7563 int clock;
7564 u32 config;
7565} hdmi_audio_clock[] = {
7566 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7567 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7568 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7569 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7570 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7571 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7572 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7573 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7574 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7575 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7576};
7577
7578/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7579static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7580{
7581 int i;
7582
7583 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7584 if (mode->clock == hdmi_audio_clock[i].clock)
7585 break;
7586 }
7587
7588 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7589 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7590 i = 1;
7591 }
7592
7593 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7594 hdmi_audio_clock[i].clock,
7595 hdmi_audio_clock[i].config);
7596
7597 return hdmi_audio_clock[i].config;
7598}
7599
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007600static bool intel_eld_uptodate(struct drm_connector *connector,
7601 int reg_eldv, uint32_t bits_eldv,
7602 int reg_elda, uint32_t bits_elda,
7603 int reg_edid)
7604{
7605 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7606 uint8_t *eld = connector->eld;
7607 uint32_t i;
7608
7609 i = I915_READ(reg_eldv);
7610 i &= bits_eldv;
7611
7612 if (!eld[0])
7613 return !i;
7614
7615 if (!i)
7616 return false;
7617
7618 i = I915_READ(reg_elda);
7619 i &= ~bits_elda;
7620 I915_WRITE(reg_elda, i);
7621
7622 for (i = 0; i < eld[2]; i++)
7623 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7624 return false;
7625
7626 return true;
7627}
7628
Wu Fengguange0dac652011-09-05 14:25:34 +08007629static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007630 struct drm_crtc *crtc,
7631 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007632{
7633 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7634 uint8_t *eld = connector->eld;
7635 uint32_t eldv;
7636 uint32_t len;
7637 uint32_t i;
7638
7639 i = I915_READ(G4X_AUD_VID_DID);
7640
7641 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7642 eldv = G4X_ELDV_DEVCL_DEVBLC;
7643 else
7644 eldv = G4X_ELDV_DEVCTG;
7645
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007646 if (intel_eld_uptodate(connector,
7647 G4X_AUD_CNTL_ST, eldv,
7648 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7649 G4X_HDMIW_HDMIEDID))
7650 return;
7651
Wu Fengguange0dac652011-09-05 14:25:34 +08007652 i = I915_READ(G4X_AUD_CNTL_ST);
7653 i &= ~(eldv | G4X_ELD_ADDR);
7654 len = (i >> 9) & 0x1f; /* ELD buffer size */
7655 I915_WRITE(G4X_AUD_CNTL_ST, i);
7656
7657 if (!eld[0])
7658 return;
7659
7660 len = min_t(uint8_t, eld[2], len);
7661 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7662 for (i = 0; i < len; i++)
7663 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7664
7665 i = I915_READ(G4X_AUD_CNTL_ST);
7666 i |= eldv;
7667 I915_WRITE(G4X_AUD_CNTL_ST, i);
7668}
7669
Wang Xingchao83358c852012-08-16 22:43:37 +08007670static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007671 struct drm_crtc *crtc,
7672 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007673{
7674 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7675 uint8_t *eld = connector->eld;
Wang Xingchao83358c852012-08-16 22:43:37 +08007676 uint32_t eldv;
7677 uint32_t i;
7678 int len;
7679 int pipe = to_intel_crtc(crtc)->pipe;
7680 int tmp;
7681
7682 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7683 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7684 int aud_config = HSW_AUD_CFG(pipe);
7685 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7686
Wang Xingchao83358c852012-08-16 22:43:37 +08007687 /* Audio output enable */
7688 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7689 tmp = I915_READ(aud_cntrl_st2);
7690 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7691 I915_WRITE(aud_cntrl_st2, tmp);
Daniel Vetterc7905792014-04-16 16:56:09 +02007692 POSTING_READ(aud_cntrl_st2);
Wang Xingchao83358c852012-08-16 22:43:37 +08007693
Daniel Vetterc7905792014-04-16 16:56:09 +02007694 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Wang Xingchao83358c852012-08-16 22:43:37 +08007695
7696 /* Set ELD valid state */
7697 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007698 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007699 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7700 I915_WRITE(aud_cntrl_st2, tmp);
7701 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007702 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007703
7704 /* Enable HDMI mode */
7705 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007706 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007707 /* clear N_programing_enable and N_value_index */
7708 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7709 I915_WRITE(aud_config, tmp);
7710
7711 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7712
7713 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7714
7715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7716 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7717 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7718 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007719 } else {
7720 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7721 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007722
7723 if (intel_eld_uptodate(connector,
7724 aud_cntrl_st2, eldv,
7725 aud_cntl_st, IBX_ELD_ADDRESS,
7726 hdmiw_hdmiedid))
7727 return;
7728
7729 i = I915_READ(aud_cntrl_st2);
7730 i &= ~eldv;
7731 I915_WRITE(aud_cntrl_st2, i);
7732
7733 if (!eld[0])
7734 return;
7735
7736 i = I915_READ(aud_cntl_st);
7737 i &= ~IBX_ELD_ADDRESS;
7738 I915_WRITE(aud_cntl_st, i);
7739 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7740 DRM_DEBUG_DRIVER("port num:%d\n", i);
7741
7742 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7743 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7744 for (i = 0; i < len; i++)
7745 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7746
7747 i = I915_READ(aud_cntrl_st2);
7748 i |= eldv;
7749 I915_WRITE(aud_cntrl_st2, i);
7750
7751}
7752
Wu Fengguange0dac652011-09-05 14:25:34 +08007753static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007754 struct drm_crtc *crtc,
7755 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007756{
7757 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7758 uint8_t *eld = connector->eld;
7759 uint32_t eldv;
7760 uint32_t i;
7761 int len;
7762 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007763 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007764 int aud_cntl_st;
7765 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007766 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007767
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007768 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007769 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7770 aud_config = IBX_AUD_CFG(pipe);
7771 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007772 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007773 } else if (IS_VALLEYVIEW(connector->dev)) {
7774 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7775 aud_config = VLV_AUD_CFG(pipe);
7776 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7777 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007778 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007779 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7780 aud_config = CPT_AUD_CFG(pipe);
7781 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007782 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007783 }
7784
Wang Xingchao9b138a82012-08-09 16:52:18 +08007785 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08007786
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007787 if (IS_VALLEYVIEW(connector->dev)) {
7788 struct intel_encoder *intel_encoder;
7789 struct intel_digital_port *intel_dig_port;
7790
7791 intel_encoder = intel_attached_encoder(connector);
7792 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7793 i = intel_dig_port->port;
7794 } else {
7795 i = I915_READ(aud_cntl_st);
7796 i = (i >> 29) & DIP_PORT_SEL_MASK;
7797 /* DIP_Port_Select, 0x1 = PortB */
7798 }
7799
Wu Fengguange0dac652011-09-05 14:25:34 +08007800 if (!i) {
7801 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7802 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007803 eldv = IBX_ELD_VALIDB;
7804 eldv |= IBX_ELD_VALIDB << 4;
7805 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08007806 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03007807 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007808 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08007809 }
7810
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007811 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7812 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7813 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06007814 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007815 } else {
7816 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7817 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007818
7819 if (intel_eld_uptodate(connector,
7820 aud_cntrl_st2, eldv,
7821 aud_cntl_st, IBX_ELD_ADDRESS,
7822 hdmiw_hdmiedid))
7823 return;
7824
Wu Fengguange0dac652011-09-05 14:25:34 +08007825 i = I915_READ(aud_cntrl_st2);
7826 i &= ~eldv;
7827 I915_WRITE(aud_cntrl_st2, i);
7828
7829 if (!eld[0])
7830 return;
7831
Wu Fengguange0dac652011-09-05 14:25:34 +08007832 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007833 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08007834 I915_WRITE(aud_cntl_st, i);
7835
7836 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7837 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7838 for (i = 0; i < len; i++)
7839 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7840
7841 i = I915_READ(aud_cntrl_st2);
7842 i |= eldv;
7843 I915_WRITE(aud_cntrl_st2, i);
7844}
7845
7846void intel_write_eld(struct drm_encoder *encoder,
7847 struct drm_display_mode *mode)
7848{
7849 struct drm_crtc *crtc = encoder->crtc;
7850 struct drm_connector *connector;
7851 struct drm_device *dev = encoder->dev;
7852 struct drm_i915_private *dev_priv = dev->dev_private;
7853
7854 connector = drm_select_eld(encoder, mode);
7855 if (!connector)
7856 return;
7857
7858 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7859 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03007860 connector->name,
Wu Fengguange0dac652011-09-05 14:25:34 +08007861 connector->encoder->base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +03007862 connector->encoder->name);
Wu Fengguange0dac652011-09-05 14:25:34 +08007863
7864 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7865
7866 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03007867 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08007868}
7869
Chris Wilson560b85b2010-08-07 11:01:38 +01007870static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7871{
7872 struct drm_device *dev = crtc->dev;
7873 struct drm_i915_private *dev_priv = dev->dev_private;
7874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson4b0e3332014-05-30 16:35:26 +03007875 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01007876
Chris Wilson4b0e3332014-05-30 16:35:26 +03007877 if (base != intel_crtc->cursor_base) {
Chris Wilson560b85b2010-08-07 11:01:38 +01007878 /* On these chipsets we can only modify the base whilst
7879 * the cursor is disabled.
7880 */
Chris Wilson4b0e3332014-05-30 16:35:26 +03007881 if (intel_crtc->cursor_cntl) {
7882 I915_WRITE(_CURACNTR, 0);
7883 POSTING_READ(_CURACNTR);
7884 intel_crtc->cursor_cntl = 0;
7885 }
7886
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007887 I915_WRITE(_CURABASE, base);
Chris Wilson4b0e3332014-05-30 16:35:26 +03007888 POSTING_READ(_CURABASE);
7889 }
Chris Wilson560b85b2010-08-07 11:01:38 +01007890
Chris Wilson4b0e3332014-05-30 16:35:26 +03007891 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7892 cntl = 0;
7893 if (base)
7894 cntl = (CURSOR_ENABLE |
Chris Wilson560b85b2010-08-07 11:01:38 +01007895 CURSOR_GAMMA_ENABLE |
Chris Wilson4b0e3332014-05-30 16:35:26 +03007896 CURSOR_FORMAT_ARGB);
7897 if (intel_crtc->cursor_cntl != cntl) {
7898 I915_WRITE(_CURACNTR, cntl);
7899 POSTING_READ(_CURACNTR);
7900 intel_crtc->cursor_cntl = cntl;
7901 }
Chris Wilson560b85b2010-08-07 11:01:38 +01007902}
7903
7904static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7905{
7906 struct drm_device *dev = crtc->dev;
7907 struct drm_i915_private *dev_priv = dev->dev_private;
7908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7909 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03007910 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01007911
Chris Wilson4b0e3332014-05-30 16:35:26 +03007912 cntl = 0;
7913 if (base) {
7914 cntl = MCURSOR_GAMMA_ENABLE;
7915 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307916 case 64:
7917 cntl |= CURSOR_MODE_64_ARGB_AX;
7918 break;
7919 case 128:
7920 cntl |= CURSOR_MODE_128_ARGB_AX;
7921 break;
7922 case 256:
7923 cntl |= CURSOR_MODE_256_ARGB_AX;
7924 break;
7925 default:
7926 WARN_ON(1);
7927 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01007928 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03007929 cntl |= pipe << 28; /* Connect to correct pipe */
Chris Wilson560b85b2010-08-07 11:01:38 +01007930 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03007931 if (intel_crtc->cursor_cntl != cntl) {
7932 I915_WRITE(CURCNTR(pipe), cntl);
7933 POSTING_READ(CURCNTR(pipe));
7934 intel_crtc->cursor_cntl = cntl;
7935 }
7936
Chris Wilson560b85b2010-08-07 11:01:38 +01007937 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007938 I915_WRITE(CURBASE(pipe), base);
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007939 POSTING_READ(CURBASE(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01007940}
7941
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007942static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7943{
7944 struct drm_device *dev = crtc->dev;
7945 struct drm_i915_private *dev_priv = dev->dev_private;
7946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7947 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03007948 uint32_t cntl;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007949
Chris Wilson4b0e3332014-05-30 16:35:26 +03007950 cntl = 0;
7951 if (base) {
7952 cntl = MCURSOR_GAMMA_ENABLE;
7953 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05307954 case 64:
7955 cntl |= CURSOR_MODE_64_ARGB_AX;
7956 break;
7957 case 128:
7958 cntl |= CURSOR_MODE_128_ARGB_AX;
7959 break;
7960 case 256:
7961 cntl |= CURSOR_MODE_256_ARGB_AX;
7962 break;
7963 default:
7964 WARN_ON(1);
7965 return;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007966 }
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007967 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03007968 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
7969 cntl |= CURSOR_PIPE_CSC_ENABLE;
7970
7971 if (intel_crtc->cursor_cntl != cntl) {
7972 I915_WRITE(CURCNTR(pipe), cntl);
7973 POSTING_READ(CURCNTR(pipe));
7974 intel_crtc->cursor_cntl = cntl;
7975 }
7976
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007977 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03007978 I915_WRITE(CURBASE(pipe), base);
7979 POSTING_READ(CURBASE(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007980}
7981
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007982/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01007983static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7984 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007985{
7986 struct drm_device *dev = crtc->dev;
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7989 int pipe = intel_crtc->pipe;
7990 int x = intel_crtc->cursor_x;
7991 int y = intel_crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007992 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007993
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007994 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007995 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007996
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007997 if (x >= intel_crtc->config.pipe_src_w)
7998 base = 0;
7999
8000 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008001 base = 0;
8002
8003 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008004 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008005 base = 0;
8006
8007 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8008 x = -x;
8009 }
8010 pos |= x << CURSOR_X_SHIFT;
8011
8012 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008013 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008014 base = 0;
8015
8016 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8017 y = -y;
8018 }
8019 pos |= y << CURSOR_Y_SHIFT;
8020
Chris Wilson4b0e3332014-05-30 16:35:26 +03008021 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008022 return;
8023
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008024 I915_WRITE(CURPOS(pipe), pos);
8025
8026 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008027 ivb_update_cursor(crtc, base);
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008028 else if (IS_845G(dev) || IS_I865G(dev))
8029 i845_update_cursor(crtc, base);
8030 else
8031 i9xx_update_cursor(crtc, base);
Chris Wilson4b0e3332014-05-30 16:35:26 +03008032 intel_crtc->cursor_base = base;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008033}
8034
Jesse Barnes79e53942008-11-07 14:24:08 -08008035static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00008036 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08008037 uint32_t handle,
8038 uint32_t width, uint32_t height)
8039{
8040 struct drm_device *dev = crtc->dev;
8041 struct drm_i915_private *dev_priv = dev->dev_private;
8042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00008043 struct drm_i915_gem_object *obj;
Chris Wilson64f962e2014-03-26 12:38:15 +00008044 unsigned old_width;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008045 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008046 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008047
Jesse Barnes79e53942008-11-07 14:24:08 -08008048 /* if we want to turn off the cursor ignore width and height */
8049 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008050 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008051 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00008052 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008053 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008054 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008055 }
8056
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308057 /* Check for which cursor types we support */
8058 if (!((width == 64 && height == 64) ||
8059 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8060 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8061 DRM_DEBUG("Cursor dimension not supported\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08008062 return -EINVAL;
8063 }
8064
Chris Wilson05394f32010-11-08 19:18:58 +00008065 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00008066 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08008067 return -ENOENT;
8068
Chris Wilson05394f32010-11-08 19:18:58 +00008069 if (obj->base.size < width * height * 4) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008070 DRM_DEBUG_KMS("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10008071 ret = -ENOMEM;
8072 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008073 }
8074
Dave Airlie71acb5e2008-12-30 20:31:46 +10008075 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008076 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008077 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008078 unsigned alignment;
8079
Chris Wilsond9e86c02010-11-10 16:40:20 +00008080 if (obj->tiling_mode) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008081 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008082 ret = -EINVAL;
8083 goto fail_locked;
8084 }
8085
Chris Wilson693db182013-03-05 14:52:39 +00008086 /* Note that the w/a also requires 2 PTE of padding following
8087 * the bo. We currently fill all unused PTE with the shadow
8088 * page and so we should always have valid PTE following the
8089 * cursor preventing the VT-d warning.
8090 */
8091 alignment = 0;
8092 if (need_vtd_wa(dev))
8093 alignment = 64*1024;
8094
8095 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008096 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008097 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008098 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008099 }
8100
Chris Wilsond9e86c02010-11-10 16:40:20 +00008101 ret = i915_gem_object_put_fence(obj);
8102 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008103 DRM_DEBUG_KMS("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008104 goto fail_unpin;
8105 }
8106
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008107 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008108 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008109 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson00731152014-05-21 12:42:56 +01008110 ret = i915_gem_object_attach_phys(obj, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008111 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008112 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008113 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008114 }
Chris Wilson00731152014-05-21 12:42:56 +01008115 addr = obj->phys_handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008116 }
8117
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008118 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04008119 I915_WRITE(CURSIZE, (height << 12) | width);
8120
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008121 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008122 if (intel_crtc->cursor_bo) {
Chris Wilson00731152014-05-21 12:42:56 +01008123 if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilsoncc98b412013-08-09 12:25:09 +01008124 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00008125 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008126 }
Jesse Barnes80824002009-09-10 15:28:06 -07008127
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008128 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008129
Chris Wilson64f962e2014-03-26 12:38:15 +00008130 old_width = intel_crtc->cursor_width;
8131
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008132 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008133 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008134 intel_crtc->cursor_width = width;
8135 intel_crtc->cursor_height = height;
8136
Chris Wilson64f962e2014-03-26 12:38:15 +00008137 if (intel_crtc->active) {
8138 if (old_width != width)
8139 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008140 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Chris Wilson64f962e2014-03-26 12:38:15 +00008141 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008142
Jesse Barnes79e53942008-11-07 14:24:08 -08008143 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008144fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008145 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008146fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008147 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00008148fail:
Chris Wilson05394f32010-11-08 19:18:58 +00008149 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10008150 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008151}
8152
8153static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8154{
Jesse Barnes79e53942008-11-07 14:24:08 -08008155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008156
Ville Syrjälä92e76c82013-10-21 19:01:58 +03008157 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8158 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
Jesse Barnes652c3932009-08-17 13:31:43 -07008159
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008160 if (intel_crtc->active)
8161 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Jesse Barnes79e53942008-11-07 14:24:08 -08008162
8163 return 0;
8164}
8165
Jesse Barnes79e53942008-11-07 14:24:08 -08008166static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008167 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008168{
James Simmons72034252010-08-03 01:33:19 +01008169 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008171
James Simmons72034252010-08-03 01:33:19 +01008172 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008173 intel_crtc->lut_r[i] = red[i] >> 8;
8174 intel_crtc->lut_g[i] = green[i] >> 8;
8175 intel_crtc->lut_b[i] = blue[i] >> 8;
8176 }
8177
8178 intel_crtc_load_lut(crtc);
8179}
8180
Jesse Barnes79e53942008-11-07 14:24:08 -08008181/* VESA 640x480x72Hz mode to set on the pipe */
8182static struct drm_display_mode load_detect_mode = {
8183 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8184 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8185};
8186
Daniel Vettera8bb6812014-02-10 18:00:39 +01008187struct drm_framebuffer *
8188__intel_framebuffer_create(struct drm_device *dev,
8189 struct drm_mode_fb_cmd2 *mode_cmd,
8190 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008191{
8192 struct intel_framebuffer *intel_fb;
8193 int ret;
8194
8195 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8196 if (!intel_fb) {
8197 drm_gem_object_unreference_unlocked(&obj->base);
8198 return ERR_PTR(-ENOMEM);
8199 }
8200
8201 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008202 if (ret)
8203 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008204
8205 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008206err:
8207 drm_gem_object_unreference_unlocked(&obj->base);
8208 kfree(intel_fb);
8209
8210 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008211}
8212
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008213static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008214intel_framebuffer_create(struct drm_device *dev,
8215 struct drm_mode_fb_cmd2 *mode_cmd,
8216 struct drm_i915_gem_object *obj)
8217{
8218 struct drm_framebuffer *fb;
8219 int ret;
8220
8221 ret = i915_mutex_lock_interruptible(dev);
8222 if (ret)
8223 return ERR_PTR(ret);
8224 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8225 mutex_unlock(&dev->struct_mutex);
8226
8227 return fb;
8228}
8229
Chris Wilsond2dff872011-04-19 08:36:26 +01008230static u32
8231intel_framebuffer_pitch_for_width(int width, int bpp)
8232{
8233 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8234 return ALIGN(pitch, 64);
8235}
8236
8237static u32
8238intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8239{
8240 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8241 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8242}
8243
8244static struct drm_framebuffer *
8245intel_framebuffer_create_for_mode(struct drm_device *dev,
8246 struct drm_display_mode *mode,
8247 int depth, int bpp)
8248{
8249 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008250 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008251
8252 obj = i915_gem_alloc_object(dev,
8253 intel_framebuffer_size_for_mode(mode, bpp));
8254 if (obj == NULL)
8255 return ERR_PTR(-ENOMEM);
8256
8257 mode_cmd.width = mode->hdisplay;
8258 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008259 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8260 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008261 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008262
8263 return intel_framebuffer_create(dev, &mode_cmd, obj);
8264}
8265
8266static struct drm_framebuffer *
8267mode_fits_in_fbdev(struct drm_device *dev,
8268 struct drm_display_mode *mode)
8269{
Daniel Vetter4520f532013-10-09 09:18:51 +02008270#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008271 struct drm_i915_private *dev_priv = dev->dev_private;
8272 struct drm_i915_gem_object *obj;
8273 struct drm_framebuffer *fb;
8274
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008275 if (!dev_priv->fbdev)
8276 return NULL;
8277
8278 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008279 return NULL;
8280
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008281 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008282 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008283
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008284 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008285 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8286 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008287 return NULL;
8288
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008289 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008290 return NULL;
8291
8292 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008293#else
8294 return NULL;
8295#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008296}
8297
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008298bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008299 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05008300 struct intel_load_detect_pipe *old,
8301 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008302{
8303 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008304 struct intel_encoder *intel_encoder =
8305 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008306 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008307 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008308 struct drm_crtc *crtc = NULL;
8309 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008310 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05008311 struct drm_mode_config *config = &dev->mode_config;
8312 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008313
Chris Wilsond2dff872011-04-19 08:36:26 +01008314 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008315 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008316 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008317
Rob Clark51fd3712013-11-19 12:10:12 -05008318 drm_modeset_acquire_init(ctx, 0);
8319
8320retry:
8321 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8322 if (ret)
8323 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008324
Jesse Barnes79e53942008-11-07 14:24:08 -08008325 /*
8326 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008327 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008328 * - if the connector already has an assigned crtc, use it (but make
8329 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008330 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008331 * - try to find the first unused crtc that can drive this connector,
8332 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008333 */
8334
8335 /* See if we already have a CRTC for this connector */
8336 if (encoder->crtc) {
8337 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008338
Rob Clark51fd3712013-11-19 12:10:12 -05008339 ret = drm_modeset_lock(&crtc->mutex, ctx);
8340 if (ret)
8341 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01008342
Daniel Vetter24218aa2012-08-12 19:27:11 +02008343 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008344 old->load_detect_temp = false;
8345
8346 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008347 if (connector->dpms != DRM_MODE_DPMS_ON)
8348 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008349
Chris Wilson71731882011-04-19 23:10:58 +01008350 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008351 }
8352
8353 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008354 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008355 i++;
8356 if (!(encoder->possible_crtcs & (1 << i)))
8357 continue;
8358 if (!possible_crtc->enabled) {
8359 crtc = possible_crtc;
8360 break;
8361 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008362 }
8363
8364 /*
8365 * If we didn't find an unused CRTC, don't use any.
8366 */
8367 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008368 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05008369 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08008370 }
8371
Rob Clark51fd3712013-11-19 12:10:12 -05008372 ret = drm_modeset_lock(&crtc->mutex, ctx);
8373 if (ret)
8374 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02008375 intel_encoder->new_crtc = to_intel_crtc(crtc);
8376 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008377
8378 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008379 intel_crtc->new_enabled = true;
8380 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008381 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008382 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008383 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008384
Chris Wilson64927112011-04-20 07:25:26 +01008385 if (!mode)
8386 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008387
Chris Wilsond2dff872011-04-19 08:36:26 +01008388 /* We need a framebuffer large enough to accommodate all accesses
8389 * that the plane may generate whilst we perform load detection.
8390 * We can not rely on the fbcon either being present (we get called
8391 * during its initialisation to detect all boot displays, or it may
8392 * not even exist) or that it is large enough to satisfy the
8393 * requested mode.
8394 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008395 fb = mode_fits_in_fbdev(dev, mode);
8396 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008397 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008398 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8399 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008400 } else
8401 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008402 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008403 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008404 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008405 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008406
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008407 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008408 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008409 if (old->release_fb)
8410 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008411 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008412 }
Chris Wilson71731882011-04-19 23:10:58 +01008413
Jesse Barnes79e53942008-11-07 14:24:08 -08008414 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008415 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008416 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008417
8418 fail:
8419 intel_crtc->new_enabled = crtc->enabled;
8420 if (intel_crtc->new_enabled)
8421 intel_crtc->new_config = &intel_crtc->config;
8422 else
8423 intel_crtc->new_config = NULL;
Rob Clark51fd3712013-11-19 12:10:12 -05008424fail_unlock:
8425 if (ret == -EDEADLK) {
8426 drm_modeset_backoff(ctx);
8427 goto retry;
8428 }
8429
8430 drm_modeset_drop_locks(ctx);
8431 drm_modeset_acquire_fini(ctx);
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008432
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008433 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008434}
8435
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008436void intel_release_load_detect_pipe(struct drm_connector *connector,
Rob Clark51fd3712013-11-19 12:10:12 -05008437 struct intel_load_detect_pipe *old,
8438 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008439{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008440 struct intel_encoder *intel_encoder =
8441 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008442 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008443 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008445
Chris Wilsond2dff872011-04-19 08:36:26 +01008446 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008447 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008448 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008449
Chris Wilson8261b192011-04-19 23:18:09 +01008450 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008451 to_intel_connector(connector)->new_encoder = NULL;
8452 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008453 intel_crtc->new_enabled = false;
8454 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008455 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008456
Daniel Vetter36206362012-12-10 20:42:17 +01008457 if (old->release_fb) {
8458 drm_framebuffer_unregister_private(old->release_fb);
8459 drm_framebuffer_unreference(old->release_fb);
8460 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008461
Rob Clark51fd3712013-11-19 12:10:12 -05008462 goto unlock;
Chris Wilson0622a532011-04-21 09:32:11 +01008463 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008464 }
8465
Eric Anholtc751ce42010-03-25 11:48:48 -07008466 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008467 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8468 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01008469
Rob Clark51fd3712013-11-19 12:10:12 -05008470unlock:
8471 drm_modeset_drop_locks(ctx);
8472 drm_modeset_acquire_fini(ctx);
Jesse Barnes79e53942008-11-07 14:24:08 -08008473}
8474
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008475static int i9xx_pll_refclk(struct drm_device *dev,
8476 const struct intel_crtc_config *pipe_config)
8477{
8478 struct drm_i915_private *dev_priv = dev->dev_private;
8479 u32 dpll = pipe_config->dpll_hw_state.dpll;
8480
8481 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008482 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008483 else if (HAS_PCH_SPLIT(dev))
8484 return 120000;
8485 else if (!IS_GEN2(dev))
8486 return 96000;
8487 else
8488 return 48000;
8489}
8490
Jesse Barnes79e53942008-11-07 14:24:08 -08008491/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008492static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8493 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008494{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008495 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008496 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008497 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008498 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008499 u32 fp;
8500 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008501 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008502
8503 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008504 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008505 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008506 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008507
8508 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008509 if (IS_PINEVIEW(dev)) {
8510 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8511 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008512 } else {
8513 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8514 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8515 }
8516
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008517 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008518 if (IS_PINEVIEW(dev))
8519 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8520 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008521 else
8522 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008523 DPLL_FPA01_P1_POST_DIV_SHIFT);
8524
8525 switch (dpll & DPLL_MODE_MASK) {
8526 case DPLLB_MODE_DAC_SERIAL:
8527 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8528 5 : 10;
8529 break;
8530 case DPLLB_MODE_LVDS:
8531 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8532 7 : 14;
8533 break;
8534 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008535 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008536 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008537 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008538 }
8539
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008540 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008541 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008542 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008543 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008544 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008545 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008546 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008547
8548 if (is_lvds) {
8549 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8550 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008551
8552 if (lvds & LVDS_CLKB_POWER_UP)
8553 clock.p2 = 7;
8554 else
8555 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008556 } else {
8557 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8558 clock.p1 = 2;
8559 else {
8560 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8561 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8562 }
8563 if (dpll & PLL_P2_DIVIDE_BY_4)
8564 clock.p2 = 4;
8565 else
8566 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008567 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008568
8569 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008570 }
8571
Ville Syrjälä18442d02013-09-13 16:00:08 +03008572 /*
8573 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008574 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008575 * encoder's get_config() function.
8576 */
8577 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008578}
8579
Ville Syrjälä6878da02013-09-13 15:59:11 +03008580int intel_dotclock_calculate(int link_freq,
8581 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008582{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008583 /*
8584 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008585 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008586 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008587 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008588 *
8589 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008590 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008591 */
8592
Ville Syrjälä6878da02013-09-13 15:59:11 +03008593 if (!m_n->link_n)
8594 return 0;
8595
8596 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8597}
8598
Ville Syrjälä18442d02013-09-13 16:00:08 +03008599static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8600 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008601{
8602 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008603
8604 /* read out port_clock from the DPLL */
8605 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008606
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008607 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008608 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008609 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008610 * agree once we know their relationship in the encoder's
8611 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008612 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008613 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008614 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8615 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008616}
8617
8618/** Returns the currently programmed mode of the given pipe. */
8619struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8620 struct drm_crtc *crtc)
8621{
Jesse Barnes548f2452011-02-17 10:40:53 -08008622 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008624 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008625 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008626 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008627 int htot = I915_READ(HTOTAL(cpu_transcoder));
8628 int hsync = I915_READ(HSYNC(cpu_transcoder));
8629 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8630 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008631 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008632
8633 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8634 if (!mode)
8635 return NULL;
8636
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008637 /*
8638 * Construct a pipe_config sufficient for getting the clock info
8639 * back out of crtc_clock_get.
8640 *
8641 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8642 * to use a real value here instead.
8643 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008644 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008645 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008646 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8647 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8648 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008649 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8650
Ville Syrjälä773ae032013-09-23 17:48:20 +03008651 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008652 mode->hdisplay = (htot & 0xffff) + 1;
8653 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8654 mode->hsync_start = (hsync & 0xffff) + 1;
8655 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8656 mode->vdisplay = (vtot & 0xffff) + 1;
8657 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8658 mode->vsync_start = (vsync & 0xffff) + 1;
8659 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8660
8661 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008662
8663 return mode;
8664}
8665
Daniel Vetter3dec0092010-08-20 21:40:52 +02008666static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07008667{
8668 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008669 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8671 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008672 int dpll_reg = DPLL(pipe);
8673 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07008674
Eric Anholtbad720f2009-10-22 16:11:14 -07008675 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008676 return;
8677
8678 if (!dev_priv->lvds_downclock_avail)
8679 return;
8680
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008681 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008682 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08008683 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008684
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008685 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008686
8687 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8688 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008689 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008690
Jesse Barnes652c3932009-08-17 13:31:43 -07008691 dpll = I915_READ(dpll_reg);
8692 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08008693 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008694 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008695}
8696
8697static void intel_decrease_pllclock(struct drm_crtc *crtc)
8698{
8699 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008700 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008702
Eric Anholtbad720f2009-10-22 16:11:14 -07008703 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008704 return;
8705
8706 if (!dev_priv->lvds_downclock_avail)
8707 return;
8708
8709 /*
8710 * Since this is called by a timer, we should never get here in
8711 * the manual case.
8712 */
8713 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008714 int pipe = intel_crtc->pipe;
8715 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008716 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008717
Zhao Yakui44d98a62009-10-09 11:39:40 +08008718 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008719
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008720 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008721
Chris Wilson074b5e12012-05-02 12:07:06 +01008722 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008723 dpll |= DISPLAY_RATE_SELECT_FPA1;
8724 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008725 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008726 dpll = I915_READ(dpll_reg);
8727 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008728 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008729 }
8730
8731}
8732
Chris Wilsonf047e392012-07-21 12:31:41 +01008733void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008734{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008735 struct drm_i915_private *dev_priv = dev->dev_private;
8736
Chris Wilsonf62a0072014-02-21 17:55:39 +00008737 if (dev_priv->mm.busy)
8738 return;
8739
Paulo Zanoni43694d62014-03-07 20:08:08 -03008740 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008741 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008742 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008743}
8744
8745void intel_mark_idle(struct drm_device *dev)
8746{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008747 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008748 struct drm_crtc *crtc;
8749
Chris Wilsonf62a0072014-02-21 17:55:39 +00008750 if (!dev_priv->mm.busy)
8751 return;
8752
8753 dev_priv->mm.busy = false;
8754
Jani Nikulad330a952014-01-21 11:24:25 +02008755 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008756 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008757
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008758 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008759 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008760 continue;
8761
8762 intel_decrease_pllclock(crtc);
8763 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008764
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008765 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008766 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008767
8768out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03008769 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008770}
8771
Chris Wilsonc65355b2013-06-06 16:53:41 -03008772void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01008773 struct intel_engine_cs *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01008774{
8775 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07008776 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07008777
Jani Nikulad330a952014-01-21 11:24:25 +02008778 if (!i915.powersave)
Jesse Barnes652c3932009-08-17 13:31:43 -07008779 return;
8780
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008781 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008782 if (!crtc->primary->fb)
Jesse Barnes652c3932009-08-17 13:31:43 -07008783 continue;
8784
Matt Roperf4510a22014-04-01 15:22:40 -07008785 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
Chris Wilsonc65355b2013-06-06 16:53:41 -03008786 continue;
8787
8788 intel_increase_pllclock(crtc);
8789 if (ring && intel_fbc_enabled(dev))
8790 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07008791 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008792}
8793
Jesse Barnes79e53942008-11-07 14:24:08 -08008794static void intel_crtc_destroy(struct drm_crtc *crtc)
8795{
8796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008797 struct drm_device *dev = crtc->dev;
8798 struct intel_unpin_work *work;
8799 unsigned long flags;
8800
8801 spin_lock_irqsave(&dev->event_lock, flags);
8802 work = intel_crtc->unpin_work;
8803 intel_crtc->unpin_work = NULL;
8804 spin_unlock_irqrestore(&dev->event_lock, flags);
8805
8806 if (work) {
8807 cancel_work_sync(&work->work);
8808 kfree(work);
8809 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008810
Mika Kuoppala40ccc722013-04-23 17:27:08 +03008811 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8812
Jesse Barnes79e53942008-11-07 14:24:08 -08008813 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008814
Jesse Barnes79e53942008-11-07 14:24:08 -08008815 kfree(intel_crtc);
8816}
8817
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008818static void intel_unpin_work_fn(struct work_struct *__work)
8819{
8820 struct intel_unpin_work *work =
8821 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008822 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008823
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008824 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01008825 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00008826 drm_gem_object_unreference(&work->pending_flip_obj->base);
8827 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008828
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008829 intel_update_fbc(dev);
8830 mutex_unlock(&dev->struct_mutex);
8831
8832 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8833 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8834
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008835 kfree(work);
8836}
8837
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008838static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01008839 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008840{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008841 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8843 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008844 unsigned long flags;
8845
8846 /* Ignore early vblank irqs */
8847 if (intel_crtc == NULL)
8848 return;
8849
8850 spin_lock_irqsave(&dev->event_lock, flags);
8851 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00008852
8853 /* Ensure we don't miss a work->pending update ... */
8854 smp_rmb();
8855
8856 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008857 spin_unlock_irqrestore(&dev->event_lock, flags);
8858 return;
8859 }
8860
Chris Wilsone7d841c2012-12-03 11:36:30 +00008861 /* and that the unpin work is consistent wrt ->pending. */
8862 smp_rmb();
8863
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008864 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008865
Rob Clark45a066e2012-10-08 14:50:40 -05008866 if (work->event)
8867 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008868
Daniel Vetter87b6b102014-05-15 15:33:46 +02008869 drm_crtc_vblank_put(crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01008870
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008871 spin_unlock_irqrestore(&dev->event_lock, flags);
8872
Daniel Vetter2c10d572012-12-20 21:24:07 +01008873 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008874
8875 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07008876
8877 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008878}
8879
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008880void intel_finish_page_flip(struct drm_device *dev, int pipe)
8881{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008882 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008883 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8884
Mario Kleiner49b14a52010-12-09 07:00:07 +01008885 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008886}
8887
8888void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8889{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008890 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008891 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8892
Mario Kleiner49b14a52010-12-09 07:00:07 +01008893 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008894}
8895
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008896/* Is 'a' after or equal to 'b'? */
8897static bool g4x_flip_count_after_eq(u32 a, u32 b)
8898{
8899 return !((a - b) & 0x80000000);
8900}
8901
8902static bool page_flip_finished(struct intel_crtc *crtc)
8903{
8904 struct drm_device *dev = crtc->base.dev;
8905 struct drm_i915_private *dev_priv = dev->dev_private;
8906
8907 /*
8908 * The relevant registers doen't exist on pre-ctg.
8909 * As the flip done interrupt doesn't trigger for mmio
8910 * flips on gmch platforms, a flip count check isn't
8911 * really needed there. But since ctg has the registers,
8912 * include it in the check anyway.
8913 */
8914 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8915 return true;
8916
8917 /*
8918 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8919 * used the same base address. In that case the mmio flip might
8920 * have completed, but the CS hasn't even executed the flip yet.
8921 *
8922 * A flip count check isn't enough as the CS might have updated
8923 * the base address just after start of vblank, but before we
8924 * managed to process the interrupt. This means we'd complete the
8925 * CS flip too soon.
8926 *
8927 * Combining both checks should get us a good enough result. It may
8928 * still happen that the CS flip has been executed, but has not
8929 * yet actually completed. But in case the base address is the same
8930 * anyway, we don't really care.
8931 */
8932 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8933 crtc->unpin_work->gtt_offset &&
8934 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8935 crtc->unpin_work->flip_count);
8936}
8937
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008938void intel_prepare_page_flip(struct drm_device *dev, int plane)
8939{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008940 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008941 struct intel_crtc *intel_crtc =
8942 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8943 unsigned long flags;
8944
Chris Wilsone7d841c2012-12-03 11:36:30 +00008945 /* NB: An MMIO update of the plane base pointer will also
8946 * generate a page-flip completion irq, i.e. every modeset
8947 * is also accompanied by a spurious intel_prepare_page_flip().
8948 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008949 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008950 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00008951 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008952 spin_unlock_irqrestore(&dev->event_lock, flags);
8953}
8954
Robin Schroereba905b2014-05-18 02:24:50 +02008955static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00008956{
8957 /* Ensure that the work item is consistent when activating it ... */
8958 smp_wmb();
8959 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8960 /* and that it is marked active as soon as the irq could fire. */
8961 smp_wmb();
8962}
8963
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008964static int intel_gen2_queue_flip(struct drm_device *dev,
8965 struct drm_crtc *crtc,
8966 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008967 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01008968 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07008969 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008970{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008972 u32 flip_mask;
8973 int ret;
8974
Daniel Vetter6d90c952012-04-26 23:28:05 +02008975 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008976 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03008977 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008978
8979 /* Can't queue multiple flips, so wait for the previous
8980 * one to finish before executing the next.
8981 */
8982 if (intel_crtc->plane)
8983 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8984 else
8985 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008986 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8987 intel_ring_emit(ring, MI_NOOP);
8988 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8989 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8990 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03008991 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008992 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00008993
8994 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008995 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008996 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008997}
8998
8999static int intel_gen3_queue_flip(struct drm_device *dev,
9000 struct drm_crtc *crtc,
9001 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009002 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009003 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009004 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009005{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009007 u32 flip_mask;
9008 int ret;
9009
Daniel Vetter6d90c952012-04-26 23:28:05 +02009010 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009011 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009012 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009013
9014 if (intel_crtc->plane)
9015 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9016 else
9017 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009018 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9019 intel_ring_emit(ring, MI_NOOP);
9020 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9021 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9022 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009023 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009024 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009025
Chris Wilsone7d841c2012-12-03 11:36:30 +00009026 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009027 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009028 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009029}
9030
9031static int intel_gen4_queue_flip(struct drm_device *dev,
9032 struct drm_crtc *crtc,
9033 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009034 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009035 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009036 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009037{
9038 struct drm_i915_private *dev_priv = dev->dev_private;
9039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9040 uint32_t pf, pipesrc;
9041 int ret;
9042
Daniel Vetter6d90c952012-04-26 23:28:05 +02009043 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009044 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009045 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009046
9047 /* i965+ uses the linear or tiled offsets from the
9048 * Display Registers (which do not change across a page-flip)
9049 * so we need only reprogram the base address.
9050 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009051 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9052 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9053 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009054 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009055 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009056
9057 /* XXX Enabling the panel-fitter across page-flip is so far
9058 * untested on non-native modes, so ignore it for now.
9059 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9060 */
9061 pf = 0;
9062 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009063 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009064
9065 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009066 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009067 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009068}
9069
9070static int intel_gen6_queue_flip(struct drm_device *dev,
9071 struct drm_crtc *crtc,
9072 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009073 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009074 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009075 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009076{
9077 struct drm_i915_private *dev_priv = dev->dev_private;
9078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9079 uint32_t pf, pipesrc;
9080 int ret;
9081
Daniel Vetter6d90c952012-04-26 23:28:05 +02009082 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009083 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009084 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009085
Daniel Vetter6d90c952012-04-26 23:28:05 +02009086 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9087 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9088 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009089 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009090
Chris Wilson99d9acd2012-04-17 20:37:00 +01009091 /* Contrary to the suggestions in the documentation,
9092 * "Enable Panel Fitter" does not seem to be required when page
9093 * flipping with a non-native mode, and worse causes a normal
9094 * modeset to fail.
9095 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9096 */
9097 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009098 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009099 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009100
9101 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009102 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009103 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009104}
9105
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009106static int intel_gen7_queue_flip(struct drm_device *dev,
9107 struct drm_crtc *crtc,
9108 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009109 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009110 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009111 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009112{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009114 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009115 int len, ret;
9116
Robin Schroereba905b2014-05-18 02:24:50 +02009117 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009118 case PLANE_A:
9119 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9120 break;
9121 case PLANE_B:
9122 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9123 break;
9124 case PLANE_C:
9125 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9126 break;
9127 default:
9128 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009129 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009130 }
9131
Chris Wilsonffe74d72013-08-26 20:58:12 +01009132 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009133 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009134 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009135 /*
9136 * On Gen 8, SRM is now taking an extra dword to accommodate
9137 * 48bits addresses, and we need a NOOP for the batch size to
9138 * stay even.
9139 */
9140 if (IS_GEN8(dev))
9141 len += 2;
9142 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009143
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009144 /*
9145 * BSpec MI_DISPLAY_FLIP for IVB:
9146 * "The full packet must be contained within the same cache line."
9147 *
9148 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9149 * cacheline, if we ever start emitting more commands before
9150 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9151 * then do the cacheline alignment, and finally emit the
9152 * MI_DISPLAY_FLIP.
9153 */
9154 ret = intel_ring_cacheline_align(ring);
9155 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009156 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009157
Chris Wilsonffe74d72013-08-26 20:58:12 +01009158 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009159 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009160 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009161
Chris Wilsonffe74d72013-08-26 20:58:12 +01009162 /* Unmask the flip-done completion message. Note that the bspec says that
9163 * we should do this for both the BCS and RCS, and that we must not unmask
9164 * more than one flip event at any time (or ensure that one flip message
9165 * can be sent by waiting for flip-done prior to queueing new flips).
9166 * Experimentation says that BCS works despite DERRMR masking all
9167 * flip-done completion events and that unmasking all planes at once
9168 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9169 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9170 */
9171 if (ring->id == RCS) {
9172 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9173 intel_ring_emit(ring, DERRMR);
9174 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9175 DERRMR_PIPEB_PRI_FLIP_DONE |
9176 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009177 if (IS_GEN8(dev))
9178 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9179 MI_SRM_LRM_GLOBAL_GTT);
9180 else
9181 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9182 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009183 intel_ring_emit(ring, DERRMR);
9184 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009185 if (IS_GEN8(dev)) {
9186 intel_ring_emit(ring, 0);
9187 intel_ring_emit(ring, MI_NOOP);
9188 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009189 }
9190
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009191 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009192 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009193 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009194 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009195
9196 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009197 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009198 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009199}
9200
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009201static int intel_default_queue_flip(struct drm_device *dev,
9202 struct drm_crtc *crtc,
9203 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009204 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009205 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009206 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009207{
9208 return -ENODEV;
9209}
9210
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009211static int intel_crtc_page_flip(struct drm_crtc *crtc,
9212 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009213 struct drm_pending_vblank_event *event,
9214 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009215{
9216 struct drm_device *dev = crtc->dev;
9217 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009218 struct drm_framebuffer *old_fb = crtc->primary->fb;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02009219 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9221 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009222 struct intel_engine_cs *ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009223 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01009224 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009225
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009226 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009227 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009228 return -EINVAL;
9229
9230 /*
9231 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9232 * Note that pitch changes could also affect these register.
9233 */
9234 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009235 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9236 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009237 return -EINVAL;
9238
Chris Wilsonf900db42014-02-20 09:26:13 +00009239 if (i915_terminally_wedged(&dev_priv->gpu_error))
9240 goto out_hang;
9241
Daniel Vetterb14c5672013-09-19 12:18:32 +02009242 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009243 if (work == NULL)
9244 return -ENOMEM;
9245
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009246 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009247 work->crtc = crtc;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02009248 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009249 INIT_WORK(&work->work, intel_unpin_work_fn);
9250
Daniel Vetter87b6b102014-05-15 15:33:46 +02009251 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009252 if (ret)
9253 goto free_work;
9254
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009255 /* We borrow the event spin lock for protecting unpin_work */
9256 spin_lock_irqsave(&dev->event_lock, flags);
9257 if (intel_crtc->unpin_work) {
9258 spin_unlock_irqrestore(&dev->event_lock, flags);
9259 kfree(work);
Daniel Vetter87b6b102014-05-15 15:33:46 +02009260 drm_crtc_vblank_put(crtc);
Chris Wilson468f0b42010-05-27 13:18:13 +01009261
9262 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009263 return -EBUSY;
9264 }
9265 intel_crtc->unpin_work = work;
9266 spin_unlock_irqrestore(&dev->event_lock, flags);
9267
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009268 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9269 flush_workqueue(dev_priv->wq);
9270
Chris Wilson79158102012-05-23 11:13:58 +01009271 ret = i915_mutex_lock_interruptible(dev);
9272 if (ret)
9273 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009274
Jesse Barnes75dfca82010-02-10 15:09:44 -08009275 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009276 drm_gem_object_reference(&work->old_fb_obj->base);
9277 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009278
Matt Roperf4510a22014-04-01 15:22:40 -07009279 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009280
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009281 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009282
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01009283 work->enable_stall_check = true;
9284
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009285 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009286 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009287
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009288 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9289 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9290
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009291 if (IS_VALLEYVIEW(dev)) {
9292 ring = &dev_priv->ring[BCS];
9293 } else if (INTEL_INFO(dev)->gen >= 7) {
9294 ring = obj->ring;
9295 if (ring == NULL || ring->id != RCS)
9296 ring = &dev_priv->ring[BCS];
9297 } else {
9298 ring = &dev_priv->ring[RCS];
9299 }
9300
9301 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009302 if (ret)
9303 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009304
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009305 work->gtt_offset =
9306 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9307
9308 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags);
9309 if (ret)
9310 goto cleanup_unpin;
9311
Chris Wilson7782de32011-07-08 12:22:41 +01009312 intel_disable_fbc(dev);
Chris Wilsonc65355b2013-06-06 16:53:41 -03009313 intel_mark_fb_busy(obj, NULL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009314 mutex_unlock(&dev->struct_mutex);
9315
Jesse Barnese5510fa2010-07-01 16:48:37 -07009316 trace_i915_flip_request(intel_crtc->plane, obj);
9317
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009318 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009319
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009320cleanup_unpin:
9321 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009322cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009323 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009324 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009325 drm_gem_object_unreference(&work->old_fb_obj->base);
9326 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009327 mutex_unlock(&dev->struct_mutex);
9328
Chris Wilson79158102012-05-23 11:13:58 +01009329cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01009330 spin_lock_irqsave(&dev->event_lock, flags);
9331 intel_crtc->unpin_work = NULL;
9332 spin_unlock_irqrestore(&dev->event_lock, flags);
9333
Daniel Vetter87b6b102014-05-15 15:33:46 +02009334 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009335free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009336 kfree(work);
9337
Chris Wilsonf900db42014-02-20 09:26:13 +00009338 if (ret == -EIO) {
9339out_hang:
9340 intel_crtc_wait_for_pending_flips(crtc);
9341 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9342 if (ret == 0 && event)
9343 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9344 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009345 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009346}
9347
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009348static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009349 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9350 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009351};
9352
Daniel Vetter9a935852012-07-05 22:34:27 +02009353/**
9354 * intel_modeset_update_staged_output_state
9355 *
9356 * Updates the staged output configuration state, e.g. after we've read out the
9357 * current hw state.
9358 */
9359static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9360{
Ville Syrjälä76688512014-01-10 11:28:06 +02009361 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009362 struct intel_encoder *encoder;
9363 struct intel_connector *connector;
9364
9365 list_for_each_entry(connector, &dev->mode_config.connector_list,
9366 base.head) {
9367 connector->new_encoder =
9368 to_intel_encoder(connector->base.encoder);
9369 }
9370
9371 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9372 base.head) {
9373 encoder->new_crtc =
9374 to_intel_crtc(encoder->base.crtc);
9375 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009376
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009377 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009378 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009379
9380 if (crtc->new_enabled)
9381 crtc->new_config = &crtc->config;
9382 else
9383 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009384 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009385}
9386
9387/**
9388 * intel_modeset_commit_output_state
9389 *
9390 * This function copies the stage display pipe configuration to the real one.
9391 */
9392static void intel_modeset_commit_output_state(struct drm_device *dev)
9393{
Ville Syrjälä76688512014-01-10 11:28:06 +02009394 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009395 struct intel_encoder *encoder;
9396 struct intel_connector *connector;
9397
9398 list_for_each_entry(connector, &dev->mode_config.connector_list,
9399 base.head) {
9400 connector->base.encoder = &connector->new_encoder->base;
9401 }
9402
9403 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9404 base.head) {
9405 encoder->base.crtc = &encoder->new_crtc->base;
9406 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009407
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009408 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009409 crtc->base.enabled = crtc->new_enabled;
9410 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009411}
9412
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009413static void
Robin Schroereba905b2014-05-18 02:24:50 +02009414connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009415 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009416{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009417 int bpp = pipe_config->pipe_bpp;
9418
9419 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9420 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009421 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009422
9423 /* Don't use an invalid EDID bpc value */
9424 if (connector->base.display_info.bpc &&
9425 connector->base.display_info.bpc * 3 < bpp) {
9426 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9427 bpp, connector->base.display_info.bpc*3);
9428 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9429 }
9430
9431 /* Clamp bpp to 8 on screens without EDID 1.4 */
9432 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9433 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9434 bpp);
9435 pipe_config->pipe_bpp = 24;
9436 }
9437}
9438
9439static int
9440compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9441 struct drm_framebuffer *fb,
9442 struct intel_crtc_config *pipe_config)
9443{
9444 struct drm_device *dev = crtc->base.dev;
9445 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009446 int bpp;
9447
Daniel Vetterd42264b2013-03-28 16:38:08 +01009448 switch (fb->pixel_format) {
9449 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009450 bpp = 8*3; /* since we go through a colormap */
9451 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009452 case DRM_FORMAT_XRGB1555:
9453 case DRM_FORMAT_ARGB1555:
9454 /* checked in intel_framebuffer_init already */
9455 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9456 return -EINVAL;
9457 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009458 bpp = 6*3; /* min is 18bpp */
9459 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009460 case DRM_FORMAT_XBGR8888:
9461 case DRM_FORMAT_ABGR8888:
9462 /* checked in intel_framebuffer_init already */
9463 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9464 return -EINVAL;
9465 case DRM_FORMAT_XRGB8888:
9466 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009467 bpp = 8*3;
9468 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009469 case DRM_FORMAT_XRGB2101010:
9470 case DRM_FORMAT_ARGB2101010:
9471 case DRM_FORMAT_XBGR2101010:
9472 case DRM_FORMAT_ABGR2101010:
9473 /* checked in intel_framebuffer_init already */
9474 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01009475 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009476 bpp = 10*3;
9477 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01009478 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009479 default:
9480 DRM_DEBUG_KMS("unsupported depth\n");
9481 return -EINVAL;
9482 }
9483
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009484 pipe_config->pipe_bpp = bpp;
9485
9486 /* Clamp display bpp to EDID value */
9487 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009488 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02009489 if (!connector->new_encoder ||
9490 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009491 continue;
9492
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009493 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009494 }
9495
9496 return bpp;
9497}
9498
Daniel Vetter644db712013-09-19 14:53:58 +02009499static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9500{
9501 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9502 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +01009503 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +02009504 mode->crtc_hdisplay, mode->crtc_hsync_start,
9505 mode->crtc_hsync_end, mode->crtc_htotal,
9506 mode->crtc_vdisplay, mode->crtc_vsync_start,
9507 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9508}
9509
Daniel Vetterc0b03412013-05-28 12:05:54 +02009510static void intel_dump_pipe_config(struct intel_crtc *crtc,
9511 struct intel_crtc_config *pipe_config,
9512 const char *context)
9513{
9514 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9515 context, pipe_name(crtc->pipe));
9516
9517 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9518 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9519 pipe_config->pipe_bpp, pipe_config->dither);
9520 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9521 pipe_config->has_pch_encoder,
9522 pipe_config->fdi_lanes,
9523 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9524 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9525 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009526 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9527 pipe_config->has_dp_encoder,
9528 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9529 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9530 pipe_config->dp_m_n.tu);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009531 DRM_DEBUG_KMS("requested mode:\n");
9532 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9533 DRM_DEBUG_KMS("adjusted mode:\n");
9534 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +02009535 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009536 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009537 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9538 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009539 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9540 pipe_config->gmch_pfit.control,
9541 pipe_config->gmch_pfit.pgm_ratios,
9542 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009543 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +02009544 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009545 pipe_config->pch_pfit.size,
9546 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009547 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03009548 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009549}
9550
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009551static bool encoders_cloneable(const struct intel_encoder *a,
9552 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009553{
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009554 /* masks could be asymmetric, so check both ways */
9555 return a == b || (a->cloneable & (1 << b->type) &&
9556 b->cloneable & (1 << a->type));
9557}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009558
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009559static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9560 struct intel_encoder *encoder)
9561{
9562 struct drm_device *dev = crtc->base.dev;
9563 struct intel_encoder *source_encoder;
9564
9565 list_for_each_entry(source_encoder,
9566 &dev->mode_config.encoder_list, base.head) {
9567 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009568 continue;
9569
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009570 if (!encoders_cloneable(encoder, source_encoder))
9571 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009572 }
9573
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009574 return true;
9575}
9576
9577static bool check_encoder_cloning(struct intel_crtc *crtc)
9578{
9579 struct drm_device *dev = crtc->base.dev;
9580 struct intel_encoder *encoder;
9581
9582 list_for_each_entry(encoder,
9583 &dev->mode_config.encoder_list, base.head) {
9584 if (encoder->new_crtc != crtc)
9585 continue;
9586
9587 if (!check_single_encoder_cloning(crtc, encoder))
9588 return false;
9589 }
9590
9591 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009592}
9593
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009594static struct intel_crtc_config *
9595intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009596 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009597 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02009598{
9599 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02009600 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009601 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +01009602 int plane_bpp, ret = -EINVAL;
9603 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +02009604
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009605 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009606 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9607 return ERR_PTR(-EINVAL);
9608 }
9609
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009610 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9611 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02009612 return ERR_PTR(-ENOMEM);
9613
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009614 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9615 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009616
Daniel Vettere143a212013-07-04 12:01:15 +02009617 pipe_config->cpu_transcoder =
9618 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009619 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009620
Imre Deak2960bc92013-07-30 13:36:32 +03009621 /*
9622 * Sanitize sync polarity flags based on requested ones. If neither
9623 * positive or negative polarity is requested, treat this as meaning
9624 * negative polarity.
9625 */
9626 if (!(pipe_config->adjusted_mode.flags &
9627 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9628 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9629
9630 if (!(pipe_config->adjusted_mode.flags &
9631 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9632 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9633
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009634 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9635 * plane pixel format and any sink constraints into account. Returns the
9636 * source plane bpp so that dithering can be selected on mismatches
9637 * after encoders and crtc also have had their say. */
9638 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9639 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009640 if (plane_bpp < 0)
9641 goto fail;
9642
Ville Syrjäläe41a56b2013-10-01 22:52:14 +03009643 /*
9644 * Determine the real pipe dimensions. Note that stereo modes can
9645 * increase the actual pipe size due to the frame doubling and
9646 * insertion of additional space for blanks between the frame. This
9647 * is stored in the crtc timings. We use the requested mode to do this
9648 * computation to clearly distinguish it from the adjusted mode, which
9649 * can be changed by the connectors in the below retry loop.
9650 */
9651 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9652 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9653 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9654
Daniel Vettere29c22c2013-02-21 00:00:16 +01009655encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +02009656 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +02009657 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +02009658 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +02009659
Daniel Vetter135c81b2013-07-21 21:37:09 +02009660 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +01009661 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +02009662
Daniel Vetter7758a112012-07-08 19:40:39 +02009663 /* Pass our mode to the connectors and the CRTC to give them a chance to
9664 * adjust it according to limitations or connector properties, and also
9665 * a chance to reject the mode entirely.
9666 */
9667 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9668 base.head) {
9669
9670 if (&encoder->new_crtc->base != crtc)
9671 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +01009672
Daniel Vetterefea6e82013-07-21 21:36:59 +02009673 if (!(encoder->compute_config(encoder, pipe_config))) {
9674 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +02009675 goto fail;
9676 }
9677 }
9678
Daniel Vetterff9a6752013-06-01 17:16:21 +02009679 /* Set default port clock if not overwritten by the encoder. Needs to be
9680 * done afterwards in case the encoder adjusts the mode. */
9681 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +01009682 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9683 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +02009684
Daniel Vettera43f6e02013-06-07 23:10:32 +02009685 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01009686 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +02009687 DRM_DEBUG_KMS("CRTC fixup failed\n");
9688 goto fail;
9689 }
Daniel Vettere29c22c2013-02-21 00:00:16 +01009690
9691 if (ret == RETRY) {
9692 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9693 ret = -EINVAL;
9694 goto fail;
9695 }
9696
9697 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9698 retry = false;
9699 goto encoder_retry;
9700 }
9701
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009702 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9703 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9704 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9705
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009706 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +02009707fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009708 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01009709 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +02009710}
9711
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009712/* Computes which crtcs are affected and sets the relevant bits in the mask. For
9713 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9714static void
9715intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9716 unsigned *prepare_pipes, unsigned *disable_pipes)
9717{
9718 struct intel_crtc *intel_crtc;
9719 struct drm_device *dev = crtc->dev;
9720 struct intel_encoder *encoder;
9721 struct intel_connector *connector;
9722 struct drm_crtc *tmp_crtc;
9723
9724 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9725
9726 /* Check which crtcs have changed outputs connected to them, these need
9727 * to be part of the prepare_pipes mask. We don't (yet) support global
9728 * modeset across multiple crtcs, so modeset_pipes will only have one
9729 * bit set at most. */
9730 list_for_each_entry(connector, &dev->mode_config.connector_list,
9731 base.head) {
9732 if (connector->base.encoder == &connector->new_encoder->base)
9733 continue;
9734
9735 if (connector->base.encoder) {
9736 tmp_crtc = connector->base.encoder->crtc;
9737
9738 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9739 }
9740
9741 if (connector->new_encoder)
9742 *prepare_pipes |=
9743 1 << connector->new_encoder->new_crtc->pipe;
9744 }
9745
9746 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9747 base.head) {
9748 if (encoder->base.crtc == &encoder->new_crtc->base)
9749 continue;
9750
9751 if (encoder->base.crtc) {
9752 tmp_crtc = encoder->base.crtc;
9753
9754 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9755 }
9756
9757 if (encoder->new_crtc)
9758 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9759 }
9760
Ville Syrjälä76688512014-01-10 11:28:06 +02009761 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009762 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009763 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009764 continue;
9765
Ville Syrjälä76688512014-01-10 11:28:06 +02009766 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009767 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +02009768 else
9769 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009770 }
9771
9772
9773 /* set_mode is also used to update properties on life display pipes. */
9774 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +02009775 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009776 *prepare_pipes |= 1 << intel_crtc->pipe;
9777
Daniel Vetterb6c51642013-04-12 18:48:43 +02009778 /*
9779 * For simplicity do a full modeset on any pipe where the output routing
9780 * changed. We could be more clever, but that would require us to be
9781 * more careful with calling the relevant encoder->mode_set functions.
9782 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009783 if (*prepare_pipes)
9784 *modeset_pipes = *prepare_pipes;
9785
9786 /* ... and mask these out. */
9787 *modeset_pipes &= ~(*disable_pipes);
9788 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +02009789
9790 /*
9791 * HACK: We don't (yet) fully support global modesets. intel_set_config
9792 * obies this rule, but the modeset restore mode of
9793 * intel_modeset_setup_hw_state does not.
9794 */
9795 *modeset_pipes &= 1 << intel_crtc->pipe;
9796 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +02009797
9798 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9799 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009800}
9801
Daniel Vetterea9d7582012-07-10 10:42:52 +02009802static bool intel_crtc_in_use(struct drm_crtc *crtc)
9803{
9804 struct drm_encoder *encoder;
9805 struct drm_device *dev = crtc->dev;
9806
9807 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9808 if (encoder->crtc == crtc)
9809 return true;
9810
9811 return false;
9812}
9813
9814static void
9815intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9816{
9817 struct intel_encoder *intel_encoder;
9818 struct intel_crtc *intel_crtc;
9819 struct drm_connector *connector;
9820
9821 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9822 base.head) {
9823 if (!intel_encoder->base.crtc)
9824 continue;
9825
9826 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9827
9828 if (prepare_pipes & (1 << intel_crtc->pipe))
9829 intel_encoder->connectors_active = false;
9830 }
9831
9832 intel_modeset_commit_output_state(dev);
9833
Ville Syrjälä76688512014-01-10 11:28:06 +02009834 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009835 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009836 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009837 WARN_ON(intel_crtc->new_config &&
9838 intel_crtc->new_config != &intel_crtc->config);
9839 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +02009840 }
9841
9842 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9843 if (!connector->encoder || !connector->encoder->crtc)
9844 continue;
9845
9846 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9847
9848 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02009849 struct drm_property *dpms_property =
9850 dev->mode_config.dpms_property;
9851
Daniel Vetterea9d7582012-07-10 10:42:52 +02009852 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05009853 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02009854 dpms_property,
9855 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02009856
9857 intel_encoder = to_intel_encoder(connector->encoder);
9858 intel_encoder->connectors_active = true;
9859 }
9860 }
9861
9862}
9863
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009864static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009865{
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009866 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009867
9868 if (clock1 == clock2)
9869 return true;
9870
9871 if (!clock1 || !clock2)
9872 return false;
9873
9874 diff = abs(clock1 - clock2);
9875
9876 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9877 return true;
9878
9879 return false;
9880}
9881
Daniel Vetter25c5b262012-07-08 22:08:04 +02009882#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9883 list_for_each_entry((intel_crtc), \
9884 &(dev)->mode_config.crtc_list, \
9885 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +02009886 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +02009887
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009888static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009889intel_pipe_config_compare(struct drm_device *dev,
9890 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009891 struct intel_crtc_config *pipe_config)
9892{
Daniel Vetter66e985c2013-06-05 13:34:20 +02009893#define PIPE_CONF_CHECK_X(name) \
9894 if (current_config->name != pipe_config->name) { \
9895 DRM_ERROR("mismatch in " #name " " \
9896 "(expected 0x%08x, found 0x%08x)\n", \
9897 current_config->name, \
9898 pipe_config->name); \
9899 return false; \
9900 }
9901
Daniel Vetter08a24032013-04-19 11:25:34 +02009902#define PIPE_CONF_CHECK_I(name) \
9903 if (current_config->name != pipe_config->name) { \
9904 DRM_ERROR("mismatch in " #name " " \
9905 "(expected %i, found %i)\n", \
9906 current_config->name, \
9907 pipe_config->name); \
9908 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +01009909 }
9910
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009911#define PIPE_CONF_CHECK_FLAGS(name, mask) \
9912 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -07009913 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009914 "(expected %i, found %i)\n", \
9915 current_config->name & (mask), \
9916 pipe_config->name & (mask)); \
9917 return false; \
9918 }
9919
Ville Syrjälä5e550652013-09-06 23:29:07 +03009920#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9921 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9922 DRM_ERROR("mismatch in " #name " " \
9923 "(expected %i, found %i)\n", \
9924 current_config->name, \
9925 pipe_config->name); \
9926 return false; \
9927 }
9928
Daniel Vetterbb760062013-06-06 14:55:52 +02009929#define PIPE_CONF_QUIRK(quirk) \
9930 ((current_config->quirks | pipe_config->quirks) & (quirk))
9931
Daniel Vettereccb1402013-05-22 00:50:22 +02009932 PIPE_CONF_CHECK_I(cpu_transcoder);
9933
Daniel Vetter08a24032013-04-19 11:25:34 +02009934 PIPE_CONF_CHECK_I(has_pch_encoder);
9935 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +02009936 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9937 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9938 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9939 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9940 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +02009941
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009942 PIPE_CONF_CHECK_I(has_dp_encoder);
9943 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9944 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9945 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9946 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9947 PIPE_CONF_CHECK_I(dp_m_n.tu);
9948
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009949 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9950 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9951 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9952 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9953 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9954 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9955
9956 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9957 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9958 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9959 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9960 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9961 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9962
Daniel Vetterc93f54c2013-06-27 19:47:19 +02009963 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +02009964 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02009965 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9966 IS_VALLEYVIEW(dev))
9967 PIPE_CONF_CHECK_I(limited_color_range);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009968
Daniel Vetter9ed109a2014-04-24 23:54:52 +02009969 PIPE_CONF_CHECK_I(has_audio);
9970
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009971 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9972 DRM_MODE_FLAG_INTERLACE);
9973
Daniel Vetterbb760062013-06-06 14:55:52 +02009974 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9975 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9976 DRM_MODE_FLAG_PHSYNC);
9977 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9978 DRM_MODE_FLAG_NHSYNC);
9979 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9980 DRM_MODE_FLAG_PVSYNC);
9981 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9982 DRM_MODE_FLAG_NVSYNC);
9983 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009984
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009985 PIPE_CONF_CHECK_I(pipe_src_w);
9986 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009987
Daniel Vetter99535992014-04-13 12:00:33 +02009988 /*
9989 * FIXME: BIOS likes to set up a cloned config with lvds+external
9990 * screen. Since we don't yet re-compute the pipe config when moving
9991 * just the lvds port away to another pipe the sw tracking won't match.
9992 *
9993 * Proper atomic modesets with recomputed global state will fix this.
9994 * Until then just don't check gmch state for inherited modes.
9995 */
9996 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9997 PIPE_CONF_CHECK_I(gmch_pfit.control);
9998 /* pfit ratios are autocomputed by the hw on gen4+ */
9999 if (INTEL_INFO(dev)->gen < 4)
10000 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10001 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10002 }
10003
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010004 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10005 if (current_config->pch_pfit.enabled) {
10006 PIPE_CONF_CHECK_I(pch_pfit.pos);
10007 PIPE_CONF_CHECK_I(pch_pfit.size);
10008 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010009
Jesse Barnese59150d2014-01-07 13:30:45 -080010010 /* BDW+ don't expose a synchronous way to read the state */
10011 if (IS_HASWELL(dev))
10012 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010013
Ville Syrjälä282740f2013-09-04 18:30:03 +030010014 PIPE_CONF_CHECK_I(double_wide);
10015
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010016 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010017 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010018 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010019 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10020 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010021
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010022 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10023 PIPE_CONF_CHECK_I(pipe_bpp);
10024
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010025 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10026 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010027
Daniel Vetter66e985c2013-06-05 13:34:20 +020010028#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010029#undef PIPE_CONF_CHECK_I
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010030#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010031#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010032#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010033
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010034 return true;
10035}
10036
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010037static void
10038check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010039{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010040 struct intel_connector *connector;
10041
10042 list_for_each_entry(connector, &dev->mode_config.connector_list,
10043 base.head) {
10044 /* This also checks the encoder/connector hw state with the
10045 * ->get_hw_state callbacks. */
10046 intel_connector_check_state(connector);
10047
10048 WARN(&connector->new_encoder->base != connector->base.encoder,
10049 "connector's staged encoder doesn't match current encoder\n");
10050 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010051}
10052
10053static void
10054check_encoder_state(struct drm_device *dev)
10055{
10056 struct intel_encoder *encoder;
10057 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010058
10059 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10060 base.head) {
10061 bool enabled = false;
10062 bool active = false;
10063 enum pipe pipe, tracked_pipe;
10064
10065 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10066 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030010067 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010068
10069 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10070 "encoder's stage crtc doesn't match current crtc\n");
10071 WARN(encoder->connectors_active && !encoder->base.crtc,
10072 "encoder's active_connectors set, but no crtc\n");
10073
10074 list_for_each_entry(connector, &dev->mode_config.connector_list,
10075 base.head) {
10076 if (connector->base.encoder != &encoder->base)
10077 continue;
10078 enabled = true;
10079 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10080 active = true;
10081 }
10082 WARN(!!encoder->base.crtc != enabled,
10083 "encoder's enabled state mismatch "
10084 "(expected %i, found %i)\n",
10085 !!encoder->base.crtc, enabled);
10086 WARN(active && !encoder->base.crtc,
10087 "active encoder with no crtc\n");
10088
10089 WARN(encoder->connectors_active != active,
10090 "encoder's computed active state doesn't match tracked active state "
10091 "(expected %i, found %i)\n", active, encoder->connectors_active);
10092
10093 active = encoder->get_hw_state(encoder, &pipe);
10094 WARN(active != encoder->connectors_active,
10095 "encoder's hw state doesn't match sw tracking "
10096 "(expected %i, found %i)\n",
10097 encoder->connectors_active, active);
10098
10099 if (!encoder->base.crtc)
10100 continue;
10101
10102 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10103 WARN(active && pipe != tracked_pipe,
10104 "active encoder's pipe doesn't match"
10105 "(expected %i, found %i)\n",
10106 tracked_pipe, pipe);
10107
10108 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010109}
10110
10111static void
10112check_crtc_state(struct drm_device *dev)
10113{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010114 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010115 struct intel_crtc *crtc;
10116 struct intel_encoder *encoder;
10117 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010118
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010119 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010120 bool enabled = false;
10121 bool active = false;
10122
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010123 memset(&pipe_config, 0, sizeof(pipe_config));
10124
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010125 DRM_DEBUG_KMS("[CRTC:%d]\n",
10126 crtc->base.base.id);
10127
10128 WARN(crtc->active && !crtc->base.enabled,
10129 "active crtc, but not enabled in sw tracking\n");
10130
10131 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10132 base.head) {
10133 if (encoder->base.crtc != &crtc->base)
10134 continue;
10135 enabled = true;
10136 if (encoder->connectors_active)
10137 active = true;
10138 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010139
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010140 WARN(active != crtc->active,
10141 "crtc's computed active state doesn't match tracked active state "
10142 "(expected %i, found %i)\n", active, crtc->active);
10143 WARN(enabled != crtc->base.enabled,
10144 "crtc's computed enabled state doesn't match tracked enabled state "
10145 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10146
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010147 active = dev_priv->display.get_pipe_config(crtc,
10148 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010149
10150 /* hw state is inconsistent with the pipe A quirk */
10151 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10152 active = crtc->active;
10153
Daniel Vetter6c49f242013-06-06 12:45:25 +020010154 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10155 base.head) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010156 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010157 if (encoder->base.crtc != &crtc->base)
10158 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010159 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010160 encoder->get_config(encoder, &pipe_config);
10161 }
10162
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010163 WARN(crtc->active != active,
10164 "crtc active state doesn't match with hw state "
10165 "(expected %i, found %i)\n", crtc->active, active);
10166
Daniel Vetterc0b03412013-05-28 12:05:54 +020010167 if (active &&
10168 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10169 WARN(1, "pipe state doesn't match!\n");
10170 intel_dump_pipe_config(crtc, &pipe_config,
10171 "[hw state]");
10172 intel_dump_pipe_config(crtc, &crtc->config,
10173 "[sw state]");
10174 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010175 }
10176}
10177
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010178static void
10179check_shared_dpll_state(struct drm_device *dev)
10180{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010181 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010182 struct intel_crtc *crtc;
10183 struct intel_dpll_hw_state dpll_hw_state;
10184 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010185
10186 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10187 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10188 int enabled_crtcs = 0, active_crtcs = 0;
10189 bool active;
10190
10191 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10192
10193 DRM_DEBUG_KMS("%s\n", pll->name);
10194
10195 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10196
10197 WARN(pll->active > pll->refcount,
10198 "more active pll users than references: %i vs %i\n",
10199 pll->active, pll->refcount);
10200 WARN(pll->active && !pll->on,
10201 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010202 WARN(pll->on && !pll->active,
10203 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010204 WARN(pll->on != active,
10205 "pll on state mismatch (expected %i, found %i)\n",
10206 pll->on, active);
10207
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010208 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010209 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10210 enabled_crtcs++;
10211 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10212 active_crtcs++;
10213 }
10214 WARN(pll->active != active_crtcs,
10215 "pll active crtcs mismatch (expected %i, found %i)\n",
10216 pll->active, active_crtcs);
10217 WARN(pll->refcount != enabled_crtcs,
10218 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10219 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010220
10221 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10222 sizeof(dpll_hw_state)),
10223 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010224 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010225}
10226
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010227void
10228intel_modeset_check_state(struct drm_device *dev)
10229{
10230 check_connector_state(dev);
10231 check_encoder_state(dev);
10232 check_crtc_state(dev);
10233 check_shared_dpll_state(dev);
10234}
10235
Ville Syrjälä18442d02013-09-13 16:00:08 +030010236void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10237 int dotclock)
10238{
10239 /*
10240 * FDI already provided one idea for the dotclock.
10241 * Yell if the encoder disagrees.
10242 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010243 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010244 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010245 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010246}
10247
Ville Syrjälä80715b22014-05-15 20:23:23 +030010248static void update_scanline_offset(struct intel_crtc *crtc)
10249{
10250 struct drm_device *dev = crtc->base.dev;
10251
10252 /*
10253 * The scanline counter increments at the leading edge of hsync.
10254 *
10255 * On most platforms it starts counting from vtotal-1 on the
10256 * first active line. That means the scanline counter value is
10257 * always one less than what we would expect. Ie. just after
10258 * start of vblank, which also occurs at start of hsync (on the
10259 * last active line), the scanline counter will read vblank_start-1.
10260 *
10261 * On gen2 the scanline counter starts counting from 1 instead
10262 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10263 * to keep the value positive), instead of adding one.
10264 *
10265 * On HSW+ the behaviour of the scanline counter depends on the output
10266 * type. For DP ports it behaves like most other platforms, but on HDMI
10267 * there's an extra 1 line difference. So we need to add two instead of
10268 * one to the value.
10269 */
10270 if (IS_GEN2(dev)) {
10271 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10272 int vtotal;
10273
10274 vtotal = mode->crtc_vtotal;
10275 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10276 vtotal /= 2;
10277
10278 crtc->scanline_offset = vtotal - 1;
10279 } else if (HAS_DDI(dev) &&
10280 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10281 crtc->scanline_offset = 2;
10282 } else
10283 crtc->scanline_offset = 1;
10284}
10285
Daniel Vetterf30da182013-04-11 20:22:50 +020010286static int __intel_set_mode(struct drm_crtc *crtc,
10287 struct drm_display_mode *mode,
10288 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +020010289{
10290 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010291 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010292 struct drm_display_mode *saved_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010293 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010294 struct intel_crtc *intel_crtc;
10295 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010296 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010297
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010298 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010299 if (!saved_mode)
10300 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010301
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010302 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +020010303 &prepare_pipes, &disable_pipes);
10304
Tim Gardner3ac18232012-12-07 07:54:26 -070010305 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010306
Daniel Vetter25c5b262012-07-08 22:08:04 +020010307 /* Hack: Because we don't (yet) support global modeset on multiple
10308 * crtcs, we don't keep track of the new mode for more than one crtc.
10309 * Hence simply check whether any bit is set in modeset_pipes in all the
10310 * pieces of code that are not yet converted to deal with mutliple crtcs
10311 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010312 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010313 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010314 if (IS_ERR(pipe_config)) {
10315 ret = PTR_ERR(pipe_config);
10316 pipe_config = NULL;
10317
Tim Gardner3ac18232012-12-07 07:54:26 -070010318 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010319 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020010320 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10321 "[modeset]");
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010322 to_intel_crtc(crtc)->new_config = pipe_config;
Daniel Vettera6778b32012-07-02 09:56:42 +020010323 }
10324
Jesse Barnes30a970c2013-11-04 13:48:12 -080010325 /*
10326 * See if the config requires any additional preparation, e.g.
10327 * to adjust global state with pipes off. We need to do this
10328 * here so we can get the modeset_pipe updated config for the new
10329 * mode set on this crtc. For other crtcs we need to use the
10330 * adjusted_mode bits in the crtc directly.
10331 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010332 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010333 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010334
Ville Syrjäläc164f832013-11-05 22:34:12 +020010335 /* may have added more to prepare_pipes than we should */
10336 prepare_pipes &= ~disable_pipes;
10337 }
10338
Daniel Vetter460da9162013-03-27 00:44:51 +010010339 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10340 intel_crtc_disable(&intel_crtc->base);
10341
Daniel Vetterea9d7582012-07-10 10:42:52 +020010342 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10343 if (intel_crtc->base.enabled)
10344 dev_priv->display.crtc_disable(&intel_crtc->base);
10345 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010346
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010347 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10348 * to set it here already despite that we pass it down the callchain.
10349 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010350 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010351 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010352 /* mode_set/enable/disable functions rely on a correct pipe
10353 * config. */
10354 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010355 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010356
10357 /*
10358 * Calculate and store various constants which
10359 * are later needed by vblank and swap-completion
10360 * timestamping. They are derived from true hwmode.
10361 */
10362 drm_calc_timestamping_constants(crtc,
10363 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010364 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010365
Daniel Vetterea9d7582012-07-10 10:42:52 +020010366 /* Only after disabling all output pipelines that will be changed can we
10367 * update the the output configuration. */
10368 intel_modeset_update_state(dev, prepare_pipes);
10369
Daniel Vetter47fab732012-10-26 10:58:18 +020010370 if (dev_priv->display.modeset_global_resources)
10371 dev_priv->display.modeset_global_resources(dev);
10372
Daniel Vettera6778b32012-07-02 09:56:42 +020010373 /* Set up the DPLL and any encoders state that needs to adjust or depend
10374 * on the DPLL.
10375 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010376 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Daniel Vetter4c107942014-04-24 23:55:05 +020010377 struct drm_framebuffer *old_fb;
10378
10379 mutex_lock(&dev->struct_mutex);
10380 ret = intel_pin_and_fence_fb_obj(dev,
10381 to_intel_framebuffer(fb)->obj,
10382 NULL);
10383 if (ret != 0) {
10384 DRM_ERROR("pin & fence failed\n");
10385 mutex_unlock(&dev->struct_mutex);
10386 goto done;
10387 }
10388 old_fb = crtc->primary->fb;
10389 if (old_fb)
10390 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10391 mutex_unlock(&dev->struct_mutex);
10392
10393 crtc->primary->fb = fb;
10394 crtc->x = x;
10395 crtc->y = y;
10396
Daniel Vetter4271b752014-04-24 23:55:00 +020010397 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10398 x, y, fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010399 if (ret)
10400 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +020010401 }
10402
10403 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030010404 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10405 update_scanline_offset(intel_crtc);
10406
Daniel Vetter25c5b262012-07-08 22:08:04 +020010407 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030010408 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010409
Daniel Vettera6778b32012-07-02 09:56:42 +020010410 /* FIXME: add subpixel order */
10411done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010412 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070010413 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010414
Tim Gardner3ac18232012-12-07 07:54:26 -070010415out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010416 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070010417 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020010418 return ret;
10419}
10420
Damien Lespiaue7457a92013-08-08 22:28:59 +010010421static int intel_set_mode(struct drm_crtc *crtc,
10422 struct drm_display_mode *mode,
10423 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020010424{
10425 int ret;
10426
10427 ret = __intel_set_mode(crtc, mode, x, y, fb);
10428
10429 if (ret == 0)
10430 intel_modeset_check_state(crtc->dev);
10431
10432 return ret;
10433}
10434
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010435void intel_crtc_restore_mode(struct drm_crtc *crtc)
10436{
Matt Roperf4510a22014-04-01 15:22:40 -070010437 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010438}
10439
Daniel Vetter25c5b262012-07-08 22:08:04 +020010440#undef for_each_intel_crtc_masked
10441
Daniel Vetterd9e55602012-07-04 22:16:09 +020010442static void intel_set_config_free(struct intel_set_config *config)
10443{
10444 if (!config)
10445 return;
10446
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010447 kfree(config->save_connector_encoders);
10448 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020010449 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020010450 kfree(config);
10451}
10452
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010453static int intel_set_config_save_state(struct drm_device *dev,
10454 struct intel_set_config *config)
10455{
Ville Syrjälä76688512014-01-10 11:28:06 +020010456 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010457 struct drm_encoder *encoder;
10458 struct drm_connector *connector;
10459 int count;
10460
Ville Syrjälä76688512014-01-10 11:28:06 +020010461 config->save_crtc_enabled =
10462 kcalloc(dev->mode_config.num_crtc,
10463 sizeof(bool), GFP_KERNEL);
10464 if (!config->save_crtc_enabled)
10465 return -ENOMEM;
10466
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010467 config->save_encoder_crtcs =
10468 kcalloc(dev->mode_config.num_encoder,
10469 sizeof(struct drm_crtc *), GFP_KERNEL);
10470 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010471 return -ENOMEM;
10472
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010473 config->save_connector_encoders =
10474 kcalloc(dev->mode_config.num_connector,
10475 sizeof(struct drm_encoder *), GFP_KERNEL);
10476 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010477 return -ENOMEM;
10478
10479 /* Copy data. Note that driver private data is not affected.
10480 * Should anything bad happen only the expected state is
10481 * restored, not the drivers personal bookkeeping.
10482 */
10483 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010010484 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010485 config->save_crtc_enabled[count++] = crtc->enabled;
10486 }
10487
10488 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010489 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010490 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010491 }
10492
10493 count = 0;
10494 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010495 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010496 }
10497
10498 return 0;
10499}
10500
10501static void intel_set_config_restore_state(struct drm_device *dev,
10502 struct intel_set_config *config)
10503{
Ville Syrjälä76688512014-01-10 11:28:06 +020010504 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020010505 struct intel_encoder *encoder;
10506 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010507 int count;
10508
10509 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010510 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010511 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010512
10513 if (crtc->new_enabled)
10514 crtc->new_config = &crtc->config;
10515 else
10516 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020010517 }
10518
10519 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010520 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10521 encoder->new_crtc =
10522 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010523 }
10524
10525 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010526 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10527 connector->new_encoder =
10528 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010529 }
10530}
10531
Imre Deake3de42b2013-05-03 19:44:07 +020010532static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010010533is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020010534{
10535 int i;
10536
Chris Wilson2e57f472013-07-17 12:14:40 +010010537 if (set->num_connectors == 0)
10538 return false;
10539
10540 if (WARN_ON(set->connectors == NULL))
10541 return false;
10542
10543 for (i = 0; i < set->num_connectors; i++)
10544 if (set->connectors[i]->encoder &&
10545 set->connectors[i]->encoder->crtc == set->crtc &&
10546 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020010547 return true;
10548
10549 return false;
10550}
10551
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010552static void
10553intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10554 struct intel_set_config *config)
10555{
10556
10557 /* We should be able to check here if the fb has the same properties
10558 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010010559 if (is_crtc_connector_off(set)) {
10560 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070010561 } else if (set->crtc->primary->fb != set->fb) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010562 /* If we have no fb then treat it as a full mode set */
Matt Roperf4510a22014-04-01 15:22:40 -070010563 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030010564 struct intel_crtc *intel_crtc =
10565 to_intel_crtc(set->crtc);
10566
Jani Nikulad330a952014-01-21 11:24:25 +020010567 if (intel_crtc->active && i915.fastboot) {
Jesse Barnes319d9822013-06-26 01:38:19 +030010568 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10569 config->fb_changed = true;
10570 } else {
10571 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10572 config->mode_changed = true;
10573 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010574 } else if (set->fb == NULL) {
10575 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010010576 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070010577 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010578 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020010579 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010580 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020010581 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010582 }
10583
Daniel Vetter835c5872012-07-10 18:11:08 +020010584 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010585 config->fb_changed = true;
10586
10587 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10588 DRM_DEBUG_KMS("modes are different, full mode set\n");
10589 drm_mode_debug_printmodeline(&set->crtc->mode);
10590 drm_mode_debug_printmodeline(set->mode);
10591 config->mode_changed = true;
10592 }
Chris Wilsona1d95702013-08-13 18:48:47 +010010593
10594 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10595 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010596}
10597
Daniel Vetter2e431052012-07-04 22:42:15 +020010598static int
Daniel Vetter9a935852012-07-05 22:34:27 +020010599intel_modeset_stage_output_state(struct drm_device *dev,
10600 struct drm_mode_set *set,
10601 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020010602{
Daniel Vetter9a935852012-07-05 22:34:27 +020010603 struct intel_connector *connector;
10604 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020010605 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030010606 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020010607
Damien Lespiau9abdda72013-02-13 13:29:23 +000010608 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020010609 * of connectors. For paranoia, double-check this. */
10610 WARN_ON(!set->fb && (set->num_connectors != 0));
10611 WARN_ON(set->fb && (set->num_connectors == 0));
10612
Daniel Vetter9a935852012-07-05 22:34:27 +020010613 list_for_each_entry(connector, &dev->mode_config.connector_list,
10614 base.head) {
10615 /* Otherwise traverse passed in connector list and get encoders
10616 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020010617 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020010618 if (set->connectors[ro] == &connector->base) {
10619 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +020010620 break;
10621 }
10622 }
10623
Daniel Vetter9a935852012-07-05 22:34:27 +020010624 /* If we disable the crtc, disable all its connectors. Also, if
10625 * the connector is on the changing crtc but not on the new
10626 * connector list, disable it. */
10627 if ((!set->fb || ro == set->num_connectors) &&
10628 connector->base.encoder &&
10629 connector->base.encoder->crtc == set->crtc) {
10630 connector->new_encoder = NULL;
10631
10632 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10633 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030010634 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020010635 }
10636
10637
10638 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020010639 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010640 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020010641 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010642 }
10643 /* connector->new_encoder is now updated for all connectors. */
10644
10645 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020010646 list_for_each_entry(connector, &dev->mode_config.connector_list,
10647 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010648 struct drm_crtc *new_crtc;
10649
Daniel Vetter9a935852012-07-05 22:34:27 +020010650 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020010651 continue;
10652
Daniel Vetter9a935852012-07-05 22:34:27 +020010653 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020010654
10655 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020010656 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020010657 new_crtc = set->crtc;
10658 }
10659
10660 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010010661 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10662 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010663 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020010664 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010665 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10666
10667 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10668 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030010669 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020010670 new_crtc->base.id);
10671 }
10672
10673 /* Check for any encoders that needs to be disabled. */
10674 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10675 base.head) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010676 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020010677 list_for_each_entry(connector,
10678 &dev->mode_config.connector_list,
10679 base.head) {
10680 if (connector->new_encoder == encoder) {
10681 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010682 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020010683 }
10684 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020010685
10686 if (num_connectors == 0)
10687 encoder->new_crtc = NULL;
10688 else if (num_connectors > 1)
10689 return -EINVAL;
10690
Daniel Vetter9a935852012-07-05 22:34:27 +020010691 /* Only now check for crtc changes so we don't miss encoders
10692 * that will be disabled. */
10693 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020010694 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010695 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020010696 }
10697 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010698 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +020010699
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010700 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010701 crtc->new_enabled = false;
10702
10703 list_for_each_entry(encoder,
10704 &dev->mode_config.encoder_list,
10705 base.head) {
10706 if (encoder->new_crtc == crtc) {
10707 crtc->new_enabled = true;
10708 break;
10709 }
10710 }
10711
10712 if (crtc->new_enabled != crtc->base.enabled) {
10713 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10714 crtc->new_enabled ? "en" : "dis");
10715 config->mode_changed = true;
10716 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010717
10718 if (crtc->new_enabled)
10719 crtc->new_config = &crtc->config;
10720 else
10721 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020010722 }
10723
Daniel Vetter2e431052012-07-04 22:42:15 +020010724 return 0;
10725}
10726
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010727static void disable_crtc_nofb(struct intel_crtc *crtc)
10728{
10729 struct drm_device *dev = crtc->base.dev;
10730 struct intel_encoder *encoder;
10731 struct intel_connector *connector;
10732
10733 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10734 pipe_name(crtc->pipe));
10735
10736 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10737 if (connector->new_encoder &&
10738 connector->new_encoder->new_crtc == crtc)
10739 connector->new_encoder = NULL;
10740 }
10741
10742 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10743 if (encoder->new_crtc == crtc)
10744 encoder->new_crtc = NULL;
10745 }
10746
10747 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010748 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010749}
10750
Daniel Vetter2e431052012-07-04 22:42:15 +020010751static int intel_crtc_set_config(struct drm_mode_set *set)
10752{
10753 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020010754 struct drm_mode_set save_set;
10755 struct intel_set_config *config;
10756 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020010757
Daniel Vetter8d3e3752012-07-05 16:09:09 +020010758 BUG_ON(!set);
10759 BUG_ON(!set->crtc);
10760 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020010761
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010010762 /* Enforce sane interface api - has been abused by the fb helper. */
10763 BUG_ON(!set->mode && set->fb);
10764 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020010765
Daniel Vetter2e431052012-07-04 22:42:15 +020010766 if (set->fb) {
10767 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10768 set->crtc->base.id, set->fb->base.id,
10769 (int)set->num_connectors, set->x, set->y);
10770 } else {
10771 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020010772 }
10773
10774 dev = set->crtc->dev;
10775
10776 ret = -ENOMEM;
10777 config = kzalloc(sizeof(*config), GFP_KERNEL);
10778 if (!config)
10779 goto out_config;
10780
10781 ret = intel_set_config_save_state(dev, config);
10782 if (ret)
10783 goto out_config;
10784
10785 save_set.crtc = set->crtc;
10786 save_set.mode = &set->crtc->mode;
10787 save_set.x = set->crtc->x;
10788 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070010789 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020010790
10791 /* Compute whether we need a full modeset, only an fb base update or no
10792 * change at all. In the future we might also check whether only the
10793 * mode changed, e.g. for LVDS where we only change the panel fitter in
10794 * such cases. */
10795 intel_set_config_compute_mode_changes(set, config);
10796
Daniel Vetter9a935852012-07-05 22:34:27 +020010797 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020010798 if (ret)
10799 goto fail;
10800
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010801 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010802 ret = intel_set_mode(set->crtc, set->mode,
10803 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010804 } else if (config->fb_changed) {
Ville Syrjälä4878cae2013-02-18 19:08:48 +020010805 intel_crtc_wait_for_pending_flips(set->crtc);
10806
Daniel Vetter4f660f42012-07-02 09:47:37 +020010807 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020010808 set->x, set->y, set->fb);
Jesse Barnes7ca51a32014-01-07 13:50:49 -080010809 /*
10810 * In the fastboot case this may be our only check of the
10811 * state after boot. It would be better to only do it on
10812 * the first update, but we don't have a nice way of doing that
10813 * (and really, set_config isn't used much for high freq page
10814 * flipping, so increasing its cost here shouldn't be a big
10815 * deal).
10816 */
Jani Nikulad330a952014-01-21 11:24:25 +020010817 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080010818 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020010819 }
10820
Chris Wilson2d05eae2013-05-03 17:36:25 +010010821 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020010822 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10823 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020010824fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010010825 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020010826
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020010827 /*
10828 * HACK: if the pipe was on, but we didn't have a framebuffer,
10829 * force the pipe off to avoid oopsing in the modeset code
10830 * due to fb==NULL. This should only happen during boot since
10831 * we don't yet reconstruct the FB from the hardware state.
10832 */
10833 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10834 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10835
Chris Wilson2d05eae2013-05-03 17:36:25 +010010836 /* Try to restore the config */
10837 if (config->mode_changed &&
10838 intel_set_mode(save_set.crtc, save_set.mode,
10839 save_set.x, save_set.y, save_set.fb))
10840 DRM_ERROR("failed to restore config after modeset failure\n");
10841 }
Daniel Vetter50f56112012-07-02 09:35:43 +020010842
Daniel Vetterd9e55602012-07-04 22:16:09 +020010843out_config:
10844 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020010845 return ret;
10846}
10847
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010848static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010849 .cursor_set = intel_crtc_cursor_set,
10850 .cursor_move = intel_crtc_cursor_move,
10851 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020010852 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010853 .destroy = intel_crtc_destroy,
10854 .page_flip = intel_crtc_page_flip,
10855};
10856
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010857static void intel_cpu_pll_init(struct drm_device *dev)
10858{
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010859 if (HAS_DDI(dev))
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010860 intel_ddi_pll_init(dev);
10861}
10862
Daniel Vetter53589012013-06-05 13:34:16 +020010863static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10864 struct intel_shared_dpll *pll,
10865 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010866{
Daniel Vetter53589012013-06-05 13:34:16 +020010867 uint32_t val;
10868
10869 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020010870 hw_state->dpll = val;
10871 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10872 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020010873
10874 return val & DPLL_VCO_ENABLE;
10875}
10876
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010877static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10878 struct intel_shared_dpll *pll)
10879{
10880 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10881 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10882}
10883
Daniel Vettere7b903d2013-06-05 13:34:14 +020010884static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10885 struct intel_shared_dpll *pll)
10886{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010887 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020010888 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020010889
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010890 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10891
10892 /* Wait for the clocks to stabilize. */
10893 POSTING_READ(PCH_DPLL(pll->id));
10894 udelay(150);
10895
10896 /* The pixel multiplier can only be updated once the
10897 * DPLL is enabled and the clocks are stable.
10898 *
10899 * So write it again.
10900 */
10901 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10902 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020010903 udelay(200);
10904}
10905
10906static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10907 struct intel_shared_dpll *pll)
10908{
10909 struct drm_device *dev = dev_priv->dev;
10910 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020010911
10912 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010913 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020010914 if (intel_crtc_to_shared_dpll(crtc) == pll)
10915 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10916 }
10917
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010918 I915_WRITE(PCH_DPLL(pll->id), 0);
10919 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020010920 udelay(200);
10921}
10922
Daniel Vetter46edb022013-06-05 13:34:12 +020010923static char *ibx_pch_dpll_names[] = {
10924 "PCH DPLL A",
10925 "PCH DPLL B",
10926};
10927
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010928static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010929{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010930 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010931 int i;
10932
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010933 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010934
Daniel Vettere72f9fb2013-06-05 13:34:06 +020010935 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020010936 dev_priv->shared_dplls[i].id = i;
10937 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010938 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020010939 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10940 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020010941 dev_priv->shared_dplls[i].get_hw_state =
10942 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010943 }
10944}
10945
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010946static void intel_shared_dpll_init(struct drm_device *dev)
10947{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010948 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010949
10950 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10951 ibx_pch_dpll_init(dev);
10952 else
10953 dev_priv->num_shared_dpll = 0;
10954
10955 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010956}
10957
Hannes Ederb358d0a2008-12-18 21:18:47 +010010958static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080010959{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010960 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080010961 struct intel_crtc *intel_crtc;
10962 int i;
10963
Daniel Vetter955382f2013-09-19 14:05:45 +020010964 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080010965 if (intel_crtc == NULL)
10966 return;
10967
10968 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10969
10970 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080010971 for (i = 0; i < 256; i++) {
10972 intel_crtc->lut_r[i] = i;
10973 intel_crtc->lut_g[i] = i;
10974 intel_crtc->lut_b[i] = i;
10975 }
10976
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020010977 /*
10978 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10979 * is hooked to plane B. Hence we want plane A feeding pipe B.
10980 */
Jesse Barnes80824002009-09-10 15:28:06 -070010981 intel_crtc->pipe = pipe;
10982 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010010983 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080010984 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010010985 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070010986 }
10987
Chris Wilson4b0e3332014-05-30 16:35:26 +030010988 intel_crtc->cursor_base = ~0;
10989 intel_crtc->cursor_cntl = ~0;
10990
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030010991 init_waitqueue_head(&intel_crtc->vbl_wait);
10992
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080010993 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10994 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10995 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10996 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10997
Jesse Barnes79e53942008-11-07 14:24:08 -080010998 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020010999
11000 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -080011001}
11002
Jesse Barnes752aa882013-10-31 18:55:49 +020011003enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11004{
11005 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011006 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020011007
Rob Clark51fd3712013-11-19 12:10:12 -050011008 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020011009
11010 if (!encoder)
11011 return INVALID_PIPE;
11012
11013 return to_intel_crtc(encoder->crtc)->pipe;
11014}
11015
Carl Worth08d7b3d2009-04-29 14:43:54 -070011016int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000011017 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070011018{
Carl Worth08d7b3d2009-04-29 14:43:54 -070011019 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +020011020 struct drm_mode_object *drmmode_obj;
11021 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011022
Daniel Vetter1cff8f62012-04-24 09:55:08 +020011023 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11024 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011025
Daniel Vetterc05422d2009-08-11 16:05:30 +020011026 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11027 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -070011028
Daniel Vetterc05422d2009-08-11 16:05:30 +020011029 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070011030 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030011031 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011032 }
11033
Daniel Vetterc05422d2009-08-11 16:05:30 +020011034 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11035 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011036
Daniel Vetterc05422d2009-08-11 16:05:30 +020011037 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011038}
11039
Daniel Vetter66a92782012-07-12 20:08:18 +020011040static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080011041{
Daniel Vetter66a92782012-07-12 20:08:18 +020011042 struct drm_device *dev = encoder->base.dev;
11043 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080011044 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080011045 int entry = 0;
11046
Daniel Vetter66a92782012-07-12 20:08:18 +020011047 list_for_each_entry(source_encoder,
11048 &dev->mode_config.encoder_list, base.head) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011049 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020011050 index_mask |= (1 << entry);
11051
Jesse Barnes79e53942008-11-07 14:24:08 -080011052 entry++;
11053 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010011054
Jesse Barnes79e53942008-11-07 14:24:08 -080011055 return index_mask;
11056}
11057
Chris Wilson4d302442010-12-14 19:21:29 +000011058static bool has_edp_a(struct drm_device *dev)
11059{
11060 struct drm_i915_private *dev_priv = dev->dev_private;
11061
11062 if (!IS_MOBILE(dev))
11063 return false;
11064
11065 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11066 return false;
11067
Damien Lespiaue3589902014-02-07 19:12:50 +000011068 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000011069 return false;
11070
11071 return true;
11072}
11073
Damien Lespiauba0fbca2014-01-08 14:18:23 +000011074const char *intel_output_name(int output)
11075{
11076 static const char *names[] = {
11077 [INTEL_OUTPUT_UNUSED] = "Unused",
11078 [INTEL_OUTPUT_ANALOG] = "Analog",
11079 [INTEL_OUTPUT_DVO] = "DVO",
11080 [INTEL_OUTPUT_SDVO] = "SDVO",
11081 [INTEL_OUTPUT_LVDS] = "LVDS",
11082 [INTEL_OUTPUT_TVOUT] = "TV",
11083 [INTEL_OUTPUT_HDMI] = "HDMI",
11084 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11085 [INTEL_OUTPUT_EDP] = "eDP",
11086 [INTEL_OUTPUT_DSI] = "DSI",
11087 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11088 };
11089
11090 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11091 return "Invalid";
11092
11093 return names[output];
11094}
11095
Jesse Barnes79e53942008-11-07 14:24:08 -080011096static void intel_setup_outputs(struct drm_device *dev)
11097{
Eric Anholt725e30a2009-01-22 13:01:02 -080011098 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010011099 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011100 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080011101
Daniel Vetterc9093352013-06-06 22:22:47 +020011102 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011103
Jesse Barnes27da3bd2014-04-04 16:12:07 -070011104 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
Paulo Zanoni79935fc2012-11-20 13:27:40 -020011105 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011106
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011107 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030011108 int found;
11109
11110 /* Haswell uses DDI functions to detect digital outputs */
11111 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11112 /* DDI A only supports eDP */
11113 if (found)
11114 intel_ddi_init(dev, PORT_A);
11115
11116 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11117 * register */
11118 found = I915_READ(SFUSE_STRAP);
11119
11120 if (found & SFUSE_STRAP_DDIB_DETECTED)
11121 intel_ddi_init(dev, PORT_B);
11122 if (found & SFUSE_STRAP_DDIC_DETECTED)
11123 intel_ddi_init(dev, PORT_C);
11124 if (found & SFUSE_STRAP_DDID_DETECTED)
11125 intel_ddi_init(dev, PORT_D);
11126 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011127 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020011128 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020011129
11130 if (has_edp_a(dev))
11131 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040011132
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011133 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080011134 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010011135 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011136 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011137 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011138 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011139 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011140 }
11141
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011142 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011143 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011144
Paulo Zanonidc0fa712013-02-19 16:21:46 -030011145 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030011146 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080011147
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011148 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011149 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080011150
Daniel Vetter270b3042012-10-27 15:52:05 +020011151 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011152 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070011153 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030011154 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11155 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11156 PORT_B);
11157 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11158 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11159 }
11160
Jesse Barnes6f6005a2013-08-09 09:34:35 -070011161 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11162 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11163 PORT_C);
11164 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020011165 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Jesse Barnes6f6005a2013-08-09 09:34:35 -070011166 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053011167
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030011168 if (IS_CHERRYVIEW(dev)) {
11169 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11170 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11171 PORT_D);
11172 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11173 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11174 }
11175 }
11176
Jani Nikula3cfca972013-08-27 15:12:26 +030011177 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080011178 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080011179 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080011180
Paulo Zanonie2debe92013-02-18 19:00:27 -030011181 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011182 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011183 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011184 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11185 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011186 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011187 }
Ma Ling27185ae2009-08-24 13:50:23 +080011188
Imre Deake7281ea2013-05-08 13:14:08 +030011189 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011190 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080011191 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040011192
11193 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040011194
Paulo Zanonie2debe92013-02-18 19:00:27 -030011195 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011196 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011197 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011198 }
Ma Ling27185ae2009-08-24 13:50:23 +080011199
Paulo Zanonie2debe92013-02-18 19:00:27 -030011200 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080011201
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011202 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11203 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030011204 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011205 }
Imre Deake7281ea2013-05-08 13:14:08 +030011206 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011207 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080011208 }
Ma Ling27185ae2009-08-24 13:50:23 +080011209
Jesse Barnesb01f2c32009-12-11 11:07:17 -080011210 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030011211 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030011212 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070011213 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080011214 intel_dvo_init(dev);
11215
Zhenyu Wang103a1962009-11-27 11:44:36 +080011216 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080011217 intel_tv_init(dev);
11218
Chris Wilson4ef69c72010-09-09 15:14:28 +010011219 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11220 encoder->base.possible_crtcs = encoder->crtc_mask;
11221 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020011222 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080011223 }
Chris Wilson47356eb2011-01-11 17:06:04 +000011224
Paulo Zanonidde86e22012-12-01 12:04:25 -020011225 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020011226
11227 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011228}
11229
11230static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11231{
11232 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080011233
Daniel Vetteref2d6332014-02-10 18:00:38 +010011234 drm_framebuffer_cleanup(fb);
11235 WARN_ON(!intel_fb->obj->framebuffer_references--);
11236 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080011237 kfree(intel_fb);
11238}
11239
11240static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000011241 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080011242 unsigned int *handle)
11243{
11244 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000011245 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080011246
Chris Wilson05394f32010-11-08 19:18:58 +000011247 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080011248}
11249
11250static const struct drm_framebuffer_funcs intel_fb_funcs = {
11251 .destroy = intel_user_framebuffer_destroy,
11252 .create_handle = intel_user_framebuffer_create_handle,
11253};
11254
Daniel Vetterb5ea6422014-03-02 21:18:00 +010011255static int intel_framebuffer_init(struct drm_device *dev,
11256 struct intel_framebuffer *intel_fb,
11257 struct drm_mode_fb_cmd2 *mode_cmd,
11258 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080011259{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080011260 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010011261 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080011262 int ret;
11263
Daniel Vetterdd4916c2013-10-09 21:23:51 +020011264 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11265
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011266 if (obj->tiling_mode == I915_TILING_Y) {
11267 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010011268 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011269 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011270
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011271 if (mode_cmd->pitches[0] & 63) {
11272 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11273 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010011274 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011275 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011276
Chris Wilsona35cdaa2013-06-25 17:26:45 +010011277 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11278 pitch_limit = 32*1024;
11279 } else if (INTEL_INFO(dev)->gen >= 4) {
11280 if (obj->tiling_mode)
11281 pitch_limit = 16*1024;
11282 else
11283 pitch_limit = 32*1024;
11284 } else if (INTEL_INFO(dev)->gen >= 3) {
11285 if (obj->tiling_mode)
11286 pitch_limit = 8*1024;
11287 else
11288 pitch_limit = 16*1024;
11289 } else
11290 /* XXX DSPC is limited to 4k tiled */
11291 pitch_limit = 8*1024;
11292
11293 if (mode_cmd->pitches[0] > pitch_limit) {
11294 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11295 obj->tiling_mode ? "tiled" : "linear",
11296 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011297 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011298 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011299
11300 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011301 mode_cmd->pitches[0] != obj->stride) {
11302 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11303 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011304 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011305 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020011306
Ville Syrjälä57779d02012-10-31 17:50:14 +020011307 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011308 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020011309 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020011310 case DRM_FORMAT_RGB565:
11311 case DRM_FORMAT_XRGB8888:
11312 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020011313 break;
11314 case DRM_FORMAT_XRGB1555:
11315 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011316 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011317 DRM_DEBUG("unsupported pixel format: %s\n",
11318 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011319 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011320 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020011321 break;
11322 case DRM_FORMAT_XBGR8888:
11323 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020011324 case DRM_FORMAT_XRGB2101010:
11325 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020011326 case DRM_FORMAT_XBGR2101010:
11327 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011328 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011329 DRM_DEBUG("unsupported pixel format: %s\n",
11330 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011331 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011332 }
Jesse Barnesb5626742011-06-24 12:19:27 -070011333 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020011334 case DRM_FORMAT_YUYV:
11335 case DRM_FORMAT_UYVY:
11336 case DRM_FORMAT_YVYU:
11337 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011338 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011339 DRM_DEBUG("unsupported pixel format: %s\n",
11340 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020011341 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000011342 }
Chris Wilson57cd6502010-08-08 12:34:44 +010011343 break;
11344 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000011345 DRM_DEBUG("unsupported pixel format: %s\n",
11346 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010011347 return -EINVAL;
11348 }
11349
Ville Syrjälä90f9a332012-10-31 17:50:19 +020011350 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11351 if (mode_cmd->offsets[0] != 0)
11352 return -EINVAL;
11353
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080011354 aligned_height = intel_align_height(dev, mode_cmd->height,
11355 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020011356 /* FIXME drm helper for size checks (especially planar formats)? */
11357 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11358 return -EINVAL;
11359
Daniel Vetterc7d73f62012-12-13 23:38:38 +010011360 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11361 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020011362 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010011363
Jesse Barnes79e53942008-11-07 14:24:08 -080011364 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11365 if (ret) {
11366 DRM_ERROR("framebuffer init failed %d\n", ret);
11367 return ret;
11368 }
11369
Jesse Barnes79e53942008-11-07 14:24:08 -080011370 return 0;
11371}
11372
Jesse Barnes79e53942008-11-07 14:24:08 -080011373static struct drm_framebuffer *
11374intel_user_framebuffer_create(struct drm_device *dev,
11375 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011376 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080011377{
Chris Wilson05394f32010-11-08 19:18:58 +000011378 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080011379
Jesse Barnes308e5bc2011-11-14 14:51:28 -080011380 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11381 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000011382 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010011383 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080011384
Chris Wilsond2dff872011-04-19 08:36:26 +010011385 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080011386}
11387
Daniel Vetter4520f532013-10-09 09:18:51 +020011388#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020011389static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020011390{
11391}
11392#endif
11393
Jesse Barnes79e53942008-11-07 14:24:08 -080011394static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080011395 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020011396 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080011397};
11398
Jesse Barnese70236a2009-09-21 10:42:27 -070011399/* Set up chip specific display functions */
11400static void intel_init_display(struct drm_device *dev)
11401{
11402 struct drm_i915_private *dev_priv = dev->dev_private;
11403
Daniel Vetteree9300b2013-06-03 22:40:22 +020011404 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11405 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030011406 else if (IS_CHERRYVIEW(dev))
11407 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020011408 else if (IS_VALLEYVIEW(dev))
11409 dev_priv->display.find_dpll = vlv_find_best_dpll;
11410 else if (IS_PINEVIEW(dev))
11411 dev_priv->display.find_dpll = pnv_find_best_dpll;
11412 else
11413 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11414
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011415 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011416 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080011417 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030011418 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020011419 dev_priv->display.crtc_enable = haswell_crtc_enable;
11420 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -030011421 dev_priv->display.off = haswell_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011422 dev_priv->display.update_primary_plane =
11423 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030011424 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011425 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080011426 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070011427 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020011428 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11429 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011430 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011431 dev_priv->display.update_primary_plane =
11432 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070011433 } else if (IS_VALLEYVIEW(dev)) {
11434 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080011435 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Jesse Barnes89b667f2013-04-18 14:51:36 -070011436 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11437 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11438 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11439 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011440 dev_priv->display.update_primary_plane =
11441 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070011442 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011443 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080011444 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070011445 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020011446 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11447 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011448 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070011449 dev_priv->display.update_primary_plane =
11450 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070011451 }
Jesse Barnese70236a2009-09-21 10:42:27 -070011452
Jesse Barnese70236a2009-09-21 10:42:27 -070011453 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070011454 if (IS_VALLEYVIEW(dev))
11455 dev_priv->display.get_display_clock_speed =
11456 valleyview_get_display_clock_speed;
11457 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070011458 dev_priv->display.get_display_clock_speed =
11459 i945_get_display_clock_speed;
11460 else if (IS_I915G(dev))
11461 dev_priv->display.get_display_clock_speed =
11462 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020011463 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070011464 dev_priv->display.get_display_clock_speed =
11465 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020011466 else if (IS_PINEVIEW(dev))
11467 dev_priv->display.get_display_clock_speed =
11468 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070011469 else if (IS_I915GM(dev))
11470 dev_priv->display.get_display_clock_speed =
11471 i915gm_get_display_clock_speed;
11472 else if (IS_I865G(dev))
11473 dev_priv->display.get_display_clock_speed =
11474 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020011475 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070011476 dev_priv->display.get_display_clock_speed =
11477 i855_get_display_clock_speed;
11478 else /* 852, 830 */
11479 dev_priv->display.get_display_clock_speed =
11480 i830_get_display_clock_speed;
11481
Zhenyu Wang7f8a8562010-04-01 13:07:53 +080011482 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +010011483 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070011484 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011485 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +080011486 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070011487 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011488 dev_priv->display.write_eld = ironlake_write_eld;
Paulo Zanoni9a952a02014-03-07 20:12:34 -030011489 dev_priv->display.modeset_global_resources =
11490 snb_modeset_global_resources;
Jesse Barnes357555c2011-04-28 15:09:55 -070011491 } else if (IS_IVYBRIDGE(dev)) {
11492 /* FIXME: detect B0+ stepping and use auto training */
11493 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080011494 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +020011495 dev_priv->display.modeset_global_resources =
11496 ivb_modeset_global_resources;
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070011497 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -030011498 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +080011499 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -020011500 dev_priv->display.modeset_global_resources =
11501 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -020011502 }
Jesse Barnes6067aae2011-04-28 15:04:31 -070011503 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080011504 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnes30a970c2013-11-04 13:48:12 -080011505 } else if (IS_VALLEYVIEW(dev)) {
11506 dev_priv->display.modeset_global_resources =
11507 valleyview_modeset_global_resources;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -040011508 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -070011509 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011510
11511 /* Default just returns -ENODEV to indicate unsupported */
11512 dev_priv->display.queue_flip = intel_default_queue_flip;
11513
11514 switch (INTEL_INFO(dev)->gen) {
11515 case 2:
11516 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11517 break;
11518
11519 case 3:
11520 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11521 break;
11522
11523 case 4:
11524 case 5:
11525 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11526 break;
11527
11528 case 6:
11529 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11530 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011531 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070011532 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011533 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11534 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011535 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020011536
11537 intel_panel_init_backlight_funcs(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070011538}
11539
Jesse Barnesb690e962010-07-19 13:53:12 -070011540/*
11541 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11542 * resume, or other times. This quirk makes sure that's the case for
11543 * affected systems.
11544 */
Akshay Joshi0206e352011-08-16 15:34:10 -040011545static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070011546{
11547 struct drm_i915_private *dev_priv = dev->dev_private;
11548
11549 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011550 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070011551}
11552
Keith Packard435793d2011-07-12 14:56:22 -070011553/*
11554 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11555 */
11556static void quirk_ssc_force_disable(struct drm_device *dev)
11557{
11558 struct drm_i915_private *dev_priv = dev->dev_private;
11559 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011560 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070011561}
11562
Carsten Emde4dca20e2012-03-15 15:56:26 +010011563/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010011564 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11565 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010011566 */
11567static void quirk_invert_brightness(struct drm_device *dev)
11568{
11569 struct drm_i915_private *dev_priv = dev->dev_private;
11570 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020011571 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070011572}
11573
11574struct intel_quirk {
11575 int device;
11576 int subsystem_vendor;
11577 int subsystem_device;
11578 void (*hook)(struct drm_device *dev);
11579};
11580
Egbert Eich5f85f1762012-10-14 15:46:38 +020011581/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11582struct intel_dmi_quirk {
11583 void (*hook)(struct drm_device *dev);
11584 const struct dmi_system_id (*dmi_id_list)[];
11585};
11586
11587static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11588{
11589 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11590 return 1;
11591}
11592
11593static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11594 {
11595 .dmi_id_list = &(const struct dmi_system_id[]) {
11596 {
11597 .callback = intel_dmi_reverse_brightness,
11598 .ident = "NCR Corporation",
11599 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11600 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11601 },
11602 },
11603 { } /* terminating entry */
11604 },
11605 .hook = quirk_invert_brightness,
11606 },
11607};
11608
Ben Widawskyc43b5632012-04-16 14:07:40 -070011609static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070011610 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040011611 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070011612
Jesse Barnesb690e962010-07-19 13:53:12 -070011613 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11614 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11615
Jesse Barnesb690e962010-07-19 13:53:12 -070011616 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11617 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11618
Keith Packard435793d2011-07-12 14:56:22 -070011619 /* Lenovo U160 cannot use SSC on LVDS */
11620 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020011621
11622 /* Sony Vaio Y cannot use SSC on LVDS */
11623 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010011624
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010011625 /* Acer Aspire 5734Z must invert backlight brightness */
11626 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11627
11628 /* Acer/eMachines G725 */
11629 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11630
11631 /* Acer/eMachines e725 */
11632 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11633
11634 /* Acer/Packard Bell NCL20 */
11635 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11636
11637 /* Acer Aspire 4736Z */
11638 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020011639
11640 /* Acer Aspire 5336 */
11641 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -070011642};
11643
11644static void intel_init_quirks(struct drm_device *dev)
11645{
11646 struct pci_dev *d = dev->pdev;
11647 int i;
11648
11649 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11650 struct intel_quirk *q = &intel_quirks[i];
11651
11652 if (d->device == q->device &&
11653 (d->subsystem_vendor == q->subsystem_vendor ||
11654 q->subsystem_vendor == PCI_ANY_ID) &&
11655 (d->subsystem_device == q->subsystem_device ||
11656 q->subsystem_device == PCI_ANY_ID))
11657 q->hook(dev);
11658 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020011659 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11660 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11661 intel_dmi_quirks[i].hook(dev);
11662 }
Jesse Barnesb690e962010-07-19 13:53:12 -070011663}
11664
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011665/* Disable the VGA plane that we never use */
11666static void i915_disable_vga(struct drm_device *dev)
11667{
11668 struct drm_i915_private *dev_priv = dev->dev_private;
11669 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020011670 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011671
Ville Syrjälä2b37c612014-01-22 21:32:38 +020011672 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011673 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070011674 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011675 sr1 = inb(VGA_SR_DATA);
11676 outb(sr1 | 1<<5, VGA_SR_DATA);
11677 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11678 udelay(300);
11679
11680 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11681 POSTING_READ(vga_reg);
11682}
11683
Daniel Vetterf8175862012-04-10 15:50:11 +020011684void intel_modeset_init_hw(struct drm_device *dev)
11685{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030011686 intel_prepare_ddi(dev);
11687
Daniel Vetterf8175862012-04-10 15:50:11 +020011688 intel_init_clock_gating(dev);
11689
Jesse Barnes5382f5f352013-12-16 16:34:24 -080011690 intel_reset_dpio(dev);
Jesse Barnes40e9cf62013-10-03 11:35:46 -070011691
Daniel Vetter8090c6b2012-06-24 16:42:32 +020011692 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020011693}
11694
Imre Deak7d708ee2013-04-17 14:04:50 +030011695void intel_modeset_suspend_hw(struct drm_device *dev)
11696{
11697 intel_suspend_hw(dev);
11698}
11699
Jesse Barnes79e53942008-11-07 14:24:08 -080011700void intel_modeset_init(struct drm_device *dev)
11701{
Jesse Barnes652c3932009-08-17 13:31:43 -070011702 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000011703 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000011704 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080011705 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080011706
11707 drm_mode_config_init(dev);
11708
11709 dev->mode_config.min_width = 0;
11710 dev->mode_config.min_height = 0;
11711
Dave Airlie019d96c2011-09-29 16:20:42 +010011712 dev->mode_config.preferred_depth = 24;
11713 dev->mode_config.prefer_shadow = 1;
11714
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020011715 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080011716
Jesse Barnesb690e962010-07-19 13:53:12 -070011717 intel_init_quirks(dev);
11718
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030011719 intel_init_pm(dev);
11720
Ben Widawskye3c74752013-04-05 13:12:39 -070011721 if (INTEL_INFO(dev)->num_pipes == 0)
11722 return;
11723
Jesse Barnese70236a2009-09-21 10:42:27 -070011724 intel_init_display(dev);
11725
Chris Wilsona6c45cf2010-09-17 00:32:17 +010011726 if (IS_GEN2(dev)) {
11727 dev->mode_config.max_width = 2048;
11728 dev->mode_config.max_height = 2048;
11729 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070011730 dev->mode_config.max_width = 4096;
11731 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080011732 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010011733 dev->mode_config.max_width = 8192;
11734 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080011735 }
Damien Lespiau068be562014-03-28 14:17:49 +000011736
11737 if (IS_GEN2(dev)) {
11738 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11739 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11740 } else {
11741 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11742 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11743 }
11744
Ben Widawsky5d4545a2013-01-17 12:45:15 -080011745 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080011746
Zhao Yakui28c97732009-10-09 11:39:41 +080011747 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011748 INTEL_INFO(dev)->num_pipes,
11749 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080011750
Damien Lespiau8cc87b72014-03-03 17:31:44 +000011751 for_each_pipe(pipe) {
11752 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000011753 for_each_sprite(pipe, sprite) {
11754 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070011755 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030011756 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000011757 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070011758 }
Jesse Barnes79e53942008-11-07 14:24:08 -080011759 }
11760
Jesse Barnesf42bb702013-12-16 16:34:23 -080011761 intel_init_dpio(dev);
Jesse Barnes5382f5f352013-12-16 16:34:24 -080011762 intel_reset_dpio(dev);
Jesse Barnesf42bb702013-12-16 16:34:23 -080011763
Paulo Zanoni79f689a2012-10-05 12:05:52 -030011764 intel_cpu_pll_init(dev);
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011765 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011766
Jesse Barnes9cce37f2010-08-13 15:11:26 -070011767 /* Just disable it once at startup */
11768 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011769 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000011770
11771 /* Just in case the BIOS is doing something questionable. */
11772 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080011773
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011774 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080011775 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011776 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080011777
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011778 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080011779 if (!crtc->active)
11780 continue;
11781
Jesse Barnes46f297f2014-03-07 08:57:48 -080011782 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080011783 * Note that reserving the BIOS fb up front prevents us
11784 * from stuffing other stolen allocations like the ring
11785 * on top. This prevents some ugliness at boot time, and
11786 * can even allow for smooth boot transitions if the BIOS
11787 * fb is large enough for the active pipe configuration.
11788 */
11789 if (dev_priv->display.get_plane_config) {
11790 dev_priv->display.get_plane_config(crtc,
11791 &crtc->plane_config);
11792 /*
11793 * If the fb is shared between multiple heads, we'll
11794 * just get the first one.
11795 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080011796 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080011797 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080011798 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010011799}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080011800
Daniel Vetter7fad7982012-07-04 17:51:47 +020011801static void intel_enable_pipe_a(struct drm_device *dev)
11802{
11803 struct intel_connector *connector;
11804 struct drm_connector *crt = NULL;
11805 struct intel_load_detect_pipe load_detect_temp;
Rob Clark51fd3712013-11-19 12:10:12 -050011806 struct drm_modeset_acquire_ctx ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020011807
11808 /* We can't just switch on the pipe A, we need to set things up with a
11809 * proper mode and output configuration. As a gross hack, enable pipe A
11810 * by enabling the load detect pipe once. */
11811 list_for_each_entry(connector,
11812 &dev->mode_config.connector_list,
11813 base.head) {
11814 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11815 crt = &connector->base;
11816 break;
11817 }
11818 }
11819
11820 if (!crt)
11821 return;
11822
Rob Clark51fd3712013-11-19 12:10:12 -050011823 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
11824 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
Daniel Vetter7fad7982012-07-04 17:51:47 +020011825
11826
11827}
11828
Daniel Vetterfa555832012-10-10 23:14:00 +020011829static bool
11830intel_check_plane_mapping(struct intel_crtc *crtc)
11831{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011832 struct drm_device *dev = crtc->base.dev;
11833 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020011834 u32 reg, val;
11835
Ben Widawsky7eb552a2013-03-13 14:05:41 -070011836 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020011837 return true;
11838
11839 reg = DSPCNTR(!crtc->plane);
11840 val = I915_READ(reg);
11841
11842 if ((val & DISPLAY_PLANE_ENABLE) &&
11843 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11844 return false;
11845
11846 return true;
11847}
11848
Daniel Vetter24929352012-07-02 20:28:59 +020011849static void intel_sanitize_crtc(struct intel_crtc *crtc)
11850{
11851 struct drm_device *dev = crtc->base.dev;
11852 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020011853 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020011854
Daniel Vetter24929352012-07-02 20:28:59 +020011855 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020011856 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020011857 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11858
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030011859 /* restore vblank interrupts to correct state */
11860 if (crtc->active)
11861 drm_vblank_on(dev, crtc->pipe);
11862 else
11863 drm_vblank_off(dev, crtc->pipe);
11864
Daniel Vetter24929352012-07-02 20:28:59 +020011865 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020011866 * disable the crtc (and hence change the state) if it is wrong. Note
11867 * that gen4+ has a fixed plane -> pipe mapping. */
11868 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020011869 struct intel_connector *connector;
11870 bool plane;
11871
Daniel Vetter24929352012-07-02 20:28:59 +020011872 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11873 crtc->base.base.id);
11874
11875 /* Pipe has the wrong plane attached and the plane is active.
11876 * Temporarily change the plane mapping and disable everything
11877 * ... */
11878 plane = crtc->plane;
11879 crtc->plane = !plane;
11880 dev_priv->display.crtc_disable(&crtc->base);
11881 crtc->plane = plane;
11882
11883 /* ... and break all links. */
11884 list_for_each_entry(connector, &dev->mode_config.connector_list,
11885 base.head) {
11886 if (connector->encoder->base.crtc != &crtc->base)
11887 continue;
11888
Egbert Eich7f1950f2014-04-25 10:56:22 +020011889 connector->base.dpms = DRM_MODE_DPMS_OFF;
11890 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020011891 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020011892 /* multiple connectors may have the same encoder:
11893 * handle them and break crtc link separately */
11894 list_for_each_entry(connector, &dev->mode_config.connector_list,
11895 base.head)
11896 if (connector->encoder->base.crtc == &crtc->base) {
11897 connector->encoder->base.crtc = NULL;
11898 connector->encoder->connectors_active = false;
11899 }
Daniel Vetter24929352012-07-02 20:28:59 +020011900
11901 WARN_ON(crtc->active);
11902 crtc->base.enabled = false;
11903 }
Daniel Vetter24929352012-07-02 20:28:59 +020011904
Daniel Vetter7fad7982012-07-04 17:51:47 +020011905 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11906 crtc->pipe == PIPE_A && !crtc->active) {
11907 /* BIOS forgot to enable pipe A, this mostly happens after
11908 * resume. Force-enable the pipe to fix this, the update_dpms
11909 * call below we restore the pipe to the right state, but leave
11910 * the required bits on. */
11911 intel_enable_pipe_a(dev);
11912 }
11913
Daniel Vetter24929352012-07-02 20:28:59 +020011914 /* Adjust the state of the output pipe according to whether we
11915 * have active connectors/encoders. */
11916 intel_crtc_update_dpms(&crtc->base);
11917
11918 if (crtc->active != crtc->base.enabled) {
11919 struct intel_encoder *encoder;
11920
11921 /* This can happen either due to bugs in the get_hw_state
11922 * functions or because the pipe is force-enabled due to the
11923 * pipe A quirk. */
11924 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11925 crtc->base.base.id,
11926 crtc->base.enabled ? "enabled" : "disabled",
11927 crtc->active ? "enabled" : "disabled");
11928
11929 crtc->base.enabled = crtc->active;
11930
11931 /* Because we only establish the connector -> encoder ->
11932 * crtc links if something is active, this means the
11933 * crtc is now deactivated. Break the links. connector
11934 * -> encoder links are only establish when things are
11935 * actually up, hence no need to break them. */
11936 WARN_ON(crtc->active);
11937
11938 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11939 WARN_ON(encoder->connectors_active);
11940 encoder->base.crtc = NULL;
11941 }
11942 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020011943
11944 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010011945 /*
11946 * We start out with underrun reporting disabled to avoid races.
11947 * For correct bookkeeping mark this on active crtcs.
11948 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020011949 * Also on gmch platforms we dont have any hardware bits to
11950 * disable the underrun reporting. Which means we need to start
11951 * out with underrun reporting disabled also on inactive pipes,
11952 * since otherwise we'll complain about the garbage we read when
11953 * e.g. coming up after runtime pm.
11954 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010011955 * No protection against concurrent access is required - at
11956 * worst a fifo underrun happens which also sets this to false.
11957 */
11958 crtc->cpu_fifo_underrun_disabled = true;
11959 crtc->pch_fifo_underrun_disabled = true;
Ville Syrjälä80715b22014-05-15 20:23:23 +030011960
11961 update_scanline_offset(crtc);
Daniel Vetter4cc31482014-03-24 00:01:41 +010011962 }
Daniel Vetter24929352012-07-02 20:28:59 +020011963}
11964
11965static void intel_sanitize_encoder(struct intel_encoder *encoder)
11966{
11967 struct intel_connector *connector;
11968 struct drm_device *dev = encoder->base.dev;
11969
11970 /* We need to check both for a crtc link (meaning that the
11971 * encoder is active and trying to read from a pipe) and the
11972 * pipe itself being active. */
11973 bool has_active_crtc = encoder->base.crtc &&
11974 to_intel_crtc(encoder->base.crtc)->active;
11975
11976 if (encoder->connectors_active && !has_active_crtc) {
11977 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11978 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030011979 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020011980
11981 /* Connector is active, but has no active pipe. This is
11982 * fallout from our resume register restoring. Disable
11983 * the encoder manually again. */
11984 if (encoder->base.crtc) {
11985 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11986 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030011987 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020011988 encoder->disable(encoder);
11989 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020011990 encoder->base.crtc = NULL;
11991 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020011992
11993 /* Inconsistent output/port/pipe state happens presumably due to
11994 * a bug in one of the get_hw_state functions. Or someplace else
11995 * in our code, like the register restore mess on resume. Clamp
11996 * things to off as a safer default. */
11997 list_for_each_entry(connector,
11998 &dev->mode_config.connector_list,
11999 base.head) {
12000 if (connector->encoder != encoder)
12001 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020012002 connector->base.dpms = DRM_MODE_DPMS_OFF;
12003 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020012004 }
12005 }
12006 /* Enabled encoders without active connectors will be fixed in
12007 * the crtc fixup. */
12008}
12009
Imre Deak04098752014-02-18 00:02:16 +020012010void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012011{
12012 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012013 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012014
Imre Deak04098752014-02-18 00:02:16 +020012015 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12016 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12017 i915_disable_vga(dev);
12018 }
12019}
12020
12021void i915_redisable_vga(struct drm_device *dev)
12022{
12023 struct drm_i915_private *dev_priv = dev->dev_private;
12024
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030012025 /* This function can be called both from intel_modeset_setup_hw_state or
12026 * at a very early point in our resume sequence, where the power well
12027 * structures are not yet restored. Since this function is at a very
12028 * paranoid "someone might have enabled VGA while we were not looking"
12029 * level, just check if the power well is enabled instead of trying to
12030 * follow the "don't touch the power well if we don't need it" policy
12031 * the rest of the driver uses. */
Imre Deak04098752014-02-18 00:02:16 +020012032 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030012033 return;
12034
Imre Deak04098752014-02-18 00:02:16 +020012035 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012036}
12037
Ville Syrjälä98ec7732014-04-30 17:43:01 +030012038static bool primary_get_hw_state(struct intel_crtc *crtc)
12039{
12040 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12041
12042 if (!crtc->active)
12043 return false;
12044
12045 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12046}
12047
Daniel Vetter30e984d2013-06-05 13:34:17 +020012048static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020012049{
12050 struct drm_i915_private *dev_priv = dev->dev_private;
12051 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020012052 struct intel_crtc *crtc;
12053 struct intel_encoder *encoder;
12054 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020012055 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020012056
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012057 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010012058 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020012059
Daniel Vetter99535992014-04-13 12:00:33 +020012060 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12061
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012062 crtc->active = dev_priv->display.get_pipe_config(crtc,
12063 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020012064
12065 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030012066 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020012067
12068 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12069 crtc->base.base.id,
12070 crtc->active ? "enabled" : "disabled");
12071 }
12072
Daniel Vetter53589012013-06-05 13:34:16 +020012073 /* FIXME: Smash this into the new shared dpll infrastructure. */
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012074 if (HAS_DDI(dev))
Paulo Zanoni6441ab52012-10-05 12:05:58 -030012075 intel_ddi_setup_hw_pll_state(dev);
12076
Daniel Vetter53589012013-06-05 13:34:16 +020012077 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12078 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12079
12080 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12081 pll->active = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012082 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020012083 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12084 pll->active++;
12085 }
12086 pll->refcount = pll->active;
12087
Daniel Vetter35c95372013-07-17 06:55:04 +020012088 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12089 pll->name, pll->refcount, pll->on);
Daniel Vetter53589012013-06-05 13:34:16 +020012090 }
12091
Daniel Vetter24929352012-07-02 20:28:59 +020012092 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12093 base.head) {
12094 pipe = 0;
12095
12096 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070012097 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12098 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010012099 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020012100 } else {
12101 encoder->base.crtc = NULL;
12102 }
12103
12104 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010012105 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020012106 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012107 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020012108 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010012109 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020012110 }
12111
12112 list_for_each_entry(connector, &dev->mode_config.connector_list,
12113 base.head) {
12114 if (connector->get_hw_state(connector)) {
12115 connector->base.dpms = DRM_MODE_DPMS_ON;
12116 connector->encoder->connectors_active = true;
12117 connector->base.encoder = &connector->encoder->base;
12118 } else {
12119 connector->base.dpms = DRM_MODE_DPMS_OFF;
12120 connector->base.encoder = NULL;
12121 }
12122 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12123 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030012124 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020012125 connector->base.encoder ? "enabled" : "disabled");
12126 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020012127}
12128
12129/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12130 * and i915 state tracking structures. */
12131void intel_modeset_setup_hw_state(struct drm_device *dev,
12132 bool force_restore)
12133{
12134 struct drm_i915_private *dev_priv = dev->dev_private;
12135 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020012136 struct intel_crtc *crtc;
12137 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020012138 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020012139
12140 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020012141
Jesse Barnesbabea612013-06-26 18:57:38 +030012142 /*
12143 * Now that we have the config, copy it to each CRTC struct
12144 * Note that this could go away if we move to using crtc_config
12145 * checking everywhere.
12146 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012147 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020012148 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080012149 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030012150 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12151 crtc->base.base.id);
12152 drm_mode_debug_printmodeline(&crtc->base.mode);
12153 }
12154 }
12155
Daniel Vetter24929352012-07-02 20:28:59 +020012156 /* HW state is read out, now we need to sanitize this mess. */
12157 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12158 base.head) {
12159 intel_sanitize_encoder(encoder);
12160 }
12161
12162 for_each_pipe(pipe) {
12163 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12164 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020012165 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020012166 }
Daniel Vetter9a935852012-07-05 22:34:27 +020012167
Daniel Vetter35c95372013-07-17 06:55:04 +020012168 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12169 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12170
12171 if (!pll->on || pll->active)
12172 continue;
12173
12174 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12175
12176 pll->disable(dev_priv, pll);
12177 pll->on = false;
12178 }
12179
Ville Syrjälä96f90c52013-12-05 15:51:38 +020012180 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030012181 ilk_wm_get_hw_state(dev);
12182
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012183 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030012184 i915_redisable_vga(dev);
12185
Daniel Vetterf30da182013-04-11 20:22:50 +020012186 /*
12187 * We need to use raw interfaces for restoring state to avoid
12188 * checking (bogus) intermediate states.
12189 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012190 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070012191 struct drm_crtc *crtc =
12192 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020012193
12194 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
Matt Roperf4510a22014-04-01 15:22:40 -070012195 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010012196 }
12197 } else {
12198 intel_modeset_update_staged_output_state(dev);
12199 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012200
12201 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010012202}
12203
12204void intel_modeset_gem_init(struct drm_device *dev)
12205{
Jesse Barnes484b41d2014-03-07 08:57:55 -080012206 struct drm_crtc *c;
12207 struct intel_framebuffer *fb;
12208
Imre Deakae484342014-03-31 15:10:44 +030012209 mutex_lock(&dev->struct_mutex);
12210 intel_init_gt_powersave(dev);
12211 mutex_unlock(&dev->struct_mutex);
12212
Chris Wilson1833b132012-05-09 11:56:28 +010012213 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020012214
12215 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080012216
12217 /*
12218 * Make sure any fbs we allocated at startup are properly
12219 * pinned & fenced. When we do the allocation it's too early
12220 * for this.
12221 */
12222 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010012223 for_each_crtc(dev, c) {
Dave Airlie66e514c2014-04-03 07:51:54 +100012224 if (!c->primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -080012225 continue;
12226
Dave Airlie66e514c2014-04-03 07:51:54 +100012227 fb = to_intel_framebuffer(c->primary->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -080012228 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12229 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12230 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100012231 drm_framebuffer_unreference(c->primary->fb);
12232 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080012233 }
12234 }
12235 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012236}
12237
Imre Deak4932e2c2014-02-11 17:12:48 +020012238void intel_connector_unregister(struct intel_connector *intel_connector)
12239{
12240 struct drm_connector *connector = &intel_connector->base;
12241
12242 intel_panel_destroy_backlight(connector);
12243 drm_sysfs_connector_remove(connector);
12244}
12245
Jesse Barnes79e53942008-11-07 14:24:08 -080012246void intel_modeset_cleanup(struct drm_device *dev)
12247{
Jesse Barnes652c3932009-08-17 13:31:43 -070012248 struct drm_i915_private *dev_priv = dev->dev_private;
12249 struct drm_crtc *crtc;
Paulo Zanonid9255d52013-09-26 20:05:59 -030012250 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070012251
Daniel Vetterfd0c0642013-04-24 11:13:35 +020012252 /*
12253 * Interrupts and polling as the first thing to avoid creating havoc.
12254 * Too much stuff here (turning of rps, connectors, ...) would
12255 * experience fancy races otherwise.
12256 */
12257 drm_irq_uninstall(dev);
12258 cancel_work_sync(&dev_priv->hotplug_work);
12259 /*
12260 * Due to the hpd irq storm handling the hotplug work can re-arm the
12261 * poll handlers. Hence disable polling after hpd handling is shut down.
12262 */
Keith Packardf87ea762010-10-03 19:36:26 -070012263 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020012264
Jesse Barnes652c3932009-08-17 13:31:43 -070012265 mutex_lock(&dev->struct_mutex);
12266
Jesse Barnes723bfd72010-10-07 16:01:13 -070012267 intel_unregister_dsm_handler();
12268
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010012269 for_each_crtc(dev, crtc) {
Jesse Barnes652c3932009-08-17 13:31:43 -070012270 /* Skip inactive CRTCs */
Matt Roperf4510a22014-04-01 15:22:40 -070012271 if (!crtc->primary->fb)
Jesse Barnes652c3932009-08-17 13:31:43 -070012272 continue;
12273
Daniel Vetter3dec0092010-08-20 21:40:52 +020012274 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -070012275 }
12276
Chris Wilson973d04f2011-07-08 12:22:37 +010012277 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012278
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012279 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000012280
Daniel Vetter930ebb42012-06-29 23:32:16 +020012281 ironlake_teardown_rc6(dev);
12282
Kristian Høgsberg69341a52009-11-11 12:19:17 -050012283 mutex_unlock(&dev->struct_mutex);
12284
Chris Wilson1630fe72011-07-08 12:22:42 +010012285 /* flush any delayed tasks or pending work */
12286 flush_scheduled_work();
12287
Jani Nikuladb31af12013-11-08 16:48:53 +020012288 /* destroy the backlight and sysfs files before encoders/connectors */
12289 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020012290 struct intel_connector *intel_connector;
12291
12292 intel_connector = to_intel_connector(connector);
12293 intel_connector->unregister(intel_connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020012294 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030012295
Jesse Barnes79e53942008-11-07 14:24:08 -080012296 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010012297
12298 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030012299
12300 mutex_lock(&dev->struct_mutex);
12301 intel_cleanup_gt_powersave(dev);
12302 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012303}
12304
Dave Airlie28d52042009-09-21 14:33:58 +100012305/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080012306 * Return which encoder is currently attached for connector.
12307 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010012308struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080012309{
Chris Wilsondf0e9242010-09-09 16:20:55 +010012310 return &intel_attached_encoder(connector)->base;
12311}
Jesse Barnes79e53942008-11-07 14:24:08 -080012312
Chris Wilsondf0e9242010-09-09 16:20:55 +010012313void intel_connector_attach_encoder(struct intel_connector *connector,
12314 struct intel_encoder *encoder)
12315{
12316 connector->encoder = encoder;
12317 drm_mode_connector_attach_encoder(&connector->base,
12318 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080012319}
Dave Airlie28d52042009-09-21 14:33:58 +100012320
12321/*
12322 * set vga decode state - true == enable VGA decode
12323 */
12324int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12325{
12326 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000012327 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100012328 u16 gmch_ctrl;
12329
Chris Wilson75fa0412014-02-07 18:37:02 -020012330 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12331 DRM_ERROR("failed to read control word\n");
12332 return -EIO;
12333 }
12334
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020012335 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12336 return 0;
12337
Dave Airlie28d52042009-09-21 14:33:58 +100012338 if (state)
12339 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12340 else
12341 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020012342
12343 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12344 DRM_ERROR("failed to write control word\n");
12345 return -EIO;
12346 }
12347
Dave Airlie28d52042009-09-21 14:33:58 +100012348 return 0;
12349}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012350
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012351struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012352
12353 u32 power_well_driver;
12354
Chris Wilson63b66e52013-08-08 15:12:06 +020012355 int num_transcoders;
12356
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012357 struct intel_cursor_error_state {
12358 u32 control;
12359 u32 position;
12360 u32 base;
12361 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010012362 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012363
12364 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020012365 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012366 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030012367 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010012368 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012369
12370 struct intel_plane_error_state {
12371 u32 control;
12372 u32 stride;
12373 u32 size;
12374 u32 pos;
12375 u32 addr;
12376 u32 surface;
12377 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010012378 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020012379
12380 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020012381 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020012382 enum transcoder cpu_transcoder;
12383
12384 u32 conf;
12385
12386 u32 htotal;
12387 u32 hblank;
12388 u32 hsync;
12389 u32 vtotal;
12390 u32 vblank;
12391 u32 vsync;
12392 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012393};
12394
12395struct intel_display_error_state *
12396intel_display_capture_error_state(struct drm_device *dev)
12397{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012398 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012399 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020012400 int transcoders[] = {
12401 TRANSCODER_A,
12402 TRANSCODER_B,
12403 TRANSCODER_C,
12404 TRANSCODER_EDP,
12405 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012406 int i;
12407
Chris Wilson63b66e52013-08-08 15:12:06 +020012408 if (INTEL_INFO(dev)->num_pipes == 0)
12409 return NULL;
12410
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012411 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012412 if (error == NULL)
12413 return NULL;
12414
Imre Deak190be112013-11-25 17:15:31 +020012415 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012416 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12417
Damien Lespiau52331302012-08-15 19:23:25 +010012418 for_each_pipe(i) {
Imre Deakddf9c532013-11-27 22:02:02 +020012419 error->pipe[i].power_domain_on =
Imre Deakda7e29b2014-02-18 00:02:02 +020012420 intel_display_power_enabled_sw(dev_priv,
12421 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020012422 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012423 continue;
12424
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030012425 error->cursor[i].control = I915_READ(CURCNTR(i));
12426 error->cursor[i].position = I915_READ(CURPOS(i));
12427 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012428
12429 error->plane[i].control = I915_READ(DSPCNTR(i));
12430 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012431 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030012432 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012433 error->plane[i].pos = I915_READ(DSPPOS(i));
12434 }
Paulo Zanonica291362013-03-06 20:03:14 -030012435 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12436 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012437 if (INTEL_INFO(dev)->gen >= 4) {
12438 error->plane[i].surface = I915_READ(DSPSURF(i));
12439 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12440 }
12441
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012442 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030012443
12444 if (!HAS_PCH_SPLIT(dev))
12445 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020012446 }
12447
12448 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12449 if (HAS_DDI(dev_priv->dev))
12450 error->num_transcoders++; /* Account for eDP. */
12451
12452 for (i = 0; i < error->num_transcoders; i++) {
12453 enum transcoder cpu_transcoder = transcoders[i];
12454
Imre Deakddf9c532013-11-27 22:02:02 +020012455 error->transcoder[i].power_domain_on =
Imre Deakda7e29b2014-02-18 00:02:02 +020012456 intel_display_power_enabled_sw(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020012457 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020012458 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020012459 continue;
12460
Chris Wilson63b66e52013-08-08 15:12:06 +020012461 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12462
12463 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12464 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12465 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12466 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12467 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12468 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12469 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012470 }
12471
12472 return error;
12473}
12474
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012475#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12476
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012477void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012478intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012479 struct drm_device *dev,
12480 struct intel_display_error_state *error)
12481{
12482 int i;
12483
Chris Wilson63b66e52013-08-08 15:12:06 +020012484 if (!error)
12485 return;
12486
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012487 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020012488 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012489 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030012490 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010012491 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012492 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020012493 err_printf(m, " Power: %s\n",
12494 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012495 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030012496 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012497
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012498 err_printf(m, "Plane [%d]:\n", i);
12499 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12500 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012501 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012502 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12503 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030012504 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030012505 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012506 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012507 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012508 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12509 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012510 }
12511
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030012512 err_printf(m, "Cursor [%d]:\n", i);
12513 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12514 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12515 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012516 }
Chris Wilson63b66e52013-08-08 15:12:06 +020012517
12518 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010012519 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020012520 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020012521 err_printf(m, " Power: %s\n",
12522 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020012523 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12524 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12525 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12526 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12527 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12528 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12529 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12530 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000012531}