Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 29 | #include <drm/drm_vma_manager.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 34 | #include <linux/oom.h> |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 35 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 36 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 37 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 39 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 40 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 43 | bool force); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 44 | static __must_check int |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 46 | bool readonly); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 47 | static void |
| 48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); |
| 49 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 51 | struct drm_i915_gem_object *obj); |
| 52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 53 | struct drm_i915_fence_reg *fence, |
| 54 | bool enable); |
| 55 | |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 57 | struct shrink_control *sc); |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 59 | struct shrink_control *sc); |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
| 61 | unsigned long event, |
| 62 | void *ptr); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 63 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 64 | |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 65 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 66 | enum i915_cache_level level) |
| 67 | { |
| 68 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 69 | } |
| 70 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 71 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 72 | { |
| 73 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 74 | return true; |
| 75 | |
| 76 | return obj->pin_display; |
| 77 | } |
| 78 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 79 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 80 | { |
| 81 | if (obj->tiling_mode) |
| 82 | i915_gem_release_mmap(obj); |
| 83 | |
| 84 | /* As we do not have an associated fence register, we will force |
| 85 | * a tiling change if we ever need to acquire one. |
| 86 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 87 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 88 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 89 | } |
| 90 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 91 | /* some bookkeeping */ |
| 92 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 93 | size_t size) |
| 94 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 95 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 96 | dev_priv->mm.object_count++; |
| 97 | dev_priv->mm.object_memory += size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 98 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 102 | size_t size) |
| 103 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 104 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 105 | dev_priv->mm.object_count--; |
| 106 | dev_priv->mm.object_memory -= size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 107 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 108 | } |
| 109 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 110 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 111 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 112 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 113 | int ret; |
| 114 | |
Daniel Vetter | 7abb690 | 2013-05-24 21:29:32 +0200 | [diff] [blame] | 115 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
| 116 | i915_terminally_wedged(error)) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 117 | if (EXIT_COND) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 118 | return 0; |
| 119 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 120 | /* |
| 121 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 122 | * userspace. If it takes that long something really bad is going on and |
| 123 | * we should simply try to bail out and fail as gracefully as possible. |
| 124 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 125 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 126 | EXIT_COND, |
| 127 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 128 | if (ret == 0) { |
| 129 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 130 | return -EIO; |
| 131 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 132 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 133 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 134 | #undef EXIT_COND |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 135 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 136 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 137 | } |
| 138 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 139 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 140 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 141 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 142 | int ret; |
| 143 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 144 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 145 | if (ret) |
| 146 | return ret; |
| 147 | |
| 148 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 149 | if (ret) |
| 150 | return ret; |
| 151 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 152 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 153 | return 0; |
| 154 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 155 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 156 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 157 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 158 | { |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 159 | return i915_gem_obj_bound_any(obj) && !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 160 | } |
| 161 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 162 | int |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 163 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 164 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 165 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 167 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 168 | struct drm_i915_gem_object *obj; |
| 169 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 170 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 171 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 172 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 173 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 174 | if (i915_gem_obj_is_pinned(obj)) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 175 | pinned += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 176 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 177 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 178 | args->aper_size = dev_priv->gtt.base.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 179 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 180 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 181 | return 0; |
| 182 | } |
| 183 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 184 | static int |
| 185 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 186 | { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 187 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 188 | char *vaddr = obj->phys_handle->vaddr; |
| 189 | struct sg_table *st; |
| 190 | struct scatterlist *sg; |
| 191 | int i; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 192 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 193 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
| 194 | return -EINVAL; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 195 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 196 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 197 | struct page *page; |
| 198 | char *src; |
| 199 | |
| 200 | page = shmem_read_mapping_page(mapping, i); |
| 201 | if (IS_ERR(page)) |
| 202 | return PTR_ERR(page); |
| 203 | |
| 204 | src = kmap_atomic(page); |
| 205 | memcpy(vaddr, src, PAGE_SIZE); |
| 206 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 207 | kunmap_atomic(src); |
| 208 | |
| 209 | page_cache_release(page); |
| 210 | vaddr += PAGE_SIZE; |
| 211 | } |
| 212 | |
| 213 | i915_gem_chipset_flush(obj->base.dev); |
| 214 | |
| 215 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 216 | if (st == NULL) |
| 217 | return -ENOMEM; |
| 218 | |
| 219 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { |
| 220 | kfree(st); |
| 221 | return -ENOMEM; |
| 222 | } |
| 223 | |
| 224 | sg = st->sgl; |
| 225 | sg->offset = 0; |
| 226 | sg->length = obj->base.size; |
| 227 | |
| 228 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
| 229 | sg_dma_len(sg) = obj->base.size; |
| 230 | |
| 231 | obj->pages = st; |
| 232 | obj->has_dma_mapping = true; |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | static void |
| 237 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) |
| 238 | { |
| 239 | int ret; |
| 240 | |
| 241 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 242 | |
| 243 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 244 | if (ret) { |
| 245 | /* In the event of a disaster, abandon all caches and |
| 246 | * hope for the best. |
| 247 | */ |
| 248 | WARN_ON(ret != -EIO); |
| 249 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 250 | } |
| 251 | |
| 252 | if (obj->madv == I915_MADV_DONTNEED) |
| 253 | obj->dirty = 0; |
| 254 | |
| 255 | if (obj->dirty) { |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 256 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 257 | char *vaddr = obj->phys_handle->vaddr; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 258 | int i; |
| 259 | |
| 260 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 261 | struct page *page; |
| 262 | char *dst; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 263 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 264 | page = shmem_read_mapping_page(mapping, i); |
| 265 | if (IS_ERR(page)) |
| 266 | continue; |
| 267 | |
| 268 | dst = kmap_atomic(page); |
| 269 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 270 | memcpy(dst, vaddr, PAGE_SIZE); |
| 271 | kunmap_atomic(dst); |
| 272 | |
| 273 | set_page_dirty(page); |
| 274 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 275 | mark_page_accessed(page); |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 276 | page_cache_release(page); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 277 | vaddr += PAGE_SIZE; |
| 278 | } |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 279 | obj->dirty = 0; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 280 | } |
| 281 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 282 | sg_free_table(obj->pages); |
| 283 | kfree(obj->pages); |
| 284 | |
| 285 | obj->has_dma_mapping = false; |
| 286 | } |
| 287 | |
| 288 | static void |
| 289 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) |
| 290 | { |
| 291 | drm_pci_free(obj->base.dev, obj->phys_handle); |
| 292 | } |
| 293 | |
| 294 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { |
| 295 | .get_pages = i915_gem_object_get_pages_phys, |
| 296 | .put_pages = i915_gem_object_put_pages_phys, |
| 297 | .release = i915_gem_object_release_phys, |
| 298 | }; |
| 299 | |
| 300 | static int |
| 301 | drop_pages(struct drm_i915_gem_object *obj) |
| 302 | { |
| 303 | struct i915_vma *vma, *next; |
| 304 | int ret; |
| 305 | |
| 306 | drm_gem_object_reference(&obj->base); |
| 307 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) |
| 308 | if (i915_vma_unbind(vma)) |
| 309 | break; |
| 310 | |
| 311 | ret = i915_gem_object_put_pages(obj); |
| 312 | drm_gem_object_unreference(&obj->base); |
| 313 | |
| 314 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 315 | } |
| 316 | |
| 317 | int |
| 318 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
| 319 | int align) |
| 320 | { |
| 321 | drm_dma_handle_t *phys; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 322 | int ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 323 | |
| 324 | if (obj->phys_handle) { |
| 325 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) |
| 326 | return -EBUSY; |
| 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
| 331 | if (obj->madv != I915_MADV_WILLNEED) |
| 332 | return -EFAULT; |
| 333 | |
| 334 | if (obj->base.filp == NULL) |
| 335 | return -EINVAL; |
| 336 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 337 | ret = drop_pages(obj); |
| 338 | if (ret) |
| 339 | return ret; |
| 340 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 341 | /* create a new object */ |
| 342 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); |
| 343 | if (!phys) |
| 344 | return -ENOMEM; |
| 345 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 346 | obj->phys_handle = phys; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 347 | obj->ops = &i915_gem_phys_ops; |
| 348 | |
| 349 | return i915_gem_object_get_pages(obj); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | static int |
| 353 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, |
| 354 | struct drm_i915_gem_pwrite *args, |
| 355 | struct drm_file *file_priv) |
| 356 | { |
| 357 | struct drm_device *dev = obj->base.dev; |
| 358 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
| 359 | char __user *user_data = to_user_ptr(args->data_ptr); |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 360 | int ret; |
| 361 | |
| 362 | /* We manually control the domain here and pretend that it |
| 363 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. |
| 364 | */ |
| 365 | ret = i915_gem_object_wait_rendering(obj, false); |
| 366 | if (ret) |
| 367 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 368 | |
| 369 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 370 | unsigned long unwritten; |
| 371 | |
| 372 | /* The physical object once assigned is fixed for the lifetime |
| 373 | * of the obj, so we can safely drop the lock and continue |
| 374 | * to access vaddr. |
| 375 | */ |
| 376 | mutex_unlock(&dev->struct_mutex); |
| 377 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 378 | mutex_lock(&dev->struct_mutex); |
| 379 | if (unwritten) |
| 380 | return -EFAULT; |
| 381 | } |
| 382 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 383 | drm_clflush_virt_range(vaddr, args->size); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 384 | i915_gem_chipset_flush(dev); |
| 385 | return 0; |
| 386 | } |
| 387 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 388 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 389 | { |
| 390 | struct drm_i915_private *dev_priv = dev->dev_private; |
Joe Perches | fac15c1 | 2013-08-29 13:11:07 -0700 | [diff] [blame] | 391 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 392 | } |
| 393 | |
| 394 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 395 | { |
| 396 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 397 | kmem_cache_free(dev_priv->slab, obj); |
| 398 | } |
| 399 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 400 | static int |
| 401 | i915_gem_create(struct drm_file *file, |
| 402 | struct drm_device *dev, |
| 403 | uint64_t size, |
| 404 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 405 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 406 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 407 | int ret; |
| 408 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 409 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 410 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 411 | if (size == 0) |
| 412 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 413 | |
| 414 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 415 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 416 | if (obj == NULL) |
| 417 | return -ENOMEM; |
| 418 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 419 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 420 | /* drop reference from allocate - handle holds it now */ |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 421 | drm_gem_object_unreference_unlocked(&obj->base); |
| 422 | if (ret) |
| 423 | return ret; |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 424 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 425 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 426 | return 0; |
| 427 | } |
| 428 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 429 | int |
| 430 | i915_gem_dumb_create(struct drm_file *file, |
| 431 | struct drm_device *dev, |
| 432 | struct drm_mode_create_dumb *args) |
| 433 | { |
| 434 | /* have to work out size/pitch and return them */ |
Paulo Zanoni | de45eaf | 2013-10-18 18:48:24 -0300 | [diff] [blame] | 435 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 436 | args->size = args->pitch * args->height; |
| 437 | return i915_gem_create(file, dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame^] | 438 | args->size, &args->handle); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 439 | } |
| 440 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 441 | /** |
| 442 | * Creates a new mm object and returns a handle to it. |
| 443 | */ |
| 444 | int |
| 445 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 446 | struct drm_file *file) |
| 447 | { |
| 448 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 449 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 450 | return i915_gem_create(file, dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame^] | 451 | args->size, &args->handle); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 452 | } |
| 453 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 454 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 455 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 456 | const char *gpu_vaddr, int gpu_offset, |
| 457 | int length) |
| 458 | { |
| 459 | int ret, cpu_offset = 0; |
| 460 | |
| 461 | while (length > 0) { |
| 462 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 463 | int this_length = min(cacheline_end - gpu_offset, length); |
| 464 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 465 | |
| 466 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 467 | gpu_vaddr + swizzled_gpu_offset, |
| 468 | this_length); |
| 469 | if (ret) |
| 470 | return ret + length; |
| 471 | |
| 472 | cpu_offset += this_length; |
| 473 | gpu_offset += this_length; |
| 474 | length -= this_length; |
| 475 | } |
| 476 | |
| 477 | return 0; |
| 478 | } |
| 479 | |
| 480 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 481 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 482 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 483 | int length) |
| 484 | { |
| 485 | int ret, cpu_offset = 0; |
| 486 | |
| 487 | while (length > 0) { |
| 488 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 489 | int this_length = min(cacheline_end - gpu_offset, length); |
| 490 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 491 | |
| 492 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 493 | cpu_vaddr + cpu_offset, |
| 494 | this_length); |
| 495 | if (ret) |
| 496 | return ret + length; |
| 497 | |
| 498 | cpu_offset += this_length; |
| 499 | gpu_offset += this_length; |
| 500 | length -= this_length; |
| 501 | } |
| 502 | |
| 503 | return 0; |
| 504 | } |
| 505 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 506 | /* |
| 507 | * Pins the specified object's pages and synchronizes the object with |
| 508 | * GPU accesses. Sets needs_clflush to non-zero if the caller should |
| 509 | * flush the object from the CPU cache. |
| 510 | */ |
| 511 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 512 | int *needs_clflush) |
| 513 | { |
| 514 | int ret; |
| 515 | |
| 516 | *needs_clflush = 0; |
| 517 | |
| 518 | if (!obj->base.filp) |
| 519 | return -EINVAL; |
| 520 | |
| 521 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 522 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 523 | * read domain and manually flush cachelines (if required). This |
| 524 | * optimizes for the case when the gpu will dirty the data |
| 525 | * anyway again before the next pread happens. */ |
| 526 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
| 527 | obj->cache_level); |
| 528 | ret = i915_gem_object_wait_rendering(obj, true); |
| 529 | if (ret) |
| 530 | return ret; |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 531 | |
| 532 | i915_gem_object_retire(obj); |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | ret = i915_gem_object_get_pages(obj); |
| 536 | if (ret) |
| 537 | return ret; |
| 538 | |
| 539 | i915_gem_object_pin_pages(obj); |
| 540 | |
| 541 | return ret; |
| 542 | } |
| 543 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 544 | /* Per-page copy function for the shmem pread fastpath. |
| 545 | * Flushes invalid cachelines before reading the target if |
| 546 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 547 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 548 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 549 | char __user *user_data, |
| 550 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 551 | { |
| 552 | char *vaddr; |
| 553 | int ret; |
| 554 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 555 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 556 | return -EINVAL; |
| 557 | |
| 558 | vaddr = kmap_atomic(page); |
| 559 | if (needs_clflush) |
| 560 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 561 | page_length); |
| 562 | ret = __copy_to_user_inatomic(user_data, |
| 563 | vaddr + shmem_page_offset, |
| 564 | page_length); |
| 565 | kunmap_atomic(vaddr); |
| 566 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 567 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 568 | } |
| 569 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 570 | static void |
| 571 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 572 | bool swizzled) |
| 573 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 574 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 575 | unsigned long start = (unsigned long) addr; |
| 576 | unsigned long end = (unsigned long) addr + length; |
| 577 | |
| 578 | /* For swizzling simply ensure that we always flush both |
| 579 | * channels. Lame, but simple and it works. Swizzled |
| 580 | * pwrite/pread is far from a hotpath - current userspace |
| 581 | * doesn't use it at all. */ |
| 582 | start = round_down(start, 128); |
| 583 | end = round_up(end, 128); |
| 584 | |
| 585 | drm_clflush_virt_range((void *)start, end - start); |
| 586 | } else { |
| 587 | drm_clflush_virt_range(addr, length); |
| 588 | } |
| 589 | |
| 590 | } |
| 591 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 592 | /* Only difference to the fast-path function is that this can handle bit17 |
| 593 | * and uses non-atomic copy and kmap functions. */ |
| 594 | static int |
| 595 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 596 | char __user *user_data, |
| 597 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 598 | { |
| 599 | char *vaddr; |
| 600 | int ret; |
| 601 | |
| 602 | vaddr = kmap(page); |
| 603 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 604 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 605 | page_length, |
| 606 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 607 | |
| 608 | if (page_do_bit17_swizzling) |
| 609 | ret = __copy_to_user_swizzled(user_data, |
| 610 | vaddr, shmem_page_offset, |
| 611 | page_length); |
| 612 | else |
| 613 | ret = __copy_to_user(user_data, |
| 614 | vaddr + shmem_page_offset, |
| 615 | page_length); |
| 616 | kunmap(page); |
| 617 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 618 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 619 | } |
| 620 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 621 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 622 | i915_gem_shmem_pread(struct drm_device *dev, |
| 623 | struct drm_i915_gem_object *obj, |
| 624 | struct drm_i915_gem_pread *args, |
| 625 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 626 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 627 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 628 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 629 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 630 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 631 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 632 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 633 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 634 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 635 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 636 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 637 | remain = args->size; |
| 638 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 639 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 640 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 641 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 642 | if (ret) |
| 643 | return ret; |
| 644 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 645 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 646 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 647 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 648 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 649 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 650 | |
| 651 | if (remain <= 0) |
| 652 | break; |
| 653 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 654 | /* Operation in this page |
| 655 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 656 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 657 | * page_length = bytes to copy for this page |
| 658 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 659 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 660 | page_length = remain; |
| 661 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 662 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 663 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 664 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 665 | (page_to_phys(page) & (1 << 17)) != 0; |
| 666 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 667 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 668 | user_data, page_do_bit17_swizzling, |
| 669 | needs_clflush); |
| 670 | if (ret == 0) |
| 671 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 672 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 673 | mutex_unlock(&dev->struct_mutex); |
| 674 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 675 | if (likely(!i915.prefault_disable) && !prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 676 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 677 | /* Userspace is tricking us, but we've already clobbered |
| 678 | * its pages with the prefault and promised to write the |
| 679 | * data up to the first fault. Hence ignore any errors |
| 680 | * and just continue. */ |
| 681 | (void)ret; |
| 682 | prefaulted = 1; |
| 683 | } |
| 684 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 685 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 686 | user_data, page_do_bit17_swizzling, |
| 687 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 688 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 689 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 690 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 691 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 692 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 693 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 694 | next_page: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 695 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 696 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 697 | offset += page_length; |
| 698 | } |
| 699 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 700 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 701 | i915_gem_object_unpin_pages(obj); |
| 702 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 703 | return ret; |
| 704 | } |
| 705 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 706 | /** |
| 707 | * Reads data from the object referenced by handle. |
| 708 | * |
| 709 | * On error, the contents of *data are undefined. |
| 710 | */ |
| 711 | int |
| 712 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 713 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 714 | { |
| 715 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 716 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 717 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 718 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 719 | if (args->size == 0) |
| 720 | return 0; |
| 721 | |
| 722 | if (!access_ok(VERIFY_WRITE, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 723 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 724 | args->size)) |
| 725 | return -EFAULT; |
| 726 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 727 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 728 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 729 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 730 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 731 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 732 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 733 | ret = -ENOENT; |
| 734 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 735 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 736 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 737 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 738 | if (args->offset > obj->base.size || |
| 739 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 740 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 741 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 742 | } |
| 743 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 744 | /* prime objects have no backing filp to GEM pread/pwrite |
| 745 | * pages from. |
| 746 | */ |
| 747 | if (!obj->base.filp) { |
| 748 | ret = -EINVAL; |
| 749 | goto out; |
| 750 | } |
| 751 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 752 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 753 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 754 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 755 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 756 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 757 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 758 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 759 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 760 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 761 | } |
| 762 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 763 | /* This is the fast write path which cannot handle |
| 764 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 765 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 766 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 767 | static inline int |
| 768 | fast_user_write(struct io_mapping *mapping, |
| 769 | loff_t page_base, int page_offset, |
| 770 | char __user *user_data, |
| 771 | int length) |
| 772 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 773 | void __iomem *vaddr_atomic; |
| 774 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 775 | unsigned long unwritten; |
| 776 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 777 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 778 | /* We can use the cpu mem copy function because this is X86. */ |
| 779 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 780 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 781 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 782 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 783 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 784 | } |
| 785 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 786 | /** |
| 787 | * This is the fast pwrite path, where we copy the data directly from the |
| 788 | * user into the GTT, uncached. |
| 789 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 790 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 791 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 792 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 793 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 794 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 795 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 796 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 797 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 798 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 799 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 800 | int page_offset, page_length, ret; |
| 801 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 802 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 803 | if (ret) |
| 804 | goto out; |
| 805 | |
| 806 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 807 | if (ret) |
| 808 | goto out_unpin; |
| 809 | |
| 810 | ret = i915_gem_object_put_fence(obj); |
| 811 | if (ret) |
| 812 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 813 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 814 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 815 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 816 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 817 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 818 | |
| 819 | while (remain > 0) { |
| 820 | /* Operation in this page |
| 821 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 822 | * page_base = page offset within aperture |
| 823 | * page_offset = offset within page |
| 824 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 825 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 826 | page_base = offset & PAGE_MASK; |
| 827 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 828 | page_length = remain; |
| 829 | if ((page_offset + remain) > PAGE_SIZE) |
| 830 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 831 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 832 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 833 | * source page isn't available. Return the error and we'll |
| 834 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 835 | */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 836 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 837 | page_offset, user_data, page_length)) { |
| 838 | ret = -EFAULT; |
| 839 | goto out_unpin; |
| 840 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 841 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 842 | remain -= page_length; |
| 843 | user_data += page_length; |
| 844 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 845 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 846 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 847 | out_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 848 | i915_gem_object_ggtt_unpin(obj); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 849 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 850 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 851 | } |
| 852 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 853 | /* Per-page copy function for the shmem pwrite fastpath. |
| 854 | * Flushes invalid cachelines before writing to the target if |
| 855 | * needs_clflush_before is set and flushes out any written cachelines after |
| 856 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 857 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 858 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 859 | char __user *user_data, |
| 860 | bool page_do_bit17_swizzling, |
| 861 | bool needs_clflush_before, |
| 862 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 863 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 864 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 865 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 866 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 867 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 868 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 869 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 870 | vaddr = kmap_atomic(page); |
| 871 | if (needs_clflush_before) |
| 872 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 873 | page_length); |
Chris Wilson | c2831a9 | 2014-03-07 08:30:37 +0000 | [diff] [blame] | 874 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
| 875 | user_data, page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 876 | if (needs_clflush_after) |
| 877 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 878 | page_length); |
| 879 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 880 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 881 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 882 | } |
| 883 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 884 | /* Only difference to the fast-path function is that this can handle bit17 |
| 885 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 886 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 887 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 888 | char __user *user_data, |
| 889 | bool page_do_bit17_swizzling, |
| 890 | bool needs_clflush_before, |
| 891 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 892 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 893 | char *vaddr; |
| 894 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 895 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 896 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 897 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 898 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 899 | page_length, |
| 900 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 901 | if (page_do_bit17_swizzling) |
| 902 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 903 | user_data, |
| 904 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 905 | else |
| 906 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 907 | user_data, |
| 908 | page_length); |
| 909 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 910 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 911 | page_length, |
| 912 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 913 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 914 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 915 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 916 | } |
| 917 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 918 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 919 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 920 | struct drm_i915_gem_object *obj, |
| 921 | struct drm_i915_gem_pwrite *args, |
| 922 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 923 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 924 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 925 | loff_t offset; |
| 926 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 927 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 928 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 929 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 930 | int needs_clflush_after = 0; |
| 931 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 932 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 933 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 934 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 935 | remain = args->size; |
| 936 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 937 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 938 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 939 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 940 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 941 | * write domain and manually flush cachelines (if required). This |
| 942 | * optimizes for the case when the gpu will use the data |
| 943 | * right away and we therefore have to clflush anyway. */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 944 | needs_clflush_after = cpu_write_needs_clflush(obj); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 945 | ret = i915_gem_object_wait_rendering(obj, false); |
| 946 | if (ret) |
| 947 | return ret; |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 948 | |
| 949 | i915_gem_object_retire(obj); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 950 | } |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 951 | /* Same trick applies to invalidate partially written cachelines read |
| 952 | * before writing. */ |
| 953 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 954 | needs_clflush_before = |
| 955 | !cpu_cache_is_coherent(dev, obj->cache_level); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 956 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 957 | ret = i915_gem_object_get_pages(obj); |
| 958 | if (ret) |
| 959 | return ret; |
| 960 | |
| 961 | i915_gem_object_pin_pages(obj); |
| 962 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 963 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 964 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 965 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 966 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 967 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 968 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 969 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 970 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 971 | if (remain <= 0) |
| 972 | break; |
| 973 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 974 | /* Operation in this page |
| 975 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 976 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 977 | * page_length = bytes to copy for this page |
| 978 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 979 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 980 | |
| 981 | page_length = remain; |
| 982 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 983 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 984 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 985 | /* If we don't overwrite a cacheline completely we need to be |
| 986 | * careful to have up-to-date data by first clflushing. Don't |
| 987 | * overcomplicate things and flush the entire patch. */ |
| 988 | partial_cacheline_write = needs_clflush_before && |
| 989 | ((shmem_page_offset | page_length) |
| 990 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 991 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 992 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 993 | (page_to_phys(page) & (1 << 17)) != 0; |
| 994 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 995 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 996 | user_data, page_do_bit17_swizzling, |
| 997 | partial_cacheline_write, |
| 998 | needs_clflush_after); |
| 999 | if (ret == 0) |
| 1000 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1001 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1002 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1003 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 1004 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 1005 | user_data, page_do_bit17_swizzling, |
| 1006 | partial_cacheline_write, |
| 1007 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1008 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1009 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 1010 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 1011 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1012 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1013 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 1014 | next_page: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1015 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1016 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1017 | offset += page_length; |
| 1018 | } |
| 1019 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1020 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 1021 | i915_gem_object_unpin_pages(obj); |
| 1022 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1023 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 1024 | /* |
| 1025 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 1026 | * cachelines in-line while writing and the object moved |
| 1027 | * out of the cpu write domain while we've dropped the lock. |
| 1028 | */ |
| 1029 | if (!needs_clflush_after && |
| 1030 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 1031 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 1032 | i915_gem_chipset_flush(dev); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1033 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1034 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1035 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 1036 | if (needs_clflush_after) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1037 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 1038 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1039 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1040 | } |
| 1041 | |
| 1042 | /** |
| 1043 | * Writes data to the object referenced by handle. |
| 1044 | * |
| 1045 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1046 | */ |
| 1047 | int |
| 1048 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1049 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1050 | { |
| 1051 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1052 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1053 | int ret; |
| 1054 | |
| 1055 | if (args->size == 0) |
| 1056 | return 0; |
| 1057 | |
| 1058 | if (!access_ok(VERIFY_READ, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 1059 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1060 | args->size)) |
| 1061 | return -EFAULT; |
| 1062 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1063 | if (likely(!i915.prefault_disable)) { |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 1064 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 1065 | args->size); |
| 1066 | if (ret) |
| 1067 | return -EFAULT; |
| 1068 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1069 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1070 | ret = i915_mutex_lock_interruptible(dev); |
| 1071 | if (ret) |
| 1072 | return ret; |
| 1073 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1074 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1075 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1076 | ret = -ENOENT; |
| 1077 | goto unlock; |
| 1078 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1079 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1080 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1081 | if (args->offset > obj->base.size || |
| 1082 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1083 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1084 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1085 | } |
| 1086 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1087 | /* prime objects have no backing filp to GEM pread/pwrite |
| 1088 | * pages from. |
| 1089 | */ |
| 1090 | if (!obj->base.filp) { |
| 1091 | ret = -EINVAL; |
| 1092 | goto out; |
| 1093 | } |
| 1094 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1095 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 1096 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1097 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1098 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1099 | * it would end up going through the fenced access, and we'll get |
| 1100 | * different detiling behavior between reading and writing. |
| 1101 | * pread/pwrite currently are reading and writing from the CPU |
| 1102 | * perspective, requiring manual detiling by the client. |
| 1103 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1104 | if (obj->tiling_mode == I915_TILING_NONE && |
| 1105 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 1106 | cpu_write_needs_clflush(obj)) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1107 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1108 | /* Note that the gtt paths might fail with non-page-backed user |
| 1109 | * pointers (e.g. gtt mappings when moving data between |
| 1110 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1111 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1112 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 1113 | if (ret == -EFAULT || ret == -ENOSPC) { |
| 1114 | if (obj->phys_handle) |
| 1115 | ret = i915_gem_phys_pwrite(obj, args, file); |
| 1116 | else |
| 1117 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
| 1118 | } |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 1119 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1120 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1121 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1122 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1123 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1124 | return ret; |
| 1125 | } |
| 1126 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1127 | int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1128 | i915_gem_check_wedge(struct i915_gpu_error *error, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1129 | bool interruptible) |
| 1130 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1131 | if (i915_reset_in_progress(error)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1132 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1133 | * -EIO unconditionally for these. */ |
| 1134 | if (!interruptible) |
| 1135 | return -EIO; |
| 1136 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1137 | /* Recovery complete, but the reset failed ... */ |
| 1138 | if (i915_terminally_wedged(error)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1139 | return -EIO; |
| 1140 | |
McAulay, Alistair | 6689c16 | 2014-08-15 18:51:35 +0100 | [diff] [blame] | 1141 | /* |
| 1142 | * Check if GPU Reset is in progress - we need intel_ring_begin |
| 1143 | * to work properly to reinit the hw state while the gpu is |
| 1144 | * still marked as reset-in-progress. Handle this with a flag. |
| 1145 | */ |
| 1146 | if (!error->reload_in_reset) |
| 1147 | return -EAGAIN; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1148 | } |
| 1149 | |
| 1150 | return 0; |
| 1151 | } |
| 1152 | |
| 1153 | /* |
| 1154 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 1155 | * equal. |
| 1156 | */ |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 1157 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1158 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1159 | { |
| 1160 | int ret; |
| 1161 | |
| 1162 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 1163 | |
| 1164 | ret = 0; |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1165 | if (seqno == ring->outstanding_lazy_seqno) |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 1166 | ret = i915_add_request(ring, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1167 | |
| 1168 | return ret; |
| 1169 | } |
| 1170 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1171 | static void fake_irq(unsigned long data) |
| 1172 | { |
| 1173 | wake_up_process((struct task_struct *)data); |
| 1174 | } |
| 1175 | |
| 1176 | static bool missed_irq(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1177 | struct intel_engine_cs *ring) |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1178 | { |
| 1179 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); |
| 1180 | } |
| 1181 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1182 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
| 1183 | { |
| 1184 | if (file_priv == NULL) |
| 1185 | return true; |
| 1186 | |
| 1187 | return !atomic_xchg(&file_priv->rps_wait_boost, true); |
| 1188 | } |
| 1189 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1190 | /** |
Ander Conselvan de Oliveira | 16e9a21 | 2014-11-06 09:26:38 +0200 | [diff] [blame] | 1191 | * __i915_wait_seqno - wait until execution of seqno has finished |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1192 | * @ring: the ring expected to report seqno |
| 1193 | * @seqno: duh! |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1194 | * @reset_counter: reset sequence associated with the given seqno |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1195 | * @interruptible: do an interruptible wait (normally yes) |
| 1196 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1197 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1198 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1199 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1200 | * locks are involved, it is sufficient to read the reset_counter before |
| 1201 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1202 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1203 | * inserted. |
| 1204 | * |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1205 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 1206 | * errno with remaining time filled in timeout argument. |
| 1207 | */ |
Ander Conselvan de Oliveira | 16e9a21 | 2014-11-06 09:26:38 +0200 | [diff] [blame] | 1208 | int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1209 | unsigned reset_counter, |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1210 | bool interruptible, |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1211 | s64 *timeout, |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1212 | struct drm_i915_file_private *file_priv) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1213 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1214 | struct drm_device *dev = ring->dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 1215 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1216 | const bool irq_test_in_progress = |
| 1217 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1218 | DEFINE_WAIT(wait); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1219 | unsigned long timeout_expire; |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1220 | s64 before, now; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1221 | int ret; |
| 1222 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 1223 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1224 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1225 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
| 1226 | return 0; |
| 1227 | |
Daniel Vetter | 7bd0e22 | 2014-12-04 11:12:54 +0100 | [diff] [blame] | 1228 | timeout_expire = timeout ? |
| 1229 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1230 | |
Chris Wilson | ec5cc0f | 2014-06-12 10:28:55 +0100 | [diff] [blame] | 1231 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1232 | gen6_rps_boost(dev_priv); |
| 1233 | if (file_priv) |
| 1234 | mod_delayed_work(dev_priv->wq, |
| 1235 | &file_priv->mm.idle_work, |
| 1236 | msecs_to_jiffies(100)); |
| 1237 | } |
| 1238 | |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1239 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1240 | return -ENODEV; |
| 1241 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1242 | /* Record current time in case interrupted by signal, or wedged */ |
| 1243 | trace_i915_gem_request_wait_begin(ring, seqno); |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1244 | before = ktime_get_raw_ns(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1245 | for (;;) { |
| 1246 | struct timer_list timer; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1247 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1248 | prepare_to_wait(&ring->irq_queue, &wait, |
| 1249 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1250 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1251 | /* We need to check whether any gpu reset happened in between |
| 1252 | * the caller grabbing the seqno and now ... */ |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1253 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
| 1254 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu |
| 1255 | * is truely gone. */ |
| 1256 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
| 1257 | if (ret == 0) |
| 1258 | ret = -EAGAIN; |
| 1259 | break; |
| 1260 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1261 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1262 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
| 1263 | ret = 0; |
| 1264 | break; |
| 1265 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1266 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1267 | if (interruptible && signal_pending(current)) { |
| 1268 | ret = -ERESTARTSYS; |
| 1269 | break; |
| 1270 | } |
| 1271 | |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1272 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1273 | ret = -ETIME; |
| 1274 | break; |
| 1275 | } |
| 1276 | |
| 1277 | timer.function = NULL; |
| 1278 | if (timeout || missed_irq(dev_priv, ring)) { |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1279 | unsigned long expire; |
| 1280 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1281 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1282 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1283 | mod_timer(&timer, expire); |
| 1284 | } |
| 1285 | |
Chris Wilson | 5035c27 | 2013-10-04 09:58:46 +0100 | [diff] [blame] | 1286 | io_schedule(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1287 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1288 | if (timer.function) { |
| 1289 | del_singleshot_timer_sync(&timer); |
| 1290 | destroy_timer_on_stack(&timer); |
| 1291 | } |
| 1292 | } |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1293 | now = ktime_get_raw_ns(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1294 | trace_i915_gem_request_wait_end(ring, seqno); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1295 | |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1296 | if (!irq_test_in_progress) |
| 1297 | ring->irq_put(ring); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1298 | |
| 1299 | finish_wait(&ring->irq_queue, &wait); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1300 | |
| 1301 | if (timeout) { |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1302 | s64 tres = *timeout - (now - before); |
| 1303 | |
| 1304 | *timeout = tres < 0 ? 0 : tres; |
Daniel Vetter | 9cca306 | 2014-11-28 10:29:55 +0100 | [diff] [blame] | 1305 | |
| 1306 | /* |
| 1307 | * Apparently ktime isn't accurate enough and occasionally has a |
| 1308 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch |
| 1309 | * things up to make the test happy. We allow up to 1 jiffy. |
| 1310 | * |
| 1311 | * This is a regrssion from the timespec->ktime conversion. |
| 1312 | */ |
| 1313 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) |
| 1314 | *timeout = 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1315 | } |
| 1316 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1317 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1318 | } |
| 1319 | |
| 1320 | /** |
| 1321 | * Waits for a sequence number to be signaled, and cleans up the |
| 1322 | * request and object lists appropriately for that event. |
| 1323 | */ |
| 1324 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1325 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1326 | { |
| 1327 | struct drm_device *dev = ring->dev; |
| 1328 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1329 | bool interruptible = dev_priv->mm.interruptible; |
Ander Conselvan de Oliveira | 16e9a21 | 2014-11-06 09:26:38 +0200 | [diff] [blame] | 1330 | unsigned reset_counter; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1331 | int ret; |
| 1332 | |
| 1333 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1334 | BUG_ON(seqno == 0); |
| 1335 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1336 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1337 | if (ret) |
| 1338 | return ret; |
| 1339 | |
| 1340 | ret = i915_gem_check_olr(ring, seqno); |
| 1341 | if (ret) |
| 1342 | return ret; |
| 1343 | |
Ander Conselvan de Oliveira | 16e9a21 | 2014-11-06 09:26:38 +0200 | [diff] [blame] | 1344 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 1345 | return __i915_wait_seqno(ring, seqno, reset_counter, interruptible, |
| 1346 | NULL, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1347 | } |
| 1348 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1349 | static int |
John Harrison | 8e639549 | 2014-10-30 18:40:53 +0000 | [diff] [blame] | 1350 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1351 | { |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 1352 | if (!obj->active) |
| 1353 | return 0; |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1354 | |
| 1355 | /* Manually manage the write flush as we may have not yet |
| 1356 | * retired the buffer. |
| 1357 | * |
| 1358 | * Note that the last_write_seqno is always the earlier of |
| 1359 | * the two (read/write) seqno, so if we haved successfully waited, |
| 1360 | * we know we have passed the last write. |
| 1361 | */ |
| 1362 | obj->last_write_seqno = 0; |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1363 | |
| 1364 | return 0; |
| 1365 | } |
| 1366 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1367 | /** |
| 1368 | * Ensures that all rendering to the object has completed and the object is |
| 1369 | * safe to unbind from the GTT or access from the CPU. |
| 1370 | */ |
| 1371 | static __must_check int |
| 1372 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1373 | bool readonly) |
| 1374 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1375 | struct intel_engine_cs *ring = obj->ring; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1376 | u32 seqno; |
| 1377 | int ret; |
| 1378 | |
| 1379 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1380 | if (seqno == 0) |
| 1381 | return 0; |
| 1382 | |
| 1383 | ret = i915_wait_seqno(ring, seqno); |
| 1384 | if (ret) |
| 1385 | return ret; |
| 1386 | |
John Harrison | 8e639549 | 2014-10-30 18:40:53 +0000 | [diff] [blame] | 1387 | return i915_gem_object_wait_rendering__tail(obj); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1388 | } |
| 1389 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1390 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1391 | * as the object state may change during this call. |
| 1392 | */ |
| 1393 | static __must_check int |
| 1394 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1395 | struct drm_i915_file_private *file_priv, |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1396 | bool readonly) |
| 1397 | { |
| 1398 | struct drm_device *dev = obj->base.dev; |
| 1399 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1400 | struct intel_engine_cs *ring = obj->ring; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1401 | unsigned reset_counter; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1402 | u32 seqno; |
| 1403 | int ret; |
| 1404 | |
| 1405 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1406 | BUG_ON(!dev_priv->mm.interruptible); |
| 1407 | |
| 1408 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1409 | if (seqno == 0) |
| 1410 | return 0; |
| 1411 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1412 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1413 | if (ret) |
| 1414 | return ret; |
| 1415 | |
| 1416 | ret = i915_gem_check_olr(ring, seqno); |
| 1417 | if (ret) |
| 1418 | return ret; |
| 1419 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1420 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1421 | mutex_unlock(&dev->struct_mutex); |
Ander Conselvan de Oliveira | 16e9a21 | 2014-11-06 09:26:38 +0200 | [diff] [blame] | 1422 | ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, |
| 1423 | file_priv); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1424 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1425 | if (ret) |
| 1426 | return ret; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1427 | |
John Harrison | 8e639549 | 2014-10-30 18:40:53 +0000 | [diff] [blame] | 1428 | return i915_gem_object_wait_rendering__tail(obj); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1429 | } |
| 1430 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1431 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1432 | * Called when user space prepares to use an object with the CPU, either |
| 1433 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1434 | */ |
| 1435 | int |
| 1436 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1437 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1438 | { |
| 1439 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1440 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1441 | uint32_t read_domains = args->read_domains; |
| 1442 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1443 | int ret; |
| 1444 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1445 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1446 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1447 | return -EINVAL; |
| 1448 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1449 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1450 | return -EINVAL; |
| 1451 | |
| 1452 | /* Having something in the write domain implies it's in the read |
| 1453 | * domain, and only that read domain. Enforce that in the request. |
| 1454 | */ |
| 1455 | if (write_domain != 0 && read_domains != write_domain) |
| 1456 | return -EINVAL; |
| 1457 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1458 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1459 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1460 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1461 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1462 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1463 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1464 | ret = -ENOENT; |
| 1465 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1466 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1467 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1468 | /* Try to flush the object off the GPU without holding the lock. |
| 1469 | * We will repeat the flush holding the lock in the normal manner |
| 1470 | * to catch cases where we are gazumped. |
| 1471 | */ |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1472 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
| 1473 | file->driver_priv, |
| 1474 | !write_domain); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1475 | if (ret) |
| 1476 | goto unref; |
| 1477 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1478 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1479 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1480 | |
| 1481 | /* Silently promote "you're not bound, there was nothing to do" |
| 1482 | * to success, since the client was just asking us to |
| 1483 | * make sure everything was done. |
| 1484 | */ |
| 1485 | if (ret == -EINVAL) |
| 1486 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1487 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1488 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1489 | } |
| 1490 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1491 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1492 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1493 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1494 | mutex_unlock(&dev->struct_mutex); |
| 1495 | return ret; |
| 1496 | } |
| 1497 | |
| 1498 | /** |
| 1499 | * Called when user space has done writes to this buffer |
| 1500 | */ |
| 1501 | int |
| 1502 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1503 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1504 | { |
| 1505 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1506 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1507 | int ret = 0; |
| 1508 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1509 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1510 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1511 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1512 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1513 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1514 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1515 | ret = -ENOENT; |
| 1516 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1517 | } |
| 1518 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1519 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1520 | if (obj->pin_display) |
| 1521 | i915_gem_object_flush_cpu_write_domain(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1522 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1523 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1524 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1525 | mutex_unlock(&dev->struct_mutex); |
| 1526 | return ret; |
| 1527 | } |
| 1528 | |
| 1529 | /** |
| 1530 | * Maps the contents of an object, returning the address it is mapped |
| 1531 | * into. |
| 1532 | * |
| 1533 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1534 | * imply a ref on the object itself. |
Daniel Vetter | 3436738 | 2014-10-16 12:28:18 +0200 | [diff] [blame] | 1535 | * |
| 1536 | * IMPORTANT: |
| 1537 | * |
| 1538 | * DRM driver writers who look a this function as an example for how to do GEM |
| 1539 | * mmap support, please don't implement mmap support like here. The modern way |
| 1540 | * to implement DRM mmap support is with an mmap offset ioctl (like |
| 1541 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. |
| 1542 | * That way debug tooling like valgrind will understand what's going on, hiding |
| 1543 | * the mmap call in a driver private ioctl will break that. The i915 driver only |
| 1544 | * does cpu mmaps this way because we didn't know better. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1545 | */ |
| 1546 | int |
| 1547 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1548 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1549 | { |
| 1550 | struct drm_i915_gem_mmap *args = data; |
| 1551 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1552 | unsigned long addr; |
| 1553 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1554 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1555 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1556 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1557 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1558 | /* prime objects have no backing filp to GEM mmap |
| 1559 | * pages from. |
| 1560 | */ |
| 1561 | if (!obj->filp) { |
| 1562 | drm_gem_object_unreference_unlocked(obj); |
| 1563 | return -EINVAL; |
| 1564 | } |
| 1565 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1566 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1567 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1568 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1569 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1570 | if (IS_ERR((void *)addr)) |
| 1571 | return addr; |
| 1572 | |
| 1573 | args->addr_ptr = (uint64_t) addr; |
| 1574 | |
| 1575 | return 0; |
| 1576 | } |
| 1577 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1578 | /** |
| 1579 | * i915_gem_fault - fault a page into the GTT |
| 1580 | * vma: VMA in question |
| 1581 | * vmf: fault info |
| 1582 | * |
| 1583 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1584 | * from userspace. The fault handler takes care of binding the object to |
| 1585 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1586 | * only if needed based on whether the old reg is still valid or the object |
| 1587 | * is tiled) and inserting a new PTE into the faulting process. |
| 1588 | * |
| 1589 | * Note that the faulting process may involve evicting existing objects |
| 1590 | * from the GTT and/or fence registers to make room. So performance may |
| 1591 | * suffer if the GTT working set is large or there are few fence registers |
| 1592 | * left. |
| 1593 | */ |
| 1594 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1595 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1596 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1597 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 1598 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1599 | pgoff_t page_offset; |
| 1600 | unsigned long pfn; |
| 1601 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1602 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1603 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1604 | intel_runtime_pm_get(dev_priv); |
| 1605 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1606 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1607 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1608 | PAGE_SHIFT; |
| 1609 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1610 | ret = i915_mutex_lock_interruptible(dev); |
| 1611 | if (ret) |
| 1612 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1613 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1614 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1615 | |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1616 | /* Try to flush the object off the GPU first without holding the lock. |
| 1617 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1618 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1619 | * where we are gazumped. |
| 1620 | */ |
| 1621 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1622 | if (ret) |
| 1623 | goto unlock; |
| 1624 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1625 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1626 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
Chris Wilson | ddeff6e | 2014-05-28 16:16:41 +0100 | [diff] [blame] | 1627 | ret = -EFAULT; |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1628 | goto unlock; |
| 1629 | } |
| 1630 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1631 | /* Now bind it into the GTT if needed */ |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 1632 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1633 | if (ret) |
| 1634 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1635 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1636 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1637 | if (ret) |
| 1638 | goto unpin; |
| 1639 | |
| 1640 | ret = i915_gem_object_get_fence(obj); |
| 1641 | if (ret) |
| 1642 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1643 | |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1644 | /* Finally, remap it using the new GTT offset */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1645 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
| 1646 | pfn >>= PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1647 | |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1648 | if (!obj->fault_mappable) { |
Ville Syrjälä | beff0d0 | 2014-06-17 21:03:00 +0300 | [diff] [blame] | 1649 | unsigned long size = min_t(unsigned long, |
| 1650 | vma->vm_end - vma->vm_start, |
| 1651 | obj->base.size); |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1652 | int i; |
| 1653 | |
Ville Syrjälä | beff0d0 | 2014-06-17 21:03:00 +0300 | [diff] [blame] | 1654 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1655 | ret = vm_insert_pfn(vma, |
| 1656 | (unsigned long)vma->vm_start + i * PAGE_SIZE, |
| 1657 | pfn + i); |
| 1658 | if (ret) |
| 1659 | break; |
| 1660 | } |
| 1661 | |
| 1662 | obj->fault_mappable = true; |
| 1663 | } else |
| 1664 | ret = vm_insert_pfn(vma, |
| 1665 | (unsigned long)vmf->virtual_address, |
| 1666 | pfn + page_offset); |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1667 | unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1668 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1669 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1670 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1671 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1672 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1673 | case -EIO: |
Daniel Vetter | 2232f03 | 2014-09-04 09:36:18 +0200 | [diff] [blame] | 1674 | /* |
| 1675 | * We eat errors when the gpu is terminally wedged to avoid |
| 1676 | * userspace unduly crashing (gl has no provisions for mmaps to |
| 1677 | * fail). But any other -EIO isn't ours (e.g. swap in failure) |
| 1678 | * and so needs to be reported. |
| 1679 | */ |
| 1680 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1681 | ret = VM_FAULT_SIGBUS; |
| 1682 | break; |
| 1683 | } |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1684 | case -EAGAIN: |
Daniel Vetter | 571c608 | 2013-09-12 17:57:28 +0200 | [diff] [blame] | 1685 | /* |
| 1686 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1687 | * handler to reset everything when re-faulting in |
| 1688 | * i915_mutex_lock_interruptible. |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1689 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1690 | case 0: |
| 1691 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1692 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1693 | case -EBUSY: |
| 1694 | /* |
| 1695 | * EBUSY is ok: this just means that another thread |
| 1696 | * already did the job. |
| 1697 | */ |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1698 | ret = VM_FAULT_NOPAGE; |
| 1699 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1700 | case -ENOMEM: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1701 | ret = VM_FAULT_OOM; |
| 1702 | break; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1703 | case -ENOSPC: |
Chris Wilson | 45d6781 | 2014-01-31 11:34:57 +0000 | [diff] [blame] | 1704 | case -EFAULT: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1705 | ret = VM_FAULT_SIGBUS; |
| 1706 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1707 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1708 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1709 | ret = VM_FAULT_SIGBUS; |
| 1710 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1711 | } |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1712 | |
| 1713 | intel_runtime_pm_put(dev_priv); |
| 1714 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1715 | } |
| 1716 | |
| 1717 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1718 | * i915_gem_release_mmap - remove physical page mappings |
| 1719 | * @obj: obj in question |
| 1720 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1721 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1722 | * relinquish ownership of the pages back to the system. |
| 1723 | * |
| 1724 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1725 | * object through the GTT and then lose the fence register due to |
| 1726 | * resource pressure. Similarly if the object has been moved out of the |
| 1727 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1728 | * mapping will then trigger a page fault on the next user access, allowing |
| 1729 | * fixup by i915_gem_fault(). |
| 1730 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1731 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1732 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1733 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1734 | if (!obj->fault_mappable) |
| 1735 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1736 | |
David Herrmann | 6796cb1 | 2014-01-03 14:24:19 +0100 | [diff] [blame] | 1737 | drm_vma_node_unmap(&obj->base.vma_node, |
| 1738 | obj->base.dev->anon_inode->i_mapping); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1739 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1740 | } |
| 1741 | |
Chris Wilson | eedd10f | 2014-06-16 08:57:44 +0100 | [diff] [blame] | 1742 | void |
| 1743 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 1744 | { |
| 1745 | struct drm_i915_gem_object *obj; |
| 1746 | |
| 1747 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 1748 | i915_gem_release_mmap(obj); |
| 1749 | } |
| 1750 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 1751 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1752 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1753 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1754 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1755 | |
| 1756 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1757 | tiling_mode == I915_TILING_NONE) |
| 1758 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1759 | |
| 1760 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1761 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1762 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1763 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1764 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1765 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1766 | while (gtt_size < size) |
| 1767 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1768 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1769 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1770 | } |
| 1771 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1772 | /** |
| 1773 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1774 | * @obj: object to check |
| 1775 | * |
| 1776 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1777 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1778 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1779 | uint32_t |
| 1780 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1781 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1782 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1783 | /* |
| 1784 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1785 | * if a fence register is needed for the object. |
| 1786 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1787 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1788 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1789 | return 4096; |
| 1790 | |
| 1791 | /* |
| 1792 | * Previous chips need to be aligned to the size of the smallest |
| 1793 | * fence register that can contain the object. |
| 1794 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1795 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1796 | } |
| 1797 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1798 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1799 | { |
| 1800 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1801 | int ret; |
| 1802 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1803 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1804 | return 0; |
| 1805 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1806 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1807 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1808 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1809 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1810 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1811 | |
| 1812 | /* Badly fragmented mmap space? The only way we can recover |
| 1813 | * space is by destroying unwanted objects. We can't randomly release |
| 1814 | * mmap_offsets as userspace expects them to be persistent for the |
| 1815 | * lifetime of the objects. The closest we can is to release the |
| 1816 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1817 | * which prevents userspace from ever using that object again. |
| 1818 | */ |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 1819 | i915_gem_shrink(dev_priv, |
| 1820 | obj->base.size >> PAGE_SHIFT, |
| 1821 | I915_SHRINK_BOUND | |
| 1822 | I915_SHRINK_UNBOUND | |
| 1823 | I915_SHRINK_PURGEABLE); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1824 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1825 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1826 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1827 | |
| 1828 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1829 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1830 | out: |
| 1831 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 1832 | |
| 1833 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1834 | } |
| 1835 | |
| 1836 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 1837 | { |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1838 | drm_gem_free_mmap_offset(&obj->base); |
| 1839 | } |
| 1840 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame^] | 1841 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1842 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1843 | struct drm_device *dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame^] | 1844 | uint32_t handle, |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1845 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1846 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1847 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1848 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1849 | int ret; |
| 1850 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1851 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1852 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1853 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1854 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1855 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1856 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1857 | ret = -ENOENT; |
| 1858 | goto unlock; |
| 1859 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1860 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1861 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1862 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1863 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1864 | } |
| 1865 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1866 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 1867 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 1868 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1869 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1870 | } |
| 1871 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1872 | ret = i915_gem_object_create_mmap_offset(obj); |
| 1873 | if (ret) |
| 1874 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1875 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1876 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1877 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1878 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1879 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1880 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1881 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1882 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1883 | } |
| 1884 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1885 | /** |
| 1886 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1887 | * @dev: DRM device |
| 1888 | * @data: GTT mapping ioctl data |
| 1889 | * @file: GEM object info |
| 1890 | * |
| 1891 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1892 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1893 | * up so we can get faults in the handler above. |
| 1894 | * |
| 1895 | * The fault handler will take care of binding the object into the GTT |
| 1896 | * (since it may have been evicted to make room for something), allocating |
| 1897 | * a fence register, and mapping the appropriate aperture address into |
| 1898 | * userspace. |
| 1899 | */ |
| 1900 | int |
| 1901 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1902 | struct drm_file *file) |
| 1903 | { |
| 1904 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1905 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame^] | 1906 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1907 | } |
| 1908 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1909 | static inline int |
| 1910 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
| 1911 | { |
| 1912 | return obj->madv == I915_MADV_DONTNEED; |
| 1913 | } |
| 1914 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1915 | /* Immediately discard the backing storage */ |
| 1916 | static void |
| 1917 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1918 | { |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1919 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1920 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1921 | if (obj->base.filp == NULL) |
| 1922 | return; |
| 1923 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1924 | /* Our goal here is to return as much of the memory as |
| 1925 | * is possible back to the system as we are called from OOM. |
| 1926 | * To do this we must instruct the shmfs to drop all of its |
| 1927 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1928 | */ |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1929 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1930 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1931 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1932 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1933 | /* Try to discard unwanted pages */ |
| 1934 | static void |
| 1935 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1936 | { |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 1937 | struct address_space *mapping; |
| 1938 | |
| 1939 | switch (obj->madv) { |
| 1940 | case I915_MADV_DONTNEED: |
| 1941 | i915_gem_object_truncate(obj); |
| 1942 | case __I915_MADV_PURGED: |
| 1943 | return; |
| 1944 | } |
| 1945 | |
| 1946 | if (obj->base.filp == NULL) |
| 1947 | return; |
| 1948 | |
| 1949 | mapping = file_inode(obj->base.filp)->i_mapping, |
| 1950 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1951 | } |
| 1952 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1953 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1954 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1955 | { |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1956 | struct sg_page_iter sg_iter; |
| 1957 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1958 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1959 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1960 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1961 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 1962 | if (ret) { |
| 1963 | /* In the event of a disaster, abandon all caches and |
| 1964 | * hope for the best. |
| 1965 | */ |
| 1966 | WARN_ON(ret != -EIO); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1967 | i915_gem_clflush_object(obj, true); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1968 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 1969 | } |
| 1970 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1971 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1972 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1973 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1974 | if (obj->madv == I915_MADV_DONTNEED) |
| 1975 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1976 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1977 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1978 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1979 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1980 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1981 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1982 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1983 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1984 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1985 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1986 | page_cache_release(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1987 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1988 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1989 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1990 | sg_free_table(obj->pages); |
| 1991 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1992 | } |
| 1993 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1994 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1995 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 1996 | { |
| 1997 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1998 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1999 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2000 | return 0; |
| 2001 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2002 | if (obj->pages_pin_count) |
| 2003 | return -EBUSY; |
| 2004 | |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 2005 | BUG_ON(i915_gem_obj_bound_any(obj)); |
Ben Widawsky | 3e12302 | 2013-07-31 17:00:04 -0700 | [diff] [blame] | 2006 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 2007 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 2008 | * array, hence protect them from being reaped by removing them from gtt |
| 2009 | * lists early. */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2010 | list_del(&obj->global_list); |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 2011 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2012 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2013 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2014 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2015 | i915_gem_object_invalidate(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2016 | |
| 2017 | return 0; |
| 2018 | } |
| 2019 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2020 | unsigned long |
| 2021 | i915_gem_shrink(struct drm_i915_private *dev_priv, |
| 2022 | long target, unsigned flags) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2023 | { |
Chris Wilson | 60a5372 | 2014-10-03 10:29:51 +0100 | [diff] [blame] | 2024 | const struct { |
| 2025 | struct list_head *list; |
| 2026 | unsigned int bit; |
| 2027 | } phases[] = { |
| 2028 | { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND }, |
| 2029 | { &dev_priv->mm.bound_list, I915_SHRINK_BOUND }, |
| 2030 | { NULL, 0 }, |
| 2031 | }, *phase; |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 2032 | unsigned long count = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2033 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 2034 | /* |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2035 | * As we may completely rewrite the (un)bound list whilst unbinding |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 2036 | * (due to retiring requests) we have to strictly process only |
| 2037 | * one element of the list at the time, and recheck the list |
| 2038 | * on every iteration. |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2039 | * |
| 2040 | * In particular, we must hold a reference whilst removing the |
| 2041 | * object as we may end up waiting for and/or retiring the objects. |
| 2042 | * This might release the final reference (held by the active list) |
| 2043 | * and result in the object being freed from under us. This is |
| 2044 | * similar to the precautions the eviction code must take whilst |
| 2045 | * removing objects. |
| 2046 | * |
| 2047 | * Also note that although these lists do not hold a reference to |
| 2048 | * the object we can safely grab one here: The final object |
| 2049 | * unreferencing and the bound_list are both protected by the |
| 2050 | * dev->struct_mutex and so we won't ever be able to observe an |
| 2051 | * object on the bound_list with a reference count equals 0. |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 2052 | */ |
Chris Wilson | 60a5372 | 2014-10-03 10:29:51 +0100 | [diff] [blame] | 2053 | for (phase = phases; phase->list; phase++) { |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2054 | struct list_head still_in_list; |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2055 | |
Chris Wilson | 60a5372 | 2014-10-03 10:29:51 +0100 | [diff] [blame] | 2056 | if ((flags & phase->bit) == 0) |
| 2057 | continue; |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 2058 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2059 | INIT_LIST_HEAD(&still_in_list); |
Chris Wilson | 60a5372 | 2014-10-03 10:29:51 +0100 | [diff] [blame] | 2060 | while (count < target && !list_empty(phase->list)) { |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2061 | struct drm_i915_gem_object *obj; |
| 2062 | struct i915_vma *vma, *v; |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 2063 | |
Chris Wilson | 60a5372 | 2014-10-03 10:29:51 +0100 | [diff] [blame] | 2064 | obj = list_first_entry(phase->list, |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2065 | typeof(*obj), global_list); |
| 2066 | list_move_tail(&obj->global_list, &still_in_list); |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 2067 | |
Chris Wilson | 60a5372 | 2014-10-03 10:29:51 +0100 | [diff] [blame] | 2068 | if (flags & I915_SHRINK_PURGEABLE && |
| 2069 | !i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2070 | continue; |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 2071 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2072 | drm_gem_object_reference(&obj->base); |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 2073 | |
Chris Wilson | 60a5372 | 2014-10-03 10:29:51 +0100 | [diff] [blame] | 2074 | /* For the unbound phase, this should be a no-op! */ |
| 2075 | list_for_each_entry_safe(vma, v, |
| 2076 | &obj->vma_list, vma_link) |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2077 | if (i915_vma_unbind(vma)) |
| 2078 | break; |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 2079 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2080 | if (i915_gem_object_put_pages(obj) == 0) |
| 2081 | count += obj->base.size >> PAGE_SHIFT; |
| 2082 | |
| 2083 | drm_gem_object_unreference(&obj->base); |
| 2084 | } |
Chris Wilson | 60a5372 | 2014-10-03 10:29:51 +0100 | [diff] [blame] | 2085 | list_splice(&still_in_list, phase->list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2086 | } |
| 2087 | |
| 2088 | return count; |
| 2089 | } |
| 2090 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 2091 | static unsigned long |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2092 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
| 2093 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2094 | i915_gem_evict_everything(dev_priv->dev); |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2095 | return i915_gem_shrink(dev_priv, LONG_MAX, |
| 2096 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2097 | } |
| 2098 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2099 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2100 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2101 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2102 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2103 | int page_count, i; |
| 2104 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2105 | struct sg_table *st; |
| 2106 | struct scatterlist *sg; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2107 | struct sg_page_iter sg_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2108 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2109 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2110 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2111 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2112 | /* Assert that the object is not currently in any GPU domain. As it |
| 2113 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2114 | * a GPU cache |
| 2115 | */ |
| 2116 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2117 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 2118 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2119 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2120 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2121 | return -ENOMEM; |
| 2122 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2123 | page_count = obj->base.size / PAGE_SIZE; |
| 2124 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2125 | kfree(st); |
| 2126 | return -ENOMEM; |
| 2127 | } |
| 2128 | |
| 2129 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2130 | * at this point until we release them. |
| 2131 | * |
| 2132 | * Fail silently without starting the shrinker |
| 2133 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 2134 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2135 | gfp = mapping_gfp_mask(mapping); |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 2136 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2137 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2138 | sg = st->sgl; |
| 2139 | st->nents = 0; |
| 2140 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2141 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2142 | if (IS_ERR(page)) { |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2143 | i915_gem_shrink(dev_priv, |
| 2144 | page_count, |
| 2145 | I915_SHRINK_BOUND | |
| 2146 | I915_SHRINK_UNBOUND | |
| 2147 | I915_SHRINK_PURGEABLE); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2148 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2149 | } |
| 2150 | if (IS_ERR(page)) { |
| 2151 | /* We've tried hard to allocate the memory by reaping |
| 2152 | * our own buffer, now let the real VM do its job and |
| 2153 | * go down in flames if truly OOM. |
| 2154 | */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2155 | i915_gem_shrink_all(dev_priv); |
David Herrmann | f461d1b | 2014-05-25 14:34:10 +0200 | [diff] [blame] | 2156 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2157 | if (IS_ERR(page)) |
| 2158 | goto err_pages; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2159 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2160 | #ifdef CONFIG_SWIOTLB |
| 2161 | if (swiotlb_nr_tbl()) { |
| 2162 | st->nents++; |
| 2163 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2164 | sg = sg_next(sg); |
| 2165 | continue; |
| 2166 | } |
| 2167 | #endif |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2168 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 2169 | if (i) |
| 2170 | sg = sg_next(sg); |
| 2171 | st->nents++; |
| 2172 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2173 | } else { |
| 2174 | sg->length += PAGE_SIZE; |
| 2175 | } |
| 2176 | last_pfn = page_to_pfn(page); |
Daniel Vetter | 3bbbe70 | 2013-10-07 17:15:45 -0300 | [diff] [blame] | 2177 | |
| 2178 | /* Check that the i965g/gm workaround works. */ |
| 2179 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2180 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2181 | #ifdef CONFIG_SWIOTLB |
| 2182 | if (!swiotlb_nr_tbl()) |
| 2183 | #endif |
| 2184 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 2185 | obj->pages = st; |
| 2186 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2187 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2188 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2189 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2190 | if (obj->tiling_mode != I915_TILING_NONE && |
| 2191 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2192 | i915_gem_object_pin_pages(obj); |
| 2193 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2194 | return 0; |
| 2195 | |
| 2196 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2197 | sg_mark_end(sg); |
| 2198 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 2199 | page_cache_release(sg_page_iter_page(&sg_iter)); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2200 | sg_free_table(st); |
| 2201 | kfree(st); |
Chris Wilson | 0820baf | 2014-03-25 13:23:03 +0000 | [diff] [blame] | 2202 | |
| 2203 | /* shmemfs first checks if there is enough memory to allocate the page |
| 2204 | * and reports ENOSPC should there be insufficient, along with the usual |
| 2205 | * ENOMEM for a genuine allocation failure. |
| 2206 | * |
| 2207 | * We use ENOSPC in our driver to mean that we have run out of aperture |
| 2208 | * space and so want to translate the error from shmemfs back to our |
| 2209 | * usual understanding of ENOMEM. |
| 2210 | */ |
| 2211 | if (PTR_ERR(page) == -ENOSPC) |
| 2212 | return -ENOMEM; |
| 2213 | else |
| 2214 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2215 | } |
| 2216 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2217 | /* Ensure that the associated pages are gathered from the backing storage |
| 2218 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 2219 | * multiple times before they are released by a single call to |
| 2220 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 2221 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 2222 | * or as the object is itself released. |
| 2223 | */ |
| 2224 | int |
| 2225 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 2226 | { |
| 2227 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2228 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2229 | int ret; |
| 2230 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 2231 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2232 | return 0; |
| 2233 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2234 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 2235 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 2236 | return -EFAULT; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2237 | } |
| 2238 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2239 | BUG_ON(obj->pages_pin_count); |
| 2240 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2241 | ret = ops->get_pages(obj); |
| 2242 | if (ret) |
| 2243 | return ret; |
| 2244 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2245 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2246 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2247 | } |
| 2248 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2249 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2250 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2251 | struct intel_engine_cs *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2252 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2253 | u32 seqno = intel_ring_get_seqno(ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 2254 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2255 | BUG_ON(ring == NULL); |
Chris Wilson | 02978ff | 2013-07-09 09:22:39 +0100 | [diff] [blame] | 2256 | if (obj->ring != ring && obj->last_write_seqno) { |
| 2257 | /* Keep the seqno relative to the current ring */ |
| 2258 | obj->last_write_seqno = seqno; |
| 2259 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2260 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2261 | |
| 2262 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2263 | if (!obj->active) { |
| 2264 | drm_gem_object_reference(&obj->base); |
| 2265 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2266 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2267 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2268 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2269 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2270 | obj->last_read_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2271 | } |
| 2272 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2273 | void i915_vma_move_to_active(struct i915_vma *vma, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2274 | struct intel_engine_cs *ring) |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2275 | { |
| 2276 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
| 2277 | return i915_gem_object_move_to_active(vma->obj, ring); |
| 2278 | } |
| 2279 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2280 | static void |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2281 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 2282 | { |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 2283 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2284 | struct i915_address_space *vm; |
| 2285 | struct i915_vma *vma; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2286 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2287 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2288 | BUG_ON(!obj->active); |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2289 | |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2290 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 2291 | vma = i915_gem_obj_to_vma(obj, vm); |
| 2292 | if (vma && !list_empty(&vma->mm_list)) |
| 2293 | list_move_tail(&vma->mm_list, &vm->inactive_list); |
| 2294 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2295 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 2296 | intel_fb_obj_flush(obj, true); |
| 2297 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2298 | list_del_init(&obj->ring_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2299 | obj->ring = NULL; |
| 2300 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2301 | obj->last_read_seqno = 0; |
| 2302 | obj->last_write_seqno = 0; |
| 2303 | obj->base.write_domain = 0; |
| 2304 | |
| 2305 | obj->last_fenced_seqno = 0; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2306 | |
| 2307 | obj->active = 0; |
| 2308 | drm_gem_object_unreference(&obj->base); |
| 2309 | |
| 2310 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 2311 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2312 | |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2313 | static void |
| 2314 | i915_gem_object_retire(struct drm_i915_gem_object *obj) |
| 2315 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2316 | struct intel_engine_cs *ring = obj->ring; |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2317 | |
| 2318 | if (ring == NULL) |
| 2319 | return; |
| 2320 | |
| 2321 | if (i915_seqno_passed(ring->get_seqno(ring, true), |
| 2322 | obj->last_read_seqno)) |
| 2323 | i915_gem_object_move_to_inactive(obj); |
| 2324 | } |
| 2325 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2326 | static int |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2327 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2328 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2329 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2330 | struct intel_engine_cs *ring; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2331 | int ret, i, j; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2332 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2333 | /* Carefully retire all requests without writing to the rings */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2334 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2335 | ret = intel_ring_idle(ring); |
| 2336 | if (ret) |
| 2337 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2338 | } |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2339 | i915_gem_retire_requests(dev); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2340 | |
| 2341 | /* Finally reset hw state */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2342 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2343 | intel_ring_init_seqno(ring, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2344 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2345 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
| 2346 | ring->semaphore.sync_seqno[j] = 0; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2347 | } |
| 2348 | |
| 2349 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2350 | } |
| 2351 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2352 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2353 | { |
| 2354 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2355 | int ret; |
| 2356 | |
| 2357 | if (seqno == 0) |
| 2358 | return -EINVAL; |
| 2359 | |
| 2360 | /* HWS page needs to be set less than what we |
| 2361 | * will inject to ring |
| 2362 | */ |
| 2363 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 2364 | if (ret) |
| 2365 | return ret; |
| 2366 | |
| 2367 | /* Carefully set the last_seqno value so that wrap |
| 2368 | * detection still works |
| 2369 | */ |
| 2370 | dev_priv->next_seqno = seqno; |
| 2371 | dev_priv->last_seqno = seqno - 1; |
| 2372 | if (dev_priv->last_seqno == 0) |
| 2373 | dev_priv->last_seqno--; |
| 2374 | |
| 2375 | return 0; |
| 2376 | } |
| 2377 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2378 | int |
| 2379 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2380 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2381 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2382 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2383 | /* reserve 0 for non-seqno */ |
| 2384 | if (dev_priv->next_seqno == 0) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2385 | int ret = i915_gem_init_seqno(dev, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2386 | if (ret) |
| 2387 | return ret; |
| 2388 | |
| 2389 | dev_priv->next_seqno = 1; |
| 2390 | } |
| 2391 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 2392 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2393 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2394 | } |
| 2395 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2396 | int __i915_add_request(struct intel_engine_cs *ring, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2397 | struct drm_file *file, |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2398 | struct drm_i915_gem_object *obj, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2399 | u32 *out_seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2400 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2401 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2402 | struct drm_i915_gem_request *request; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2403 | struct intel_ringbuffer *ringbuf; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2404 | u32 request_ring_position, request_start; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2405 | int ret; |
| 2406 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2407 | request = ring->preallocated_lazy_request; |
| 2408 | if (WARN_ON(request == NULL)) |
| 2409 | return -ENOMEM; |
| 2410 | |
| 2411 | if (i915.enable_execlists) { |
| 2412 | struct intel_context *ctx = request->ctx; |
| 2413 | ringbuf = ctx->engine[ring->id].ringbuf; |
| 2414 | } else |
| 2415 | ringbuf = ring->buffer; |
| 2416 | |
| 2417 | request_start = intel_ring_get_tail(ringbuf); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2418 | /* |
| 2419 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2420 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2421 | * things up similar to emitting the lazy request. The difference here |
| 2422 | * is that the flush _must_ happen before the next request, no matter |
| 2423 | * what. |
| 2424 | */ |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2425 | if (i915.enable_execlists) { |
| 2426 | ret = logical_ring_flush_all_caches(ringbuf); |
| 2427 | if (ret) |
| 2428 | return ret; |
| 2429 | } else { |
| 2430 | ret = intel_ring_flush_all_caches(ring); |
| 2431 | if (ret) |
| 2432 | return ret; |
| 2433 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2434 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2435 | /* Record the position of the start of the request so that |
| 2436 | * should we detect the updated seqno part-way through the |
| 2437 | * GPU processing the request, we never over-estimate the |
| 2438 | * position of the head. |
| 2439 | */ |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2440 | request_ring_position = intel_ring_get_tail(ringbuf); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2441 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2442 | if (i915.enable_execlists) { |
| 2443 | ret = ring->emit_request(ringbuf); |
| 2444 | if (ret) |
| 2445 | return ret; |
| 2446 | } else { |
| 2447 | ret = ring->add_request(ring); |
| 2448 | if (ret) |
| 2449 | return ret; |
| 2450 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2451 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2452 | request->seqno = intel_ring_get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2453 | request->ring = ring; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2454 | request->head = request_start; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2455 | request->tail = request_ring_position; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2456 | |
| 2457 | /* Whilst this request exists, batch_obj will be on the |
| 2458 | * active_list, and so will hold the active reference. Only when this |
| 2459 | * request is retired will the the batch_obj be moved onto the |
| 2460 | * inactive_list and lose its active reference. Hence we do not need |
| 2461 | * to explicitly hold another reference here. |
| 2462 | */ |
Chris Wilson | 9a7e0c2 | 2013-08-26 19:50:54 -0300 | [diff] [blame] | 2463 | request->batch_obj = obj; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2464 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2465 | if (!i915.enable_execlists) { |
| 2466 | /* Hold a reference to the current context so that we can inspect |
| 2467 | * it later in case a hangcheck error event fires. |
| 2468 | */ |
| 2469 | request->ctx = ring->last_context; |
| 2470 | if (request->ctx) |
| 2471 | i915_gem_context_reference(request->ctx); |
| 2472 | } |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2473 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2474 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2475 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2476 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2477 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2478 | if (file) { |
| 2479 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2480 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2481 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2482 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2483 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2484 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2485 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2486 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2487 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2488 | trace_i915_gem_request_add(ring, request->seqno); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2489 | ring->outstanding_lazy_seqno = 0; |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2490 | ring->preallocated_lazy_request = NULL; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2491 | |
Daniel Vetter | 8725548 | 2014-11-19 20:36:48 +0100 | [diff] [blame] | 2492 | i915_queue_hangcheck(ring->dev); |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2493 | |
Daniel Vetter | 8725548 | 2014-11-19 20:36:48 +0100 | [diff] [blame] | 2494 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
| 2495 | queue_delayed_work(dev_priv->wq, |
| 2496 | &dev_priv->mm.retire_work, |
| 2497 | round_jiffies_up_relative(HZ)); |
| 2498 | intel_mark_busy(dev_priv->dev); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2499 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2500 | if (out_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2501 | *out_seqno = request->seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2502 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2503 | } |
| 2504 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2505 | static inline void |
| 2506 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2507 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2508 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2509 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2510 | if (!file_priv) |
| 2511 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2512 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2513 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2514 | list_del(&request->client_list); |
| 2515 | request->file_priv = NULL; |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2516 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2517 | } |
| 2518 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2519 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2520 | const struct intel_context *ctx) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2521 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2522 | unsigned long elapsed; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2523 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2524 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2525 | |
| 2526 | if (ctx->hang_stats.banned) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2527 | return true; |
| 2528 | |
| 2529 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2530 | if (!i915_gem_context_is_default(ctx)) { |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2531 | DRM_DEBUG("context hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2532 | return true; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 2533 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
| 2534 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 2535 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2536 | return true; |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2537 | } |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2538 | } |
| 2539 | |
| 2540 | return false; |
| 2541 | } |
| 2542 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2543 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2544 | struct intel_context *ctx, |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2545 | const bool guilty) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2546 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2547 | struct i915_ctx_hang_stats *hs; |
| 2548 | |
| 2549 | if (WARN_ON(!ctx)) |
| 2550 | return; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2551 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2552 | hs = &ctx->hang_stats; |
| 2553 | |
| 2554 | if (guilty) { |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2555 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2556 | hs->batch_active++; |
| 2557 | hs->guilty_ts = get_seconds(); |
| 2558 | } else { |
| 2559 | hs->batch_pending++; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2560 | } |
| 2561 | } |
| 2562 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2563 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
| 2564 | { |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2565 | struct intel_context *ctx = request->ctx; |
| 2566 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2567 | list_del(&request->list); |
| 2568 | i915_gem_request_remove_from_client(request); |
| 2569 | |
Thomas Daniel | 0794aed | 2014-11-25 10:39:25 +0000 | [diff] [blame] | 2570 | if (ctx) { |
| 2571 | if (i915.enable_execlists) { |
| 2572 | struct intel_engine_cs *ring = request->ring; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2573 | |
Thomas Daniel | 0794aed | 2014-11-25 10:39:25 +0000 | [diff] [blame] | 2574 | if (ctx != ring->default_context) |
| 2575 | intel_lr_context_unpin(ring, ctx); |
| 2576 | } |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2577 | i915_gem_context_unreference(ctx); |
| 2578 | } |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2579 | kfree(request); |
| 2580 | } |
| 2581 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2582 | struct drm_i915_gem_request * |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2583 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2584 | { |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2585 | struct drm_i915_gem_request *request; |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2586 | u32 completed_seqno; |
| 2587 | |
| 2588 | completed_seqno = ring->get_seqno(ring, false); |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2589 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2590 | list_for_each_entry(request, &ring->request_list, list) { |
| 2591 | if (i915_seqno_passed(completed_seqno, request->seqno)) |
| 2592 | continue; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2593 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2594 | return request; |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2595 | } |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2596 | |
| 2597 | return NULL; |
| 2598 | } |
| 2599 | |
| 2600 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2601 | struct intel_engine_cs *ring) |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2602 | { |
| 2603 | struct drm_i915_gem_request *request; |
| 2604 | bool ring_hung; |
| 2605 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2606 | request = i915_gem_find_active_request(ring); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2607 | |
| 2608 | if (request == NULL) |
| 2609 | return; |
| 2610 | |
| 2611 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
| 2612 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2613 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2614 | |
| 2615 | list_for_each_entry_continue(request, &ring->request_list, list) |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2616 | i915_set_reset_status(dev_priv, request->ctx, false); |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2617 | } |
| 2618 | |
| 2619 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2620 | struct intel_engine_cs *ring) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2621 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2622 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2623 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2624 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2625 | obj = list_first_entry(&ring->active_list, |
| 2626 | struct drm_i915_gem_object, |
| 2627 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2628 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2629 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2630 | } |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2631 | |
| 2632 | /* |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2633 | * Clear the execlists queue up before freeing the requests, as those |
| 2634 | * are the ones that keep the context and ringbuffer backing objects |
| 2635 | * pinned in place. |
| 2636 | */ |
| 2637 | while (!list_empty(&ring->execlist_queue)) { |
| 2638 | struct intel_ctx_submit_request *submit_req; |
| 2639 | |
| 2640 | submit_req = list_first_entry(&ring->execlist_queue, |
| 2641 | struct intel_ctx_submit_request, |
| 2642 | execlist_link); |
| 2643 | list_del(&submit_req->execlist_link); |
| 2644 | intel_runtime_pm_put(dev_priv); |
| 2645 | i915_gem_context_unreference(submit_req->ctx); |
| 2646 | kfree(submit_req); |
| 2647 | } |
| 2648 | |
| 2649 | /* |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2650 | * We must free the requests after all the corresponding objects have |
| 2651 | * been moved off active lists. Which is the same order as the normal |
| 2652 | * retire_requests function does. This is important if object hold |
| 2653 | * implicit references on things like e.g. ppgtt address spaces through |
| 2654 | * the request. |
| 2655 | */ |
| 2656 | while (!list_empty(&ring->request_list)) { |
| 2657 | struct drm_i915_gem_request *request; |
| 2658 | |
| 2659 | request = list_first_entry(&ring->request_list, |
| 2660 | struct drm_i915_gem_request, |
| 2661 | list); |
| 2662 | |
| 2663 | i915_gem_free_request(request); |
| 2664 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2665 | |
| 2666 | /* These may not have been flush before the reset, do so now */ |
| 2667 | kfree(ring->preallocated_lazy_request); |
| 2668 | ring->preallocated_lazy_request = NULL; |
| 2669 | ring->outstanding_lazy_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2670 | } |
| 2671 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2672 | void i915_gem_restore_fences(struct drm_device *dev) |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2673 | { |
| 2674 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2675 | int i; |
| 2676 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 2677 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2678 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2679 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 2680 | /* |
| 2681 | * Commit delayed tiling changes if we have an object still |
| 2682 | * attached to the fence, otherwise just clear the fence. |
| 2683 | */ |
| 2684 | if (reg->obj) { |
| 2685 | i915_gem_object_update_fence(reg->obj, reg, |
| 2686 | reg->obj->tiling_mode); |
| 2687 | } else { |
| 2688 | i915_gem_write_fence(dev, i, NULL); |
| 2689 | } |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2690 | } |
| 2691 | } |
| 2692 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2693 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2694 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2695 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2696 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2697 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2698 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2699 | /* |
| 2700 | * Before we free the objects from the requests, we need to inspect |
| 2701 | * them for finding the guilty party. As the requests only borrow |
| 2702 | * their reference to the objects, the inspection must be done first. |
| 2703 | */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2704 | for_each_ring(ring, dev_priv, i) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2705 | i915_gem_reset_ring_status(dev_priv, ring); |
| 2706 | |
| 2707 | for_each_ring(ring, dev_priv, i) |
| 2708 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2709 | |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2710 | i915_gem_context_reset(dev); |
| 2711 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2712 | i915_gem_restore_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2713 | } |
| 2714 | |
| 2715 | /** |
| 2716 | * This function clears the request list as sequence numbers are passed. |
| 2717 | */ |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 2718 | void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2719 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2720 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2721 | uint32_t seqno; |
| 2722 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2723 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 2724 | return; |
| 2725 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2726 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 2728 | seqno = ring->get_seqno(ring, true); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2729 | |
Chris Wilson | e910303 | 2014-01-07 11:45:14 +0000 | [diff] [blame] | 2730 | /* Move any buffers on the active list that are no longer referenced |
| 2731 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 2732 | * before we free the context associated with the requests. |
| 2733 | */ |
| 2734 | while (!list_empty(&ring->active_list)) { |
| 2735 | struct drm_i915_gem_object *obj; |
| 2736 | |
| 2737 | obj = list_first_entry(&ring->active_list, |
| 2738 | struct drm_i915_gem_object, |
| 2739 | ring_list); |
| 2740 | |
| 2741 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
| 2742 | break; |
| 2743 | |
| 2744 | i915_gem_object_move_to_inactive(obj); |
| 2745 | } |
| 2746 | |
| 2747 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2748 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2749 | struct drm_i915_gem_request *request; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2750 | struct intel_ringbuffer *ringbuf; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2751 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2752 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2753 | struct drm_i915_gem_request, |
| 2754 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2755 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2756 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2757 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2758 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2759 | trace_i915_gem_request_retire(ring, request->seqno); |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2760 | |
| 2761 | /* This is one of the few common intersection points |
| 2762 | * between legacy ringbuffer submission and execlists: |
| 2763 | * we need to tell them apart in order to find the correct |
| 2764 | * ringbuffer to which the request belongs to. |
| 2765 | */ |
| 2766 | if (i915.enable_execlists) { |
| 2767 | struct intel_context *ctx = request->ctx; |
| 2768 | ringbuf = ctx->engine[ring->id].ringbuf; |
| 2769 | } else |
| 2770 | ringbuf = ring->buffer; |
| 2771 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2772 | /* We know the GPU must have read the request to have |
| 2773 | * sent us the seqno + interrupt, so use the position |
| 2774 | * of tail of the request to update the last known position |
| 2775 | * of the GPU head. |
| 2776 | */ |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2777 | ringbuf->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2778 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2779 | i915_gem_free_request(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2780 | } |
| 2781 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2782 | if (unlikely(ring->trace_irq_seqno && |
| 2783 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2784 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2785 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2786 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2787 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2788 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2789 | } |
| 2790 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2791 | bool |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2792 | i915_gem_retire_requests(struct drm_device *dev) |
| 2793 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2794 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2795 | struct intel_engine_cs *ring; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2796 | bool idle = true; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2797 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2798 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2799 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2800 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2801 | idle &= list_empty(&ring->request_list); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 2802 | if (i915.enable_execlists) { |
| 2803 | unsigned long flags; |
| 2804 | |
| 2805 | spin_lock_irqsave(&ring->execlist_lock, flags); |
| 2806 | idle &= list_empty(&ring->execlist_queue); |
| 2807 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
| 2808 | |
| 2809 | intel_execlists_retire_requests(ring); |
| 2810 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2811 | } |
| 2812 | |
| 2813 | if (idle) |
| 2814 | mod_delayed_work(dev_priv->wq, |
| 2815 | &dev_priv->mm.idle_work, |
| 2816 | msecs_to_jiffies(100)); |
| 2817 | |
| 2818 | return idle; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2819 | } |
| 2820 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2821 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2822 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2823 | { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2824 | struct drm_i915_private *dev_priv = |
| 2825 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 2826 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2827 | bool idle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2828 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2829 | /* Come back later if the device is busy... */ |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2830 | idle = false; |
| 2831 | if (mutex_trylock(&dev->struct_mutex)) { |
| 2832 | idle = i915_gem_retire_requests(dev); |
| 2833 | mutex_unlock(&dev->struct_mutex); |
| 2834 | } |
| 2835 | if (!idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2836 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2837 | round_jiffies_up_relative(HZ)); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2838 | } |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2839 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2840 | static void |
| 2841 | i915_gem_idle_work_handler(struct work_struct *work) |
| 2842 | { |
| 2843 | struct drm_i915_private *dev_priv = |
| 2844 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2845 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2846 | intel_mark_idle(dev_priv->dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2847 | } |
| 2848 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2849 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2850 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2851 | * write domains, emitting any outstanding lazy request and retiring and |
| 2852 | * completed requests. |
| 2853 | */ |
| 2854 | static int |
| 2855 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2856 | { |
| 2857 | int ret; |
| 2858 | |
| 2859 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2860 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2861 | if (ret) |
| 2862 | return ret; |
| 2863 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2864 | i915_gem_retire_requests_ring(obj->ring); |
| 2865 | } |
| 2866 | |
| 2867 | return 0; |
| 2868 | } |
| 2869 | |
| 2870 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2871 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2872 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2873 | * |
| 2874 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2875 | * the timeout parameter. |
| 2876 | * -ETIME: object is still busy after timeout |
| 2877 | * -ERESTARTSYS: signal interrupted the wait |
| 2878 | * -ENONENT: object doesn't exist |
| 2879 | * Also possible, but rare: |
| 2880 | * -EAGAIN: GPU wedged |
| 2881 | * -ENOMEM: damn |
| 2882 | * -ENODEV: Internal IRQ fail |
| 2883 | * -E?: The add request failed |
| 2884 | * |
| 2885 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2886 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2887 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2888 | * without holding struct_mutex the object may become re-busied before this |
| 2889 | * function completes. A similar but shorter * race condition exists in the busy |
| 2890 | * ioctl |
| 2891 | */ |
| 2892 | int |
| 2893 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2894 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 2895 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2896 | struct drm_i915_gem_wait *args = data; |
| 2897 | struct drm_i915_gem_object *obj; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2898 | struct intel_engine_cs *ring = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2899 | unsigned reset_counter; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2900 | u32 seqno = 0; |
| 2901 | int ret = 0; |
| 2902 | |
Daniel Vetter | 11b5d51 | 2014-09-29 15:31:26 +0200 | [diff] [blame] | 2903 | if (args->flags != 0) |
| 2904 | return -EINVAL; |
| 2905 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2906 | ret = i915_mutex_lock_interruptible(dev); |
| 2907 | if (ret) |
| 2908 | return ret; |
| 2909 | |
| 2910 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2911 | if (&obj->base == NULL) { |
| 2912 | mutex_unlock(&dev->struct_mutex); |
| 2913 | return -ENOENT; |
| 2914 | } |
| 2915 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2916 | /* Need to make sure the object gets inactive eventually. */ |
| 2917 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2918 | if (ret) |
| 2919 | goto out; |
| 2920 | |
| 2921 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2922 | seqno = obj->last_read_seqno; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2923 | ring = obj->ring; |
| 2924 | } |
| 2925 | |
| 2926 | if (seqno == 0) |
| 2927 | goto out; |
| 2928 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2929 | /* Do this after OLR check to make sure we make forward progress polling |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 2930 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2931 | */ |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 2932 | if (args->timeout_ns <= 0) { |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2933 | ret = -ETIME; |
| 2934 | goto out; |
| 2935 | } |
| 2936 | |
| 2937 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2938 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2939 | mutex_unlock(&dev->struct_mutex); |
| 2940 | |
Ander Conselvan de Oliveira | 16e9a21 | 2014-11-06 09:26:38 +0200 | [diff] [blame] | 2941 | return __i915_wait_seqno(ring, seqno, reset_counter, true, |
| 2942 | &args->timeout_ns, file->driver_priv); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2943 | |
| 2944 | out: |
| 2945 | drm_gem_object_unreference(&obj->base); |
| 2946 | mutex_unlock(&dev->struct_mutex); |
| 2947 | return ret; |
| 2948 | } |
| 2949 | |
| 2950 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2951 | * i915_gem_object_sync - sync an object to a ring. |
| 2952 | * |
| 2953 | * @obj: object which may be in use on another ring. |
| 2954 | * @to: ring we wish to use the object on. May be NULL. |
| 2955 | * |
| 2956 | * This code is meant to abstract object synchronization with the GPU. |
| 2957 | * Calling with NULL implies synchronizing the object with the CPU |
| 2958 | * rather than a particular GPU ring. |
| 2959 | * |
| 2960 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2961 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2962 | int |
| 2963 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2964 | struct intel_engine_cs *to) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2965 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2966 | struct intel_engine_cs *from = obj->ring; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2967 | u32 seqno; |
| 2968 | int ret, idx; |
| 2969 | |
| 2970 | if (from == NULL || to == from) |
| 2971 | return 0; |
| 2972 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2973 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2974 | return i915_gem_object_wait_rendering(obj, false); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2975 | |
| 2976 | idx = intel_ring_sync_index(from, to); |
| 2977 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2978 | seqno = obj->last_read_seqno; |
Rodrigo Vivi | ddd4dbc | 2014-06-30 09:51:11 -0700 | [diff] [blame] | 2979 | /* Optimization: Avoid semaphore sync when we are sure we already |
| 2980 | * waited for an object with higher seqno */ |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2981 | if (seqno <= from->semaphore.sync_seqno[idx]) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2982 | return 0; |
| 2983 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2984 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2985 | if (ret) |
| 2986 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2987 | |
Chris Wilson | b52b89d | 2013-09-25 11:43:28 +0100 | [diff] [blame] | 2988 | trace_i915_gem_ring_sync_to(from, to, seqno); |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2989 | ret = to->semaphore.sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2990 | if (!ret) |
Mika Kuoppala | 7b01e26 | 2012-11-28 17:18:45 +0200 | [diff] [blame] | 2991 | /* We use last_read_seqno because sync_to() |
| 2992 | * might have just caused seqno wrap under |
| 2993 | * the radar. |
| 2994 | */ |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2995 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2996 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2997 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2998 | } |
| 2999 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3000 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 3001 | { |
| 3002 | u32 old_write_domain, old_read_domains; |
| 3003 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3004 | /* Force a pagefault for domain tracking on next user access */ |
| 3005 | i915_gem_release_mmap(obj); |
| 3006 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 3007 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3008 | return; |
| 3009 | |
Chris Wilson | 97c809fd | 2012-10-09 19:24:38 +0100 | [diff] [blame] | 3010 | /* Wait for any direct GTT access to complete */ |
| 3011 | mb(); |
| 3012 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3013 | old_read_domains = obj->base.read_domains; |
| 3014 | old_write_domain = obj->base.write_domain; |
| 3015 | |
| 3016 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 3017 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 3018 | |
| 3019 | trace_i915_gem_object_change_domain(obj, |
| 3020 | old_read_domains, |
| 3021 | old_write_domain); |
| 3022 | } |
| 3023 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3024 | int i915_vma_unbind(struct i915_vma *vma) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3025 | { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3026 | struct drm_i915_gem_object *obj = vma->obj; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3027 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 3028 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3029 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3030 | if (list_empty(&vma->vma_link)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3031 | return 0; |
| 3032 | |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 3033 | if (!drm_mm_node_allocated(&vma->node)) { |
| 3034 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 3035 | return 0; |
| 3036 | } |
Ben Widawsky | 433544b | 2013-08-13 18:09:06 -0700 | [diff] [blame] | 3037 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3038 | if (vma->pin_count) |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 3039 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3040 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 3041 | BUG_ON(obj->pages == NULL); |
| 3042 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3043 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3044 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3045 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 3046 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 3047 | * should be safe and we need to cleanup or else we might |
| 3048 | * cause memory corruption through use-after-free. |
| 3049 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3050 | |
Chris Wilson | 1d1ef21d | 2014-09-09 07:02:43 +0100 | [diff] [blame] | 3051 | /* Throw away the active reference before moving to the unbound list */ |
| 3052 | i915_gem_object_retire(obj); |
| 3053 | |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3054 | if (i915_is_ggtt(vma->vm)) { |
| 3055 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3056 | |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3057 | /* release the fence reg _after_ flushing */ |
| 3058 | ret = i915_gem_object_put_fence(obj); |
| 3059 | if (ret) |
| 3060 | return ret; |
| 3061 | } |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 3062 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3063 | trace_i915_vma_unbind(vma); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3064 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3065 | vma->unbind_vma(vma); |
| 3066 | |
Chris Wilson | 64bf930 | 2014-02-25 14:23:28 +0000 | [diff] [blame] | 3067 | list_del_init(&vma->mm_list); |
Ben Widawsky | 5cacaac | 2013-07-31 17:00:13 -0700 | [diff] [blame] | 3068 | if (i915_is_ggtt(vma->vm)) |
Chris Wilson | e6a8446 | 2014-08-11 12:00:12 +0200 | [diff] [blame] | 3069 | obj->map_and_fenceable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3070 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3071 | drm_mm_remove_node(&vma->node); |
| 3072 | i915_gem_vma_destroy(vma); |
| 3073 | |
| 3074 | /* Since the unbound list is global, only move to that list if |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 3075 | * no more VMAs exist. */ |
Armin Reese | 9490edb | 2014-07-11 10:20:07 -0700 | [diff] [blame] | 3076 | if (list_empty(&obj->vma_list)) { |
| 3077 | i915_gem_gtt_finish_object(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3078 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Armin Reese | 9490edb | 2014-07-11 10:20:07 -0700 | [diff] [blame] | 3079 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3080 | |
Chris Wilson | 70903c3 | 2013-12-04 09:59:09 +0000 | [diff] [blame] | 3081 | /* And finally now the object is completely decoupled from this vma, |
| 3082 | * we can drop its hold on the backing storage and allow it to be |
| 3083 | * reaped by the shrinker. |
| 3084 | */ |
| 3085 | i915_gem_object_unpin_pages(obj); |
| 3086 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3087 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 3088 | } |
| 3089 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3090 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3091 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3092 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3093 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3094 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3095 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3096 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3097 | for_each_ring(ring, dev_priv, i) { |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame] | 3098 | if (!i915.enable_execlists) { |
| 3099 | ret = i915_switch_context(ring, ring->default_context); |
| 3100 | if (ret) |
| 3101 | return ret; |
| 3102 | } |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 3103 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3104 | ret = intel_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3105 | if (ret) |
| 3106 | return ret; |
| 3107 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3108 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3109 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3110 | } |
| 3111 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3112 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 3113 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3114 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3115 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3116 | int fence_reg; |
| 3117 | int fence_pitch_shift; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3118 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3119 | if (INTEL_INFO(dev)->gen >= 6) { |
| 3120 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 3121 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 3122 | } else { |
| 3123 | fence_reg = FENCE_REG_965_0; |
| 3124 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 3125 | } |
| 3126 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3127 | fence_reg += reg * 8; |
| 3128 | |
| 3129 | /* To w/a incoherency with non-atomic 64-bit register updates, |
| 3130 | * we split the 64-bit update into two 32-bit writes. In order |
| 3131 | * for a partial fence not to be evaluated between writes, we |
| 3132 | * precede the update with write to turn off the fence register, |
| 3133 | * and only enable the fence as the last step. |
| 3134 | * |
| 3135 | * For extra levels of paranoia, we make sure each step lands |
| 3136 | * before applying the next step. |
| 3137 | */ |
| 3138 | I915_WRITE(fence_reg, 0); |
| 3139 | POSTING_READ(fence_reg); |
| 3140 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3141 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3142 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3143 | uint64_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3144 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3145 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3146 | 0xfffff000) << 32; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3147 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3148 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3149 | if (obj->tiling_mode == I915_TILING_Y) |
| 3150 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 3151 | val |= I965_FENCE_REG_VALID; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 3152 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 3153 | I915_WRITE(fence_reg + 4, val >> 32); |
| 3154 | POSTING_READ(fence_reg + 4); |
| 3155 | |
| 3156 | I915_WRITE(fence_reg + 0, val); |
| 3157 | POSTING_READ(fence_reg); |
| 3158 | } else { |
| 3159 | I915_WRITE(fence_reg + 4, 0); |
| 3160 | POSTING_READ(fence_reg + 4); |
| 3161 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3162 | } |
| 3163 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3164 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 3165 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3166 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3167 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3168 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3169 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3170 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3171 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3172 | int pitch_val; |
| 3173 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3174 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3175 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3176 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3177 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3178 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 3179 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3180 | |
| 3181 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 3182 | tile_width = 128; |
| 3183 | else |
| 3184 | tile_width = 512; |
| 3185 | |
| 3186 | /* Note: pitch better be a power of two tile widths */ |
| 3187 | pitch_val = obj->stride / tile_width; |
| 3188 | pitch_val = ffs(pitch_val) - 1; |
| 3189 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3190 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3191 | if (obj->tiling_mode == I915_TILING_Y) |
| 3192 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3193 | val |= I915_FENCE_SIZE_BITS(size); |
| 3194 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3195 | val |= I830_FENCE_REG_VALID; |
| 3196 | } else |
| 3197 | val = 0; |
| 3198 | |
| 3199 | if (reg < 8) |
| 3200 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3201 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3202 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 3203 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3204 | I915_WRITE(reg, val); |
| 3205 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3206 | } |
| 3207 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3208 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 3209 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3210 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3211 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3212 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3213 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3214 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3215 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3216 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3217 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3218 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3219 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3220 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3221 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
| 3222 | i915_gem_obj_ggtt_offset(obj), size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 3223 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3224 | pitch_val = obj->stride / 128; |
| 3225 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3226 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3227 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3228 | if (obj->tiling_mode == I915_TILING_Y) |
| 3229 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3230 | val |= I830_FENCE_SIZE_BITS(size); |
| 3231 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3232 | val |= I830_FENCE_REG_VALID; |
| 3233 | } else |
| 3234 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 3235 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3236 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 3237 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 3238 | } |
| 3239 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3240 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 3241 | { |
| 3242 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 3243 | } |
| 3244 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3245 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 3246 | struct drm_i915_gem_object *obj) |
| 3247 | { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3248 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3249 | |
| 3250 | /* Ensure that all CPU reads are completed before installing a fence |
| 3251 | * and all writes before removing the fence. |
| 3252 | */ |
| 3253 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 3254 | mb(); |
| 3255 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 3256 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
| 3257 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
| 3258 | obj->stride, obj->tiling_mode); |
| 3259 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3260 | switch (INTEL_INFO(dev)->gen) { |
Damien Lespiau | 01209dd | 2013-02-13 15:27:25 +0000 | [diff] [blame] | 3261 | case 9: |
Ben Widawsky | 5ab3133 | 2013-11-02 21:07:03 -0700 | [diff] [blame] | 3262 | case 8: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3263 | case 7: |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 3264 | case 6: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3265 | case 5: |
| 3266 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 3267 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 3268 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
Ben Widawsky | 7dbf9d6 | 2012-12-18 10:31:22 -0800 | [diff] [blame] | 3269 | default: BUG(); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3270 | } |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3271 | |
| 3272 | /* And similarly be paranoid that no direct access to this region |
| 3273 | * is reordered to before the fence is installed. |
| 3274 | */ |
| 3275 | if (i915_gem_object_needs_mb(obj)) |
| 3276 | mb(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3277 | } |
| 3278 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3279 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 3280 | struct drm_i915_fence_reg *fence) |
| 3281 | { |
| 3282 | return fence - dev_priv->fence_regs; |
| 3283 | } |
| 3284 | |
| 3285 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 3286 | struct drm_i915_fence_reg *fence, |
| 3287 | bool enable) |
| 3288 | { |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 3289 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3290 | int reg = fence_number(dev_priv, fence); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3291 | |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3292 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3293 | |
| 3294 | if (enable) { |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 3295 | obj->fence_reg = reg; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3296 | fence->obj = obj; |
| 3297 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 3298 | } else { |
| 3299 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3300 | fence->obj = NULL; |
| 3301 | list_del_init(&fence->lru_list); |
| 3302 | } |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 3303 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3304 | } |
| 3305 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3306 | static int |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3307 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3308 | { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 3309 | if (obj->last_fenced_seqno) { |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 3310 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 3311 | if (ret) |
| 3312 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3313 | |
| 3314 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3315 | } |
| 3316 | |
| 3317 | return 0; |
| 3318 | } |
| 3319 | |
| 3320 | int |
| 3321 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 3322 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3323 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3324 | struct drm_i915_fence_reg *fence; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3325 | int ret; |
| 3326 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3327 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3328 | if (ret) |
| 3329 | return ret; |
| 3330 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3331 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 3332 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3333 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3334 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 3335 | |
Daniel Vetter | aff10b30 | 2014-02-14 14:06:05 +0100 | [diff] [blame] | 3336 | if (WARN_ON(fence->pin_count)) |
| 3337 | return -EBUSY; |
| 3338 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3339 | i915_gem_object_fence_lost(obj); |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3340 | i915_gem_object_update_fence(obj, fence, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3341 | |
| 3342 | return 0; |
| 3343 | } |
| 3344 | |
| 3345 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 3346 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3347 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3348 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 3349 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3350 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3351 | |
| 3352 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3353 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3354 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 3355 | reg = &dev_priv->fence_regs[i]; |
| 3356 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3357 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3358 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3359 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3360 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3361 | } |
| 3362 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3363 | if (avail == NULL) |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3364 | goto deadlock; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3365 | |
| 3366 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3367 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3368 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3369 | continue; |
| 3370 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 3371 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3372 | } |
| 3373 | |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3374 | deadlock: |
| 3375 | /* Wait for completion of pending flips which consume fences */ |
| 3376 | if (intel_has_pending_fb_unpin(dev)) |
| 3377 | return ERR_PTR(-EAGAIN); |
| 3378 | |
| 3379 | return ERR_PTR(-EDEADLK); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3380 | } |
| 3381 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3382 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3383 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3384 | * @obj: object to map through a fence reg |
| 3385 | * |
| 3386 | * When mapping objects through the GTT, userspace wants to be able to write |
| 3387 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3388 | * This function walks the fence regs looking for a free one for @obj, |
| 3389 | * stealing one if it can't find any. |
| 3390 | * |
| 3391 | * It then sets up the reg based on the object's properties: address, pitch |
| 3392 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3393 | * |
| 3394 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3395 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 3396 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 3397 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3398 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3399 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3400 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3401 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3402 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3403 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3404 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3405 | /* Have we updated the tiling parameters upon the object and so |
| 3406 | * will need to serialise the write to the associated fence register? |
| 3407 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3408 | if (obj->fence_dirty) { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3409 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3410 | if (ret) |
| 3411 | return ret; |
| 3412 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3413 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3414 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3415 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 3416 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3417 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3418 | list_move_tail(®->lru_list, |
| 3419 | &dev_priv->mm.fence_list); |
| 3420 | return 0; |
| 3421 | } |
| 3422 | } else if (enable) { |
Chris Wilson | e6a8446 | 2014-08-11 12:00:12 +0200 | [diff] [blame] | 3423 | if (WARN_ON(!obj->map_and_fenceable)) |
| 3424 | return -EINVAL; |
| 3425 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3426 | reg = i915_find_fence_reg(dev); |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3427 | if (IS_ERR(reg)) |
| 3428 | return PTR_ERR(reg); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3429 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3430 | if (reg->obj) { |
| 3431 | struct drm_i915_gem_object *old = reg->obj; |
| 3432 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3433 | ret = i915_gem_object_wait_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3434 | if (ret) |
| 3435 | return ret; |
| 3436 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3437 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3438 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3439 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3440 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3441 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3442 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3443 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3444 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3445 | } |
| 3446 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3447 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3448 | unsigned long cache_level) |
| 3449 | { |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3450 | struct drm_mm_node *gtt_space = &vma->node; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3451 | struct drm_mm_node *other; |
| 3452 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3453 | /* |
| 3454 | * On some machines we have to be careful when putting differing types |
| 3455 | * of snoopable memory together to avoid the prefetcher crossing memory |
| 3456 | * domains and dying. During vm initialisation, we decide whether or not |
| 3457 | * these constraints apply and set the drm_mm.color_adjust |
| 3458 | * appropriately. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3459 | */ |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3460 | if (vma->vm->mm.color_adjust == NULL) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3461 | return true; |
| 3462 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3463 | if (!drm_mm_node_allocated(gtt_space)) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3464 | return true; |
| 3465 | |
| 3466 | if (list_empty(>t_space->node_list)) |
| 3467 | return true; |
| 3468 | |
| 3469 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3470 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3471 | return false; |
| 3472 | |
| 3473 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3474 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3475 | return false; |
| 3476 | |
| 3477 | return true; |
| 3478 | } |
| 3479 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3480 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3481 | * Finds free space in the GTT aperture and binds the object there. |
| 3482 | */ |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3483 | static struct i915_vma * |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3484 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3485 | struct i915_address_space *vm, |
| 3486 | unsigned alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3487 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3488 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3489 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3490 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3491 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3492 | unsigned long start = |
| 3493 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
| 3494 | unsigned long end = |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3495 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3496 | struct i915_vma *vma; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3497 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3498 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3499 | fence_size = i915_gem_get_gtt_size(dev, |
| 3500 | obj->base.size, |
| 3501 | obj->tiling_mode); |
| 3502 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3503 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3504 | obj->tiling_mode, true); |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3505 | unfenced_alignment = |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3506 | i915_gem_get_gtt_alignment(dev, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3507 | obj->base.size, |
| 3508 | obj->tiling_mode, false); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3509 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3510 | if (alignment == 0) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3511 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3512 | unfenced_alignment; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3513 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 3514 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3515 | return ERR_PTR(-EINVAL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3516 | } |
| 3517 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3518 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3519 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3520 | /* If the object is bigger than the entire aperture, reject it early |
| 3521 | * before evicting everything in a vain attempt to find space. |
| 3522 | */ |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3523 | if (obj->base.size > end) { |
| 3524 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", |
Chris Wilson | a36689c | 2013-05-21 16:58:49 +0100 | [diff] [blame] | 3525 | obj->base.size, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3526 | flags & PIN_MAPPABLE ? "mappable" : "total", |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3527 | end); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3528 | return ERR_PTR(-E2BIG); |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3529 | } |
| 3530 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3531 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3532 | if (ret) |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3533 | return ERR_PTR(ret); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3534 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3535 | i915_gem_object_pin_pages(obj); |
| 3536 | |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 3537 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3538 | if (IS_ERR(vma)) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3539 | goto err_unpin; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3540 | |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3541 | search_free: |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3542 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3543 | size, alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3544 | obj->cache_level, |
| 3545 | start, end, |
Lauri Kasanen | 62347f9 | 2014-04-02 20:03:57 +0300 | [diff] [blame] | 3546 | DRM_MM_SEARCH_DEFAULT, |
| 3547 | DRM_MM_CREATE_DEFAULT); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3548 | if (ret) { |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 3549 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3550 | obj->cache_level, |
| 3551 | start, end, |
| 3552 | flags); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3553 | if (ret == 0) |
| 3554 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3555 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3556 | goto err_free_vma; |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3557 | } |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3558 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3559 | ret = -EINVAL; |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3560 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3561 | } |
| 3562 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 3563 | ret = i915_gem_gtt_prepare_object(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3564 | if (ret) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3565 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3566 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3567 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3568 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3569 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3570 | trace_i915_vma_bind(vma, flags); |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 3571 | vma->bind_vma(vma, obj->cache_level, |
Chris Wilson | c826c44 | 2014-10-31 13:53:53 +0000 | [diff] [blame] | 3572 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 3573 | |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3574 | return vma; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3575 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3576 | err_remove_node: |
Dan Carpenter | 6286ef9 | 2013-07-19 08:46:27 +0300 | [diff] [blame] | 3577 | drm_mm_remove_node(&vma->node); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3578 | err_free_vma: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3579 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3580 | vma = ERR_PTR(ret); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3581 | err_unpin: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3582 | i915_gem_object_unpin_pages(obj); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3583 | return vma; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3584 | } |
| 3585 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3586 | bool |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3587 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3588 | bool force) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3589 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3590 | /* If we don't have a page list set up, then we're not pinned |
| 3591 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3592 | * again at bind time. |
| 3593 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3594 | if (obj->pages == NULL) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3595 | return false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3596 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3597 | /* |
| 3598 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3599 | * marked as wc by the system, or the system is cache-coherent. |
| 3600 | */ |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 3601 | if (obj->stolen || obj->phys_handle) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3602 | return false; |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3603 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3604 | /* If the GPU is snooping the contents of the CPU cache, |
| 3605 | * we do not need to manually clear the CPU cache lines. However, |
| 3606 | * the caches are only snooped when the render cache is |
| 3607 | * flushed/invalidated. As we always have to emit invalidations |
| 3608 | * and flushes when moving into and out of the RENDER domain, correct |
| 3609 | * snooping behaviour occurs naturally as the result of our domain |
| 3610 | * tracking. |
| 3611 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3612 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3613 | return false; |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3614 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3615 | trace_i915_gem_object_clflush(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3616 | drm_clflush_sg(obj->pages); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3617 | |
| 3618 | return true; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3619 | } |
| 3620 | |
| 3621 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3622 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3623 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3624 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3625 | uint32_t old_write_domain; |
| 3626 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3627 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3628 | return; |
| 3629 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3630 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3631 | * to it immediately go to main memory as far as we know, so there's |
| 3632 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3633 | * |
| 3634 | * However, we do have to enforce the order so that all writes through |
| 3635 | * the GTT land before any writes to the device, such as updates to |
| 3636 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3637 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3638 | wmb(); |
| 3639 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3640 | old_write_domain = obj->base.write_domain; |
| 3641 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3642 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3643 | intel_fb_obj_flush(obj, false); |
| 3644 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3645 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3646 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3647 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3648 | } |
| 3649 | |
| 3650 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3651 | static void |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3652 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 3653 | bool force) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3654 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3655 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3656 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3657 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3658 | return; |
| 3659 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3660 | if (i915_gem_clflush_object(obj, force)) |
| 3661 | i915_gem_chipset_flush(obj->base.dev); |
| 3662 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3663 | old_write_domain = obj->base.write_domain; |
| 3664 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3665 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3666 | intel_fb_obj_flush(obj, false); |
| 3667 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3668 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3669 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3670 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3671 | } |
| 3672 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3673 | /** |
| 3674 | * Moves a single object to the GTT read, and possibly write domain. |
| 3675 | * |
| 3676 | * This function returns when the move is complete, including waiting on |
| 3677 | * flushes to occur. |
| 3678 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3679 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3680 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3681 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3682 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | dc8cd1e | 2014-08-09 17:37:22 +0100 | [diff] [blame] | 3683 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3684 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3685 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3686 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3687 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | dc8cd1e | 2014-08-09 17:37:22 +0100 | [diff] [blame] | 3688 | if (vma == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3689 | return -EINVAL; |
| 3690 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3691 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3692 | return 0; |
| 3693 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3694 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3695 | if (ret) |
| 3696 | return ret; |
| 3697 | |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 3698 | i915_gem_object_retire(obj); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3699 | i915_gem_object_flush_cpu_write_domain(obj, false); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3700 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3701 | /* Serialise direct access to this object with the barriers for |
| 3702 | * coherent writes from the GPU, by effectively invalidating the |
| 3703 | * GTT domain upon first access. |
| 3704 | */ |
| 3705 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3706 | mb(); |
| 3707 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3708 | old_write_domain = obj->base.write_domain; |
| 3709 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3710 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3711 | /* It should now be out of any other write domains, and we can update |
| 3712 | * the domain values for our changes. |
| 3713 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3714 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3715 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3716 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3717 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3718 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3719 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3720 | } |
| 3721 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3722 | if (write) |
| 3723 | intel_fb_obj_invalidate(obj, NULL); |
| 3724 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3725 | trace_i915_gem_object_change_domain(obj, |
| 3726 | old_read_domains, |
| 3727 | old_write_domain); |
| 3728 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3729 | /* And bump the LRU for this access */ |
Chris Wilson | dc8cd1e | 2014-08-09 17:37:22 +0100 | [diff] [blame] | 3730 | if (i915_gem_object_is_inactive(obj)) |
| 3731 | list_move_tail(&vma->mm_list, |
| 3732 | &dev_priv->gtt.base.inactive_list); |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3733 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3734 | return 0; |
| 3735 | } |
| 3736 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3737 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3738 | enum i915_cache_level cache_level) |
| 3739 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3740 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | df6f783 | 2014-03-21 07:40:56 +0000 | [diff] [blame] | 3741 | struct i915_vma *vma, *next; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3742 | int ret; |
| 3743 | |
| 3744 | if (obj->cache_level == cache_level) |
| 3745 | return 0; |
| 3746 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3747 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3748 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3749 | return -EBUSY; |
| 3750 | } |
| 3751 | |
Chris Wilson | df6f783 | 2014-03-21 07:40:56 +0000 | [diff] [blame] | 3752 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3753 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3754 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3755 | if (ret) |
| 3756 | return ret; |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3757 | } |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3758 | } |
| 3759 | |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3760 | if (i915_gem_obj_bound_any(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3761 | ret = i915_gem_object_finish_gpu(obj); |
| 3762 | if (ret) |
| 3763 | return ret; |
| 3764 | |
| 3765 | i915_gem_object_finish_gtt(obj); |
| 3766 | |
| 3767 | /* Before SandyBridge, you could not use tiling or fence |
| 3768 | * registers with snooped memory, so relinquish any fences |
| 3769 | * currently pointing to our region in the aperture. |
| 3770 | */ |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3771 | if (INTEL_INFO(dev)->gen < 6) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3772 | ret = i915_gem_object_put_fence(obj); |
| 3773 | if (ret) |
| 3774 | return ret; |
| 3775 | } |
| 3776 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3777 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 3778 | if (drm_mm_node_allocated(&vma->node)) |
| 3779 | vma->bind_vma(vma, cache_level, |
Tvrtko Ursulin | aff4376 | 2014-10-24 12:42:33 +0100 | [diff] [blame] | 3780 | vma->bound & GLOBAL_BIND); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3781 | } |
| 3782 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3783 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 3784 | vma->node.color = cache_level; |
| 3785 | obj->cache_level = cache_level; |
| 3786 | |
| 3787 | if (cpu_write_needs_clflush(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3788 | u32 old_read_domains, old_write_domain; |
| 3789 | |
| 3790 | /* If we're coming from LLC cached, then we haven't |
| 3791 | * actually been tracking whether the data is in the |
| 3792 | * CPU cache or not, since we only allow one bit set |
| 3793 | * in obj->write_domain and have been skipping the clflushes. |
| 3794 | * Just set it to the CPU cache for now. |
| 3795 | */ |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 3796 | i915_gem_object_retire(obj); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3797 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3798 | |
| 3799 | old_read_domains = obj->base.read_domains; |
| 3800 | old_write_domain = obj->base.write_domain; |
| 3801 | |
| 3802 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3803 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3804 | |
| 3805 | trace_i915_gem_object_change_domain(obj, |
| 3806 | old_read_domains, |
| 3807 | old_write_domain); |
| 3808 | } |
| 3809 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3810 | return 0; |
| 3811 | } |
| 3812 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3813 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3814 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3815 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3816 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3817 | struct drm_i915_gem_object *obj; |
| 3818 | int ret; |
| 3819 | |
| 3820 | ret = i915_mutex_lock_interruptible(dev); |
| 3821 | if (ret) |
| 3822 | return ret; |
| 3823 | |
| 3824 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3825 | if (&obj->base == NULL) { |
| 3826 | ret = -ENOENT; |
| 3827 | goto unlock; |
| 3828 | } |
| 3829 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3830 | switch (obj->cache_level) { |
| 3831 | case I915_CACHE_LLC: |
| 3832 | case I915_CACHE_L3_LLC: |
| 3833 | args->caching = I915_CACHING_CACHED; |
| 3834 | break; |
| 3835 | |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3836 | case I915_CACHE_WT: |
| 3837 | args->caching = I915_CACHING_DISPLAY; |
| 3838 | break; |
| 3839 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3840 | default: |
| 3841 | args->caching = I915_CACHING_NONE; |
| 3842 | break; |
| 3843 | } |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3844 | |
| 3845 | drm_gem_object_unreference(&obj->base); |
| 3846 | unlock: |
| 3847 | mutex_unlock(&dev->struct_mutex); |
| 3848 | return ret; |
| 3849 | } |
| 3850 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3851 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3852 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3853 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3854 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3855 | struct drm_i915_gem_object *obj; |
| 3856 | enum i915_cache_level level; |
| 3857 | int ret; |
| 3858 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3859 | switch (args->caching) { |
| 3860 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3861 | level = I915_CACHE_NONE; |
| 3862 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3863 | case I915_CACHING_CACHED: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3864 | level = I915_CACHE_LLC; |
| 3865 | break; |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3866 | case I915_CACHING_DISPLAY: |
| 3867 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 3868 | break; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3869 | default: |
| 3870 | return -EINVAL; |
| 3871 | } |
| 3872 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 3873 | ret = i915_mutex_lock_interruptible(dev); |
| 3874 | if (ret) |
| 3875 | return ret; |
| 3876 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3877 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3878 | if (&obj->base == NULL) { |
| 3879 | ret = -ENOENT; |
| 3880 | goto unlock; |
| 3881 | } |
| 3882 | |
| 3883 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3884 | |
| 3885 | drm_gem_object_unreference(&obj->base); |
| 3886 | unlock: |
| 3887 | mutex_unlock(&dev->struct_mutex); |
| 3888 | return ret; |
| 3889 | } |
| 3890 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3891 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
| 3892 | { |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3893 | struct i915_vma *vma; |
| 3894 | |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3895 | vma = i915_gem_obj_to_ggtt(obj); |
| 3896 | if (!vma) |
| 3897 | return false; |
| 3898 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3899 | /* There are 3 sources that pin objects: |
| 3900 | * 1. The display engine (scanouts, sprites, cursors); |
| 3901 | * 2. Reservations for execbuffer; |
| 3902 | * 3. The user. |
| 3903 | * |
| 3904 | * We can ignore reservations as we hold the struct_mutex and |
| 3905 | * are only called outside of the reservation path. The user |
| 3906 | * can only increment pin_count once, and so if after |
| 3907 | * subtracting the potential reference by the user, any pin_count |
| 3908 | * remains, it must be due to another use by the display engine. |
| 3909 | */ |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3910 | return vma->pin_count - !!obj->user_pin_count; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3911 | } |
| 3912 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3913 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3914 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3915 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3916 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3917 | */ |
| 3918 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3919 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3920 | u32 alignment, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3921 | struct intel_engine_cs *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3922 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3923 | u32 old_read_domains, old_write_domain; |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3924 | bool was_pin_display; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3925 | int ret; |
| 3926 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3927 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3928 | ret = i915_gem_object_sync(obj, pipelined); |
| 3929 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3930 | return ret; |
| 3931 | } |
| 3932 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3933 | /* Mark the pin_display early so that we account for the |
| 3934 | * display coherency whilst setting up the cache domains. |
| 3935 | */ |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3936 | was_pin_display = obj->pin_display; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3937 | obj->pin_display = true; |
| 3938 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3939 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3940 | * a result, we make sure that the pinning that is about to occur is |
| 3941 | * done with uncached PTEs. This is lowest common denominator for all |
| 3942 | * chipsets. |
| 3943 | * |
| 3944 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3945 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3946 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3947 | */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3948 | ret = i915_gem_object_set_cache_level(obj, |
| 3949 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3950 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3951 | goto err_unpin_display; |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3952 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3953 | /* As the user may map the buffer once pinned in the display plane |
| 3954 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3955 | * always use map_and_fenceable for all scanout buffers. |
| 3956 | */ |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3957 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3958 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3959 | goto err_unpin_display; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3960 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3961 | i915_gem_object_flush_cpu_write_domain(obj, true); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3962 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3963 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3964 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3965 | |
| 3966 | /* It should now be out of any other write domains, and we can update |
| 3967 | * the domain values for our changes. |
| 3968 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 3969 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3970 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3971 | |
| 3972 | trace_i915_gem_object_change_domain(obj, |
| 3973 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3974 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3975 | |
| 3976 | return 0; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3977 | |
| 3978 | err_unpin_display: |
Oscar Mateo | 1965643 | 2014-05-16 14:20:43 +0100 | [diff] [blame] | 3979 | WARN_ON(was_pin_display != is_pin_display(obj)); |
| 3980 | obj->pin_display = was_pin_display; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3981 | return ret; |
| 3982 | } |
| 3983 | |
| 3984 | void |
| 3985 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
| 3986 | { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3987 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3988 | obj->pin_display = is_pin_display(obj); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3989 | } |
| 3990 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3991 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3992 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3993 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3994 | int ret; |
| 3995 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3996 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3997 | return 0; |
| 3998 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3999 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 4000 | if (ret) |
| 4001 | return ret; |
| 4002 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 4003 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 4004 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 4005 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 4006 | } |
| 4007 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4008 | /** |
| 4009 | * Moves a single object to the CPU read, and possibly write domain. |
| 4010 | * |
| 4011 | * This function returns when the move is complete, including waiting on |
| 4012 | * flushes to occur. |
| 4013 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 4014 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 4015 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4016 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4017 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4018 | int ret; |
| 4019 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 4020 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 4021 | return 0; |
| 4022 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 4023 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 4024 | if (ret) |
| 4025 | return ret; |
| 4026 | |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 4027 | i915_gem_object_retire(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4028 | i915_gem_object_flush_gtt_write_domain(obj); |
| 4029 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4030 | old_write_domain = obj->base.write_domain; |
| 4031 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4032 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4033 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4034 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 4035 | i915_gem_clflush_object(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4036 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4037 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4038 | } |
| 4039 | |
| 4040 | /* It should now be out of any other write domains, and we can update |
| 4041 | * the domain values for our changes. |
| 4042 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4043 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4044 | |
| 4045 | /* If we're writing through the CPU, then the GPU read domains will |
| 4046 | * need to be invalidated at next use. |
| 4047 | */ |
| 4048 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4049 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4050 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4051 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4052 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 4053 | if (write) |
| 4054 | intel_fb_obj_invalidate(obj, NULL); |
| 4055 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4056 | trace_i915_gem_object_change_domain(obj, |
| 4057 | old_read_domains, |
| 4058 | old_write_domain); |
| 4059 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4060 | return 0; |
| 4061 | } |
| 4062 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4063 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 4064 | * emitted over 20 msec ago. |
| 4065 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4066 | * Note that if we were to use the current jiffies each time around the loop, |
| 4067 | * we wouldn't escape the function with any frames outstanding if the time to |
| 4068 | * render a frame was over 20ms. |
| 4069 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4070 | * This should get us reasonable parallelism between CPU and GPU but also |
| 4071 | * relatively low latency when blocking on a particular request to finish. |
| 4072 | */ |
| 4073 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4074 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4075 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4076 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4077 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4078 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4079 | struct drm_i915_gem_request *request; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4080 | struct intel_engine_cs *ring = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 4081 | unsigned reset_counter; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4082 | u32 seqno = 0; |
| 4083 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4084 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 4085 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 4086 | if (ret) |
| 4087 | return ret; |
| 4088 | |
| 4089 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 4090 | if (ret) |
| 4091 | return ret; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 4092 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4093 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4094 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4095 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 4096 | break; |
| 4097 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4098 | ring = request->ring; |
| 4099 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4100 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 4101 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4102 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4103 | |
| 4104 | if (seqno == 0) |
| 4105 | return 0; |
| 4106 | |
Ander Conselvan de Oliveira | 16e9a21 | 2014-11-06 09:26:38 +0200 | [diff] [blame] | 4107 | ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4108 | if (ret == 0) |
| 4109 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4110 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4111 | return ret; |
| 4112 | } |
| 4113 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4114 | static bool |
| 4115 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
| 4116 | { |
| 4117 | struct drm_i915_gem_object *obj = vma->obj; |
| 4118 | |
| 4119 | if (alignment && |
| 4120 | vma->node.start & (alignment - 1)) |
| 4121 | return true; |
| 4122 | |
| 4123 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
| 4124 | return true; |
| 4125 | |
| 4126 | if (flags & PIN_OFFSET_BIAS && |
| 4127 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
| 4128 | return true; |
| 4129 | |
| 4130 | return false; |
| 4131 | } |
| 4132 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4133 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4134 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 4135 | struct i915_address_space *vm, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4136 | uint32_t alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4137 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4138 | { |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4139 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4140 | struct i915_vma *vma; |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4141 | unsigned bound; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4142 | int ret; |
| 4143 | |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4144 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
| 4145 | return -ENODEV; |
| 4146 | |
Daniel Vetter | bf3d149 | 2014-02-14 14:01:12 +0100 | [diff] [blame] | 4147 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4148 | return -EINVAL; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4149 | |
Chris Wilson | c826c44 | 2014-10-31 13:53:53 +0000 | [diff] [blame] | 4150 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
| 4151 | return -EINVAL; |
| 4152 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4153 | vma = i915_gem_obj_to_vma(obj, vm); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4154 | if (vma) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4155 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 4156 | return -EBUSY; |
| 4157 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4158 | if (i915_vma_misplaced(vma, alignment, flags)) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4159 | WARN(vma->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4160 | "bo is already pinned with incorrect alignment:" |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 4161 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4162 | " obj->map_and_fenceable=%d\n", |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4163 | i915_gem_obj_offset(obj, vm), alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4164 | !!(flags & PIN_MAPPABLE), |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4165 | obj->map_and_fenceable); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4166 | ret = i915_vma_unbind(vma); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4167 | if (ret) |
| 4168 | return ret; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4169 | |
| 4170 | vma = NULL; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4171 | } |
| 4172 | } |
| 4173 | |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4174 | bound = vma ? vma->bound : 0; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4175 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 4176 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
| 4177 | if (IS_ERR(vma)) |
| 4178 | return PTR_ERR(vma); |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4179 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4180 | |
Tvrtko Ursulin | aff4376 | 2014-10-24 12:42:33 +0100 | [diff] [blame] | 4181 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4182 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 4183 | |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4184 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
| 4185 | bool mappable, fenceable; |
| 4186 | u32 fence_size, fence_alignment; |
| 4187 | |
| 4188 | fence_size = i915_gem_get_gtt_size(obj->base.dev, |
| 4189 | obj->base.size, |
| 4190 | obj->tiling_mode); |
| 4191 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, |
| 4192 | obj->base.size, |
| 4193 | obj->tiling_mode, |
| 4194 | true); |
| 4195 | |
| 4196 | fenceable = (vma->node.size == fence_size && |
| 4197 | (vma->node.start & (fence_alignment - 1)) == 0); |
| 4198 | |
| 4199 | mappable = (vma->node.start + obj->base.size <= |
| 4200 | dev_priv->gtt.mappable_end); |
| 4201 | |
| 4202 | obj->map_and_fenceable = mappable && fenceable; |
| 4203 | } |
| 4204 | |
| 4205 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
| 4206 | |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4207 | vma->pin_count++; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4208 | if (flags & PIN_MAPPABLE) |
| 4209 | obj->pin_mappable |= true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4210 | |
| 4211 | return 0; |
| 4212 | } |
| 4213 | |
| 4214 | void |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4215 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4216 | { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4217 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4218 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4219 | BUG_ON(!vma); |
| 4220 | BUG_ON(vma->pin_count == 0); |
| 4221 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
| 4222 | |
| 4223 | if (--vma->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 4224 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4225 | } |
| 4226 | |
Daniel Vetter | d8ffa60 | 2014-05-13 12:11:26 +0200 | [diff] [blame] | 4227 | bool |
| 4228 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 4229 | { |
| 4230 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4231 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4232 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); |
| 4233 | |
| 4234 | WARN_ON(!ggtt_vma || |
| 4235 | dev_priv->fence_regs[obj->fence_reg].pin_count > |
| 4236 | ggtt_vma->pin_count); |
| 4237 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
| 4238 | return true; |
| 4239 | } else |
| 4240 | return false; |
| 4241 | } |
| 4242 | |
| 4243 | void |
| 4244 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 4245 | { |
| 4246 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4247 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4248 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
| 4249 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 4250 | } |
| 4251 | } |
| 4252 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4253 | int |
| 4254 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4255 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4256 | { |
| 4257 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4258 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4259 | int ret; |
| 4260 | |
Daniel Vetter | d472fcc | 2014-11-24 11:12:42 +0100 | [diff] [blame] | 4261 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
Daniel Vetter | 02f6bcc | 2013-12-18 16:30:22 +0100 | [diff] [blame] | 4262 | return -ENODEV; |
| 4263 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4264 | ret = i915_mutex_lock_interruptible(dev); |
| 4265 | if (ret) |
| 4266 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4267 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4268 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4269 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4270 | ret = -ENOENT; |
| 4271 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4272 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4273 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4274 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 4275 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 4276 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4277 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4278 | } |
| 4279 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4280 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 4281 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4282 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4283 | ret = -EINVAL; |
| 4284 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4285 | } |
| 4286 | |
Daniel Vetter | aa5f802 | 2013-10-10 14:46:37 +0200 | [diff] [blame] | 4287 | if (obj->user_pin_count == ULONG_MAX) { |
| 4288 | ret = -EBUSY; |
| 4289 | goto out; |
| 4290 | } |
| 4291 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 4292 | if (obj->user_pin_count == 0) { |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4293 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4294 | if (ret) |
| 4295 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4296 | } |
| 4297 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 4298 | obj->user_pin_count++; |
| 4299 | obj->pin_filp = file; |
| 4300 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 4301 | args->offset = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4302 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4303 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4304 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4305 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4306 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4307 | } |
| 4308 | |
| 4309 | int |
| 4310 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4311 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4312 | { |
| 4313 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4314 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4315 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4316 | |
Daniel Vetter | d472fcc | 2014-11-24 11:12:42 +0100 | [diff] [blame] | 4317 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4318 | return -ENODEV; |
| 4319 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4320 | ret = i915_mutex_lock_interruptible(dev); |
| 4321 | if (ret) |
| 4322 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4323 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4324 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4325 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4326 | ret = -ENOENT; |
| 4327 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4328 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4329 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4330 | if (obj->pin_filp != file) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 4331 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4332 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4333 | ret = -EINVAL; |
| 4334 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4335 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4336 | obj->user_pin_count--; |
| 4337 | if (obj->user_pin_count == 0) { |
| 4338 | obj->pin_filp = NULL; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4339 | i915_gem_object_ggtt_unpin(obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4340 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4341 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4342 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4343 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4344 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4345 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4346 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4347 | } |
| 4348 | |
| 4349 | int |
| 4350 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4351 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4352 | { |
| 4353 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4354 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4355 | int ret; |
| 4356 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4357 | ret = i915_mutex_lock_interruptible(dev); |
| 4358 | if (ret) |
| 4359 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4360 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4361 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4362 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4363 | ret = -ENOENT; |
| 4364 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4365 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4366 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4367 | /* Count all active objects as busy, even if they are currently not used |
| 4368 | * by the gpu. Users of this interface expect objects to eventually |
| 4369 | * become non-busy without any further actions, therefore emit any |
| 4370 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4371 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4372 | ret = i915_gem_object_flush_active(obj); |
| 4373 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4374 | args->busy = obj->active; |
Chris Wilson | e9808ed | 2012-07-04 12:25:08 +0100 | [diff] [blame] | 4375 | if (obj->ring) { |
| 4376 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 4377 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 4378 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4379 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4380 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4381 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4382 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4383 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4384 | } |
| 4385 | |
| 4386 | int |
| 4387 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4388 | struct drm_file *file_priv) |
| 4389 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 4390 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4391 | } |
| 4392 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4393 | int |
| 4394 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4395 | struct drm_file *file_priv) |
| 4396 | { |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4397 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4398 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4399 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4400 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4401 | |
| 4402 | switch (args->madv) { |
| 4403 | case I915_MADV_DONTNEED: |
| 4404 | case I915_MADV_WILLNEED: |
| 4405 | break; |
| 4406 | default: |
| 4407 | return -EINVAL; |
| 4408 | } |
| 4409 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4410 | ret = i915_mutex_lock_interruptible(dev); |
| 4411 | if (ret) |
| 4412 | return ret; |
| 4413 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4414 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4415 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4416 | ret = -ENOENT; |
| 4417 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4418 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4419 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4420 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4421 | ret = -EINVAL; |
| 4422 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4423 | } |
| 4424 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4425 | if (obj->pages && |
| 4426 | obj->tiling_mode != I915_TILING_NONE && |
| 4427 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
| 4428 | if (obj->madv == I915_MADV_WILLNEED) |
| 4429 | i915_gem_object_unpin_pages(obj); |
| 4430 | if (args->madv == I915_MADV_WILLNEED) |
| 4431 | i915_gem_object_pin_pages(obj); |
| 4432 | } |
| 4433 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4434 | if (obj->madv != __I915_MADV_PURGED) |
| 4435 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4436 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4437 | /* if the object is no longer attached, discard its backing storage */ |
| 4438 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4439 | i915_gem_object_truncate(obj); |
| 4440 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4441 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4442 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4443 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4444 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4445 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4446 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4447 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4448 | } |
| 4449 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4450 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4451 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4452 | { |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4453 | INIT_LIST_HEAD(&obj->global_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4454 | INIT_LIST_HEAD(&obj->ring_list); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 4455 | INIT_LIST_HEAD(&obj->obj_exec_link); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4456 | INIT_LIST_HEAD(&obj->vma_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4457 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4458 | obj->ops = ops; |
| 4459 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4460 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4461 | obj->madv = I915_MADV_WILLNEED; |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4462 | |
| 4463 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4464 | } |
| 4465 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4466 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 4467 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4468 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4469 | }; |
| 4470 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4471 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4472 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4473 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4474 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4475 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 4476 | gfp_t mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4477 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4478 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4479 | if (obj == NULL) |
| 4480 | return NULL; |
| 4481 | |
| 4482 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4483 | i915_gem_object_free(obj); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4484 | return NULL; |
| 4485 | } |
| 4486 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4487 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4488 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4489 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4490 | mask &= ~__GFP_HIGHMEM; |
| 4491 | mask |= __GFP_DMA32; |
| 4492 | } |
| 4493 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4494 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4495 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4496 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4497 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4498 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4499 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4500 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4501 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 4502 | if (HAS_LLC(dev)) { |
| 4503 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 4504 | * cache) for about a 10% performance improvement |
| 4505 | * compared to uncached. Graphics requests other than |
| 4506 | * display scanout are coherent with the CPU in |
| 4507 | * accessing this cache. This means in this mode we |
| 4508 | * don't need to clflush on the CPU side, and on the |
| 4509 | * GPU side we only need to flush internal caches to |
| 4510 | * get data visible to the CPU. |
| 4511 | * |
| 4512 | * However, we maintain the display planes as UC, and so |
| 4513 | * need to rebind when first used as such. |
| 4514 | */ |
| 4515 | obj->cache_level = I915_CACHE_LLC; |
| 4516 | } else |
| 4517 | obj->cache_level = I915_CACHE_NONE; |
| 4518 | |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 4519 | trace_i915_gem_object_create(obj); |
| 4520 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4521 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4522 | } |
| 4523 | |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4524 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
| 4525 | { |
| 4526 | /* If we are the last user of the backing storage (be it shmemfs |
| 4527 | * pages or stolen etc), we know that the pages are going to be |
| 4528 | * immediately released. In this case, we can then skip copying |
| 4529 | * back the contents from the GPU. |
| 4530 | */ |
| 4531 | |
| 4532 | if (obj->madv != I915_MADV_WILLNEED) |
| 4533 | return false; |
| 4534 | |
| 4535 | if (obj->base.filp == NULL) |
| 4536 | return true; |
| 4537 | |
| 4538 | /* At first glance, this looks racy, but then again so would be |
| 4539 | * userspace racing mmap against close. However, the first external |
| 4540 | * reference to the filp can only be obtained through the |
| 4541 | * i915_gem_mmap_ioctl() which safeguards us against the user |
| 4542 | * acquiring such a reference whilst we are in the middle of |
| 4543 | * freeing the object. |
| 4544 | */ |
| 4545 | return atomic_long_read(&obj->base.filp->f_count) == 1; |
| 4546 | } |
| 4547 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4548 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4549 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4550 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4551 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4552 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4553 | struct i915_vma *vma, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4554 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4555 | intel_runtime_pm_get(dev_priv); |
| 4556 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 4557 | trace_i915_gem_object_destroy(obj); |
| 4558 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4559 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4560 | int ret; |
| 4561 | |
| 4562 | vma->pin_count = 0; |
| 4563 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4564 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4565 | bool was_interruptible; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4566 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4567 | was_interruptible = dev_priv->mm.interruptible; |
| 4568 | dev_priv->mm.interruptible = false; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4569 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4570 | WARN_ON(i915_vma_unbind(vma)); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4571 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4572 | dev_priv->mm.interruptible = was_interruptible; |
| 4573 | } |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4574 | } |
| 4575 | |
Ben Widawsky | 1d64ae7 | 2013-05-31 14:46:20 -0700 | [diff] [blame] | 4576 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4577 | * before progressing. */ |
| 4578 | if (obj->stolen) |
| 4579 | i915_gem_object_unpin_pages(obj); |
| 4580 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 4581 | WARN_ON(obj->frontbuffer_bits); |
| 4582 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4583 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
| 4584 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
| 4585 | obj->tiling_mode != I915_TILING_NONE) |
| 4586 | i915_gem_object_unpin_pages(obj); |
| 4587 | |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 4588 | if (WARN_ON(obj->pages_pin_count)) |
| 4589 | obj->pages_pin_count = 0; |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4590 | if (discard_backing_storage(obj)) |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 4591 | obj->madv = I915_MADV_DONTNEED; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4592 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 4593 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4594 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 4595 | BUG_ON(obj->pages); |
| 4596 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 4597 | if (obj->base.import_attach) |
| 4598 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4599 | |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 4600 | if (obj->ops->release) |
| 4601 | obj->ops->release(obj); |
| 4602 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4603 | drm_gem_object_release(&obj->base); |
| 4604 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4605 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4606 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4607 | i915_gem_object_free(obj); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4608 | |
| 4609 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4610 | } |
| 4611 | |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4612 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4613 | struct i915_address_space *vm) |
| 4614 | { |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4615 | struct i915_vma *vma; |
| 4616 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4617 | if (vma->vm == vm) |
| 4618 | return vma; |
| 4619 | |
| 4620 | return NULL; |
| 4621 | } |
| 4622 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4623 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4624 | { |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4625 | struct i915_address_space *vm = NULL; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4626 | WARN_ON(vma->node.allocated); |
Chris Wilson | aaa0566 | 2013-08-20 12:56:40 +0100 | [diff] [blame] | 4627 | |
| 4628 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4629 | if (!list_empty(&vma->exec_list)) |
| 4630 | return; |
| 4631 | |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4632 | vm = vma->vm; |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4633 | |
Daniel Vetter | 841cd77 | 2014-08-06 15:04:48 +0200 | [diff] [blame] | 4634 | if (!i915_is_ggtt(vm)) |
| 4635 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4636 | |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 4637 | list_del(&vma->vma_link); |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 4638 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4639 | kfree(vma); |
| 4640 | } |
| 4641 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4642 | static void |
| 4643 | i915_gem_stop_ringbuffers(struct drm_device *dev) |
| 4644 | { |
| 4645 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4646 | struct intel_engine_cs *ring; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4647 | int i; |
| 4648 | |
| 4649 | for_each_ring(ring, dev_priv, i) |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4650 | dev_priv->gt.stop_ring(ring); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4651 | } |
| 4652 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4653 | int |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4654 | i915_gem_suspend(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4655 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4656 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4657 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4658 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4659 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4660 | ret = i915_gpu_idle(dev); |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4661 | if (ret) |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4662 | goto err; |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4663 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4664 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4665 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4666 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 4667 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4668 | i915_gem_evict_everything(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4669 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4670 | i915_gem_stop_ringbuffers(dev); |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4671 | mutex_unlock(&dev->struct_mutex); |
| 4672 | |
| 4673 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4674 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
Deepak S | 274fa1c | 2014-08-05 07:51:20 -0700 | [diff] [blame] | 4675 | flush_delayed_work(&dev_priv->mm.idle_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4676 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4677 | return 0; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4678 | |
| 4679 | err: |
| 4680 | mutex_unlock(&dev->struct_mutex); |
| 4681 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4682 | } |
| 4683 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4684 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4685 | { |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4686 | struct drm_device *dev = ring->dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4687 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 4688 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
| 4689 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4690 | int i, ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4691 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 4692 | if (!HAS_L3_DPF(dev) || !remap_info) |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4693 | return 0; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4694 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4695 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
| 4696 | if (ret) |
| 4697 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4698 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4699 | /* |
| 4700 | * Note: We do not worry about the concurrent register cacheline hang |
| 4701 | * here because no other code should access these registers other than |
| 4702 | * at initialization time. |
| 4703 | */ |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4704 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4705 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 4706 | intel_ring_emit(ring, reg_base + i); |
| 4707 | intel_ring_emit(ring, remap_info[i/4]); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4708 | } |
| 4709 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4710 | intel_ring_advance(ring); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4711 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4712 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4713 | } |
| 4714 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4715 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4716 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4717 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4718 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4719 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4720 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4721 | return; |
| 4722 | |
| 4723 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4724 | DISP_TILE_SURFACE_SWIZZLING); |
| 4725 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4726 | if (IS_GEN5(dev)) |
| 4727 | return; |
| 4728 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4729 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4730 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4731 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4732 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4733 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 31a5336 | 2013-11-02 21:07:04 -0700 | [diff] [blame] | 4734 | else if (IS_GEN8(dev)) |
| 4735 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4736 | else |
| 4737 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4738 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4739 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4740 | static bool |
| 4741 | intel_enable_blt(struct drm_device *dev) |
| 4742 | { |
| 4743 | if (!HAS_BLT(dev)) |
| 4744 | return false; |
| 4745 | |
| 4746 | /* The blitter was dysfunctional on early prototypes */ |
| 4747 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 4748 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 4749 | " graphics performance will be degraded.\n"); |
| 4750 | return false; |
| 4751 | } |
| 4752 | |
| 4753 | return true; |
| 4754 | } |
| 4755 | |
Ville Syrjälä | 81e7f20 | 2014-08-15 01:21:55 +0300 | [diff] [blame] | 4756 | static void init_unused_ring(struct drm_device *dev, u32 base) |
| 4757 | { |
| 4758 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4759 | |
| 4760 | I915_WRITE(RING_CTL(base), 0); |
| 4761 | I915_WRITE(RING_HEAD(base), 0); |
| 4762 | I915_WRITE(RING_TAIL(base), 0); |
| 4763 | I915_WRITE(RING_START(base), 0); |
| 4764 | } |
| 4765 | |
| 4766 | static void init_unused_rings(struct drm_device *dev) |
| 4767 | { |
| 4768 | if (IS_I830(dev)) { |
| 4769 | init_unused_ring(dev, PRB1_BASE); |
| 4770 | init_unused_ring(dev, SRB0_BASE); |
| 4771 | init_unused_ring(dev, SRB1_BASE); |
| 4772 | init_unused_ring(dev, SRB2_BASE); |
| 4773 | init_unused_ring(dev, SRB3_BASE); |
| 4774 | } else if (IS_GEN2(dev)) { |
| 4775 | init_unused_ring(dev, SRB0_BASE); |
| 4776 | init_unused_ring(dev, SRB1_BASE); |
| 4777 | } else if (IS_GEN3(dev)) { |
| 4778 | init_unused_ring(dev, PRB1_BASE); |
| 4779 | init_unused_ring(dev, PRB2_BASE); |
| 4780 | } |
| 4781 | } |
| 4782 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4783 | int i915_gem_init_rings(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4784 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4785 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4786 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4787 | |
Ville Syrjälä | 81e7f20 | 2014-08-15 01:21:55 +0300 | [diff] [blame] | 4788 | /* |
| 4789 | * At least 830 can leave some of the unused rings |
| 4790 | * "active" (ie. head != tail) after resume which |
| 4791 | * will prevent c3 entry. Makes sure all unused rings |
| 4792 | * are totally idle. |
| 4793 | */ |
| 4794 | init_unused_rings(dev); |
| 4795 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4796 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4797 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4798 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4799 | |
| 4800 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4801 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4802 | if (ret) |
| 4803 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4804 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4805 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4806 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4807 | ret = intel_init_blt_ring_buffer(dev); |
| 4808 | if (ret) |
| 4809 | goto cleanup_bsd_ring; |
| 4810 | } |
| 4811 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4812 | if (HAS_VEBOX(dev)) { |
| 4813 | ret = intel_init_vebox_ring_buffer(dev); |
| 4814 | if (ret) |
| 4815 | goto cleanup_blt_ring; |
| 4816 | } |
| 4817 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4818 | if (HAS_BSD2(dev)) { |
| 4819 | ret = intel_init_bsd2_ring_buffer(dev); |
| 4820 | if (ret) |
| 4821 | goto cleanup_vebox_ring; |
| 4822 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4823 | |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4824 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 4825 | if (ret) |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4826 | goto cleanup_bsd2_ring; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4827 | |
| 4828 | return 0; |
| 4829 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4830 | cleanup_bsd2_ring: |
| 4831 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4832 | cleanup_vebox_ring: |
| 4833 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4834 | cleanup_blt_ring: |
| 4835 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 4836 | cleanup_bsd_ring: |
| 4837 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 4838 | cleanup_render_ring: |
| 4839 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 4840 | |
| 4841 | return ret; |
| 4842 | } |
| 4843 | |
| 4844 | int |
| 4845 | i915_gem_init_hw(struct drm_device *dev) |
| 4846 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4847 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 4848 | int ret, i; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4849 | |
| 4850 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 4851 | return -EIO; |
| 4852 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 4853 | if (dev_priv->ellc_size) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 4854 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4855 | |
Ville Syrjälä | 0bf2134 | 2013-11-29 14:56:12 +0200 | [diff] [blame] | 4856 | if (IS_HASWELL(dev)) |
| 4857 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 4858 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 4859 | |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4860 | if (HAS_PCH_NOP(dev)) { |
Daniel Vetter | 6ba844b | 2014-01-22 23:39:30 +0100 | [diff] [blame] | 4861 | if (IS_IVYBRIDGE(dev)) { |
| 4862 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4863 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4864 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4865 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 4866 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 4867 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 4868 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 4869 | } |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4870 | } |
| 4871 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4872 | i915_gem_init_swizzling(dev); |
| 4873 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4874 | ret = dev_priv->gt.init_rings(dev); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4875 | if (ret) |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4876 | return ret; |
| 4877 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4878 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
| 4879 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); |
| 4880 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4881 | /* |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4882 | * XXX: Contexts should only be initialized once. Doing a switch to the |
| 4883 | * default context switch however is something we'd like to do after |
| 4884 | * reset or thaw (the latter may not actually be necessary for HW, but |
| 4885 | * goes with our code better). Context switching requires rings (for |
| 4886 | * the do_switch), but before enabling PPGTT. So don't move this. |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4887 | */ |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4888 | ret = i915_gem_context_enable(dev_priv); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4889 | if (ret && ret != -EIO) { |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4890 | DRM_ERROR("Context enable failed %d\n", ret); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4891 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 4892 | |
| 4893 | return ret; |
| 4894 | } |
| 4895 | |
| 4896 | ret = i915_ppgtt_init_hw(dev); |
| 4897 | if (ret && ret != -EIO) { |
| 4898 | DRM_ERROR("PPGTT enable failed %d\n", ret); |
| 4899 | i915_gem_cleanup_ringbuffer(dev); |
Ben Widawsky | b7c36d2 | 2013-04-08 18:43:56 -0700 | [diff] [blame] | 4900 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4901 | |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4902 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4903 | } |
| 4904 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4905 | int i915_gem_init(struct drm_device *dev) |
| 4906 | { |
| 4907 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4908 | int ret; |
| 4909 | |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 4910 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
| 4911 | i915.enable_execlists); |
| 4912 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4913 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4914 | |
| 4915 | if (IS_VALLEYVIEW(dev)) { |
| 4916 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
Imre Deak | 981a5ae | 2014-04-14 20:24:22 +0300 | [diff] [blame] | 4917 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
| 4918 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & |
| 4919 | VLV_GTLC_ALLOWWAKEACK), 10)) |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4920 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 4921 | } |
| 4922 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4923 | if (!i915.enable_execlists) { |
| 4924 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; |
| 4925 | dev_priv->gt.init_rings = i915_gem_init_rings; |
| 4926 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; |
| 4927 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 4928 | } else { |
| 4929 | dev_priv->gt.do_execbuf = intel_execlists_submission; |
| 4930 | dev_priv->gt.init_rings = intel_logical_rings_init; |
| 4931 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; |
| 4932 | dev_priv->gt.stop_ring = intel_logical_ring_stop; |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4933 | } |
| 4934 | |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 4935 | ret = i915_gem_init_userptr(dev); |
| 4936 | if (ret) { |
| 4937 | mutex_unlock(&dev->struct_mutex); |
| 4938 | return ret; |
| 4939 | } |
| 4940 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 4941 | i915_gem_init_global_gtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4942 | |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4943 | ret = i915_gem_context_init(dev); |
Mika Kuoppala | e384869 | 2014-01-31 17:14:02 +0200 | [diff] [blame] | 4944 | if (ret) { |
| 4945 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4946 | return ret; |
Mika Kuoppala | e384869 | 2014-01-31 17:14:02 +0200 | [diff] [blame] | 4947 | } |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4948 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4949 | ret = i915_gem_init_hw(dev); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4950 | if (ret == -EIO) { |
| 4951 | /* Allow ring initialisation to fail by marking the GPU as |
| 4952 | * wedged. But we only want to do this where the GPU is angry, |
| 4953 | * for all other failure, such as an allocation failure, bail. |
| 4954 | */ |
| 4955 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
| 4956 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
| 4957 | ret = 0; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4958 | } |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4959 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4960 | |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4961 | return ret; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4962 | } |
| 4963 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4964 | void |
| 4965 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4966 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4967 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4968 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4969 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4970 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4971 | for_each_ring(ring, dev_priv, i) |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4972 | dev_priv->gt.cleanup_ring(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4973 | } |
| 4974 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4975 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4976 | init_ring_lists(struct intel_engine_cs *ring) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4977 | { |
| 4978 | INIT_LIST_HEAD(&ring->active_list); |
| 4979 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4980 | } |
| 4981 | |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 4982 | void i915_init_vm(struct drm_i915_private *dev_priv, |
| 4983 | struct i915_address_space *vm) |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4984 | { |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 4985 | if (!i915_is_ggtt(vm)) |
| 4986 | drm_mm_init(&vm->mm, vm->start, vm->total); |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4987 | vm->dev = dev_priv->dev; |
| 4988 | INIT_LIST_HEAD(&vm->active_list); |
| 4989 | INIT_LIST_HEAD(&vm->inactive_list); |
| 4990 | INIT_LIST_HEAD(&vm->global_link); |
Chris Wilson | f72d21e | 2014-01-09 22:57:22 +0000 | [diff] [blame] | 4991 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4992 | } |
| 4993 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4994 | void |
| 4995 | i915_gem_load(struct drm_device *dev) |
| 4996 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4997 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4998 | int i; |
| 4999 | |
| 5000 | dev_priv->slab = |
| 5001 | kmem_cache_create("i915_gem_object", |
| 5002 | sizeof(struct drm_i915_gem_object), 0, |
| 5003 | SLAB_HWCACHE_ALIGN, |
| 5004 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5005 | |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 5006 | INIT_LIST_HEAD(&dev_priv->vm_list); |
| 5007 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
| 5008 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 5009 | INIT_LIST_HEAD(&dev_priv->context_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 5010 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 5011 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 5012 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 5013 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 5014 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 5015 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 5016 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5017 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 5018 | i915_gem_retire_work_handler); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5019 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 5020 | i915_gem_idle_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 5021 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5022 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 5023 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
Ville Syrjälä | dbb4274 | 2014-02-25 15:13:41 +0200 | [diff] [blame] | 5024 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 5025 | I915_WRITE(MI_ARB_STATE, |
| 5026 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 5027 | } |
| 5028 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 5029 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 5030 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 5031 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 5032 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 5033 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 5034 | |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 5035 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
| 5036 | dev_priv->num_fence_regs = 32; |
| 5037 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 5038 | dev_priv->num_fence_regs = 16; |
| 5039 | else |
| 5040 | dev_priv->num_fence_regs = 8; |
| 5041 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 5042 | /* Initialize fence registers to zero */ |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 5043 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 5044 | i915_gem_restore_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 5045 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5046 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5047 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5048 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 5049 | dev_priv->mm.interruptible = true; |
| 5050 | |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5051 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
| 5052 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; |
| 5053 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; |
| 5054 | register_shrinker(&dev_priv->mm.shrinker); |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5055 | |
| 5056 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; |
| 5057 | register_oom_notifier(&dev_priv->mm.oom_notifier); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 5058 | |
| 5059 | mutex_init(&dev_priv->fb_tracking.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5060 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5061 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5062 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5063 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5064 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5065 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5066 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
| 5067 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5068 | /* Clean up our request list when the client is going away, so that |
| 5069 | * later retire_requests won't dereference our soon-to-be-gone |
| 5070 | * file_priv. |
| 5071 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5072 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5073 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5074 | struct drm_i915_gem_request *request; |
| 5075 | |
| 5076 | request = list_first_entry(&file_priv->mm.request_list, |
| 5077 | struct drm_i915_gem_request, |
| 5078 | client_list); |
| 5079 | list_del(&request->client_list); |
| 5080 | request->file_priv = NULL; |
| 5081 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5082 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5083 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5084 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5085 | static void |
| 5086 | i915_gem_file_idle_work_handler(struct work_struct *work) |
| 5087 | { |
| 5088 | struct drm_i915_file_private *file_priv = |
| 5089 | container_of(work, typeof(*file_priv), mm.idle_work.work); |
| 5090 | |
| 5091 | atomic_set(&file_priv->rps_wait_boost, false); |
| 5092 | } |
| 5093 | |
| 5094 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 5095 | { |
| 5096 | struct drm_i915_file_private *file_priv; |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5097 | int ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5098 | |
| 5099 | DRM_DEBUG_DRIVER("\n"); |
| 5100 | |
| 5101 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 5102 | if (!file_priv) |
| 5103 | return -ENOMEM; |
| 5104 | |
| 5105 | file->driver_priv = file_priv; |
| 5106 | file_priv->dev_priv = dev->dev_private; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 5107 | file_priv->file = file; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5108 | |
| 5109 | spin_lock_init(&file_priv->mm.lock); |
| 5110 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
| 5111 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, |
| 5112 | i915_gem_file_idle_work_handler); |
| 5113 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5114 | ret = i915_gem_context_open(dev, file); |
| 5115 | if (ret) |
| 5116 | kfree(file_priv); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5117 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5118 | return ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5119 | } |
| 5120 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 5121 | /** |
| 5122 | * i915_gem_track_fb - update frontbuffer tracking |
| 5123 | * old: current GEM buffer for the frontbuffer slots |
| 5124 | * new: new GEM buffer for the frontbuffer slots |
| 5125 | * frontbuffer_bits: bitmask of frontbuffer slots |
| 5126 | * |
| 5127 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them |
| 5128 | * from @old and setting them in @new. Both @old and @new can be NULL. |
| 5129 | */ |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 5130 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 5131 | struct drm_i915_gem_object *new, |
| 5132 | unsigned frontbuffer_bits) |
| 5133 | { |
| 5134 | if (old) { |
| 5135 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
| 5136 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
| 5137 | old->frontbuffer_bits &= ~frontbuffer_bits; |
| 5138 | } |
| 5139 | |
| 5140 | if (new) { |
| 5141 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
| 5142 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
| 5143 | new->frontbuffer_bits |= frontbuffer_bits; |
| 5144 | } |
| 5145 | } |
| 5146 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 5147 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
| 5148 | { |
| 5149 | if (!mutex_is_locked(mutex)) |
| 5150 | return false; |
| 5151 | |
| 5152 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
| 5153 | return mutex->owner == task; |
| 5154 | #else |
| 5155 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
| 5156 | return false; |
| 5157 | #endif |
| 5158 | } |
| 5159 | |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5160 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
| 5161 | { |
| 5162 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 5163 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) |
| 5164 | return false; |
| 5165 | |
| 5166 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) |
| 5167 | return false; |
| 5168 | |
| 5169 | *unlock = false; |
| 5170 | } else |
| 5171 | *unlock = true; |
| 5172 | |
| 5173 | return true; |
| 5174 | } |
| 5175 | |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5176 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
| 5177 | { |
| 5178 | struct i915_vma *vma; |
| 5179 | int count = 0; |
| 5180 | |
| 5181 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 5182 | if (drm_mm_node_allocated(&vma->node)) |
| 5183 | count++; |
| 5184 | |
| 5185 | return count; |
| 5186 | } |
| 5187 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5188 | static unsigned long |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5189 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5190 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5191 | struct drm_i915_private *dev_priv = |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5192 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5193 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 5194 | struct drm_i915_gem_object *obj; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5195 | unsigned long count; |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5196 | bool unlock; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5197 | |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5198 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
| 5199 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5200 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5201 | count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 5202 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 5203 | if (obj->pages_pin_count == 0) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5204 | count += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | fcb4a57 | 2013-07-31 16:59:57 -0700 | [diff] [blame] | 5205 | |
| 5206 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5207 | if (!i915_gem_obj_is_pinned(obj) && |
| 5208 | obj->pages_pin_count == num_vma_bound(obj)) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5209 | count += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | fcb4a57 | 2013-07-31 16:59:57 -0700 | [diff] [blame] | 5210 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5211 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 5212 | if (unlock) |
| 5213 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 5214 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5215 | return count; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5216 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5217 | |
| 5218 | /* All the new VM stuff */ |
| 5219 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 5220 | struct i915_address_space *vm) |
| 5221 | { |
| 5222 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5223 | struct i915_vma *vma; |
| 5224 | |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 5225 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5226 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5227 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 5228 | if (vma->vm == vm) |
| 5229 | return vma->node.start; |
| 5230 | |
| 5231 | } |
Daniel Vetter | f25748ea | 2014-06-17 22:34:38 +0200 | [diff] [blame] | 5232 | WARN(1, "%s vma for this object not found.\n", |
| 5233 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5234 | return -1; |
| 5235 | } |
| 5236 | |
| 5237 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 5238 | struct i915_address_space *vm) |
| 5239 | { |
| 5240 | struct i915_vma *vma; |
| 5241 | |
| 5242 | list_for_each_entry(vma, &o->vma_list, vma_link) |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 5243 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5244 | return true; |
| 5245 | |
| 5246 | return false; |
| 5247 | } |
| 5248 | |
| 5249 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 5250 | { |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5251 | struct i915_vma *vma; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5252 | |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5253 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5254 | if (drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5255 | return true; |
| 5256 | |
| 5257 | return false; |
| 5258 | } |
| 5259 | |
| 5260 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 5261 | struct i915_address_space *vm) |
| 5262 | { |
| 5263 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5264 | struct i915_vma *vma; |
| 5265 | |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 5266 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5267 | |
| 5268 | BUG_ON(list_empty(&o->vma_list)); |
| 5269 | |
| 5270 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5271 | if (vma->vm == vm) |
| 5272 | return vma->node.size; |
| 5273 | |
| 5274 | return 0; |
| 5275 | } |
| 5276 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5277 | static unsigned long |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5278 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5279 | { |
| 5280 | struct drm_i915_private *dev_priv = |
Chris Wilson | ceabbba5 | 2014-03-25 13:23:04 +0000 | [diff] [blame] | 5281 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5282 | struct drm_device *dev = dev_priv->dev; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5283 | unsigned long freed; |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5284 | bool unlock; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5285 | |
Chris Wilson | b453c4d | 2014-03-25 13:23:05 +0000 | [diff] [blame] | 5286 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
| 5287 | return SHRINK_STOP; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5288 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 5289 | freed = i915_gem_shrink(dev_priv, |
| 5290 | sc->nr_to_scan, |
| 5291 | I915_SHRINK_BOUND | |
| 5292 | I915_SHRINK_UNBOUND | |
| 5293 | I915_SHRINK_PURGEABLE); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 5294 | if (freed < sc->nr_to_scan) |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 5295 | freed += i915_gem_shrink(dev_priv, |
| 5296 | sc->nr_to_scan - freed, |
| 5297 | I915_SHRINK_BOUND | |
| 5298 | I915_SHRINK_UNBOUND); |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5299 | if (unlock) |
| 5300 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 5301 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5302 | return freed; |
| 5303 | } |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5304 | |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5305 | static int |
| 5306 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) |
| 5307 | { |
| 5308 | struct drm_i915_private *dev_priv = |
| 5309 | container_of(nb, struct drm_i915_private, mm.oom_notifier); |
| 5310 | struct drm_device *dev = dev_priv->dev; |
| 5311 | struct drm_i915_gem_object *obj; |
| 5312 | unsigned long timeout = msecs_to_jiffies(5000) + 1; |
Chris Wilson | 005445c | 2014-10-08 11:25:16 +0100 | [diff] [blame] | 5313 | unsigned long pinned, bound, unbound, freed_pages; |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5314 | bool was_interruptible; |
| 5315 | bool unlock; |
| 5316 | |
Chris Wilson | a1db2fa | 2014-07-11 11:28:00 +0100 | [diff] [blame] | 5317 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5318 | schedule_timeout_killable(1); |
Chris Wilson | a1db2fa | 2014-07-11 11:28:00 +0100 | [diff] [blame] | 5319 | if (fatal_signal_pending(current)) |
| 5320 | return NOTIFY_DONE; |
| 5321 | } |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5322 | if (timeout == 0) { |
| 5323 | pr_err("Unable to purge GPU memory due lock contention.\n"); |
| 5324 | return NOTIFY_DONE; |
| 5325 | } |
| 5326 | |
| 5327 | was_interruptible = dev_priv->mm.interruptible; |
| 5328 | dev_priv->mm.interruptible = false; |
| 5329 | |
Chris Wilson | 005445c | 2014-10-08 11:25:16 +0100 | [diff] [blame] | 5330 | freed_pages = i915_gem_shrink_all(dev_priv); |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5331 | |
| 5332 | dev_priv->mm.interruptible = was_interruptible; |
| 5333 | |
| 5334 | /* Because we may be allocating inside our own driver, we cannot |
| 5335 | * assert that there are no objects with pinned pages that are not |
| 5336 | * being pointed to by hardware. |
| 5337 | */ |
| 5338 | unbound = bound = pinned = 0; |
| 5339 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 5340 | if (!obj->base.filp) /* not backed by a freeable object */ |
| 5341 | continue; |
| 5342 | |
| 5343 | if (obj->pages_pin_count) |
| 5344 | pinned += obj->base.size; |
| 5345 | else |
| 5346 | unbound += obj->base.size; |
| 5347 | } |
| 5348 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 5349 | if (!obj->base.filp) |
| 5350 | continue; |
| 5351 | |
| 5352 | if (obj->pages_pin_count) |
| 5353 | pinned += obj->base.size; |
| 5354 | else |
| 5355 | bound += obj->base.size; |
| 5356 | } |
| 5357 | |
| 5358 | if (unlock) |
| 5359 | mutex_unlock(&dev->struct_mutex); |
| 5360 | |
Chris Wilson | bb9059d | 2014-10-08 11:25:17 +0100 | [diff] [blame] | 5361 | if (freed_pages || unbound || bound) |
| 5362 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", |
| 5363 | freed_pages << PAGE_SHIFT, pinned); |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5364 | if (unbound || bound) |
| 5365 | pr_err("%lu and %lu bytes still available in the " |
| 5366 | "bound and unbound GPU page lists.\n", |
| 5367 | bound, unbound); |
| 5368 | |
Chris Wilson | 005445c | 2014-10-08 11:25:16 +0100 | [diff] [blame] | 5369 | *(unsigned long *)ptr += freed_pages; |
Chris Wilson | 2cfcd32 | 2014-05-20 08:28:43 +0100 | [diff] [blame] | 5370 | return NOTIFY_DONE; |
| 5371 | } |
| 5372 | |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5373 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
| 5374 | { |
| 5375 | struct i915_vma *vma; |
| 5376 | |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5377 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
Daniel Vetter | 5dc383b | 2014-08-06 15:04:49 +0200 | [diff] [blame] | 5378 | if (vma->vm != i915_obj_to_ggtt(obj)) |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5379 | return NULL; |
| 5380 | |
| 5381 | return vma; |
| 5382 | } |