blob: 9d362d320d824cddac9c33b5ce39905017d60ac2 [file] [log] [blame]
Eric Anholt673a3942008-07-30 12:06:12 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
David Herrmann0de23972013-07-24 21:07:52 +020029#include <drm/drm_vma_manager.h>
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/i915_drm.h>
Eric Anholt673a3942008-07-30 12:06:12 -070031#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010032#include "i915_trace.h"
Jesse Barnes652c3932009-08-17 13:31:43 -070033#include "intel_drv.h"
Chris Wilson2cfcd322014-05-20 08:28:43 +010034#include <linux/oom.h>
Hugh Dickins5949eac2011-06-27 16:18:18 -070035#include <linux/shmem_fs.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090036#include <linux/slab.h>
Eric Anholt673a3942008-07-30 12:06:12 -070037#include <linux/swap.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include <linux/pci.h>
Daniel Vetter1286ff72012-05-10 15:25:09 +020039#include <linux/dma-buf.h>
Eric Anholt673a3942008-07-30 12:06:12 -070040
Chris Wilson05394f32010-11-08 19:18:58 +000041static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
Chris Wilson2c225692013-08-09 12:26:45 +010042static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
43 bool force);
Ben Widawsky07fe0b12013-07-31 17:00:10 -070044static __must_check int
Ben Widawsky23f54482013-09-11 14:57:48 -070045i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 bool readonly);
Chris Wilsonc8725f32014-03-17 12:21:55 +000047static void
48i915_gem_object_retire(struct drm_i915_gem_object *obj);
49
Chris Wilson61050802012-04-17 15:31:31 +010050static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
54 bool enable);
55
Chris Wilsonceabbba52014-03-25 13:23:04 +000056static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
Dave Chinner7dc19d52013-08-28 10:18:11 +100057 struct shrink_control *sc);
Chris Wilsonceabbba52014-03-25 13:23:04 +000058static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
Dave Chinner7dc19d52013-08-28 10:18:11 +100059 struct shrink_control *sc);
Chris Wilson2cfcd322014-05-20 08:28:43 +010060static int i915_gem_shrinker_oom(struct notifier_block *nb,
61 unsigned long event,
62 void *ptr);
Chris Wilsond9973b42013-10-04 10:33:00 +010063static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
Chris Wilson31169712009-09-14 16:50:28 +010064
Chris Wilsonc76ce032013-08-08 14:41:03 +010065static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
67{
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
69}
70
Chris Wilson2c225692013-08-09 12:26:45 +010071static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
72{
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
74 return true;
75
76 return obj->pin_display;
77}
78
Chris Wilson61050802012-04-17 15:31:31 +010079static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
80{
81 if (obj->tiling_mode)
82 i915_gem_release_mmap(obj);
83
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
86 */
Chris Wilson5d82e3e2012-04-21 16:23:23 +010087 obj->fence_dirty = false;
Chris Wilson61050802012-04-17 15:31:31 +010088 obj->fence_reg = I915_FENCE_REG_NONE;
89}
90
Chris Wilson73aa8082010-09-30 11:46:12 +010091/* some bookkeeping */
92static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
93 size_t size)
94{
Daniel Vetterc20e8352013-07-24 22:40:23 +020095 spin_lock(&dev_priv->mm.object_stat_lock);
Chris Wilson73aa8082010-09-30 11:46:12 +010096 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
Daniel Vetterc20e8352013-07-24 22:40:23 +020098 spin_unlock(&dev_priv->mm.object_stat_lock);
Chris Wilson73aa8082010-09-30 11:46:12 +010099}
100
101static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
102 size_t size)
103{
Daniel Vetterc20e8352013-07-24 22:40:23 +0200104 spin_lock(&dev_priv->mm.object_stat_lock);
Chris Wilson73aa8082010-09-30 11:46:12 +0100105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
Daniel Vetterc20e8352013-07-24 22:40:23 +0200107 spin_unlock(&dev_priv->mm.object_stat_lock);
Chris Wilson73aa8082010-09-30 11:46:12 +0100108}
109
Chris Wilson21dd3732011-01-26 15:55:56 +0000110static int
Daniel Vetter33196de2012-11-14 17:14:05 +0100111i915_gem_wait_for_error(struct i915_gpu_error *error)
Chris Wilson30dbf0c2010-09-25 10:19:17 +0100112{
Chris Wilson30dbf0c2010-09-25 10:19:17 +0100113 int ret;
114
Daniel Vetter7abb6902013-05-24 21:29:32 +0200115#define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100117 if (EXIT_COND)
Chris Wilson30dbf0c2010-09-25 10:19:17 +0100118 return 0;
119
Daniel Vetter0a6759c2012-07-04 22:18:41 +0200120 /*
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
124 */
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100125 ret = wait_event_interruptible_timeout(error->reset_queue,
126 EXIT_COND,
127 10*HZ);
Daniel Vetter0a6759c2012-07-04 22:18:41 +0200128 if (ret == 0) {
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
130 return -EIO;
131 } else if (ret < 0) {
Chris Wilson30dbf0c2010-09-25 10:19:17 +0100132 return ret;
Daniel Vetter0a6759c2012-07-04 22:18:41 +0200133 }
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100134#undef EXIT_COND
Chris Wilson30dbf0c2010-09-25 10:19:17 +0100135
Chris Wilson21dd3732011-01-26 15:55:56 +0000136 return 0;
Chris Wilson30dbf0c2010-09-25 10:19:17 +0100137}
138
Chris Wilson54cf91d2010-11-25 18:00:26 +0000139int i915_mutex_lock_interruptible(struct drm_device *dev)
Chris Wilson76c1dec2010-09-25 11:22:51 +0100140{
Daniel Vetter33196de2012-11-14 17:14:05 +0100141 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson76c1dec2010-09-25 11:22:51 +0100142 int ret;
143
Daniel Vetter33196de2012-11-14 17:14:05 +0100144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
Chris Wilson76c1dec2010-09-25 11:22:51 +0100145 if (ret)
146 return ret;
147
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
149 if (ret)
150 return ret;
151
Chris Wilson23bc5982010-09-29 16:10:57 +0100152 WARN_ON(i915_verify_lists(dev));
Chris Wilson76c1dec2010-09-25 11:22:51 +0100153 return 0;
154}
Chris Wilson30dbf0c2010-09-25 10:19:17 +0100155
Chris Wilson7d1c4802010-08-07 21:45:03 +0100156static inline bool
Chris Wilson05394f32010-11-08 19:18:58 +0000157i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
Chris Wilson7d1c4802010-08-07 21:45:03 +0100158{
Ben Widawsky98438772013-07-31 17:00:12 -0700159 return i915_gem_obj_bound_any(obj) && !obj->active;
Chris Wilson7d1c4802010-08-07 21:45:03 +0100160}
161
Eric Anholt673a3942008-07-30 12:06:12 -0700162int
Eric Anholt5a125c32008-10-22 21:40:13 -0700163i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +0000164 struct drm_file *file)
Eric Anholt5a125c32008-10-22 21:40:13 -0700165{
Chris Wilson73aa8082010-09-30 11:46:12 +0100166 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt5a125c32008-10-22 21:40:13 -0700167 struct drm_i915_gem_get_aperture *args = data;
Chris Wilson6299f992010-11-24 12:23:44 +0000168 struct drm_i915_gem_object *obj;
169 size_t pinned;
Eric Anholt5a125c32008-10-22 21:40:13 -0700170
Chris Wilson6299f992010-11-24 12:23:44 +0000171 pinned = 0;
Chris Wilson73aa8082010-09-30 11:46:12 +0100172 mutex_lock(&dev->struct_mutex);
Ben Widawsky35c20a62013-05-31 11:28:48 -0700173 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800174 if (i915_gem_obj_is_pinned(obj))
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700175 pinned += i915_gem_obj_ggtt_size(obj);
Chris Wilson73aa8082010-09-30 11:46:12 +0100176 mutex_unlock(&dev->struct_mutex);
Eric Anholt5a125c32008-10-22 21:40:13 -0700177
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700178 args->aper_size = dev_priv->gtt.base.total;
Akshay Joshi0206e352011-08-16 15:34:10 -0400179 args->aper_available_size = args->aper_size - pinned;
Chris Wilson6299f992010-11-24 12:23:44 +0000180
Eric Anholt5a125c32008-10-22 21:40:13 -0700181 return 0;
182}
183
Chris Wilson6a2c4232014-11-04 04:51:40 -0800184static int
185i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
Chris Wilson00731152014-05-21 12:42:56 +0100186{
Chris Wilson6a2c4232014-11-04 04:51:40 -0800187 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
188 char *vaddr = obj->phys_handle->vaddr;
189 struct sg_table *st;
190 struct scatterlist *sg;
191 int i;
Chris Wilson00731152014-05-21 12:42:56 +0100192
Chris Wilson6a2c4232014-11-04 04:51:40 -0800193 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
194 return -EINVAL;
Chris Wilson00731152014-05-21 12:42:56 +0100195
Chris Wilson6a2c4232014-11-04 04:51:40 -0800196 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
197 struct page *page;
198 char *src;
199
200 page = shmem_read_mapping_page(mapping, i);
201 if (IS_ERR(page))
202 return PTR_ERR(page);
203
204 src = kmap_atomic(page);
205 memcpy(vaddr, src, PAGE_SIZE);
206 drm_clflush_virt_range(vaddr, PAGE_SIZE);
207 kunmap_atomic(src);
208
209 page_cache_release(page);
210 vaddr += PAGE_SIZE;
211 }
212
213 i915_gem_chipset_flush(obj->base.dev);
214
215 st = kmalloc(sizeof(*st), GFP_KERNEL);
216 if (st == NULL)
217 return -ENOMEM;
218
219 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
220 kfree(st);
221 return -ENOMEM;
222 }
223
224 sg = st->sgl;
225 sg->offset = 0;
226 sg->length = obj->base.size;
227
228 sg_dma_address(sg) = obj->phys_handle->busaddr;
229 sg_dma_len(sg) = obj->base.size;
230
231 obj->pages = st;
232 obj->has_dma_mapping = true;
233 return 0;
234}
235
236static void
237i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
238{
239 int ret;
240
241 BUG_ON(obj->madv == __I915_MADV_PURGED);
242
243 ret = i915_gem_object_set_to_cpu_domain(obj, true);
244 if (ret) {
245 /* In the event of a disaster, abandon all caches and
246 * hope for the best.
247 */
248 WARN_ON(ret != -EIO);
249 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
250 }
251
252 if (obj->madv == I915_MADV_DONTNEED)
253 obj->dirty = 0;
254
255 if (obj->dirty) {
Chris Wilson00731152014-05-21 12:42:56 +0100256 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
Chris Wilson6a2c4232014-11-04 04:51:40 -0800257 char *vaddr = obj->phys_handle->vaddr;
Chris Wilson00731152014-05-21 12:42:56 +0100258 int i;
259
260 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
Chris Wilson6a2c4232014-11-04 04:51:40 -0800261 struct page *page;
262 char *dst;
Chris Wilson00731152014-05-21 12:42:56 +0100263
Chris Wilson6a2c4232014-11-04 04:51:40 -0800264 page = shmem_read_mapping_page(mapping, i);
265 if (IS_ERR(page))
266 continue;
267
268 dst = kmap_atomic(page);
269 drm_clflush_virt_range(vaddr, PAGE_SIZE);
270 memcpy(dst, vaddr, PAGE_SIZE);
271 kunmap_atomic(dst);
272
273 set_page_dirty(page);
274 if (obj->madv == I915_MADV_WILLNEED)
Chris Wilson00731152014-05-21 12:42:56 +0100275 mark_page_accessed(page);
Chris Wilson6a2c4232014-11-04 04:51:40 -0800276 page_cache_release(page);
Chris Wilson00731152014-05-21 12:42:56 +0100277 vaddr += PAGE_SIZE;
278 }
Chris Wilson6a2c4232014-11-04 04:51:40 -0800279 obj->dirty = 0;
Chris Wilson00731152014-05-21 12:42:56 +0100280 }
281
Chris Wilson6a2c4232014-11-04 04:51:40 -0800282 sg_free_table(obj->pages);
283 kfree(obj->pages);
284
285 obj->has_dma_mapping = false;
286}
287
288static void
289i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
290{
291 drm_pci_free(obj->base.dev, obj->phys_handle);
292}
293
294static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
295 .get_pages = i915_gem_object_get_pages_phys,
296 .put_pages = i915_gem_object_put_pages_phys,
297 .release = i915_gem_object_release_phys,
298};
299
300static int
301drop_pages(struct drm_i915_gem_object *obj)
302{
303 struct i915_vma *vma, *next;
304 int ret;
305
306 drm_gem_object_reference(&obj->base);
307 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
308 if (i915_vma_unbind(vma))
309 break;
310
311 ret = i915_gem_object_put_pages(obj);
312 drm_gem_object_unreference(&obj->base);
313
314 return ret;
Chris Wilson00731152014-05-21 12:42:56 +0100315}
316
317int
318i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
319 int align)
320{
321 drm_dma_handle_t *phys;
Chris Wilson6a2c4232014-11-04 04:51:40 -0800322 int ret;
Chris Wilson00731152014-05-21 12:42:56 +0100323
324 if (obj->phys_handle) {
325 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
326 return -EBUSY;
327
328 return 0;
329 }
330
331 if (obj->madv != I915_MADV_WILLNEED)
332 return -EFAULT;
333
334 if (obj->base.filp == NULL)
335 return -EINVAL;
336
Chris Wilson6a2c4232014-11-04 04:51:40 -0800337 ret = drop_pages(obj);
338 if (ret)
339 return ret;
340
Chris Wilson00731152014-05-21 12:42:56 +0100341 /* create a new object */
342 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
343 if (!phys)
344 return -ENOMEM;
345
Chris Wilson00731152014-05-21 12:42:56 +0100346 obj->phys_handle = phys;
Chris Wilson6a2c4232014-11-04 04:51:40 -0800347 obj->ops = &i915_gem_phys_ops;
348
349 return i915_gem_object_get_pages(obj);
Chris Wilson00731152014-05-21 12:42:56 +0100350}
351
352static int
353i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
354 struct drm_i915_gem_pwrite *args,
355 struct drm_file *file_priv)
356{
357 struct drm_device *dev = obj->base.dev;
358 void *vaddr = obj->phys_handle->vaddr + args->offset;
359 char __user *user_data = to_user_ptr(args->data_ptr);
Chris Wilson6a2c4232014-11-04 04:51:40 -0800360 int ret;
361
362 /* We manually control the domain here and pretend that it
363 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
364 */
365 ret = i915_gem_object_wait_rendering(obj, false);
366 if (ret)
367 return ret;
Chris Wilson00731152014-05-21 12:42:56 +0100368
369 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
370 unsigned long unwritten;
371
372 /* The physical object once assigned is fixed for the lifetime
373 * of the obj, so we can safely drop the lock and continue
374 * to access vaddr.
375 */
376 mutex_unlock(&dev->struct_mutex);
377 unwritten = copy_from_user(vaddr, user_data, args->size);
378 mutex_lock(&dev->struct_mutex);
379 if (unwritten)
380 return -EFAULT;
381 }
382
Chris Wilson6a2c4232014-11-04 04:51:40 -0800383 drm_clflush_virt_range(vaddr, args->size);
Chris Wilson00731152014-05-21 12:42:56 +0100384 i915_gem_chipset_flush(dev);
385 return 0;
386}
387
Chris Wilson42dcedd2012-11-15 11:32:30 +0000388void *i915_gem_object_alloc(struct drm_device *dev)
389{
390 struct drm_i915_private *dev_priv = dev->dev_private;
Joe Perchesfac15c12013-08-29 13:11:07 -0700391 return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
Chris Wilson42dcedd2012-11-15 11:32:30 +0000392}
393
394void i915_gem_object_free(struct drm_i915_gem_object *obj)
395{
396 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
397 kmem_cache_free(dev_priv->slab, obj);
398}
399
Dave Airlieff72145b2011-02-07 12:16:14 +1000400static int
401i915_gem_create(struct drm_file *file,
402 struct drm_device *dev,
403 uint64_t size,
Thomas Hellstrom355a7012014-11-20 09:56:25 +0100404 bool dumb,
Dave Airlieff72145b2011-02-07 12:16:14 +1000405 uint32_t *handle_p)
Eric Anholt673a3942008-07-30 12:06:12 -0700406{
Chris Wilson05394f32010-11-08 19:18:58 +0000407 struct drm_i915_gem_object *obj;
Pekka Paalanena1a2d1d2009-08-23 12:40:55 +0300408 int ret;
409 u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700410
Dave Airlieff72145b2011-02-07 12:16:14 +1000411 size = roundup(size, PAGE_SIZE);
Chris Wilson8ffc0242011-09-14 14:14:28 +0200412 if (size == 0)
413 return -EINVAL;
Eric Anholt673a3942008-07-30 12:06:12 -0700414
415 /* Allocate the new object */
Dave Airlieff72145b2011-02-07 12:16:14 +1000416 obj = i915_gem_alloc_object(dev, size);
Eric Anholt673a3942008-07-30 12:06:12 -0700417 if (obj == NULL)
418 return -ENOMEM;
419
Thomas Hellstrom355a7012014-11-20 09:56:25 +0100420 obj->base.dumb = dumb;
Chris Wilson05394f32010-11-08 19:18:58 +0000421 ret = drm_gem_handle_create(file, &obj->base, &handle);
Chris Wilson202f2fe2010-10-14 13:20:40 +0100422 /* drop reference from allocate - handle holds it now */
Daniel Vetterd861e332013-07-24 23:25:03 +0200423 drm_gem_object_unreference_unlocked(&obj->base);
424 if (ret)
425 return ret;
Chris Wilson202f2fe2010-10-14 13:20:40 +0100426
Dave Airlieff72145b2011-02-07 12:16:14 +1000427 *handle_p = handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700428 return 0;
429}
430
Dave Airlieff72145b2011-02-07 12:16:14 +1000431int
432i915_gem_dumb_create(struct drm_file *file,
433 struct drm_device *dev,
434 struct drm_mode_create_dumb *args)
435{
436 /* have to work out size/pitch and return them */
Paulo Zanonide45eaf2013-10-18 18:48:24 -0300437 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
Dave Airlieff72145b2011-02-07 12:16:14 +1000438 args->size = args->pitch * args->height;
439 return i915_gem_create(file, dev,
Thomas Hellstrom355a7012014-11-20 09:56:25 +0100440 args->size, true, &args->handle);
Dave Airlieff72145b2011-02-07 12:16:14 +1000441}
442
Dave Airlieff72145b2011-02-07 12:16:14 +1000443/**
444 * Creates a new mm object and returns a handle to it.
445 */
446int
447i915_gem_create_ioctl(struct drm_device *dev, void *data,
448 struct drm_file *file)
449{
450 struct drm_i915_gem_create *args = data;
Daniel Vetter63ed2cb2012-04-23 16:50:50 +0200451
Dave Airlieff72145b2011-02-07 12:16:14 +1000452 return i915_gem_create(file, dev,
Thomas Hellstrom355a7012014-11-20 09:56:25 +0100453 args->size, false, &args->handle);
Dave Airlieff72145b2011-02-07 12:16:14 +1000454}
455
Daniel Vetter8c599672011-12-14 13:57:31 +0100456static inline int
Daniel Vetter8461d222011-12-14 13:57:32 +0100457__copy_to_user_swizzled(char __user *cpu_vaddr,
458 const char *gpu_vaddr, int gpu_offset,
459 int length)
460{
461 int ret, cpu_offset = 0;
462
463 while (length > 0) {
464 int cacheline_end = ALIGN(gpu_offset + 1, 64);
465 int this_length = min(cacheline_end - gpu_offset, length);
466 int swizzled_gpu_offset = gpu_offset ^ 64;
467
468 ret = __copy_to_user(cpu_vaddr + cpu_offset,
469 gpu_vaddr + swizzled_gpu_offset,
470 this_length);
471 if (ret)
472 return ret + length;
473
474 cpu_offset += this_length;
475 gpu_offset += this_length;
476 length -= this_length;
477 }
478
479 return 0;
480}
481
482static inline int
Ben Widawsky4f0c7cf2012-04-16 14:07:47 -0700483__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
484 const char __user *cpu_vaddr,
Daniel Vetter8c599672011-12-14 13:57:31 +0100485 int length)
486{
487 int ret, cpu_offset = 0;
488
489 while (length > 0) {
490 int cacheline_end = ALIGN(gpu_offset + 1, 64);
491 int this_length = min(cacheline_end - gpu_offset, length);
492 int swizzled_gpu_offset = gpu_offset ^ 64;
493
494 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
495 cpu_vaddr + cpu_offset,
496 this_length);
497 if (ret)
498 return ret + length;
499
500 cpu_offset += this_length;
501 gpu_offset += this_length;
502 length -= this_length;
503 }
504
505 return 0;
506}
507
Brad Volkin4c914c02014-02-18 10:15:45 -0800508/*
509 * Pins the specified object's pages and synchronizes the object with
510 * GPU accesses. Sets needs_clflush to non-zero if the caller should
511 * flush the object from the CPU cache.
512 */
513int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
514 int *needs_clflush)
515{
516 int ret;
517
518 *needs_clflush = 0;
519
520 if (!obj->base.filp)
521 return -EINVAL;
522
523 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
524 /* If we're not in the cpu read domain, set ourself into the gtt
525 * read domain and manually flush cachelines (if required). This
526 * optimizes for the case when the gpu will dirty the data
527 * anyway again before the next pread happens. */
528 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
529 obj->cache_level);
530 ret = i915_gem_object_wait_rendering(obj, true);
531 if (ret)
532 return ret;
Chris Wilsonc8725f32014-03-17 12:21:55 +0000533
534 i915_gem_object_retire(obj);
Brad Volkin4c914c02014-02-18 10:15:45 -0800535 }
536
537 ret = i915_gem_object_get_pages(obj);
538 if (ret)
539 return ret;
540
541 i915_gem_object_pin_pages(obj);
542
543 return ret;
544}
545
Daniel Vetterd174bd62012-03-25 19:47:40 +0200546/* Per-page copy function for the shmem pread fastpath.
547 * Flushes invalid cachelines before reading the target if
548 * needs_clflush is set. */
Eric Anholteb014592009-03-10 11:44:52 -0700549static int
Daniel Vetterd174bd62012-03-25 19:47:40 +0200550shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
551 char __user *user_data,
552 bool page_do_bit17_swizzling, bool needs_clflush)
553{
554 char *vaddr;
555 int ret;
556
Daniel Vettere7e58eb2012-03-25 19:47:43 +0200557 if (unlikely(page_do_bit17_swizzling))
Daniel Vetterd174bd62012-03-25 19:47:40 +0200558 return -EINVAL;
559
560 vaddr = kmap_atomic(page);
561 if (needs_clflush)
562 drm_clflush_virt_range(vaddr + shmem_page_offset,
563 page_length);
564 ret = __copy_to_user_inatomic(user_data,
565 vaddr + shmem_page_offset,
566 page_length);
567 kunmap_atomic(vaddr);
568
Chris Wilsonf60d7f02012-09-04 21:02:56 +0100569 return ret ? -EFAULT : 0;
Daniel Vetterd174bd62012-03-25 19:47:40 +0200570}
571
Daniel Vetter23c18c72012-03-25 19:47:42 +0200572static void
573shmem_clflush_swizzled_range(char *addr, unsigned long length,
574 bool swizzled)
575{
Daniel Vettere7e58eb2012-03-25 19:47:43 +0200576 if (unlikely(swizzled)) {
Daniel Vetter23c18c72012-03-25 19:47:42 +0200577 unsigned long start = (unsigned long) addr;
578 unsigned long end = (unsigned long) addr + length;
579
580 /* For swizzling simply ensure that we always flush both
581 * channels. Lame, but simple and it works. Swizzled
582 * pwrite/pread is far from a hotpath - current userspace
583 * doesn't use it at all. */
584 start = round_down(start, 128);
585 end = round_up(end, 128);
586
587 drm_clflush_virt_range((void *)start, end - start);
588 } else {
589 drm_clflush_virt_range(addr, length);
590 }
591
592}
593
Daniel Vetterd174bd62012-03-25 19:47:40 +0200594/* Only difference to the fast-path function is that this can handle bit17
595 * and uses non-atomic copy and kmap functions. */
596static int
597shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
598 char __user *user_data,
599 bool page_do_bit17_swizzling, bool needs_clflush)
600{
601 char *vaddr;
602 int ret;
603
604 vaddr = kmap(page);
605 if (needs_clflush)
Daniel Vetter23c18c72012-03-25 19:47:42 +0200606 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
607 page_length,
608 page_do_bit17_swizzling);
Daniel Vetterd174bd62012-03-25 19:47:40 +0200609
610 if (page_do_bit17_swizzling)
611 ret = __copy_to_user_swizzled(user_data,
612 vaddr, shmem_page_offset,
613 page_length);
614 else
615 ret = __copy_to_user(user_data,
616 vaddr + shmem_page_offset,
617 page_length);
618 kunmap(page);
619
Chris Wilsonf60d7f02012-09-04 21:02:56 +0100620 return ret ? - EFAULT : 0;
Daniel Vetterd174bd62012-03-25 19:47:40 +0200621}
622
Eric Anholteb014592009-03-10 11:44:52 -0700623static int
Daniel Vetterdbf7bff2012-03-25 19:47:29 +0200624i915_gem_shmem_pread(struct drm_device *dev,
625 struct drm_i915_gem_object *obj,
626 struct drm_i915_gem_pread *args,
627 struct drm_file *file)
Eric Anholteb014592009-03-10 11:44:52 -0700628{
Daniel Vetter8461d222011-12-14 13:57:32 +0100629 char __user *user_data;
Eric Anholteb014592009-03-10 11:44:52 -0700630 ssize_t remain;
Daniel Vetter8461d222011-12-14 13:57:32 +0100631 loff_t offset;
Ben Widawskyeb2c0c82012-02-15 14:42:43 +0100632 int shmem_page_offset, page_length, ret = 0;
Daniel Vetter8461d222011-12-14 13:57:32 +0100633 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
Daniel Vetter96d79b52012-03-25 19:47:36 +0200634 int prefaulted = 0;
Daniel Vetter84897312012-03-25 19:47:31 +0200635 int needs_clflush = 0;
Imre Deak67d5a502013-02-18 19:28:02 +0200636 struct sg_page_iter sg_iter;
Eric Anholteb014592009-03-10 11:44:52 -0700637
Ville Syrjälä2bb46292013-02-22 16:12:51 +0200638 user_data = to_user_ptr(args->data_ptr);
Eric Anholteb014592009-03-10 11:44:52 -0700639 remain = args->size;
640
Daniel Vetter8461d222011-12-14 13:57:32 +0100641 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700642
Brad Volkin4c914c02014-02-18 10:15:45 -0800643 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
Chris Wilsonf60d7f02012-09-04 21:02:56 +0100644 if (ret)
645 return ret;
646
Eric Anholteb014592009-03-10 11:44:52 -0700647 offset = args->offset;
Daniel Vetter8461d222011-12-14 13:57:32 +0100648
Imre Deak67d5a502013-02-18 19:28:02 +0200649 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
650 offset >> PAGE_SHIFT) {
Imre Deak2db76d72013-03-26 15:14:18 +0200651 struct page *page = sg_page_iter_page(&sg_iter);
Chris Wilson9da3da62012-06-01 15:20:22 +0100652
653 if (remain <= 0)
654 break;
655
Eric Anholteb014592009-03-10 11:44:52 -0700656 /* Operation in this page
657 *
Eric Anholteb014592009-03-10 11:44:52 -0700658 * shmem_page_offset = offset within page in shmem file
Eric Anholteb014592009-03-10 11:44:52 -0700659 * page_length = bytes to copy for this page
660 */
Chris Wilsonc8cbbb82011-05-12 22:17:11 +0100661 shmem_page_offset = offset_in_page(offset);
Eric Anholteb014592009-03-10 11:44:52 -0700662 page_length = remain;
663 if ((shmem_page_offset + page_length) > PAGE_SIZE)
664 page_length = PAGE_SIZE - shmem_page_offset;
Eric Anholteb014592009-03-10 11:44:52 -0700665
Daniel Vetter8461d222011-12-14 13:57:32 +0100666 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
667 (page_to_phys(page) & (1 << 17)) != 0;
668
Daniel Vetterd174bd62012-03-25 19:47:40 +0200669 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
670 user_data, page_do_bit17_swizzling,
671 needs_clflush);
672 if (ret == 0)
673 goto next_page;
Eric Anholteb014592009-03-10 11:44:52 -0700674
Daniel Vetterdbf7bff2012-03-25 19:47:29 +0200675 mutex_unlock(&dev->struct_mutex);
676
Jani Nikulad330a952014-01-21 11:24:25 +0200677 if (likely(!i915.prefault_disable) && !prefaulted) {
Daniel Vetterf56f8212012-03-25 19:47:41 +0200678 ret = fault_in_multipages_writeable(user_data, remain);
Daniel Vetter96d79b52012-03-25 19:47:36 +0200679 /* Userspace is tricking us, but we've already clobbered
680 * its pages with the prefault and promised to write the
681 * data up to the first fault. Hence ignore any errors
682 * and just continue. */
683 (void)ret;
684 prefaulted = 1;
685 }
686
Daniel Vetterd174bd62012-03-25 19:47:40 +0200687 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
688 user_data, page_do_bit17_swizzling,
689 needs_clflush);
Eric Anholteb014592009-03-10 11:44:52 -0700690
Daniel Vetterdbf7bff2012-03-25 19:47:29 +0200691 mutex_lock(&dev->struct_mutex);
Chris Wilsonf60d7f02012-09-04 21:02:56 +0100692
Chris Wilsonf60d7f02012-09-04 21:02:56 +0100693 if (ret)
Daniel Vetter8461d222011-12-14 13:57:32 +0100694 goto out;
Daniel Vetter8461d222011-12-14 13:57:32 +0100695
Chris Wilson17793c92014-03-07 08:30:36 +0000696next_page:
Eric Anholteb014592009-03-10 11:44:52 -0700697 remain -= page_length;
Daniel Vetter8461d222011-12-14 13:57:32 +0100698 user_data += page_length;
Eric Anholteb014592009-03-10 11:44:52 -0700699 offset += page_length;
700 }
701
Chris Wilson4f27b752010-10-14 15:26:45 +0100702out:
Chris Wilsonf60d7f02012-09-04 21:02:56 +0100703 i915_gem_object_unpin_pages(obj);
704
Eric Anholteb014592009-03-10 11:44:52 -0700705 return ret;
706}
707
Eric Anholt673a3942008-07-30 12:06:12 -0700708/**
709 * Reads data from the object referenced by handle.
710 *
711 * On error, the contents of *data are undefined.
712 */
713int
714i915_gem_pread_ioctl(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +0000715 struct drm_file *file)
Eric Anholt673a3942008-07-30 12:06:12 -0700716{
717 struct drm_i915_gem_pread *args = data;
Chris Wilson05394f32010-11-08 19:18:58 +0000718 struct drm_i915_gem_object *obj;
Chris Wilson35b62a82010-09-26 20:23:38 +0100719 int ret = 0;
Eric Anholt673a3942008-07-30 12:06:12 -0700720
Chris Wilson51311d02010-11-17 09:10:42 +0000721 if (args->size == 0)
722 return 0;
723
724 if (!access_ok(VERIFY_WRITE,
Ville Syrjälä2bb46292013-02-22 16:12:51 +0200725 to_user_ptr(args->data_ptr),
Chris Wilson51311d02010-11-17 09:10:42 +0000726 args->size))
727 return -EFAULT;
728
Chris Wilson4f27b752010-10-14 15:26:45 +0100729 ret = i915_mutex_lock_interruptible(dev);
Chris Wilson1d7cfea2010-10-17 09:45:41 +0100730 if (ret)
Chris Wilson4f27b752010-10-14 15:26:45 +0100731 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700732
Chris Wilson05394f32010-11-08 19:18:58 +0000733 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +0000734 if (&obj->base == NULL) {
Chris Wilson1d7cfea2010-10-17 09:45:41 +0100735 ret = -ENOENT;
736 goto unlock;
Chris Wilson4f27b752010-10-14 15:26:45 +0100737 }
Eric Anholt673a3942008-07-30 12:06:12 -0700738
Chris Wilson7dcd2492010-09-26 20:21:44 +0100739 /* Bounds check source. */
Chris Wilson05394f32010-11-08 19:18:58 +0000740 if (args->offset > obj->base.size ||
741 args->size > obj->base.size - args->offset) {
Chris Wilsonce9d4192010-09-26 20:50:05 +0100742 ret = -EINVAL;
Chris Wilson35b62a82010-09-26 20:23:38 +0100743 goto out;
Chris Wilsonce9d4192010-09-26 20:50:05 +0100744 }
745
Daniel Vetter1286ff72012-05-10 15:25:09 +0200746 /* prime objects have no backing filp to GEM pread/pwrite
747 * pages from.
748 */
749 if (!obj->base.filp) {
750 ret = -EINVAL;
751 goto out;
752 }
753
Chris Wilsondb53a302011-02-03 11:57:46 +0000754 trace_i915_gem_object_pread(obj, args->offset, args->size);
755
Daniel Vetterdbf7bff2012-03-25 19:47:29 +0200756 ret = i915_gem_shmem_pread(dev, obj, args, file);
Eric Anholt673a3942008-07-30 12:06:12 -0700757
Chris Wilson35b62a82010-09-26 20:23:38 +0100758out:
Chris Wilson05394f32010-11-08 19:18:58 +0000759 drm_gem_object_unreference(&obj->base);
Chris Wilson1d7cfea2010-10-17 09:45:41 +0100760unlock:
Chris Wilson4f27b752010-10-14 15:26:45 +0100761 mutex_unlock(&dev->struct_mutex);
Eric Anholteb014592009-03-10 11:44:52 -0700762 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700763}
764
Keith Packard0839ccb2008-10-30 19:38:48 -0700765/* This is the fast write path which cannot handle
766 * page faults in the source data
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700767 */
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700768
Keith Packard0839ccb2008-10-30 19:38:48 -0700769static inline int
770fast_user_write(struct io_mapping *mapping,
771 loff_t page_base, int page_offset,
772 char __user *user_data,
773 int length)
774{
Ben Widawsky4f0c7cf2012-04-16 14:07:47 -0700775 void __iomem *vaddr_atomic;
776 void *vaddr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700777 unsigned long unwritten;
778
Peter Zijlstra3e4d3af2010-10-26 14:21:51 -0700779 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
Ben Widawsky4f0c7cf2012-04-16 14:07:47 -0700780 /* We can use the cpu mem copy function because this is X86. */
781 vaddr = (void __force*)vaddr_atomic + page_offset;
782 unwritten = __copy_from_user_inatomic_nocache(vaddr,
Keith Packard0839ccb2008-10-30 19:38:48 -0700783 user_data, length);
Peter Zijlstra3e4d3af2010-10-26 14:21:51 -0700784 io_mapping_unmap_atomic(vaddr_atomic);
Chris Wilsonfbd5a262010-10-14 15:03:58 +0100785 return unwritten;
Keith Packard0839ccb2008-10-30 19:38:48 -0700786}
787
Eric Anholt3de09aa2009-03-09 09:42:23 -0700788/**
789 * This is the fast pwrite path, where we copy the data directly from the
790 * user into the GTT, uncached.
791 */
Eric Anholt673a3942008-07-30 12:06:12 -0700792static int
Chris Wilson05394f32010-11-08 19:18:58 +0000793i915_gem_gtt_pwrite_fast(struct drm_device *dev,
794 struct drm_i915_gem_object *obj,
Eric Anholt3de09aa2009-03-09 09:42:23 -0700795 struct drm_i915_gem_pwrite *args,
Chris Wilson05394f32010-11-08 19:18:58 +0000796 struct drm_file *file)
Eric Anholt673a3942008-07-30 12:06:12 -0700797{
Jani Nikula3e31c6c2014-03-31 14:27:16 +0300798 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700799 ssize_t remain;
Keith Packard0839ccb2008-10-30 19:38:48 -0700800 loff_t offset, page_base;
Eric Anholt673a3942008-07-30 12:06:12 -0700801 char __user *user_data;
Daniel Vetter935aaa62012-03-25 19:47:35 +0200802 int page_offset, page_length, ret;
803
Daniel Vetter1ec9e262014-02-14 14:01:11 +0100804 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
Daniel Vetter935aaa62012-03-25 19:47:35 +0200805 if (ret)
806 goto out;
807
808 ret = i915_gem_object_set_to_gtt_domain(obj, true);
809 if (ret)
810 goto out_unpin;
811
812 ret = i915_gem_object_put_fence(obj);
813 if (ret)
814 goto out_unpin;
Eric Anholt673a3942008-07-30 12:06:12 -0700815
Ville Syrjälä2bb46292013-02-22 16:12:51 +0200816 user_data = to_user_ptr(args->data_ptr);
Eric Anholt673a3942008-07-30 12:06:12 -0700817 remain = args->size;
Eric Anholt673a3942008-07-30 12:06:12 -0700818
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700819 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700820
821 while (remain > 0) {
822 /* Operation in this page
823 *
Keith Packard0839ccb2008-10-30 19:38:48 -0700824 * page_base = page offset within aperture
825 * page_offset = offset within page
826 * page_length = bytes to copy for this page
Eric Anholt673a3942008-07-30 12:06:12 -0700827 */
Chris Wilsonc8cbbb82011-05-12 22:17:11 +0100828 page_base = offset & PAGE_MASK;
829 page_offset = offset_in_page(offset);
Keith Packard0839ccb2008-10-30 19:38:48 -0700830 page_length = remain;
831 if ((page_offset + remain) > PAGE_SIZE)
832 page_length = PAGE_SIZE - page_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700833
Keith Packard0839ccb2008-10-30 19:38:48 -0700834 /* If we get a fault while copying data, then (presumably) our
Eric Anholt3de09aa2009-03-09 09:42:23 -0700835 * source page isn't available. Return the error and we'll
836 * retry in the slow path.
Keith Packard0839ccb2008-10-30 19:38:48 -0700837 */
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800838 if (fast_user_write(dev_priv->gtt.mappable, page_base,
Daniel Vetter935aaa62012-03-25 19:47:35 +0200839 page_offset, user_data, page_length)) {
840 ret = -EFAULT;
841 goto out_unpin;
842 }
Eric Anholt673a3942008-07-30 12:06:12 -0700843
Keith Packard0839ccb2008-10-30 19:38:48 -0700844 remain -= page_length;
845 user_data += page_length;
846 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700847 }
Eric Anholt673a3942008-07-30 12:06:12 -0700848
Daniel Vetter935aaa62012-03-25 19:47:35 +0200849out_unpin:
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800850 i915_gem_object_ggtt_unpin(obj);
Daniel Vetter935aaa62012-03-25 19:47:35 +0200851out:
Eric Anholt3de09aa2009-03-09 09:42:23 -0700852 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700853}
854
Daniel Vetterd174bd62012-03-25 19:47:40 +0200855/* Per-page copy function for the shmem pwrite fastpath.
856 * Flushes invalid cachelines before writing to the target if
857 * needs_clflush_before is set and flushes out any written cachelines after
858 * writing if needs_clflush is set. */
Eric Anholt673a3942008-07-30 12:06:12 -0700859static int
Daniel Vetterd174bd62012-03-25 19:47:40 +0200860shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
861 char __user *user_data,
862 bool page_do_bit17_swizzling,
863 bool needs_clflush_before,
864 bool needs_clflush_after)
Eric Anholt673a3942008-07-30 12:06:12 -0700865{
Daniel Vetterd174bd62012-03-25 19:47:40 +0200866 char *vaddr;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700867 int ret;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700868
Daniel Vettere7e58eb2012-03-25 19:47:43 +0200869 if (unlikely(page_do_bit17_swizzling))
Daniel Vetterd174bd62012-03-25 19:47:40 +0200870 return -EINVAL;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700871
Daniel Vetterd174bd62012-03-25 19:47:40 +0200872 vaddr = kmap_atomic(page);
873 if (needs_clflush_before)
874 drm_clflush_virt_range(vaddr + shmem_page_offset,
875 page_length);
Chris Wilsonc2831a92014-03-07 08:30:37 +0000876 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
877 user_data, page_length);
Daniel Vetterd174bd62012-03-25 19:47:40 +0200878 if (needs_clflush_after)
879 drm_clflush_virt_range(vaddr + shmem_page_offset,
880 page_length);
881 kunmap_atomic(vaddr);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700882
Chris Wilson755d2212012-09-04 21:02:55 +0100883 return ret ? -EFAULT : 0;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700884}
885
Daniel Vetterd174bd62012-03-25 19:47:40 +0200886/* Only difference to the fast-path function is that this can handle bit17
887 * and uses non-atomic copy and kmap functions. */
Eric Anholt3043c602008-10-02 12:24:47 -0700888static int
Daniel Vetterd174bd62012-03-25 19:47:40 +0200889shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
890 char __user *user_data,
891 bool page_do_bit17_swizzling,
892 bool needs_clflush_before,
893 bool needs_clflush_after)
Eric Anholt673a3942008-07-30 12:06:12 -0700894{
Daniel Vetterd174bd62012-03-25 19:47:40 +0200895 char *vaddr;
896 int ret;
Eric Anholt40123c12009-03-09 13:42:30 -0700897
Daniel Vetterd174bd62012-03-25 19:47:40 +0200898 vaddr = kmap(page);
Daniel Vettere7e58eb2012-03-25 19:47:43 +0200899 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
Daniel Vetter23c18c72012-03-25 19:47:42 +0200900 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
901 page_length,
902 page_do_bit17_swizzling);
Daniel Vetterd174bd62012-03-25 19:47:40 +0200903 if (page_do_bit17_swizzling)
904 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
Chris Wilsone5281cc2010-10-28 13:45:36 +0100905 user_data,
906 page_length);
Daniel Vetterd174bd62012-03-25 19:47:40 +0200907 else
908 ret = __copy_from_user(vaddr + shmem_page_offset,
909 user_data,
910 page_length);
911 if (needs_clflush_after)
Daniel Vetter23c18c72012-03-25 19:47:42 +0200912 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
913 page_length,
914 page_do_bit17_swizzling);
Daniel Vetterd174bd62012-03-25 19:47:40 +0200915 kunmap(page);
Chris Wilsone5281cc2010-10-28 13:45:36 +0100916
Chris Wilson755d2212012-09-04 21:02:55 +0100917 return ret ? -EFAULT : 0;
Eric Anholt40123c12009-03-09 13:42:30 -0700918}
919
Eric Anholt40123c12009-03-09 13:42:30 -0700920static int
Daniel Vettere244a442012-03-25 19:47:28 +0200921i915_gem_shmem_pwrite(struct drm_device *dev,
922 struct drm_i915_gem_object *obj,
923 struct drm_i915_gem_pwrite *args,
924 struct drm_file *file)
Eric Anholt40123c12009-03-09 13:42:30 -0700925{
Eric Anholt40123c12009-03-09 13:42:30 -0700926 ssize_t remain;
Daniel Vetter8c599672011-12-14 13:57:31 +0100927 loff_t offset;
928 char __user *user_data;
Ben Widawskyeb2c0c82012-02-15 14:42:43 +0100929 int shmem_page_offset, page_length, ret = 0;
Daniel Vetter8c599672011-12-14 13:57:31 +0100930 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
Daniel Vettere244a442012-03-25 19:47:28 +0200931 int hit_slowpath = 0;
Daniel Vetter58642882012-03-25 19:47:37 +0200932 int needs_clflush_after = 0;
933 int needs_clflush_before = 0;
Imre Deak67d5a502013-02-18 19:28:02 +0200934 struct sg_page_iter sg_iter;
Eric Anholt40123c12009-03-09 13:42:30 -0700935
Ville Syrjälä2bb46292013-02-22 16:12:51 +0200936 user_data = to_user_ptr(args->data_ptr);
Eric Anholt40123c12009-03-09 13:42:30 -0700937 remain = args->size;
938
Daniel Vetter8c599672011-12-14 13:57:31 +0100939 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700940
Daniel Vetter58642882012-03-25 19:47:37 +0200941 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
942 /* If we're not in the cpu write domain, set ourself into the gtt
943 * write domain and manually flush cachelines (if required). This
944 * optimizes for the case when the gpu will use the data
945 * right away and we therefore have to clflush anyway. */
Chris Wilson2c225692013-08-09 12:26:45 +0100946 needs_clflush_after = cpu_write_needs_clflush(obj);
Ben Widawsky23f54482013-09-11 14:57:48 -0700947 ret = i915_gem_object_wait_rendering(obj, false);
948 if (ret)
949 return ret;
Chris Wilsonc8725f32014-03-17 12:21:55 +0000950
951 i915_gem_object_retire(obj);
Daniel Vetter58642882012-03-25 19:47:37 +0200952 }
Chris Wilsonc76ce032013-08-08 14:41:03 +0100953 /* Same trick applies to invalidate partially written cachelines read
954 * before writing. */
955 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
956 needs_clflush_before =
957 !cpu_cache_is_coherent(dev, obj->cache_level);
Daniel Vetter58642882012-03-25 19:47:37 +0200958
Chris Wilson755d2212012-09-04 21:02:55 +0100959 ret = i915_gem_object_get_pages(obj);
960 if (ret)
961 return ret;
962
963 i915_gem_object_pin_pages(obj);
964
Eric Anholt40123c12009-03-09 13:42:30 -0700965 offset = args->offset;
Chris Wilson05394f32010-11-08 19:18:58 +0000966 obj->dirty = 1;
Eric Anholt40123c12009-03-09 13:42:30 -0700967
Imre Deak67d5a502013-02-18 19:28:02 +0200968 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
969 offset >> PAGE_SHIFT) {
Imre Deak2db76d72013-03-26 15:14:18 +0200970 struct page *page = sg_page_iter_page(&sg_iter);
Daniel Vetter58642882012-03-25 19:47:37 +0200971 int partial_cacheline_write;
Chris Wilsone5281cc2010-10-28 13:45:36 +0100972
Chris Wilson9da3da62012-06-01 15:20:22 +0100973 if (remain <= 0)
974 break;
975
Eric Anholt40123c12009-03-09 13:42:30 -0700976 /* Operation in this page
977 *
Eric Anholt40123c12009-03-09 13:42:30 -0700978 * shmem_page_offset = offset within page in shmem file
Eric Anholt40123c12009-03-09 13:42:30 -0700979 * page_length = bytes to copy for this page
980 */
Chris Wilsonc8cbbb82011-05-12 22:17:11 +0100981 shmem_page_offset = offset_in_page(offset);
Eric Anholt40123c12009-03-09 13:42:30 -0700982
983 page_length = remain;
984 if ((shmem_page_offset + page_length) > PAGE_SIZE)
985 page_length = PAGE_SIZE - shmem_page_offset;
Eric Anholt40123c12009-03-09 13:42:30 -0700986
Daniel Vetter58642882012-03-25 19:47:37 +0200987 /* If we don't overwrite a cacheline completely we need to be
988 * careful to have up-to-date data by first clflushing. Don't
989 * overcomplicate things and flush the entire patch. */
990 partial_cacheline_write = needs_clflush_before &&
991 ((shmem_page_offset | page_length)
992 & (boot_cpu_data.x86_clflush_size - 1));
993
Daniel Vetter8c599672011-12-14 13:57:31 +0100994 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
995 (page_to_phys(page) & (1 << 17)) != 0;
996
Daniel Vetterd174bd62012-03-25 19:47:40 +0200997 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
998 user_data, page_do_bit17_swizzling,
999 partial_cacheline_write,
1000 needs_clflush_after);
1001 if (ret == 0)
1002 goto next_page;
Eric Anholt40123c12009-03-09 13:42:30 -07001003
Daniel Vettere244a442012-03-25 19:47:28 +02001004 hit_slowpath = 1;
Daniel Vettere244a442012-03-25 19:47:28 +02001005 mutex_unlock(&dev->struct_mutex);
Daniel Vetterd174bd62012-03-25 19:47:40 +02001006 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1007 user_data, page_do_bit17_swizzling,
1008 partial_cacheline_write,
1009 needs_clflush_after);
Eric Anholt40123c12009-03-09 13:42:30 -07001010
Daniel Vettere244a442012-03-25 19:47:28 +02001011 mutex_lock(&dev->struct_mutex);
Chris Wilson755d2212012-09-04 21:02:55 +01001012
Chris Wilson755d2212012-09-04 21:02:55 +01001013 if (ret)
Daniel Vetter8c599672011-12-14 13:57:31 +01001014 goto out;
Daniel Vetter8c599672011-12-14 13:57:31 +01001015
Chris Wilson17793c92014-03-07 08:30:36 +00001016next_page:
Eric Anholt40123c12009-03-09 13:42:30 -07001017 remain -= page_length;
Daniel Vetter8c599672011-12-14 13:57:31 +01001018 user_data += page_length;
Eric Anholt40123c12009-03-09 13:42:30 -07001019 offset += page_length;
1020 }
1021
Chris Wilsonfbd5a262010-10-14 15:03:58 +01001022out:
Chris Wilson755d2212012-09-04 21:02:55 +01001023 i915_gem_object_unpin_pages(obj);
1024
Daniel Vettere244a442012-03-25 19:47:28 +02001025 if (hit_slowpath) {
Daniel Vetter8dcf0152012-11-15 16:53:58 +01001026 /*
1027 * Fixup: Flush cpu caches in case we didn't flush the dirty
1028 * cachelines in-line while writing and the object moved
1029 * out of the cpu write domain while we've dropped the lock.
1030 */
1031 if (!needs_clflush_after &&
1032 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
Chris Wilson000433b2013-08-08 14:41:09 +01001033 if (i915_gem_clflush_object(obj, obj->pin_display))
1034 i915_gem_chipset_flush(dev);
Daniel Vettere244a442012-03-25 19:47:28 +02001035 }
Daniel Vetter8c599672011-12-14 13:57:31 +01001036 }
Eric Anholt40123c12009-03-09 13:42:30 -07001037
Daniel Vetter58642882012-03-25 19:47:37 +02001038 if (needs_clflush_after)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001039 i915_gem_chipset_flush(dev);
Daniel Vetter58642882012-03-25 19:47:37 +02001040
Eric Anholt40123c12009-03-09 13:42:30 -07001041 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07001042}
1043
1044/**
1045 * Writes data to the object referenced by handle.
1046 *
1047 * On error, the contents of the buffer that were to be modified are undefined.
1048 */
1049int
1050i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
Chris Wilsonfbd5a262010-10-14 15:03:58 +01001051 struct drm_file *file)
Eric Anholt673a3942008-07-30 12:06:12 -07001052{
1053 struct drm_i915_gem_pwrite *args = data;
Chris Wilson05394f32010-11-08 19:18:58 +00001054 struct drm_i915_gem_object *obj;
Chris Wilson51311d02010-11-17 09:10:42 +00001055 int ret;
1056
1057 if (args->size == 0)
1058 return 0;
1059
1060 if (!access_ok(VERIFY_READ,
Ville Syrjälä2bb46292013-02-22 16:12:51 +02001061 to_user_ptr(args->data_ptr),
Chris Wilson51311d02010-11-17 09:10:42 +00001062 args->size))
1063 return -EFAULT;
1064
Jani Nikulad330a952014-01-21 11:24:25 +02001065 if (likely(!i915.prefault_disable)) {
Xiong Zhang0b74b502013-07-19 13:51:24 +08001066 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1067 args->size);
1068 if (ret)
1069 return -EFAULT;
1070 }
Eric Anholt673a3942008-07-30 12:06:12 -07001071
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001072 ret = i915_mutex_lock_interruptible(dev);
1073 if (ret)
1074 return ret;
1075
Chris Wilson05394f32010-11-08 19:18:58 +00001076 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00001077 if (&obj->base == NULL) {
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001078 ret = -ENOENT;
1079 goto unlock;
1080 }
Eric Anholt673a3942008-07-30 12:06:12 -07001081
Chris Wilson7dcd2492010-09-26 20:21:44 +01001082 /* Bounds check destination. */
Chris Wilson05394f32010-11-08 19:18:58 +00001083 if (args->offset > obj->base.size ||
1084 args->size > obj->base.size - args->offset) {
Chris Wilsonce9d4192010-09-26 20:50:05 +01001085 ret = -EINVAL;
Chris Wilson35b62a82010-09-26 20:23:38 +01001086 goto out;
Chris Wilsonce9d4192010-09-26 20:50:05 +01001087 }
1088
Daniel Vetter1286ff72012-05-10 15:25:09 +02001089 /* prime objects have no backing filp to GEM pread/pwrite
1090 * pages from.
1091 */
1092 if (!obj->base.filp) {
1093 ret = -EINVAL;
1094 goto out;
1095 }
1096
Chris Wilsondb53a302011-02-03 11:57:46 +00001097 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1098
Daniel Vetter935aaa62012-03-25 19:47:35 +02001099 ret = -EFAULT;
Eric Anholt673a3942008-07-30 12:06:12 -07001100 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1101 * it would end up going through the fenced access, and we'll get
1102 * different detiling behavior between reading and writing.
1103 * pread/pwrite currently are reading and writing from the CPU
1104 * perspective, requiring manual detiling by the client.
1105 */
Chris Wilson2c225692013-08-09 12:26:45 +01001106 if (obj->tiling_mode == I915_TILING_NONE &&
1107 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1108 cpu_write_needs_clflush(obj)) {
Chris Wilsonfbd5a262010-10-14 15:03:58 +01001109 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
Daniel Vetter935aaa62012-03-25 19:47:35 +02001110 /* Note that the gtt paths might fail with non-page-backed user
1111 * pointers (e.g. gtt mappings when moving data between
1112 * textures). Fallback to the shmem path in that case. */
Eric Anholt40123c12009-03-09 13:42:30 -07001113 }
Eric Anholt673a3942008-07-30 12:06:12 -07001114
Chris Wilson6a2c4232014-11-04 04:51:40 -08001115 if (ret == -EFAULT || ret == -ENOSPC) {
1116 if (obj->phys_handle)
1117 ret = i915_gem_phys_pwrite(obj, args, file);
1118 else
1119 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1120 }
Daniel Vetter5c0480f2011-12-14 13:57:30 +01001121
Chris Wilson35b62a82010-09-26 20:23:38 +01001122out:
Chris Wilson05394f32010-11-08 19:18:58 +00001123 drm_gem_object_unreference(&obj->base);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001124unlock:
Chris Wilsonfbd5a262010-10-14 15:03:58 +01001125 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07001126 return ret;
1127}
1128
Chris Wilsonb3612372012-08-24 09:35:08 +01001129int
Daniel Vetter33196de2012-11-14 17:14:05 +01001130i915_gem_check_wedge(struct i915_gpu_error *error,
Chris Wilsonb3612372012-08-24 09:35:08 +01001131 bool interruptible)
1132{
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001133 if (i915_reset_in_progress(error)) {
Chris Wilsonb3612372012-08-24 09:35:08 +01001134 /* Non-interruptible callers can't handle -EAGAIN, hence return
1135 * -EIO unconditionally for these. */
1136 if (!interruptible)
1137 return -EIO;
1138
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001139 /* Recovery complete, but the reset failed ... */
1140 if (i915_terminally_wedged(error))
Chris Wilsonb3612372012-08-24 09:35:08 +01001141 return -EIO;
1142
McAulay, Alistair6689c162014-08-15 18:51:35 +01001143 /*
1144 * Check if GPU Reset is in progress - we need intel_ring_begin
1145 * to work properly to reinit the hw state while the gpu is
1146 * still marked as reset-in-progress. Handle this with a flag.
1147 */
1148 if (!error->reload_in_reset)
1149 return -EAGAIN;
Chris Wilsonb3612372012-08-24 09:35:08 +01001150 }
1151
1152 return 0;
1153}
1154
1155/*
John Harrisonb6660d52014-11-24 18:49:30 +00001156 * Compare arbitrary request against outstanding lazy request. Emit on match.
Chris Wilsonb3612372012-08-24 09:35:08 +01001157 */
Sourab Gupta84c33a62014-06-02 16:47:17 +05301158int
John Harrisonb6660d52014-11-24 18:49:30 +00001159i915_gem_check_olr(struct drm_i915_gem_request *req)
Chris Wilsonb3612372012-08-24 09:35:08 +01001160{
1161 int ret;
1162
John Harrisonb6660d52014-11-24 18:49:30 +00001163 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
Chris Wilsonb3612372012-08-24 09:35:08 +01001164
1165 ret = 0;
John Harrisonb6660d52014-11-24 18:49:30 +00001166 if (req == req->ring->outstanding_lazy_request)
John Harrison9400ae52014-11-24 18:49:36 +00001167 ret = i915_add_request(req->ring);
Chris Wilsonb3612372012-08-24 09:35:08 +01001168
1169 return ret;
1170}
1171
Chris Wilson094f9a52013-09-25 17:34:55 +01001172static void fake_irq(unsigned long data)
1173{
1174 wake_up_process((struct task_struct *)data);
1175}
1176
1177static bool missed_irq(struct drm_i915_private *dev_priv,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001178 struct intel_engine_cs *ring)
Chris Wilson094f9a52013-09-25 17:34:55 +01001179{
1180 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1181}
1182
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001183static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1184{
1185 if (file_priv == NULL)
1186 return true;
1187
1188 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1189}
1190
Chris Wilsonb3612372012-08-24 09:35:08 +01001191/**
John Harrison9c654812014-11-24 18:49:35 +00001192 * __i915_wait_request - wait until execution of request has finished
1193 * @req: duh!
1194 * @reset_counter: reset sequence associated with the given request
Chris Wilsonb3612372012-08-24 09:35:08 +01001195 * @interruptible: do an interruptible wait (normally yes)
1196 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1197 *
Daniel Vetterf69061b2012-12-06 09:01:42 +01001198 * Note: It is of utmost importance that the passed in seqno and reset_counter
1199 * values have been read by the caller in an smp safe manner. Where read-side
1200 * locks are involved, it is sufficient to read the reset_counter before
1201 * unlocking the lock that protects the seqno. For lockless tricks, the
1202 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1203 * inserted.
1204 *
John Harrison9c654812014-11-24 18:49:35 +00001205 * Returns 0 if the request was found within the alloted time. Else returns the
Chris Wilsonb3612372012-08-24 09:35:08 +01001206 * errno with remaining time filled in timeout argument.
1207 */
John Harrison9c654812014-11-24 18:49:35 +00001208int __i915_wait_request(struct drm_i915_gem_request *req,
Daniel Vetterf69061b2012-12-06 09:01:42 +01001209 unsigned reset_counter,
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001210 bool interruptible,
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001211 s64 *timeout,
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001212 struct drm_i915_file_private *file_priv)
Chris Wilsonb3612372012-08-24 09:35:08 +01001213{
John Harrison9c654812014-11-24 18:49:35 +00001214 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001215 struct drm_device *dev = ring->dev;
Jani Nikula3e31c6c2014-03-31 14:27:16 +03001216 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppala168c3f22013-12-12 17:54:42 +02001217 const bool irq_test_in_progress =
1218 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
Chris Wilson094f9a52013-09-25 17:34:55 +01001219 DEFINE_WAIT(wait);
Mika Kuoppala47e9766d2013-12-10 17:02:43 +02001220 unsigned long timeout_expire;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001221 s64 before, now;
Chris Wilsonb3612372012-08-24 09:35:08 +01001222 int ret;
1223
Jesse Barnes9df7575f2014-06-20 09:29:20 -07001224 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
Paulo Zanonic67a4702013-08-19 13:18:09 -03001225
John Harrison1b5a4332014-11-24 18:49:42 +00001226 if (i915_gem_request_completed(req, true))
Chris Wilsonb3612372012-08-24 09:35:08 +01001227 return 0;
1228
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001229 timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
Chris Wilsonb3612372012-08-24 09:35:08 +01001230
Chris Wilsonec5cc0f2014-06-12 10:28:55 +01001231 if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001232 gen6_rps_boost(dev_priv);
1233 if (file_priv)
1234 mod_delayed_work(dev_priv->wq,
1235 &file_priv->mm.idle_work,
1236 msecs_to_jiffies(100));
1237 }
1238
Mika Kuoppala168c3f22013-12-12 17:54:42 +02001239 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
Chris Wilsonb3612372012-08-24 09:35:08 +01001240 return -ENODEV;
1241
Chris Wilson094f9a52013-09-25 17:34:55 +01001242 /* Record current time in case interrupted by signal, or wedged */
John Harrison74328ee2014-11-24 18:49:38 +00001243 trace_i915_gem_request_wait_begin(req);
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001244 before = ktime_get_raw_ns();
Chris Wilson094f9a52013-09-25 17:34:55 +01001245 for (;;) {
1246 struct timer_list timer;
Chris Wilsonb3612372012-08-24 09:35:08 +01001247
Chris Wilson094f9a52013-09-25 17:34:55 +01001248 prepare_to_wait(&ring->irq_queue, &wait,
1249 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
Chris Wilsonb3612372012-08-24 09:35:08 +01001250
Daniel Vetterf69061b2012-12-06 09:01:42 +01001251 /* We need to check whether any gpu reset happened in between
1252 * the caller grabbing the seqno and now ... */
Chris Wilson094f9a52013-09-25 17:34:55 +01001253 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1254 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1255 * is truely gone. */
1256 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1257 if (ret == 0)
1258 ret = -EAGAIN;
1259 break;
1260 }
Daniel Vetterf69061b2012-12-06 09:01:42 +01001261
John Harrison1b5a4332014-11-24 18:49:42 +00001262 if (i915_gem_request_completed(req, false)) {
Chris Wilson094f9a52013-09-25 17:34:55 +01001263 ret = 0;
1264 break;
1265 }
Chris Wilsonb3612372012-08-24 09:35:08 +01001266
Chris Wilson094f9a52013-09-25 17:34:55 +01001267 if (interruptible && signal_pending(current)) {
1268 ret = -ERESTARTSYS;
1269 break;
1270 }
1271
Mika Kuoppala47e9766d2013-12-10 17:02:43 +02001272 if (timeout && time_after_eq(jiffies, timeout_expire)) {
Chris Wilson094f9a52013-09-25 17:34:55 +01001273 ret = -ETIME;
1274 break;
1275 }
1276
1277 timer.function = NULL;
1278 if (timeout || missed_irq(dev_priv, ring)) {
Mika Kuoppala47e9766d2013-12-10 17:02:43 +02001279 unsigned long expire;
1280
Chris Wilson094f9a52013-09-25 17:34:55 +01001281 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
Mika Kuoppala47e9766d2013-12-10 17:02:43 +02001282 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
Chris Wilson094f9a52013-09-25 17:34:55 +01001283 mod_timer(&timer, expire);
1284 }
1285
Chris Wilson5035c272013-10-04 09:58:46 +01001286 io_schedule();
Chris Wilson094f9a52013-09-25 17:34:55 +01001287
Chris Wilson094f9a52013-09-25 17:34:55 +01001288 if (timer.function) {
1289 del_singleshot_timer_sync(&timer);
1290 destroy_timer_on_stack(&timer);
1291 }
1292 }
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001293 now = ktime_get_raw_ns();
John Harrison74328ee2014-11-24 18:49:38 +00001294 trace_i915_gem_request_wait_end(req);
Chris Wilsonb3612372012-08-24 09:35:08 +01001295
Mika Kuoppala168c3f22013-12-12 17:54:42 +02001296 if (!irq_test_in_progress)
1297 ring->irq_put(ring);
Chris Wilson094f9a52013-09-25 17:34:55 +01001298
1299 finish_wait(&ring->irq_queue, &wait);
Chris Wilsonb3612372012-08-24 09:35:08 +01001300
1301 if (timeout) {
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001302 s64 tres = *timeout - (now - before);
1303
1304 *timeout = tres < 0 ? 0 : tres;
Chris Wilsonb3612372012-08-24 09:35:08 +01001305 }
1306
Chris Wilson094f9a52013-09-25 17:34:55 +01001307 return ret;
Chris Wilsonb3612372012-08-24 09:35:08 +01001308}
1309
1310/**
Daniel Vettera4b3a572014-11-26 14:17:05 +01001311 * Waits for a request to be signaled, and cleans up the
Chris Wilsonb3612372012-08-24 09:35:08 +01001312 * request and object lists appropriately for that event.
1313 */
1314int
Daniel Vettera4b3a572014-11-26 14:17:05 +01001315i915_wait_request(struct drm_i915_gem_request *req)
Chris Wilsonb3612372012-08-24 09:35:08 +01001316{
Daniel Vettera4b3a572014-11-26 14:17:05 +01001317 struct drm_device *dev;
1318 struct drm_i915_private *dev_priv;
1319 bool interruptible;
Ander Conselvan de Oliveira16e9a212014-11-06 09:26:38 +02001320 unsigned reset_counter;
Chris Wilsonb3612372012-08-24 09:35:08 +01001321 int ret;
1322
Daniel Vettera4b3a572014-11-26 14:17:05 +01001323 BUG_ON(req == NULL);
1324
1325 dev = req->ring->dev;
1326 dev_priv = dev->dev_private;
1327 interruptible = dev_priv->mm.interruptible;
1328
Chris Wilsonb3612372012-08-24 09:35:08 +01001329 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
Chris Wilsonb3612372012-08-24 09:35:08 +01001330
Daniel Vetter33196de2012-11-14 17:14:05 +01001331 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
Chris Wilsonb3612372012-08-24 09:35:08 +01001332 if (ret)
1333 return ret;
1334
Daniel Vettera4b3a572014-11-26 14:17:05 +01001335 ret = i915_gem_check_olr(req);
Chris Wilsonb3612372012-08-24 09:35:08 +01001336 if (ret)
1337 return ret;
1338
Ander Conselvan de Oliveira16e9a212014-11-06 09:26:38 +02001339 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Daniel Vettera4b3a572014-11-26 14:17:05 +01001340 i915_gem_request_reference(req);
John Harrison9c654812014-11-24 18:49:35 +00001341 ret = __i915_wait_request(req, reset_counter,
1342 interruptible, NULL, NULL);
Daniel Vettera4b3a572014-11-26 14:17:05 +01001343 i915_gem_request_unreference(req);
1344 return ret;
Chris Wilsonb3612372012-08-24 09:35:08 +01001345}
1346
Chris Wilsond26e3af2013-06-29 22:05:26 +01001347static int
John Harrison8e6395492014-10-30 18:40:53 +00001348i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
Chris Wilsond26e3af2013-06-29 22:05:26 +01001349{
Chris Wilsonc8725f32014-03-17 12:21:55 +00001350 if (!obj->active)
1351 return 0;
Chris Wilsond26e3af2013-06-29 22:05:26 +01001352
1353 /* Manually manage the write flush as we may have not yet
1354 * retired the buffer.
1355 *
John Harrison97b2a6a2014-11-24 18:49:26 +00001356 * Note that the last_write_req is always the earlier of
1357 * the two (read/write) requests, so if we haved successfully waited,
Chris Wilsond26e3af2013-06-29 22:05:26 +01001358 * we know we have passed the last write.
1359 */
John Harrison97b2a6a2014-11-24 18:49:26 +00001360 i915_gem_request_assign(&obj->last_write_req, NULL);
Chris Wilsond26e3af2013-06-29 22:05:26 +01001361
1362 return 0;
1363}
1364
Chris Wilsonb3612372012-08-24 09:35:08 +01001365/**
1366 * Ensures that all rendering to the object has completed and the object is
1367 * safe to unbind from the GTT or access from the CPU.
1368 */
1369static __must_check int
1370i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1371 bool readonly)
1372{
John Harrison97b2a6a2014-11-24 18:49:26 +00001373 struct drm_i915_gem_request *req;
Chris Wilsonb3612372012-08-24 09:35:08 +01001374 int ret;
1375
John Harrison97b2a6a2014-11-24 18:49:26 +00001376 req = readonly ? obj->last_write_req : obj->last_read_req;
1377 if (!req)
Chris Wilsonb3612372012-08-24 09:35:08 +01001378 return 0;
1379
Daniel Vettera4b3a572014-11-26 14:17:05 +01001380 ret = i915_wait_request(req);
Chris Wilsonb3612372012-08-24 09:35:08 +01001381 if (ret)
1382 return ret;
1383
John Harrison8e6395492014-10-30 18:40:53 +00001384 return i915_gem_object_wait_rendering__tail(obj);
Chris Wilsonb3612372012-08-24 09:35:08 +01001385}
1386
Chris Wilson3236f572012-08-24 09:35:09 +01001387/* A nonblocking variant of the above wait. This is a highly dangerous routine
1388 * as the object state may change during this call.
1389 */
1390static __must_check int
1391i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
Chris Wilson6e4930f2014-02-07 18:37:06 -02001392 struct drm_i915_file_private *file_priv,
Chris Wilson3236f572012-08-24 09:35:09 +01001393 bool readonly)
1394{
John Harrison97b2a6a2014-11-24 18:49:26 +00001395 struct drm_i915_gem_request *req;
Chris Wilson3236f572012-08-24 09:35:09 +01001396 struct drm_device *dev = obj->base.dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf69061b2012-12-06 09:01:42 +01001398 unsigned reset_counter;
Chris Wilson3236f572012-08-24 09:35:09 +01001399 int ret;
1400
1401 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1402 BUG_ON(!dev_priv->mm.interruptible);
1403
John Harrison97b2a6a2014-11-24 18:49:26 +00001404 req = readonly ? obj->last_write_req : obj->last_read_req;
1405 if (!req)
Chris Wilson3236f572012-08-24 09:35:09 +01001406 return 0;
1407
Daniel Vetter33196de2012-11-14 17:14:05 +01001408 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
Chris Wilson3236f572012-08-24 09:35:09 +01001409 if (ret)
1410 return ret;
1411
John Harrisonb6660d52014-11-24 18:49:30 +00001412 ret = i915_gem_check_olr(req);
Chris Wilson3236f572012-08-24 09:35:09 +01001413 if (ret)
1414 return ret;
1415
Daniel Vetterf69061b2012-12-06 09:01:42 +01001416 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
John Harrisonff865882014-11-24 18:49:28 +00001417 i915_gem_request_reference(req);
Chris Wilson3236f572012-08-24 09:35:09 +01001418 mutex_unlock(&dev->struct_mutex);
John Harrison9c654812014-11-24 18:49:35 +00001419 ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
Chris Wilson3236f572012-08-24 09:35:09 +01001420 mutex_lock(&dev->struct_mutex);
John Harrisonff865882014-11-24 18:49:28 +00001421 i915_gem_request_unreference(req);
Chris Wilsond26e3af2013-06-29 22:05:26 +01001422 if (ret)
1423 return ret;
Chris Wilson3236f572012-08-24 09:35:09 +01001424
John Harrison8e6395492014-10-30 18:40:53 +00001425 return i915_gem_object_wait_rendering__tail(obj);
Chris Wilson3236f572012-08-24 09:35:09 +01001426}
1427
Eric Anholt673a3942008-07-30 12:06:12 -07001428/**
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001429 * Called when user space prepares to use an object with the CPU, either
1430 * through the mmap ioctl's mapping or a GTT mapping.
Eric Anholt673a3942008-07-30 12:06:12 -07001431 */
1432int
1433i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00001434 struct drm_file *file)
Eric Anholt673a3942008-07-30 12:06:12 -07001435{
1436 struct drm_i915_gem_set_domain *args = data;
Chris Wilson05394f32010-11-08 19:18:58 +00001437 struct drm_i915_gem_object *obj;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001438 uint32_t read_domains = args->read_domains;
1439 uint32_t write_domain = args->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07001440 int ret;
1441
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001442 /* Only handle setting domains to types used by the CPU. */
Chris Wilson21d509e2009-06-06 09:46:02 +01001443 if (write_domain & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001444 return -EINVAL;
1445
Chris Wilson21d509e2009-06-06 09:46:02 +01001446 if (read_domains & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001447 return -EINVAL;
1448
1449 /* Having something in the write domain implies it's in the read
1450 * domain, and only that read domain. Enforce that in the request.
1451 */
1452 if (write_domain != 0 && read_domains != write_domain)
1453 return -EINVAL;
1454
Chris Wilson76c1dec2010-09-25 11:22:51 +01001455 ret = i915_mutex_lock_interruptible(dev);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001456 if (ret)
Chris Wilson76c1dec2010-09-25 11:22:51 +01001457 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07001458
Chris Wilson05394f32010-11-08 19:18:58 +00001459 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00001460 if (&obj->base == NULL) {
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001461 ret = -ENOENT;
1462 goto unlock;
Chris Wilson76c1dec2010-09-25 11:22:51 +01001463 }
Jesse Barnes652c3932009-08-17 13:31:43 -07001464
Chris Wilson3236f572012-08-24 09:35:09 +01001465 /* Try to flush the object off the GPU without holding the lock.
1466 * We will repeat the flush holding the lock in the normal manner
1467 * to catch cases where we are gazumped.
1468 */
Chris Wilson6e4930f2014-02-07 18:37:06 -02001469 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1470 file->driver_priv,
1471 !write_domain);
Chris Wilson3236f572012-08-24 09:35:09 +01001472 if (ret)
1473 goto unref;
1474
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001475 if (read_domains & I915_GEM_DOMAIN_GTT) {
1476 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
Eric Anholt02354392008-11-26 13:58:13 -08001477
1478 /* Silently promote "you're not bound, there was nothing to do"
1479 * to success, since the client was just asking us to
1480 * make sure everything was done.
1481 */
1482 if (ret == -EINVAL)
1483 ret = 0;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001484 } else {
Eric Anholte47c68e2008-11-14 13:35:19 -08001485 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001486 }
1487
Chris Wilson3236f572012-08-24 09:35:09 +01001488unref:
Chris Wilson05394f32010-11-08 19:18:58 +00001489 drm_gem_object_unreference(&obj->base);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001490unlock:
Eric Anholt673a3942008-07-30 12:06:12 -07001491 mutex_unlock(&dev->struct_mutex);
1492 return ret;
1493}
1494
1495/**
1496 * Called when user space has done writes to this buffer
1497 */
1498int
1499i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00001500 struct drm_file *file)
Eric Anholt673a3942008-07-30 12:06:12 -07001501{
1502 struct drm_i915_gem_sw_finish *args = data;
Chris Wilson05394f32010-11-08 19:18:58 +00001503 struct drm_i915_gem_object *obj;
Eric Anholt673a3942008-07-30 12:06:12 -07001504 int ret = 0;
1505
Chris Wilson76c1dec2010-09-25 11:22:51 +01001506 ret = i915_mutex_lock_interruptible(dev);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001507 if (ret)
Chris Wilson76c1dec2010-09-25 11:22:51 +01001508 return ret;
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001509
Chris Wilson05394f32010-11-08 19:18:58 +00001510 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00001511 if (&obj->base == NULL) {
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001512 ret = -ENOENT;
1513 goto unlock;
Eric Anholt673a3942008-07-30 12:06:12 -07001514 }
1515
Eric Anholt673a3942008-07-30 12:06:12 -07001516 /* Pinned buffers may be scanout, so flush the cache */
Chris Wilson2c225692013-08-09 12:26:45 +01001517 if (obj->pin_display)
1518 i915_gem_object_flush_cpu_write_domain(obj, true);
Eric Anholte47c68e2008-11-14 13:35:19 -08001519
Chris Wilson05394f32010-11-08 19:18:58 +00001520 drm_gem_object_unreference(&obj->base);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001521unlock:
Eric Anholt673a3942008-07-30 12:06:12 -07001522 mutex_unlock(&dev->struct_mutex);
1523 return ret;
1524}
1525
1526/**
1527 * Maps the contents of an object, returning the address it is mapped
1528 * into.
1529 *
1530 * While the mapping holds a reference on the contents of the object, it doesn't
1531 * imply a ref on the object itself.
Daniel Vetter34367382014-10-16 12:28:18 +02001532 *
1533 * IMPORTANT:
1534 *
1535 * DRM driver writers who look a this function as an example for how to do GEM
1536 * mmap support, please don't implement mmap support like here. The modern way
1537 * to implement DRM mmap support is with an mmap offset ioctl (like
1538 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1539 * That way debug tooling like valgrind will understand what's going on, hiding
1540 * the mmap call in a driver private ioctl will break that. The i915 driver only
1541 * does cpu mmaps this way because we didn't know better.
Eric Anholt673a3942008-07-30 12:06:12 -07001542 */
1543int
1544i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00001545 struct drm_file *file)
Eric Anholt673a3942008-07-30 12:06:12 -07001546{
1547 struct drm_i915_gem_mmap *args = data;
1548 struct drm_gem_object *obj;
Eric Anholt673a3942008-07-30 12:06:12 -07001549 unsigned long addr;
1550
Chris Wilson05394f32010-11-08 19:18:58 +00001551 obj = drm_gem_object_lookup(dev, file, args->handle);
Eric Anholt673a3942008-07-30 12:06:12 -07001552 if (obj == NULL)
Chris Wilsonbf79cb92010-08-04 14:19:46 +01001553 return -ENOENT;
Eric Anholt673a3942008-07-30 12:06:12 -07001554
Daniel Vetter1286ff72012-05-10 15:25:09 +02001555 /* prime objects have no backing filp to GEM mmap
1556 * pages from.
1557 */
1558 if (!obj->filp) {
1559 drm_gem_object_unreference_unlocked(obj);
1560 return -EINVAL;
1561 }
1562
Linus Torvalds6be5ceb2012-04-20 17:13:58 -07001563 addr = vm_mmap(obj->filp, 0, args->size,
Eric Anholt673a3942008-07-30 12:06:12 -07001564 PROT_READ | PROT_WRITE, MAP_SHARED,
1565 args->offset);
Luca Barbieribc9025b2010-02-09 05:49:12 +00001566 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001567 if (IS_ERR((void *)addr))
1568 return addr;
1569
1570 args->addr_ptr = (uint64_t) addr;
1571
1572 return 0;
1573}
1574
Jesse Barnesde151cf2008-11-12 10:03:55 -08001575/**
1576 * i915_gem_fault - fault a page into the GTT
1577 * vma: VMA in question
1578 * vmf: fault info
1579 *
1580 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1581 * from userspace. The fault handler takes care of binding the object to
1582 * the GTT (if needed), allocating and programming a fence register (again,
1583 * only if needed based on whether the old reg is still valid or the object
1584 * is tiled) and inserting a new PTE into the faulting process.
1585 *
1586 * Note that the faulting process may involve evicting existing objects
1587 * from the GTT and/or fence registers to make room. So performance may
1588 * suffer if the GTT working set is large or there are few fence registers
1589 * left.
1590 */
1591int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1592{
Chris Wilson05394f32010-11-08 19:18:58 +00001593 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1594 struct drm_device *dev = obj->base.dev;
Jani Nikula3e31c6c2014-03-31 14:27:16 +03001595 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001596 pgoff_t page_offset;
1597 unsigned long pfn;
1598 int ret = 0;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001599 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001600
Paulo Zanonif65c9162013-11-27 18:20:34 -02001601 intel_runtime_pm_get(dev_priv);
1602
Jesse Barnesde151cf2008-11-12 10:03:55 -08001603 /* We don't use vmf->pgoff since that has the fake offset */
1604 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1605 PAGE_SHIFT;
1606
Chris Wilsond9bc7e92011-02-07 13:09:31 +00001607 ret = i915_mutex_lock_interruptible(dev);
1608 if (ret)
1609 goto out;
Chris Wilsona00b10c2010-09-24 21:15:47 +01001610
Chris Wilsondb53a302011-02-03 11:57:46 +00001611 trace_i915_gem_object_fault(obj, page_offset, true, write);
1612
Chris Wilson6e4930f2014-02-07 18:37:06 -02001613 /* Try to flush the object off the GPU first without holding the lock.
1614 * Upon reacquiring the lock, we will perform our sanity checks and then
1615 * repeat the flush holding the lock in the normal manner to catch cases
1616 * where we are gazumped.
1617 */
1618 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1619 if (ret)
1620 goto unlock;
1621
Chris Wilsoneb119bd2012-12-16 12:43:36 +00001622 /* Access to snoopable pages through the GTT is incoherent. */
1623 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
Chris Wilsonddeff6e2014-05-28 16:16:41 +01001624 ret = -EFAULT;
Chris Wilsoneb119bd2012-12-16 12:43:36 +00001625 goto unlock;
1626 }
1627
Chris Wilsond9bc7e92011-02-07 13:09:31 +00001628 /* Now bind it into the GTT if needed */
Daniel Vetter1ec9e262014-02-14 14:01:11 +01001629 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
Chris Wilsond9e86c02010-11-10 16:40:20 +00001630 if (ret)
1631 goto unlock;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001632
Chris Wilsonc9839302012-11-20 10:45:17 +00001633 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1634 if (ret)
1635 goto unpin;
1636
1637 ret = i915_gem_object_get_fence(obj);
1638 if (ret)
1639 goto unpin;
Chris Wilson7d1c4802010-08-07 21:45:03 +01001640
Chris Wilsonb90b91d2014-06-10 12:14:40 +01001641 /* Finally, remap it using the new GTT offset */
Ben Widawskyf343c5f2013-07-05 14:41:04 -07001642 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1643 pfn >>= PAGE_SHIFT;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001644
Chris Wilsonb90b91d2014-06-10 12:14:40 +01001645 if (!obj->fault_mappable) {
Ville Syrjäläbeff0d02014-06-17 21:03:00 +03001646 unsigned long size = min_t(unsigned long,
1647 vma->vm_end - vma->vm_start,
1648 obj->base.size);
Chris Wilsonb90b91d2014-06-10 12:14:40 +01001649 int i;
1650
Ville Syrjäläbeff0d02014-06-17 21:03:00 +03001651 for (i = 0; i < size >> PAGE_SHIFT; i++) {
Chris Wilsonb90b91d2014-06-10 12:14:40 +01001652 ret = vm_insert_pfn(vma,
1653 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1654 pfn + i);
1655 if (ret)
1656 break;
1657 }
1658
1659 obj->fault_mappable = true;
1660 } else
1661 ret = vm_insert_pfn(vma,
1662 (unsigned long)vmf->virtual_address,
1663 pfn + page_offset);
Chris Wilsonc9839302012-11-20 10:45:17 +00001664unpin:
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08001665 i915_gem_object_ggtt_unpin(obj);
Chris Wilsonc7150892009-09-23 00:43:56 +01001666unlock:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001667 mutex_unlock(&dev->struct_mutex);
Chris Wilsond9bc7e92011-02-07 13:09:31 +00001668out:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001669 switch (ret) {
Chris Wilsond9bc7e92011-02-07 13:09:31 +00001670 case -EIO:
Daniel Vetter2232f032014-09-04 09:36:18 +02001671 /*
1672 * We eat errors when the gpu is terminally wedged to avoid
1673 * userspace unduly crashing (gl has no provisions for mmaps to
1674 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1675 * and so needs to be reported.
1676 */
1677 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
Paulo Zanonif65c9162013-11-27 18:20:34 -02001678 ret = VM_FAULT_SIGBUS;
1679 break;
1680 }
Chris Wilson045e7692010-11-07 09:18:22 +00001681 case -EAGAIN:
Daniel Vetter571c6082013-09-12 17:57:28 +02001682 /*
1683 * EAGAIN means the gpu is hung and we'll wait for the error
1684 * handler to reset everything when re-faulting in
1685 * i915_mutex_lock_interruptible.
Chris Wilsond9bc7e92011-02-07 13:09:31 +00001686 */
Chris Wilsonc7150892009-09-23 00:43:56 +01001687 case 0:
1688 case -ERESTARTSYS:
Chris Wilsonbed636a2011-02-11 20:31:19 +00001689 case -EINTR:
Dmitry Rogozhkine79e0fe2012-10-03 17:15:26 +03001690 case -EBUSY:
1691 /*
1692 * EBUSY is ok: this just means that another thread
1693 * already did the job.
1694 */
Paulo Zanonif65c9162013-11-27 18:20:34 -02001695 ret = VM_FAULT_NOPAGE;
1696 break;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001697 case -ENOMEM:
Paulo Zanonif65c9162013-11-27 18:20:34 -02001698 ret = VM_FAULT_OOM;
1699 break;
Daniel Vettera7c2e1a2012-10-17 11:17:16 +02001700 case -ENOSPC:
Chris Wilson45d67812014-01-31 11:34:57 +00001701 case -EFAULT:
Paulo Zanonif65c9162013-11-27 18:20:34 -02001702 ret = VM_FAULT_SIGBUS;
1703 break;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001704 default:
Daniel Vettera7c2e1a2012-10-17 11:17:16 +02001705 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
Paulo Zanonif65c9162013-11-27 18:20:34 -02001706 ret = VM_FAULT_SIGBUS;
1707 break;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001708 }
Paulo Zanonif65c9162013-11-27 18:20:34 -02001709
1710 intel_runtime_pm_put(dev_priv);
1711 return ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001712}
1713
1714/**
Chris Wilson901782b2009-07-10 08:18:50 +01001715 * i915_gem_release_mmap - remove physical page mappings
1716 * @obj: obj in question
1717 *
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001718 * Preserve the reservation of the mmapping with the DRM core code, but
Chris Wilson901782b2009-07-10 08:18:50 +01001719 * relinquish ownership of the pages back to the system.
1720 *
1721 * It is vital that we remove the page mapping if we have mapped a tiled
1722 * object through the GTT and then lose the fence register due to
1723 * resource pressure. Similarly if the object has been moved out of the
1724 * aperture, than pages mapped into userspace must be revoked. Removing the
1725 * mapping will then trigger a page fault on the next user access, allowing
1726 * fixup by i915_gem_fault().
1727 */
Eric Anholtd05ca302009-07-10 13:02:26 -07001728void
Chris Wilson05394f32010-11-08 19:18:58 +00001729i915_gem_release_mmap(struct drm_i915_gem_object *obj)
Chris Wilson901782b2009-07-10 08:18:50 +01001730{
Chris Wilson6299f992010-11-24 12:23:44 +00001731 if (!obj->fault_mappable)
1732 return;
Chris Wilson901782b2009-07-10 08:18:50 +01001733
David Herrmann6796cb12014-01-03 14:24:19 +01001734 drm_vma_node_unmap(&obj->base.vma_node,
1735 obj->base.dev->anon_inode->i_mapping);
Chris Wilson6299f992010-11-24 12:23:44 +00001736 obj->fault_mappable = false;
Chris Wilson901782b2009-07-10 08:18:50 +01001737}
1738
Chris Wilsoneedd10f2014-06-16 08:57:44 +01001739void
1740i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1741{
1742 struct drm_i915_gem_object *obj;
1743
1744 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1745 i915_gem_release_mmap(obj);
1746}
1747
Imre Deak0fa87792013-01-07 21:47:35 +02001748uint32_t
Chris Wilsone28f8712011-07-18 13:11:49 -07001749i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
Chris Wilson92b88ae2010-11-09 11:47:32 +00001750{
Chris Wilsone28f8712011-07-18 13:11:49 -07001751 uint32_t gtt_size;
Chris Wilson92b88ae2010-11-09 11:47:32 +00001752
1753 if (INTEL_INFO(dev)->gen >= 4 ||
Chris Wilsone28f8712011-07-18 13:11:49 -07001754 tiling_mode == I915_TILING_NONE)
1755 return size;
Chris Wilson92b88ae2010-11-09 11:47:32 +00001756
1757 /* Previous chips need a power-of-two fence region when tiling */
1758 if (INTEL_INFO(dev)->gen == 3)
Chris Wilsone28f8712011-07-18 13:11:49 -07001759 gtt_size = 1024*1024;
Chris Wilson92b88ae2010-11-09 11:47:32 +00001760 else
Chris Wilsone28f8712011-07-18 13:11:49 -07001761 gtt_size = 512*1024;
Chris Wilson92b88ae2010-11-09 11:47:32 +00001762
Chris Wilsone28f8712011-07-18 13:11:49 -07001763 while (gtt_size < size)
1764 gtt_size <<= 1;
Chris Wilson92b88ae2010-11-09 11:47:32 +00001765
Chris Wilsone28f8712011-07-18 13:11:49 -07001766 return gtt_size;
Chris Wilson92b88ae2010-11-09 11:47:32 +00001767}
1768
Jesse Barnesde151cf2008-11-12 10:03:55 -08001769/**
1770 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1771 * @obj: object to check
1772 *
1773 * Return the required GTT alignment for an object, taking into account
Daniel Vetter5e783302010-11-14 22:32:36 +01001774 * potential fence register mapping.
Jesse Barnesde151cf2008-11-12 10:03:55 -08001775 */
Imre Deakd8651102013-01-07 21:47:33 +02001776uint32_t
1777i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1778 int tiling_mode, bool fenced)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001779{
Jesse Barnesde151cf2008-11-12 10:03:55 -08001780 /*
1781 * Minimum alignment is 4k (GTT page size), but might be greater
1782 * if a fence register is needed for the object.
1783 */
Imre Deakd8651102013-01-07 21:47:33 +02001784 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
Chris Wilsone28f8712011-07-18 13:11:49 -07001785 tiling_mode == I915_TILING_NONE)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001786 return 4096;
1787
1788 /*
1789 * Previous chips need to be aligned to the size of the smallest
1790 * fence register that can contain the object.
1791 */
Chris Wilsone28f8712011-07-18 13:11:49 -07001792 return i915_gem_get_gtt_size(dev, size, tiling_mode);
Chris Wilsona00b10c2010-09-24 21:15:47 +01001793}
1794
Chris Wilsond8cb5082012-08-11 15:41:03 +01001795static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1796{
1797 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1798 int ret;
1799
David Herrmann0de23972013-07-24 21:07:52 +02001800 if (drm_vma_node_has_offset(&obj->base.vma_node))
Chris Wilsond8cb5082012-08-11 15:41:03 +01001801 return 0;
1802
Daniel Vetterda494d72012-12-20 15:11:16 +01001803 dev_priv->mm.shrinker_no_lock_stealing = true;
1804
Chris Wilsond8cb5082012-08-11 15:41:03 +01001805 ret = drm_gem_create_mmap_offset(&obj->base);
1806 if (ret != -ENOSPC)
Daniel Vetterda494d72012-12-20 15:11:16 +01001807 goto out;
Chris Wilsond8cb5082012-08-11 15:41:03 +01001808
1809 /* Badly fragmented mmap space? The only way we can recover
1810 * space is by destroying unwanted objects. We can't randomly release
1811 * mmap_offsets as userspace expects them to be persistent for the
1812 * lifetime of the objects. The closest we can is to release the
1813 * offsets on purgeable objects by truncating it and marking it purged,
1814 * which prevents userspace from ever using that object again.
1815 */
Chris Wilson21ab4e72014-09-09 11:16:08 +01001816 i915_gem_shrink(dev_priv,
1817 obj->base.size >> PAGE_SHIFT,
1818 I915_SHRINK_BOUND |
1819 I915_SHRINK_UNBOUND |
1820 I915_SHRINK_PURGEABLE);
Chris Wilsond8cb5082012-08-11 15:41:03 +01001821 ret = drm_gem_create_mmap_offset(&obj->base);
1822 if (ret != -ENOSPC)
Daniel Vetterda494d72012-12-20 15:11:16 +01001823 goto out;
Chris Wilsond8cb5082012-08-11 15:41:03 +01001824
1825 i915_gem_shrink_all(dev_priv);
Daniel Vetterda494d72012-12-20 15:11:16 +01001826 ret = drm_gem_create_mmap_offset(&obj->base);
1827out:
1828 dev_priv->mm.shrinker_no_lock_stealing = false;
1829
1830 return ret;
Chris Wilsond8cb5082012-08-11 15:41:03 +01001831}
1832
1833static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1834{
Chris Wilsond8cb5082012-08-11 15:41:03 +01001835 drm_gem_free_mmap_offset(&obj->base);
1836}
1837
Thomas Hellstrom355a7012014-11-20 09:56:25 +01001838static int
Dave Airlieff72145b2011-02-07 12:16:14 +10001839i915_gem_mmap_gtt(struct drm_file *file,
1840 struct drm_device *dev,
Thomas Hellstrom355a7012014-11-20 09:56:25 +01001841 uint32_t handle, bool dumb,
Dave Airlieff72145b2011-02-07 12:16:14 +10001842 uint64_t *offset)
Jesse Barnesde151cf2008-11-12 10:03:55 -08001843{
Chris Wilsonda761a62010-10-27 17:37:08 +01001844 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00001845 struct drm_i915_gem_object *obj;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001846 int ret;
1847
Chris Wilson76c1dec2010-09-25 11:22:51 +01001848 ret = i915_mutex_lock_interruptible(dev);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001849 if (ret)
Chris Wilson76c1dec2010-09-25 11:22:51 +01001850 return ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001851
Dave Airlieff72145b2011-02-07 12:16:14 +10001852 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00001853 if (&obj->base == NULL) {
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001854 ret = -ENOENT;
1855 goto unlock;
1856 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001857
Thomas Hellstrom355a7012014-11-20 09:56:25 +01001858 /*
1859 * We don't allow dumb mmaps on objects created using another
1860 * interface.
1861 */
1862 WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach),
1863 "Illegal dumb map of accelerated buffer.\n");
1864
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001865 if (obj->base.size > dev_priv->gtt.mappable_end) {
Chris Wilsonda761a62010-10-27 17:37:08 +01001866 ret = -E2BIG;
Eric Anholtff56b0b2011-10-31 23:16:21 -07001867 goto out;
Chris Wilsonda761a62010-10-27 17:37:08 +01001868 }
1869
Chris Wilson05394f32010-11-08 19:18:58 +00001870 if (obj->madv != I915_MADV_WILLNEED) {
Chris Wilsonbd9b6a42014-02-10 09:03:50 +00001871 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
Chris Wilson8c99e572014-01-31 11:34:58 +00001872 ret = -EFAULT;
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001873 goto out;
Chris Wilsonab182822009-09-22 18:46:17 +01001874 }
1875
Chris Wilsond8cb5082012-08-11 15:41:03 +01001876 ret = i915_gem_object_create_mmap_offset(obj);
1877 if (ret)
1878 goto out;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001879
David Herrmann0de23972013-07-24 21:07:52 +02001880 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001881
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001882out:
Chris Wilson05394f32010-11-08 19:18:58 +00001883 drm_gem_object_unreference(&obj->base);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001884unlock:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001885 mutex_unlock(&dev->struct_mutex);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01001886 return ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001887}
1888
Thomas Hellstrom355a7012014-11-20 09:56:25 +01001889int
1890i915_gem_dumb_map_offset(struct drm_file *file,
1891 struct drm_device *dev,
1892 uint32_t handle,
1893 uint64_t *offset)
1894{
1895 return i915_gem_mmap_gtt(file, dev, handle, true, offset);
1896}
1897
Dave Airlieff72145b2011-02-07 12:16:14 +10001898/**
1899 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1900 * @dev: DRM device
1901 * @data: GTT mapping ioctl data
1902 * @file: GEM object info
1903 *
1904 * Simply returns the fake offset to userspace so it can mmap it.
1905 * The mmap call will end up in drm_gem_mmap(), which will set things
1906 * up so we can get faults in the handler above.
1907 *
1908 * The fault handler will take care of binding the object into the GTT
1909 * (since it may have been evicted to make room for something), allocating
1910 * a fence register, and mapping the appropriate aperture address into
1911 * userspace.
1912 */
1913int
1914i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1915 struct drm_file *file)
1916{
1917 struct drm_i915_gem_mmap_gtt *args = data;
1918
Thomas Hellstrom355a7012014-11-20 09:56:25 +01001919 return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset);
Dave Airlieff72145b2011-02-07 12:16:14 +10001920}
1921
Chris Wilson55372522014-03-25 13:23:06 +00001922static inline int
1923i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1924{
1925 return obj->madv == I915_MADV_DONTNEED;
1926}
1927
Daniel Vetter225067e2012-08-20 10:23:20 +02001928/* Immediately discard the backing storage */
1929static void
1930i915_gem_object_truncate(struct drm_i915_gem_object *obj)
Chris Wilsone5281cc2010-10-28 13:45:36 +01001931{
Chris Wilson4d6294bf2012-08-11 15:41:05 +01001932 i915_gem_object_free_mmap_offset(obj);
Daniel Vetter1286ff72012-05-10 15:25:09 +02001933
Chris Wilson4d6294bf2012-08-11 15:41:05 +01001934 if (obj->base.filp == NULL)
1935 return;
1936
Daniel Vetter225067e2012-08-20 10:23:20 +02001937 /* Our goal here is to return as much of the memory as
1938 * is possible back to the system as we are called from OOM.
1939 * To do this we must instruct the shmfs to drop all of its
1940 * backing pages, *now*.
Chris Wilsone5281cc2010-10-28 13:45:36 +01001941 */
Chris Wilson55372522014-03-25 13:23:06 +00001942 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
Daniel Vetter225067e2012-08-20 10:23:20 +02001943 obj->madv = __I915_MADV_PURGED;
Chris Wilsone5281cc2010-10-28 13:45:36 +01001944}
Chris Wilsone5281cc2010-10-28 13:45:36 +01001945
Chris Wilson55372522014-03-25 13:23:06 +00001946/* Try to discard unwanted pages */
1947static void
1948i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
Daniel Vetter225067e2012-08-20 10:23:20 +02001949{
Chris Wilson55372522014-03-25 13:23:06 +00001950 struct address_space *mapping;
1951
1952 switch (obj->madv) {
1953 case I915_MADV_DONTNEED:
1954 i915_gem_object_truncate(obj);
1955 case __I915_MADV_PURGED:
1956 return;
1957 }
1958
1959 if (obj->base.filp == NULL)
1960 return;
1961
1962 mapping = file_inode(obj->base.filp)->i_mapping,
1963 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
Chris Wilsone5281cc2010-10-28 13:45:36 +01001964}
1965
Chris Wilson5cdf5882010-09-27 15:51:07 +01001966static void
Chris Wilson05394f32010-11-08 19:18:58 +00001967i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07001968{
Imre Deak90797e62013-02-18 19:28:03 +02001969 struct sg_page_iter sg_iter;
1970 int ret;
Daniel Vetter1286ff72012-05-10 15:25:09 +02001971
Chris Wilson05394f32010-11-08 19:18:58 +00001972 BUG_ON(obj->madv == __I915_MADV_PURGED);
Eric Anholt856fa192009-03-19 14:10:50 -07001973
Chris Wilson6c085a72012-08-20 11:40:46 +02001974 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1975 if (ret) {
1976 /* In the event of a disaster, abandon all caches and
1977 * hope for the best.
1978 */
1979 WARN_ON(ret != -EIO);
Chris Wilson2c225692013-08-09 12:26:45 +01001980 i915_gem_clflush_object(obj, true);
Chris Wilson6c085a72012-08-20 11:40:46 +02001981 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1982 }
1983
Daniel Vetter6dacfd22011-09-12 21:30:02 +02001984 if (i915_gem_object_needs_bit17_swizzle(obj))
Eric Anholt280b7132009-03-12 16:56:27 -07001985 i915_gem_object_save_bit_17_swizzle(obj);
1986
Chris Wilson05394f32010-11-08 19:18:58 +00001987 if (obj->madv == I915_MADV_DONTNEED)
1988 obj->dirty = 0;
Chris Wilson3ef94da2009-09-14 16:50:29 +01001989
Imre Deak90797e62013-02-18 19:28:03 +02001990 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
Imre Deak2db76d72013-03-26 15:14:18 +02001991 struct page *page = sg_page_iter_page(&sg_iter);
Chris Wilson9da3da62012-06-01 15:20:22 +01001992
Chris Wilson05394f32010-11-08 19:18:58 +00001993 if (obj->dirty)
Chris Wilson9da3da62012-06-01 15:20:22 +01001994 set_page_dirty(page);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001995
Chris Wilson05394f32010-11-08 19:18:58 +00001996 if (obj->madv == I915_MADV_WILLNEED)
Chris Wilson9da3da62012-06-01 15:20:22 +01001997 mark_page_accessed(page);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001998
Chris Wilson9da3da62012-06-01 15:20:22 +01001999 page_cache_release(page);
Chris Wilson3ef94da2009-09-14 16:50:29 +01002000 }
Chris Wilson05394f32010-11-08 19:18:58 +00002001 obj->dirty = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07002002
Chris Wilson9da3da62012-06-01 15:20:22 +01002003 sg_free_table(obj->pages);
2004 kfree(obj->pages);
Chris Wilson37e680a2012-06-07 15:38:42 +01002005}
2006
Chris Wilsondd624af2013-01-15 12:39:35 +00002007int
Chris Wilson37e680a2012-06-07 15:38:42 +01002008i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2009{
2010 const struct drm_i915_gem_object_ops *ops = obj->ops;
2011
Chris Wilson2f745ad2012-09-04 21:02:58 +01002012 if (obj->pages == NULL)
Chris Wilson37e680a2012-06-07 15:38:42 +01002013 return 0;
2014
Chris Wilsona5570172012-09-04 21:02:54 +01002015 if (obj->pages_pin_count)
2016 return -EBUSY;
2017
Ben Widawsky98438772013-07-31 17:00:12 -07002018 BUG_ON(i915_gem_obj_bound_any(obj));
Ben Widawsky3e123022013-07-31 17:00:04 -07002019
Chris Wilsona2165e32012-12-03 11:49:00 +00002020 /* ->put_pages might need to allocate memory for the bit17 swizzle
2021 * array, hence protect them from being reaped by removing them from gtt
2022 * lists early. */
Ben Widawsky35c20a62013-05-31 11:28:48 -07002023 list_del(&obj->global_list);
Chris Wilsona2165e32012-12-03 11:49:00 +00002024
Chris Wilson37e680a2012-06-07 15:38:42 +01002025 ops->put_pages(obj);
Chris Wilson05394f32010-11-08 19:18:58 +00002026 obj->pages = NULL;
Chris Wilson6c085a72012-08-20 11:40:46 +02002027
Chris Wilson55372522014-03-25 13:23:06 +00002028 i915_gem_object_invalidate(obj);
Chris Wilson6c085a72012-08-20 11:40:46 +02002029
2030 return 0;
2031}
2032
Chris Wilson21ab4e72014-09-09 11:16:08 +01002033unsigned long
2034i915_gem_shrink(struct drm_i915_private *dev_priv,
2035 long target, unsigned flags)
Chris Wilson6c085a72012-08-20 11:40:46 +02002036{
Chris Wilson60a53722014-10-03 10:29:51 +01002037 const struct {
2038 struct list_head *list;
2039 unsigned int bit;
2040 } phases[] = {
2041 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2042 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2043 { NULL, 0 },
2044 }, *phase;
Chris Wilsond9973b42013-10-04 10:33:00 +01002045 unsigned long count = 0;
Chris Wilson6c085a72012-08-20 11:40:46 +02002046
Chris Wilson57094f82013-09-04 10:45:50 +01002047 /*
Chris Wilsonc8725f32014-03-17 12:21:55 +00002048 * As we may completely rewrite the (un)bound list whilst unbinding
Chris Wilson57094f82013-09-04 10:45:50 +01002049 * (due to retiring requests) we have to strictly process only
2050 * one element of the list at the time, and recheck the list
2051 * on every iteration.
Chris Wilsonc8725f32014-03-17 12:21:55 +00002052 *
2053 * In particular, we must hold a reference whilst removing the
2054 * object as we may end up waiting for and/or retiring the objects.
2055 * This might release the final reference (held by the active list)
2056 * and result in the object being freed from under us. This is
2057 * similar to the precautions the eviction code must take whilst
2058 * removing objects.
2059 *
2060 * Also note that although these lists do not hold a reference to
2061 * the object we can safely grab one here: The final object
2062 * unreferencing and the bound_list are both protected by the
2063 * dev->struct_mutex and so we won't ever be able to observe an
2064 * object on the bound_list with a reference count equals 0.
Chris Wilson57094f82013-09-04 10:45:50 +01002065 */
Chris Wilson60a53722014-10-03 10:29:51 +01002066 for (phase = phases; phase->list; phase++) {
Chris Wilson21ab4e72014-09-09 11:16:08 +01002067 struct list_head still_in_list;
Chris Wilsonc8725f32014-03-17 12:21:55 +00002068
Chris Wilson60a53722014-10-03 10:29:51 +01002069 if ((flags & phase->bit) == 0)
2070 continue;
Ben Widawsky80dcfdb2013-07-31 17:00:01 -07002071
Chris Wilson21ab4e72014-09-09 11:16:08 +01002072 INIT_LIST_HEAD(&still_in_list);
Chris Wilson60a53722014-10-03 10:29:51 +01002073 while (count < target && !list_empty(phase->list)) {
Chris Wilson21ab4e72014-09-09 11:16:08 +01002074 struct drm_i915_gem_object *obj;
2075 struct i915_vma *vma, *v;
Chris Wilson57094f82013-09-04 10:45:50 +01002076
Chris Wilson60a53722014-10-03 10:29:51 +01002077 obj = list_first_entry(phase->list,
Chris Wilson21ab4e72014-09-09 11:16:08 +01002078 typeof(*obj), global_list);
2079 list_move_tail(&obj->global_list, &still_in_list);
Ben Widawsky80dcfdb2013-07-31 17:00:01 -07002080
Chris Wilson60a53722014-10-03 10:29:51 +01002081 if (flags & I915_SHRINK_PURGEABLE &&
2082 !i915_gem_object_is_purgeable(obj))
Chris Wilson21ab4e72014-09-09 11:16:08 +01002083 continue;
Chris Wilson57094f82013-09-04 10:45:50 +01002084
Chris Wilson21ab4e72014-09-09 11:16:08 +01002085 drm_gem_object_reference(&obj->base);
Ben Widawsky80dcfdb2013-07-31 17:00:01 -07002086
Chris Wilson60a53722014-10-03 10:29:51 +01002087 /* For the unbound phase, this should be a no-op! */
2088 list_for_each_entry_safe(vma, v,
2089 &obj->vma_list, vma_link)
Chris Wilson21ab4e72014-09-09 11:16:08 +01002090 if (i915_vma_unbind(vma))
2091 break;
Chris Wilson57094f82013-09-04 10:45:50 +01002092
Chris Wilson21ab4e72014-09-09 11:16:08 +01002093 if (i915_gem_object_put_pages(obj) == 0)
2094 count += obj->base.size >> PAGE_SHIFT;
2095
2096 drm_gem_object_unreference(&obj->base);
2097 }
Chris Wilson60a53722014-10-03 10:29:51 +01002098 list_splice(&still_in_list, phase->list);
Chris Wilson6c085a72012-08-20 11:40:46 +02002099 }
2100
2101 return count;
2102}
2103
Chris Wilsond9973b42013-10-04 10:33:00 +01002104static unsigned long
Chris Wilson6c085a72012-08-20 11:40:46 +02002105i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2106{
Chris Wilson6c085a72012-08-20 11:40:46 +02002107 i915_gem_evict_everything(dev_priv->dev);
Chris Wilson21ab4e72014-09-09 11:16:08 +01002108 return i915_gem_shrink(dev_priv, LONG_MAX,
2109 I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
Daniel Vetter225067e2012-08-20 10:23:20 +02002110}
2111
Chris Wilson37e680a2012-06-07 15:38:42 +01002112static int
Chris Wilson6c085a72012-08-20 11:40:46 +02002113i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07002114{
Chris Wilson6c085a72012-08-20 11:40:46 +02002115 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07002116 int page_count, i;
2117 struct address_space *mapping;
Chris Wilson9da3da62012-06-01 15:20:22 +01002118 struct sg_table *st;
2119 struct scatterlist *sg;
Imre Deak90797e62013-02-18 19:28:03 +02002120 struct sg_page_iter sg_iter;
Eric Anholt673a3942008-07-30 12:06:12 -07002121 struct page *page;
Imre Deak90797e62013-02-18 19:28:03 +02002122 unsigned long last_pfn = 0; /* suppress gcc warning */
Chris Wilson6c085a72012-08-20 11:40:46 +02002123 gfp_t gfp;
Eric Anholt673a3942008-07-30 12:06:12 -07002124
Chris Wilson6c085a72012-08-20 11:40:46 +02002125 /* Assert that the object is not currently in any GPU domain. As it
2126 * wasn't in the GTT, there shouldn't be any way it could have been in
2127 * a GPU cache
2128 */
2129 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2130 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2131
Chris Wilson9da3da62012-06-01 15:20:22 +01002132 st = kmalloc(sizeof(*st), GFP_KERNEL);
2133 if (st == NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002134 return -ENOMEM;
2135
Chris Wilson9da3da62012-06-01 15:20:22 +01002136 page_count = obj->base.size / PAGE_SIZE;
2137 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
Chris Wilson9da3da62012-06-01 15:20:22 +01002138 kfree(st);
2139 return -ENOMEM;
2140 }
2141
2142 /* Get the list of pages out of our struct file. They'll be pinned
2143 * at this point until we release them.
2144 *
2145 * Fail silently without starting the shrinker
2146 */
Al Viro496ad9a2013-01-23 17:07:38 -05002147 mapping = file_inode(obj->base.filp)->i_mapping;
Chris Wilson6c085a72012-08-20 11:40:46 +02002148 gfp = mapping_gfp_mask(mapping);
Linus Torvaldscaf49192012-12-10 10:51:16 -08002149 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
Chris Wilson6c085a72012-08-20 11:40:46 +02002150 gfp &= ~(__GFP_IO | __GFP_WAIT);
Imre Deak90797e62013-02-18 19:28:03 +02002151 sg = st->sgl;
2152 st->nents = 0;
2153 for (i = 0; i < page_count; i++) {
Chris Wilson6c085a72012-08-20 11:40:46 +02002154 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2155 if (IS_ERR(page)) {
Chris Wilson21ab4e72014-09-09 11:16:08 +01002156 i915_gem_shrink(dev_priv,
2157 page_count,
2158 I915_SHRINK_BOUND |
2159 I915_SHRINK_UNBOUND |
2160 I915_SHRINK_PURGEABLE);
Chris Wilson6c085a72012-08-20 11:40:46 +02002161 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2162 }
2163 if (IS_ERR(page)) {
2164 /* We've tried hard to allocate the memory by reaping
2165 * our own buffer, now let the real VM do its job and
2166 * go down in flames if truly OOM.
2167 */
Chris Wilson6c085a72012-08-20 11:40:46 +02002168 i915_gem_shrink_all(dev_priv);
David Herrmannf461d1b2014-05-25 14:34:10 +02002169 page = shmem_read_mapping_page(mapping, i);
Chris Wilson6c085a72012-08-20 11:40:46 +02002170 if (IS_ERR(page))
2171 goto err_pages;
Chris Wilson6c085a72012-08-20 11:40:46 +02002172 }
Konrad Rzeszutek Wilk426729d2013-06-24 11:47:48 -04002173#ifdef CONFIG_SWIOTLB
2174 if (swiotlb_nr_tbl()) {
2175 st->nents++;
2176 sg_set_page(sg, page, PAGE_SIZE, 0);
2177 sg = sg_next(sg);
2178 continue;
2179 }
2180#endif
Imre Deak90797e62013-02-18 19:28:03 +02002181 if (!i || page_to_pfn(page) != last_pfn + 1) {
2182 if (i)
2183 sg = sg_next(sg);
2184 st->nents++;
2185 sg_set_page(sg, page, PAGE_SIZE, 0);
2186 } else {
2187 sg->length += PAGE_SIZE;
2188 }
2189 last_pfn = page_to_pfn(page);
Daniel Vetter3bbbe702013-10-07 17:15:45 -03002190
2191 /* Check that the i965g/gm workaround works. */
2192 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
Eric Anholt673a3942008-07-30 12:06:12 -07002193 }
Konrad Rzeszutek Wilk426729d2013-06-24 11:47:48 -04002194#ifdef CONFIG_SWIOTLB
2195 if (!swiotlb_nr_tbl())
2196#endif
2197 sg_mark_end(sg);
Chris Wilson74ce6b62012-10-19 15:51:06 +01002198 obj->pages = st;
2199
Eric Anholt673a3942008-07-30 12:06:12 -07002200 if (i915_gem_object_needs_bit17_swizzle(obj))
2201 i915_gem_object_do_bit_17_swizzle(obj);
2202
Daniel Vetter656bfa32014-11-20 09:26:30 +01002203 if (obj->tiling_mode != I915_TILING_NONE &&
2204 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2205 i915_gem_object_pin_pages(obj);
2206
Eric Anholt673a3942008-07-30 12:06:12 -07002207 return 0;
2208
2209err_pages:
Imre Deak90797e62013-02-18 19:28:03 +02002210 sg_mark_end(sg);
2211 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
Imre Deak2db76d72013-03-26 15:14:18 +02002212 page_cache_release(sg_page_iter_page(&sg_iter));
Chris Wilson9da3da62012-06-01 15:20:22 +01002213 sg_free_table(st);
2214 kfree(st);
Chris Wilson0820baf2014-03-25 13:23:03 +00002215
2216 /* shmemfs first checks if there is enough memory to allocate the page
2217 * and reports ENOSPC should there be insufficient, along with the usual
2218 * ENOMEM for a genuine allocation failure.
2219 *
2220 * We use ENOSPC in our driver to mean that we have run out of aperture
2221 * space and so want to translate the error from shmemfs back to our
2222 * usual understanding of ENOMEM.
2223 */
2224 if (PTR_ERR(page) == -ENOSPC)
2225 return -ENOMEM;
2226 else
2227 return PTR_ERR(page);
Eric Anholt673a3942008-07-30 12:06:12 -07002228}
2229
Chris Wilson37e680a2012-06-07 15:38:42 +01002230/* Ensure that the associated pages are gathered from the backing storage
2231 * and pinned into our object. i915_gem_object_get_pages() may be called
2232 * multiple times before they are released by a single call to
2233 * i915_gem_object_put_pages() - once the pages are no longer referenced
2234 * either as a result of memory pressure (reaping pages under the shrinker)
2235 * or as the object is itself released.
2236 */
2237int
2238i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2239{
2240 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241 const struct drm_i915_gem_object_ops *ops = obj->ops;
2242 int ret;
2243
Chris Wilson2f745ad2012-09-04 21:02:58 +01002244 if (obj->pages)
Chris Wilson37e680a2012-06-07 15:38:42 +01002245 return 0;
2246
Chris Wilson43e28f02013-01-08 10:53:09 +00002247 if (obj->madv != I915_MADV_WILLNEED) {
Chris Wilsonbd9b6a42014-02-10 09:03:50 +00002248 DRM_DEBUG("Attempting to obtain a purgeable object\n");
Chris Wilson8c99e572014-01-31 11:34:58 +00002249 return -EFAULT;
Chris Wilson43e28f02013-01-08 10:53:09 +00002250 }
2251
Chris Wilsona5570172012-09-04 21:02:54 +01002252 BUG_ON(obj->pages_pin_count);
2253
Chris Wilson37e680a2012-06-07 15:38:42 +01002254 ret = ops->get_pages(obj);
2255 if (ret)
2256 return ret;
2257
Ben Widawsky35c20a62013-05-31 11:28:48 -07002258 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
Chris Wilson37e680a2012-06-07 15:38:42 +01002259 return 0;
Eric Anholt673a3942008-07-30 12:06:12 -07002260}
2261
Ben Widawskye2d05a82013-09-24 09:57:58 -07002262static void
Chris Wilson05394f32010-11-08 19:18:58 +00002263i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002264 struct intel_engine_cs *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07002265{
John Harrison41c52412014-11-24 18:49:43 +00002266 struct drm_i915_gem_request *req;
2267 struct intel_engine_cs *old_ring;
Daniel Vetter617dbe22010-02-11 22:16:02 +01002268
Zou Nan hai852835f2010-05-21 09:08:56 +08002269 BUG_ON(ring == NULL);
John Harrison41c52412014-11-24 18:49:43 +00002270
2271 req = intel_ring_get_request(ring);
2272 old_ring = i915_gem_request_get_ring(obj->last_read_req);
2273
2274 if (old_ring != ring && obj->last_write_req) {
John Harrison97b2a6a2014-11-24 18:49:26 +00002275 /* Keep the request relative to the current ring */
2276 i915_gem_request_assign(&obj->last_write_req, req);
Chris Wilson02978ff2013-07-09 09:22:39 +01002277 }
Eric Anholt673a3942008-07-30 12:06:12 -07002278
2279 /* Add a reference if we're newly entering the active list. */
Chris Wilson05394f32010-11-08 19:18:58 +00002280 if (!obj->active) {
2281 drm_gem_object_reference(&obj->base);
2282 obj->active = 1;
Eric Anholt673a3942008-07-30 12:06:12 -07002283 }
Daniel Vettere35a41d2010-02-11 22:13:59 +01002284
Chris Wilson05394f32010-11-08 19:18:58 +00002285 list_move_tail(&obj->ring_list, &ring->active_list);
Chris Wilsoncaea7472010-11-12 13:53:37 +00002286
John Harrison97b2a6a2014-11-24 18:49:26 +00002287 i915_gem_request_assign(&obj->last_read_req, req);
Chris Wilsoncaea7472010-11-12 13:53:37 +00002288}
2289
Ben Widawskye2d05a82013-09-24 09:57:58 -07002290void i915_vma_move_to_active(struct i915_vma *vma,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002291 struct intel_engine_cs *ring)
Ben Widawskye2d05a82013-09-24 09:57:58 -07002292{
2293 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2294 return i915_gem_object_move_to_active(vma->obj, ring);
2295}
2296
Chris Wilsoncaea7472010-11-12 13:53:37 +00002297static void
Chris Wilsoncaea7472010-11-12 13:53:37 +00002298i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2299{
Ben Widawskyca191b12013-07-31 17:00:14 -07002300 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Ben Widawskyfeb822c2013-12-06 14:10:51 -08002301 struct i915_address_space *vm;
2302 struct i915_vma *vma;
Chris Wilsoncaea7472010-11-12 13:53:37 +00002303
Chris Wilson65ce3022012-07-20 12:41:02 +01002304 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
Chris Wilsoncaea7472010-11-12 13:53:37 +00002305 BUG_ON(!obj->active);
Chris Wilson65ce3022012-07-20 12:41:02 +01002306
Ben Widawskyfeb822c2013-12-06 14:10:51 -08002307 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2308 vma = i915_gem_obj_to_vma(obj, vm);
2309 if (vma && !list_empty(&vma->mm_list))
2310 list_move_tail(&vma->mm_list, &vm->inactive_list);
2311 }
Chris Wilsoncaea7472010-11-12 13:53:37 +00002312
Daniel Vetterf99d7062014-06-19 16:01:59 +02002313 intel_fb_obj_flush(obj, true);
2314
Chris Wilson65ce3022012-07-20 12:41:02 +01002315 list_del_init(&obj->ring_list);
Chris Wilsoncaea7472010-11-12 13:53:37 +00002316
John Harrison97b2a6a2014-11-24 18:49:26 +00002317 i915_gem_request_assign(&obj->last_read_req, NULL);
2318 i915_gem_request_assign(&obj->last_write_req, NULL);
Chris Wilson65ce3022012-07-20 12:41:02 +01002319 obj->base.write_domain = 0;
2320
John Harrison97b2a6a2014-11-24 18:49:26 +00002321 i915_gem_request_assign(&obj->last_fenced_req, NULL);
Chris Wilsoncaea7472010-11-12 13:53:37 +00002322
2323 obj->active = 0;
2324 drm_gem_object_unreference(&obj->base);
2325
2326 WARN_ON(i915_verify_lists(dev));
Eric Anholtce44b0e2008-11-06 16:00:31 -08002327}
Eric Anholt673a3942008-07-30 12:06:12 -07002328
Chris Wilsonc8725f32014-03-17 12:21:55 +00002329static void
2330i915_gem_object_retire(struct drm_i915_gem_object *obj)
2331{
John Harrison41c52412014-11-24 18:49:43 +00002332 if (obj->last_read_req == NULL)
Chris Wilsonc8725f32014-03-17 12:21:55 +00002333 return;
2334
John Harrison1b5a4332014-11-24 18:49:42 +00002335 if (i915_gem_request_completed(obj->last_read_req, true))
Chris Wilsonc8725f32014-03-17 12:21:55 +00002336 i915_gem_object_move_to_inactive(obj);
2337}
2338
Chris Wilson9d7730912012-11-27 16:22:52 +00002339static int
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002340i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
Daniel Vetter53d227f2012-01-25 16:32:49 +01002341{
Chris Wilson9d7730912012-11-27 16:22:52 +00002342 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002343 struct intel_engine_cs *ring;
Chris Wilson9d7730912012-11-27 16:22:52 +00002344 int ret, i, j;
Daniel Vetter53d227f2012-01-25 16:32:49 +01002345
Chris Wilson107f27a52012-12-10 13:56:17 +02002346 /* Carefully retire all requests without writing to the rings */
Chris Wilson9d7730912012-11-27 16:22:52 +00002347 for_each_ring(ring, dev_priv, i) {
Chris Wilson107f27a52012-12-10 13:56:17 +02002348 ret = intel_ring_idle(ring);
2349 if (ret)
2350 return ret;
Chris Wilson9d7730912012-11-27 16:22:52 +00002351 }
Chris Wilson9d7730912012-11-27 16:22:52 +00002352 i915_gem_retire_requests(dev);
Chris Wilson107f27a52012-12-10 13:56:17 +02002353
2354 /* Finally reset hw state */
Chris Wilson9d7730912012-11-27 16:22:52 +00002355 for_each_ring(ring, dev_priv, i) {
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002356 intel_ring_init_seqno(ring, seqno);
Mika Kuoppala498d2ac2012-12-04 15:12:04 +02002357
Ben Widawskyebc348b2014-04-29 14:52:28 -07002358 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2359 ring->semaphore.sync_seqno[j] = 0;
Chris Wilson9d7730912012-11-27 16:22:52 +00002360 }
2361
2362 return 0;
Daniel Vetter53d227f2012-01-25 16:32:49 +01002363}
2364
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002365int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2366{
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 int ret;
2369
2370 if (seqno == 0)
2371 return -EINVAL;
2372
2373 /* HWS page needs to be set less than what we
2374 * will inject to ring
2375 */
2376 ret = i915_gem_init_seqno(dev, seqno - 1);
2377 if (ret)
2378 return ret;
2379
2380 /* Carefully set the last_seqno value so that wrap
2381 * detection still works
2382 */
2383 dev_priv->next_seqno = seqno;
2384 dev_priv->last_seqno = seqno - 1;
2385 if (dev_priv->last_seqno == 0)
2386 dev_priv->last_seqno--;
2387
2388 return 0;
2389}
2390
Chris Wilson9d7730912012-11-27 16:22:52 +00002391int
2392i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
Daniel Vetter53d227f2012-01-25 16:32:49 +01002393{
Chris Wilson9d7730912012-11-27 16:22:52 +00002394 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter53d227f2012-01-25 16:32:49 +01002395
Chris Wilson9d7730912012-11-27 16:22:52 +00002396 /* reserve 0 for non-seqno */
2397 if (dev_priv->next_seqno == 0) {
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002398 int ret = i915_gem_init_seqno(dev, 0);
Chris Wilson9d7730912012-11-27 16:22:52 +00002399 if (ret)
2400 return ret;
2401
2402 dev_priv->next_seqno = 1;
2403 }
2404
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02002405 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
Chris Wilson9d7730912012-11-27 16:22:52 +00002406 return 0;
Daniel Vetter53d227f2012-01-25 16:32:49 +01002407}
2408
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002409int __i915_add_request(struct intel_engine_cs *ring,
Mika Kuoppala0025c072013-06-12 12:35:30 +03002410 struct drm_file *file,
John Harrison9400ae52014-11-24 18:49:36 +00002411 struct drm_i915_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07002412{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03002413 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Chris Wilsonacb868d2012-09-26 13:47:30 +01002414 struct drm_i915_gem_request *request;
Oscar Mateo48e29f52014-07-24 17:04:29 +01002415 struct intel_ringbuffer *ringbuf;
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002416 u32 request_ring_position, request_start;
Chris Wilson3cce4692010-10-27 16:11:02 +01002417 int ret;
2418
John Harrison6259cea2014-11-24 18:49:29 +00002419 request = ring->outstanding_lazy_request;
Oscar Mateo48e29f52014-07-24 17:04:29 +01002420 if (WARN_ON(request == NULL))
2421 return -ENOMEM;
2422
2423 if (i915.enable_execlists) {
2424 struct intel_context *ctx = request->ctx;
2425 ringbuf = ctx->engine[ring->id].ringbuf;
2426 } else
2427 ringbuf = ring->buffer;
2428
2429 request_start = intel_ring_get_tail(ringbuf);
Daniel Vettercc889e02012-06-13 20:45:19 +02002430 /*
2431 * Emit any outstanding flushes - execbuf can fail to emit the flush
2432 * after having emitted the batchbuffer command. Hence we need to fix
2433 * things up similar to emitting the lazy request. The difference here
2434 * is that the flush _must_ happen before the next request, no matter
2435 * what.
2436 */
Oscar Mateo48e29f52014-07-24 17:04:29 +01002437 if (i915.enable_execlists) {
2438 ret = logical_ring_flush_all_caches(ringbuf);
2439 if (ret)
2440 return ret;
2441 } else {
2442 ret = intel_ring_flush_all_caches(ring);
2443 if (ret)
2444 return ret;
2445 }
Daniel Vettercc889e02012-06-13 20:45:19 +02002446
Chris Wilsona71d8d92012-02-15 11:25:36 +00002447 /* Record the position of the start of the request so that
2448 * should we detect the updated seqno part-way through the
2449 * GPU processing the request, we never over-estimate the
2450 * position of the head.
2451 */
Oscar Mateo48e29f52014-07-24 17:04:29 +01002452 request_ring_position = intel_ring_get_tail(ringbuf);
Chris Wilsona71d8d92012-02-15 11:25:36 +00002453
Oscar Mateo48e29f52014-07-24 17:04:29 +01002454 if (i915.enable_execlists) {
2455 ret = ring->emit_request(ringbuf);
2456 if (ret)
2457 return ret;
2458 } else {
2459 ret = ring->add_request(ring);
2460 if (ret)
2461 return ret;
2462 }
Eric Anholt673a3942008-07-30 12:06:12 -07002463
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002464 request->head = request_start;
Chris Wilsona71d8d92012-02-15 11:25:36 +00002465 request->tail = request_ring_position;
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002466
2467 /* Whilst this request exists, batch_obj will be on the
2468 * active_list, and so will hold the active reference. Only when this
2469 * request is retired will the the batch_obj be moved onto the
2470 * inactive_list and lose its active reference. Hence we do not need
2471 * to explicitly hold another reference here.
2472 */
Chris Wilson9a7e0c22013-08-26 19:50:54 -03002473 request->batch_obj = obj;
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002474
Oscar Mateo48e29f52014-07-24 17:04:29 +01002475 if (!i915.enable_execlists) {
2476 /* Hold a reference to the current context so that we can inspect
2477 * it later in case a hangcheck error event fires.
2478 */
2479 request->ctx = ring->last_context;
2480 if (request->ctx)
2481 i915_gem_context_reference(request->ctx);
2482 }
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002483
Eric Anholt673a3942008-07-30 12:06:12 -07002484 request->emitted_jiffies = jiffies;
Zou Nan hai852835f2010-05-21 09:08:56 +08002485 list_add_tail(&request->list, &ring->request_list);
Chris Wilson3bb73ab2012-07-20 12:40:59 +01002486 request->file_priv = NULL;
Zou Nan hai852835f2010-05-21 09:08:56 +08002487
Chris Wilsondb53a302011-02-03 11:57:46 +00002488 if (file) {
2489 struct drm_i915_file_private *file_priv = file->driver_priv;
2490
Chris Wilson1c255952010-09-26 11:03:27 +01002491 spin_lock(&file_priv->mm.lock);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002492 request->file_priv = file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00002493 list_add_tail(&request->client_list,
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002494 &file_priv->mm.request_list);
Chris Wilson1c255952010-09-26 11:03:27 +01002495 spin_unlock(&file_priv->mm.lock);
Eric Anholtb9624422009-06-03 07:27:35 +00002496 }
Eric Anholt673a3942008-07-30 12:06:12 -07002497
John Harrison74328ee2014-11-24 18:49:38 +00002498 trace_i915_gem_request_add(request);
John Harrison6259cea2014-11-24 18:49:29 +00002499 ring->outstanding_lazy_request = NULL;
Chris Wilsondb53a302011-02-03 11:57:46 +00002500
Daniel Vetter87255482014-11-19 20:36:48 +01002501 i915_queue_hangcheck(ring->dev);
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03002502
Daniel Vetter87255482014-11-19 20:36:48 +01002503 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2504 queue_delayed_work(dev_priv->wq,
2505 &dev_priv->mm.retire_work,
2506 round_jiffies_up_relative(HZ));
2507 intel_mark_busy(dev_priv->dev);
Daniel Vettercc889e02012-06-13 20:45:19 +02002508
Chris Wilson3cce4692010-10-27 16:11:02 +01002509 return 0;
Eric Anholt673a3942008-07-30 12:06:12 -07002510}
2511
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002512static inline void
2513i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
Eric Anholt673a3942008-07-30 12:06:12 -07002514{
Chris Wilson1c255952010-09-26 11:03:27 +01002515 struct drm_i915_file_private *file_priv = request->file_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07002516
Chris Wilson1c255952010-09-26 11:03:27 +01002517 if (!file_priv)
2518 return;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002519
Chris Wilson1c255952010-09-26 11:03:27 +01002520 spin_lock(&file_priv->mm.lock);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002521 list_del(&request->client_list);
2522 request->file_priv = NULL;
Chris Wilson1c255952010-09-26 11:03:27 +01002523 spin_unlock(&file_priv->mm.lock);
Eric Anholt673a3942008-07-30 12:06:12 -07002524}
2525
Mika Kuoppala939fd762014-01-30 19:04:44 +02002526static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
Oscar Mateo273497e2014-05-22 14:13:37 +01002527 const struct intel_context *ctx)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03002528{
Mika Kuoppala44e2c072014-01-30 16:01:15 +02002529 unsigned long elapsed;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03002530
Mika Kuoppala44e2c072014-01-30 16:01:15 +02002531 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2532
2533 if (ctx->hang_stats.banned)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03002534 return true;
2535
2536 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
Ville Syrjäläccc7bed2014-02-21 16:26:47 +02002537 if (!i915_gem_context_is_default(ctx)) {
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002538 DRM_DEBUG("context hanging too fast, banning!\n");
Ville Syrjäläccc7bed2014-02-21 16:26:47 +02002539 return true;
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02002540 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2541 if (i915_stop_ring_allow_warn(dev_priv))
2542 DRM_ERROR("gpu hanging too fast, banning!\n");
Ville Syrjäläccc7bed2014-02-21 16:26:47 +02002543 return true;
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002544 }
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03002545 }
2546
2547 return false;
2548}
2549
Mika Kuoppala939fd762014-01-30 19:04:44 +02002550static void i915_set_reset_status(struct drm_i915_private *dev_priv,
Oscar Mateo273497e2014-05-22 14:13:37 +01002551 struct intel_context *ctx,
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02002552 const bool guilty)
Mika Kuoppalaaa60c662013-06-12 15:13:20 +03002553{
Mika Kuoppala44e2c072014-01-30 16:01:15 +02002554 struct i915_ctx_hang_stats *hs;
2555
2556 if (WARN_ON(!ctx))
2557 return;
Mika Kuoppalaaa60c662013-06-12 15:13:20 +03002558
Mika Kuoppala44e2c072014-01-30 16:01:15 +02002559 hs = &ctx->hang_stats;
2560
2561 if (guilty) {
Mika Kuoppala939fd762014-01-30 19:04:44 +02002562 hs->banned = i915_context_is_banned(dev_priv, ctx);
Mika Kuoppala44e2c072014-01-30 16:01:15 +02002563 hs->batch_active++;
2564 hs->guilty_ts = get_seconds();
2565 } else {
2566 hs->batch_pending++;
Mika Kuoppalaaa60c662013-06-12 15:13:20 +03002567 }
2568}
2569
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002570static void i915_gem_free_request(struct drm_i915_gem_request *request)
2571{
2572 list_del(&request->list);
2573 i915_gem_request_remove_from_client(request);
2574
John Harrisonabfe2622014-11-24 18:49:24 +00002575 i915_gem_request_unreference(request);
2576}
2577
2578void i915_gem_request_free(struct kref *req_ref)
2579{
2580 struct drm_i915_gem_request *req = container_of(req_ref,
2581 typeof(*req), ref);
2582 struct intel_context *ctx = req->ctx;
2583
Thomas Daniel0794aed2014-11-25 10:39:25 +00002584 if (ctx) {
2585 if (i915.enable_execlists) {
John Harrisonabfe2622014-11-24 18:49:24 +00002586 struct intel_engine_cs *ring = req->ring;
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002587
Thomas Daniel0794aed2014-11-25 10:39:25 +00002588 if (ctx != ring->default_context)
2589 intel_lr_context_unpin(ring, ctx);
2590 }
John Harrisonabfe2622014-11-24 18:49:24 +00002591
Oscar Mateodcb4c122014-11-13 10:28:10 +00002592 i915_gem_context_unreference(ctx);
2593 }
John Harrisonabfe2622014-11-24 18:49:24 +00002594
2595 kfree(req);
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002596}
2597
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002598struct drm_i915_gem_request *
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002599i915_gem_find_active_request(struct intel_engine_cs *ring)
Chris Wilson9375e442010-09-19 12:21:28 +01002600{
Chris Wilson4db080f2013-12-04 11:37:09 +00002601 struct drm_i915_gem_request *request;
Mika Kuoppalaaa60c662013-06-12 15:13:20 +03002602
Chris Wilson4db080f2013-12-04 11:37:09 +00002603 list_for_each_entry(request, &ring->request_list, list) {
John Harrison1b5a4332014-11-24 18:49:42 +00002604 if (i915_gem_request_completed(request, false))
Chris Wilson4db080f2013-12-04 11:37:09 +00002605 continue;
Mika Kuoppalaaa60c662013-06-12 15:13:20 +03002606
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02002607 return request;
Chris Wilson4db080f2013-12-04 11:37:09 +00002608 }
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02002609
2610 return NULL;
2611}
2612
2613static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002614 struct intel_engine_cs *ring)
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02002615{
2616 struct drm_i915_gem_request *request;
2617 bool ring_hung;
2618
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002619 request = i915_gem_find_active_request(ring);
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02002620
2621 if (request == NULL)
2622 return;
2623
2624 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2625
Mika Kuoppala939fd762014-01-30 19:04:44 +02002626 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02002627
2628 list_for_each_entry_continue(request, &ring->request_list, list)
Mika Kuoppala939fd762014-01-30 19:04:44 +02002629 i915_set_reset_status(dev_priv, request->ctx, false);
Chris Wilson4db080f2013-12-04 11:37:09 +00002630}
2631
2632static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002633 struct intel_engine_cs *ring)
Chris Wilson4db080f2013-12-04 11:37:09 +00002634{
Chris Wilsondfaae392010-09-22 10:31:52 +01002635 while (!list_empty(&ring->active_list)) {
Chris Wilson05394f32010-11-08 19:18:58 +00002636 struct drm_i915_gem_object *obj;
Eric Anholt673a3942008-07-30 12:06:12 -07002637
Chris Wilson05394f32010-11-08 19:18:58 +00002638 obj = list_first_entry(&ring->active_list,
2639 struct drm_i915_gem_object,
2640 ring_list);
Eric Anholt673a3942008-07-30 12:06:12 -07002641
Chris Wilson05394f32010-11-08 19:18:58 +00002642 i915_gem_object_move_to_inactive(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002643 }
Ben Widawsky1d62bee2014-01-01 10:15:13 -08002644
2645 /*
Oscar Mateodcb4c122014-11-13 10:28:10 +00002646 * Clear the execlists queue up before freeing the requests, as those
2647 * are the ones that keep the context and ringbuffer backing objects
2648 * pinned in place.
2649 */
2650 while (!list_empty(&ring->execlist_queue)) {
2651 struct intel_ctx_submit_request *submit_req;
2652
2653 submit_req = list_first_entry(&ring->execlist_queue,
2654 struct intel_ctx_submit_request,
2655 execlist_link);
2656 list_del(&submit_req->execlist_link);
2657 intel_runtime_pm_put(dev_priv);
2658 i915_gem_context_unreference(submit_req->ctx);
2659 kfree(submit_req);
2660 }
2661
2662 /*
Ben Widawsky1d62bee2014-01-01 10:15:13 -08002663 * We must free the requests after all the corresponding objects have
2664 * been moved off active lists. Which is the same order as the normal
2665 * retire_requests function does. This is important if object hold
2666 * implicit references on things like e.g. ppgtt address spaces through
2667 * the request.
2668 */
2669 while (!list_empty(&ring->request_list)) {
2670 struct drm_i915_gem_request *request;
2671
2672 request = list_first_entry(&ring->request_list,
2673 struct drm_i915_gem_request,
2674 list);
2675
2676 i915_gem_free_request(request);
2677 }
Chris Wilsone3efda42014-04-09 09:19:41 +01002678
John Harrison6259cea2014-11-24 18:49:29 +00002679 /* This may not have been flushed before the reset, so clean it now */
2680 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
Eric Anholt673a3942008-07-30 12:06:12 -07002681}
2682
Chris Wilson19b2dbd2013-06-12 10:15:12 +01002683void i915_gem_restore_fences(struct drm_device *dev)
Chris Wilson312817a2010-11-22 11:50:11 +00002684{
2685 struct drm_i915_private *dev_priv = dev->dev_private;
2686 int i;
2687
Daniel Vetter4b9de732011-10-09 21:52:02 +02002688 for (i = 0; i < dev_priv->num_fence_regs; i++) {
Chris Wilson312817a2010-11-22 11:50:11 +00002689 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
Chris Wilson7d2cb392010-11-27 17:38:29 +00002690
Daniel Vetter94a335d2013-07-17 14:51:28 +02002691 /*
2692 * Commit delayed tiling changes if we have an object still
2693 * attached to the fence, otherwise just clear the fence.
2694 */
2695 if (reg->obj) {
2696 i915_gem_object_update_fence(reg->obj, reg,
2697 reg->obj->tiling_mode);
2698 } else {
2699 i915_gem_write_fence(dev, i, NULL);
2700 }
Chris Wilson312817a2010-11-22 11:50:11 +00002701 }
2702}
2703
Chris Wilson069efc12010-09-30 16:53:18 +01002704void i915_gem_reset(struct drm_device *dev)
Eric Anholt673a3942008-07-30 12:06:12 -07002705{
Chris Wilsondfaae392010-09-22 10:31:52 +01002706 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002707 struct intel_engine_cs *ring;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002708 int i;
Eric Anholt673a3942008-07-30 12:06:12 -07002709
Chris Wilson4db080f2013-12-04 11:37:09 +00002710 /*
2711 * Before we free the objects from the requests, we need to inspect
2712 * them for finding the guilty party. As the requests only borrow
2713 * their reference to the objects, the inspection must be done first.
2714 */
Chris Wilsonb4519512012-05-11 14:29:30 +01002715 for_each_ring(ring, dev_priv, i)
Chris Wilson4db080f2013-12-04 11:37:09 +00002716 i915_gem_reset_ring_status(dev_priv, ring);
2717
2718 for_each_ring(ring, dev_priv, i)
2719 i915_gem_reset_ring_cleanup(dev_priv, ring);
Chris Wilsondfaae392010-09-22 10:31:52 +01002720
Ben Widawskyacce9ff2013-12-06 14:11:03 -08002721 i915_gem_context_reset(dev);
2722
Chris Wilson19b2dbd2013-06-12 10:15:12 +01002723 i915_gem_restore_fences(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002724}
2725
2726/**
2727 * This function clears the request list as sequence numbers are passed.
2728 */
Chris Wilson1cf0ba12014-05-05 09:07:33 +01002729void
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002730i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07002731{
Chris Wilsondb53a302011-02-03 11:57:46 +00002732 if (list_empty(&ring->request_list))
Karsten Wiese6c0594a2009-02-23 15:07:57 +01002733 return;
2734
Chris Wilsondb53a302011-02-03 11:57:46 +00002735 WARN_ON(i915_verify_lists(ring->dev));
Eric Anholt673a3942008-07-30 12:06:12 -07002736
Chris Wilsone9103032014-01-07 11:45:14 +00002737 /* Move any buffers on the active list that are no longer referenced
2738 * by the ringbuffer to the flushing/inactive lists as appropriate,
2739 * before we free the context associated with the requests.
2740 */
2741 while (!list_empty(&ring->active_list)) {
2742 struct drm_i915_gem_object *obj;
2743
2744 obj = list_first_entry(&ring->active_list,
2745 struct drm_i915_gem_object,
2746 ring_list);
2747
John Harrison1b5a4332014-11-24 18:49:42 +00002748 if (!i915_gem_request_completed(obj->last_read_req, true))
Chris Wilsone9103032014-01-07 11:45:14 +00002749 break;
2750
2751 i915_gem_object_move_to_inactive(obj);
2752 }
2753
2754
Zou Nan hai852835f2010-05-21 09:08:56 +08002755 while (!list_empty(&ring->request_list)) {
Eric Anholt673a3942008-07-30 12:06:12 -07002756 struct drm_i915_gem_request *request;
Oscar Mateo48e29f52014-07-24 17:04:29 +01002757 struct intel_ringbuffer *ringbuf;
Eric Anholt673a3942008-07-30 12:06:12 -07002758
Zou Nan hai852835f2010-05-21 09:08:56 +08002759 request = list_first_entry(&ring->request_list,
Eric Anholt673a3942008-07-30 12:06:12 -07002760 struct drm_i915_gem_request,
2761 list);
Eric Anholt673a3942008-07-30 12:06:12 -07002762
John Harrison1b5a4332014-11-24 18:49:42 +00002763 if (!i915_gem_request_completed(request, true))
Eric Anholt673a3942008-07-30 12:06:12 -07002764 break;
Chris Wilsonb84d5f02010-09-18 01:38:04 +01002765
John Harrison74328ee2014-11-24 18:49:38 +00002766 trace_i915_gem_request_retire(request);
Oscar Mateo48e29f52014-07-24 17:04:29 +01002767
2768 /* This is one of the few common intersection points
2769 * between legacy ringbuffer submission and execlists:
2770 * we need to tell them apart in order to find the correct
2771 * ringbuffer to which the request belongs to.
2772 */
2773 if (i915.enable_execlists) {
2774 struct intel_context *ctx = request->ctx;
2775 ringbuf = ctx->engine[ring->id].ringbuf;
2776 } else
2777 ringbuf = ring->buffer;
2778
Chris Wilsona71d8d92012-02-15 11:25:36 +00002779 /* We know the GPU must have read the request to have
2780 * sent us the seqno + interrupt, so use the position
2781 * of tail of the request to update the last known position
2782 * of the GPU head.
2783 */
Oscar Mateo48e29f52014-07-24 17:04:29 +01002784 ringbuf->last_retired_head = request->tail;
Chris Wilsonb84d5f02010-09-18 01:38:04 +01002785
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002786 i915_gem_free_request(request);
Chris Wilsonb84d5f02010-09-18 01:38:04 +01002787 }
2788
John Harrison581c26e82014-11-24 18:49:39 +00002789 if (unlikely(ring->trace_irq_req &&
2790 i915_gem_request_completed(ring->trace_irq_req, true))) {
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002791 ring->irq_put(ring);
John Harrison581c26e82014-11-24 18:49:39 +00002792 i915_gem_request_assign(&ring->trace_irq_req, NULL);
Chris Wilson9d34e5d2009-09-24 05:26:06 +01002793 }
Chris Wilson23bc5982010-09-29 16:10:57 +01002794
Chris Wilsondb53a302011-02-03 11:57:46 +00002795 WARN_ON(i915_verify_lists(ring->dev));
Eric Anholt673a3942008-07-30 12:06:12 -07002796}
2797
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002798bool
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01002799i915_gem_retire_requests(struct drm_device *dev)
2800{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03002801 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002802 struct intel_engine_cs *ring;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002803 bool idle = true;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002804 int i;
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01002805
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002806 for_each_ring(ring, dev_priv, i) {
Chris Wilsonb4519512012-05-11 14:29:30 +01002807 i915_gem_retire_requests_ring(ring);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002808 idle &= list_empty(&ring->request_list);
Thomas Danielc86ee3a92014-11-13 10:27:05 +00002809 if (i915.enable_execlists) {
2810 unsigned long flags;
2811
2812 spin_lock_irqsave(&ring->execlist_lock, flags);
2813 idle &= list_empty(&ring->execlist_queue);
2814 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2815
2816 intel_execlists_retire_requests(ring);
2817 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002818 }
2819
2820 if (idle)
2821 mod_delayed_work(dev_priv->wq,
2822 &dev_priv->mm.idle_work,
2823 msecs_to_jiffies(100));
2824
2825 return idle;
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01002826}
2827
Daniel Vetter75ef9da2010-08-21 00:25:16 +02002828static void
Eric Anholt673a3942008-07-30 12:06:12 -07002829i915_gem_retire_work_handler(struct work_struct *work)
2830{
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002831 struct drm_i915_private *dev_priv =
2832 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2833 struct drm_device *dev = dev_priv->dev;
Chris Wilson0a587052011-01-09 21:05:44 +00002834 bool idle;
Eric Anholt673a3942008-07-30 12:06:12 -07002835
Chris Wilson891b48c2010-09-29 12:26:37 +01002836 /* Come back later if the device is busy... */
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002837 idle = false;
2838 if (mutex_trylock(&dev->struct_mutex)) {
2839 idle = i915_gem_retire_requests(dev);
2840 mutex_unlock(&dev->struct_mutex);
2841 }
2842 if (!idle)
Chris Wilsonbcb45082012-10-05 17:02:57 +01002843 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2844 round_jiffies_up_relative(HZ));
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002845}
Chris Wilson891b48c2010-09-29 12:26:37 +01002846
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002847static void
2848i915_gem_idle_work_handler(struct work_struct *work)
2849{
2850 struct drm_i915_private *dev_priv =
2851 container_of(work, typeof(*dev_priv), mm.idle_work.work);
Zou Nan haid1b851f2010-05-21 09:08:57 +08002852
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002853 intel_mark_idle(dev_priv->dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002854}
2855
Ben Widawsky5816d642012-04-11 11:18:19 -07002856/**
Daniel Vetter30dfebf2012-06-01 15:21:23 +02002857 * Ensures that an object will eventually get non-busy by flushing any required
2858 * write domains, emitting any outstanding lazy request and retiring and
2859 * completed requests.
2860 */
2861static int
2862i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2863{
John Harrison41c52412014-11-24 18:49:43 +00002864 struct intel_engine_cs *ring;
Daniel Vetter30dfebf2012-06-01 15:21:23 +02002865 int ret;
2866
2867 if (obj->active) {
John Harrison41c52412014-11-24 18:49:43 +00002868 ring = i915_gem_request_get_ring(obj->last_read_req);
2869
John Harrisonb6660d52014-11-24 18:49:30 +00002870 ret = i915_gem_check_olr(obj->last_read_req);
Daniel Vetter30dfebf2012-06-01 15:21:23 +02002871 if (ret)
2872 return ret;
2873
John Harrison41c52412014-11-24 18:49:43 +00002874 i915_gem_retire_requests_ring(ring);
Daniel Vetter30dfebf2012-06-01 15:21:23 +02002875 }
2876
2877 return 0;
2878}
2879
2880/**
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002881 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2882 * @DRM_IOCTL_ARGS: standard ioctl arguments
2883 *
2884 * Returns 0 if successful, else an error is returned with the remaining time in
2885 * the timeout parameter.
2886 * -ETIME: object is still busy after timeout
2887 * -ERESTARTSYS: signal interrupted the wait
2888 * -ENONENT: object doesn't exist
2889 * Also possible, but rare:
2890 * -EAGAIN: GPU wedged
2891 * -ENOMEM: damn
2892 * -ENODEV: Internal IRQ fail
2893 * -E?: The add request failed
2894 *
2895 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2896 * non-zero timeout parameter the wait ioctl will wait for the given number of
2897 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2898 * without holding struct_mutex the object may become re-busied before this
2899 * function completes. A similar but shorter * race condition exists in the busy
2900 * ioctl
2901 */
2902int
2903i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2904{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03002905 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002906 struct drm_i915_gem_wait *args = data;
2907 struct drm_i915_gem_object *obj;
John Harrisonff865882014-11-24 18:49:28 +00002908 struct drm_i915_gem_request *req;
Daniel Vetterf69061b2012-12-06 09:01:42 +01002909 unsigned reset_counter;
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002910 int ret = 0;
2911
Daniel Vetter11b5d512014-09-29 15:31:26 +02002912 if (args->flags != 0)
2913 return -EINVAL;
2914
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002915 ret = i915_mutex_lock_interruptible(dev);
2916 if (ret)
2917 return ret;
2918
2919 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2920 if (&obj->base == NULL) {
2921 mutex_unlock(&dev->struct_mutex);
2922 return -ENOENT;
2923 }
2924
Daniel Vetter30dfebf2012-06-01 15:21:23 +02002925 /* Need to make sure the object gets inactive eventually. */
2926 ret = i915_gem_object_flush_active(obj);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002927 if (ret)
2928 goto out;
2929
John Harrison97b2a6a2014-11-24 18:49:26 +00002930 if (!obj->active || !obj->last_read_req)
2931 goto out;
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002932
John Harrisonff865882014-11-24 18:49:28 +00002933 req = obj->last_read_req;
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002934
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002935 /* Do this after OLR check to make sure we make forward progress polling
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00002936 * on this IOCTL with a timeout <=0 (like busy ioctl)
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002937 */
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00002938 if (args->timeout_ns <= 0) {
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002939 ret = -ETIME;
2940 goto out;
2941 }
2942
2943 drm_gem_object_unreference(&obj->base);
Daniel Vetterf69061b2012-12-06 09:01:42 +01002944 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
John Harrisonff865882014-11-24 18:49:28 +00002945 i915_gem_request_reference(req);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002946 mutex_unlock(&dev->struct_mutex);
2947
John Harrison9c654812014-11-24 18:49:35 +00002948 ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns,
2949 file->driver_priv);
John Harrisonff865882014-11-24 18:49:28 +00002950 mutex_lock(&dev->struct_mutex);
2951 i915_gem_request_unreference(req);
2952 mutex_unlock(&dev->struct_mutex);
2953 return ret;
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002954
2955out:
2956 drm_gem_object_unreference(&obj->base);
2957 mutex_unlock(&dev->struct_mutex);
2958 return ret;
2959}
2960
2961/**
Ben Widawsky5816d642012-04-11 11:18:19 -07002962 * i915_gem_object_sync - sync an object to a ring.
2963 *
2964 * @obj: object which may be in use on another ring.
2965 * @to: ring we wish to use the object on. May be NULL.
2966 *
2967 * This code is meant to abstract object synchronization with the GPU.
2968 * Calling with NULL implies synchronizing the object with the CPU
2969 * rather than a particular GPU ring.
2970 *
2971 * Returns 0 if successful, else propagates up the lower layer error.
2972 */
Ben Widawsky2911a352012-04-05 14:47:36 -07002973int
2974i915_gem_object_sync(struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002975 struct intel_engine_cs *to)
Ben Widawsky2911a352012-04-05 14:47:36 -07002976{
John Harrison41c52412014-11-24 18:49:43 +00002977 struct intel_engine_cs *from;
Ben Widawsky2911a352012-04-05 14:47:36 -07002978 u32 seqno;
2979 int ret, idx;
2980
John Harrison41c52412014-11-24 18:49:43 +00002981 from = i915_gem_request_get_ring(obj->last_read_req);
2982
Ben Widawsky2911a352012-04-05 14:47:36 -07002983 if (from == NULL || to == from)
2984 return 0;
2985
Ben Widawsky5816d642012-04-11 11:18:19 -07002986 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
Chris Wilson0201f1e2012-07-20 12:41:01 +01002987 return i915_gem_object_wait_rendering(obj, false);
Ben Widawsky2911a352012-04-05 14:47:36 -07002988
2989 idx = intel_ring_sync_index(from, to);
2990
John Harrison97b2a6a2014-11-24 18:49:26 +00002991 seqno = i915_gem_request_get_seqno(obj->last_read_req);
Rodrigo Vividdd4dbc2014-06-30 09:51:11 -07002992 /* Optimization: Avoid semaphore sync when we are sure we already
2993 * waited for an object with higher seqno */
Ben Widawskyebc348b2014-04-29 14:52:28 -07002994 if (seqno <= from->semaphore.sync_seqno[idx])
Ben Widawsky2911a352012-04-05 14:47:36 -07002995 return 0;
2996
John Harrisonb6660d52014-11-24 18:49:30 +00002997 ret = i915_gem_check_olr(obj->last_read_req);
Ben Widawskyb4aca012012-04-25 20:50:12 -07002998 if (ret)
2999 return ret;
Ben Widawsky2911a352012-04-05 14:47:36 -07003000
John Harrison74328ee2014-11-24 18:49:38 +00003001 trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
Ben Widawskyebc348b2014-04-29 14:52:28 -07003002 ret = to->semaphore.sync_to(to, from, seqno);
Ben Widawskye3a5a222012-04-11 11:18:20 -07003003 if (!ret)
John Harrison97b2a6a2014-11-24 18:49:26 +00003004 /* We use last_read_req because sync_to()
Mika Kuoppala7b01e262012-11-28 17:18:45 +02003005 * might have just caused seqno wrap under
3006 * the radar.
3007 */
John Harrison97b2a6a2014-11-24 18:49:26 +00003008 from->semaphore.sync_seqno[idx] =
3009 i915_gem_request_get_seqno(obj->last_read_req);
Ben Widawsky2911a352012-04-05 14:47:36 -07003010
Ben Widawskye3a5a222012-04-11 11:18:20 -07003011 return ret;
Ben Widawsky2911a352012-04-05 14:47:36 -07003012}
3013
Chris Wilsonb5ffc9b2011-04-13 22:06:03 +01003014static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3015{
3016 u32 old_write_domain, old_read_domains;
3017
Chris Wilsonb5ffc9b2011-04-13 22:06:03 +01003018 /* Force a pagefault for domain tracking on next user access */
3019 i915_gem_release_mmap(obj);
3020
Keith Packardb97c3d92011-06-24 21:02:59 -07003021 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3022 return;
3023
Chris Wilson97c809fd2012-10-09 19:24:38 +01003024 /* Wait for any direct GTT access to complete */
3025 mb();
3026
Chris Wilsonb5ffc9b2011-04-13 22:06:03 +01003027 old_read_domains = obj->base.read_domains;
3028 old_write_domain = obj->base.write_domain;
3029
3030 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3031 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3032
3033 trace_i915_gem_object_change_domain(obj,
3034 old_read_domains,
3035 old_write_domain);
3036}
3037
Ben Widawsky07fe0b12013-07-31 17:00:10 -07003038int i915_vma_unbind(struct i915_vma *vma)
Eric Anholt673a3942008-07-30 12:06:12 -07003039{
Ben Widawsky07fe0b12013-07-31 17:00:10 -07003040 struct drm_i915_gem_object *obj = vma->obj;
Jani Nikula3e31c6c2014-03-31 14:27:16 +03003041 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilson43e28f02013-01-08 10:53:09 +00003042 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003043
Ben Widawsky07fe0b12013-07-31 17:00:10 -07003044 if (list_empty(&vma->vma_link))
Eric Anholt673a3942008-07-30 12:06:12 -07003045 return 0;
3046
Daniel Vetter0ff501c2013-08-29 19:50:31 +02003047 if (!drm_mm_node_allocated(&vma->node)) {
3048 i915_gem_vma_destroy(vma);
Daniel Vetter0ff501c2013-08-29 19:50:31 +02003049 return 0;
3050 }
Ben Widawsky433544b2013-08-13 18:09:06 -07003051
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08003052 if (vma->pin_count)
Chris Wilson31d8d652012-05-24 19:11:20 +01003053 return -EBUSY;
Eric Anholt673a3942008-07-30 12:06:12 -07003054
Chris Wilsonc4670ad2012-08-20 10:23:27 +01003055 BUG_ON(obj->pages == NULL);
3056
Chris Wilsona8198ee2011-04-13 22:04:09 +01003057 ret = i915_gem_object_finish_gpu(obj);
Chris Wilson1488fc02012-04-24 15:47:31 +01003058 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07003059 return ret;
Chris Wilson8dc17752010-07-23 23:18:51 +01003060 /* Continue on if we fail due to EIO, the GPU is hung so we
3061 * should be safe and we need to cleanup or else we might
3062 * cause memory corruption through use-after-free.
3063 */
Chris Wilsona8198ee2011-04-13 22:04:09 +01003064
Chris Wilson1d1ef21d2014-09-09 07:02:43 +01003065 /* Throw away the active reference before moving to the unbound list */
3066 i915_gem_object_retire(obj);
3067
Daniel Vetter8b1bc9b2014-02-14 14:06:07 +01003068 if (i915_is_ggtt(vma->vm)) {
3069 i915_gem_object_finish_gtt(obj);
Chris Wilsona8198ee2011-04-13 22:04:09 +01003070
Daniel Vetter8b1bc9b2014-02-14 14:06:07 +01003071 /* release the fence reg _after_ flushing */
3072 ret = i915_gem_object_put_fence(obj);
3073 if (ret)
3074 return ret;
3075 }
Daniel Vetter96b47b62009-12-15 17:50:00 +01003076
Ben Widawsky07fe0b12013-07-31 17:00:10 -07003077 trace_i915_vma_unbind(vma);
Chris Wilsondb53a302011-02-03 11:57:46 +00003078
Ben Widawsky6f65e292013-12-06 14:10:56 -08003079 vma->unbind_vma(vma);
3080
Chris Wilson64bf9302014-02-25 14:23:28 +00003081 list_del_init(&vma->mm_list);
Ben Widawsky5cacaac2013-07-31 17:00:13 -07003082 if (i915_is_ggtt(vma->vm))
Chris Wilsone6a84462014-08-11 12:00:12 +02003083 obj->map_and_fenceable = false;
Eric Anholt673a3942008-07-30 12:06:12 -07003084
Ben Widawsky2f633152013-07-17 12:19:03 -07003085 drm_mm_remove_node(&vma->node);
3086 i915_gem_vma_destroy(vma);
3087
3088 /* Since the unbound list is global, only move to that list if
Daniel Vetterb93dab62013-08-26 11:23:47 +02003089 * no more VMAs exist. */
Armin Reese9490edb2014-07-11 10:20:07 -07003090 if (list_empty(&obj->vma_list)) {
3091 i915_gem_gtt_finish_object(obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07003092 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
Armin Reese9490edb2014-07-11 10:20:07 -07003093 }
Eric Anholt673a3942008-07-30 12:06:12 -07003094
Chris Wilson70903c32013-12-04 09:59:09 +00003095 /* And finally now the object is completely decoupled from this vma,
3096 * we can drop its hold on the backing storage and allow it to be
3097 * reaped by the shrinker.
3098 */
3099 i915_gem_object_unpin_pages(obj);
3100
Chris Wilson88241782011-01-07 17:09:48 +00003101 return 0;
Chris Wilson54cf91d2010-11-25 18:00:26 +00003102}
3103
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07003104int i915_gpu_idle(struct drm_device *dev)
Daniel Vetter4df2faf2010-02-19 11:52:00 +01003105{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03003106 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01003107 struct intel_engine_cs *ring;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00003108 int ret, i;
Daniel Vetter4df2faf2010-02-19 11:52:00 +01003109
Daniel Vetter4df2faf2010-02-19 11:52:00 +01003110 /* Flush everything onto the inactive list. */
Chris Wilsonb4519512012-05-11 14:29:30 +01003111 for_each_ring(ring, dev_priv, i) {
Thomas Danielecdb5fd2014-08-20 16:29:24 +01003112 if (!i915.enable_execlists) {
3113 ret = i915_switch_context(ring, ring->default_context);
3114 if (ret)
3115 return ret;
3116 }
Ben Widawskyb6c74882012-08-14 14:35:14 -07003117
Chris Wilson3e960502012-11-27 16:22:54 +00003118 ret = intel_ring_idle(ring);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00003119 if (ret)
3120 return ret;
3121 }
Zou Nan haid1b851f2010-05-21 09:08:57 +08003122
Daniel Vetter8a1a49f2010-02-11 22:29:04 +01003123 return 0;
Daniel Vetter4df2faf2010-02-19 11:52:00 +01003124}
3125
Chris Wilson9ce079e2012-04-17 15:31:30 +01003126static void i965_write_fence_reg(struct drm_device *dev, int reg,
3127 struct drm_i915_gem_object *obj)
Jesse Barnesde151cf2008-11-12 10:03:55 -08003128{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03003129 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak56c844e2013-01-07 21:47:34 +02003130 int fence_reg;
3131 int fence_pitch_shift;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003132
Imre Deak56c844e2013-01-07 21:47:34 +02003133 if (INTEL_INFO(dev)->gen >= 6) {
3134 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3135 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3136 } else {
3137 fence_reg = FENCE_REG_965_0;
3138 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3139 }
3140
Chris Wilsond18b9612013-07-10 13:36:23 +01003141 fence_reg += reg * 8;
3142
3143 /* To w/a incoherency with non-atomic 64-bit register updates,
3144 * we split the 64-bit update into two 32-bit writes. In order
3145 * for a partial fence not to be evaluated between writes, we
3146 * precede the update with write to turn off the fence register,
3147 * and only enable the fence as the last step.
3148 *
3149 * For extra levels of paranoia, we make sure each step lands
3150 * before applying the next step.
3151 */
3152 I915_WRITE(fence_reg, 0);
3153 POSTING_READ(fence_reg);
3154
Chris Wilson9ce079e2012-04-17 15:31:30 +01003155 if (obj) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003156 u32 size = i915_gem_obj_ggtt_size(obj);
Chris Wilsond18b9612013-07-10 13:36:23 +01003157 uint64_t val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003158
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003159 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
Chris Wilson9ce079e2012-04-17 15:31:30 +01003160 0xfffff000) << 32;
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003161 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
Imre Deak56c844e2013-01-07 21:47:34 +02003162 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
Chris Wilson9ce079e2012-04-17 15:31:30 +01003163 if (obj->tiling_mode == I915_TILING_Y)
3164 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3165 val |= I965_FENCE_REG_VALID;
Daniel Vetterc6642782010-11-12 13:46:18 +00003166
Chris Wilsond18b9612013-07-10 13:36:23 +01003167 I915_WRITE(fence_reg + 4, val >> 32);
3168 POSTING_READ(fence_reg + 4);
3169
3170 I915_WRITE(fence_reg + 0, val);
3171 POSTING_READ(fence_reg);
3172 } else {
3173 I915_WRITE(fence_reg + 4, 0);
3174 POSTING_READ(fence_reg + 4);
3175 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08003176}
3177
Chris Wilson9ce079e2012-04-17 15:31:30 +01003178static void i915_write_fence_reg(struct drm_device *dev, int reg,
3179 struct drm_i915_gem_object *obj)
Jesse Barnesde151cf2008-11-12 10:03:55 -08003180{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03003181 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9ce079e2012-04-17 15:31:30 +01003182 u32 val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003183
Chris Wilson9ce079e2012-04-17 15:31:30 +01003184 if (obj) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003185 u32 size = i915_gem_obj_ggtt_size(obj);
Chris Wilson9ce079e2012-04-17 15:31:30 +01003186 int pitch_val;
3187 int tile_width;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003188
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003189 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
Chris Wilson9ce079e2012-04-17 15:31:30 +01003190 (size & -size) != size ||
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003191 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3192 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3193 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
Chris Wilson9ce079e2012-04-17 15:31:30 +01003194
3195 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3196 tile_width = 128;
3197 else
3198 tile_width = 512;
3199
3200 /* Note: pitch better be a power of two tile widths */
3201 pitch_val = obj->stride / tile_width;
3202 pitch_val = ffs(pitch_val) - 1;
3203
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003204 val = i915_gem_obj_ggtt_offset(obj);
Chris Wilson9ce079e2012-04-17 15:31:30 +01003205 if (obj->tiling_mode == I915_TILING_Y)
3206 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3207 val |= I915_FENCE_SIZE_BITS(size);
3208 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3209 val |= I830_FENCE_REG_VALID;
3210 } else
3211 val = 0;
3212
3213 if (reg < 8)
3214 reg = FENCE_REG_830_0 + reg * 4;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003215 else
Chris Wilson9ce079e2012-04-17 15:31:30 +01003216 reg = FENCE_REG_945_8 + (reg - 8) * 4;
Jesse Barnes0f973f22009-01-26 17:10:45 -08003217
Chris Wilson9ce079e2012-04-17 15:31:30 +01003218 I915_WRITE(reg, val);
3219 POSTING_READ(reg);
Jesse Barnesde151cf2008-11-12 10:03:55 -08003220}
3221
Chris Wilson9ce079e2012-04-17 15:31:30 +01003222static void i830_write_fence_reg(struct drm_device *dev, int reg,
3223 struct drm_i915_gem_object *obj)
Jesse Barnesde151cf2008-11-12 10:03:55 -08003224{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03003225 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003226 uint32_t val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003227
Chris Wilson9ce079e2012-04-17 15:31:30 +01003228 if (obj) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003229 u32 size = i915_gem_obj_ggtt_size(obj);
Chris Wilson9ce079e2012-04-17 15:31:30 +01003230 uint32_t pitch_val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003231
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003232 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
Chris Wilson9ce079e2012-04-17 15:31:30 +01003233 (size & -size) != size ||
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003234 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3235 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3236 i915_gem_obj_ggtt_offset(obj), size);
Eric Anholte76a16d2009-05-26 17:44:56 -07003237
Chris Wilson9ce079e2012-04-17 15:31:30 +01003238 pitch_val = obj->stride / 128;
3239 pitch_val = ffs(pitch_val) - 1;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003240
Ben Widawskyf343c5f2013-07-05 14:41:04 -07003241 val = i915_gem_obj_ggtt_offset(obj);
Chris Wilson9ce079e2012-04-17 15:31:30 +01003242 if (obj->tiling_mode == I915_TILING_Y)
3243 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3244 val |= I830_FENCE_SIZE_BITS(size);
3245 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3246 val |= I830_FENCE_REG_VALID;
3247 } else
3248 val = 0;
Daniel Vetterc6642782010-11-12 13:46:18 +00003249
Chris Wilson9ce079e2012-04-17 15:31:30 +01003250 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3251 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3252}
3253
Chris Wilsond0a57782012-10-09 19:24:37 +01003254inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3255{
3256 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3257}
3258
Chris Wilson9ce079e2012-04-17 15:31:30 +01003259static void i915_gem_write_fence(struct drm_device *dev, int reg,
3260 struct drm_i915_gem_object *obj)
3261{
Chris Wilsond0a57782012-10-09 19:24:37 +01003262 struct drm_i915_private *dev_priv = dev->dev_private;
3263
3264 /* Ensure that all CPU reads are completed before installing a fence
3265 * and all writes before removing the fence.
3266 */
3267 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3268 mb();
3269
Daniel Vetter94a335d2013-07-17 14:51:28 +02003270 WARN(obj && (!obj->stride || !obj->tiling_mode),
3271 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3272 obj->stride, obj->tiling_mode);
3273
Chris Wilson9ce079e2012-04-17 15:31:30 +01003274 switch (INTEL_INFO(dev)->gen) {
Damien Lespiau01209dd2013-02-13 15:27:25 +00003275 case 9:
Ben Widawsky5ab31332013-11-02 21:07:03 -07003276 case 8:
Chris Wilson9ce079e2012-04-17 15:31:30 +01003277 case 7:
Imre Deak56c844e2013-01-07 21:47:34 +02003278 case 6:
Chris Wilson9ce079e2012-04-17 15:31:30 +01003279 case 5:
3280 case 4: i965_write_fence_reg(dev, reg, obj); break;
3281 case 3: i915_write_fence_reg(dev, reg, obj); break;
3282 case 2: i830_write_fence_reg(dev, reg, obj); break;
Ben Widawsky7dbf9d62012-12-18 10:31:22 -08003283 default: BUG();
Chris Wilson9ce079e2012-04-17 15:31:30 +01003284 }
Chris Wilsond0a57782012-10-09 19:24:37 +01003285
3286 /* And similarly be paranoid that no direct access to this region
3287 * is reordered to before the fence is installed.
3288 */
3289 if (i915_gem_object_needs_mb(obj))
3290 mb();
Jesse Barnesde151cf2008-11-12 10:03:55 -08003291}
3292
Chris Wilson61050802012-04-17 15:31:31 +01003293static inline int fence_number(struct drm_i915_private *dev_priv,
3294 struct drm_i915_fence_reg *fence)
3295{
3296 return fence - dev_priv->fence_regs;
3297}
3298
3299static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3300 struct drm_i915_fence_reg *fence,
3301 bool enable)
3302{
Chris Wilson2dc8aae2013-05-22 17:08:06 +01003303 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilson46a0b632013-07-10 13:36:24 +01003304 int reg = fence_number(dev_priv, fence);
Chris Wilson61050802012-04-17 15:31:31 +01003305
Chris Wilson46a0b632013-07-10 13:36:24 +01003306 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
Chris Wilson61050802012-04-17 15:31:31 +01003307
3308 if (enable) {
Chris Wilson46a0b632013-07-10 13:36:24 +01003309 obj->fence_reg = reg;
Chris Wilson61050802012-04-17 15:31:31 +01003310 fence->obj = obj;
3311 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3312 } else {
3313 obj->fence_reg = I915_FENCE_REG_NONE;
3314 fence->obj = NULL;
3315 list_del_init(&fence->lru_list);
3316 }
Daniel Vetter94a335d2013-07-17 14:51:28 +02003317 obj->fence_dirty = false;
Chris Wilson61050802012-04-17 15:31:31 +01003318}
3319
Chris Wilsond9e86c02010-11-10 16:40:20 +00003320static int
Chris Wilsond0a57782012-10-09 19:24:37 +01003321i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
Chris Wilsond9e86c02010-11-10 16:40:20 +00003322{
John Harrison97b2a6a2014-11-24 18:49:26 +00003323 if (obj->last_fenced_req) {
Daniel Vettera4b3a572014-11-26 14:17:05 +01003324 int ret = i915_wait_request(obj->last_fenced_req);
Chris Wilson18991842012-04-17 15:31:29 +01003325 if (ret)
3326 return ret;
Chris Wilsond9e86c02010-11-10 16:40:20 +00003327
John Harrison97b2a6a2014-11-24 18:49:26 +00003328 i915_gem_request_assign(&obj->last_fenced_req, NULL);
Chris Wilsond9e86c02010-11-10 16:40:20 +00003329 }
3330
3331 return 0;
3332}
3333
3334int
3335i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3336{
Chris Wilson61050802012-04-17 15:31:31 +01003337 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsonf9c513e2013-03-26 11:29:27 +00003338 struct drm_i915_fence_reg *fence;
Chris Wilsond9e86c02010-11-10 16:40:20 +00003339 int ret;
3340
Chris Wilsond0a57782012-10-09 19:24:37 +01003341 ret = i915_gem_object_wait_fence(obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00003342 if (ret)
3343 return ret;
3344
Chris Wilson61050802012-04-17 15:31:31 +01003345 if (obj->fence_reg == I915_FENCE_REG_NONE)
3346 return 0;
Chris Wilson1690e1e2011-12-14 13:57:08 +01003347
Chris Wilsonf9c513e2013-03-26 11:29:27 +00003348 fence = &dev_priv->fence_regs[obj->fence_reg];
3349
Daniel Vetteraff10b302014-02-14 14:06:05 +01003350 if (WARN_ON(fence->pin_count))
3351 return -EBUSY;
3352
Chris Wilson61050802012-04-17 15:31:31 +01003353 i915_gem_object_fence_lost(obj);
Chris Wilsonf9c513e2013-03-26 11:29:27 +00003354 i915_gem_object_update_fence(obj, fence, false);
Chris Wilsond9e86c02010-11-10 16:40:20 +00003355
3356 return 0;
3357}
3358
3359static struct drm_i915_fence_reg *
Chris Wilsona360bb12012-04-17 15:31:25 +01003360i915_find_fence_reg(struct drm_device *dev)
Daniel Vetterae3db242010-02-19 11:51:58 +01003361{
Daniel Vetterae3db242010-02-19 11:51:58 +01003362 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8fe301a2012-04-17 15:31:28 +01003363 struct drm_i915_fence_reg *reg, *avail;
Chris Wilsond9e86c02010-11-10 16:40:20 +00003364 int i;
Daniel Vetterae3db242010-02-19 11:51:58 +01003365
3366 /* First try to find a free reg */
Chris Wilsond9e86c02010-11-10 16:40:20 +00003367 avail = NULL;
Daniel Vetterae3db242010-02-19 11:51:58 +01003368 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3369 reg = &dev_priv->fence_regs[i];
3370 if (!reg->obj)
Chris Wilsond9e86c02010-11-10 16:40:20 +00003371 return reg;
Daniel Vetterae3db242010-02-19 11:51:58 +01003372
Chris Wilson1690e1e2011-12-14 13:57:08 +01003373 if (!reg->pin_count)
Chris Wilsond9e86c02010-11-10 16:40:20 +00003374 avail = reg;
Daniel Vetterae3db242010-02-19 11:51:58 +01003375 }
3376
Chris Wilsond9e86c02010-11-10 16:40:20 +00003377 if (avail == NULL)
Chris Wilson5dce5b932014-01-20 10:17:36 +00003378 goto deadlock;
Daniel Vetterae3db242010-02-19 11:51:58 +01003379
3380 /* None available, try to steal one or wait for a user to finish */
Chris Wilsond9e86c02010-11-10 16:40:20 +00003381 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
Chris Wilson1690e1e2011-12-14 13:57:08 +01003382 if (reg->pin_count)
Daniel Vetterae3db242010-02-19 11:51:58 +01003383 continue;
3384
Chris Wilson8fe301a2012-04-17 15:31:28 +01003385 return reg;
Daniel Vetterae3db242010-02-19 11:51:58 +01003386 }
3387
Chris Wilson5dce5b932014-01-20 10:17:36 +00003388deadlock:
3389 /* Wait for completion of pending flips which consume fences */
3390 if (intel_has_pending_fb_unpin(dev))
3391 return ERR_PTR(-EAGAIN);
3392
3393 return ERR_PTR(-EDEADLK);
Daniel Vetterae3db242010-02-19 11:51:58 +01003394}
3395
Jesse Barnesde151cf2008-11-12 10:03:55 -08003396/**
Chris Wilson9a5a53b2012-03-22 15:10:00 +00003397 * i915_gem_object_get_fence - set up fencing for an object
Jesse Barnesde151cf2008-11-12 10:03:55 -08003398 * @obj: object to map through a fence reg
3399 *
3400 * When mapping objects through the GTT, userspace wants to be able to write
3401 * to them without having to worry about swizzling if the object is tiled.
Jesse Barnesde151cf2008-11-12 10:03:55 -08003402 * This function walks the fence regs looking for a free one for @obj,
3403 * stealing one if it can't find any.
3404 *
3405 * It then sets up the reg based on the object's properties: address, pitch
3406 * and tiling format.
Chris Wilson9a5a53b2012-03-22 15:10:00 +00003407 *
3408 * For an untiled surface, this removes any existing fence.
Jesse Barnesde151cf2008-11-12 10:03:55 -08003409 */
Chris Wilson8c4b8c32009-06-17 22:08:52 +01003410int
Chris Wilson06d98132012-04-17 15:31:24 +01003411i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
Jesse Barnesde151cf2008-11-12 10:03:55 -08003412{
Chris Wilson05394f32010-11-08 19:18:58 +00003413 struct drm_device *dev = obj->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003414 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson14415742012-04-17 15:31:33 +01003415 bool enable = obj->tiling_mode != I915_TILING_NONE;
Chris Wilsond9e86c02010-11-10 16:40:20 +00003416 struct drm_i915_fence_reg *reg;
Daniel Vetterae3db242010-02-19 11:51:58 +01003417 int ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003418
Chris Wilson14415742012-04-17 15:31:33 +01003419 /* Have we updated the tiling parameters upon the object and so
3420 * will need to serialise the write to the associated fence register?
3421 */
Chris Wilson5d82e3e2012-04-21 16:23:23 +01003422 if (obj->fence_dirty) {
Chris Wilsond0a57782012-10-09 19:24:37 +01003423 ret = i915_gem_object_wait_fence(obj);
Chris Wilson14415742012-04-17 15:31:33 +01003424 if (ret)
3425 return ret;
3426 }
Chris Wilson9a5a53b2012-03-22 15:10:00 +00003427
Chris Wilsond9e86c02010-11-10 16:40:20 +00003428 /* Just update our place in the LRU if our fence is getting reused. */
Chris Wilson05394f32010-11-08 19:18:58 +00003429 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3430 reg = &dev_priv->fence_regs[obj->fence_reg];
Chris Wilson5d82e3e2012-04-21 16:23:23 +01003431 if (!obj->fence_dirty) {
Chris Wilson14415742012-04-17 15:31:33 +01003432 list_move_tail(&reg->lru_list,
3433 &dev_priv->mm.fence_list);
3434 return 0;
3435 }
3436 } else if (enable) {
Chris Wilsone6a84462014-08-11 12:00:12 +02003437 if (WARN_ON(!obj->map_and_fenceable))
3438 return -EINVAL;
3439
Chris Wilson14415742012-04-17 15:31:33 +01003440 reg = i915_find_fence_reg(dev);
Chris Wilson5dce5b932014-01-20 10:17:36 +00003441 if (IS_ERR(reg))
3442 return PTR_ERR(reg);
Chris Wilsond9e86c02010-11-10 16:40:20 +00003443
Chris Wilson14415742012-04-17 15:31:33 +01003444 if (reg->obj) {
3445 struct drm_i915_gem_object *old = reg->obj;
3446
Chris Wilsond0a57782012-10-09 19:24:37 +01003447 ret = i915_gem_object_wait_fence(old);
Chris Wilson29c5a582011-03-17 15:23:22 +00003448 if (ret)
3449 return ret;
3450
Chris Wilson14415742012-04-17 15:31:33 +01003451 i915_gem_object_fence_lost(old);
Chris Wilson29c5a582011-03-17 15:23:22 +00003452 }
Chris Wilson14415742012-04-17 15:31:33 +01003453 } else
Eric Anholta09ba7f2009-08-29 12:49:51 -07003454 return 0;
Eric Anholta09ba7f2009-08-29 12:49:51 -07003455
Chris Wilson14415742012-04-17 15:31:33 +01003456 i915_gem_object_update_fence(obj, reg, enable);
Chris Wilson14415742012-04-17 15:31:33 +01003457
Chris Wilson9ce079e2012-04-17 15:31:30 +01003458 return 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003459}
3460
Chris Wilson4144f9b2014-09-11 08:43:48 +01003461static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
Chris Wilson42d6ab42012-07-26 11:49:32 +01003462 unsigned long cache_level)
3463{
Chris Wilson4144f9b2014-09-11 08:43:48 +01003464 struct drm_mm_node *gtt_space = &vma->node;
Chris Wilson42d6ab42012-07-26 11:49:32 +01003465 struct drm_mm_node *other;
3466
Chris Wilson4144f9b2014-09-11 08:43:48 +01003467 /*
3468 * On some machines we have to be careful when putting differing types
3469 * of snoopable memory together to avoid the prefetcher crossing memory
3470 * domains and dying. During vm initialisation, we decide whether or not
3471 * these constraints apply and set the drm_mm.color_adjust
3472 * appropriately.
Chris Wilson42d6ab42012-07-26 11:49:32 +01003473 */
Chris Wilson4144f9b2014-09-11 08:43:48 +01003474 if (vma->vm->mm.color_adjust == NULL)
Chris Wilson42d6ab42012-07-26 11:49:32 +01003475 return true;
3476
Ben Widawskyc6cfb322013-07-05 14:41:06 -07003477 if (!drm_mm_node_allocated(gtt_space))
Chris Wilson42d6ab42012-07-26 11:49:32 +01003478 return true;
3479
3480 if (list_empty(&gtt_space->node_list))
3481 return true;
3482
3483 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3484 if (other->allocated && !other->hole_follows && other->color != cache_level)
3485 return false;
3486
3487 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3488 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3489 return false;
3490
3491 return true;
3492}
3493
Jesse Barnesde151cf2008-11-12 10:03:55 -08003494/**
Eric Anholt673a3942008-07-30 12:06:12 -07003495 * Finds free space in the GTT aperture and binds the object there.
3496 */
Daniel Vetter262de142014-02-14 14:01:20 +01003497static struct i915_vma *
Ben Widawsky07fe0b12013-07-31 17:00:10 -07003498i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3499 struct i915_address_space *vm,
3500 unsigned alignment,
Chris Wilsond23db882014-05-23 08:48:08 +02003501 uint64_t flags)
Eric Anholt673a3942008-07-30 12:06:12 -07003502{
Chris Wilson05394f32010-11-08 19:18:58 +00003503 struct drm_device *dev = obj->base.dev;
Jani Nikula3e31c6c2014-03-31 14:27:16 +03003504 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter5e783302010-11-14 22:32:36 +01003505 u32 size, fence_size, fence_alignment, unfenced_alignment;
Chris Wilsond23db882014-05-23 08:48:08 +02003506 unsigned long start =
3507 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3508 unsigned long end =
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003509 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
Ben Widawsky2f633152013-07-17 12:19:03 -07003510 struct i915_vma *vma;
Chris Wilson07f73f62009-09-14 16:50:30 +01003511 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003512
Chris Wilsone28f8712011-07-18 13:11:49 -07003513 fence_size = i915_gem_get_gtt_size(dev,
3514 obj->base.size,
3515 obj->tiling_mode);
3516 fence_alignment = i915_gem_get_gtt_alignment(dev,
3517 obj->base.size,
Imre Deakd8651102013-01-07 21:47:33 +02003518 obj->tiling_mode, true);
Chris Wilsone28f8712011-07-18 13:11:49 -07003519 unfenced_alignment =
Imre Deakd8651102013-01-07 21:47:33 +02003520 i915_gem_get_gtt_alignment(dev,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003521 obj->base.size,
3522 obj->tiling_mode, false);
Chris Wilsona00b10c2010-09-24 21:15:47 +01003523
Eric Anholt673a3942008-07-30 12:06:12 -07003524 if (alignment == 0)
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003525 alignment = flags & PIN_MAPPABLE ? fence_alignment :
Daniel Vetter5e783302010-11-14 22:32:36 +01003526 unfenced_alignment;
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003527 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
Chris Wilsonbd9b6a42014-02-10 09:03:50 +00003528 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
Daniel Vetter262de142014-02-14 14:01:20 +01003529 return ERR_PTR(-EINVAL);
Eric Anholt673a3942008-07-30 12:06:12 -07003530 }
3531
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003532 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
Chris Wilsona00b10c2010-09-24 21:15:47 +01003533
Chris Wilson654fc602010-05-27 13:18:21 +01003534 /* If the object is bigger than the entire aperture, reject it early
3535 * before evicting everything in a vain attempt to find space.
3536 */
Chris Wilsond23db882014-05-23 08:48:08 +02003537 if (obj->base.size > end) {
3538 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
Chris Wilsona36689c2013-05-21 16:58:49 +01003539 obj->base.size,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003540 flags & PIN_MAPPABLE ? "mappable" : "total",
Chris Wilsond23db882014-05-23 08:48:08 +02003541 end);
Daniel Vetter262de142014-02-14 14:01:20 +01003542 return ERR_PTR(-E2BIG);
Chris Wilson654fc602010-05-27 13:18:21 +01003543 }
3544
Chris Wilson37e680a2012-06-07 15:38:42 +01003545 ret = i915_gem_object_get_pages(obj);
Chris Wilson6c085a72012-08-20 11:40:46 +02003546 if (ret)
Daniel Vetter262de142014-02-14 14:01:20 +01003547 return ERR_PTR(ret);
Chris Wilson6c085a72012-08-20 11:40:46 +02003548
Chris Wilsonfbdda6f2012-11-20 10:45:16 +00003549 i915_gem_object_pin_pages(obj);
3550
Ben Widawskyaccfef22013-08-14 11:38:35 +02003551 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
Daniel Vetter262de142014-02-14 14:01:20 +01003552 if (IS_ERR(vma))
Daniel Vetterbc6bc152013-07-22 12:12:38 +02003553 goto err_unpin;
Ben Widawsky2f633152013-07-17 12:19:03 -07003554
Ben Widawsky0a9ae0d2013-05-25 12:26:35 -07003555search_free:
Ben Widawsky07fe0b12013-07-31 17:00:10 -07003556 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
Ben Widawsky0a9ae0d2013-05-25 12:26:35 -07003557 size, alignment,
Chris Wilsond23db882014-05-23 08:48:08 +02003558 obj->cache_level,
3559 start, end,
Lauri Kasanen62347f92014-04-02 20:03:57 +03003560 DRM_MM_SEARCH_DEFAULT,
3561 DRM_MM_CREATE_DEFAULT);
Chris Wilsondc9dd7a2012-12-07 20:37:07 +00003562 if (ret) {
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07003563 ret = i915_gem_evict_something(dev, vm, size, alignment,
Chris Wilsond23db882014-05-23 08:48:08 +02003564 obj->cache_level,
3565 start, end,
3566 flags);
Chris Wilsondc9dd7a2012-12-07 20:37:07 +00003567 if (ret == 0)
3568 goto search_free;
Chris Wilson97311292009-09-21 00:22:34 +01003569
Daniel Vetterbc6bc152013-07-22 12:12:38 +02003570 goto err_free_vma;
Chris Wilsondc9dd7a2012-12-07 20:37:07 +00003571 }
Chris Wilson4144f9b2014-09-11 08:43:48 +01003572 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
Ben Widawsky2f633152013-07-17 12:19:03 -07003573 ret = -EINVAL;
Daniel Vetterbc6bc152013-07-22 12:12:38 +02003574 goto err_remove_node;
Eric Anholt673a3942008-07-30 12:06:12 -07003575 }
3576
Daniel Vetter74163902012-02-15 23:50:21 +01003577 ret = i915_gem_gtt_prepare_object(obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07003578 if (ret)
Daniel Vetterbc6bc152013-07-22 12:12:38 +02003579 goto err_remove_node;
Eric Anholt673a3942008-07-30 12:06:12 -07003580
Ben Widawsky35c20a62013-05-31 11:28:48 -07003581 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
Ben Widawskyca191b12013-07-31 17:00:14 -07003582 list_add_tail(&vma->mm_list, &vm->inactive_list);
Chris Wilsonbf1a1092010-08-07 11:01:20 +01003583
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003584 trace_i915_vma_bind(vma, flags);
Daniel Vetter8ea99c92014-02-14 14:01:21 +01003585 vma->bind_vma(vma, obj->cache_level,
Chris Wilsonc826c442014-10-31 13:53:53 +00003586 flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
Daniel Vetter8ea99c92014-02-14 14:01:21 +01003587
Daniel Vetter262de142014-02-14 14:01:20 +01003588 return vma;
Ben Widawsky2f633152013-07-17 12:19:03 -07003589
Daniel Vetterbc6bc152013-07-22 12:12:38 +02003590err_remove_node:
Dan Carpenter6286ef92013-07-19 08:46:27 +03003591 drm_mm_remove_node(&vma->node);
Daniel Vetterbc6bc152013-07-22 12:12:38 +02003592err_free_vma:
Ben Widawsky2f633152013-07-17 12:19:03 -07003593 i915_gem_vma_destroy(vma);
Daniel Vetter262de142014-02-14 14:01:20 +01003594 vma = ERR_PTR(ret);
Daniel Vetterbc6bc152013-07-22 12:12:38 +02003595err_unpin:
Ben Widawsky2f633152013-07-17 12:19:03 -07003596 i915_gem_object_unpin_pages(obj);
Daniel Vetter262de142014-02-14 14:01:20 +01003597 return vma;
Eric Anholt673a3942008-07-30 12:06:12 -07003598}
3599
Chris Wilson000433b2013-08-08 14:41:09 +01003600bool
Chris Wilson2c225692013-08-09 12:26:45 +01003601i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3602 bool force)
Eric Anholt673a3942008-07-30 12:06:12 -07003603{
Eric Anholt673a3942008-07-30 12:06:12 -07003604 /* If we don't have a page list set up, then we're not pinned
3605 * to GPU, and we can ignore the cache flush because it'll happen
3606 * again at bind time.
3607 */
Chris Wilson05394f32010-11-08 19:18:58 +00003608 if (obj->pages == NULL)
Chris Wilson000433b2013-08-08 14:41:09 +01003609 return false;
Eric Anholt673a3942008-07-30 12:06:12 -07003610
Imre Deak769ce462013-02-13 21:56:05 +02003611 /*
3612 * Stolen memory is always coherent with the GPU as it is explicitly
3613 * marked as wc by the system, or the system is cache-coherent.
3614 */
Chris Wilson6a2c4232014-11-04 04:51:40 -08003615 if (obj->stolen || obj->phys_handle)
Chris Wilson000433b2013-08-08 14:41:09 +01003616 return false;
Imre Deak769ce462013-02-13 21:56:05 +02003617
Chris Wilson9c23f7f2011-03-29 16:59:52 -07003618 /* If the GPU is snooping the contents of the CPU cache,
3619 * we do not need to manually clear the CPU cache lines. However,
3620 * the caches are only snooped when the render cache is
3621 * flushed/invalidated. As we always have to emit invalidations
3622 * and flushes when moving into and out of the RENDER domain, correct
3623 * snooping behaviour occurs naturally as the result of our domain
3624 * tracking.
3625 */
Chris Wilson2c225692013-08-09 12:26:45 +01003626 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
Chris Wilson000433b2013-08-08 14:41:09 +01003627 return false;
Chris Wilson9c23f7f2011-03-29 16:59:52 -07003628
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003629 trace_i915_gem_object_clflush(obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01003630 drm_clflush_sg(obj->pages);
Chris Wilson000433b2013-08-08 14:41:09 +01003631
3632 return true;
Eric Anholte47c68e2008-11-14 13:35:19 -08003633}
3634
3635/** Flushes the GTT write domain for the object if it's dirty. */
3636static void
Chris Wilson05394f32010-11-08 19:18:58 +00003637i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
Eric Anholte47c68e2008-11-14 13:35:19 -08003638{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003639 uint32_t old_write_domain;
3640
Chris Wilson05394f32010-11-08 19:18:58 +00003641 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
Eric Anholte47c68e2008-11-14 13:35:19 -08003642 return;
3643
Chris Wilson63256ec2011-01-04 18:42:07 +00003644 /* No actual flushing is required for the GTT write domain. Writes
Eric Anholte47c68e2008-11-14 13:35:19 -08003645 * to it immediately go to main memory as far as we know, so there's
3646 * no chipset flush. It also doesn't land in render cache.
Chris Wilson63256ec2011-01-04 18:42:07 +00003647 *
3648 * However, we do have to enforce the order so that all writes through
3649 * the GTT land before any writes to the device, such as updates to
3650 * the GATT itself.
Eric Anholte47c68e2008-11-14 13:35:19 -08003651 */
Chris Wilson63256ec2011-01-04 18:42:07 +00003652 wmb();
3653
Chris Wilson05394f32010-11-08 19:18:58 +00003654 old_write_domain = obj->base.write_domain;
3655 obj->base.write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003656
Daniel Vetterf99d7062014-06-19 16:01:59 +02003657 intel_fb_obj_flush(obj, false);
3658
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003659 trace_i915_gem_object_change_domain(obj,
Chris Wilson05394f32010-11-08 19:18:58 +00003660 obj->base.read_domains,
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003661 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08003662}
3663
3664/** Flushes the CPU write domain for the object if it's dirty. */
3665static void
Chris Wilson2c225692013-08-09 12:26:45 +01003666i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3667 bool force)
Eric Anholte47c68e2008-11-14 13:35:19 -08003668{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003669 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08003670
Chris Wilson05394f32010-11-08 19:18:58 +00003671 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
Eric Anholte47c68e2008-11-14 13:35:19 -08003672 return;
3673
Chris Wilson000433b2013-08-08 14:41:09 +01003674 if (i915_gem_clflush_object(obj, force))
3675 i915_gem_chipset_flush(obj->base.dev);
3676
Chris Wilson05394f32010-11-08 19:18:58 +00003677 old_write_domain = obj->base.write_domain;
3678 obj->base.write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003679
Daniel Vetterf99d7062014-06-19 16:01:59 +02003680 intel_fb_obj_flush(obj, false);
3681
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003682 trace_i915_gem_object_change_domain(obj,
Chris Wilson05394f32010-11-08 19:18:58 +00003683 obj->base.read_domains,
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003684 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08003685}
3686
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003687/**
3688 * Moves a single object to the GTT read, and possibly write domain.
3689 *
3690 * This function returns when the move is complete, including waiting on
3691 * flushes to occur.
3692 */
Jesse Barnes79e53942008-11-07 14:24:08 -08003693int
Chris Wilson20217462010-11-23 15:26:33 +00003694i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003695{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03003696 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsondc8cd1e2014-08-09 17:37:22 +01003697 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003698 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003699 int ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003700
Eric Anholt02354392008-11-26 13:58:13 -08003701 /* Not valid to be called on unbound objects. */
Chris Wilsondc8cd1e2014-08-09 17:37:22 +01003702 if (vma == NULL)
Eric Anholt02354392008-11-26 13:58:13 -08003703 return -EINVAL;
3704
Chris Wilson8d7e3de2011-02-07 15:23:02 +00003705 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3706 return 0;
3707
Chris Wilson0201f1e2012-07-20 12:41:01 +01003708 ret = i915_gem_object_wait_rendering(obj, !write);
Chris Wilson88241782011-01-07 17:09:48 +00003709 if (ret)
3710 return ret;
3711
Chris Wilsonc8725f32014-03-17 12:21:55 +00003712 i915_gem_object_retire(obj);
Chris Wilson2c225692013-08-09 12:26:45 +01003713 i915_gem_object_flush_cpu_write_domain(obj, false);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003714
Chris Wilsond0a57782012-10-09 19:24:37 +01003715 /* Serialise direct access to this object with the barriers for
3716 * coherent writes from the GPU, by effectively invalidating the
3717 * GTT domain upon first access.
3718 */
3719 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3720 mb();
3721
Chris Wilson05394f32010-11-08 19:18:58 +00003722 old_write_domain = obj->base.write_domain;
3723 old_read_domains = obj->base.read_domains;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003724
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003725 /* It should now be out of any other write domains, and we can update
3726 * the domain values for our changes.
3727 */
Chris Wilson05394f32010-11-08 19:18:58 +00003728 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3729 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08003730 if (write) {
Chris Wilson05394f32010-11-08 19:18:58 +00003731 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3732 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3733 obj->dirty = 1;
Eric Anholte47c68e2008-11-14 13:35:19 -08003734 }
3735
Daniel Vetterf99d7062014-06-19 16:01:59 +02003736 if (write)
3737 intel_fb_obj_invalidate(obj, NULL);
3738
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003739 trace_i915_gem_object_change_domain(obj,
3740 old_read_domains,
3741 old_write_domain);
3742
Chris Wilson8325a092012-04-24 15:52:35 +01003743 /* And bump the LRU for this access */
Chris Wilsondc8cd1e2014-08-09 17:37:22 +01003744 if (i915_gem_object_is_inactive(obj))
3745 list_move_tail(&vma->mm_list,
3746 &dev_priv->gtt.base.inactive_list);
Chris Wilson8325a092012-04-24 15:52:35 +01003747
Eric Anholte47c68e2008-11-14 13:35:19 -08003748 return 0;
3749}
3750
Chris Wilsone4ffd172011-04-04 09:44:39 +01003751int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3752 enum i915_cache_level cache_level)
3753{
Daniel Vetter7bddb012012-02-09 17:15:47 +01003754 struct drm_device *dev = obj->base.dev;
Chris Wilsondf6f7832014-03-21 07:40:56 +00003755 struct i915_vma *vma, *next;
Chris Wilsone4ffd172011-04-04 09:44:39 +01003756 int ret;
3757
3758 if (obj->cache_level == cache_level)
3759 return 0;
3760
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08003761 if (i915_gem_obj_is_pinned(obj)) {
Chris Wilsone4ffd172011-04-04 09:44:39 +01003762 DRM_DEBUG("can not change the cache level of pinned objects\n");
3763 return -EBUSY;
3764 }
3765
Chris Wilsondf6f7832014-03-21 07:40:56 +00003766 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
Chris Wilson4144f9b2014-09-11 08:43:48 +01003767 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
Ben Widawsky07fe0b12013-07-31 17:00:10 -07003768 ret = i915_vma_unbind(vma);
Ben Widawsky3089c6f2013-07-31 17:00:03 -07003769 if (ret)
3770 return ret;
Ben Widawsky3089c6f2013-07-31 17:00:03 -07003771 }
Chris Wilson42d6ab42012-07-26 11:49:32 +01003772 }
3773
Ben Widawsky3089c6f2013-07-31 17:00:03 -07003774 if (i915_gem_obj_bound_any(obj)) {
Chris Wilsone4ffd172011-04-04 09:44:39 +01003775 ret = i915_gem_object_finish_gpu(obj);
3776 if (ret)
3777 return ret;
3778
3779 i915_gem_object_finish_gtt(obj);
3780
3781 /* Before SandyBridge, you could not use tiling or fence
3782 * registers with snooped memory, so relinquish any fences
3783 * currently pointing to our region in the aperture.
3784 */
Chris Wilson42d6ab42012-07-26 11:49:32 +01003785 if (INTEL_INFO(dev)->gen < 6) {
Chris Wilsone4ffd172011-04-04 09:44:39 +01003786 ret = i915_gem_object_put_fence(obj);
3787 if (ret)
3788 return ret;
3789 }
3790
Ben Widawsky6f65e292013-12-06 14:10:56 -08003791 list_for_each_entry(vma, &obj->vma_list, vma_link)
Daniel Vetter8ea99c92014-02-14 14:01:21 +01003792 if (drm_mm_node_allocated(&vma->node))
3793 vma->bind_vma(vma, cache_level,
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01003794 vma->bound & GLOBAL_BIND);
Chris Wilsone4ffd172011-04-04 09:44:39 +01003795 }
3796
Chris Wilson2c225692013-08-09 12:26:45 +01003797 list_for_each_entry(vma, &obj->vma_list, vma_link)
3798 vma->node.color = cache_level;
3799 obj->cache_level = cache_level;
3800
3801 if (cpu_write_needs_clflush(obj)) {
Chris Wilsone4ffd172011-04-04 09:44:39 +01003802 u32 old_read_domains, old_write_domain;
3803
3804 /* If we're coming from LLC cached, then we haven't
3805 * actually been tracking whether the data is in the
3806 * CPU cache or not, since we only allow one bit set
3807 * in obj->write_domain and have been skipping the clflushes.
3808 * Just set it to the CPU cache for now.
3809 */
Chris Wilsonc8725f32014-03-17 12:21:55 +00003810 i915_gem_object_retire(obj);
Chris Wilsone4ffd172011-04-04 09:44:39 +01003811 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
Chris Wilsone4ffd172011-04-04 09:44:39 +01003812
3813 old_read_domains = obj->base.read_domains;
3814 old_write_domain = obj->base.write_domain;
3815
3816 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3817 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3818
3819 trace_i915_gem_object_change_domain(obj,
3820 old_read_domains,
3821 old_write_domain);
3822 }
3823
Chris Wilsone4ffd172011-04-04 09:44:39 +01003824 return 0;
3825}
3826
Ben Widawsky199adf42012-09-21 17:01:20 -07003827int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3828 struct drm_file *file)
Chris Wilsone6994ae2012-07-10 10:27:08 +01003829{
Ben Widawsky199adf42012-09-21 17:01:20 -07003830 struct drm_i915_gem_caching *args = data;
Chris Wilsone6994ae2012-07-10 10:27:08 +01003831 struct drm_i915_gem_object *obj;
3832 int ret;
3833
3834 ret = i915_mutex_lock_interruptible(dev);
3835 if (ret)
3836 return ret;
3837
3838 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3839 if (&obj->base == NULL) {
3840 ret = -ENOENT;
3841 goto unlock;
3842 }
3843
Chris Wilson651d7942013-08-08 14:41:10 +01003844 switch (obj->cache_level) {
3845 case I915_CACHE_LLC:
3846 case I915_CACHE_L3_LLC:
3847 args->caching = I915_CACHING_CACHED;
3848 break;
3849
Chris Wilson4257d3b2013-08-08 14:41:11 +01003850 case I915_CACHE_WT:
3851 args->caching = I915_CACHING_DISPLAY;
3852 break;
3853
Chris Wilson651d7942013-08-08 14:41:10 +01003854 default:
3855 args->caching = I915_CACHING_NONE;
3856 break;
3857 }
Chris Wilsone6994ae2012-07-10 10:27:08 +01003858
3859 drm_gem_object_unreference(&obj->base);
3860unlock:
3861 mutex_unlock(&dev->struct_mutex);
3862 return ret;
3863}
3864
Ben Widawsky199adf42012-09-21 17:01:20 -07003865int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3866 struct drm_file *file)
Chris Wilsone6994ae2012-07-10 10:27:08 +01003867{
Ben Widawsky199adf42012-09-21 17:01:20 -07003868 struct drm_i915_gem_caching *args = data;
Chris Wilsone6994ae2012-07-10 10:27:08 +01003869 struct drm_i915_gem_object *obj;
3870 enum i915_cache_level level;
3871 int ret;
3872
Ben Widawsky199adf42012-09-21 17:01:20 -07003873 switch (args->caching) {
3874 case I915_CACHING_NONE:
Chris Wilsone6994ae2012-07-10 10:27:08 +01003875 level = I915_CACHE_NONE;
3876 break;
Ben Widawsky199adf42012-09-21 17:01:20 -07003877 case I915_CACHING_CACHED:
Chris Wilsone6994ae2012-07-10 10:27:08 +01003878 level = I915_CACHE_LLC;
3879 break;
Chris Wilson4257d3b2013-08-08 14:41:11 +01003880 case I915_CACHING_DISPLAY:
3881 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3882 break;
Chris Wilsone6994ae2012-07-10 10:27:08 +01003883 default:
3884 return -EINVAL;
3885 }
3886
Ben Widawsky3bc29132012-09-26 16:15:20 -07003887 ret = i915_mutex_lock_interruptible(dev);
3888 if (ret)
3889 return ret;
3890
Chris Wilsone6994ae2012-07-10 10:27:08 +01003891 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3892 if (&obj->base == NULL) {
3893 ret = -ENOENT;
3894 goto unlock;
3895 }
3896
3897 ret = i915_gem_object_set_cache_level(obj, level);
3898
3899 drm_gem_object_unreference(&obj->base);
3900unlock:
3901 mutex_unlock(&dev->struct_mutex);
3902 return ret;
3903}
3904
Chris Wilsoncc98b412013-08-09 12:25:09 +01003905static bool is_pin_display(struct drm_i915_gem_object *obj)
3906{
Oscar Mateo19656432014-05-16 14:20:43 +01003907 struct i915_vma *vma;
3908
Oscar Mateo19656432014-05-16 14:20:43 +01003909 vma = i915_gem_obj_to_ggtt(obj);
3910 if (!vma)
3911 return false;
3912
Daniel Vetter4feb7652014-11-24 11:21:52 +01003913 /* There are 2 sources that pin objects:
Chris Wilsoncc98b412013-08-09 12:25:09 +01003914 * 1. The display engine (scanouts, sprites, cursors);
3915 * 2. Reservations for execbuffer;
Chris Wilsoncc98b412013-08-09 12:25:09 +01003916 *
3917 * We can ignore reservations as we hold the struct_mutex and
Daniel Vetter4feb7652014-11-24 11:21:52 +01003918 * are only called outside of the reservation path.
Chris Wilsoncc98b412013-08-09 12:25:09 +01003919 */
Daniel Vetter4feb7652014-11-24 11:21:52 +01003920 return vma->pin_count;
Chris Wilsoncc98b412013-08-09 12:25:09 +01003921}
3922
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08003923/*
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003924 * Prepare buffer for display plane (scanout, cursors, etc).
3925 * Can be called from an uninterruptible phase (modesetting) and allows
3926 * any flushes to be pipelined (for pageflips).
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08003927 */
3928int
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003929i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3930 u32 alignment,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01003931 struct intel_engine_cs *pipelined)
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08003932{
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003933 u32 old_read_domains, old_write_domain;
Oscar Mateo19656432014-05-16 14:20:43 +01003934 bool was_pin_display;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08003935 int ret;
3936
John Harrison41c52412014-11-24 18:49:43 +00003937 if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
Ben Widawsky2911a352012-04-05 14:47:36 -07003938 ret = i915_gem_object_sync(obj, pipelined);
3939 if (ret)
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08003940 return ret;
3941 }
3942
Chris Wilsoncc98b412013-08-09 12:25:09 +01003943 /* Mark the pin_display early so that we account for the
3944 * display coherency whilst setting up the cache domains.
3945 */
Oscar Mateo19656432014-05-16 14:20:43 +01003946 was_pin_display = obj->pin_display;
Chris Wilsoncc98b412013-08-09 12:25:09 +01003947 obj->pin_display = true;
3948
Eric Anholta7ef0642011-03-29 16:59:54 -07003949 /* The display engine is not coherent with the LLC cache on gen6. As
3950 * a result, we make sure that the pinning that is about to occur is
3951 * done with uncached PTEs. This is lowest common denominator for all
3952 * chipsets.
3953 *
3954 * However for gen6+, we could do better by using the GFDT bit instead
3955 * of uncaching, which would allow us to flush all the LLC-cached data
3956 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3957 */
Chris Wilson651d7942013-08-08 14:41:10 +01003958 ret = i915_gem_object_set_cache_level(obj,
3959 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
Eric Anholta7ef0642011-03-29 16:59:54 -07003960 if (ret)
Chris Wilsoncc98b412013-08-09 12:25:09 +01003961 goto err_unpin_display;
Eric Anholta7ef0642011-03-29 16:59:54 -07003962
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003963 /* As the user may map the buffer once pinned in the display plane
3964 * (e.g. libkms for the bootup splash), we have to ensure that we
3965 * always use map_and_fenceable for all scanout buffers.
3966 */
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003967 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003968 if (ret)
Chris Wilsoncc98b412013-08-09 12:25:09 +01003969 goto err_unpin_display;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003970
Chris Wilson2c225692013-08-09 12:26:45 +01003971 i915_gem_object_flush_cpu_write_domain(obj, true);
Chris Wilsonb118c1e2010-05-27 13:18:14 +01003972
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003973 old_write_domain = obj->base.write_domain;
Chris Wilson05394f32010-11-08 19:18:58 +00003974 old_read_domains = obj->base.read_domains;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003975
3976 /* It should now be out of any other write domains, and we can update
3977 * the domain values for our changes.
3978 */
Chris Wilsone5f1d962012-07-20 12:41:00 +01003979 obj->base.write_domain = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00003980 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08003981
3982 trace_i915_gem_object_change_domain(obj,
3983 old_read_domains,
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003984 old_write_domain);
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08003985
3986 return 0;
Chris Wilsoncc98b412013-08-09 12:25:09 +01003987
3988err_unpin_display:
Oscar Mateo19656432014-05-16 14:20:43 +01003989 WARN_ON(was_pin_display != is_pin_display(obj));
3990 obj->pin_display = was_pin_display;
Chris Wilsoncc98b412013-08-09 12:25:09 +01003991 return ret;
3992}
3993
3994void
3995i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3996{
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08003997 i915_gem_object_ggtt_unpin(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01003998 obj->pin_display = is_pin_display(obj);
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08003999}
4000
Chris Wilson85345512010-11-13 09:49:11 +00004001int
Chris Wilsona8198ee2011-04-13 22:04:09 +01004002i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
Chris Wilson85345512010-11-13 09:49:11 +00004003{
Chris Wilson88241782011-01-07 17:09:48 +00004004 int ret;
4005
Chris Wilsona8198ee2011-04-13 22:04:09 +01004006 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
Chris Wilson85345512010-11-13 09:49:11 +00004007 return 0;
4008
Chris Wilson0201f1e2012-07-20 12:41:01 +01004009 ret = i915_gem_object_wait_rendering(obj, false);
Chris Wilsonc501ae72011-12-14 13:57:23 +01004010 if (ret)
4011 return ret;
4012
Chris Wilsona8198ee2011-04-13 22:04:09 +01004013 /* Ensure that we invalidate the GPU's caches and TLBs. */
4014 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
Chris Wilsonc501ae72011-12-14 13:57:23 +01004015 return 0;
Chris Wilson85345512010-11-13 09:49:11 +00004016}
4017
Eric Anholte47c68e2008-11-14 13:35:19 -08004018/**
4019 * Moves a single object to the CPU read, and possibly write domain.
4020 *
4021 * This function returns when the move is complete, including waiting on
4022 * flushes to occur.
4023 */
Chris Wilsondabdfe02012-03-26 10:10:27 +02004024int
Chris Wilson919926a2010-11-12 13:42:53 +00004025i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
Eric Anholte47c68e2008-11-14 13:35:19 -08004026{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004027 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08004028 int ret;
4029
Chris Wilson8d7e3de2011-02-07 15:23:02 +00004030 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4031 return 0;
4032
Chris Wilson0201f1e2012-07-20 12:41:01 +01004033 ret = i915_gem_object_wait_rendering(obj, !write);
Chris Wilson88241782011-01-07 17:09:48 +00004034 if (ret)
4035 return ret;
4036
Chris Wilsonc8725f32014-03-17 12:21:55 +00004037 i915_gem_object_retire(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08004038 i915_gem_object_flush_gtt_write_domain(obj);
4039
Chris Wilson05394f32010-11-08 19:18:58 +00004040 old_write_domain = obj->base.write_domain;
4041 old_read_domains = obj->base.read_domains;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004042
Eric Anholte47c68e2008-11-14 13:35:19 -08004043 /* Flush the CPU cache if it's still invalid. */
Chris Wilson05394f32010-11-08 19:18:58 +00004044 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
Chris Wilson2c225692013-08-09 12:26:45 +01004045 i915_gem_clflush_object(obj, false);
Eric Anholte47c68e2008-11-14 13:35:19 -08004046
Chris Wilson05394f32010-11-08 19:18:58 +00004047 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
Eric Anholte47c68e2008-11-14 13:35:19 -08004048 }
4049
4050 /* It should now be out of any other write domains, and we can update
4051 * the domain values for our changes.
4052 */
Chris Wilson05394f32010-11-08 19:18:58 +00004053 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
Eric Anholte47c68e2008-11-14 13:35:19 -08004054
4055 /* If we're writing through the CPU, then the GPU read domains will
4056 * need to be invalidated at next use.
4057 */
4058 if (write) {
Chris Wilson05394f32010-11-08 19:18:58 +00004059 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4060 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
Eric Anholte47c68e2008-11-14 13:35:19 -08004061 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08004062
Daniel Vetterf99d7062014-06-19 16:01:59 +02004063 if (write)
4064 intel_fb_obj_invalidate(obj, NULL);
4065
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004066 trace_i915_gem_object_change_domain(obj,
4067 old_read_domains,
4068 old_write_domain);
4069
Eric Anholt2ef7eea2008-11-10 10:53:25 -08004070 return 0;
4071}
4072
Eric Anholt673a3942008-07-30 12:06:12 -07004073/* Throttle our rendering by waiting until the ring has completed our requests
4074 * emitted over 20 msec ago.
4075 *
Eric Anholtb9624422009-06-03 07:27:35 +00004076 * Note that if we were to use the current jiffies each time around the loop,
4077 * we wouldn't escape the function with any frames outstanding if the time to
4078 * render a frame was over 20ms.
4079 *
Eric Anholt673a3942008-07-30 12:06:12 -07004080 * This should get us reasonable parallelism between CPU and GPU but also
4081 * relatively low latency when blocking on a particular request to finish.
4082 */
4083static int
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004084i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
Eric Anholt673a3942008-07-30 12:06:12 -07004085{
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct drm_i915_file_private *file_priv = file->driver_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00004088 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
John Harrison54fb2412014-11-24 18:49:27 +00004089 struct drm_i915_gem_request *request, *target = NULL;
Daniel Vetterf69061b2012-12-06 09:01:42 +01004090 unsigned reset_counter;
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004091 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004092
Daniel Vetter308887a2012-11-14 17:14:06 +01004093 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4094 if (ret)
4095 return ret;
4096
4097 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4098 if (ret)
4099 return ret;
Chris Wilsone110e8d2011-01-26 15:39:14 +00004100
Chris Wilson1c255952010-09-26 11:03:27 +01004101 spin_lock(&file_priv->mm.lock);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004102 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
Eric Anholtb9624422009-06-03 07:27:35 +00004103 if (time_after_eq(request->emitted_jiffies, recent_enough))
4104 break;
4105
John Harrison54fb2412014-11-24 18:49:27 +00004106 target = request;
Eric Anholtb9624422009-06-03 07:27:35 +00004107 }
Daniel Vetterf69061b2012-12-06 09:01:42 +01004108 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
John Harrisonff865882014-11-24 18:49:28 +00004109 if (target)
4110 i915_gem_request_reference(target);
Chris Wilson1c255952010-09-26 11:03:27 +01004111 spin_unlock(&file_priv->mm.lock);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004112
John Harrison54fb2412014-11-24 18:49:27 +00004113 if (target == NULL)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004114 return 0;
4115
John Harrison9c654812014-11-24 18:49:35 +00004116 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004117 if (ret == 0)
4118 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
Eric Anholtb9624422009-06-03 07:27:35 +00004119
John Harrisonff865882014-11-24 18:49:28 +00004120 mutex_lock(&dev->struct_mutex);
4121 i915_gem_request_unreference(target);
4122 mutex_unlock(&dev->struct_mutex);
4123
Eric Anholt673a3942008-07-30 12:06:12 -07004124 return ret;
4125}
4126
Chris Wilsond23db882014-05-23 08:48:08 +02004127static bool
4128i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4129{
4130 struct drm_i915_gem_object *obj = vma->obj;
4131
4132 if (alignment &&
4133 vma->node.start & (alignment - 1))
4134 return true;
4135
4136 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4137 return true;
4138
4139 if (flags & PIN_OFFSET_BIAS &&
4140 vma->node.start < (flags & PIN_OFFSET_MASK))
4141 return true;
4142
4143 return false;
4144}
4145
Eric Anholt673a3942008-07-30 12:06:12 -07004146int
Chris Wilson05394f32010-11-08 19:18:58 +00004147i915_gem_object_pin(struct drm_i915_gem_object *obj,
Ben Widawskyc37e2202013-07-31 16:59:58 -07004148 struct i915_address_space *vm,
Chris Wilson05394f32010-11-08 19:18:58 +00004149 uint32_t alignment,
Chris Wilsond23db882014-05-23 08:48:08 +02004150 uint64_t flags)
Eric Anholt673a3942008-07-30 12:06:12 -07004151{
Ben Widawsky6e7186a2014-05-06 22:21:36 -07004152 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004153 struct i915_vma *vma;
Chris Wilsonef79e172014-10-31 13:53:52 +00004154 unsigned bound;
Eric Anholt673a3942008-07-30 12:06:12 -07004155 int ret;
4156
Ben Widawsky6e7186a2014-05-06 22:21:36 -07004157 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4158 return -ENODEV;
4159
Daniel Vetterbf3d1492014-02-14 14:01:12 +01004160 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
Daniel Vetter1ec9e262014-02-14 14:01:11 +01004161 return -EINVAL;
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004162
Chris Wilsonc826c442014-10-31 13:53:53 +00004163 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4164 return -EINVAL;
4165
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004166 vma = i915_gem_obj_to_vma(obj, vm);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004167 if (vma) {
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08004168 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4169 return -EBUSY;
4170
Chris Wilsond23db882014-05-23 08:48:08 +02004171 if (i915_vma_misplaced(vma, alignment, flags)) {
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08004172 WARN(vma->pin_count,
Chris Wilsonae7d49d2010-08-04 12:37:41 +01004173 "bo is already pinned with incorrect alignment:"
Ben Widawskyf343c5f2013-07-05 14:41:04 -07004174 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
Daniel Vetter75e9e912010-11-04 17:11:09 +01004175 " obj->map_and_fenceable=%d\n",
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004176 i915_gem_obj_offset(obj, vm), alignment,
Chris Wilsond23db882014-05-23 08:48:08 +02004177 !!(flags & PIN_MAPPABLE),
Chris Wilson05394f32010-11-08 19:18:58 +00004178 obj->map_and_fenceable);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004179 ret = i915_vma_unbind(vma);
Chris Wilsonac0c6b52010-05-27 13:18:18 +01004180 if (ret)
4181 return ret;
Daniel Vetter8ea99c92014-02-14 14:01:21 +01004182
4183 vma = NULL;
Chris Wilsonac0c6b52010-05-27 13:18:18 +01004184 }
4185 }
4186
Chris Wilsonef79e172014-10-31 13:53:52 +00004187 bound = vma ? vma->bound : 0;
Daniel Vetter8ea99c92014-02-14 14:01:21 +01004188 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
Daniel Vetter262de142014-02-14 14:01:20 +01004189 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4190 if (IS_ERR(vma))
4191 return PTR_ERR(vma);
Chris Wilson22c344e2009-02-11 14:26:45 +00004192 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05004193
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01004194 if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND))
Daniel Vetter8ea99c92014-02-14 14:01:21 +01004195 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
Daniel Vetter74898d72012-02-15 23:50:22 +01004196
Chris Wilsonef79e172014-10-31 13:53:52 +00004197 if ((bound ^ vma->bound) & GLOBAL_BIND) {
4198 bool mappable, fenceable;
4199 u32 fence_size, fence_alignment;
4200
4201 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4202 obj->base.size,
4203 obj->tiling_mode);
4204 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4205 obj->base.size,
4206 obj->tiling_mode,
4207 true);
4208
4209 fenceable = (vma->node.size == fence_size &&
4210 (vma->node.start & (fence_alignment - 1)) == 0);
4211
4212 mappable = (vma->node.start + obj->base.size <=
4213 dev_priv->gtt.mappable_end);
4214
4215 obj->map_and_fenceable = mappable && fenceable;
4216 }
4217
4218 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4219
Daniel Vetter8ea99c92014-02-14 14:01:21 +01004220 vma->pin_count++;
Daniel Vetter1ec9e262014-02-14 14:01:11 +01004221 if (flags & PIN_MAPPABLE)
4222 obj->pin_mappable |= true;
Eric Anholt673a3942008-07-30 12:06:12 -07004223
4224 return 0;
4225}
4226
4227void
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08004228i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07004229{
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08004230 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004231
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08004232 BUG_ON(!vma);
4233 BUG_ON(vma->pin_count == 0);
4234 BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4235
4236 if (--vma->pin_count == 0)
Chris Wilson6299f992010-11-24 12:23:44 +00004237 obj->pin_mappable = false;
Eric Anholt673a3942008-07-30 12:06:12 -07004238}
4239
Daniel Vetterd8ffa602014-05-13 12:11:26 +02004240bool
4241i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4242{
4243 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4244 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4245 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4246
4247 WARN_ON(!ggtt_vma ||
4248 dev_priv->fence_regs[obj->fence_reg].pin_count >
4249 ggtt_vma->pin_count);
4250 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4251 return true;
4252 } else
4253 return false;
4254}
4255
4256void
4257i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4258{
4259 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4260 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4261 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4262 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4263 }
4264}
4265
Eric Anholt673a3942008-07-30 12:06:12 -07004266int
Eric Anholt673a3942008-07-30 12:06:12 -07004267i915_gem_busy_ioctl(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00004268 struct drm_file *file)
Eric Anholt673a3942008-07-30 12:06:12 -07004269{
4270 struct drm_i915_gem_busy *args = data;
Chris Wilson05394f32010-11-08 19:18:58 +00004271 struct drm_i915_gem_object *obj;
Chris Wilson30dbf0c2010-09-25 10:19:17 +01004272 int ret;
4273
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004274 ret = i915_mutex_lock_interruptible(dev);
4275 if (ret)
4276 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004277
Chris Wilson05394f32010-11-08 19:18:58 +00004278 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00004279 if (&obj->base == NULL) {
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004280 ret = -ENOENT;
4281 goto unlock;
Eric Anholt673a3942008-07-30 12:06:12 -07004282 }
Zou Nan haid1b851f2010-05-21 09:08:57 +08004283
Chris Wilson0be555b2010-08-04 15:36:30 +01004284 /* Count all active objects as busy, even if they are currently not used
4285 * by the gpu. Users of this interface expect objects to eventually
4286 * become non-busy without any further actions, therefore emit any
4287 * necessary flushes here.
Eric Anholtc4de0a52008-12-14 19:05:04 -08004288 */
Daniel Vetter30dfebf2012-06-01 15:21:23 +02004289 ret = i915_gem_object_flush_active(obj);
4290
Chris Wilson05394f32010-11-08 19:18:58 +00004291 args->busy = obj->active;
John Harrison41c52412014-11-24 18:49:43 +00004292 if (obj->last_read_req) {
4293 struct intel_engine_cs *ring;
Chris Wilsone9808ed2012-07-04 12:25:08 +01004294 BUILD_BUG_ON(I915_NUM_RINGS > 16);
John Harrison41c52412014-11-24 18:49:43 +00004295 ring = i915_gem_request_get_ring(obj->last_read_req);
4296 args->busy |= intel_ring_flag(ring) << 16;
Chris Wilsone9808ed2012-07-04 12:25:08 +01004297 }
Eric Anholt673a3942008-07-30 12:06:12 -07004298
Chris Wilson05394f32010-11-08 19:18:58 +00004299 drm_gem_object_unreference(&obj->base);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004300unlock:
Eric Anholt673a3942008-07-30 12:06:12 -07004301 mutex_unlock(&dev->struct_mutex);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004302 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004303}
4304
4305int
4306i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4307 struct drm_file *file_priv)
4308{
Akshay Joshi0206e352011-08-16 15:34:10 -04004309 return i915_gem_ring_throttle(dev, file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07004310}
4311
Chris Wilson3ef94da2009-09-14 16:50:29 +01004312int
4313i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4314 struct drm_file *file_priv)
4315{
Daniel Vetter656bfa32014-11-20 09:26:30 +01004316 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004317 struct drm_i915_gem_madvise *args = data;
Chris Wilson05394f32010-11-08 19:18:58 +00004318 struct drm_i915_gem_object *obj;
Chris Wilson76c1dec2010-09-25 11:22:51 +01004319 int ret;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004320
4321 switch (args->madv) {
4322 case I915_MADV_DONTNEED:
4323 case I915_MADV_WILLNEED:
4324 break;
4325 default:
4326 return -EINVAL;
4327 }
4328
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004329 ret = i915_mutex_lock_interruptible(dev);
4330 if (ret)
4331 return ret;
4332
Chris Wilson05394f32010-11-08 19:18:58 +00004333 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00004334 if (&obj->base == NULL) {
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004335 ret = -ENOENT;
4336 goto unlock;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004337 }
Chris Wilson3ef94da2009-09-14 16:50:29 +01004338
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08004339 if (i915_gem_obj_is_pinned(obj)) {
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004340 ret = -EINVAL;
4341 goto out;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004342 }
4343
Daniel Vetter656bfa32014-11-20 09:26:30 +01004344 if (obj->pages &&
4345 obj->tiling_mode != I915_TILING_NONE &&
4346 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4347 if (obj->madv == I915_MADV_WILLNEED)
4348 i915_gem_object_unpin_pages(obj);
4349 if (args->madv == I915_MADV_WILLNEED)
4350 i915_gem_object_pin_pages(obj);
4351 }
4352
Chris Wilson05394f32010-11-08 19:18:58 +00004353 if (obj->madv != __I915_MADV_PURGED)
4354 obj->madv = args->madv;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004355
Chris Wilson6c085a72012-08-20 11:40:46 +02004356 /* if the object is no longer attached, discard its backing storage */
4357 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
Chris Wilson2d7ef392009-09-20 23:13:10 +01004358 i915_gem_object_truncate(obj);
4359
Chris Wilson05394f32010-11-08 19:18:58 +00004360 args->retained = obj->madv != __I915_MADV_PURGED;
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004361
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004362out:
Chris Wilson05394f32010-11-08 19:18:58 +00004363 drm_gem_object_unreference(&obj->base);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004364unlock:
Chris Wilson3ef94da2009-09-14 16:50:29 +01004365 mutex_unlock(&dev->struct_mutex);
Chris Wilson1d7cfea2010-10-17 09:45:41 +01004366 return ret;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004367}
4368
Chris Wilson37e680a2012-06-07 15:38:42 +01004369void i915_gem_object_init(struct drm_i915_gem_object *obj,
4370 const struct drm_i915_gem_object_ops *ops)
Chris Wilson0327d6b2012-08-11 15:41:06 +01004371{
Ben Widawsky35c20a62013-05-31 11:28:48 -07004372 INIT_LIST_HEAD(&obj->global_list);
Chris Wilson0327d6b2012-08-11 15:41:06 +01004373 INIT_LIST_HEAD(&obj->ring_list);
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02004374 INIT_LIST_HEAD(&obj->obj_exec_link);
Ben Widawsky2f633152013-07-17 12:19:03 -07004375 INIT_LIST_HEAD(&obj->vma_list);
Chris Wilson0327d6b2012-08-11 15:41:06 +01004376
Chris Wilson37e680a2012-06-07 15:38:42 +01004377 obj->ops = ops;
4378
Chris Wilson0327d6b2012-08-11 15:41:06 +01004379 obj->fence_reg = I915_FENCE_REG_NONE;
4380 obj->madv = I915_MADV_WILLNEED;
Chris Wilson0327d6b2012-08-11 15:41:06 +01004381
4382 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4383}
4384
Chris Wilson37e680a2012-06-07 15:38:42 +01004385static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4386 .get_pages = i915_gem_object_get_pages_gtt,
4387 .put_pages = i915_gem_object_put_pages_gtt,
4388};
4389
Chris Wilson05394f32010-11-08 19:18:58 +00004390struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4391 size_t size)
Daniel Vetterac52bc52010-04-09 19:05:06 +00004392{
Daniel Vetterc397b902010-04-09 19:05:07 +00004393 struct drm_i915_gem_object *obj;
Hugh Dickins5949eac2011-06-27 16:18:18 -07004394 struct address_space *mapping;
Daniel Vetter1a240d42012-11-29 22:18:51 +01004395 gfp_t mask;
Daniel Vetterc397b902010-04-09 19:05:07 +00004396
Chris Wilson42dcedd2012-11-15 11:32:30 +00004397 obj = i915_gem_object_alloc(dev);
Daniel Vetterc397b902010-04-09 19:05:07 +00004398 if (obj == NULL)
4399 return NULL;
4400
4401 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
Chris Wilson42dcedd2012-11-15 11:32:30 +00004402 i915_gem_object_free(obj);
Daniel Vetterc397b902010-04-09 19:05:07 +00004403 return NULL;
4404 }
4405
Chris Wilsonbed1ea92012-05-24 20:48:12 +01004406 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4407 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4408 /* 965gm cannot relocate objects above 4GiB. */
4409 mask &= ~__GFP_HIGHMEM;
4410 mask |= __GFP_DMA32;
4411 }
4412
Al Viro496ad9a2013-01-23 17:07:38 -05004413 mapping = file_inode(obj->base.filp)->i_mapping;
Chris Wilsonbed1ea92012-05-24 20:48:12 +01004414 mapping_set_gfp_mask(mapping, mask);
Hugh Dickins5949eac2011-06-27 16:18:18 -07004415
Chris Wilson37e680a2012-06-07 15:38:42 +01004416 i915_gem_object_init(obj, &i915_gem_object_ops);
Chris Wilson73aa8082010-09-30 11:46:12 +01004417
Daniel Vetterc397b902010-04-09 19:05:07 +00004418 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4419 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4420
Eugeni Dodonov3d29b842012-01-17 14:43:53 -02004421 if (HAS_LLC(dev)) {
4422 /* On some devices, we can have the GPU use the LLC (the CPU
Eric Anholta1871112011-03-29 16:59:55 -07004423 * cache) for about a 10% performance improvement
4424 * compared to uncached. Graphics requests other than
4425 * display scanout are coherent with the CPU in
4426 * accessing this cache. This means in this mode we
4427 * don't need to clflush on the CPU side, and on the
4428 * GPU side we only need to flush internal caches to
4429 * get data visible to the CPU.
4430 *
4431 * However, we maintain the display planes as UC, and so
4432 * need to rebind when first used as such.
4433 */
4434 obj->cache_level = I915_CACHE_LLC;
4435 } else
4436 obj->cache_level = I915_CACHE_NONE;
4437
Daniel Vetterd861e332013-07-24 23:25:03 +02004438 trace_i915_gem_object_create(obj);
4439
Chris Wilson05394f32010-11-08 19:18:58 +00004440 return obj;
Daniel Vetterac52bc52010-04-09 19:05:06 +00004441}
4442
Chris Wilson340fbd82014-05-22 09:16:52 +01004443static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4444{
4445 /* If we are the last user of the backing storage (be it shmemfs
4446 * pages or stolen etc), we know that the pages are going to be
4447 * immediately released. In this case, we can then skip copying
4448 * back the contents from the GPU.
4449 */
4450
4451 if (obj->madv != I915_MADV_WILLNEED)
4452 return false;
4453
4454 if (obj->base.filp == NULL)
4455 return true;
4456
4457 /* At first glance, this looks racy, but then again so would be
4458 * userspace racing mmap against close. However, the first external
4459 * reference to the filp can only be obtained through the
4460 * i915_gem_mmap_ioctl() which safeguards us against the user
4461 * acquiring such a reference whilst we are in the middle of
4462 * freeing the object.
4463 */
4464 return atomic_long_read(&obj->base.filp->f_count) == 1;
4465}
4466
Chris Wilson1488fc02012-04-24 15:47:31 +01004467void i915_gem_free_object(struct drm_gem_object *gem_obj)
Chris Wilsonbe726152010-07-23 23:18:50 +01004468{
Chris Wilson1488fc02012-04-24 15:47:31 +01004469 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00004470 struct drm_device *dev = obj->base.dev;
Jani Nikula3e31c6c2014-03-31 14:27:16 +03004471 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004472 struct i915_vma *vma, *next;
Chris Wilsonbe726152010-07-23 23:18:50 +01004473
Paulo Zanonif65c9162013-11-27 18:20:34 -02004474 intel_runtime_pm_get(dev_priv);
4475
Chris Wilson26e12f892011-03-20 11:20:19 +00004476 trace_i915_gem_object_destroy(obj);
4477
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004478 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08004479 int ret;
4480
4481 vma->pin_count = 0;
4482 ret = i915_vma_unbind(vma);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004483 if (WARN_ON(ret == -ERESTARTSYS)) {
4484 bool was_interruptible;
Chris Wilson1488fc02012-04-24 15:47:31 +01004485
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004486 was_interruptible = dev_priv->mm.interruptible;
4487 dev_priv->mm.interruptible = false;
Chris Wilson1488fc02012-04-24 15:47:31 +01004488
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004489 WARN_ON(i915_vma_unbind(vma));
Chris Wilson1488fc02012-04-24 15:47:31 +01004490
Ben Widawsky07fe0b12013-07-31 17:00:10 -07004491 dev_priv->mm.interruptible = was_interruptible;
4492 }
Chris Wilson1488fc02012-04-24 15:47:31 +01004493 }
4494
Ben Widawsky1d64ae72013-05-31 14:46:20 -07004495 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4496 * before progressing. */
4497 if (obj->stolen)
4498 i915_gem_object_unpin_pages(obj);
4499
Daniel Vettera071fa02014-06-18 23:28:09 +02004500 WARN_ON(obj->frontbuffer_bits);
4501
Daniel Vetter656bfa32014-11-20 09:26:30 +01004502 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4503 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4504 obj->tiling_mode != I915_TILING_NONE)
4505 i915_gem_object_unpin_pages(obj);
4506
Ben Widawsky401c29f2013-05-31 11:28:47 -07004507 if (WARN_ON(obj->pages_pin_count))
4508 obj->pages_pin_count = 0;
Chris Wilson340fbd82014-05-22 09:16:52 +01004509 if (discard_backing_storage(obj))
Chris Wilson55372522014-03-25 13:23:06 +00004510 obj->madv = I915_MADV_DONTNEED;
Chris Wilson37e680a2012-06-07 15:38:42 +01004511 i915_gem_object_put_pages(obj);
Chris Wilsond8cb5082012-08-11 15:41:03 +01004512 i915_gem_object_free_mmap_offset(obj);
Chris Wilsonbe726152010-07-23 23:18:50 +01004513
Chris Wilson9da3da62012-06-01 15:20:22 +01004514 BUG_ON(obj->pages);
4515
Chris Wilson2f745ad2012-09-04 21:02:58 +01004516 if (obj->base.import_attach)
4517 drm_prime_gem_destroy(&obj->base, NULL);
Chris Wilsonbe726152010-07-23 23:18:50 +01004518
Chris Wilson5cc9ed42014-05-16 14:22:37 +01004519 if (obj->ops->release)
4520 obj->ops->release(obj);
4521
Chris Wilson05394f32010-11-08 19:18:58 +00004522 drm_gem_object_release(&obj->base);
4523 i915_gem_info_remove_obj(dev_priv, obj->base.size);
Chris Wilsonbe726152010-07-23 23:18:50 +01004524
Chris Wilson05394f32010-11-08 19:18:58 +00004525 kfree(obj->bit_17);
Chris Wilson42dcedd2012-11-15 11:32:30 +00004526 i915_gem_object_free(obj);
Paulo Zanonif65c9162013-11-27 18:20:34 -02004527
4528 intel_runtime_pm_put(dev_priv);
Chris Wilsonbe726152010-07-23 23:18:50 +01004529}
4530
Daniel Vettere656a6c2013-08-14 14:14:04 +02004531struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
Ben Widawsky2f633152013-07-17 12:19:03 -07004532 struct i915_address_space *vm)
4533{
Daniel Vettere656a6c2013-08-14 14:14:04 +02004534 struct i915_vma *vma;
4535 list_for_each_entry(vma, &obj->vma_list, vma_link)
4536 if (vma->vm == vm)
4537 return vma;
4538
4539 return NULL;
4540}
4541
Ben Widawsky2f633152013-07-17 12:19:03 -07004542void i915_gem_vma_destroy(struct i915_vma *vma)
4543{
Michel Thierryb9d06dd2014-08-06 15:04:44 +02004544 struct i915_address_space *vm = NULL;
Ben Widawsky2f633152013-07-17 12:19:03 -07004545 WARN_ON(vma->node.allocated);
Chris Wilsonaaa05662013-08-20 12:56:40 +01004546
4547 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4548 if (!list_empty(&vma->exec_list))
4549 return;
4550
Michel Thierryb9d06dd2014-08-06 15:04:44 +02004551 vm = vma->vm;
Michel Thierryb9d06dd2014-08-06 15:04:44 +02004552
Daniel Vetter841cd772014-08-06 15:04:48 +02004553 if (!i915_is_ggtt(vm))
4554 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
Michel Thierryb9d06dd2014-08-06 15:04:44 +02004555
Ben Widawsky8b9c2b92013-07-31 17:00:16 -07004556 list_del(&vma->vma_link);
Daniel Vetterb93dab62013-08-26 11:23:47 +02004557
Ben Widawsky2f633152013-07-17 12:19:03 -07004558 kfree(vma);
4559}
4560
Chris Wilsone3efda42014-04-09 09:19:41 +01004561static void
4562i915_gem_stop_ringbuffers(struct drm_device *dev)
4563{
4564 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01004565 struct intel_engine_cs *ring;
Chris Wilsone3efda42014-04-09 09:19:41 +01004566 int i;
4567
4568 for_each_ring(ring, dev_priv, i)
Oscar Mateoa83014d2014-07-24 17:04:21 +01004569 dev_priv->gt.stop_ring(ring);
Chris Wilsone3efda42014-04-09 09:19:41 +01004570}
4571
Jesse Barnes5669fca2009-02-17 15:13:31 -08004572int
Chris Wilson45c5f202013-10-16 11:50:01 +01004573i915_gem_suspend(struct drm_device *dev)
Eric Anholt673a3942008-07-30 12:06:12 -07004574{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03004575 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson45c5f202013-10-16 11:50:01 +01004576 int ret = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07004577
Chris Wilson45c5f202013-10-16 11:50:01 +01004578 mutex_lock(&dev->struct_mutex);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07004579 ret = i915_gpu_idle(dev);
Chris Wilsonf7403342013-09-13 23:57:04 +01004580 if (ret)
Chris Wilson45c5f202013-10-16 11:50:01 +01004581 goto err;
Chris Wilsonf7403342013-09-13 23:57:04 +01004582
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07004583 i915_gem_retire_requests(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004584
Chris Wilson29105cc2010-01-07 10:39:13 +00004585 /* Under UMS, be paranoid and evict. */
Chris Wilsona39d7ef2012-04-24 18:22:52 +01004586 if (!drm_core_check_feature(dev, DRIVER_MODESET))
Chris Wilson6c085a72012-08-20 11:40:46 +02004587 i915_gem_evict_everything(dev);
Chris Wilson29105cc2010-01-07 10:39:13 +00004588
Chris Wilsone3efda42014-04-09 09:19:41 +01004589 i915_gem_stop_ringbuffers(dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01004590 mutex_unlock(&dev->struct_mutex);
4591
4592 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
Chris Wilson29105cc2010-01-07 10:39:13 +00004593 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
Deepak S274fa1c2014-08-05 07:51:20 -07004594 flush_delayed_work(&dev_priv->mm.idle_work);
Chris Wilson29105cc2010-01-07 10:39:13 +00004595
Chris Wilsonbdcf1202014-11-25 11:56:33 +00004596 /* Assert that we sucessfully flushed all the work and
4597 * reset the GPU back to its idle, low power state.
4598 */
4599 WARN_ON(dev_priv->mm.busy);
4600
Eric Anholt673a3942008-07-30 12:06:12 -07004601 return 0;
Chris Wilson45c5f202013-10-16 11:50:01 +01004602
4603err:
4604 mutex_unlock(&dev->struct_mutex);
4605 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004606}
4607
Oscar Mateoa4872ba2014-05-22 14:13:33 +01004608int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
Ben Widawskyb9524a12012-05-25 16:56:24 -07004609{
Ben Widawskyc3787e22013-09-17 21:12:44 -07004610 struct drm_device *dev = ring->dev;
Jani Nikula3e31c6c2014-03-31 14:27:16 +03004611 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07004612 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4613 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
Ben Widawskyc3787e22013-09-17 21:12:44 -07004614 int i, ret;
Ben Widawskyb9524a12012-05-25 16:56:24 -07004615
Ben Widawsky040d2ba2013-09-19 11:01:40 -07004616 if (!HAS_L3_DPF(dev) || !remap_info)
Ben Widawskyc3787e22013-09-17 21:12:44 -07004617 return 0;
Ben Widawskyb9524a12012-05-25 16:56:24 -07004618
Ben Widawskyc3787e22013-09-17 21:12:44 -07004619 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4620 if (ret)
4621 return ret;
Ben Widawskyb9524a12012-05-25 16:56:24 -07004622
Ben Widawskyc3787e22013-09-17 21:12:44 -07004623 /*
4624 * Note: We do not worry about the concurrent register cacheline hang
4625 * here because no other code should access these registers other than
4626 * at initialization time.
4627 */
Ben Widawskyb9524a12012-05-25 16:56:24 -07004628 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
Ben Widawskyc3787e22013-09-17 21:12:44 -07004629 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4630 intel_ring_emit(ring, reg_base + i);
4631 intel_ring_emit(ring, remap_info[i/4]);
Ben Widawskyb9524a12012-05-25 16:56:24 -07004632 }
4633
Ben Widawskyc3787e22013-09-17 21:12:44 -07004634 intel_ring_advance(ring);
Ben Widawskyb9524a12012-05-25 16:56:24 -07004635
Ben Widawskyc3787e22013-09-17 21:12:44 -07004636 return ret;
Ben Widawskyb9524a12012-05-25 16:56:24 -07004637}
4638
Daniel Vetterf691e2f2012-02-02 09:58:12 +01004639void i915_gem_init_swizzling(struct drm_device *dev)
4640{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03004641 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf691e2f2012-02-02 09:58:12 +01004642
Daniel Vetter11782b02012-01-31 16:47:55 +01004643 if (INTEL_INFO(dev)->gen < 5 ||
Daniel Vetterf691e2f2012-02-02 09:58:12 +01004644 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4645 return;
4646
4647 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4648 DISP_TILE_SURFACE_SWIZZLING);
4649
Daniel Vetter11782b02012-01-31 16:47:55 +01004650 if (IS_GEN5(dev))
4651 return;
4652
Daniel Vetterf691e2f2012-02-02 09:58:12 +01004653 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4654 if (IS_GEN6(dev))
Daniel Vetter6b26c862012-04-24 14:04:12 +02004655 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
Ben Widawsky8782e262012-12-18 10:31:23 -08004656 else if (IS_GEN7(dev))
Daniel Vetter6b26c862012-04-24 14:04:12 +02004657 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
Ben Widawsky31a53362013-11-02 21:07:04 -07004658 else if (IS_GEN8(dev))
4659 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
Ben Widawsky8782e262012-12-18 10:31:23 -08004660 else
4661 BUG();
Daniel Vetterf691e2f2012-02-02 09:58:12 +01004662}
Daniel Vettere21af882012-02-09 20:53:27 +01004663
Chris Wilson67b1b572012-07-05 23:49:40 +01004664static bool
4665intel_enable_blt(struct drm_device *dev)
4666{
4667 if (!HAS_BLT(dev))
4668 return false;
4669
4670 /* The blitter was dysfunctional on early prototypes */
4671 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4672 DRM_INFO("BLT not supported on this pre-production hardware;"
4673 " graphics performance will be degraded.\n");
4674 return false;
4675 }
4676
4677 return true;
4678}
4679
Ville Syrjälä81e7f202014-08-15 01:21:55 +03004680static void init_unused_ring(struct drm_device *dev, u32 base)
4681{
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4683
4684 I915_WRITE(RING_CTL(base), 0);
4685 I915_WRITE(RING_HEAD(base), 0);
4686 I915_WRITE(RING_TAIL(base), 0);
4687 I915_WRITE(RING_START(base), 0);
4688}
4689
4690static void init_unused_rings(struct drm_device *dev)
4691{
4692 if (IS_I830(dev)) {
4693 init_unused_ring(dev, PRB1_BASE);
4694 init_unused_ring(dev, SRB0_BASE);
4695 init_unused_ring(dev, SRB1_BASE);
4696 init_unused_ring(dev, SRB2_BASE);
4697 init_unused_ring(dev, SRB3_BASE);
4698 } else if (IS_GEN2(dev)) {
4699 init_unused_ring(dev, SRB0_BASE);
4700 init_unused_ring(dev, SRB1_BASE);
4701 } else if (IS_GEN3(dev)) {
4702 init_unused_ring(dev, PRB1_BASE);
4703 init_unused_ring(dev, PRB2_BASE);
4704 }
4705}
4706
Oscar Mateoa83014d2014-07-24 17:04:21 +01004707int i915_gem_init_rings(struct drm_device *dev)
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004708{
Ben Widawsky4fc7c972013-02-08 11:49:24 -08004709 struct drm_i915_private *dev_priv = dev->dev_private;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004710 int ret;
Chris Wilson68f95ba2010-05-27 13:18:22 +01004711
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08004712 ret = intel_init_render_ring_buffer(dev);
Chris Wilson68f95ba2010-05-27 13:18:22 +01004713 if (ret)
Chris Wilsonb6913e42010-11-12 10:46:37 +00004714 return ret;
Chris Wilson68f95ba2010-05-27 13:18:22 +01004715
4716 if (HAS_BSD(dev)) {
Xiang, Haihao5c1143b2010-09-16 10:43:11 +08004717 ret = intel_init_bsd_ring_buffer(dev);
Chris Wilson68f95ba2010-05-27 13:18:22 +01004718 if (ret)
4719 goto cleanup_render_ring;
Zou Nan haid1b851f2010-05-21 09:08:57 +08004720 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004721
Chris Wilson67b1b572012-07-05 23:49:40 +01004722 if (intel_enable_blt(dev)) {
Chris Wilson549f7362010-10-19 11:19:32 +01004723 ret = intel_init_blt_ring_buffer(dev);
4724 if (ret)
4725 goto cleanup_bsd_ring;
4726 }
4727
Ben Widawsky9a8a2212013-05-28 19:22:23 -07004728 if (HAS_VEBOX(dev)) {
4729 ret = intel_init_vebox_ring_buffer(dev);
4730 if (ret)
4731 goto cleanup_blt_ring;
4732 }
4733
Zhao Yakui845f74a2014-04-17 10:37:37 +08004734 if (HAS_BSD2(dev)) {
4735 ret = intel_init_bsd2_ring_buffer(dev);
4736 if (ret)
4737 goto cleanup_vebox_ring;
4738 }
Ben Widawsky9a8a2212013-05-28 19:22:23 -07004739
Mika Kuoppala99433932013-01-22 14:12:17 +02004740 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4741 if (ret)
Zhao Yakui845f74a2014-04-17 10:37:37 +08004742 goto cleanup_bsd2_ring;
Ben Widawsky4fc7c972013-02-08 11:49:24 -08004743
4744 return 0;
4745
Zhao Yakui845f74a2014-04-17 10:37:37 +08004746cleanup_bsd2_ring:
4747 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
Ben Widawsky9a8a2212013-05-28 19:22:23 -07004748cleanup_vebox_ring:
4749 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
Ben Widawsky4fc7c972013-02-08 11:49:24 -08004750cleanup_blt_ring:
4751 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4752cleanup_bsd_ring:
4753 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4754cleanup_render_ring:
4755 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4756
4757 return ret;
4758}
4759
4760int
4761i915_gem_init_hw(struct drm_device *dev)
4762{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03004763 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter35a57ff2014-11-20 00:33:07 +01004764 struct intel_engine_cs *ring;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07004765 int ret, i;
Ben Widawsky4fc7c972013-02-08 11:49:24 -08004766
4767 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4768 return -EIO;
4769
Ben Widawsky59124502013-07-04 11:02:05 -07004770 if (dev_priv->ellc_size)
Ben Widawsky05e21cc2013-07-04 11:02:04 -07004771 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
Ben Widawsky4fc7c972013-02-08 11:49:24 -08004772
Ville Syrjälä0bf21342013-11-29 14:56:12 +02004773 if (IS_HASWELL(dev))
4774 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4775 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
Rodrigo Vivi94353732013-08-28 16:45:46 -03004776
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07004777 if (HAS_PCH_NOP(dev)) {
Daniel Vetter6ba844b2014-01-22 23:39:30 +01004778 if (IS_IVYBRIDGE(dev)) {
4779 u32 temp = I915_READ(GEN7_MSG_CTL);
4780 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4781 I915_WRITE(GEN7_MSG_CTL, temp);
4782 } else if (INTEL_INFO(dev)->gen >= 7) {
4783 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4784 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4785 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4786 }
Ben Widawsky88a2b2a2013-04-05 13:12:43 -07004787 }
4788
Ben Widawsky4fc7c972013-02-08 11:49:24 -08004789 i915_gem_init_swizzling(dev);
4790
Daniel Vetterd5abdfd2014-11-20 09:45:19 +01004791 /*
4792 * At least 830 can leave some of the unused rings
4793 * "active" (ie. head != tail) after resume which
4794 * will prevent c3 entry. Makes sure all unused rings
4795 * are totally idle.
4796 */
4797 init_unused_rings(dev);
4798
Daniel Vetter35a57ff2014-11-20 00:33:07 +01004799 for_each_ring(ring, dev_priv, i) {
4800 ret = ring->init_hw(ring);
4801 if (ret)
4802 return ret;
4803 }
Mika Kuoppala99433932013-01-22 14:12:17 +02004804
Ben Widawskyc3787e22013-09-17 21:12:44 -07004805 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4806 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4807
Ben Widawsky254f9652012-06-04 14:42:42 -07004808 /*
Ben Widawsky2fa48d82013-12-06 14:11:04 -08004809 * XXX: Contexts should only be initialized once. Doing a switch to the
4810 * default context switch however is something we'd like to do after
4811 * reset or thaw (the latter may not actually be necessary for HW, but
4812 * goes with our code better). Context switching requires rings (for
4813 * the do_switch), but before enabling PPGTT. So don't move this.
Ben Widawsky254f9652012-06-04 14:42:42 -07004814 */
Ben Widawsky2fa48d82013-12-06 14:11:04 -08004815 ret = i915_gem_context_enable(dev_priv);
Chris Wilson60990322014-04-09 09:19:42 +01004816 if (ret && ret != -EIO) {
Ben Widawsky2fa48d82013-12-06 14:11:04 -08004817 DRM_ERROR("Context enable failed %d\n", ret);
Chris Wilson60990322014-04-09 09:19:42 +01004818 i915_gem_cleanup_ringbuffer(dev);
Daniel Vetter82460d92014-08-06 20:19:53 +02004819
4820 return ret;
4821 }
4822
4823 ret = i915_ppgtt_init_hw(dev);
4824 if (ret && ret != -EIO) {
4825 DRM_ERROR("PPGTT enable failed %d\n", ret);
4826 i915_gem_cleanup_ringbuffer(dev);
Ben Widawskyb7c36d22013-04-08 18:43:56 -07004827 }
Daniel Vettere21af882012-02-09 20:53:27 +01004828
Ben Widawsky2fa48d82013-12-06 14:11:04 -08004829 return ret;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004830}
4831
Chris Wilson1070a422012-04-24 15:47:41 +01004832int i915_gem_init(struct drm_device *dev)
4833{
4834 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson1070a422012-04-24 15:47:41 +01004835 int ret;
4836
Oscar Mateo127f1002014-07-24 17:04:11 +01004837 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4838 i915.enable_execlists);
4839
Chris Wilson1070a422012-04-24 15:47:41 +01004840 mutex_lock(&dev->struct_mutex);
Jesse Barnesd62b4892013-03-08 10:45:53 -08004841
4842 if (IS_VALLEYVIEW(dev)) {
4843 /* VLVA0 (potential hack), BIOS isn't actually waking us */
Imre Deak981a5ae2014-04-14 20:24:22 +03004844 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4845 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4846 VLV_GTLC_ALLOWWAKEACK), 10))
Jesse Barnesd62b4892013-03-08 10:45:53 -08004847 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4848 }
4849
Oscar Mateoa83014d2014-07-24 17:04:21 +01004850 if (!i915.enable_execlists) {
4851 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4852 dev_priv->gt.init_rings = i915_gem_init_rings;
4853 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4854 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
Oscar Mateo454afeb2014-07-24 17:04:22 +01004855 } else {
4856 dev_priv->gt.do_execbuf = intel_execlists_submission;
4857 dev_priv->gt.init_rings = intel_logical_rings_init;
4858 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4859 dev_priv->gt.stop_ring = intel_logical_ring_stop;
Oscar Mateoa83014d2014-07-24 17:04:21 +01004860 }
4861
Daniel Vetter6c5566a2014-08-06 15:04:50 +02004862 ret = i915_gem_init_userptr(dev);
4863 if (ret) {
4864 mutex_unlock(&dev->struct_mutex);
4865 return ret;
4866 }
4867
Ben Widawskyd7e50082012-12-18 10:31:25 -08004868 i915_gem_init_global_gtt(dev);
Jesse Barnesd62b4892013-03-08 10:45:53 -08004869
Ben Widawsky2fa48d82013-12-06 14:11:04 -08004870 ret = i915_gem_context_init(dev);
Mika Kuoppalae3848692014-01-31 17:14:02 +02004871 if (ret) {
4872 mutex_unlock(&dev->struct_mutex);
Ben Widawsky2fa48d82013-12-06 14:11:04 -08004873 return ret;
Mika Kuoppalae3848692014-01-31 17:14:02 +02004874 }
Ben Widawsky2fa48d82013-12-06 14:11:04 -08004875
Daniel Vetter35a57ff2014-11-20 00:33:07 +01004876 ret = dev_priv->gt.init_rings(dev);
4877 if (ret)
4878 return ret;
4879
Chris Wilson1070a422012-04-24 15:47:41 +01004880 ret = i915_gem_init_hw(dev);
Chris Wilson60990322014-04-09 09:19:42 +01004881 if (ret == -EIO) {
4882 /* Allow ring initialisation to fail by marking the GPU as
4883 * wedged. But we only want to do this where the GPU is angry,
4884 * for all other failure, such as an allocation failure, bail.
4885 */
4886 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4887 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4888 ret = 0;
Chris Wilson1070a422012-04-24 15:47:41 +01004889 }
Chris Wilson60990322014-04-09 09:19:42 +01004890 mutex_unlock(&dev->struct_mutex);
Chris Wilson1070a422012-04-24 15:47:41 +01004891
Chris Wilson60990322014-04-09 09:19:42 +01004892 return ret;
Chris Wilson1070a422012-04-24 15:47:41 +01004893}
4894
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004895void
4896i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4897{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03004898 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01004899 struct intel_engine_cs *ring;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00004900 int i;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004901
Chris Wilsonb4519512012-05-11 14:29:30 +01004902 for_each_ring(ring, dev_priv, i)
Oscar Mateoa83014d2014-07-24 17:04:21 +01004903 dev_priv->gt.cleanup_ring(ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004904}
4905
Chris Wilson64193402010-10-24 12:38:05 +01004906static void
Oscar Mateoa4872ba2014-05-22 14:13:33 +01004907init_ring_lists(struct intel_engine_cs *ring)
Chris Wilson64193402010-10-24 12:38:05 +01004908{
4909 INIT_LIST_HEAD(&ring->active_list);
4910 INIT_LIST_HEAD(&ring->request_list);
Chris Wilson64193402010-10-24 12:38:05 +01004911}
4912
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08004913void i915_init_vm(struct drm_i915_private *dev_priv,
4914 struct i915_address_space *vm)
Ben Widawskyfc8c0672013-07-31 16:59:54 -07004915{
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08004916 if (!i915_is_ggtt(vm))
4917 drm_mm_init(&vm->mm, vm->start, vm->total);
Ben Widawskyfc8c0672013-07-31 16:59:54 -07004918 vm->dev = dev_priv->dev;
4919 INIT_LIST_HEAD(&vm->active_list);
4920 INIT_LIST_HEAD(&vm->inactive_list);
4921 INIT_LIST_HEAD(&vm->global_link);
Chris Wilsonf72d21e2014-01-09 22:57:22 +00004922 list_add_tail(&vm->global_link, &dev_priv->vm_list);
Ben Widawskyfc8c0672013-07-31 16:59:54 -07004923}
4924
Eric Anholt673a3942008-07-30 12:06:12 -07004925void
4926i915_gem_load(struct drm_device *dev)
4927{
Jani Nikula3e31c6c2014-03-31 14:27:16 +03004928 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson42dcedd2012-11-15 11:32:30 +00004929 int i;
4930
4931 dev_priv->slab =
4932 kmem_cache_create("i915_gem_object",
4933 sizeof(struct drm_i915_gem_object), 0,
4934 SLAB_HWCACHE_ALIGN,
4935 NULL);
Eric Anholt673a3942008-07-30 12:06:12 -07004936
Ben Widawskyfc8c0672013-07-31 16:59:54 -07004937 INIT_LIST_HEAD(&dev_priv->vm_list);
4938 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4939
Ben Widawskya33afea2013-09-17 21:12:45 -07004940 INIT_LIST_HEAD(&dev_priv->context_list);
Chris Wilson6c085a72012-08-20 11:40:46 +02004941 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4942 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07004943 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00004944 for (i = 0; i < I915_NUM_RINGS; i++)
4945 init_ring_lists(&dev_priv->ring[i]);
Daniel Vetter4b9de732011-10-09 21:52:02 +02004946 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
Daniel Vetter007cc8a2010-04-28 11:02:31 +02004947 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004948 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4949 i915_gem_retire_work_handler);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01004950 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4951 i915_gem_idle_work_handler);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01004952 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
Chris Wilson31169712009-09-14 16:50:28 +01004953
Dave Airlie94400122010-07-20 13:15:31 +10004954 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
Ville Syrjälädbb42742014-02-25 15:13:41 +02004955 if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
Daniel Vetter50743292012-04-26 22:02:54 +02004956 I915_WRITE(MI_ARB_STATE,
4957 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
Dave Airlie94400122010-07-20 13:15:31 +10004958 }
4959
Chris Wilson72bfa192010-12-19 11:42:05 +00004960 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4961
Jesse Barnesde151cf2008-11-12 10:03:55 -08004962 /* Old X drivers will take 0-2 for front, back, depth buffers */
Eric Anholtb397c832010-01-26 09:43:10 -08004963 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4964 dev_priv->fence_reg_start = 3;
Jesse Barnesde151cf2008-11-12 10:03:55 -08004965
Ville Syrjälä42b5aea2013-04-09 13:02:47 +03004966 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4967 dev_priv->num_fence_regs = 32;
4968 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08004969 dev_priv->num_fence_regs = 16;
4970 else
4971 dev_priv->num_fence_regs = 8;
4972
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004973 /* Initialize fence registers to zero */
Chris Wilson19b2dbd2013-06-12 10:15:12 +01004974 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4975 i915_gem_restore_fences(dev);
Eric Anholt10ed13e2011-05-06 13:53:49 -07004976
Eric Anholt673a3942008-07-30 12:06:12 -07004977 i915_gem_detect_bit_6_swizzle(dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004978 init_waitqueue_head(&dev_priv->pending_flip_queue);
Chris Wilson17250b72010-10-28 12:51:39 +01004979
Chris Wilsonce453d82011-02-21 14:43:56 +00004980 dev_priv->mm.interruptible = true;
4981
Chris Wilsonceabbba52014-03-25 13:23:04 +00004982 dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4983 dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4984 dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4985 register_shrinker(&dev_priv->mm.shrinker);
Chris Wilson2cfcd322014-05-20 08:28:43 +01004986
4987 dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4988 register_oom_notifier(&dev_priv->mm.oom_notifier);
Daniel Vetterf99d7062014-06-19 16:01:59 +02004989
4990 mutex_init(&dev_priv->fb_tracking.lock);
Eric Anholt673a3942008-07-30 12:06:12 -07004991}
Dave Airlie71acb5e2008-12-30 20:31:46 +10004992
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004993void i915_gem_release(struct drm_device *dev, struct drm_file *file)
Eric Anholtb9624422009-06-03 07:27:35 +00004994{
Chris Wilsonf787a5f2010-09-24 16:02:42 +01004995 struct drm_i915_file_private *file_priv = file->driver_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00004996
Chris Wilsonb29c19b2013-09-25 17:34:56 +01004997 cancel_delayed_work_sync(&file_priv->mm.idle_work);
4998
Eric Anholtb9624422009-06-03 07:27:35 +00004999 /* Clean up our request list when the client is going away, so that
5000 * later retire_requests won't dereference our soon-to-be-gone
5001 * file_priv.
5002 */
Chris Wilson1c255952010-09-26 11:03:27 +01005003 spin_lock(&file_priv->mm.lock);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01005004 while (!list_empty(&file_priv->mm.request_list)) {
5005 struct drm_i915_gem_request *request;
5006
5007 request = list_first_entry(&file_priv->mm.request_list,
5008 struct drm_i915_gem_request,
5009 client_list);
5010 list_del(&request->client_list);
5011 request->file_priv = NULL;
5012 }
Chris Wilson1c255952010-09-26 11:03:27 +01005013 spin_unlock(&file_priv->mm.lock);
Eric Anholtb9624422009-06-03 07:27:35 +00005014}
Chris Wilson31169712009-09-14 16:50:28 +01005015
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005016static void
5017i915_gem_file_idle_work_handler(struct work_struct *work)
5018{
5019 struct drm_i915_file_private *file_priv =
5020 container_of(work, typeof(*file_priv), mm.idle_work.work);
5021
5022 atomic_set(&file_priv->rps_wait_boost, false);
5023}
5024
5025int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5026{
5027 struct drm_i915_file_private *file_priv;
Ben Widawskye422b882013-12-06 14:10:58 -08005028 int ret;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005029
5030 DRM_DEBUG_DRIVER("\n");
5031
5032 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5033 if (!file_priv)
5034 return -ENOMEM;
5035
5036 file->driver_priv = file_priv;
5037 file_priv->dev_priv = dev->dev_private;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +02005038 file_priv->file = file;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005039
5040 spin_lock_init(&file_priv->mm.lock);
5041 INIT_LIST_HEAD(&file_priv->mm.request_list);
5042 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5043 i915_gem_file_idle_work_handler);
5044
Ben Widawskye422b882013-12-06 14:10:58 -08005045 ret = i915_gem_context_open(dev, file);
5046 if (ret)
5047 kfree(file_priv);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005048
Ben Widawskye422b882013-12-06 14:10:58 -08005049 return ret;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01005050}
5051
Daniel Vetterb680c372014-09-19 18:27:27 +02005052/**
5053 * i915_gem_track_fb - update frontbuffer tracking
5054 * old: current GEM buffer for the frontbuffer slots
5055 * new: new GEM buffer for the frontbuffer slots
5056 * frontbuffer_bits: bitmask of frontbuffer slots
5057 *
5058 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5059 * from @old and setting them in @new. Both @old and @new can be NULL.
5060 */
Daniel Vettera071fa02014-06-18 23:28:09 +02005061void i915_gem_track_fb(struct drm_i915_gem_object *old,
5062 struct drm_i915_gem_object *new,
5063 unsigned frontbuffer_bits)
5064{
5065 if (old) {
5066 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5067 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5068 old->frontbuffer_bits &= ~frontbuffer_bits;
5069 }
5070
5071 if (new) {
5072 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5073 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5074 new->frontbuffer_bits |= frontbuffer_bits;
5075 }
5076}
5077
Chris Wilson57745062012-11-21 13:04:04 +00005078static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5079{
5080 if (!mutex_is_locked(mutex))
5081 return false;
5082
5083#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5084 return mutex->owner == task;
5085#else
5086 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5087 return false;
5088#endif
5089}
5090
Chris Wilsonb453c4d2014-03-25 13:23:05 +00005091static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5092{
5093 if (!mutex_trylock(&dev->struct_mutex)) {
5094 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5095 return false;
5096
5097 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5098 return false;
5099
5100 *unlock = false;
5101 } else
5102 *unlock = true;
5103
5104 return true;
5105}
5106
Chris Wilsonceabbba52014-03-25 13:23:04 +00005107static int num_vma_bound(struct drm_i915_gem_object *obj)
5108{
5109 struct i915_vma *vma;
5110 int count = 0;
5111
5112 list_for_each_entry(vma, &obj->vma_list, vma_link)
5113 if (drm_mm_node_allocated(&vma->node))
5114 count++;
5115
5116 return count;
5117}
5118
Dave Chinner7dc19d52013-08-28 10:18:11 +10005119static unsigned long
Chris Wilsonceabbba52014-03-25 13:23:04 +00005120i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
Chris Wilson31169712009-09-14 16:50:28 +01005121{
Chris Wilson17250b72010-10-28 12:51:39 +01005122 struct drm_i915_private *dev_priv =
Chris Wilsonceabbba52014-03-25 13:23:04 +00005123 container_of(shrinker, struct drm_i915_private, mm.shrinker);
Chris Wilson17250b72010-10-28 12:51:39 +01005124 struct drm_device *dev = dev_priv->dev;
Chris Wilson6c085a72012-08-20 11:40:46 +02005125 struct drm_i915_gem_object *obj;
Dave Chinner7dc19d52013-08-28 10:18:11 +10005126 unsigned long count;
Chris Wilsonb453c4d2014-03-25 13:23:05 +00005127 bool unlock;
Chris Wilson17250b72010-10-28 12:51:39 +01005128
Chris Wilsonb453c4d2014-03-25 13:23:05 +00005129 if (!i915_gem_shrinker_lock(dev, &unlock))
5130 return 0;
Chris Wilson31169712009-09-14 16:50:28 +01005131
Dave Chinner7dc19d52013-08-28 10:18:11 +10005132 count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -07005133 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
Chris Wilsona5570172012-09-04 21:02:54 +01005134 if (obj->pages_pin_count == 0)
Dave Chinner7dc19d52013-08-28 10:18:11 +10005135 count += obj->base.size >> PAGE_SHIFT;
Ben Widawskyfcb4a572013-07-31 16:59:57 -07005136
5137 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Chris Wilsonceabbba52014-03-25 13:23:04 +00005138 if (!i915_gem_obj_is_pinned(obj) &&
5139 obj->pages_pin_count == num_vma_bound(obj))
Dave Chinner7dc19d52013-08-28 10:18:11 +10005140 count += obj->base.size >> PAGE_SHIFT;
Ben Widawskyfcb4a572013-07-31 16:59:57 -07005141 }
Chris Wilson31169712009-09-14 16:50:28 +01005142
Chris Wilson57745062012-11-21 13:04:04 +00005143 if (unlock)
5144 mutex_unlock(&dev->struct_mutex);
Chris Wilsond9973b42013-10-04 10:33:00 +01005145
Dave Chinner7dc19d52013-08-28 10:18:11 +10005146 return count;
Chris Wilson31169712009-09-14 16:50:28 +01005147}
Ben Widawskya70a3142013-07-31 16:59:56 -07005148
5149/* All the new VM stuff */
5150unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5151 struct i915_address_space *vm)
5152{
5153 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5154 struct i915_vma *vma;
5155
Daniel Vetter896ab1a2014-08-06 15:04:51 +02005156 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
Ben Widawskya70a3142013-07-31 16:59:56 -07005157
Ben Widawskya70a3142013-07-31 16:59:56 -07005158 list_for_each_entry(vma, &o->vma_list, vma_link) {
5159 if (vma->vm == vm)
5160 return vma->node.start;
5161
5162 }
Daniel Vetterf25748ea2014-06-17 22:34:38 +02005163 WARN(1, "%s vma for this object not found.\n",
5164 i915_is_ggtt(vm) ? "global" : "ppgtt");
Ben Widawskya70a3142013-07-31 16:59:56 -07005165 return -1;
5166}
5167
5168bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5169 struct i915_address_space *vm)
5170{
5171 struct i915_vma *vma;
5172
5173 list_for_each_entry(vma, &o->vma_list, vma_link)
Ben Widawsky8b9c2b92013-07-31 17:00:16 -07005174 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
Ben Widawskya70a3142013-07-31 16:59:56 -07005175 return true;
5176
5177 return false;
5178}
5179
5180bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5181{
Chris Wilson5a1d5eb2013-09-10 11:27:37 +01005182 struct i915_vma *vma;
Ben Widawskya70a3142013-07-31 16:59:56 -07005183
Chris Wilson5a1d5eb2013-09-10 11:27:37 +01005184 list_for_each_entry(vma, &o->vma_list, vma_link)
5185 if (drm_mm_node_allocated(&vma->node))
Ben Widawskya70a3142013-07-31 16:59:56 -07005186 return true;
5187
5188 return false;
5189}
5190
5191unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5192 struct i915_address_space *vm)
5193{
5194 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5195 struct i915_vma *vma;
5196
Daniel Vetter896ab1a2014-08-06 15:04:51 +02005197 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
Ben Widawskya70a3142013-07-31 16:59:56 -07005198
5199 BUG_ON(list_empty(&o->vma_list));
5200
5201 list_for_each_entry(vma, &o->vma_list, vma_link)
5202 if (vma->vm == vm)
5203 return vma->node.size;
5204
5205 return 0;
5206}
5207
Dave Chinner7dc19d52013-08-28 10:18:11 +10005208static unsigned long
Chris Wilsonceabbba52014-03-25 13:23:04 +00005209i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
Dave Chinner7dc19d52013-08-28 10:18:11 +10005210{
5211 struct drm_i915_private *dev_priv =
Chris Wilsonceabbba52014-03-25 13:23:04 +00005212 container_of(shrinker, struct drm_i915_private, mm.shrinker);
Dave Chinner7dc19d52013-08-28 10:18:11 +10005213 struct drm_device *dev = dev_priv->dev;
Dave Chinner7dc19d52013-08-28 10:18:11 +10005214 unsigned long freed;
Chris Wilsonb453c4d2014-03-25 13:23:05 +00005215 bool unlock;
Dave Chinner7dc19d52013-08-28 10:18:11 +10005216
Chris Wilsonb453c4d2014-03-25 13:23:05 +00005217 if (!i915_gem_shrinker_lock(dev, &unlock))
5218 return SHRINK_STOP;
Dave Chinner7dc19d52013-08-28 10:18:11 +10005219
Chris Wilson21ab4e72014-09-09 11:16:08 +01005220 freed = i915_gem_shrink(dev_priv,
5221 sc->nr_to_scan,
5222 I915_SHRINK_BOUND |
5223 I915_SHRINK_UNBOUND |
5224 I915_SHRINK_PURGEABLE);
Chris Wilsond9973b42013-10-04 10:33:00 +01005225 if (freed < sc->nr_to_scan)
Chris Wilson21ab4e72014-09-09 11:16:08 +01005226 freed += i915_gem_shrink(dev_priv,
5227 sc->nr_to_scan - freed,
5228 I915_SHRINK_BOUND |
5229 I915_SHRINK_UNBOUND);
Dave Chinner7dc19d52013-08-28 10:18:11 +10005230 if (unlock)
5231 mutex_unlock(&dev->struct_mutex);
Chris Wilsond9973b42013-10-04 10:33:00 +01005232
Dave Chinner7dc19d52013-08-28 10:18:11 +10005233 return freed;
5234}
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07005235
Chris Wilson2cfcd322014-05-20 08:28:43 +01005236static int
5237i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5238{
5239 struct drm_i915_private *dev_priv =
5240 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5241 struct drm_device *dev = dev_priv->dev;
5242 struct drm_i915_gem_object *obj;
5243 unsigned long timeout = msecs_to_jiffies(5000) + 1;
Chris Wilson005445c2014-10-08 11:25:16 +01005244 unsigned long pinned, bound, unbound, freed_pages;
Chris Wilson2cfcd322014-05-20 08:28:43 +01005245 bool was_interruptible;
5246 bool unlock;
5247
Chris Wilsona1db2fa2014-07-11 11:28:00 +01005248 while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
Chris Wilson2cfcd322014-05-20 08:28:43 +01005249 schedule_timeout_killable(1);
Chris Wilsona1db2fa2014-07-11 11:28:00 +01005250 if (fatal_signal_pending(current))
5251 return NOTIFY_DONE;
5252 }
Chris Wilson2cfcd322014-05-20 08:28:43 +01005253 if (timeout == 0) {
5254 pr_err("Unable to purge GPU memory due lock contention.\n");
5255 return NOTIFY_DONE;
5256 }
5257
5258 was_interruptible = dev_priv->mm.interruptible;
5259 dev_priv->mm.interruptible = false;
5260
Chris Wilson005445c2014-10-08 11:25:16 +01005261 freed_pages = i915_gem_shrink_all(dev_priv);
Chris Wilson2cfcd322014-05-20 08:28:43 +01005262
5263 dev_priv->mm.interruptible = was_interruptible;
5264
5265 /* Because we may be allocating inside our own driver, we cannot
5266 * assert that there are no objects with pinned pages that are not
5267 * being pointed to by hardware.
5268 */
5269 unbound = bound = pinned = 0;
5270 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5271 if (!obj->base.filp) /* not backed by a freeable object */
5272 continue;
5273
5274 if (obj->pages_pin_count)
5275 pinned += obj->base.size;
5276 else
5277 unbound += obj->base.size;
5278 }
5279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5280 if (!obj->base.filp)
5281 continue;
5282
5283 if (obj->pages_pin_count)
5284 pinned += obj->base.size;
5285 else
5286 bound += obj->base.size;
5287 }
5288
5289 if (unlock)
5290 mutex_unlock(&dev->struct_mutex);
5291
Chris Wilsonbb9059d2014-10-08 11:25:17 +01005292 if (freed_pages || unbound || bound)
5293 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5294 freed_pages << PAGE_SHIFT, pinned);
Chris Wilson2cfcd322014-05-20 08:28:43 +01005295 if (unbound || bound)
5296 pr_err("%lu and %lu bytes still available in the "
5297 "bound and unbound GPU page lists.\n",
5298 bound, unbound);
5299
Chris Wilson005445c2014-10-08 11:25:16 +01005300 *(unsigned long *)ptr += freed_pages;
Chris Wilson2cfcd322014-05-20 08:28:43 +01005301 return NOTIFY_DONE;
5302}
5303
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07005304struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5305{
5306 struct i915_vma *vma;
5307
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07005308 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
Daniel Vetter5dc383b2014-08-06 15:04:49 +02005309 if (vma->vm != i915_obj_to_ggtt(obj))
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07005310 return NULL;
5311
5312 return vma;
5313}