Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
Zeng Zhaoxiu | a4d8a0f | 2015-12-06 18:26:30 +0800 | [diff] [blame] | 30 | #include <linux/log2.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 34 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 36 | |
Chris Wilson | a044246 | 2016-04-29 09:07:05 +0100 | [diff] [blame] | 37 | /* Rough estimate of the typical request size, performing a flush, |
| 38 | * set-context and then emitting the batch. |
| 39 | */ |
| 40 | #define LEGACY_REQUEST_SIZE 200 |
| 41 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 42 | int __intel_ring_space(int head, int tail, int size) |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 43 | { |
Dave Gordon | 4f54741 | 2014-11-27 11:22:48 +0000 | [diff] [blame] | 44 | int space = head - tail; |
| 45 | if (space <= 0) |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 46 | space += size; |
Dave Gordon | 4f54741 | 2014-11-27 11:22:48 +0000 | [diff] [blame] | 47 | return space - I915_RING_FREE_SPACE; |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 48 | } |
| 49 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 50 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
| 51 | { |
| 52 | if (ringbuf->last_retired_head != -1) { |
| 53 | ringbuf->head = ringbuf->last_retired_head; |
| 54 | ringbuf->last_retired_head = -1; |
| 55 | } |
| 56 | |
| 57 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, |
| 58 | ringbuf->tail, ringbuf->size); |
| 59 | } |
| 60 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 61 | bool intel_engine_stopped(struct intel_engine_cs *engine) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 62 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 63 | struct drm_i915_private *dev_priv = engine->i915; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 64 | return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine); |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 65 | } |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 66 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 67 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 68 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 69 | struct intel_ringbuffer *ringbuf = engine->buffer; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 70 | ringbuf->tail &= ringbuf->size - 1; |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 71 | if (intel_engine_stopped(engine)) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 72 | return; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 73 | engine->write_tail(engine, ringbuf->tail); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 74 | } |
| 75 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 76 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 77 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 78 | u32 invalidate_domains, |
| 79 | u32 flush_domains) |
| 80 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 81 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 82 | u32 cmd; |
| 83 | int ret; |
| 84 | |
| 85 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 86 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 87 | cmd |= MI_NO_WRITE_FLUSH; |
| 88 | |
| 89 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 90 | cmd |= MI_READ_FLUSH; |
| 91 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 92 | ret = intel_ring_begin(req, 2); |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 93 | if (ret) |
| 94 | return ret; |
| 95 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 96 | intel_ring_emit(engine, cmd); |
| 97 | intel_ring_emit(engine, MI_NOOP); |
| 98 | intel_ring_advance(engine); |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 99 | |
| 100 | return 0; |
| 101 | } |
| 102 | |
| 103 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 104 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 105 | u32 invalidate_domains, |
| 106 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 107 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 108 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 109 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 110 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 111 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 112 | /* |
| 113 | * read/write caches: |
| 114 | * |
| 115 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 116 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 117 | * also flushed at 2d versus 3d pipeline switches. |
| 118 | * |
| 119 | * read-only caches: |
| 120 | * |
| 121 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 122 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 123 | * |
| 124 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 125 | * |
| 126 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 127 | * invalidated when MI_EXE_FLUSH is set. |
| 128 | * |
| 129 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 130 | * invalidated with every MI_FLUSH. |
| 131 | * |
| 132 | * TLBs: |
| 133 | * |
| 134 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 135 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 136 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 137 | * are flushed at any MI_FLUSH. |
| 138 | */ |
| 139 | |
| 140 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 141 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 142 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 143 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 144 | cmd |= MI_EXE_FLUSH; |
| 145 | |
| 146 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 147 | (IS_G4X(req->i915) || IS_GEN5(req->i915))) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 148 | cmd |= MI_INVALIDATE_ISP; |
| 149 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 150 | ret = intel_ring_begin(req, 2); |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 151 | if (ret) |
| 152 | return ret; |
| 153 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 154 | intel_ring_emit(engine, cmd); |
| 155 | intel_ring_emit(engine, MI_NOOP); |
| 156 | intel_ring_advance(engine); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 157 | |
| 158 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 159 | } |
| 160 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 161 | /** |
| 162 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 163 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 164 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 165 | * |
| 166 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 167 | * produced by non-pipelined state commands), software needs to first |
| 168 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 169 | * 0. |
| 170 | * |
| 171 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 172 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 173 | * |
| 174 | * And the workaround for these two requires this workaround first: |
| 175 | * |
| 176 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 177 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 178 | * flushes. |
| 179 | * |
| 180 | * And this last workaround is tricky because of the requirements on |
| 181 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 182 | * volume 2 part 1: |
| 183 | * |
| 184 | * "1 of the following must also be set: |
| 185 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 186 | * - Depth Cache Flush Enable ([0] of DW1) |
| 187 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 188 | * - Depth Stall ([13] of DW1) |
| 189 | * - Post-Sync Operation ([13] of DW1) |
| 190 | * - Notify Enable ([8] of DW1)" |
| 191 | * |
| 192 | * The cache flushes require the workaround flush that triggered this |
| 193 | * one, so we can't use it. Depth stall would trigger the same. |
| 194 | * Post-sync nonzero is what triggered this second workaround, so we |
| 195 | * can't use that one either. Notify enable is IRQs, which aren't |
| 196 | * really our business. That leaves only stall at scoreboard. |
| 197 | */ |
| 198 | static int |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 199 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 200 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 201 | struct intel_engine_cs *engine = req->engine; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 202 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 203 | int ret; |
| 204 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 205 | ret = intel_ring_begin(req, 6); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 206 | if (ret) |
| 207 | return ret; |
| 208 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 209 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
| 210 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 211 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 212 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 213 | intel_ring_emit(engine, 0); /* low dword */ |
| 214 | intel_ring_emit(engine, 0); /* high dword */ |
| 215 | intel_ring_emit(engine, MI_NOOP); |
| 216 | intel_ring_advance(engine); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 217 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 218 | ret = intel_ring_begin(req, 6); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 219 | if (ret) |
| 220 | return ret; |
| 221 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 222 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
| 223 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); |
| 224 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 225 | intel_ring_emit(engine, 0); |
| 226 | intel_ring_emit(engine, 0); |
| 227 | intel_ring_emit(engine, MI_NOOP); |
| 228 | intel_ring_advance(engine); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 234 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
| 235 | u32 invalidate_domains, u32 flush_domains) |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 236 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 237 | struct intel_engine_cs *engine = req->engine; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 238 | u32 flags = 0; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 239 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 240 | int ret; |
| 241 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 242 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 243 | ret = intel_emit_post_sync_nonzero_flush(req); |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 244 | if (ret) |
| 245 | return ret; |
| 246 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 247 | /* Just flush everything. Experiments have shown that reducing the |
| 248 | * number of bits based on the write domains has little performance |
| 249 | * impact. |
| 250 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 251 | if (flush_domains) { |
| 252 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 253 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 254 | /* |
| 255 | * Ensure that any following seqno writes only happen |
| 256 | * when the render cache is indeed flushed. |
| 257 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 258 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 259 | } |
| 260 | if (invalidate_domains) { |
| 261 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 262 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 263 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 264 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 265 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 266 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 267 | /* |
| 268 | * TLB invalidate requires a post-sync write. |
| 269 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 270 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 271 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 272 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 273 | ret = intel_ring_begin(req, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 274 | if (ret) |
| 275 | return ret; |
| 276 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 277 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
| 278 | intel_ring_emit(engine, flags); |
| 279 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
| 280 | intel_ring_emit(engine, 0); |
| 281 | intel_ring_advance(engine); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 286 | static int |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 287 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 288 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 289 | struct intel_engine_cs *engine = req->engine; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 290 | int ret; |
| 291 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 292 | ret = intel_ring_begin(req, 4); |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 293 | if (ret) |
| 294 | return ret; |
| 295 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 296 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
| 297 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 298 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 299 | intel_ring_emit(engine, 0); |
| 300 | intel_ring_emit(engine, 0); |
| 301 | intel_ring_advance(engine); |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 307 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 308 | u32 invalidate_domains, u32 flush_domains) |
| 309 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 310 | struct intel_engine_cs *engine = req->engine; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 311 | u32 flags = 0; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 312 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 313 | int ret; |
| 314 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 315 | /* |
| 316 | * Ensure that any following seqno writes only happen when the render |
| 317 | * cache is indeed flushed. |
| 318 | * |
| 319 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 320 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 321 | * don't try to be clever and just set it unconditionally. |
| 322 | */ |
| 323 | flags |= PIPE_CONTROL_CS_STALL; |
| 324 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 325 | /* Just flush everything. Experiments have shown that reducing the |
| 326 | * number of bits based on the write domains has little performance |
| 327 | * impact. |
| 328 | */ |
| 329 | if (flush_domains) { |
| 330 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 331 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Francisco Jerez | 965fd60 | 2016-01-13 18:59:39 -0800 | [diff] [blame] | 332 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
Chris Wilson | 40a2448 | 2015-08-21 16:08:41 +0100 | [diff] [blame] | 333 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 334 | } |
| 335 | if (invalidate_domains) { |
| 336 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 337 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 338 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 339 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 340 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 341 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
Chris Wilson | 148b83d | 2014-12-16 08:44:31 +0000 | [diff] [blame] | 342 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 343 | /* |
| 344 | * TLB invalidate requires a post-sync write. |
| 345 | */ |
| 346 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 347 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 348 | |
Chris Wilson | add284a | 2014-12-16 08:44:32 +0000 | [diff] [blame] | 349 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
| 350 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 351 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 352 | * set before a pipe_control command that has the state cache |
| 353 | * invalidate bit set. */ |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 354 | gen7_render_ring_cs_stall_wa(req); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 355 | } |
| 356 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 357 | ret = intel_ring_begin(req, 4); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 358 | if (ret) |
| 359 | return ret; |
| 360 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 361 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
| 362 | intel_ring_emit(engine, flags); |
| 363 | intel_ring_emit(engine, scratch_addr); |
| 364 | intel_ring_emit(engine, 0); |
| 365 | intel_ring_advance(engine); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 366 | |
| 367 | return 0; |
| 368 | } |
| 369 | |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 370 | static int |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 371 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 372 | u32 flags, u32 scratch_addr) |
| 373 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 374 | struct intel_engine_cs *engine = req->engine; |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 375 | int ret; |
| 376 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 377 | ret = intel_ring_begin(req, 6); |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 378 | if (ret) |
| 379 | return ret; |
| 380 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 381 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
| 382 | intel_ring_emit(engine, flags); |
| 383 | intel_ring_emit(engine, scratch_addr); |
| 384 | intel_ring_emit(engine, 0); |
| 385 | intel_ring_emit(engine, 0); |
| 386 | intel_ring_emit(engine, 0); |
| 387 | intel_ring_advance(engine); |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 393 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 394 | u32 invalidate_domains, u32 flush_domains) |
| 395 | { |
| 396 | u32 flags = 0; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 397 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 398 | int ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 399 | |
| 400 | flags |= PIPE_CONTROL_CS_STALL; |
| 401 | |
| 402 | if (flush_domains) { |
| 403 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 404 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Francisco Jerez | 965fd60 | 2016-01-13 18:59:39 -0800 | [diff] [blame] | 405 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
Chris Wilson | 40a2448 | 2015-08-21 16:08:41 +0100 | [diff] [blame] | 406 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 407 | } |
| 408 | if (invalidate_domains) { |
| 409 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 410 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 411 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 412 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 413 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 414 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 415 | flags |= PIPE_CONTROL_QW_WRITE; |
| 416 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 417 | |
| 418 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 419 | ret = gen8_emit_pipe_control(req, |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 420 | PIPE_CONTROL_CS_STALL | |
| 421 | PIPE_CONTROL_STALL_AT_SCOREBOARD, |
| 422 | 0); |
| 423 | if (ret) |
| 424 | return ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 425 | } |
| 426 | |
John Harrison | f2cf1fc | 2015-05-29 17:43:58 +0100 | [diff] [blame] | 427 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 428 | } |
| 429 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 430 | static void ring_write_tail(struct intel_engine_cs *engine, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 431 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 432 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 433 | struct drm_i915_private *dev_priv = engine->i915; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 434 | I915_WRITE_TAIL(engine, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 435 | } |
| 436 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 437 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 438 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 439 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 440 | u64 acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 441 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 442 | if (INTEL_GEN(dev_priv) >= 8) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 443 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
| 444 | RING_ACTHD_UDW(engine->mmio_base)); |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 445 | else if (INTEL_GEN(dev_priv) >= 4) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 446 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 447 | else |
| 448 | acthd = I915_READ(ACTHD); |
| 449 | |
| 450 | return acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 451 | } |
| 452 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 453 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 454 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 455 | struct drm_i915_private *dev_priv = engine->i915; |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 456 | u32 addr; |
| 457 | |
| 458 | addr = dev_priv->status_page_dmah->busaddr; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 459 | if (INTEL_GEN(dev_priv) >= 4) |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 460 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 461 | I915_WRITE(HWS_PGA, addr); |
| 462 | } |
| 463 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 464 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 465 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 466 | struct drm_i915_private *dev_priv = engine->i915; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 467 | i915_reg_t mmio; |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 468 | |
| 469 | /* The ring status page addresses are no longer next to the rest of |
| 470 | * the ring registers as of gen7. |
| 471 | */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 472 | if (IS_GEN7(dev_priv)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 473 | switch (engine->id) { |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 474 | case RCS: |
| 475 | mmio = RENDER_HWS_PGA_GEN7; |
| 476 | break; |
| 477 | case BCS: |
| 478 | mmio = BLT_HWS_PGA_GEN7; |
| 479 | break; |
| 480 | /* |
| 481 | * VCS2 actually doesn't exist on Gen7. Only shut up |
| 482 | * gcc switch check warning |
| 483 | */ |
| 484 | case VCS2: |
| 485 | case VCS: |
| 486 | mmio = BSD_HWS_PGA_GEN7; |
| 487 | break; |
| 488 | case VECS: |
| 489 | mmio = VEBOX_HWS_PGA_GEN7; |
| 490 | break; |
| 491 | } |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 492 | } else if (IS_GEN6(dev_priv)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 493 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 494 | } else { |
| 495 | /* XXX: gen8 returns to sanity */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 496 | mmio = RING_HWS_PGA(engine->mmio_base); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 497 | } |
| 498 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 499 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 500 | POSTING_READ(mmio); |
| 501 | |
| 502 | /* |
| 503 | * Flush the TLB for this page |
| 504 | * |
| 505 | * FIXME: These two bits have disappeared on gen8, so a question |
| 506 | * arises: do we still need this and if so how should we go about |
| 507 | * invalidating the TLB? |
| 508 | */ |
Tvrtko Ursulin | ac657f6 | 2016-05-10 10:57:08 +0100 | [diff] [blame] | 509 | if (IS_GEN(dev_priv, 6, 7)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 510 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 511 | |
| 512 | /* ring should be idle before issuing a sync flush*/ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 513 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 514 | |
| 515 | I915_WRITE(reg, |
| 516 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 517 | INSTPM_SYNC_FLUSH)); |
Chris Wilson | 25ab57f | 2016-06-30 15:33:29 +0100 | [diff] [blame] | 518 | if (intel_wait_for_register(dev_priv, |
| 519 | reg, INSTPM_SYNC_FLUSH, 0, |
| 520 | 1000)) |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 521 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 522 | engine->name); |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 523 | } |
| 524 | } |
| 525 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 526 | static bool stop_ring(struct intel_engine_cs *engine) |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 527 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 528 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 529 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 530 | if (!IS_GEN2(dev_priv)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 531 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
Chris Wilson | 3d808eb | 2016-06-30 15:33:30 +0100 | [diff] [blame] | 532 | if (intel_wait_for_register(dev_priv, |
| 533 | RING_MI_MODE(engine->mmio_base), |
| 534 | MODE_IDLE, |
| 535 | MODE_IDLE, |
| 536 | 1000)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 537 | DRM_ERROR("%s : timed out trying to stop ring\n", |
| 538 | engine->name); |
Chris Wilson | 9bec9b1 | 2014-08-11 09:21:35 +0100 | [diff] [blame] | 539 | /* Sometimes we observe that the idle flag is not |
| 540 | * set even though the ring is empty. So double |
| 541 | * check before giving up. |
| 542 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 543 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
Chris Wilson | 9bec9b1 | 2014-08-11 09:21:35 +0100 | [diff] [blame] | 544 | return false; |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 545 | } |
| 546 | } |
| 547 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 548 | I915_WRITE_CTL(engine, 0); |
| 549 | I915_WRITE_HEAD(engine, 0); |
| 550 | engine->write_tail(engine, 0); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 551 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 552 | if (!IS_GEN2(dev_priv)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 553 | (void)I915_READ_CTL(engine); |
| 554 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 555 | } |
| 556 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 557 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 558 | } |
| 559 | |
Tomas Elf | fc0768c | 2016-03-21 16:26:59 +0000 | [diff] [blame] | 560 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
| 561 | { |
| 562 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); |
| 563 | } |
| 564 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 565 | static int init_ring_common(struct intel_engine_cs *engine) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 566 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 567 | struct drm_i915_private *dev_priv = engine->i915; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 568 | struct intel_ringbuffer *ringbuf = engine->buffer; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 569 | struct drm_i915_gem_object *obj = ringbuf->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 570 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 571 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 572 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 573 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 574 | if (!stop_ring(engine)) { |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 575 | /* G45 ring initialization often fails to reset head to zero */ |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 576 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 577 | "ctl %08x head %08x tail %08x start %08x\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 578 | engine->name, |
| 579 | I915_READ_CTL(engine), |
| 580 | I915_READ_HEAD(engine), |
| 581 | I915_READ_TAIL(engine), |
| 582 | I915_READ_START(engine)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 583 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 584 | if (!stop_ring(engine)) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 585 | DRM_ERROR("failed to set %s head to zero " |
| 586 | "ctl %08x head %08x tail %08x start %08x\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 587 | engine->name, |
| 588 | I915_READ_CTL(engine), |
| 589 | I915_READ_HEAD(engine), |
| 590 | I915_READ_TAIL(engine), |
| 591 | I915_READ_START(engine)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 592 | ret = -EIO; |
| 593 | goto out; |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 594 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 595 | } |
| 596 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 597 | if (I915_NEED_GFX_HWS(dev_priv)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 598 | intel_ring_setup_status_page(engine); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 599 | else |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 600 | ring_setup_phys_status_page(engine); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 601 | |
Jiri Kosina | ece4a17 | 2014-08-07 16:29:53 +0200 | [diff] [blame] | 602 | /* Enforce ordering by reading HEAD register back */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 603 | I915_READ_HEAD(engine); |
Jiri Kosina | ece4a17 | 2014-08-07 16:29:53 +0200 | [diff] [blame] | 604 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 605 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 606 | * registers with the above sequence (the readback of the HEAD registers |
| 607 | * also enforces ordering), otherwise the hw might lose the new ring |
| 608 | * register values. */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 609 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
Chris Wilson | 9546889 | 2014-08-07 15:39:54 +0100 | [diff] [blame] | 610 | |
| 611 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 612 | if (I915_READ_HEAD(engine)) |
Chris Wilson | 9546889 | 2014-08-07 15:39:54 +0100 | [diff] [blame] | 613 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 614 | engine->name, I915_READ_HEAD(engine)); |
| 615 | I915_WRITE_HEAD(engine, 0); |
| 616 | (void)I915_READ_HEAD(engine); |
Chris Wilson | 9546889 | 2014-08-07 15:39:54 +0100 | [diff] [blame] | 617 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 618 | I915_WRITE_CTL(engine, |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 619 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 620 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 621 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 622 | /* If the head is still not zero, the ring is dead */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 623 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
| 624 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && |
| 625 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 626 | DRM_ERROR("%s initialization failed " |
Chris Wilson | 48e48a0 | 2014-04-09 09:19:44 +0100 | [diff] [blame] | 627 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 628 | engine->name, |
| 629 | I915_READ_CTL(engine), |
| 630 | I915_READ_CTL(engine) & RING_VALID, |
| 631 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), |
| 632 | I915_READ_START(engine), |
| 633 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 634 | ret = -EIO; |
| 635 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 636 | } |
| 637 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 638 | ringbuf->last_retired_head = -1; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 639 | ringbuf->head = I915_READ_HEAD(engine); |
| 640 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 641 | intel_ring_update_space(ringbuf); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 642 | |
Tomas Elf | fc0768c | 2016-03-21 16:26:59 +0000 | [diff] [blame] | 643 | intel_engine_init_hangcheck(engine); |
Chris Wilson | 50f018d | 2013-06-10 11:20:19 +0100 | [diff] [blame] | 644 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 645 | out: |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 646 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 647 | |
| 648 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 649 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 650 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 651 | void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 652 | intel_fini_pipe_control(struct intel_engine_cs *engine) |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 653 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 654 | if (engine->scratch.obj == NULL) |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 655 | return; |
| 656 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 657 | if (INTEL_GEN(engine->i915) >= 5) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 658 | kunmap(sg_page(engine->scratch.obj->pages->sgl)); |
| 659 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 660 | } |
| 661 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 662 | drm_gem_object_unreference(&engine->scratch.obj->base); |
| 663 | engine->scratch.obj = NULL; |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 664 | } |
| 665 | |
| 666 | int |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 667 | intel_init_pipe_control(struct intel_engine_cs *engine) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 668 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 669 | int ret; |
| 670 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 671 | WARN_ON(engine->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 672 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 673 | engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 674 | if (IS_ERR(engine->scratch.obj)) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 675 | DRM_ERROR("Failed to allocate seqno page\n"); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 676 | ret = PTR_ERR(engine->scratch.obj); |
| 677 | engine->scratch.obj = NULL; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 678 | goto err; |
| 679 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 680 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 681 | ret = i915_gem_object_set_cache_level(engine->scratch.obj, |
| 682 | I915_CACHE_LLC); |
Daniel Vetter | a9cc726 | 2014-02-14 14:01:13 +0100 | [diff] [blame] | 683 | if (ret) |
| 684 | goto err_unref; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 685 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 686 | ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 687 | if (ret) |
| 688 | goto err_unref; |
| 689 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 690 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj); |
| 691 | engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl)); |
| 692 | if (engine->scratch.cpu_page == NULL) { |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 693 | ret = -ENOMEM; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 694 | goto err_unpin; |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 695 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 696 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 697 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 698 | engine->name, engine->scratch.gtt_offset); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 699 | return 0; |
| 700 | |
| 701 | err_unpin: |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 702 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 703 | err_unref: |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 704 | drm_gem_object_unreference(&engine->scratch.obj->base); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 705 | err: |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 706 | return ret; |
| 707 | } |
| 708 | |
John Harrison | e2be4fa | 2015-05-29 17:43:54 +0100 | [diff] [blame] | 709 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 710 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 711 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 712 | struct i915_workarounds *w = &req->i915->workarounds; |
| 713 | int ret, i; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 714 | |
Francisco Jerez | 0223580 | 2015-10-07 14:44:01 +0300 | [diff] [blame] | 715 | if (w->count == 0) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 716 | return 0; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 717 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 718 | engine->gpu_caches_dirty = true; |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 719 | ret = intel_ring_flush_all_caches(req); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 720 | if (ret) |
| 721 | return ret; |
| 722 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 723 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 724 | if (ret) |
| 725 | return ret; |
| 726 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 727 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 728 | for (i = 0; i < w->count; i++) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 729 | intel_ring_emit_reg(engine, w->reg[i].addr); |
| 730 | intel_ring_emit(engine, w->reg[i].value); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 731 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 732 | intel_ring_emit(engine, MI_NOOP); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 733 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 734 | intel_ring_advance(engine); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 735 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 736 | engine->gpu_caches_dirty = true; |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 737 | ret = intel_ring_flush_all_caches(req); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 738 | if (ret) |
| 739 | return ret; |
| 740 | |
| 741 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
| 742 | |
| 743 | return 0; |
| 744 | } |
| 745 | |
John Harrison | 8753181 | 2015-05-29 17:43:44 +0100 | [diff] [blame] | 746 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 747 | { |
| 748 | int ret; |
| 749 | |
John Harrison | e2be4fa | 2015-05-29 17:43:54 +0100 | [diff] [blame] | 750 | ret = intel_ring_workarounds_emit(req); |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 751 | if (ret != 0) |
| 752 | return ret; |
| 753 | |
John Harrison | be01363 | 2015-05-29 17:43:45 +0100 | [diff] [blame] | 754 | ret = i915_gem_render_state_init(req); |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 755 | if (ret) |
Chris Wilson | e26e1b9 | 2016-01-29 16:49:05 +0000 | [diff] [blame] | 756 | return ret; |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 757 | |
Chris Wilson | e26e1b9 | 2016-01-29 16:49:05 +0000 | [diff] [blame] | 758 | return 0; |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 759 | } |
| 760 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 761 | static int wa_add(struct drm_i915_private *dev_priv, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 762 | i915_reg_t addr, |
| 763 | const u32 mask, const u32 val) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 764 | { |
| 765 | const u32 idx = dev_priv->workarounds.count; |
| 766 | |
| 767 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) |
| 768 | return -ENOSPC; |
| 769 | |
| 770 | dev_priv->workarounds.reg[idx].addr = addr; |
| 771 | dev_priv->workarounds.reg[idx].value = val; |
| 772 | dev_priv->workarounds.reg[idx].mask = mask; |
| 773 | |
| 774 | dev_priv->workarounds.count++; |
| 775 | |
| 776 | return 0; |
| 777 | } |
| 778 | |
Mika Kuoppala | ca5a0fb | 2015-08-11 15:44:31 +0100 | [diff] [blame] | 779 | #define WA_REG(addr, mask, val) do { \ |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 780 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 781 | if (r) \ |
| 782 | return r; \ |
Mika Kuoppala | ca5a0fb | 2015-08-11 15:44:31 +0100 | [diff] [blame] | 783 | } while (0) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 784 | |
| 785 | #define WA_SET_BIT_MASKED(addr, mask) \ |
Damien Lespiau | 2645934 | 2014-12-08 17:35:38 +0000 | [diff] [blame] | 786 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 787 | |
| 788 | #define WA_CLR_BIT_MASKED(addr, mask) \ |
Damien Lespiau | 2645934 | 2014-12-08 17:35:38 +0000 | [diff] [blame] | 789 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 790 | |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 791 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 792 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 793 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 794 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
| 795 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 796 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 797 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 798 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 799 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
| 800 | i915_reg_t reg) |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 801 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 802 | struct drm_i915_private *dev_priv = engine->i915; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 803 | struct i915_workarounds *wa = &dev_priv->workarounds; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 804 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 805 | |
| 806 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) |
| 807 | return -EINVAL; |
| 808 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 809 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 810 | i915_mmio_reg_offset(reg)); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 811 | wa->hw_whitelist_count[engine->id]++; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 812 | |
| 813 | return 0; |
| 814 | } |
| 815 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 816 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 817 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 818 | struct drm_i915_private *dev_priv = engine->i915; |
Arun Siluvery | 68c6198 | 2015-09-25 17:40:38 +0100 | [diff] [blame] | 819 | |
| 820 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 821 | |
Arun Siluvery | 717d84d | 2015-09-25 17:40:39 +0100 | [diff] [blame] | 822 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
| 823 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); |
| 824 | |
Arun Siluvery | d058119 | 2015-09-25 17:40:40 +0100 | [diff] [blame] | 825 | /* WaDisablePartialInstShootdown:bdw,chv */ |
| 826 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 827 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
| 828 | |
Arun Siluvery | a340af5 | 2015-09-25 17:40:45 +0100 | [diff] [blame] | 829 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 830 | * workaround for for a possible hang in the unlikely event a TLB |
| 831 | * invalidation occurs during a PSD flush. |
| 832 | */ |
| 833 | /* WaForceEnableNonCoherent:bdw,chv */ |
Arun Siluvery | 120f5d2 | 2015-09-25 17:40:46 +0100 | [diff] [blame] | 834 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
Arun Siluvery | a340af5 | 2015-09-25 17:40:45 +0100 | [diff] [blame] | 835 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
Arun Siluvery | 120f5d2 | 2015-09-25 17:40:46 +0100 | [diff] [blame] | 836 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
Arun Siluvery | a340af5 | 2015-09-25 17:40:45 +0100 | [diff] [blame] | 837 | HDC_FORCE_NON_COHERENT); |
| 838 | |
Arun Siluvery | 6def8fd | 2015-09-25 17:40:42 +0100 | [diff] [blame] | 839 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
| 840 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping |
| 841 | * polygons in the same 8x4 pixel/sample area to be processed without |
| 842 | * stalling waiting for the earlier ones to write to Hierarchical Z |
| 843 | * buffer." |
| 844 | * |
| 845 | * This optimization is off by default for BDW and CHV; turn it on. |
| 846 | */ |
| 847 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); |
| 848 | |
Arun Siluvery | 4840463 | 2015-09-25 17:40:43 +0100 | [diff] [blame] | 849 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
| 850 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); |
| 851 | |
Arun Siluvery | 7eebcde | 2015-09-25 17:40:44 +0100 | [diff] [blame] | 852 | /* |
| 853 | * BSpec recommends 8x4 when MSAA is used, |
| 854 | * however in practice 16x4 seems fastest. |
| 855 | * |
| 856 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 857 | * disable bit, which we don't touch here, but it's good |
| 858 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
| 859 | */ |
| 860 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
| 861 | GEN6_WIZ_HASHING_MASK, |
| 862 | GEN6_WIZ_HASHING_16x4); |
| 863 | |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 864 | return 0; |
| 865 | } |
| 866 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 867 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 868 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 869 | struct drm_i915_private *dev_priv = engine->i915; |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 870 | int ret; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 871 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 872 | ret = gen8_init_workarounds(engine); |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 873 | if (ret) |
| 874 | return ret; |
| 875 | |
Rodrigo Vivi | 101b376 | 2014-10-09 07:11:47 -0700 | [diff] [blame] | 876 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
Arun Siluvery | d058119 | 2015-09-25 17:40:40 +0100 | [diff] [blame] | 877 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 878 | |
Rodrigo Vivi | 101b376 | 2014-10-09 07:11:47 -0700 | [diff] [blame] | 879 | /* WaDisableDopClockGating:bdw */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 880 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
| 881 | DOP_CLOCK_GATING_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 882 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 883 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 884 | GEN8_SAMPLER_POWER_BYPASS_DIS); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 885 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 886 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
Damien Lespiau | 35cb6f3 | 2015-02-10 10:31:00 +0000 | [diff] [blame] | 887 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
| 888 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | |
Damien Lespiau | 35cb6f3 | 2015-02-10 10:31:00 +0000 | [diff] [blame] | 889 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 890 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 891 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 892 | return 0; |
| 893 | } |
| 894 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 895 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 896 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 897 | struct drm_i915_private *dev_priv = engine->i915; |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 898 | int ret; |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 899 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 900 | ret = gen8_init_workarounds(engine); |
Arun Siluvery | e9a64ad | 2015-09-25 17:40:37 +0100 | [diff] [blame] | 901 | if (ret) |
| 902 | return ret; |
| 903 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 904 | /* WaDisableThreadStallDopClockGating:chv */ |
Arun Siluvery | d058119 | 2015-09-25 17:40:40 +0100 | [diff] [blame] | 905 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 906 | |
Kenneth Graunke | d60de81 | 2015-01-10 18:02:22 -0800 | [diff] [blame] | 907 | /* Improve HiZ throughput on CHV. */ |
| 908 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); |
| 909 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 910 | return 0; |
| 911 | } |
| 912 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 913 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 914 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 915 | struct drm_i915_private *dev_priv = engine->i915; |
Arun Siluvery | e0f3fa0 | 2016-01-21 21:43:48 +0000 | [diff] [blame] | 916 | int ret; |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 917 | |
Tim Gore | a8ab5ed | 2016-06-13 12:15:01 +0100 | [diff] [blame] | 918 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
| 919 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); |
| 920 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 921 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 922 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
| 923 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); |
| 924 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 925 | /* WaDisableKillLogic:bxt,skl,kbl */ |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 926 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
| 927 | ECOCHK_DIS_TLB); |
| 928 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 929 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
| 930 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 931 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
Tim Gore | 950b2aa | 2016-03-16 16:13:46 +0000 | [diff] [blame] | 932 | FLOW_CONTROL_ENABLE | |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 933 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
| 934 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 935 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
Nick Hoath | 8424171 | 2015-02-05 10:47:20 +0000 | [diff] [blame] | 936 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 937 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); |
| 938 | |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 939 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 940 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
| 941 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
Damien Lespiau | a86eb58 | 2015-02-11 18:21:44 +0000 | [diff] [blame] | 942 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
| 943 | GEN9_DG_MIRROR_FIX_ENABLE); |
Nick Hoath | 1de4582 | 2015-02-05 10:47:19 +0000 | [diff] [blame] | 944 | |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 945 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 946 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
| 947 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
Damien Lespiau | 183c6da | 2015-02-09 19:33:11 +0000 | [diff] [blame] | 948 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
| 949 | GEN9_RHWO_OPTIMIZATION_DISABLE); |
Arun Siluvery | 9b01435 | 2015-07-14 15:01:30 +0100 | [diff] [blame] | 950 | /* |
| 951 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set |
| 952 | * but we do that in per ctx batchbuffer as there is an issue |
| 953 | * with this register not getting restored on ctx restore |
| 954 | */ |
Damien Lespiau | 183c6da | 2015-02-09 19:33:11 +0000 | [diff] [blame] | 955 | } |
| 956 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 957 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
| 958 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ |
Tim Gore | bfd8ad4 | 2016-04-19 15:45:52 +0100 | [diff] [blame] | 959 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
| 960 | GEN9_ENABLE_YV12_BUGFIX | |
| 961 | GEN9_ENABLE_GPGPU_PREEMPTION); |
Nick Hoath | cac23df | 2015-02-05 10:47:22 +0000 | [diff] [blame] | 962 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 963 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
| 964 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ |
Arun Siluvery | 6029468 | 2015-09-25 14:33:37 +0100 | [diff] [blame] | 965 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
| 966 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); |
Damien Lespiau | 9370cd9 | 2015-02-09 19:33:17 +0000 | [diff] [blame] | 967 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 968 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
Damien Lespiau | e2db707 | 2015-02-09 19:33:21 +0000 | [diff] [blame] | 969 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
| 970 | GEN9_CCS_TLB_PREFETCH_ENABLE); |
| 971 | |
Imre Deak | 5a2ae95 | 2015-05-19 15:04:59 +0300 | [diff] [blame] | 972 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 973 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || |
| 974 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
Ben Widawsky | 38a39a7 | 2015-03-11 10:54:53 +0200 | [diff] [blame] | 975 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
| 976 | PIXEL_MASK_CAMMING_DISABLE); |
| 977 | |
Mika Kuoppala | 5b0e365 | 2016-06-07 17:18:57 +0300 | [diff] [blame] | 978 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
| 979 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 980 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | |
| 981 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); |
Imre Deak | 8ea6f89 | 2015-05-19 17:05:42 +0300 | [diff] [blame] | 982 | |
Mika Kuoppala | bbaefe7 | 2016-06-07 17:18:58 +0300 | [diff] [blame] | 983 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
| 984 | * both tied to WaForceContextSaveRestoreNonCoherent |
| 985 | * in some hsds for skl. We keep the tie for all gen9. The |
| 986 | * documentation is a bit hazy and so we want to get common behaviour, |
| 987 | * even though there is no clear evidence we would need both on kbl/bxt. |
| 988 | * This area has been source of system hangs so we play it safe |
| 989 | * and mimic the skl regardless of what bspec says. |
| 990 | * |
| 991 | * Use Force Non-Coherent whenever executing a 3D context. This |
| 992 | * is a workaround for a possible hang in the unlikely event |
| 993 | * a TLB invalidation occurs during a PSD flush. |
| 994 | */ |
| 995 | |
| 996 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ |
| 997 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 998 | HDC_FORCE_NON_COHERENT); |
| 999 | |
| 1000 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ |
| 1001 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
| 1002 | BDW_DISABLE_HDC_INVALIDATION); |
| 1003 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1004 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
| 1005 | if (IS_SKYLAKE(dev_priv) || |
| 1006 | IS_KABYLAKE(dev_priv) || |
| 1007 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) |
Arun Siluvery | 8c76160 | 2015-09-08 10:31:48 +0100 | [diff] [blame] | 1008 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 1009 | GEN8_SAMPLER_POWER_BYPASS_DIS); |
Arun Siluvery | 8c76160 | 2015-09-08 10:31:48 +0100 | [diff] [blame] | 1010 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1011 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
Robert Beckett | 6b6d562 | 2015-09-08 10:31:52 +0100 | [diff] [blame] | 1012 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
| 1013 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1014 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
Arun Siluvery | 6ecf56a | 2016-01-21 21:43:54 +0000 | [diff] [blame] | 1015 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
| 1016 | GEN8_LQSC_FLUSH_COHERENT_LINES)); |
| 1017 | |
arun.siluvery@linux.intel.com | 6bb62855 | 2016-06-06 09:52:49 +0100 | [diff] [blame] | 1018 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
| 1019 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); |
| 1020 | if (ret) |
| 1021 | return ret; |
| 1022 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1023 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1024 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
Arun Siluvery | e0f3fa0 | 2016-01-21 21:43:48 +0000 | [diff] [blame] | 1025 | if (ret) |
| 1026 | return ret; |
| 1027 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1028 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1029 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
Arun Siluvery | 3669ab6 | 2016-01-21 21:43:49 +0000 | [diff] [blame] | 1030 | if (ret) |
| 1031 | return ret; |
| 1032 | |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 1033 | return 0; |
| 1034 | } |
| 1035 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1036 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1037 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1038 | struct drm_i915_private *dev_priv = engine->i915; |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 1039 | u8 vals[3] = { 0, 0, 0 }; |
| 1040 | unsigned int i; |
| 1041 | |
| 1042 | for (i = 0; i < 3; i++) { |
| 1043 | u8 ss; |
| 1044 | |
| 1045 | /* |
| 1046 | * Only consider slices where one, and only one, subslice has 7 |
| 1047 | * EUs |
| 1048 | */ |
Zeng Zhaoxiu | a4d8a0f | 2015-12-06 18:26:30 +0800 | [diff] [blame] | 1049 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 1050 | continue; |
| 1051 | |
| 1052 | /* |
| 1053 | * subslice_7eu[i] != 0 (because of the check above) and |
| 1054 | * ss_max == 4 (maximum number of subslices possible per slice) |
| 1055 | * |
| 1056 | * -> 0 <= ss <= 3; |
| 1057 | */ |
| 1058 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; |
| 1059 | vals[i] = 3 - ss; |
| 1060 | } |
| 1061 | |
| 1062 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) |
| 1063 | return 0; |
| 1064 | |
| 1065 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ |
| 1066 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
| 1067 | GEN9_IZ_HASHING_MASK(2) | |
| 1068 | GEN9_IZ_HASHING_MASK(1) | |
| 1069 | GEN9_IZ_HASHING_MASK(0), |
| 1070 | GEN9_IZ_HASHING(2, vals[2]) | |
| 1071 | GEN9_IZ_HASHING(1, vals[1]) | |
| 1072 | GEN9_IZ_HASHING(0, vals[0])); |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1073 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1074 | return 0; |
| 1075 | } |
| 1076 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1077 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1078 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1079 | struct drm_i915_private *dev_priv = engine->i915; |
Arun Siluvery | aa0011a | 2015-09-25 14:33:35 +0100 | [diff] [blame] | 1080 | int ret; |
Damien Lespiau | d0bbbc4 | 2015-02-09 19:33:16 +0000 | [diff] [blame] | 1081 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1082 | ret = gen9_init_workarounds(engine); |
Arun Siluvery | aa0011a | 2015-09-25 14:33:35 +0100 | [diff] [blame] | 1083 | if (ret) |
| 1084 | return ret; |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1085 | |
Arun Siluvery | a78536e | 2016-01-21 21:43:53 +0000 | [diff] [blame] | 1086 | /* |
| 1087 | * Actual WA is to disable percontext preemption granularity control |
| 1088 | * until D0 which is the default case so this is equivalent to |
| 1089 | * !WaDisablePerCtxtPreemptionGranularityControl:skl |
| 1090 | */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1091 | if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { |
Arun Siluvery | a78536e | 2016-01-21 21:43:53 +0000 | [diff] [blame] | 1092 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
| 1093 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); |
| 1094 | } |
| 1095 | |
Mika Kuoppala | 71dce58 | 2016-06-07 17:19:14 +0300 | [diff] [blame] | 1096 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1097 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
| 1098 | I915_WRITE(FF_SLICE_CS_CHICKEN2, |
| 1099 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); |
| 1100 | } |
| 1101 | |
| 1102 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
| 1103 | * involving this register should also be added to WA batch as required. |
| 1104 | */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1105 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1106 | /* WaDisableLSQCROPERFforOCL:skl */ |
| 1107 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | |
| 1108 | GEN8_LQSC_RO_PERF_DIS); |
| 1109 | |
| 1110 | /* WaEnableGapsTsvCreditFix:skl */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1111 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1112 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
| 1113 | GEN9_GAPS_TSV_CREDIT_DISABLE)); |
| 1114 | } |
| 1115 | |
Damien Lespiau | d0bbbc4 | 2015-02-09 19:33:16 +0000 | [diff] [blame] | 1116 | /* WaDisablePowerCompilerClockGating:skl */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1117 | if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) |
Damien Lespiau | d0bbbc4 | 2015-02-09 19:33:16 +0000 | [diff] [blame] | 1118 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
| 1119 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); |
| 1120 | |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1121 | /* WaBarrierPerformanceFixDisable:skl */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1122 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) |
Ville Syrjälä | 5b6fd12 | 2015-06-02 15:37:35 +0300 | [diff] [blame] | 1123 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 1124 | HDC_FENCE_DEST_SLM_DISABLE | |
| 1125 | HDC_BARRIER_PERFORMANCE_DISABLE); |
| 1126 | |
Mika Kuoppala | 9bd9dfb | 2015-08-06 16:51:00 +0300 | [diff] [blame] | 1127 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1128 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) |
Mika Kuoppala | 9bd9dfb | 2015-08-06 16:51:00 +0300 | [diff] [blame] | 1129 | WA_SET_BIT_MASKED( |
| 1130 | GEN7_HALF_SLICE_CHICKEN1, |
| 1131 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
Mika Kuoppala | 9bd9dfb | 2015-08-06 16:51:00 +0300 | [diff] [blame] | 1132 | |
Mika Kuoppala | eee8efb | 2016-06-07 17:18:53 +0300 | [diff] [blame] | 1133 | /* WaDisableGafsUnitClkGating:skl */ |
| 1134 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); |
| 1135 | |
Arun Siluvery | 6107497 | 2016-01-21 21:43:52 +0000 | [diff] [blame] | 1136 | /* WaDisableLSQCROPERFforOCL:skl */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1137 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
Arun Siluvery | 6107497 | 2016-01-21 21:43:52 +0000 | [diff] [blame] | 1138 | if (ret) |
| 1139 | return ret; |
| 1140 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1141 | return skl_tune_iz_hashing(engine); |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1142 | } |
| 1143 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1144 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1145 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1146 | struct drm_i915_private *dev_priv = engine->i915; |
Arun Siluvery | aa0011a | 2015-09-25 14:33:35 +0100 | [diff] [blame] | 1147 | int ret; |
Nick Hoath | dfb601e | 2015-04-10 13:12:24 +0100 | [diff] [blame] | 1148 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1149 | ret = gen9_init_workarounds(engine); |
Arun Siluvery | aa0011a | 2015-09-25 14:33:35 +0100 | [diff] [blame] | 1150 | if (ret) |
| 1151 | return ret; |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1152 | |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1153 | /* WaStoreMultiplePTEenable:bxt */ |
| 1154 | /* This is a requirement according to Hardware specification */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1155 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1156 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
| 1157 | |
| 1158 | /* WaSetClckGatingDisableMedia:bxt */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1159 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
Mika Kuoppala | 9c4cbf8 | 2015-10-12 13:20:59 +0300 | [diff] [blame] | 1160 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
| 1161 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); |
| 1162 | } |
| 1163 | |
Nick Hoath | dfb601e | 2015-04-10 13:12:24 +0100 | [diff] [blame] | 1164 | /* WaDisableThreadStallDopClockGating:bxt */ |
| 1165 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 1166 | STALL_DOP_GATING_DISABLE); |
| 1167 | |
arun.siluvery@linux.intel.com | 780f0ae | 2016-06-03 11:16:10 +0100 | [diff] [blame] | 1168 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
| 1169 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { |
| 1170 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, |
| 1171 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); |
| 1172 | } |
| 1173 | |
Nick Hoath | 983b4b9 | 2015-04-10 13:12:25 +0100 | [diff] [blame] | 1174 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1175 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
Nick Hoath | 983b4b9 | 2015-04-10 13:12:25 +0100 | [diff] [blame] | 1176 | WA_SET_BIT_MASKED( |
| 1177 | GEN7_HALF_SLICE_CHICKEN1, |
| 1178 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
| 1179 | } |
| 1180 | |
Arun Siluvery | 2c8580e | 2016-01-21 21:43:50 +0000 | [diff] [blame] | 1181 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
| 1182 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ |
| 1183 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ |
Arun Siluvery | a786d53 | 2016-01-21 21:43:51 +0000 | [diff] [blame] | 1184 | /* WaDisableLSQCROPERFforOCL:bxt */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1185 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1186 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
Arun Siluvery | 2c8580e | 2016-01-21 21:43:50 +0000 | [diff] [blame] | 1187 | if (ret) |
| 1188 | return ret; |
Arun Siluvery | a786d53 | 2016-01-21 21:43:51 +0000 | [diff] [blame] | 1189 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1190 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
Arun Siluvery | a786d53 | 2016-01-21 21:43:51 +0000 | [diff] [blame] | 1191 | if (ret) |
| 1192 | return ret; |
Arun Siluvery | 2c8580e | 2016-01-21 21:43:50 +0000 | [diff] [blame] | 1193 | } |
| 1194 | |
Tim Gore | 050fc46 | 2016-04-22 09:46:01 +0100 | [diff] [blame] | 1195 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1196 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
Imre Deak | 36579cb | 2016-05-03 15:54:20 +0300 | [diff] [blame] | 1197 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
| 1198 | L3_HIGH_PRIO_CREDITS(2)); |
Tim Gore | 050fc46 | 2016-04-22 09:46:01 +0100 | [diff] [blame] | 1199 | |
Mika Kuoppala | ad2bdb4 | 2016-06-07 17:19:07 +0300 | [diff] [blame] | 1200 | /* WaInsertDummyPushConstPs:bxt */ |
| 1201 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) |
| 1202 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
| 1203 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); |
| 1204 | |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1205 | return 0; |
| 1206 | } |
| 1207 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1208 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
| 1209 | { |
Mika Kuoppala | e587f6c | 2016-06-07 17:18:59 +0300 | [diff] [blame] | 1210 | struct drm_i915_private *dev_priv = engine->i915; |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1211 | int ret; |
| 1212 | |
| 1213 | ret = gen9_init_workarounds(engine); |
| 1214 | if (ret) |
| 1215 | return ret; |
| 1216 | |
Mika Kuoppala | e587f6c | 2016-06-07 17:18:59 +0300 | [diff] [blame] | 1217 | /* WaEnableGapsTsvCreditFix:kbl */ |
| 1218 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
| 1219 | GEN9_GAPS_TSV_CREDIT_DISABLE)); |
| 1220 | |
Mika Kuoppala | c0b730d | 2016-06-07 17:19:06 +0300 | [diff] [blame] | 1221 | /* WaDisableDynamicCreditSharing:kbl */ |
| 1222 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) |
| 1223 | WA_SET_BIT(GAMT_CHKN_BIT_REG, |
| 1224 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); |
| 1225 | |
Mika Kuoppala | 8401d42 | 2016-06-07 17:19:00 +0300 | [diff] [blame] | 1226 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
| 1227 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) |
| 1228 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 1229 | HDC_FENCE_DEST_SLM_DISABLE); |
| 1230 | |
Mika Kuoppala | fe90581 | 2016-06-07 17:19:03 +0300 | [diff] [blame] | 1231 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
| 1232 | * involving this register should also be added to WA batch as required. |
| 1233 | */ |
| 1234 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) |
| 1235 | /* WaDisableLSQCROPERFforOCL:kbl */ |
| 1236 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | |
| 1237 | GEN8_LQSC_RO_PERF_DIS); |
| 1238 | |
Mika Kuoppala | ad2bdb4 | 2016-06-07 17:19:07 +0300 | [diff] [blame] | 1239 | /* WaInsertDummyPushConstPs:kbl */ |
| 1240 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) |
| 1241 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
| 1242 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); |
| 1243 | |
Mika Kuoppala | 4de5d7c | 2016-06-07 17:19:11 +0300 | [diff] [blame] | 1244 | /* WaDisableGafsUnitClkGating:kbl */ |
| 1245 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); |
| 1246 | |
Mika Kuoppala | 954337a | 2016-06-07 17:19:12 +0300 | [diff] [blame] | 1247 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
| 1248 | WA_SET_BIT_MASKED( |
| 1249 | GEN7_HALF_SLICE_CHICKEN1, |
| 1250 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
| 1251 | |
Mika Kuoppala | fe90581 | 2016-06-07 17:19:03 +0300 | [diff] [blame] | 1252 | /* WaDisableLSQCROPERFforOCL:kbl */ |
| 1253 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
| 1254 | if (ret) |
| 1255 | return ret; |
| 1256 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1257 | return 0; |
| 1258 | } |
| 1259 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1260 | int init_workarounds_ring(struct intel_engine_cs *engine) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1261 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1262 | struct drm_i915_private *dev_priv = engine->i915; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1263 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1264 | WARN_ON(engine->id != RCS); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1265 | |
| 1266 | dev_priv->workarounds.count = 0; |
Arun Siluvery | 33136b0 | 2016-01-21 21:43:47 +0000 | [diff] [blame] | 1267 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1268 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1269 | if (IS_BROADWELL(dev_priv)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1270 | return bdw_init_workarounds(engine); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1271 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1272 | if (IS_CHERRYVIEW(dev_priv)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1273 | return chv_init_workarounds(engine); |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 1274 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1275 | if (IS_SKYLAKE(dev_priv)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1276 | return skl_init_workarounds(engine); |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1277 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1278 | if (IS_BROXTON(dev_priv)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1279 | return bxt_init_workarounds(engine); |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 1280 | |
Mika Kuoppala | e5f81d6 | 2016-06-07 17:18:54 +0300 | [diff] [blame] | 1281 | if (IS_KABYLAKE(dev_priv)) |
| 1282 | return kbl_init_workarounds(engine); |
| 1283 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 1284 | return 0; |
| 1285 | } |
| 1286 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1287 | static int init_render_ring(struct intel_engine_cs *engine) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1288 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1289 | struct drm_i915_private *dev_priv = engine->i915; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1290 | int ret = init_ring_common(engine); |
Konrad Zapalowicz | 9c33baa | 2014-06-19 19:07:15 +0200 | [diff] [blame] | 1291 | if (ret) |
| 1292 | return ret; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 1293 | |
Akash Goel | 61a563a | 2014-03-25 18:01:50 +0530 | [diff] [blame] | 1294 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
Tvrtko Ursulin | ac657f6 | 2016-05-10 10:57:08 +0100 | [diff] [blame] | 1295 | if (IS_GEN(dev_priv, 4, 6)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1296 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1297 | |
| 1298 | /* We need to disable the AsyncFlip performance optimisations in order |
| 1299 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 1300 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 1301 | * |
Ville Syrjälä | 2441f87 | 2015-06-02 15:37:37 +0300 | [diff] [blame] | 1302 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1303 | */ |
Tvrtko Ursulin | ac657f6 | 2016-05-10 10:57:08 +0100 | [diff] [blame] | 1304 | if (IS_GEN(dev_priv, 6, 7)) |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1305 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 1306 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1307 | /* Required for the hardware to program scanline values for waiting */ |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1308 | /* WaEnableFlushTlbInvalidationMode:snb */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1309 | if (IS_GEN6(dev_priv)) |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1310 | I915_WRITE(GFX_MODE, |
Chris Wilson | aa83e30 | 2014-03-21 17:18:54 +0000 | [diff] [blame] | 1311 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1312 | |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1313 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1314 | if (IS_GEN7(dev_priv)) |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1315 | I915_WRITE(GFX_MODE_GEN7, |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1316 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1317 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1318 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1319 | if (IS_GEN6(dev_priv)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 1320 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 1321 | * "If this bit is set, STCunit will have LRA as replacement |
| 1322 | * policy. [...] This bit must be reset. LRA replacement |
| 1323 | * policy is not supported." |
| 1324 | */ |
| 1325 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 1326 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1327 | } |
| 1328 | |
Tvrtko Ursulin | ac657f6 | 2016-05-10 10:57:08 +0100 | [diff] [blame] | 1329 | if (IS_GEN(dev_priv, 6, 7)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1330 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1331 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1332 | if (HAS_L3_DPF(dev_priv)) |
| 1333 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1334 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1335 | return init_workarounds_ring(engine); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1336 | } |
| 1337 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1338 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1339 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1340 | struct drm_i915_private *dev_priv = engine->i915; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1341 | |
| 1342 | if (dev_priv->semaphore_obj) { |
| 1343 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); |
| 1344 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); |
| 1345 | dev_priv->semaphore_obj = NULL; |
| 1346 | } |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1347 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1348 | intel_fini_pipe_control(engine); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1349 | } |
| 1350 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1351 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1352 | unsigned int num_dwords) |
| 1353 | { |
| 1354 | #define MBOX_UPDATE_DWORDS 8 |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1355 | struct intel_engine_cs *signaller = signaller_req->engine; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1356 | struct drm_i915_private *dev_priv = signaller_req->i915; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1357 | struct intel_engine_cs *waiter; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1358 | enum intel_engine_id id; |
| 1359 | int ret, num_rings; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1360 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1361 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1362 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 1363 | #undef MBOX_UPDATE_DWORDS |
| 1364 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1365 | ret = intel_ring_begin(signaller_req, num_dwords); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1366 | if (ret) |
| 1367 | return ret; |
| 1368 | |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1369 | for_each_engine_id(waiter, dev_priv, id) { |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1370 | u32 seqno; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1371 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1372 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 1373 | continue; |
| 1374 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1375 | seqno = i915_gem_request_get_seqno(signaller_req); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1376 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
| 1377 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | |
| 1378 | PIPE_CONTROL_QW_WRITE | |
Chris Wilson | f9a4ea3 | 2016-04-29 13:18:24 +0100 | [diff] [blame] | 1379 | PIPE_CONTROL_CS_STALL); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1380 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
| 1381 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1382 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1383 | intel_ring_emit(signaller, 0); |
| 1384 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
Chris Wilson | 215a7e3 | 2016-04-29 13:18:23 +0100 | [diff] [blame] | 1385 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1386 | intel_ring_emit(signaller, 0); |
| 1387 | } |
| 1388 | |
| 1389 | return 0; |
| 1390 | } |
| 1391 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1392 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1393 | unsigned int num_dwords) |
| 1394 | { |
| 1395 | #define MBOX_UPDATE_DWORDS 6 |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1396 | struct intel_engine_cs *signaller = signaller_req->engine; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1397 | struct drm_i915_private *dev_priv = signaller_req->i915; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1398 | struct intel_engine_cs *waiter; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1399 | enum intel_engine_id id; |
| 1400 | int ret, num_rings; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1401 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1402 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1403 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 1404 | #undef MBOX_UPDATE_DWORDS |
| 1405 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1406 | ret = intel_ring_begin(signaller_req, num_dwords); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1407 | if (ret) |
| 1408 | return ret; |
| 1409 | |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1410 | for_each_engine_id(waiter, dev_priv, id) { |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1411 | u32 seqno; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1412 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1413 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 1414 | continue; |
| 1415 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1416 | seqno = i915_gem_request_get_seqno(signaller_req); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1417 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
| 1418 | MI_FLUSH_DW_OP_STOREDW); |
| 1419 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | |
| 1420 | MI_FLUSH_DW_USE_GTT); |
| 1421 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1422 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1423 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
Chris Wilson | 215a7e3 | 2016-04-29 13:18:23 +0100 | [diff] [blame] | 1424 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1425 | intel_ring_emit(signaller, 0); |
| 1426 | } |
| 1427 | |
| 1428 | return 0; |
| 1429 | } |
| 1430 | |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1431 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1432 | unsigned int num_dwords) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1433 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1434 | struct intel_engine_cs *signaller = signaller_req->engine; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1435 | struct drm_i915_private *dev_priv = signaller_req->i915; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1436 | struct intel_engine_cs *useless; |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1437 | enum intel_engine_id id; |
| 1438 | int ret, num_rings; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1439 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1440 | #define MBOX_UPDATE_DWORDS 3 |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1441 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1442 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
| 1443 | #undef MBOX_UPDATE_DWORDS |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1444 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1445 | ret = intel_ring_begin(signaller_req, num_dwords); |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1446 | if (ret) |
| 1447 | return ret; |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1448 | |
Dave Gordon | c3232b1 | 2016-03-23 18:19:53 +0000 | [diff] [blame] | 1449 | for_each_engine_id(useless, dev_priv, id) { |
| 1450 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1451 | |
| 1452 | if (i915_mmio_reg_valid(mbox_reg)) { |
John Harrison | f716968 | 2015-05-29 17:44:05 +0100 | [diff] [blame] | 1453 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1454 | |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1455 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
Ville Syrjälä | f92a916 | 2015-11-04 23:20:07 +0200 | [diff] [blame] | 1456 | intel_ring_emit_reg(signaller, mbox_reg); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1457 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1458 | } |
| 1459 | } |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1460 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1461 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
| 1462 | if (num_rings % 2 == 0) |
| 1463 | intel_ring_emit(signaller, MI_NOOP); |
| 1464 | |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1465 | return 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1466 | } |
| 1467 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1468 | /** |
| 1469 | * gen6_add_request - Update the semaphore mailbox registers |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 1470 | * |
| 1471 | * @request - request to write to the ring |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1472 | * |
| 1473 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 1474 | * This acts like a signal in the canonical semaphore. |
| 1475 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1476 | static int |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 1477 | gen6_add_request(struct drm_i915_gem_request *req) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1478 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1479 | struct intel_engine_cs *engine = req->engine; |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1480 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1481 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1482 | if (engine->semaphore.signal) |
| 1483 | ret = engine->semaphore.signal(req, 4); |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 1484 | else |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1485 | ret = intel_ring_begin(req, 4); |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 1486 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1487 | if (ret) |
| 1488 | return ret; |
| 1489 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1490 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
| 1491 | intel_ring_emit(engine, |
| 1492 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1493 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1494 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
| 1495 | __intel_ring_advance(engine); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1496 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1497 | return 0; |
| 1498 | } |
| 1499 | |
Chris Wilson | a58c01a | 2016-04-29 13:18:21 +0100 | [diff] [blame] | 1500 | static int |
| 1501 | gen8_render_add_request(struct drm_i915_gem_request *req) |
| 1502 | { |
| 1503 | struct intel_engine_cs *engine = req->engine; |
| 1504 | int ret; |
| 1505 | |
| 1506 | if (engine->semaphore.signal) |
| 1507 | ret = engine->semaphore.signal(req, 8); |
| 1508 | else |
| 1509 | ret = intel_ring_begin(req, 8); |
| 1510 | if (ret) |
| 1511 | return ret; |
| 1512 | |
| 1513 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
| 1514 | intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB | |
| 1515 | PIPE_CONTROL_CS_STALL | |
| 1516 | PIPE_CONTROL_QW_WRITE)); |
| 1517 | intel_ring_emit(engine, intel_hws_seqno_address(req->engine)); |
| 1518 | intel_ring_emit(engine, 0); |
| 1519 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1520 | /* We're thrashing one dword of HWS. */ |
| 1521 | intel_ring_emit(engine, 0); |
| 1522 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
| 1523 | intel_ring_emit(engine, MI_NOOP); |
| 1524 | __intel_ring_advance(engine); |
| 1525 | |
| 1526 | return 0; |
| 1527 | } |
| 1528 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1529 | static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv, |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1530 | u32 seqno) |
| 1531 | { |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1532 | return dev_priv->last_seqno < seqno; |
| 1533 | } |
| 1534 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1535 | /** |
| 1536 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 1537 | * |
| 1538 | * @waiter - ring that is waiting |
| 1539 | * @signaller - ring which has, or will signal |
| 1540 | * @seqno - seqno which the waiter will block on |
| 1541 | */ |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1542 | |
| 1543 | static int |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 1544 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1545 | struct intel_engine_cs *signaller, |
| 1546 | u32 seqno) |
| 1547 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1548 | struct intel_engine_cs *waiter = waiter_req->engine; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1549 | struct drm_i915_private *dev_priv = waiter_req->i915; |
Chris Wilson | 6ef48d7 | 2016-04-29 13:18:25 +0100 | [diff] [blame] | 1550 | struct i915_hw_ppgtt *ppgtt; |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1551 | int ret; |
| 1552 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1553 | ret = intel_ring_begin(waiter_req, 4); |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1554 | if (ret) |
| 1555 | return ret; |
| 1556 | |
| 1557 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | |
| 1558 | MI_SEMAPHORE_GLOBAL_GTT | |
| 1559 | MI_SEMAPHORE_SAD_GTE_SDD); |
| 1560 | intel_ring_emit(waiter, seqno); |
| 1561 | intel_ring_emit(waiter, |
| 1562 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1563 | intel_ring_emit(waiter, |
| 1564 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1565 | intel_ring_advance(waiter); |
Chris Wilson | 6ef48d7 | 2016-04-29 13:18:25 +0100 | [diff] [blame] | 1566 | |
| 1567 | /* When the !RCS engines idle waiting upon a semaphore, they lose their |
| 1568 | * pagetables and we must reload them before executing the batch. |
| 1569 | * We do this on the i915_switch_context() following the wait and |
| 1570 | * before the dispatch. |
| 1571 | */ |
| 1572 | ppgtt = waiter_req->ctx->ppgtt; |
| 1573 | if (ppgtt && waiter_req->engine->id != RCS) |
| 1574 | ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine); |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1575 | return 0; |
| 1576 | } |
| 1577 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1578 | static int |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 1579 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1580 | struct intel_engine_cs *signaller, |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1581 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1582 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1583 | struct intel_engine_cs *waiter = waiter_req->engine; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1584 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 1585 | MI_SEMAPHORE_COMPARE | |
| 1586 | MI_SEMAPHORE_REGISTER; |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1587 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
| 1588 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1589 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 1590 | /* Throughout all of the GEM code, seqno passed implies our current |
| 1591 | * seqno is >= the last seqno executed. However for hardware the |
| 1592 | * comparison is strictly greater than. |
| 1593 | */ |
| 1594 | seqno -= 1; |
| 1595 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1596 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1597 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1598 | ret = intel_ring_begin(waiter_req, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1599 | if (ret) |
| 1600 | return ret; |
| 1601 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1602 | /* If seqno wrap happened, omit the wait with no-ops */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1603 | if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) { |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1604 | intel_ring_emit(waiter, dw1 | wait_mbox); |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1605 | intel_ring_emit(waiter, seqno); |
| 1606 | intel_ring_emit(waiter, 0); |
| 1607 | intel_ring_emit(waiter, MI_NOOP); |
| 1608 | } else { |
| 1609 | intel_ring_emit(waiter, MI_NOOP); |
| 1610 | intel_ring_emit(waiter, MI_NOOP); |
| 1611 | intel_ring_emit(waiter, MI_NOOP); |
| 1612 | intel_ring_emit(waiter, MI_NOOP); |
| 1613 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1614 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1615 | |
| 1616 | return 0; |
| 1617 | } |
| 1618 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1619 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 1620 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1621 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 1622 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1623 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 1624 | intel_ring_emit(ring__, 0); \ |
| 1625 | intel_ring_emit(ring__, 0); \ |
| 1626 | } while (0) |
| 1627 | |
| 1628 | static int |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 1629 | pc_render_add_request(struct drm_i915_gem_request *req) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1630 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1631 | struct intel_engine_cs *engine = req->engine; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1632 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1633 | int ret; |
| 1634 | |
| 1635 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 1636 | * incoherent with writes to memory, i.e. completely fubar, |
| 1637 | * so we need to use PIPE_NOTIFY instead. |
| 1638 | * |
| 1639 | * However, we also need to workaround the qword write |
| 1640 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 1641 | * memory before requesting an interrupt. |
| 1642 | */ |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1643 | ret = intel_ring_begin(req, 32); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1644 | if (ret) |
| 1645 | return ret; |
| 1646 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1647 | intel_ring_emit(engine, |
| 1648 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1649 | PIPE_CONTROL_WRITE_FLUSH | |
| 1650 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1651 | intel_ring_emit(engine, |
| 1652 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 1653 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1654 | intel_ring_emit(engine, 0); |
| 1655 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1656 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1657 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1658 | scratch_addr += 2 * CACHELINE_BYTES; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1659 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1660 | scratch_addr += 2 * CACHELINE_BYTES; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1661 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1662 | scratch_addr += 2 * CACHELINE_BYTES; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1663 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1664 | scratch_addr += 2 * CACHELINE_BYTES; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1665 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1666 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1667 | intel_ring_emit(engine, |
| 1668 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1669 | PIPE_CONTROL_WRITE_FLUSH | |
| 1670 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1671 | PIPE_CONTROL_NOTIFY); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1672 | intel_ring_emit(engine, |
| 1673 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 1674 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1675 | intel_ring_emit(engine, 0); |
| 1676 | __intel_ring_advance(engine); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1677 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1678 | return 0; |
| 1679 | } |
| 1680 | |
Chris Wilson | c04e0f3 | 2016-04-09 10:57:54 +0100 | [diff] [blame] | 1681 | static void |
| 1682 | gen6_seqno_barrier(struct intel_engine_cs *engine) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1683 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1684 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | bcbdb6d | 2016-04-27 09:02:01 +0100 | [diff] [blame] | 1685 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1686 | /* Workaround to force correct ordering between irq and seqno writes on |
| 1687 | * ivb (and maybe also on snb) by reading from a CS register (like |
Chris Wilson | 9b9ed30 | 2016-04-09 10:57:53 +0100 | [diff] [blame] | 1688 | * ACTHD) before reading the status page. |
| 1689 | * |
| 1690 | * Note that this effectively stalls the read by the time it takes to |
| 1691 | * do a memory transaction, which more or less ensures that the write |
| 1692 | * from the GPU has sufficient time to invalidate the CPU cacheline. |
| 1693 | * Alternatively we could delay the interrupt from the CS ring to give |
| 1694 | * the write time to land, but that would incur a delay after every |
| 1695 | * batch i.e. much more frequent than a delay when waiting for the |
| 1696 | * interrupt (with the same net latency). |
Chris Wilson | bcbdb6d | 2016-04-27 09:02:01 +0100 | [diff] [blame] | 1697 | * |
| 1698 | * Also note that to prevent whole machine hangs on gen7, we have to |
| 1699 | * take the spinlock to guard against concurrent cacheline access. |
Chris Wilson | 9b9ed30 | 2016-04-09 10:57:53 +0100 | [diff] [blame] | 1700 | */ |
Chris Wilson | bcbdb6d | 2016-04-27 09:02:01 +0100 | [diff] [blame] | 1701 | spin_lock_irq(&dev_priv->uncore.lock); |
Chris Wilson | c04e0f3 | 2016-04-09 10:57:54 +0100 | [diff] [blame] | 1702 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
Chris Wilson | bcbdb6d | 2016-04-27 09:02:01 +0100 | [diff] [blame] | 1703 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1704 | } |
| 1705 | |
| 1706 | static u32 |
Chris Wilson | c04e0f3 | 2016-04-09 10:57:54 +0100 | [diff] [blame] | 1707 | ring_get_seqno(struct intel_engine_cs *engine) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1708 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1709 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1710 | } |
| 1711 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1712 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1713 | ring_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1714 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1715 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1716 | } |
| 1717 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1718 | static u32 |
Chris Wilson | c04e0f3 | 2016-04-09 10:57:54 +0100 | [diff] [blame] | 1719 | pc_render_get_seqno(struct intel_engine_cs *engine) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1720 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1721 | return engine->scratch.cpu_page[0]; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1722 | } |
| 1723 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1724 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1725 | pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1726 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1727 | engine->scratch.cpu_page[0] = seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1728 | } |
| 1729 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1730 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1731 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1732 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1733 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1734 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1735 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1736 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1737 | return false; |
| 1738 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1739 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1740 | if (engine->irq_refcount++ == 0) |
| 1741 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1742 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1743 | |
| 1744 | return true; |
| 1745 | } |
| 1746 | |
| 1747 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1748 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1749 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1750 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1751 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1752 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1753 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1754 | if (--engine->irq_refcount == 0) |
| 1755 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1756 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1757 | } |
| 1758 | |
| 1759 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1760 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1761 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1762 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1763 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1764 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1765 | if (!intel_irqs_enabled(dev_priv)) |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1766 | return false; |
| 1767 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1768 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1769 | if (engine->irq_refcount++ == 0) { |
| 1770 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1771 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1772 | POSTING_READ(IMR); |
| 1773 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1774 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1775 | |
| 1776 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1777 | } |
| 1778 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1779 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1780 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1781 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1782 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1783 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1784 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1785 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1786 | if (--engine->irq_refcount == 0) { |
| 1787 | dev_priv->irq_mask |= engine->irq_enable_mask; |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1788 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1789 | POSTING_READ(IMR); |
| 1790 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1791 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1792 | } |
| 1793 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1794 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1795 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1796 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1797 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1798 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1799 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1800 | if (!intel_irqs_enabled(dev_priv)) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1801 | return false; |
| 1802 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1803 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1804 | if (engine->irq_refcount++ == 0) { |
| 1805 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1806 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1807 | POSTING_READ16(IMR); |
| 1808 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1809 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1810 | |
| 1811 | return true; |
| 1812 | } |
| 1813 | |
| 1814 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1815 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1816 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1817 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1818 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1819 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1820 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1821 | if (--engine->irq_refcount == 0) { |
| 1822 | dev_priv->irq_mask |= engine->irq_enable_mask; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1823 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1824 | POSTING_READ16(IMR); |
| 1825 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1826 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1827 | } |
| 1828 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1829 | static int |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 1830 | bsd_ring_flush(struct drm_i915_gem_request *req, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1831 | u32 invalidate_domains, |
| 1832 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1833 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1834 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1835 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1836 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1837 | ret = intel_ring_begin(req, 2); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1838 | if (ret) |
| 1839 | return ret; |
| 1840 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1841 | intel_ring_emit(engine, MI_FLUSH); |
| 1842 | intel_ring_emit(engine, MI_NOOP); |
| 1843 | intel_ring_advance(engine); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1844 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1845 | } |
| 1846 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1847 | static int |
John Harrison | ee044a8 | 2015-05-29 17:44:00 +0100 | [diff] [blame] | 1848 | i9xx_add_request(struct drm_i915_gem_request *req) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1849 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1850 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1851 | int ret; |
| 1852 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1853 | ret = intel_ring_begin(req, 4); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1854 | if (ret) |
| 1855 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 1856 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1857 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
| 1858 | intel_ring_emit(engine, |
| 1859 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1860 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); |
| 1861 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
| 1862 | __intel_ring_advance(engine); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1863 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1864 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1865 | } |
| 1866 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1867 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1868 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1869 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1870 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1871 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1872 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1873 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 1874 | return false; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1875 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1876 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1877 | if (engine->irq_refcount++ == 0) { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1878 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1879 | I915_WRITE_IMR(engine, |
| 1880 | ~(engine->irq_enable_mask | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1881 | GT_PARITY_ERROR(dev_priv))); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1882 | else |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1883 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
| 1884 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1885 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1886 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1887 | |
| 1888 | return true; |
| 1889 | } |
| 1890 | |
| 1891 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1892 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1893 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1894 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1895 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1896 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1897 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1898 | if (--engine->irq_refcount == 0) { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1899 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) |
| 1900 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1901 | else |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1902 | I915_WRITE_IMR(engine, ~0); |
| 1903 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1904 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1905 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1906 | } |
| 1907 | |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1908 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1909 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1910 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1911 | struct drm_i915_private *dev_priv = engine->i915; |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1912 | unsigned long flags; |
| 1913 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1914 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1915 | return false; |
| 1916 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1917 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1918 | if (engine->irq_refcount++ == 0) { |
| 1919 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
| 1920 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1921 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1922 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1923 | |
| 1924 | return true; |
| 1925 | } |
| 1926 | |
| 1927 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1928 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1929 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1930 | struct drm_i915_private *dev_priv = engine->i915; |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1931 | unsigned long flags; |
| 1932 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1933 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1934 | if (--engine->irq_refcount == 0) { |
| 1935 | I915_WRITE_IMR(engine, ~0); |
| 1936 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1937 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1938 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1939 | } |
| 1940 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1941 | static bool |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1942 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1943 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1944 | struct drm_i915_private *dev_priv = engine->i915; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1945 | unsigned long flags; |
| 1946 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1947 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1948 | return false; |
| 1949 | |
| 1950 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1951 | if (engine->irq_refcount++ == 0) { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1952 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1953 | I915_WRITE_IMR(engine, |
| 1954 | ~(engine->irq_enable_mask | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1955 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
| 1956 | } else { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1957 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1958 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1959 | POSTING_READ(RING_IMR(engine->mmio_base)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1960 | } |
| 1961 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1962 | |
| 1963 | return true; |
| 1964 | } |
| 1965 | |
| 1966 | static void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1967 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1968 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1969 | struct drm_i915_private *dev_priv = engine->i915; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1970 | unsigned long flags; |
| 1971 | |
| 1972 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1973 | if (--engine->irq_refcount == 0) { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1974 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1975 | I915_WRITE_IMR(engine, |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1976 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
| 1977 | } else { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1978 | I915_WRITE_IMR(engine, ~0); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1979 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1980 | POSTING_READ(RING_IMR(engine->mmio_base)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1981 | } |
| 1982 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1983 | } |
| 1984 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1985 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 1986 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1987 | u64 offset, u32 length, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1988 | unsigned dispatch_flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1989 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1990 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1991 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1992 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1993 | ret = intel_ring_begin(req, 2); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1994 | if (ret) |
| 1995 | return ret; |
| 1996 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1997 | intel_ring_emit(engine, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1998 | MI_BATCH_BUFFER_START | |
| 1999 | MI_BATCH_GTT | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2000 | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 2001 | 0 : MI_BATCH_NON_SECURE_I965)); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2002 | intel_ring_emit(engine, offset); |
| 2003 | intel_ring_advance(engine); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2004 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2005 | return 0; |
| 2006 | } |
| 2007 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2008 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 2009 | #define I830_BATCH_LIMIT (256*1024) |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2010 | #define I830_TLB_ENTRIES (2) |
| 2011 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2012 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 2013 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2014 | u64 offset, u32 len, |
| 2015 | unsigned dispatch_flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2016 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2017 | struct intel_engine_cs *engine = req->engine; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2018 | u32 cs_offset = engine->scratch.gtt_offset; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 2019 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2020 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2021 | ret = intel_ring_begin(req, 6); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2022 | if (ret) |
| 2023 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2024 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2025 | /* Evict the invalid PTE TLBs */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2026 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
| 2027 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); |
| 2028 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ |
| 2029 | intel_ring_emit(engine, cs_offset); |
| 2030 | intel_ring_emit(engine, 0xdeadbeef); |
| 2031 | intel_ring_emit(engine, MI_NOOP); |
| 2032 | intel_ring_advance(engine); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2033 | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2034 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2035 | if (len > I830_BATCH_LIMIT) |
| 2036 | return -ENOSPC; |
| 2037 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2038 | ret = intel_ring_begin(req, 6 + 2); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2039 | if (ret) |
| 2040 | return ret; |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2041 | |
| 2042 | /* Blit the batch (which has now all relocs applied) to the |
| 2043 | * stable batch scratch bo area (so that the CS never |
| 2044 | * stumbles over its tlb invalidation bug) ... |
| 2045 | */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2046 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
| 2047 | intel_ring_emit(engine, |
| 2048 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
| 2049 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
| 2050 | intel_ring_emit(engine, cs_offset); |
| 2051 | intel_ring_emit(engine, 4096); |
| 2052 | intel_ring_emit(engine, offset); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2053 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2054 | intel_ring_emit(engine, MI_FLUSH); |
| 2055 | intel_ring_emit(engine, MI_NOOP); |
| 2056 | intel_ring_advance(engine); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2057 | |
| 2058 | /* ... and execute it. */ |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2059 | offset = cs_offset; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2060 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2061 | |
Ville Syrjälä | 9d611c0 | 2015-12-14 18:23:49 +0200 | [diff] [blame] | 2062 | ret = intel_ring_begin(req, 2); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2063 | if (ret) |
| 2064 | return ret; |
| 2065 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2066 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
| 2067 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 2068 | 0 : MI_BATCH_NON_SECURE)); |
| 2069 | intel_ring_advance(engine); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2070 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2071 | return 0; |
| 2072 | } |
| 2073 | |
| 2074 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 2075 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2076 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2077 | unsigned dispatch_flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2078 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2079 | struct intel_engine_cs *engine = req->engine; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2080 | int ret; |
| 2081 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2082 | ret = intel_ring_begin(req, 2); |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2083 | if (ret) |
| 2084 | return ret; |
| 2085 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2086 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
| 2087 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 2088 | 0 : MI_BATCH_NON_SECURE)); |
| 2089 | intel_ring_advance(engine); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2090 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2091 | return 0; |
| 2092 | } |
| 2093 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2094 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2095 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2096 | struct drm_i915_private *dev_priv = engine->i915; |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2097 | |
| 2098 | if (!dev_priv->status_page_dmah) |
| 2099 | return; |
| 2100 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2101 | drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2102 | engine->status_page.page_addr = NULL; |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2103 | } |
| 2104 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2105 | static void cleanup_status_page(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2106 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2107 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2108 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2109 | obj = engine->status_page.obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2110 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2111 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2112 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2113 | kunmap(sg_page(obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2114 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2115 | drm_gem_object_unreference(&obj->base); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2116 | engine->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2117 | } |
| 2118 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2119 | static int init_status_page(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2120 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2121 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2122 | |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2123 | if (obj == NULL) { |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 2124 | unsigned flags; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2125 | int ret; |
| 2126 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2127 | obj = i915_gem_object_create(engine->i915->dev, 4096); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 2128 | if (IS_ERR(obj)) { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2129 | DRM_ERROR("Failed to allocate status page\n"); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 2130 | return PTR_ERR(obj); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2131 | } |
| 2132 | |
| 2133 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 2134 | if (ret) |
| 2135 | goto err_unref; |
| 2136 | |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 2137 | flags = 0; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2138 | if (!HAS_LLC(engine->i915)) |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 2139 | /* On g33, we cannot place HWS above 256MiB, so |
| 2140 | * restrict its pinning to the low mappable arena. |
| 2141 | * Though this restriction is not documented for |
| 2142 | * gen4, gen5, or byt, they also behave similarly |
| 2143 | * and hang if the HWS is placed at the top of the |
| 2144 | * GTT. To generalise, it appears that all !llc |
| 2145 | * platforms have issues with us placing the HWS |
| 2146 | * above the mappable region (even though we never |
| 2147 | * actualy map it). |
| 2148 | */ |
| 2149 | flags |= PIN_MAPPABLE; |
| 2150 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2151 | if (ret) { |
| 2152 | err_unref: |
| 2153 | drm_gem_object_unreference(&obj->base); |
| 2154 | return ret; |
| 2155 | } |
| 2156 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2157 | engine->status_page.obj = obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2158 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2159 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2160 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
| 2161 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
| 2162 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2163 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2164 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2165 | engine->name, engine->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2166 | |
| 2167 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2168 | } |
| 2169 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2170 | static int init_phys_status_page(struct intel_engine_cs *engine) |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2171 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2172 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2173 | |
| 2174 | if (!dev_priv->status_page_dmah) { |
| 2175 | dev_priv->status_page_dmah = |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2176 | drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2177 | if (!dev_priv->status_page_dmah) |
| 2178 | return -ENOMEM; |
| 2179 | } |
| 2180 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2181 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 2182 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2183 | |
| 2184 | return 0; |
| 2185 | } |
| 2186 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2187 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
| 2188 | { |
Chris Wilson | 3d77e9b | 2016-04-28 09:56:40 +0100 | [diff] [blame] | 2189 | GEM_BUG_ON(ringbuf->vma == NULL); |
| 2190 | GEM_BUG_ON(ringbuf->virtual_start == NULL); |
| 2191 | |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2192 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2193 | i915_gem_object_unpin_map(ringbuf->obj); |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2194 | else |
Chris Wilson | 3d77e9b | 2016-04-28 09:56:40 +0100 | [diff] [blame] | 2195 | i915_vma_unpin_iomap(ringbuf->vma); |
Dave Gordon | 8305216 | 2016-04-12 14:46:16 +0100 | [diff] [blame] | 2196 | ringbuf->virtual_start = NULL; |
Chris Wilson | 3d77e9b | 2016-04-28 09:56:40 +0100 | [diff] [blame] | 2197 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2198 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
Chris Wilson | 3d77e9b | 2016-04-28 09:56:40 +0100 | [diff] [blame] | 2199 | ringbuf->vma = NULL; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2200 | } |
| 2201 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2202 | int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv, |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2203 | struct intel_ringbuffer *ringbuf) |
| 2204 | { |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2205 | struct drm_i915_gem_object *obj = ringbuf->obj; |
Chris Wilson | a687a43 | 2016-04-13 17:35:11 +0100 | [diff] [blame] | 2206 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
| 2207 | unsigned flags = PIN_OFFSET_BIAS | 4096; |
Dave Gordon | 8305216 | 2016-04-12 14:46:16 +0100 | [diff] [blame] | 2208 | void *addr; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2209 | int ret; |
| 2210 | |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2211 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
Chris Wilson | a687a43 | 2016-04-13 17:35:11 +0100 | [diff] [blame] | 2212 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2213 | if (ret) |
| 2214 | return ret; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2215 | |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2216 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
Chris Wilson | d2cad53 | 2016-04-08 12:11:10 +0100 | [diff] [blame] | 2217 | if (ret) |
| 2218 | goto err_unpin; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2219 | |
Dave Gordon | 8305216 | 2016-04-12 14:46:16 +0100 | [diff] [blame] | 2220 | addr = i915_gem_object_pin_map(obj); |
| 2221 | if (IS_ERR(addr)) { |
| 2222 | ret = PTR_ERR(addr); |
Chris Wilson | d2cad53 | 2016-04-08 12:11:10 +0100 | [diff] [blame] | 2223 | goto err_unpin; |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2224 | } |
| 2225 | } else { |
Chris Wilson | a687a43 | 2016-04-13 17:35:11 +0100 | [diff] [blame] | 2226 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
| 2227 | flags | PIN_MAPPABLE); |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2228 | if (ret) |
| 2229 | return ret; |
| 2230 | |
| 2231 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
Chris Wilson | d2cad53 | 2016-04-08 12:11:10 +0100 | [diff] [blame] | 2232 | if (ret) |
| 2233 | goto err_unpin; |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2234 | |
Daniele Ceraolo Spurio | ff3dc08 | 2016-01-27 15:43:49 +0000 | [diff] [blame] | 2235 | /* Access through the GTT requires the device to be awake. */ |
| 2236 | assert_rpm_wakelock_held(dev_priv); |
| 2237 | |
Chris Wilson | 3d77e9b | 2016-04-28 09:56:40 +0100 | [diff] [blame] | 2238 | addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); |
| 2239 | if (IS_ERR(addr)) { |
| 2240 | ret = PTR_ERR(addr); |
Chris Wilson | d2cad53 | 2016-04-08 12:11:10 +0100 | [diff] [blame] | 2241 | goto err_unpin; |
Chris Wilson | def0c5f | 2015-10-08 13:39:54 +0100 | [diff] [blame] | 2242 | } |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2243 | } |
| 2244 | |
Dave Gordon | 8305216 | 2016-04-12 14:46:16 +0100 | [diff] [blame] | 2245 | ringbuf->virtual_start = addr; |
Tvrtko Ursulin | 0eb973d | 2016-01-15 15:10:28 +0000 | [diff] [blame] | 2246 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2247 | return 0; |
Chris Wilson | d2cad53 | 2016-04-08 12:11:10 +0100 | [diff] [blame] | 2248 | |
| 2249 | err_unpin: |
| 2250 | i915_gem_object_ggtt_unpin(obj); |
| 2251 | return ret; |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2252 | } |
| 2253 | |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2254 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2255 | { |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 2256 | drm_gem_object_unreference(&ringbuf->obj->base); |
| 2257 | ringbuf->obj = NULL; |
| 2258 | } |
| 2259 | |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2260 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
| 2261 | struct intel_ringbuffer *ringbuf) |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 2262 | { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2263 | struct drm_i915_gem_object *obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2264 | |
| 2265 | obj = NULL; |
| 2266 | if (!HAS_LLC(dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2267 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2268 | if (obj == NULL) |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 2269 | obj = i915_gem_object_create(dev, ringbuf->size); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 2270 | if (IS_ERR(obj)) |
| 2271 | return PTR_ERR(obj); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2272 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 2273 | /* mark ring buffers as read-only from GPU side by default */ |
| 2274 | obj->gt_ro = 1; |
| 2275 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2276 | ringbuf->obj = obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2277 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2278 | return 0; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2279 | } |
| 2280 | |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2281 | struct intel_ringbuffer * |
| 2282 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) |
| 2283 | { |
| 2284 | struct intel_ringbuffer *ring; |
| 2285 | int ret; |
| 2286 | |
| 2287 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2288 | if (ring == NULL) { |
| 2289 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", |
| 2290 | engine->name); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2291 | return ERR_PTR(-ENOMEM); |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2292 | } |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2293 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2294 | ring->engine = engine; |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2295 | list_add(&ring->link, &engine->buffers); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2296 | |
| 2297 | ring->size = size; |
| 2298 | /* Workaround an erratum on the i830 which causes a hang if |
| 2299 | * the TAIL pointer points to within the last 2 cachelines |
| 2300 | * of the buffer. |
| 2301 | */ |
| 2302 | ring->effective_size = size; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2303 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2304 | ring->effective_size -= 2 * CACHELINE_BYTES; |
| 2305 | |
| 2306 | ring->last_retired_head = -1; |
| 2307 | intel_ring_update_space(ring); |
| 2308 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2309 | ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2310 | if (ret) { |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2311 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
| 2312 | engine->name, ret); |
| 2313 | list_del(&ring->link); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2314 | kfree(ring); |
| 2315 | return ERR_PTR(ret); |
| 2316 | } |
| 2317 | |
| 2318 | return ring; |
| 2319 | } |
| 2320 | |
| 2321 | void |
| 2322 | intel_ringbuffer_free(struct intel_ringbuffer *ring) |
| 2323 | { |
| 2324 | intel_destroy_ringbuffer_obj(ring); |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2325 | list_del(&ring->link); |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2326 | kfree(ring); |
| 2327 | } |
| 2328 | |
Chris Wilson | 0cb26a8 | 2016-06-24 14:55:53 +0100 | [diff] [blame] | 2329 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
| 2330 | struct intel_engine_cs *engine) |
| 2331 | { |
| 2332 | struct intel_context *ce = &ctx->engine[engine->id]; |
| 2333 | int ret; |
| 2334 | |
| 2335 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); |
| 2336 | |
| 2337 | if (ce->pin_count++) |
| 2338 | return 0; |
| 2339 | |
| 2340 | if (ce->state) { |
| 2341 | ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0); |
| 2342 | if (ret) |
| 2343 | goto error; |
| 2344 | } |
| 2345 | |
Chris Wilson | c7c3c07 | 2016-06-24 14:55:54 +0100 | [diff] [blame] | 2346 | /* The kernel context is only used as a placeholder for flushing the |
| 2347 | * active context. It is never used for submitting user rendering and |
| 2348 | * as such never requires the golden render context, and so we can skip |
| 2349 | * emitting it when we switch to the kernel context. This is required |
| 2350 | * as during eviction we cannot allocate and pin the renderstate in |
| 2351 | * order to initialise the context. |
| 2352 | */ |
| 2353 | if (ctx == ctx->i915->kernel_context) |
| 2354 | ce->initialised = true; |
| 2355 | |
Chris Wilson | 0cb26a8 | 2016-06-24 14:55:53 +0100 | [diff] [blame] | 2356 | i915_gem_context_reference(ctx); |
| 2357 | return 0; |
| 2358 | |
| 2359 | error: |
| 2360 | ce->pin_count = 0; |
| 2361 | return ret; |
| 2362 | } |
| 2363 | |
| 2364 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, |
| 2365 | struct intel_engine_cs *engine) |
| 2366 | { |
| 2367 | struct intel_context *ce = &ctx->engine[engine->id]; |
| 2368 | |
| 2369 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); |
| 2370 | |
| 2371 | if (--ce->pin_count) |
| 2372 | return; |
| 2373 | |
| 2374 | if (ce->state) |
| 2375 | i915_gem_object_ggtt_unpin(ce->state); |
| 2376 | |
| 2377 | i915_gem_context_unreference(ctx); |
| 2378 | } |
| 2379 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2380 | static int intel_init_ring_buffer(struct drm_device *dev, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2381 | struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2382 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2383 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2384 | struct intel_ringbuffer *ringbuf; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 2385 | int ret; |
| 2386 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2387 | WARN_ON(engine->buffer); |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2388 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2389 | engine->i915 = dev_priv; |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2390 | INIT_LIST_HEAD(&engine->active_list); |
| 2391 | INIT_LIST_HEAD(&engine->request_list); |
| 2392 | INIT_LIST_HEAD(&engine->execlist_queue); |
| 2393 | INIT_LIST_HEAD(&engine->buffers); |
| 2394 | i915_gem_batch_pool_init(dev, &engine->batch_pool); |
| 2395 | memset(engine->semaphore.sync_seqno, 0, |
| 2396 | sizeof(engine->semaphore.sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 2397 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2398 | init_waitqueue_head(&engine->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2399 | |
Chris Wilson | 0cb26a8 | 2016-06-24 14:55:53 +0100 | [diff] [blame] | 2400 | /* We may need to do things with the shrinker which |
| 2401 | * require us to immediately switch back to the default |
| 2402 | * context. This can cause a problem as pinning the |
| 2403 | * default context also requires GTT space which may not |
| 2404 | * be available. To avoid this we always pin the default |
| 2405 | * context. |
| 2406 | */ |
| 2407 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); |
| 2408 | if (ret) |
| 2409 | goto error; |
| 2410 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2411 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 2412 | if (IS_ERR(ringbuf)) { |
| 2413 | ret = PTR_ERR(ringbuf); |
| 2414 | goto error; |
| 2415 | } |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2416 | engine->buffer = ringbuf; |
Chris Wilson | 01101fa | 2015-09-03 13:01:39 +0100 | [diff] [blame] | 2417 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2418 | if (I915_NEED_GFX_HWS(dev_priv)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2419 | ret = init_status_page(engine); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2420 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2421 | goto error; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2422 | } else { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2423 | WARN_ON(engine->id != RCS); |
| 2424 | ret = init_phys_status_page(engine); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2425 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2426 | goto error; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2427 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2428 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2429 | ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf); |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2430 | if (ret) { |
| 2431 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2432 | engine->name, ret); |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2433 | intel_destroy_ringbuffer_obj(ringbuf); |
| 2434 | goto error; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2435 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2436 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2437 | ret = i915_cmd_parser_init_ring(engine); |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 2438 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2439 | goto error; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2440 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2441 | return 0; |
| 2442 | |
| 2443 | error: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2444 | intel_cleanup_engine(engine); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2445 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2446 | } |
| 2447 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2448 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2449 | { |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 2450 | struct drm_i915_private *dev_priv; |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 2451 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2452 | if (!intel_engine_initialized(engine)) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2453 | return; |
| 2454 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2455 | dev_priv = engine->i915; |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 2456 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2457 | if (engine->buffer) { |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2458 | intel_stop_engine(engine); |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2459 | WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 2460 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2461 | intel_unpin_ringbuffer_obj(engine->buffer); |
| 2462 | intel_ringbuffer_free(engine->buffer); |
| 2463 | engine->buffer = NULL; |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 2464 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2465 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2466 | if (engine->cleanup) |
| 2467 | engine->cleanup(engine); |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2468 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2469 | if (I915_NEED_GFX_HWS(dev_priv)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2470 | cleanup_status_page(engine); |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2471 | } else { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2472 | WARN_ON(engine->id != RCS); |
| 2473 | cleanup_phys_status_page(engine); |
Ville Syrjälä | 7d3fdff | 2016-01-11 20:48:32 +0200 | [diff] [blame] | 2474 | } |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 2475 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2476 | i915_cmd_parser_fini_ring(engine); |
| 2477 | i915_gem_batch_pool_fini(&engine->batch_pool); |
Chris Wilson | 0cb26a8 | 2016-06-24 14:55:53 +0100 | [diff] [blame] | 2478 | |
| 2479 | intel_ring_context_unpin(dev_priv->kernel_context, engine); |
| 2480 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2481 | engine->i915 = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2482 | } |
| 2483 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2484 | int intel_engine_idle(struct intel_engine_cs *engine) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2485 | { |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 2486 | struct drm_i915_gem_request *req; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2487 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2488 | /* Wait upon the last request to be completed */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2489 | if (list_empty(&engine->request_list)) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2490 | return 0; |
| 2491 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2492 | req = list_entry(engine->request_list.prev, |
| 2493 | struct drm_i915_gem_request, |
| 2494 | list); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2495 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2496 | /* Make sure we do not trigger any retires */ |
| 2497 | return __i915_wait_request(req, |
Chris Wilson | c19ae98 | 2016-04-13 17:35:03 +0100 | [diff] [blame] | 2498 | req->i915->mm.interruptible, |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2499 | NULL, NULL); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2500 | } |
| 2501 | |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2502 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2503 | { |
Chris Wilson | 6310346 | 2016-04-28 09:56:49 +0100 | [diff] [blame] | 2504 | int ret; |
| 2505 | |
| 2506 | /* Flush enough space to reduce the likelihood of waiting after |
| 2507 | * we start building the request - in which case we will just |
| 2508 | * have to repeat work. |
| 2509 | */ |
Chris Wilson | a044246 | 2016-04-29 09:07:05 +0100 | [diff] [blame] | 2510 | request->reserved_space += LEGACY_REQUEST_SIZE; |
Chris Wilson | 6310346 | 2016-04-28 09:56:49 +0100 | [diff] [blame] | 2511 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2512 | request->ringbuf = request->engine->buffer; |
Chris Wilson | 6310346 | 2016-04-28 09:56:49 +0100 | [diff] [blame] | 2513 | |
| 2514 | ret = intel_ring_begin(request, 0); |
| 2515 | if (ret) |
| 2516 | return ret; |
| 2517 | |
Chris Wilson | a044246 | 2016-04-29 09:07:05 +0100 | [diff] [blame] | 2518 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
Chris Wilson | 6310346 | 2016-04-28 09:56:49 +0100 | [diff] [blame] | 2519 | return 0; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2520 | } |
| 2521 | |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2522 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2523 | { |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2524 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
| 2525 | struct intel_engine_cs *engine = req->engine; |
| 2526 | struct drm_i915_gem_request *target; |
| 2527 | |
| 2528 | intel_ring_update_space(ringbuf); |
| 2529 | if (ringbuf->space >= bytes) |
| 2530 | return 0; |
| 2531 | |
| 2532 | /* |
| 2533 | * Space is reserved in the ringbuffer for finalising the request, |
| 2534 | * as that cannot be allowed to fail. During request finalisation, |
| 2535 | * reserved_space is set to 0 to stop the overallocation and the |
| 2536 | * assumption is that then we never need to wait (which has the |
| 2537 | * risk of failing with EINTR). |
| 2538 | * |
| 2539 | * See also i915_gem_request_alloc() and i915_add_request(). |
| 2540 | */ |
Chris Wilson | 0251a96 | 2016-04-28 09:56:47 +0100 | [diff] [blame] | 2541 | GEM_BUG_ON(!req->reserved_space); |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2542 | |
| 2543 | list_for_each_entry(target, &engine->request_list, list) { |
| 2544 | unsigned space; |
| 2545 | |
| 2546 | /* |
| 2547 | * The request queue is per-engine, so can contain requests |
| 2548 | * from multiple ringbuffers. Here, we must ignore any that |
| 2549 | * aren't from the ringbuffer we're considering. |
| 2550 | */ |
| 2551 | if (target->ringbuf != ringbuf) |
| 2552 | continue; |
| 2553 | |
| 2554 | /* Would completion of this request free enough space? */ |
| 2555 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
| 2556 | ringbuf->size); |
| 2557 | if (space >= bytes) |
| 2558 | break; |
| 2559 | } |
| 2560 | |
| 2561 | if (WARN_ON(&target->list == &engine->request_list)) |
| 2562 | return -ENOSPC; |
| 2563 | |
| 2564 | return i915_wait_request(target); |
| 2565 | } |
| 2566 | |
| 2567 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
| 2568 | { |
| 2569 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2570 | int remain_actual = ringbuf->size - ringbuf->tail; |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2571 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
| 2572 | int bytes = num_dwords * sizeof(u32); |
| 2573 | int total_bytes, wait_bytes; |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2574 | bool need_wrap = false; |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2575 | |
Chris Wilson | 0251a96 | 2016-04-28 09:56:47 +0100 | [diff] [blame] | 2576 | total_bytes = bytes + req->reserved_space; |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2577 | |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2578 | if (unlikely(bytes > remain_usable)) { |
| 2579 | /* |
| 2580 | * Not enough space for the basic request. So need to flush |
| 2581 | * out the remainder and then wait for base + reserved. |
| 2582 | */ |
| 2583 | wait_bytes = remain_actual + total_bytes; |
| 2584 | need_wrap = true; |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2585 | } else if (unlikely(total_bytes > remain_usable)) { |
| 2586 | /* |
| 2587 | * The base request will fit but the reserved space |
| 2588 | * falls off the end. So we don't need an immediate wrap |
| 2589 | * and only need to effectively wait for the reserved |
| 2590 | * size space from the start of ringbuffer. |
| 2591 | */ |
Chris Wilson | 0251a96 | 2016-04-28 09:56:47 +0100 | [diff] [blame] | 2592 | wait_bytes = remain_actual + req->reserved_space; |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2593 | } else { |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2594 | /* No wrapping required, just waiting. */ |
| 2595 | wait_bytes = total_bytes; |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2596 | } |
| 2597 | |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2598 | if (wait_bytes > ringbuf->space) { |
| 2599 | int ret = wait_for_space(req, wait_bytes); |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2600 | if (unlikely(ret)) |
| 2601 | return ret; |
John Harrison | 79bbcc2 | 2015-06-30 12:40:55 +0100 | [diff] [blame] | 2602 | |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2603 | intel_ring_update_space(ringbuf); |
Chris Wilson | e075a32 | 2016-05-13 11:57:22 +0100 | [diff] [blame] | 2604 | if (unlikely(ringbuf->space < wait_bytes)) |
| 2605 | return -EAGAIN; |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2606 | } |
| 2607 | |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2608 | if (unlikely(need_wrap)) { |
| 2609 | GEM_BUG_ON(remain_actual > ringbuf->space); |
| 2610 | GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size); |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2611 | |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2612 | /* Fill the tail with MI_NOOP */ |
| 2613 | memset(ringbuf->virtual_start + ringbuf->tail, |
| 2614 | 0, remain_actual); |
| 2615 | ringbuf->tail = 0; |
| 2616 | ringbuf->space -= remain_actual; |
| 2617 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2618 | |
Chris Wilson | 987046a | 2016-04-28 09:56:46 +0100 | [diff] [blame] | 2619 | ringbuf->space -= bytes; |
| 2620 | GEM_BUG_ON(ringbuf->space < 0); |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2621 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2622 | } |
| 2623 | |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2624 | /* Align the ring tail to a cacheline boundary */ |
John Harrison | bba09b1 | 2015-05-29 17:44:06 +0100 | [diff] [blame] | 2625 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2626 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2627 | struct intel_engine_cs *engine = req->engine; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2628 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2629 | int ret; |
| 2630 | |
| 2631 | if (num_dwords == 0) |
| 2632 | return 0; |
| 2633 | |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 2634 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2635 | ret = intel_ring_begin(req, num_dwords); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2636 | if (ret) |
| 2637 | return ret; |
| 2638 | |
| 2639 | while (num_dwords--) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2640 | intel_ring_emit(engine, MI_NOOP); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2641 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2642 | intel_ring_advance(engine); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2643 | |
| 2644 | return 0; |
| 2645 | } |
| 2646 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2647 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2648 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2649 | struct drm_i915_private *dev_priv = engine->i915; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2650 | |
Chris Wilson | 29dcb57 | 2016-04-07 07:29:13 +0100 | [diff] [blame] | 2651 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
| 2652 | * so long as the semaphore value in the register/page is greater |
| 2653 | * than the sync value), so whenever we reset the seqno, |
| 2654 | * so long as we reset the tracking semaphore value to 0, it will |
| 2655 | * always be before the next request's seqno. If we don't reset |
| 2656 | * the semaphore value, then when the seqno moves backwards all |
| 2657 | * future waits will complete instantly (causing rendering corruption). |
| 2658 | */ |
Tvrtko Ursulin | 7e22dbb | 2016-05-10 10:57:06 +0100 | [diff] [blame] | 2659 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2660 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
| 2661 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); |
Chris Wilson | d04bce4 | 2016-04-07 07:29:12 +0100 | [diff] [blame] | 2662 | if (HAS_VEBOX(dev_priv)) |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2663 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2664 | } |
Chris Wilson | a058d93 | 2016-04-07 07:29:15 +0100 | [diff] [blame] | 2665 | if (dev_priv->semaphore_obj) { |
| 2666 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; |
| 2667 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); |
| 2668 | void *semaphores = kmap(page); |
| 2669 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), |
| 2670 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); |
| 2671 | kunmap(page); |
| 2672 | } |
Chris Wilson | 29dcb57 | 2016-04-07 07:29:13 +0100 | [diff] [blame] | 2673 | memset(engine->semaphore.sync_seqno, 0, |
| 2674 | sizeof(engine->semaphore.sync_seqno)); |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 2675 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2676 | engine->set_seqno(engine, seqno); |
Chris Wilson | 0134712 | 2016-04-07 07:29:16 +0100 | [diff] [blame] | 2677 | engine->last_submitted_seqno = seqno; |
Chris Wilson | 29dcb57 | 2016-04-07 07:29:13 +0100 | [diff] [blame] | 2678 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2679 | engine->hangcheck.seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2680 | } |
| 2681 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2682 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2683 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2684 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2685 | struct drm_i915_private *dev_priv = engine->i915; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2686 | |
Chris Wilson | 76f8421 | 2016-06-30 15:33:45 +0100 | [diff] [blame] | 2687 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 2688 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2689 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2690 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2691 | /* Disable notification that the ring is IDLE. The GT |
| 2692 | * will then assume that it is busy and bring it out of rc6. |
| 2693 | */ |
Chris Wilson | 76f8421 | 2016-06-30 15:33:45 +0100 | [diff] [blame] | 2694 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 2695 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2696 | |
| 2697 | /* Clear the context id. Here be magic! */ |
Chris Wilson | 76f8421 | 2016-06-30 15:33:45 +0100 | [diff] [blame] | 2698 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2699 | |
| 2700 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Chris Wilson | 76f8421 | 2016-06-30 15:33:45 +0100 | [diff] [blame] | 2701 | if (intel_wait_for_register_fw(dev_priv, |
| 2702 | GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 2703 | GEN6_BSD_SLEEP_INDICATOR, |
| 2704 | 0, |
| 2705 | 50)) |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2706 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2707 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2708 | /* Now that the ring is fully powered up, update the tail */ |
Chris Wilson | 76f8421 | 2016-06-30 15:33:45 +0100 | [diff] [blame] | 2709 | I915_WRITE_FW(RING_TAIL(engine->mmio_base), value); |
| 2710 | POSTING_READ_FW(RING_TAIL(engine->mmio_base)); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2711 | |
| 2712 | /* Let the ring send IDLE messages to the GT again, |
| 2713 | * and so let it sleep to conserve power when idle. |
| 2714 | */ |
Chris Wilson | 76f8421 | 2016-06-30 15:33:45 +0100 | [diff] [blame] | 2715 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 2716 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 2717 | |
| 2718 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2719 | } |
| 2720 | |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 2721 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2722 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2723 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2724 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2725 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2726 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2727 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2728 | ret = intel_ring_begin(req, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2729 | if (ret) |
| 2730 | return ret; |
| 2731 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2732 | cmd = MI_FLUSH_DW; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2733 | if (INTEL_GEN(req->i915) >= 8) |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2734 | cmd += 1; |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2735 | |
| 2736 | /* We always require a command barrier so that subsequent |
| 2737 | * commands, such as breadcrumb interrupts, are strictly ordered |
| 2738 | * wrt the contents of the write cache being flushed to memory |
| 2739 | * (and thus being coherent from the CPU). |
| 2740 | */ |
| 2741 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
| 2742 | |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2743 | /* |
| 2744 | * Bspec vol 1c.5 - video engine command streamer: |
| 2745 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2746 | * operation is complete. This bit is only valid when the |
| 2747 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2748 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2749 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2750 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
| 2751 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2752 | intel_ring_emit(engine, cmd); |
| 2753 | intel_ring_emit(engine, |
| 2754 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2755 | if (INTEL_GEN(req->i915) >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2756 | intel_ring_emit(engine, 0); /* upper addr */ |
| 2757 | intel_ring_emit(engine, 0); /* value */ |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2758 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2759 | intel_ring_emit(engine, 0); |
| 2760 | intel_ring_emit(engine, MI_NOOP); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2761 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2762 | intel_ring_advance(engine); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2763 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2764 | } |
| 2765 | |
| 2766 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 2767 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2768 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2769 | unsigned dispatch_flags) |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2770 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2771 | struct intel_engine_cs *engine = req->engine; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2772 | bool ppgtt = USES_PPGTT(engine->dev) && |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2773 | !(dispatch_flags & I915_DISPATCH_SECURE); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2774 | int ret; |
| 2775 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2776 | ret = intel_ring_begin(req, 4); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2777 | if (ret) |
| 2778 | return ret; |
| 2779 | |
| 2780 | /* FIXME(BDW): Address space and security selectors. */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2781 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
Abdiel Janulgue | 919032e | 2015-06-16 13:39:40 +0300 | [diff] [blame] | 2782 | (dispatch_flags & I915_DISPATCH_RS ? |
| 2783 | MI_BATCH_RESOURCE_STREAMER : 0)); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2784 | intel_ring_emit(engine, lower_32_bits(offset)); |
| 2785 | intel_ring_emit(engine, upper_32_bits(offset)); |
| 2786 | intel_ring_emit(engine, MI_NOOP); |
| 2787 | intel_ring_advance(engine); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2788 | |
| 2789 | return 0; |
| 2790 | } |
| 2791 | |
| 2792 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 2793 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2794 | u64 offset, u32 len, |
| 2795 | unsigned dispatch_flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2796 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2797 | struct intel_engine_cs *engine = req->engine; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2798 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2799 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2800 | ret = intel_ring_begin(req, 2); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2801 | if (ret) |
| 2802 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2803 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2804 | intel_ring_emit(engine, |
Chris Wilson | 7707225 | 2014-09-10 12:18:27 +0100 | [diff] [blame] | 2805 | MI_BATCH_BUFFER_START | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2806 | (dispatch_flags & I915_DISPATCH_SECURE ? |
Abdiel Janulgue | 919032e | 2015-06-16 13:39:40 +0300 | [diff] [blame] | 2807 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
| 2808 | (dispatch_flags & I915_DISPATCH_RS ? |
| 2809 | MI_BATCH_RESOURCE_STREAMER : 0)); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2810 | /* bit0-7 is the length on GEN6+ */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2811 | intel_ring_emit(engine, offset); |
| 2812 | intel_ring_advance(engine); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2813 | |
| 2814 | return 0; |
| 2815 | } |
| 2816 | |
| 2817 | static int |
John Harrison | 53fddaf | 2015-05-29 17:44:02 +0100 | [diff] [blame] | 2818 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2819 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2820 | unsigned dispatch_flags) |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2821 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2822 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2823 | int ret; |
| 2824 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2825 | ret = intel_ring_begin(req, 2); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2826 | if (ret) |
| 2827 | return ret; |
| 2828 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2829 | intel_ring_emit(engine, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2830 | MI_BATCH_BUFFER_START | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2831 | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 2832 | 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2833 | /* bit0-7 is the length on GEN6+ */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2834 | intel_ring_emit(engine, offset); |
| 2835 | intel_ring_advance(engine); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2836 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2837 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2838 | } |
| 2839 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2840 | /* Blitter support (SandyBridge+) */ |
| 2841 | |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 2842 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2843 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2844 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2845 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2846 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2847 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2848 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 2849 | ret = intel_ring_begin(req, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2850 | if (ret) |
| 2851 | return ret; |
| 2852 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2853 | cmd = MI_FLUSH_DW; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2854 | if (INTEL_GEN(req->i915) >= 8) |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2855 | cmd += 1; |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2856 | |
| 2857 | /* We always require a command barrier so that subsequent |
| 2858 | * commands, such as breadcrumb interrupts, are strictly ordered |
| 2859 | * wrt the contents of the write cache being flushed to memory |
| 2860 | * (and thus being coherent from the CPU). |
| 2861 | */ |
| 2862 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
| 2863 | |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2864 | /* |
| 2865 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 2866 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2867 | * operation is complete. This bit is only valid when the |
| 2868 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2869 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2870 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2871 | cmd |= MI_INVALIDATE_TLB; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2872 | intel_ring_emit(engine, cmd); |
| 2873 | intel_ring_emit(engine, |
| 2874 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2875 | if (INTEL_GEN(req->i915) >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2876 | intel_ring_emit(engine, 0); /* upper addr */ |
| 2877 | intel_ring_emit(engine, 0); /* value */ |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2878 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2879 | intel_ring_emit(engine, 0); |
| 2880 | intel_ring_emit(engine, MI_NOOP); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2881 | } |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2882 | intel_ring_advance(engine); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2883 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2884 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2885 | } |
| 2886 | |
Tvrtko Ursulin | d9a6461 | 2016-06-29 16:09:27 +0100 | [diff] [blame] | 2887 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
| 2888 | struct intel_engine_cs *engine) |
| 2889 | { |
Tvrtko Ursulin | db3d401 | 2016-06-29 16:09:28 +0100 | [diff] [blame^] | 2890 | struct drm_i915_gem_object *obj; |
| 2891 | int ret; |
| 2892 | |
| 2893 | if (!i915_semaphore_is_enabled(dev_priv)) |
| 2894 | return; |
| 2895 | |
| 2896 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) { |
| 2897 | obj = i915_gem_object_create(dev_priv->dev, 4096); |
| 2898 | if (IS_ERR(obj)) { |
| 2899 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); |
| 2900 | i915.semaphores = 0; |
| 2901 | } else { |
| 2902 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 2903 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); |
| 2904 | if (ret != 0) { |
| 2905 | drm_gem_object_unreference(&obj->base); |
| 2906 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); |
| 2907 | i915.semaphores = 0; |
| 2908 | } else { |
| 2909 | dev_priv->semaphore_obj = obj; |
| 2910 | } |
| 2911 | } |
| 2912 | } |
| 2913 | |
Tvrtko Ursulin | d9a6461 | 2016-06-29 16:09:27 +0100 | [diff] [blame] | 2914 | if (!i915_semaphore_is_enabled(dev_priv)) |
| 2915 | return; |
| 2916 | |
| 2917 | if (INTEL_GEN(dev_priv) >= 8) { |
| 2918 | engine->semaphore.sync_to = gen8_ring_sync; |
| 2919 | engine->semaphore.signal = gen8_xcs_signal; |
| 2920 | GEN8_RING_SEMAPHORE_INIT(engine); |
| 2921 | } else if (INTEL_GEN(dev_priv) >= 6) { |
| 2922 | engine->semaphore.sync_to = gen6_ring_sync; |
| 2923 | engine->semaphore.signal = gen6_signal; |
| 2924 | } |
| 2925 | } |
| 2926 | |
Tvrtko Ursulin | 06a2fe2 | 2016-06-29 16:09:20 +0100 | [diff] [blame] | 2927 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
| 2928 | struct intel_engine_cs *engine) |
| 2929 | { |
Tvrtko Ursulin | 1d8a133 | 2016-06-29 16:09:25 +0100 | [diff] [blame] | 2930 | engine->init_hw = init_ring_common; |
Tvrtko Ursulin | 06a2fe2 | 2016-06-29 16:09:20 +0100 | [diff] [blame] | 2931 | engine->write_tail = ring_write_tail; |
Tvrtko Ursulin | 604096d | 2016-06-29 16:09:24 +0100 | [diff] [blame] | 2932 | engine->get_seqno = ring_get_seqno; |
| 2933 | engine->set_seqno = ring_set_seqno; |
Tvrtko Ursulin | 7445a2a | 2016-06-29 16:09:21 +0100 | [diff] [blame] | 2934 | |
Tvrtko Ursulin | 960ecaa | 2016-06-29 17:40:26 +0100 | [diff] [blame] | 2935 | if (INTEL_GEN(dev_priv) >= 8) { |
| 2936 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
| 2937 | engine->add_request = gen6_add_request; |
| 2938 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
| 2939 | } else if (INTEL_GEN(dev_priv) >= 6) { |
| 2940 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Tvrtko Ursulin | 7445a2a | 2016-06-29 16:09:21 +0100 | [diff] [blame] | 2941 | engine->add_request = gen6_add_request; |
Tvrtko Ursulin | cc54a82 | 2016-06-29 16:09:22 +0100 | [diff] [blame] | 2942 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
| 2943 | } else { |
Tvrtko Ursulin | 960ecaa | 2016-06-29 17:40:26 +0100 | [diff] [blame] | 2944 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
Tvrtko Ursulin | 7445a2a | 2016-06-29 16:09:21 +0100 | [diff] [blame] | 2945 | engine->add_request = i9xx_add_request; |
Tvrtko Ursulin | cc54a82 | 2016-06-29 16:09:22 +0100 | [diff] [blame] | 2946 | } |
Tvrtko Ursulin | b970032 | 2016-06-29 16:09:23 +0100 | [diff] [blame] | 2947 | |
| 2948 | if (INTEL_GEN(dev_priv) >= 8) { |
| 2949 | engine->irq_get = gen8_ring_get_irq; |
| 2950 | engine->irq_put = gen8_ring_put_irq; |
| 2951 | } else if (INTEL_GEN(dev_priv) >= 6) { |
| 2952 | engine->irq_get = gen6_ring_get_irq; |
| 2953 | engine->irq_put = gen6_ring_put_irq; |
| 2954 | } else if (INTEL_GEN(dev_priv) >= 5) { |
| 2955 | engine->irq_get = gen5_ring_get_irq; |
| 2956 | engine->irq_put = gen5_ring_put_irq; |
| 2957 | } else if (INTEL_GEN(dev_priv) >= 3) { |
| 2958 | engine->irq_get = i9xx_ring_get_irq; |
| 2959 | engine->irq_put = i9xx_ring_put_irq; |
| 2960 | } else { |
| 2961 | engine->irq_get = i8xx_ring_get_irq; |
| 2962 | engine->irq_put = i8xx_ring_put_irq; |
| 2963 | } |
Tvrtko Ursulin | d9a6461 | 2016-06-29 16:09:27 +0100 | [diff] [blame] | 2964 | |
| 2965 | intel_ring_init_semaphores(dev_priv, engine); |
Tvrtko Ursulin | 06a2fe2 | 2016-06-29 16:09:20 +0100 | [diff] [blame] | 2966 | } |
| 2967 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2968 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 2969 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2970 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2971 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2972 | struct drm_i915_gem_object *obj; |
| 2973 | int ret; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2974 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2975 | engine->name = "render ring"; |
| 2976 | engine->id = RCS; |
| 2977 | engine->exec_id = I915_EXEC_RENDER; |
Chris Wilson | 215a7e3 | 2016-04-29 13:18:23 +0100 | [diff] [blame] | 2978 | engine->hw_id = 0; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2979 | engine->mmio_base = RENDER_RING_BASE; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2980 | |
Tvrtko Ursulin | 06a2fe2 | 2016-06-29 16:09:20 +0100 | [diff] [blame] | 2981 | intel_ring_default_vfuncs(dev_priv, engine); |
| 2982 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2983 | if (INTEL_GEN(dev_priv) >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2984 | engine->init_context = intel_rcs_ctx_init; |
Chris Wilson | a58c01a | 2016-04-29 13:18:21 +0100 | [diff] [blame] | 2985 | engine->add_request = gen8_render_add_request; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2986 | engine->flush = gen8_render_ring_flush; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2987 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
Tvrtko Ursulin | db3d401 | 2016-06-29 16:09:28 +0100 | [diff] [blame^] | 2988 | if (i915_semaphore_is_enabled(dev_priv)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2989 | engine->semaphore.signal = gen8_rcs_signal; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2990 | } else if (INTEL_GEN(dev_priv) >= 6) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2991 | engine->init_context = intel_rcs_ctx_init; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2992 | engine->flush = gen7_render_ring_flush; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2993 | if (IS_GEN6(dev_priv)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2994 | engine->flush = gen6_render_ring_flush; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2995 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2996 | if (i915_semaphore_is_enabled(dev_priv)) { |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2997 | /* |
| 2998 | * The current semaphore is only applied on pre-gen8 |
| 2999 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 3000 | * platform. So the semaphore between RCS and VCS2 is |
| 3001 | * initialized as INVALID. Gen8 will initialize the |
| 3002 | * sema between VCS2 and RCS later. |
| 3003 | */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3004 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 3005 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 3006 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; |
| 3007 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; |
| 3008 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 3009 | engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; |
| 3010 | engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; |
| 3011 | engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; |
| 3012 | engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; |
| 3013 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3014 | } |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3015 | } else if (IS_GEN5(dev_priv)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3016 | engine->add_request = pc_render_add_request; |
| 3017 | engine->flush = gen4_render_ring_flush; |
| 3018 | engine->get_seqno = pc_render_get_seqno; |
| 3019 | engine->set_seqno = pc_render_set_seqno; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3020 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 3021 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 3022 | } else { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3023 | if (INTEL_GEN(dev_priv) < 4) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3024 | engine->flush = gen2_render_ring_flush; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 3025 | else |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3026 | engine->flush = gen4_render_ring_flush; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3027 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3028 | } |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3029 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3030 | if (IS_HASWELL(dev_priv)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3031 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3032 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3033 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; |
Tvrtko Ursulin | 960ecaa | 2016-06-29 17:40:26 +0100 | [diff] [blame] | 3034 | else if (INTEL_GEN(dev_priv) <= 3) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3035 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; |
| 3036 | engine->init_hw = init_render_ring; |
| 3037 | engine->cleanup = render_ring_cleanup; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 3038 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 3039 | /* Workaround batchbuffer to combat CS tlb bug. */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3040 | if (HAS_BROKEN_CS_TLB(dev_priv)) { |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 3041 | obj = i915_gem_object_create(dev, I830_WA_SIZE); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 3042 | if (IS_ERR(obj)) { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 3043 | DRM_ERROR("Failed to allocate batch bo\n"); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 3044 | return PTR_ERR(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 3045 | } |
| 3046 | |
Daniel Vetter | be1fa12 | 2014-02-14 14:01:14 +0100 | [diff] [blame] | 3047 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 3048 | if (ret != 0) { |
| 3049 | drm_gem_object_unreference(&obj->base); |
| 3050 | DRM_ERROR("Failed to ping batch bo\n"); |
| 3051 | return ret; |
| 3052 | } |
| 3053 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3054 | engine->scratch.obj = obj; |
| 3055 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 3056 | } |
| 3057 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3058 | ret = intel_init_ring_buffer(dev, engine); |
Daniel Vetter | 99be1df | 2014-11-20 00:33:06 +0100 | [diff] [blame] | 3059 | if (ret) |
| 3060 | return ret; |
| 3061 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3062 | if (INTEL_GEN(dev_priv) >= 5) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3063 | ret = intel_init_pipe_control(engine); |
Daniel Vetter | 99be1df | 2014-11-20 00:33:06 +0100 | [diff] [blame] | 3064 | if (ret) |
| 3065 | return ret; |
| 3066 | } |
| 3067 | |
| 3068 | return 0; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3069 | } |
| 3070 | |
| 3071 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 3072 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 3073 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 3074 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3075 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3076 | engine->name = "bsd ring"; |
| 3077 | engine->id = VCS; |
| 3078 | engine->exec_id = I915_EXEC_BSD; |
Chris Wilson | 215a7e3 | 2016-04-29 13:18:23 +0100 | [diff] [blame] | 3079 | engine->hw_id = 1; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 3080 | |
Tvrtko Ursulin | 06a2fe2 | 2016-06-29 16:09:20 +0100 | [diff] [blame] | 3081 | intel_ring_default_vfuncs(dev_priv, engine); |
| 3082 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3083 | if (INTEL_GEN(dev_priv) >= 6) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3084 | engine->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 3085 | /* gen6 bsd needs a special wa for tail updates */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3086 | if (IS_GEN6(dev_priv)) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3087 | engine->write_tail = gen6_bsd_ring_write_tail; |
| 3088 | engine->flush = gen6_bsd_ring_flush; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3089 | if (INTEL_GEN(dev_priv) >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3090 | engine->irq_enable_mask = |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3091 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3092 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3093 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3094 | if (i915_semaphore_is_enabled(dev_priv)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3095 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 3096 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 3097 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; |
| 3098 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; |
| 3099 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 3100 | engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; |
| 3101 | engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; |
| 3102 | engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; |
| 3103 | engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; |
| 3104 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3105 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3106 | } |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 3107 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3108 | engine->mmio_base = BSD_RING_BASE; |
| 3109 | engine->flush = bsd_ring_flush; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3110 | if (IS_GEN5(dev_priv)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3111 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 3112 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3113 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 3114 | } |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 3115 | } |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 3116 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3117 | return intel_init_ring_buffer(dev, engine); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3118 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3119 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3120 | /** |
Damien Lespiau | 6265992 | 2015-01-29 14:13:40 +0000 | [diff] [blame] | 3121 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3122 | */ |
| 3123 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) |
| 3124 | { |
| 3125 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 3126 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3127 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3128 | engine->name = "bsd2 ring"; |
| 3129 | engine->id = VCS2; |
| 3130 | engine->exec_id = I915_EXEC_BSD; |
Chris Wilson | 215a7e3 | 2016-04-29 13:18:23 +0100 | [diff] [blame] | 3131 | engine->hw_id = 4; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3132 | engine->mmio_base = GEN8_BSD2_RING_BASE; |
Tvrtko Ursulin | 06a2fe2 | 2016-06-29 16:09:20 +0100 | [diff] [blame] | 3133 | |
| 3134 | intel_ring_default_vfuncs(dev_priv, engine); |
| 3135 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3136 | engine->flush = gen6_bsd_ring_flush; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3137 | engine->irq_enable_mask = |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3138 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3139 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3140 | return intel_init_ring_buffer(dev, engine); |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 3141 | } |
| 3142 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3143 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 3144 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 3145 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 3146 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3147 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3148 | engine->name = "blitter ring"; |
| 3149 | engine->id = BCS; |
| 3150 | engine->exec_id = I915_EXEC_BLT; |
Chris Wilson | 215a7e3 | 2016-04-29 13:18:23 +0100 | [diff] [blame] | 3151 | engine->hw_id = 2; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3152 | engine->mmio_base = BLT_RING_BASE; |
Tvrtko Ursulin | 06a2fe2 | 2016-06-29 16:09:20 +0100 | [diff] [blame] | 3153 | |
| 3154 | intel_ring_default_vfuncs(dev_priv, engine); |
| 3155 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3156 | engine->flush = gen6_ring_flush; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3157 | if (INTEL_GEN(dev_priv) >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3158 | engine->irq_enable_mask = |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3159 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3160 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3161 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3162 | if (i915_semaphore_is_enabled(dev_priv)) { |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3163 | /* |
| 3164 | * The current semaphore is only applied on pre-gen8 |
| 3165 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 3166 | * platform. So the semaphore between BCS and VCS2 is |
| 3167 | * initialized as INVALID. Gen8 will initialize the |
| 3168 | * sema between BCS and VCS2 later. |
| 3169 | */ |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3170 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 3171 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 3172 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 3173 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; |
| 3174 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 3175 | engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; |
| 3176 | engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; |
| 3177 | engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; |
| 3178 | engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; |
| 3179 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3180 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3181 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3182 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3183 | return intel_init_ring_buffer(dev, engine); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3184 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3185 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3186 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 3187 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 3188 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 3189 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3190 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3191 | engine->name = "video enhancement ring"; |
| 3192 | engine->id = VECS; |
| 3193 | engine->exec_id = I915_EXEC_VEBOX; |
Chris Wilson | 215a7e3 | 2016-04-29 13:18:23 +0100 | [diff] [blame] | 3194 | engine->hw_id = 3; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3195 | engine->mmio_base = VEBOX_RING_BASE; |
Tvrtko Ursulin | 06a2fe2 | 2016-06-29 16:09:20 +0100 | [diff] [blame] | 3196 | |
| 3197 | intel_ring_default_vfuncs(dev_priv, engine); |
| 3198 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3199 | engine->flush = gen6_ring_flush; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3200 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3201 | if (INTEL_GEN(dev_priv) >= 8) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3202 | engine->irq_enable_mask = |
Daniel Vetter | 40c499f | 2013-11-07 21:40:39 -0800 | [diff] [blame] | 3203 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3204 | } else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3205 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| 3206 | engine->irq_get = hsw_vebox_get_irq; |
| 3207 | engine->irq_put = hsw_vebox_put_irq; |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3208 | if (i915_semaphore_is_enabled(dev_priv)) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3209 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 3210 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 3211 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 3212 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 3213 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 3214 | engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; |
| 3215 | engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; |
| 3216 | engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; |
| 3217 | engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; |
| 3218 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 3219 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3220 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3221 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3222 | return intel_init_ring_buffer(dev, engine); |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 3223 | } |
| 3224 | |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3225 | int |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 3226 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3227 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 3228 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3229 | int ret; |
| 3230 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3231 | if (!engine->gpu_caches_dirty) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3232 | return 0; |
| 3233 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3234 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3235 | if (ret) |
| 3236 | return ret; |
| 3237 | |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 3238 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3239 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3240 | engine->gpu_caches_dirty = false; |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3241 | return 0; |
| 3242 | } |
| 3243 | |
| 3244 | int |
John Harrison | 2f20055 | 2015-05-29 17:43:53 +0100 | [diff] [blame] | 3245 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3246 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 3247 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3248 | uint32_t flush_domains; |
| 3249 | int ret; |
| 3250 | |
| 3251 | flush_domains = 0; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3252 | if (engine->gpu_caches_dirty) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3253 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 3254 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3255 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3256 | if (ret) |
| 3257 | return ret; |
| 3258 | |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 3259 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3260 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3261 | engine->gpu_caches_dirty = false; |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 3262 | return 0; |
| 3263 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3264 | |
| 3265 | void |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 3266 | intel_stop_engine(struct intel_engine_cs *engine) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3267 | { |
| 3268 | int ret; |
| 3269 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 3270 | if (!intel_engine_initialized(engine)) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3271 | return; |
| 3272 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3273 | ret = intel_engine_idle(engine); |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 3274 | if (ret) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3275 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3276 | engine->name, ret); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3277 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3278 | stop_ring(engine); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 3279 | } |