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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
34
Jesse Barnes585fb112008-07-29 11:54:06 -070035#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080037#include "intel_ringbuffer.h"
Oscar Mateob20385f2014-07-24 17:04:10 +010038#include "intel_lrc.h"
Ben Widawsky0260c422014-03-22 22:47:21 -070039#include "i915_gem_gtt.h"
Oscar Mateo564ddb22014-08-21 11:40:54 +010040#include "i915_gem_render_state.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070041#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070042#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010043#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020044#include <drm/intel-gtt.h>
Daniel Vetterba8286f2014-09-11 07:43:25 +020045#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
Daniel Vetterd9fc9412014-09-23 15:46:53 +020046#include <drm/drm_gem.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020047#include <linux/backlight.h>
Chris Wilson5cc9ed42014-05-16 14:22:37 +010048#include <linux/hashtable.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070049#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020050#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010051#include <linux/pm_qos.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070052
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/* General customization:
54 */
55
Linus Torvalds1da177e2005-04-16 15:20:36 -070056#define DRIVER_NAME "i915"
57#define DRIVER_DESC "Intel Graphics"
Daniel Vettere7f1d0b2014-11-21 10:37:14 +010058#define DRIVER_DATE "20141121"
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Mika Kuoppalac883ef12014-10-28 17:32:30 +020060#undef WARN_ON
61#define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
62
Jesse Barnes317c35d2008-08-25 15:11:06 -070063enum pipe {
Jesse Barnes752aa882013-10-31 18:55:49 +020064 INVALID_PIPE = -1,
Jesse Barnes317c35d2008-08-25 15:11:06 -070065 PIPE_A = 0,
66 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080067 PIPE_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020068 _PIPE_EDP,
69 I915_MAX_PIPES = _PIPE_EDP
Jesse Barnes317c35d2008-08-25 15:11:06 -070070};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080071#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -070072
Paulo Zanonia5c961d2012-10-24 15:59:34 -020073enum transcoder {
74 TRANSCODER_A = 0,
75 TRANSCODER_B,
76 TRANSCODER_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020077 TRANSCODER_EDP,
78 I915_MAX_TRANSCODERS
Paulo Zanonia5c961d2012-10-24 15:59:34 -020079};
80#define transcoder_name(t) ((t) + 'A')
81
Damien Lespiau84139d12014-03-28 00:18:32 +053082/*
83 * This is the maximum (across all platforms) number of planes (primary +
84 * sprites) that can be active at the same time on one pipe.
85 *
86 * This value doesn't count the cursor plane.
87 */
88#define I915_MAX_PLANES 3
89
Jesse Barnes80824002009-09-10 15:28:06 -070090enum plane {
91 PLANE_A = 0,
92 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080093 PLANE_C,
Jesse Barnes80824002009-09-10 15:28:06 -070094};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080095#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -080096
Damien Lespiaud615a162014-03-03 17:31:48 +000097#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
Ville Syrjälä06da8da2013-04-17 17:48:51 +030098
Eugeni Dodonov2b139522012-03-29 12:32:22 -030099enum port {
100 PORT_A = 0,
101 PORT_B,
102 PORT_C,
103 PORT_D,
104 PORT_E,
105 I915_MAX_PORTS
106};
107#define port_name(p) ((p) + 'A')
108
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300109#define I915_NUM_PHYS_VLV 2
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800110
111enum dpio_channel {
112 DPIO_CH0,
113 DPIO_CH1
114};
115
116enum dpio_phy {
117 DPIO_PHY0,
118 DPIO_PHY1
119};
120
Paulo Zanonib97186f2013-05-03 12:15:36 -0300121enum intel_display_power_domain {
122 POWER_DOMAIN_PIPE_A,
123 POWER_DOMAIN_PIPE_B,
124 POWER_DOMAIN_PIPE_C,
125 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
126 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
127 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
128 POWER_DOMAIN_TRANSCODER_A,
129 POWER_DOMAIN_TRANSCODER_B,
130 POWER_DOMAIN_TRANSCODER_C,
Imre Deakf52e3532013-10-16 17:25:48 +0300131 POWER_DOMAIN_TRANSCODER_EDP,
Imre Deak319be8a2014-03-04 19:22:57 +0200132 POWER_DOMAIN_PORT_DDI_A_2_LANES,
133 POWER_DOMAIN_PORT_DDI_A_4_LANES,
134 POWER_DOMAIN_PORT_DDI_B_2_LANES,
135 POWER_DOMAIN_PORT_DDI_B_4_LANES,
136 POWER_DOMAIN_PORT_DDI_C_2_LANES,
137 POWER_DOMAIN_PORT_DDI_C_4_LANES,
138 POWER_DOMAIN_PORT_DDI_D_2_LANES,
139 POWER_DOMAIN_PORT_DDI_D_4_LANES,
140 POWER_DOMAIN_PORT_DSI,
141 POWER_DOMAIN_PORT_CRT,
142 POWER_DOMAIN_PORT_OTHER,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300143 POWER_DOMAIN_VGA,
Imre Deakfbeeaa22013-11-25 17:15:28 +0200144 POWER_DOMAIN_AUDIO,
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -0300145 POWER_DOMAIN_PLLS,
Imre Deakbaa70702013-10-25 17:36:48 +0300146 POWER_DOMAIN_INIT,
Imre Deakbddc7642013-10-16 17:25:49 +0300147
148 POWER_DOMAIN_NUM,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300149};
150
151#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
152#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
153 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300154#define POWER_DOMAIN_TRANSCODER(tran) \
155 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
156 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300157
Egbert Eich1d843f92013-02-25 12:06:49 -0500158enum hpd_pin {
159 HPD_NONE = 0,
160 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
161 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
162 HPD_CRT,
163 HPD_SDVO_B,
164 HPD_SDVO_C,
165 HPD_PORT_B,
166 HPD_PORT_C,
167 HPD_PORT_D,
168 HPD_NUM_PINS
169};
170
Chris Wilson2a2d5482012-12-03 11:49:06 +0000171#define I915_GEM_GPU_DOMAINS \
172 (I915_GEM_DOMAIN_RENDER | \
173 I915_GEM_DOMAIN_SAMPLER | \
174 I915_GEM_DOMAIN_COMMAND | \
175 I915_GEM_DOMAIN_INSTRUCTION | \
176 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700177
Damien Lespiau055e3932014-08-18 13:49:10 +0100178#define for_each_pipe(__dev_priv, __p) \
179 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
Damien Lespiau2d025a52014-09-04 12:27:43 +0100180#define for_each_plane(pipe, p) \
181 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
Damien Lespiaud615a162014-03-03 17:31:48 +0000182#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800183
Damien Lespiaud79b8142014-05-13 23:32:23 +0100184#define for_each_crtc(dev, crtc) \
185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
186
Damien Lespiaud063ae42014-05-13 23:32:21 +0100187#define for_each_intel_crtc(dev, intel_crtc) \
188 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
189
Damien Lespiaub2784e12014-08-05 11:29:37 +0100190#define for_each_intel_encoder(dev, intel_encoder) \
191 list_for_each_entry(intel_encoder, \
192 &(dev)->mode_config.encoder_list, \
193 base.head)
194
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200195#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
196 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
197 if ((intel_encoder)->base.crtc == (__crtc))
198
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800199#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
200 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
201 if ((intel_connector)->base.encoder == (__encoder))
202
Borun Fub04c5bd2014-07-12 10:02:27 +0530203#define for_each_power_domain(domain, mask) \
204 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
205 if ((1 << (domain)) & (mask))
206
Daniel Vettere7b903d2013-06-05 13:34:14 +0200207struct drm_i915_private;
Chris Wilsonad46cb52014-08-07 14:20:40 +0100208struct i915_mm_struct;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100209struct i915_mmu_object;
Daniel Vettere7b903d2013-06-05 13:34:14 +0200210
Daniel Vettere2b78262013-06-07 23:10:03 +0200211enum intel_dpll_id {
212 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
213 /* real shared dpll ids must be >= 0 */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300214 DPLL_ID_PCH_PLL_A = 0,
215 DPLL_ID_PCH_PLL_B = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000216 /* hsw/bdw */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300217 DPLL_ID_WRPLL1 = 0,
218 DPLL_ID_WRPLL2 = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000219 /* skl */
220 DPLL_ID_SKL_DPLL1 = 0,
221 DPLL_ID_SKL_DPLL2 = 1,
222 DPLL_ID_SKL_DPLL3 = 2,
Daniel Vettere2b78262013-06-07 23:10:03 +0200223};
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000224#define I915_NUM_PLLS 3
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100225
Daniel Vetter53589012013-06-05 13:34:16 +0200226struct intel_dpll_hw_state {
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100227 /* i9xx, pch plls */
Daniel Vetter66e985c2013-06-05 13:34:20 +0200228 uint32_t dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +0200229 uint32_t dpll_md;
Daniel Vetter66e985c2013-06-05 13:34:20 +0200230 uint32_t fp0;
231 uint32_t fp1;
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100232
233 /* hsw, bdw */
Daniel Vetterd452c5b2014-07-04 11:27:39 -0300234 uint32_t wrpll;
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +0000235
236 /* skl */
237 /*
238 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
239 * lower part of crtl1 and they get shifted into position when writing
240 * the register. This allows us to easily compare the state to share
241 * the DPLL.
242 */
243 uint32_t ctrl1;
244 /* HDMI only, 0 when used for DP */
245 uint32_t cfgcr1, cfgcr2;
Daniel Vetter53589012013-06-05 13:34:16 +0200246};
247
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200248struct intel_shared_dpll_config {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +0200249 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200250 struct intel_dpll_hw_state hw_state;
251};
252
253struct intel_shared_dpll {
254 struct intel_shared_dpll_config config;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +0200255 struct intel_shared_dpll_config *new_config;
256
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 int active; /* count of number of active CRTCs (i.e. DPMS on) */
258 bool on; /* is the PLL actually active? Disabled during modeset */
Daniel Vetter46edb022013-06-05 13:34:12 +0200259 const char *name;
260 /* should match the index in the dev_priv->shared_dplls array */
261 enum intel_dpll_id id;
Daniel Vetter96f61282014-06-25 22:01:58 +0300262 /* The mode_set hook is optional and should be used together with the
263 * intel_prepare_shared_dpll function. */
Daniel Vetter15bdd4c2013-06-05 13:34:23 +0200264 void (*mode_set)(struct drm_i915_private *dev_priv,
265 struct intel_shared_dpll *pll);
Daniel Vettere7b903d2013-06-05 13:34:14 +0200266 void (*enable)(struct drm_i915_private *dev_priv,
267 struct intel_shared_dpll *pll);
268 void (*disable)(struct drm_i915_private *dev_priv,
269 struct intel_shared_dpll *pll);
Daniel Vetter53589012013-06-05 13:34:16 +0200270 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
271 struct intel_shared_dpll *pll,
272 struct intel_dpll_hw_state *hw_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000275#define SKL_DPLL0 0
276#define SKL_DPLL1 1
277#define SKL_DPLL2 2
278#define SKL_DPLL3 3
279
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100280/* Used by dp and fdi links */
281struct intel_link_m_n {
282 uint32_t tu;
283 uint32_t gmch_m;
284 uint32_t gmch_n;
285 uint32_t link_m;
286 uint32_t link_n;
287};
288
289void intel_link_compute_m_n(int bpp, int nlanes,
290 int pixel_clock, int link_clock,
291 struct intel_link_m_n *m_n);
292
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293/* Interface history:
294 *
295 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100296 * 1.2: Add Power Management
297 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100298 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000299 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000300 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
301 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302 */
303#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000304#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305#define DRIVER_PATCHLEVEL 0
306
Chris Wilson23bc5982010-09-29 16:10:57 +0100307#define WATCH_LISTS 0
Eric Anholt673a3942008-07-30 12:06:12 -0700308
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700309struct opregion_header;
310struct opregion_acpi;
311struct opregion_swsci;
312struct opregion_asle;
313
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100314struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700315 struct opregion_header __iomem *header;
316 struct opregion_acpi __iomem *acpi;
317 struct opregion_swsci __iomem *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300318 u32 swsci_gbda_sub_functions;
319 u32 swsci_sbcb_sub_functions;
Ben Widawsky5bc44182012-04-16 14:07:42 -0700320 struct opregion_asle __iomem *asle;
321 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000322 u32 __iomem *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200323 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100324};
Chris Wilson44834a62010-08-19 16:09:23 +0100325#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100326
Chris Wilson6ef3d422010-08-04 20:26:07 +0100327struct intel_overlay;
328struct intel_overlay_error_state;
329
Jesse Barnesde151cf2008-11-12 10:03:55 -0800330#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300331#define I915_MAX_NUM_FENCES 32
332/* 32 fences + sign bit for FENCE_REG_NONE */
333#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800334
335struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200336 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000337 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100338 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800339};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000340
yakui_zhao9b9d1722009-05-31 17:17:17 +0800341struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100342 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800343 u8 dvo_port;
344 u8 slave_addr;
345 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100346 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400347 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800348};
349
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000350struct intel_display_error_state;
351
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700352struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200353 struct kref ref;
Ben Widawsky585b0282014-01-30 00:19:37 -0800354 struct timeval time;
355
Mika Kuoppalacb383002014-02-25 17:11:25 +0200356 char error_msg[128];
Mika Kuoppala48b031e2014-02-25 17:11:27 +0200357 u32 reset_count;
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200358 u32 suspend_count;
Mika Kuoppalacb383002014-02-25 17:11:25 +0200359
Ben Widawsky585b0282014-01-30 00:19:37 -0800360 /* Generic register state */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700361 u32 eir;
362 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700363 u32 ier;
Rodrigo Vivi885ea5a2014-08-05 10:07:13 -0700364 u32 gtier[4];
Ben Widawskyb9a39062012-06-04 14:42:52 -0700365 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000366 u32 derrmr;
367 u32 forcewake;
Ben Widawsky585b0282014-01-30 00:19:37 -0800368 u32 error; /* gen6+ */
369 u32 err_int; /* gen7 */
370 u32 done_reg;
Ben Widawsky91ec5d12014-01-30 00:19:39 -0800371 u32 gac_eco;
372 u32 gam_ecochk;
373 u32 gab_ctl;
374 u32 gfx_mode;
Ben Widawsky585b0282014-01-30 00:19:37 -0800375 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Ben Widawsky585b0282014-01-30 00:19:37 -0800376 u64 fence[I915_MAX_NUM_FENCES];
377 struct intel_overlay_error_state *overlay;
378 struct intel_display_error_state *display;
Ben Widawsky0ca36d72014-06-30 09:53:41 -0700379 struct drm_i915_error_object *semaphore_obj;
Ben Widawsky585b0282014-01-30 00:19:37 -0800380
Chris Wilson52d39a22012-02-15 11:25:37 +0000381 struct drm_i915_error_ring {
Chris Wilson372fbb82014-01-27 13:52:34 +0000382 bool valid;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800383 /* Software tracked state */
384 bool waiting;
385 int hangcheck_score;
386 enum intel_ring_hangcheck_action hangcheck_action;
387 int num_requests;
388
389 /* our own tracking of ring head and tail */
390 u32 cpu_ring_head;
391 u32 cpu_ring_tail;
392
393 u32 semaphore_seqno[I915_NUM_RINGS - 1];
394
395 /* Register state */
396 u32 tail;
397 u32 head;
398 u32 ctl;
399 u32 hws;
400 u32 ipeir;
401 u32 ipehr;
402 u32 instdone;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800403 u32 bbstate;
404 u32 instpm;
405 u32 instps;
406 u32 seqno;
407 u64 bbaddr;
Chris Wilson50877442014-03-21 12:41:53 +0000408 u64 acthd;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800409 u32 fault_reg;
Ben Widawsky13ffadd2014-04-01 16:31:07 -0700410 u64 faddr;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800411 u32 rc_psmi; /* sleep state */
412 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
413
Chris Wilson52d39a22012-02-15 11:25:37 +0000414 struct drm_i915_error_object {
415 int page_count;
416 u32 gtt_offset;
417 u32 *pages[0];
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200418 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800419
Chris Wilson52d39a22012-02-15 11:25:37 +0000420 struct drm_i915_error_request {
421 long jiffies;
422 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000423 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000424 } *requests;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800425
426 struct {
427 u32 gfx_mode;
428 union {
429 u64 pdp[4];
430 u32 pp_dir_base;
431 };
432 } vm_info;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200433
434 pid_t pid;
435 char comm[TASK_COMM_LEN];
Chris Wilson52d39a22012-02-15 11:25:37 +0000436 } ring[I915_NUM_RINGS];
Chris Wilson3a448732014-08-12 20:05:47 +0100437
Chris Wilson9df30792010-02-18 10:24:56 +0000438 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000439 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000440 u32 name;
Chris Wilson0201f1e2012-07-20 12:41:01 +0100441 u32 rseqno, wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000442 u32 gtt_offset;
443 u32 read_domains;
444 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200445 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000446 s32 pinned:2;
447 u32 tiling:2;
448 u32 dirty:1;
449 u32 purgeable:1;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100450 u32 userptr:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100451 s32 ring:4;
Chris Wilsonf56383c2013-09-25 10:23:19 +0100452 u32 cache_level:3;
Ben Widawsky95f53012013-07-31 17:00:15 -0700453 } **active_bo, **pinned_bo;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800454
Ben Widawsky95f53012013-07-31 17:00:15 -0700455 u32 *active_bo_count, *pinned_bo_count;
Chris Wilson3a448732014-08-12 20:05:47 +0100456 u32 vm_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700457};
458
Jani Nikula7bd688c2013-11-08 16:48:56 +0200459struct intel_connector;
Jani Nikula820d2d72014-10-27 16:26:47 +0200460struct intel_encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100461struct intel_crtc_config;
Jesse Barnes46f297f2014-03-07 08:57:48 -0800462struct intel_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100463struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200464struct intel_limit;
465struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100466
Jesse Barnese70236a2009-09-21 10:42:27 -0700467struct drm_i915_display_funcs {
Adam Jacksonee5382a2010-04-23 11:17:39 -0400468 bool (*fbc_enabled)(struct drm_device *dev);
Ville Syrjälä993495a2013-12-12 17:27:40 +0200469 void (*enable_fbc)(struct drm_crtc *crtc);
Jesse Barnese70236a2009-09-21 10:42:27 -0700470 void (*disable_fbc)(struct drm_device *dev);
471 int (*get_display_clock_speed)(struct drm_device *dev);
472 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200473 /**
474 * find_dpll() - Find the best values for the PLL
475 * @limit: limits for the PLL
476 * @crtc: current CRTC
477 * @target: target frequency in kHz
478 * @refclk: reference clock frequency in kHz
479 * @match_clock: if provided, @best_clock P divider must
480 * match the P divider from @match_clock
481 * used for LVDS downclocking
482 * @best_clock: best PLL values found
483 *
484 * Returns true on success, false on failure.
485 */
486 bool (*find_dpll)(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300487 struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200488 int target, int refclk,
489 struct dpll *match_clock,
490 struct dpll *best_clock);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300491 void (*update_wm)(struct drm_crtc *crtc);
Ville Syrjäläadf3d352013-08-06 22:24:11 +0300492 void (*update_sprite_wm)(struct drm_plane *plane,
493 struct drm_crtc *crtc,
Damien Lespiaued57cb82014-07-15 09:21:24 +0200494 uint32_t sprite_width, uint32_t sprite_height,
495 int pixel_size, bool enable, bool scaled);
Daniel Vetter47fab732012-10-26 10:58:18 +0200496 void (*modeset_global_resources)(struct drm_device *dev);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100497 /* Returns the active state of the crtc, and if the crtc is active,
498 * fills out the pipe-config with the hw state. */
499 bool (*get_pipe_config)(struct intel_crtc *,
500 struct intel_crtc_config *);
Jesse Barnes46f297f2014-03-07 08:57:48 -0800501 void (*get_plane_config)(struct intel_crtc *,
502 struct intel_plane_config *);
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +0200503 int (*crtc_compute_clock)(struct intel_crtc *crtc);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200504 void (*crtc_enable)(struct drm_crtc *crtc);
505 void (*crtc_disable)(struct drm_crtc *crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100506 void (*off)(struct drm_crtc *crtc);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200507 void (*audio_codec_enable)(struct drm_connector *connector,
508 struct intel_encoder *encoder,
509 struct drm_display_mode *mode);
510 void (*audio_codec_disable)(struct intel_encoder *encoder);
Jesse Barnes674cf962011-04-28 14:27:04 -0700511 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700512 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700513 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
514 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700515 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100516 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -0700517 uint32_t flags);
Daniel Vetter29b9bde2014-04-24 23:55:01 +0200518 void (*update_primary_plane)(struct drm_crtc *crtc,
519 struct drm_framebuffer *fb,
520 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100521 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700522 /* clock updates for mode set */
523 /* cursor updates */
524 /* render clock increase/decrease */
525 /* display clock increase/decrease */
526 /* pll clock increase/decrease */
Jani Nikula7bd688c2013-11-08 16:48:56 +0200527
Ville Syrjälä6517d272014-11-07 11:16:02 +0200528 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
Jani Nikula7bd688c2013-11-08 16:48:56 +0200529 uint32_t (*get_backlight)(struct intel_connector *connector);
530 void (*set_backlight)(struct intel_connector *connector,
531 uint32_t level);
532 void (*disable_backlight)(struct intel_connector *connector);
533 void (*enable_backlight)(struct intel_connector *connector);
Jesse Barnese70236a2009-09-21 10:42:27 -0700534};
535
Chris Wilson907b28c2013-07-19 20:36:52 +0100536struct intel_uncore_funcs {
Deepak Sc8d9a592013-11-23 14:55:42 +0530537 void (*force_wake_get)(struct drm_i915_private *dev_priv,
538 int fw_engine);
539 void (*force_wake_put)(struct drm_i915_private *dev_priv,
540 int fw_engine);
Ben Widawsky0b274482013-10-04 21:22:51 -0700541
542 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
543 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
544 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
545 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
546
547 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
548 uint8_t val, bool trace);
549 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
550 uint16_t val, bool trace);
551 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
552 uint32_t val, bool trace);
553 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
554 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300555};
556
Chris Wilson907b28c2013-07-19 20:36:52 +0100557struct intel_uncore {
558 spinlock_t lock; /** lock is also taken in irq contexts. */
559
560 struct intel_uncore_funcs funcs;
561
562 unsigned fifo_count;
563 unsigned forcewake_count;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100564
Deepak S940aece2013-11-23 14:55:43 +0530565 unsigned fw_rendercount;
566 unsigned fw_mediacount;
Zhe Wang38cff0b2014-11-04 17:07:04 +0000567 unsigned fw_blittercount;
Deepak S940aece2013-11-23 14:55:43 +0530568
Chris Wilson82326442014-03-05 12:00:39 +0000569 struct timer_list force_wake_timer;
Chris Wilson907b28c2013-07-19 20:36:52 +0100570};
571
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100572#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
573 func(is_mobile) sep \
574 func(is_i85x) sep \
575 func(is_i915g) sep \
576 func(is_i945gm) sep \
577 func(is_g33) sep \
578 func(need_gfx_hws) sep \
579 func(is_g4x) sep \
580 func(is_pineview) sep \
581 func(is_broadwater) sep \
582 func(is_crestline) sep \
583 func(is_ivybridge) sep \
584 func(is_valleyview) sep \
585 func(is_haswell) sep \
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530586 func(is_skylake) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700587 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100588 func(has_fbc) sep \
589 func(has_pipe_cxsr) sep \
590 func(has_hotplug) sep \
591 func(cursor_needs_physical) sep \
592 func(has_overlay) sep \
593 func(overlay_needs_physical) sep \
594 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100595 func(has_llc) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100596 func(has_ddi) sep \
597 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200598
Damien Lespiaua587f772013-04-22 18:40:38 +0100599#define DEFINE_FLAG(name) u8 name:1
600#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200601
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500602struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200603 u32 display_mmio_offset;
Chris Wilson87f1f462014-08-09 19:18:42 +0100604 u16 device_id;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700605 u8 num_pipes:3;
Damien Lespiaud615a162014-03-03 17:31:48 +0000606 u8 num_sprites[I915_MAX_PIPES];
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000607 u8 gen;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700608 u8 ring_mask; /* Rings supported by the HW */
Damien Lespiaua587f772013-04-22 18:40:38 +0100609 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200610 /* Register offsets for the various display pipes and transcoders */
611 int pipe_offsets[I915_MAX_TRANSCODERS];
612 int trans_offsets[I915_MAX_TRANSCODERS];
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200613 int palette_offsets[I915_MAX_PIPES];
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300614 int cursor_offsets[I915_MAX_PIPES];
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500615};
616
Damien Lespiaua587f772013-04-22 18:40:38 +0100617#undef DEFINE_FLAG
618#undef SEP_SEMICOLON
619
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800620enum i915_cache_level {
621 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100622 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
623 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
624 caches, eg sampler/render caches, and the
625 large Last-Level-Cache. LLC is coherent with
626 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100627 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800628};
629
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300630struct i915_ctx_hang_stats {
631 /* This context had batch pending when hang was declared */
632 unsigned batch_pending;
633
634 /* This context had batch active when hang was declared */
635 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300636
637 /* Time when this context was last blamed for a GPU reset */
638 unsigned long guilty_ts;
639
640 /* This context is banned to submit more work */
641 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300642};
Ben Widawsky40521052012-06-04 14:42:43 -0700643
644/* This must match up with the value previously used for execbuf2.rsvd1. */
Oscar Mateo821d66d2014-07-03 16:28:00 +0100645#define DEFAULT_CONTEXT_HANDLE 0
Oscar Mateo31b7a882014-07-03 16:28:01 +0100646/**
647 * struct intel_context - as the name implies, represents a context.
648 * @ref: reference count.
649 * @user_handle: userspace tracking identity for this context.
650 * @remap_slice: l3 row remapping information.
651 * @file_priv: filp associated with this context (NULL for global default
652 * context).
653 * @hang_stats: information about the role of this context in possible GPU
654 * hangs.
655 * @vm: virtual memory space used by this context.
656 * @legacy_hw_ctx: render context backing object and whether it is correctly
657 * initialized (legacy ring submission mechanism only).
658 * @link: link in the global list of contexts.
659 *
660 * Contexts are memory images used by the hardware to store copies of their
661 * internal state.
662 */
Oscar Mateo273497e2014-05-22 14:13:37 +0100663struct intel_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300664 struct kref ref;
Oscar Mateo821d66d2014-07-03 16:28:00 +0100665 int user_handle;
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700666 uint8_t remap_slice;
Ben Widawsky40521052012-06-04 14:42:43 -0700667 struct drm_i915_file_private *file_priv;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300668 struct i915_ctx_hang_stats hang_stats;
Daniel Vetterae6c4802014-08-06 15:04:53 +0200669 struct i915_hw_ppgtt *ppgtt;
Ben Widawskya33afea2013-09-17 21:12:45 -0700670
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100671 /* Legacy ring buffer submission */
Oscar Mateoea0c76f2014-07-03 16:27:59 +0100672 struct {
673 struct drm_i915_gem_object *rcs_state;
674 bool initialized;
675 } legacy_hw_ctx;
676
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100677 /* Execlists */
Oscar Mateo564ddb22014-08-21 11:40:54 +0100678 bool rcs_initialized;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100679 struct {
680 struct drm_i915_gem_object *state;
Oscar Mateo84c23772014-07-24 17:04:15 +0100681 struct intel_ringbuffer *ringbuf;
Oscar Mateodcb4c122014-11-13 10:28:10 +0000682 int unpin_count;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100683 } engine[I915_NUM_RINGS];
684
Ben Widawskya33afea2013-09-17 21:12:45 -0700685 struct list_head link;
Ben Widawsky40521052012-06-04 14:42:43 -0700686};
687
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700688struct i915_fbc {
689 unsigned long size;
Ben Widawsky5e59f712014-06-30 10:41:24 -0700690 unsigned threshold;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700691 unsigned int fb_id;
692 enum plane plane;
693 int y;
694
Ben Widawskyc4213882014-06-19 12:06:10 -0700695 struct drm_mm_node compressed_fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700696 struct drm_mm_node *compressed_llb;
697
Rodrigo Vivida46f932014-08-01 02:04:45 -0700698 bool false_color;
699
Paulo Zanoni9adccc62014-09-19 16:04:55 -0300700 /* Tracks whether the HW is actually enabled, not whether the feature is
701 * possible. */
702 bool enabled;
703
Rodrigo Vivi1d73c2a2014-09-24 19:50:59 -0400704 /* On gen8 some rings cannont perform fbc clean operation so for now
705 * we are doing this on SW with mmio.
706 * This variable works in the opposite information direction
707 * of ring->fbc_dirty telling software on frontbuffer tracking
708 * to perform the cache clean on sw side.
709 */
710 bool need_sw_cache_clean;
711
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700712 struct intel_fbc_work {
713 struct delayed_work work;
714 struct drm_crtc *crtc;
715 struct drm_framebuffer *fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700716 } *fbc_work;
717
Chris Wilson29ebf902013-07-27 17:23:55 +0100718 enum no_fbc_reason {
719 FBC_OK, /* FBC is enabled */
720 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700721 FBC_NO_OUTPUT, /* no outputs enabled to compress */
722 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
723 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
724 FBC_MODE_TOO_LARGE, /* mode too large for compression */
725 FBC_BAD_PLANE, /* fbc not supported on plane */
726 FBC_NOT_TILED, /* buffer not tiled */
727 FBC_MULTIPLE_PIPES, /* more than one pipe active */
728 FBC_MODULE_PARAM,
729 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
730 } no_fbc_reason;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800731};
732
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530733struct i915_drrs {
734 struct intel_connector *connector;
735};
736
Daniel Vetter2807cf62014-07-11 10:30:11 -0700737struct intel_dp;
Rodrigo Vivia031d702013-10-03 16:15:06 -0300738struct i915_psr {
Daniel Vetterf0355c42014-07-11 10:30:15 -0700739 struct mutex lock;
Rodrigo Vivia031d702013-10-03 16:15:06 -0300740 bool sink_support;
741 bool source_ok;
Daniel Vetter2807cf62014-07-11 10:30:11 -0700742 struct intel_dp *enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -0700743 bool active;
744 struct delayed_work work;
Daniel Vetter9ca15302014-07-11 10:30:16 -0700745 unsigned busy_frontbuffer_bits;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300746};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700747
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800748enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300749 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800750 PCH_IBX, /* Ibexpeak PCH */
751 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300752 PCH_LPT, /* Lynxpoint PCH */
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530753 PCH_SPT, /* Sunrisepoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700754 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800755};
756
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200757enum intel_sbi_destination {
758 SBI_ICLK,
759 SBI_MPHY,
760};
761
Jesse Barnesb690e962010-07-19 13:53:12 -0700762#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700763#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100764#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Scot Doyle9c72cc62014-07-03 23:27:50 +0000765#define QUIRK_BACKLIGHT_PRESENT (1<<3)
Ville Syrjäläb6b5d042014-08-15 01:22:07 +0300766#define QUIRK_PIPEB_FORCE (1<<4)
Daniel Vetter656bfa32014-11-20 09:26:30 +0100767#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
Jesse Barnesb690e962010-07-19 13:53:12 -0700768
Dave Airlie8be48d92010-03-30 05:34:14 +0000769struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100770struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000771
Daniel Vetterc2b91522012-02-14 22:37:19 +0100772struct intel_gmbus {
773 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000774 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100775 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100776 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100777 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100778 struct drm_i915_private *dev_priv;
779};
780
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100781struct i915_suspend_saved_registers {
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000782 u8 saveLBB;
783 u32 saveDSPACNTR;
784 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000785 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000786 u32 savePIPEACONF;
787 u32 savePIPEBCONF;
788 u32 savePIPEASRC;
789 u32 savePIPEBSRC;
790 u32 saveFPA0;
791 u32 saveFPA1;
792 u32 saveDPLL_A;
793 u32 saveDPLL_A_MD;
794 u32 saveHTOTAL_A;
795 u32 saveHBLANK_A;
796 u32 saveHSYNC_A;
797 u32 saveVTOTAL_A;
798 u32 saveVBLANK_A;
799 u32 saveVSYNC_A;
800 u32 saveBCLRPAT_A;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000801 u32 saveTRANSACONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800802 u32 saveTRANS_HTOTAL_A;
803 u32 saveTRANS_HBLANK_A;
804 u32 saveTRANS_HSYNC_A;
805 u32 saveTRANS_VTOTAL_A;
806 u32 saveTRANS_VBLANK_A;
807 u32 saveTRANS_VSYNC_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000808 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000809 u32 saveDSPASTRIDE;
810 u32 saveDSPASIZE;
811 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700812 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000813 u32 saveDSPASURF;
814 u32 saveDSPATILEOFF;
815 u32 savePFIT_PGM_RATIOS;
Jesse Barnes0eb96d62009-10-14 12:33:41 -0700816 u32 saveBLC_HIST_CTL;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000817 u32 saveBLC_PWM_CTL;
818 u32 saveBLC_PWM_CTL2;
Zhenyu Wang42048782009-10-21 15:27:01 +0800819 u32 saveBLC_CPU_PWM_CTL;
820 u32 saveBLC_CPU_PWM_CTL2;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000821 u32 saveFPB0;
822 u32 saveFPB1;
823 u32 saveDPLL_B;
824 u32 saveDPLL_B_MD;
825 u32 saveHTOTAL_B;
826 u32 saveHBLANK_B;
827 u32 saveHSYNC_B;
828 u32 saveVTOTAL_B;
829 u32 saveVBLANK_B;
830 u32 saveVSYNC_B;
831 u32 saveBCLRPAT_B;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000832 u32 saveTRANSBCONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800833 u32 saveTRANS_HTOTAL_B;
834 u32 saveTRANS_HBLANK_B;
835 u32 saveTRANS_HSYNC_B;
836 u32 saveTRANS_VTOTAL_B;
837 u32 saveTRANS_VBLANK_B;
838 u32 saveTRANS_VSYNC_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000839 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000840 u32 saveDSPBSTRIDE;
841 u32 saveDSPBSIZE;
842 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700843 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000844 u32 saveDSPBSURF;
845 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700846 u32 saveVGA0;
847 u32 saveVGA1;
848 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000849 u32 saveVGACNTRL;
850 u32 saveADPA;
851 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700852 u32 savePP_ON_DELAYS;
853 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000854 u32 saveDVOA;
855 u32 saveDVOB;
856 u32 saveDVOC;
857 u32 savePP_ON;
858 u32 savePP_OFF;
859 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700860 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000861 u32 savePFIT_CONTROL;
862 u32 save_palette_a[256];
863 u32 save_palette_b[256];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000864 u32 saveFBC_CONTROL;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000865 u32 saveIER;
866 u32 saveIIR;
867 u32 saveIMR;
Zhenyu Wang42048782009-10-21 15:27:01 +0800868 u32 saveDEIER;
869 u32 saveDEIMR;
870 u32 saveGTIER;
871 u32 saveGTIMR;
872 u32 saveFDI_RXA_IMR;
873 u32 saveFDI_RXB_IMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800874 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800875 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000876 u32 saveSWF0[16];
877 u32 saveSWF1[16];
878 u32 saveSWF2[3];
879 u8 saveMSR;
880 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800881 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000882 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000883 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000884 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000885 u8 saveCR[37];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200886 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000887 u32 saveCURACNTR;
888 u32 saveCURAPOS;
889 u32 saveCURABASE;
890 u32 saveCURBCNTR;
891 u32 saveCURBPOS;
892 u32 saveCURBBASE;
893 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700894 u32 saveDP_B;
895 u32 saveDP_C;
896 u32 saveDP_D;
897 u32 savePIPEA_GMCH_DATA_M;
898 u32 savePIPEB_GMCH_DATA_M;
899 u32 savePIPEA_GMCH_DATA_N;
900 u32 savePIPEB_GMCH_DATA_N;
901 u32 savePIPEA_DP_LINK_M;
902 u32 savePIPEB_DP_LINK_M;
903 u32 savePIPEA_DP_LINK_N;
904 u32 savePIPEB_DP_LINK_N;
Zhenyu Wang42048782009-10-21 15:27:01 +0800905 u32 saveFDI_RXA_CTL;
906 u32 saveFDI_TXA_CTL;
907 u32 saveFDI_RXB_CTL;
908 u32 saveFDI_TXB_CTL;
909 u32 savePFA_CTL_1;
910 u32 savePFB_CTL_1;
911 u32 savePFA_WIN_SZ;
912 u32 savePFB_WIN_SZ;
913 u32 savePFA_WIN_POS;
914 u32 savePFB_WIN_POS;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000915 u32 savePCH_DREF_CONTROL;
916 u32 saveDISP_ARB_CTL;
917 u32 savePIPEA_DATA_M1;
918 u32 savePIPEA_DATA_N1;
919 u32 savePIPEA_LINK_M1;
920 u32 savePIPEA_LINK_N1;
921 u32 savePIPEB_DATA_M1;
922 u32 savePIPEB_DATA_N1;
923 u32 savePIPEB_LINK_M1;
924 u32 savePIPEB_LINK_N1;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000925 u32 saveMCHBAR_RENDER_STANDBY;
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400926 u32 savePCH_PORT_HOTPLUG;
Jesse Barnes9f49c372014-12-10 12:16:05 -0800927 u16 saveGCDGMBUS;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100928};
Daniel Vetterc85aa882012-11-02 19:55:03 +0100929
Imre Deakddeea5b2014-05-05 15:19:56 +0300930struct vlv_s0ix_state {
931 /* GAM */
932 u32 wr_watermark;
933 u32 gfx_prio_ctrl;
934 u32 arb_mode;
935 u32 gfx_pend_tlb0;
936 u32 gfx_pend_tlb1;
937 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
938 u32 media_max_req_count;
939 u32 gfx_max_req_count;
940 u32 render_hwsp;
941 u32 ecochk;
942 u32 bsd_hwsp;
943 u32 blt_hwsp;
944 u32 tlb_rd_addr;
945
946 /* MBC */
947 u32 g3dctl;
948 u32 gsckgctl;
949 u32 mbctl;
950
951 /* GCP */
952 u32 ucgctl1;
953 u32 ucgctl3;
954 u32 rcgctl1;
955 u32 rcgctl2;
956 u32 rstctl;
957 u32 misccpctl;
958
959 /* GPM */
960 u32 gfxpause;
961 u32 rpdeuhwtc;
962 u32 rpdeuc;
963 u32 ecobus;
964 u32 pwrdwnupctl;
965 u32 rp_down_timeout;
966 u32 rp_deucsw;
967 u32 rcubmabdtmr;
968 u32 rcedata;
969 u32 spare2gh;
970
971 /* Display 1 CZ domain */
972 u32 gt_imr;
973 u32 gt_ier;
974 u32 pm_imr;
975 u32 pm_ier;
976 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
977
978 /* GT SA CZ domain */
979 u32 tilectl;
980 u32 gt_fifoctl;
981 u32 gtlc_wake_ctrl;
982 u32 gtlc_survive;
983 u32 pmwgicz;
984
985 /* Display 2 CZ domain */
986 u32 gu_ctl0;
987 u32 gu_ctl1;
988 u32 clock_gate_dis2;
989};
990
Chris Wilsonbf225f22014-07-10 20:31:18 +0100991struct intel_rps_ei {
992 u32 cz_clock;
993 u32 render_c0;
994 u32 media_c0;
Deepak S31685c22014-07-03 17:33:01 -0400995};
996
Daniel Vetterc85aa882012-11-02 19:55:03 +0100997struct intel_gen6_power_mgmt {
Imre Deakd4d70aa2014-11-19 15:30:04 +0200998 /*
999 * work, interrupts_enabled and pm_iir are protected by
1000 * dev_priv->irq_lock
1001 */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001002 struct work_struct work;
Imre Deakd4d70aa2014-11-19 15:30:04 +02001003 bool interrupts_enabled;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001004 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001005
Ben Widawskyb39fb292014-03-19 18:31:11 -07001006 /* Frequencies are stored in potentially platform dependent multiples.
1007 * In other words, *_freq needs to be multiplied by X to be interesting.
1008 * Soft limits are those which are used for the dynamic reclocking done
1009 * by the driver (raise frequencies under heavy loads, and lower for
1010 * lighter loads). Hard limits are those imposed by the hardware.
1011 *
1012 * A distinction is made for overclocking, which is never enabled by
1013 * default, and is considered to be above the hard limit if it's
1014 * possible at all.
1015 */
1016 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1017 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1018 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1019 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1020 u8 min_freq; /* AKA RPn. Minimum frequency */
1021 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1022 u8 rp1_freq; /* "less than" RP0 power/freqency */
1023 u8 rp0_freq; /* Non-overclocked max frequency. */
Deepak S67c3bf62014-07-10 13:16:24 +05301024 u32 cz_freq;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001025
Deepak S31685c22014-07-03 17:33:01 -04001026 u32 ei_interrupt_count;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001027
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001028 int last_adj;
1029 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1030
Chris Wilsonc0951f02013-10-10 21:58:50 +01001031 bool enabled;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001032 struct delayed_work delayed_resume_work;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001033
Chris Wilsonbf225f22014-07-10 20:31:18 +01001034 /* manual wa residency calculations */
1035 struct intel_rps_ei up_ei, down_ei;
1036
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001037 /*
1038 * Protects RPS/RC6 register access and PCU communication.
1039 * Must be taken after struct_mutex if nested.
1040 */
1041 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001042};
1043
Daniel Vetter1a240d42012-11-29 22:18:51 +01001044/* defined intel_pm.c */
1045extern spinlock_t mchdev_lock;
1046
Daniel Vetterc85aa882012-11-02 19:55:03 +01001047struct intel_ilk_power_mgmt {
1048 u8 cur_delay;
1049 u8 min_delay;
1050 u8 max_delay;
1051 u8 fmax;
1052 u8 fstart;
1053
1054 u64 last_count1;
1055 unsigned long last_time1;
1056 unsigned long chipset_power;
1057 u64 last_count2;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001058 u64 last_time2;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001059 unsigned long gfx_power;
1060 u8 corr;
1061
1062 int c_m;
1063 int r_t;
Daniel Vetter3e373942012-11-02 19:55:04 +01001064
1065 struct drm_i915_gem_object *pwrctx;
1066 struct drm_i915_gem_object *renderctx;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001067};
1068
Imre Deakc6cb5822014-03-04 19:22:55 +02001069struct drm_i915_private;
1070struct i915_power_well;
1071
1072struct i915_power_well_ops {
1073 /*
1074 * Synchronize the well's hw state to match the current sw state, for
1075 * example enable/disable it based on the current refcount. Called
1076 * during driver init and resume time, possibly after first calling
1077 * the enable/disable handlers.
1078 */
1079 void (*sync_hw)(struct drm_i915_private *dev_priv,
1080 struct i915_power_well *power_well);
1081 /*
1082 * Enable the well and resources that depend on it (for example
1083 * interrupts located on the well). Called after the 0->1 refcount
1084 * transition.
1085 */
1086 void (*enable)(struct drm_i915_private *dev_priv,
1087 struct i915_power_well *power_well);
1088 /*
1089 * Disable the well and resources that depend on it. Called after
1090 * the 1->0 refcount transition.
1091 */
1092 void (*disable)(struct drm_i915_private *dev_priv,
1093 struct i915_power_well *power_well);
1094 /* Returns the hw enabled state. */
1095 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1096 struct i915_power_well *power_well);
1097};
1098
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001099/* Power well structure for haswell */
1100struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +02001101 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +02001102 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001103 /* power well enable/disable usage count */
1104 int count;
Imre Deakbfafe932014-06-05 20:31:47 +03001105 /* cached hw enabled state */
1106 bool hw_enabled;
Imre Deakc1ca7272013-11-25 17:15:29 +02001107 unsigned long domains;
Imre Deak77961eb2014-03-05 16:20:56 +02001108 unsigned long data;
Imre Deakc6cb5822014-03-04 19:22:55 +02001109 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001110};
1111
Imre Deak83c00f552013-10-25 17:36:47 +03001112struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +03001113 /*
1114 * Power wells needed for initialization at driver init and suspend
1115 * time are on. They are kept on until after the first modeset.
1116 */
1117 bool init_power_on;
Imre Deak0d116a22014-04-25 13:19:05 +03001118 bool initializing;
Imre Deakc1ca7272013-11-25 17:15:29 +02001119 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +03001120
Imre Deak83c00f552013-10-25 17:36:47 +03001121 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +02001122 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +02001123 struct i915_power_well *power_wells;
Imre Deak83c00f552013-10-25 17:36:47 +03001124};
1125
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001126#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001127struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001128 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001129 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001130 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001131};
1132
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001133struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001134 /** Memory allocator for GTT stolen memory */
1135 struct drm_mm stolen;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001136 /** List of all objects in gtt_space. Used to restore gtt
1137 * mappings on resume */
1138 struct list_head bound_list;
1139 /**
1140 * List of objects which are not bound to the GTT (thus
1141 * are idle and not used by the GPU) but still have
1142 * (presumably uncached) pages still attached.
1143 */
1144 struct list_head unbound_list;
1145
1146 /** Usable portion of the GTT for GEM */
1147 unsigned long stolen_base; /* limited to low memory (32-bit) */
1148
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001149 /** PPGTT used for aliasing the PPGTT with the GTT */
1150 struct i915_hw_ppgtt *aliasing_ppgtt;
1151
Chris Wilson2cfcd322014-05-20 08:28:43 +01001152 struct notifier_block oom_notifier;
Chris Wilsonceabbba52014-03-25 13:23:04 +00001153 struct shrinker shrinker;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001154 bool shrinker_no_lock_stealing;
1155
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001156 /** LRU list of objects with fence regs on them. */
1157 struct list_head fence_list;
1158
1159 /**
1160 * We leave the user IRQ off as much as possible,
1161 * but this means that requests will finish and never
1162 * be retired once the system goes idle. Set a timer to
1163 * fire periodically while the ring is running. When it
1164 * fires, go retire requests.
1165 */
1166 struct delayed_work retire_work;
1167
1168 /**
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001169 * When we detect an idle GPU, we want to turn on
1170 * powersaving features. So once we see that there
1171 * are no more requests outstanding and no more
1172 * arrive within a small period of time, we fire
1173 * off the idle_work.
1174 */
1175 struct delayed_work idle_work;
1176
1177 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001178 * Are we in a non-interruptible section of code like
1179 * modesetting?
1180 */
1181 bool interruptible;
1182
Chris Wilsonf62a0072014-02-21 17:55:39 +00001183 /**
1184 * Is the GPU currently considered idle, or busy executing userspace
1185 * requests? Whilst idle, we attempt to power down the hardware and
1186 * display clocks. In order to reduce the effect on performance, there
1187 * is a slight delay before we do so.
1188 */
1189 bool busy;
1190
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001191 /* the indicator for dispatch video commands on two BSD rings */
1192 int bsd_ring_dispatch_index;
1193
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001194 /** Bit 6 swizzling required for X tiling */
1195 uint32_t bit_6_swizzle_x;
1196 /** Bit 6 swizzling required for Y tiling */
1197 uint32_t bit_6_swizzle_y;
1198
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001199 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001200 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001201 size_t object_memory;
1202 u32 object_count;
1203};
1204
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001205struct drm_i915_error_state_buf {
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01001206 struct drm_i915_private *i915;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001207 unsigned bytes;
1208 unsigned size;
1209 int err;
1210 u8 *buf;
1211 loff_t start;
1212 loff_t pos;
1213};
1214
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001215struct i915_error_state_file_priv {
1216 struct drm_device *dev;
1217 struct drm_i915_error_state *error;
1218};
1219
Daniel Vetter99584db2012-11-14 17:14:04 +01001220struct i915_gpu_error {
1221 /* For hangcheck timer */
1222#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1223#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001224 /* Hang gpu twice in this window and your context gets banned */
1225#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1226
Daniel Vetter99584db2012-11-14 17:14:04 +01001227 struct timer_list hangcheck_timer;
Daniel Vetter99584db2012-11-14 17:14:04 +01001228
1229 /* For reset and error_state handling. */
1230 spinlock_t lock;
1231 /* Protected by the above dev->gpu_error.lock. */
1232 struct drm_i915_error_state *first_error;
1233 struct work_struct work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001234
Chris Wilson094f9a52013-09-25 17:34:55 +01001235
1236 unsigned long missed_irq_rings;
1237
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001238 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001239 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001240 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001241 * This is a counter which gets incremented when reset is triggered,
1242 * and again when reset has been handled. So odd values (lowest bit set)
1243 * means that reset is in progress and even values that
1244 * (reset_counter >> 1):th reset was successfully completed.
1245 *
1246 * If reset is not completed succesfully, the I915_WEDGE bit is
1247 * set meaning that hardware is terminally sour and there is no
1248 * recovery. All waiters on the reset_queue will be woken when
1249 * that happens.
1250 *
1251 * This counter is used by the wait_seqno code to notice that reset
1252 * event happened and it needs to restart the entire ioctl (since most
1253 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001254 *
1255 * This is important for lock-free wait paths, where no contended lock
1256 * naturally enforces the correct ordering between the bail-out of the
1257 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001258 */
1259 atomic_t reset_counter;
1260
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001261#define I915_RESET_IN_PROGRESS_FLAG 1
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001262#define I915_WEDGED (1 << 31)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001263
1264 /**
1265 * Waitqueue to signal when the reset has completed. Used by clients
1266 * that wait for dev_priv->mm.wedged to settle.
1267 */
1268 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001269
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02001270 /* Userspace knobs for gpu hang simulation;
1271 * combines both a ring mask, and extra flags
1272 */
1273 u32 stop_rings;
1274#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1275#define I915_STOP_RING_ALLOW_WARN (1 << 30)
Chris Wilson094f9a52013-09-25 17:34:55 +01001276
1277 /* For missed irq/seqno simulation. */
1278 unsigned int test_irq_rings;
McAulay, Alistair6689c162014-08-15 18:51:35 +01001279
1280 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1281 bool reload_in_reset;
Daniel Vetter99584db2012-11-14 17:14:04 +01001282};
1283
Zhang Ruib8efb172013-02-05 15:41:53 +08001284enum modeset_restore {
1285 MODESET_ON_LID_OPEN,
1286 MODESET_DONE,
1287 MODESET_SUSPENDED,
1288};
1289
Paulo Zanoni6acab152013-09-12 17:06:24 -03001290struct ddi_vbt_port_info {
Damien Lespiauce4dd492014-08-01 11:07:54 +01001291 /*
1292 * This is an index in the HDMI/DVI DDI buffer translation table.
1293 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1294 * populate this field.
1295 */
1296#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
Paulo Zanoni6acab152013-09-12 17:06:24 -03001297 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001298
1299 uint8_t supports_dvi:1;
1300 uint8_t supports_hdmi:1;
1301 uint8_t supports_dp:1;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001302};
1303
Pradeep Bhat83a72802014-03-28 10:14:57 +05301304enum drrs_support_type {
1305 DRRS_NOT_SUPPORTED = 0,
1306 STATIC_DRRS_SUPPORT = 1,
1307 SEAMLESS_DRRS_SUPPORT = 2
1308};
1309
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001310struct intel_vbt_data {
1311 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1312 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1313
1314 /* Feature bits */
1315 unsigned int int_tv_support:1;
1316 unsigned int lvds_dither:1;
1317 unsigned int lvds_vbt:1;
1318 unsigned int int_crt_support:1;
1319 unsigned int lvds_use_ssc:1;
1320 unsigned int display_clock_mode:1;
1321 unsigned int fdi_rx_polarity_inverted:1;
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301322 unsigned int has_mipi:1;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001323 int lvds_ssc_freq;
1324 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1325
Pradeep Bhat83a72802014-03-28 10:14:57 +05301326 enum drrs_support_type drrs_type;
1327
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001328 /* eDP */
1329 int edp_rate;
1330 int edp_lanes;
1331 int edp_preemphasis;
1332 int edp_vswing;
1333 bool edp_initialized;
1334 bool edp_support;
1335 int edp_bpp;
1336 struct edp_power_seq edp_pps;
1337
Jani Nikulaf00076d2013-12-14 20:38:29 -02001338 struct {
1339 u16 pwm_freq_hz;
Jani Nikula39fbc9c2014-04-09 11:22:06 +03001340 bool present;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001341 bool active_low_pwm;
Jani Nikula1de60682014-06-24 18:27:39 +03001342 u8 min_brightness; /* min_brightness/255 of max */
Jani Nikulaf00076d2013-12-14 20:38:29 -02001343 } backlight;
1344
Shobhit Kumard17c5442013-08-27 15:12:25 +03001345 /* MIPI DSI */
1346 struct {
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301347 u16 port;
Shobhit Kumard17c5442013-08-27 15:12:25 +03001348 u16 panel_id;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301349 struct mipi_config *config;
1350 struct mipi_pps_data *pps;
1351 u8 seq_version;
1352 u32 size;
1353 u8 *data;
1354 u8 *sequence[MIPI_SEQ_MAX];
Shobhit Kumard17c5442013-08-27 15:12:25 +03001355 } dsi;
1356
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001357 int crt_ddc_pin;
1358
1359 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001360 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001361
1362 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001363};
1364
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001365enum intel_ddb_partitioning {
1366 INTEL_DDB_PART_1_2,
1367 INTEL_DDB_PART_5_6, /* IVB+ */
1368};
1369
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001370struct intel_wm_level {
1371 bool enable;
1372 uint32_t pri_val;
1373 uint32_t spr_val;
1374 uint32_t cur_val;
1375 uint32_t fbc_val;
1376};
1377
Imre Deak820c1982013-12-17 14:46:36 +02001378struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001379 uint32_t wm_pipe[3];
1380 uint32_t wm_lp[3];
1381 uint32_t wm_lp_spr[3];
1382 uint32_t wm_linetime[3];
1383 bool enable_fbc_wm;
1384 enum intel_ddb_partitioning partitioning;
1385};
1386
Damien Lespiauc1939242014-11-04 17:06:41 +00001387struct skl_ddb_entry {
Damien Lespiau16160e32014-11-04 17:06:53 +00001388 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
Damien Lespiauc1939242014-11-04 17:06:41 +00001389};
1390
1391static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1392{
Damien Lespiau16160e32014-11-04 17:06:53 +00001393 return entry->end - entry->start;
Damien Lespiauc1939242014-11-04 17:06:41 +00001394}
1395
Damien Lespiau08db6652014-11-04 17:06:52 +00001396static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1397 const struct skl_ddb_entry *e2)
1398{
1399 if (e1->start == e2->start && e1->end == e2->end)
1400 return true;
1401
1402 return false;
1403}
1404
Damien Lespiauc1939242014-11-04 17:06:41 +00001405struct skl_ddb_allocation {
Damien Lespiau34bb56a2014-11-04 17:07:01 +00001406 struct skl_ddb_entry pipe[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001407 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1408 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1409};
1410
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001411struct skl_wm_values {
1412 bool dirty[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001413 struct skl_ddb_allocation ddb;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001414 uint32_t wm_linetime[I915_MAX_PIPES];
1415 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1416 uint32_t cursor[I915_MAX_PIPES][8];
1417 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1418 uint32_t cursor_trans[I915_MAX_PIPES];
1419};
1420
1421struct skl_wm_level {
1422 bool plane_en[I915_MAX_PLANES];
Damien Lespiaub99f58d2014-11-04 17:06:56 +00001423 bool cursor_en;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001424 uint16_t plane_res_b[I915_MAX_PLANES];
1425 uint8_t plane_res_l[I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001426 uint16_t cursor_res_b;
1427 uint8_t cursor_res_l;
1428};
1429
Paulo Zanonic67a4702013-08-19 13:18:09 -03001430/*
Paulo Zanoni765dab62014-03-07 20:08:18 -03001431 * This struct helps tracking the state needed for runtime PM, which puts the
1432 * device in PCI D3 state. Notice that when this happens, nothing on the
1433 * graphics device works, even register access, so we don't get interrupts nor
1434 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001435 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001436 * Every piece of our code that needs to actually touch the hardware needs to
1437 * either call intel_runtime_pm_get or call intel_display_power_get with the
1438 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001439 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001440 * Our driver uses the autosuspend delay feature, which means we'll only really
1441 * suspend if we stay with zero refcount for a certain amount of time. The
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001442 * default value is currently very conservative (see intel_runtime_pm_enable), but
Paulo Zanoni765dab62014-03-07 20:08:18 -03001443 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001444 *
1445 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1446 * goes back to false exactly before we reenable the IRQs. We use this variable
1447 * to check if someone is trying to enable/disable IRQs while they're supposed
1448 * to be disabled. This shouldn't happen and we'll print some error messages in
Paulo Zanoni730488b2014-03-07 20:12:32 -03001449 * case it happens.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001450 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001451 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001452 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001453struct i915_runtime_pm {
1454 bool suspended;
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001455 bool irqs_enabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001456};
1457
Daniel Vetter926321d2013-10-16 13:30:34 +02001458enum intel_pipe_crc_source {
1459 INTEL_PIPE_CRC_SOURCE_NONE,
1460 INTEL_PIPE_CRC_SOURCE_PLANE1,
1461 INTEL_PIPE_CRC_SOURCE_PLANE2,
1462 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001463 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001464 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1465 INTEL_PIPE_CRC_SOURCE_TV,
1466 INTEL_PIPE_CRC_SOURCE_DP_B,
1467 INTEL_PIPE_CRC_SOURCE_DP_C,
1468 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001469 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001470 INTEL_PIPE_CRC_SOURCE_MAX,
1471};
1472
Shuang He8bf1e9f2013-10-15 18:55:27 +01001473struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001474 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001475 uint32_t crc[5];
1476};
1477
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001478#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001479struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001480 spinlock_t lock;
1481 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001482 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001483 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001484 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001485 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001486};
1487
Daniel Vetterf99d7062014-06-19 16:01:59 +02001488struct i915_frontbuffer_tracking {
1489 struct mutex lock;
1490
1491 /*
1492 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1493 * scheduled flips.
1494 */
1495 unsigned busy_bits;
1496 unsigned flip_bits;
1497};
1498
Mika Kuoppala72253422014-10-07 17:21:26 +03001499struct i915_wa_reg {
1500 u32 addr;
1501 u32 value;
1502 /* bitmask representing WA bits */
1503 u32 mask;
1504};
1505
1506#define I915_MAX_WA_REGS 16
1507
1508struct i915_workarounds {
1509 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1510 u32 count;
1511};
1512
Jani Nikula77fec552014-03-31 14:27:22 +03001513struct drm_i915_private {
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001514 struct drm_device *dev;
Chris Wilson42dcedd2012-11-15 11:32:30 +00001515 struct kmem_cache *slab;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001516
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001517 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001518
1519 int relative_constants_mode;
1520
1521 void __iomem *regs;
1522
Chris Wilson907b28c2013-07-19 20:36:52 +01001523 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001524
1525 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1526
Daniel Vetter28c70f12012-12-01 13:53:45 +01001527
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001528 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1529 * controller on different i2c buses. */
1530 struct mutex gmbus_mutex;
1531
1532 /**
1533 * Base address of the gmbus and gpio block.
1534 */
1535 uint32_t gpio_mmio_base;
1536
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301537 /* MMIO base address for MIPI regs */
1538 uint32_t mipi_mmio_base;
1539
Daniel Vetter28c70f12012-12-01 13:53:45 +01001540 wait_queue_head_t gmbus_wait_queue;
1541
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001542 struct pci_dev *bridge_dev;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001543 struct intel_engine_cs ring[I915_NUM_RINGS];
Ben Widawsky3e789982014-06-30 09:53:37 -07001544 struct drm_i915_gem_object *semaphore_obj;
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001545 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001546
Daniel Vetterba8286f2014-09-11 07:43:25 +02001547 struct drm_dma_handle *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001548 struct resource mch_res;
1549
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001550 /* protects the irq masks */
1551 spinlock_t irq_lock;
1552
Sourab Gupta84c33a62014-06-02 16:47:17 +05301553 /* protects the mmio flip data */
1554 spinlock_t mmio_flip_lock;
1555
Imre Deakf8b79e52014-03-04 19:23:07 +02001556 bool display_irqs_enabled;
1557
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001558 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1559 struct pm_qos_request pm_qos;
1560
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001561 /* DPIO indirect register protection */
Daniel Vetter09153002012-12-12 14:06:44 +01001562 struct mutex dpio_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001563
1564 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001565 union {
1566 u32 irq_mask;
1567 u32 de_irq_mask[I915_MAX_PIPES];
1568 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001569 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001570 u32 pm_irq_mask;
Deepak Sa6706b42014-03-15 20:23:22 +05301571 u32 pm_rps_events;
Imre Deak91d181d2014-02-10 18:42:49 +02001572 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001573
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001574 struct work_struct hotplug_work;
Egbert Eichb543fb02013-04-16 13:36:54 +02001575 struct {
1576 unsigned long hpd_last_jiffies;
1577 int hpd_cnt;
1578 enum {
1579 HPD_ENABLED = 0,
1580 HPD_DISABLED = 1,
1581 HPD_MARK_DISABLED = 2
1582 } hpd_mark;
1583 } hpd_stats[HPD_NUM_PINS];
Egbert Eich142e2392013-04-11 15:57:57 +02001584 u32 hpd_event_bits;
Imre Deak63237512014-08-18 15:37:02 +03001585 struct delayed_work hotplug_reenable_work;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001586
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001587 struct i915_fbc fbc;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301588 struct i915_drrs drrs;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001589 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001590 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001591
Jesse Barnesd9ceb812014-10-09 12:57:43 -07001592 bool preserve_bios_swizzle;
1593
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001594 /* overlay */
1595 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001596
Jani Nikula58c68772013-11-08 16:48:54 +02001597 /* backlight registers and fields in struct intel_panel */
Daniel Vetter07f11d42014-09-15 14:35:09 +02001598 struct mutex backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001599
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001600 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001601 bool no_aux_handshake;
1602
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001603 /* protects panel power sequencer state */
1604 struct mutex pps_mutex;
1605
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001606 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1607 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1608 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1609
1610 unsigned int fsb_freq, mem_freq, is_ddr3;
Imre Deakd60c4472014-03-27 17:45:10 +02001611 unsigned int vlv_cdclk_freq;
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03001612 unsigned int hpll_freq;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001613
Daniel Vetter645416f2013-09-02 16:22:25 +02001614 /**
1615 * wq - Driver workqueue for GEM.
1616 *
1617 * NOTE: Work items scheduled here are not allowed to grab any modeset
1618 * locks, for otherwise the flushing done in the pageflip code will
1619 * result in deadlocks.
1620 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001621 struct workqueue_struct *wq;
1622
1623 /* Display functions */
1624 struct drm_i915_display_funcs display;
1625
1626 /* PCH chipset type */
1627 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001628 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001629
1630 unsigned long quirks;
1631
Zhang Ruib8efb172013-02-05 15:41:53 +08001632 enum modeset_restore modeset_restore;
1633 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001634
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001635 struct list_head vm_list; /* Global list of all address spaces */
Ben Widawsky0260c422014-03-22 22:47:21 -07001636 struct i915_gtt gtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001637
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001638 struct i915_gem_mm mm;
Chris Wilsonad46cb52014-08-07 14:20:40 +01001639 DECLARE_HASHTABLE(mm_structs, 7);
1640 struct mutex mm_lock;
Daniel Vetter87813422012-05-02 11:49:32 +02001641
Daniel Vetter87813422012-05-02 11:49:32 +02001642 /* Kernel Modesetting */
1643
yakui_zhao9b9d1722009-05-31 17:17:17 +08001644 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001645
Damien Lespiau76c4ac02014-02-07 19:12:52 +00001646 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1647 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001648 wait_queue_head_t pending_flip_queue;
1649
Daniel Vetterc4597872013-10-21 21:04:07 +02001650#ifdef CONFIG_DEBUG_FS
1651 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1652#endif
1653
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001654 int num_shared_dpll;
1655 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001656 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001657
Mika Kuoppala72253422014-10-07 17:21:26 +03001658 struct i915_workarounds workarounds;
Arun Siluvery888b5992014-08-26 14:44:51 +01001659
Jesse Barnes652c3932009-08-17 13:31:43 -07001660 /* Reclocking support */
1661 bool render_reclock_avail;
1662 bool lvds_downclock_avail;
Zhao Yakui18f9ed12009-11-20 03:24:16 +00001663 /* indicates the reduced downclock for LVDS*/
1664 int lvds_downclock;
Daniel Vetterf99d7062014-06-19 16:01:59 +02001665
1666 struct i915_frontbuffer_tracking fb_tracking;
1667
Jesse Barnes652c3932009-08-17 13:31:43 -07001668 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001669
Zhenyu Wangc48044112009-12-17 14:48:43 +08001670 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001671
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001672 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001673
Ben Widawsky59124502013-07-04 11:02:05 -07001674 /* Cannot be determined by PCIID. You must always read a register. */
1675 size_t ellc_size;
1676
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001677 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001678 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001679
Daniel Vetter20e4d402012-08-08 23:35:39 +02001680 /* ilk-only ips/rps state. Everything in here is protected by the global
1681 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001682 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001683
Imre Deak83c00f552013-10-25 17:36:47 +03001684 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001685
Rodrigo Vivia031d702013-10-03 16:15:06 -03001686 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001687
Daniel Vetter99584db2012-11-14 17:14:04 +01001688 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001689
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001690 struct drm_i915_gem_object *vlv_pctx;
1691
Daniel Vetter4520f532013-10-09 09:18:51 +02001692#ifdef CONFIG_DRM_I915_FBDEV
Dave Airlie8be48d92010-03-30 05:34:14 +00001693 /* list of fbdev register on this device */
1694 struct intel_fbdev *fbdev;
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001695 struct work_struct fbdev_suspend_work;
Daniel Vetter4520f532013-10-09 09:18:51 +02001696#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001697
1698 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001699 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001700
Ben Widawsky254f9652012-06-04 14:42:42 -07001701 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001702 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001703
Damien Lespiau3e683202012-12-11 18:48:29 +00001704 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001705
Daniel Vetter842f1c82014-03-10 10:01:44 +01001706 u32 suspend_count;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001707 struct i915_suspend_saved_registers regfile;
Imre Deakddeea5b2014-05-05 15:19:56 +03001708 struct vlv_s0ix_state vlv_s0ix_state;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001709
Ville Syrjälä53615a52013-08-01 16:18:50 +03001710 struct {
1711 /*
1712 * Raw watermark latency values:
1713 * in 0.1us units for WM0,
1714 * in 0.5us units for WM1+.
1715 */
1716 /* primary */
1717 uint16_t pri_latency[5];
1718 /* sprite */
1719 uint16_t spr_latency[5];
1720 /* cursor */
1721 uint16_t cur_latency[5];
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001722 /*
1723 * Raw watermark memory latency values
1724 * for SKL for all 8 levels
1725 * in 1us units.
1726 */
1727 uint16_t skl_latency[8];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001728
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001729 /*
1730 * The skl_wm_values structure is a bit too big for stack
1731 * allocation, so we keep the staging struct where we store
1732 * intermediate results here instead.
1733 */
1734 struct skl_wm_values skl_results;
1735
Ville Syrjälä609cede2013-10-09 19:18:03 +03001736 /* current hardware state */
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001737 union {
1738 struct ilk_wm_values hw;
1739 struct skl_wm_values skl_hw;
1740 };
Ville Syrjälä53615a52013-08-01 16:18:50 +03001741 } wm;
1742
Paulo Zanoni8a187452013-12-06 20:32:13 -02001743 struct i915_runtime_pm pm;
1744
Dave Airlie13cf5502014-06-18 11:29:35 +10001745 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1746 u32 long_hpd_port_mask;
1747 u32 short_hpd_port_mask;
1748 struct work_struct dig_port_work;
1749
Dave Airlie0e32b392014-05-02 14:02:48 +10001750 /*
1751 * if we get a HPD irq from DP and a HPD irq from non-DP
1752 * the non-DP HPD could block the workqueue on a mode config
1753 * mutex getting, that userspace may have taken. However
1754 * userspace is waiting on the DP workqueue to run which is
1755 * blocked behind the non-DP one.
1756 */
1757 struct workqueue_struct *dp_wq;
1758
Oscar Mateoa83014d2014-07-24 17:04:21 +01001759 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1760 struct {
1761 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1762 struct intel_engine_cs *ring,
1763 struct intel_context *ctx,
1764 struct drm_i915_gem_execbuffer2 *args,
1765 struct list_head *vmas,
1766 struct drm_i915_gem_object *batch_obj,
1767 u64 exec_start, u32 flags);
1768 int (*init_rings)(struct drm_device *dev);
1769 void (*cleanup_ring)(struct intel_engine_cs *ring);
1770 void (*stop_ring)(struct intel_engine_cs *ring);
1771 } gt;
1772
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001773 /*
1774 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1775 * will be rejected. Instead look for a better place.
1776 */
Jani Nikula77fec552014-03-31 14:27:22 +03001777};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001778
Chris Wilson2c1792a2013-08-01 18:39:55 +01001779static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1780{
1781 return dev->dev_private;
1782}
1783
Chris Wilsonb4519512012-05-11 14:29:30 +01001784/* Iterate over initialised rings */
1785#define for_each_ring(ring__, dev_priv__, i__) \
1786 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1787 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1788
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001789enum hdmi_force_audio {
1790 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1791 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1792 HDMI_AUDIO_AUTO, /* trust EDID */
1793 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1794};
1795
Daniel Vetter190d6cd2013-07-04 13:06:28 +02001796#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00001797
Chris Wilson37e680a2012-06-07 15:38:42 +01001798struct drm_i915_gem_object_ops {
1799 /* Interface between the GEM object and its backing storage.
1800 * get_pages() is called once prior to the use of the associated set
1801 * of pages before to binding them into the GTT, and put_pages() is
1802 * called after we no longer need them. As we expect there to be
1803 * associated cost with migrating pages between the backing storage
1804 * and making them available for the GPU (e.g. clflush), we may hold
1805 * onto the pages after they are no longer referenced by the GPU
1806 * in case they may be used again shortly (for example migrating the
1807 * pages to a different memory domain within the GTT). put_pages()
1808 * will therefore most likely be called when the object itself is
1809 * being released or under memory pressure (where we attempt to
1810 * reap pages for the shrinker).
1811 */
1812 int (*get_pages)(struct drm_i915_gem_object *);
1813 void (*put_pages)(struct drm_i915_gem_object *);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01001814 int (*dmabuf_export)(struct drm_i915_gem_object *);
1815 void (*release)(struct drm_i915_gem_object *);
Chris Wilson37e680a2012-06-07 15:38:42 +01001816};
1817
Daniel Vettera071fa02014-06-18 23:28:09 +02001818/*
1819 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1820 * considered to be the frontbuffer for the given plane interface-vise. This
1821 * doesn't mean that the hw necessarily already scans it out, but that any
1822 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1823 *
1824 * We have one bit per pipe and per scanout plane type.
1825 */
1826#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1827#define INTEL_FRONTBUFFER_BITS \
1828 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1829#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1830 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1831#define INTEL_FRONTBUFFER_CURSOR(pipe) \
1832 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1833#define INTEL_FRONTBUFFER_SPRITE(pipe) \
1834 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1835#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1836 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettercc365132014-06-18 13:59:13 +02001837#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1838 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
Daniel Vettera071fa02014-06-18 23:28:09 +02001839
Eric Anholt673a3942008-07-30 12:06:12 -07001840struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00001841 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07001842
Chris Wilson37e680a2012-06-07 15:38:42 +01001843 const struct drm_i915_gem_object_ops *ops;
1844
Ben Widawsky2f633152013-07-17 12:19:03 -07001845 /** List of VMAs backed by this object */
1846 struct list_head vma_list;
1847
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00001848 /** Stolen memory for this object, instead of being backed by shmem. */
1849 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07001850 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001851
Chris Wilson69dc4982010-10-19 10:36:51 +01001852 struct list_head ring_list;
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02001853 /** Used in execbuf to temporarily hold a ref */
1854 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07001855
1856 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01001857 * This is set if the object is on the active lists (has pending
1858 * rendering and so a non-zero seqno), and is not set if it i s on
1859 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07001860 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001861 unsigned int active:1;
Eric Anholt673a3942008-07-30 12:06:12 -07001862
1863 /**
1864 * This is set if the object has been written to since last bound
1865 * to the GTT
1866 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001867 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001868
1869 /**
1870 * Fence register bits (if any) for this object. Will be set
1871 * as needed when mapped into the GTT.
1872 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02001873 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02001874 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02001875
1876 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001877 * Advice: are the backing pages purgeable?
1878 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001879 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02001880
1881 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001882 * Current tiling mode for the object.
1883 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001884 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01001885 /**
1886 * Whether the tiling parameters for the currently associated fence
1887 * register have changed. Note that for the purposes of tracking
1888 * tiling changes we also treat the unfenced register, the register
1889 * slot that the object occupies whilst it executes a fenced
1890 * command (such as BLT on gen2/3), as a "fence".
1891 */
1892 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001893
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001894 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01001895 * Is the object at the current location in the gtt mappable and
1896 * fenceable? Used to avoid costly recalculations.
1897 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001898 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01001899
1900 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001901 * Whether the current gtt mapping needs to be mappable (and isn't just
1902 * mappable by accident). Track pin and fault separate for a more
1903 * accurate mappable working set.
1904 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001905 unsigned int fault_mappable:1;
1906 unsigned int pin_mappable:1;
Chris Wilsoncc98b412013-08-09 12:25:09 +01001907 unsigned int pin_display:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001908
Chris Wilsoncaea7472010-11-12 13:53:37 +00001909 /*
Akash Goel24f3a8c2014-06-17 10:59:42 +05301910 * Is the object to be mapped as read-only to the GPU
1911 * Only honoured if hardware has relevant pte bit
1912 */
1913 unsigned long gt_ro:1;
Chris Wilson651d7942013-08-08 14:41:10 +01001914 unsigned int cache_level:3;
Chris Wilson93dfb402011-03-29 16:59:50 -07001915
Chris Wilson9da3da62012-06-01 15:20:22 +01001916 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001917
Daniel Vettera071fa02014-06-18 23:28:09 +02001918 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1919
Chris Wilson9da3da62012-06-01 15:20:22 +01001920 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01001921 int pages_pin_count;
Eric Anholt673a3942008-07-30 12:06:12 -07001922
Daniel Vetter1286ff72012-05-10 15:25:09 +02001923 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01001924 void *dma_buf_vmapping;
1925 int vmapping_count;
1926
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001927 struct intel_engine_cs *ring;
Chris Wilsoncaea7472010-11-12 13:53:37 +00001928
Chris Wilson1c293ea2012-04-17 15:31:27 +01001929 /** Breadcrumb of last rendering to the buffer. */
Chris Wilson0201f1e2012-07-20 12:41:01 +01001930 uint32_t last_read_seqno;
1931 uint32_t last_write_seqno;
Chris Wilsoncaea7472010-11-12 13:53:37 +00001932 /** Breadcrumb of last fenced GPU access to the buffer. */
1933 uint32_t last_fenced_seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001934
Daniel Vetter778c3542010-05-13 11:49:44 +02001935 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08001936 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07001937
Daniel Vetter80075d42013-10-09 21:23:52 +02001938 /** References from framebuffers, locks out tiling changes. */
1939 unsigned long framebuffer_references;
1940
Eric Anholt280b7132009-03-12 16:56:27 -07001941 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01001942 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07001943
Jesse Barnes79e53942008-11-07 14:24:08 -08001944 /** User space pin count and filp owning the pin */
Daniel Vetteraa5f8022013-10-10 14:46:37 +02001945 unsigned long user_pin_count;
Jesse Barnes79e53942008-11-07 14:24:08 -08001946 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001947
Chris Wilson5cc9ed42014-05-16 14:22:37 +01001948 union {
Chris Wilson6a2c4232014-11-04 04:51:40 -08001949 /** for phy allocated objects */
1950 struct drm_dma_handle *phys_handle;
1951
Chris Wilson5cc9ed42014-05-16 14:22:37 +01001952 struct i915_gem_userptr {
1953 uintptr_t ptr;
1954 unsigned read_only :1;
1955 unsigned workers :4;
1956#define I915_GEM_USERPTR_MAX_WORKERS 15
1957
Chris Wilsonad46cb52014-08-07 14:20:40 +01001958 struct i915_mm_struct *mm;
1959 struct i915_mmu_object *mmu_object;
Chris Wilson5cc9ed42014-05-16 14:22:37 +01001960 struct work_struct *work;
1961 } userptr;
1962 };
1963};
Daniel Vetter62b8b212010-04-09 19:05:08 +00001964#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01001965
Daniel Vettera071fa02014-06-18 23:28:09 +02001966void i915_gem_track_fb(struct drm_i915_gem_object *old,
1967 struct drm_i915_gem_object *new,
1968 unsigned frontbuffer_bits);
1969
Eric Anholt673a3942008-07-30 12:06:12 -07001970/**
1971 * Request queue structure.
1972 *
1973 * The request queue allows us to note sequence numbers that have been emitted
1974 * and may be associated with active buffers to be retired.
1975 *
1976 * By keeping this list, we can avoid having to do questionable
1977 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1978 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1979 */
1980struct drm_i915_gem_request {
Zou Nan hai852835f2010-05-21 09:08:56 +08001981 /** On Which ring this request was generated */
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001982 struct intel_engine_cs *ring;
Zou Nan hai852835f2010-05-21 09:08:56 +08001983
Eric Anholt673a3942008-07-30 12:06:12 -07001984 /** GEM sequence number associated with this request. */
1985 uint32_t seqno;
1986
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001987 /** Position in the ringbuffer of the start of the request */
1988 u32 head;
1989
1990 /** Position in the ringbuffer of the end of the request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00001991 u32 tail;
1992
Mika Kuoppala0e50e962013-05-02 16:48:08 +03001993 /** Context related to this request */
Oscar Mateo273497e2014-05-22 14:13:37 +01001994 struct intel_context *ctx;
Mika Kuoppala0e50e962013-05-02 16:48:08 +03001995
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001996 /** Batch buffer related to this request if any */
1997 struct drm_i915_gem_object *batch_obj;
1998
Eric Anholt673a3942008-07-30 12:06:12 -07001999 /** Time at which this request was emitted, in jiffies. */
2000 unsigned long emitted_jiffies;
2001
Eric Anholtb9624422009-06-03 07:27:35 +00002002 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07002003 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00002004
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002005 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00002006 /** file_priv list entry for this request */
2007 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -07002008};
2009
2010struct drm_i915_file_private {
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002011 struct drm_i915_private *dev_priv;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +02002012 struct drm_file *file;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002013
Eric Anholt673a3942008-07-30 12:06:12 -07002014 struct {
Luis R. Rodriguez99057c82012-11-29 12:45:06 -08002015 spinlock_t lock;
Eric Anholtb9624422009-06-03 07:27:35 +00002016 struct list_head request_list;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002017 struct delayed_work idle_work;
Eric Anholt673a3942008-07-30 12:06:12 -07002018 } mm;
Ben Widawsky40521052012-06-04 14:42:43 -07002019 struct idr context_idr;
Mika Kuoppalae59ec132013-06-12 12:35:28 +03002020
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002021 atomic_t rps_wait_boost;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002022 struct intel_engine_cs *bsd_ring;
Eric Anholt673a3942008-07-30 12:06:12 -07002023};
2024
Brad Volkin351e3db2014-02-18 10:15:46 -08002025/*
2026 * A command that requires special handling by the command parser.
2027 */
2028struct drm_i915_cmd_descriptor {
2029 /*
2030 * Flags describing how the command parser processes the command.
2031 *
2032 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2033 * a length mask if not set
2034 * CMD_DESC_SKIP: The command is allowed but does not follow the
2035 * standard length encoding for the opcode range in
2036 * which it falls
2037 * CMD_DESC_REJECT: The command is never allowed
2038 * CMD_DESC_REGISTER: The command should be checked against the
2039 * register whitelist for the appropriate ring
2040 * CMD_DESC_MASTER: The command is allowed if the submitting process
2041 * is the DRM master
2042 */
2043 u32 flags;
2044#define CMD_DESC_FIXED (1<<0)
2045#define CMD_DESC_SKIP (1<<1)
2046#define CMD_DESC_REJECT (1<<2)
2047#define CMD_DESC_REGISTER (1<<3)
2048#define CMD_DESC_BITMASK (1<<4)
2049#define CMD_DESC_MASTER (1<<5)
2050
2051 /*
2052 * The command's unique identification bits and the bitmask to get them.
2053 * This isn't strictly the opcode field as defined in the spec and may
2054 * also include type, subtype, and/or subop fields.
2055 */
2056 struct {
2057 u32 value;
2058 u32 mask;
2059 } cmd;
2060
2061 /*
2062 * The command's length. The command is either fixed length (i.e. does
2063 * not include a length field) or has a length field mask. The flag
2064 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2065 * a length mask. All command entries in a command table must include
2066 * length information.
2067 */
2068 union {
2069 u32 fixed;
2070 u32 mask;
2071 } length;
2072
2073 /*
2074 * Describes where to find a register address in the command to check
2075 * against the ring's register whitelist. Only valid if flags has the
2076 * CMD_DESC_REGISTER bit set.
2077 */
2078 struct {
2079 u32 offset;
2080 u32 mask;
2081 } reg;
2082
2083#define MAX_CMD_DESC_BITMASKS 3
2084 /*
2085 * Describes command checks where a particular dword is masked and
2086 * compared against an expected value. If the command does not match
2087 * the expected value, the parser rejects it. Only valid if flags has
2088 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2089 * are valid.
Brad Volkind4d48032014-02-18 10:15:54 -08002090 *
2091 * If the check specifies a non-zero condition_mask then the parser
2092 * only performs the check when the bits specified by condition_mask
2093 * are non-zero.
Brad Volkin351e3db2014-02-18 10:15:46 -08002094 */
2095 struct {
2096 u32 offset;
2097 u32 mask;
2098 u32 expected;
Brad Volkind4d48032014-02-18 10:15:54 -08002099 u32 condition_offset;
2100 u32 condition_mask;
Brad Volkin351e3db2014-02-18 10:15:46 -08002101 } bits[MAX_CMD_DESC_BITMASKS];
2102};
2103
2104/*
2105 * A table of commands requiring special handling by the command parser.
2106 *
2107 * Each ring has an array of tables. Each table consists of an array of command
2108 * descriptors, which must be sorted with command opcodes in ascending order.
2109 */
2110struct drm_i915_cmd_table {
2111 const struct drm_i915_cmd_descriptor *table;
2112 int count;
2113};
2114
Chris Wilsondbbe9122014-08-09 19:18:43 +01002115/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
Chris Wilson7312e2d2014-08-13 12:14:12 +01002116#define __I915__(p) ({ \
2117 struct drm_i915_private *__p; \
2118 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2119 __p = (struct drm_i915_private *)p; \
2120 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2121 __p = to_i915((struct drm_device *)p); \
2122 else \
2123 BUILD_BUG(); \
2124 __p; \
2125})
Chris Wilsondbbe9122014-08-09 19:18:43 +01002126#define INTEL_INFO(p) (&__I915__(p)->info)
Chris Wilson87f1f462014-08-09 19:18:42 +01002127#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
Zou Nan haicae58522010-11-09 17:17:32 +08002128
Chris Wilson87f1f462014-08-09 19:18:42 +01002129#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2130#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08002131#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002132#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08002133#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Chris Wilson87f1f462014-08-09 19:18:42 +01002134#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2135#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08002136#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2137#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2138#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Chris Wilson87f1f462014-08-09 19:18:42 +01002139#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08002140#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002141#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2142#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08002143#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2144#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Chris Wilson87f1f462014-08-09 19:18:42 +01002145#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07002146#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Chris Wilson87f1f462014-08-09 19:18:42 +01002147#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2148 INTEL_DEVID(dev) == 0x0152 || \
2149 INTEL_DEVID(dev) == 0x015a)
2150#define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2151 INTEL_DEVID(dev) == 0x0106 || \
2152 INTEL_DEVID(dev) == 0x010A)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07002153#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Ville Syrjälä6df40272014-04-09 13:28:00 +03002154#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03002155#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Ville Syrjälä8179f1f2014-04-09 13:27:59 +03002156#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +05302157#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
Zou Nan haicae58522010-11-09 17:17:32 +08002158#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03002159#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002160 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002161#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
Rodrigo Vivi6b96d702015-01-19 16:16:15 -08002162 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
Chris Wilson87f1f462014-08-09 19:18:42 +01002163 (INTEL_DEVID(dev) & 0xf) == 0xe))
Rodrigo Vivia0fcbd92014-09-19 20:16:26 -04002164#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2165 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002166#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002167 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
Rodrigo Vivi94353732013-08-28 16:45:46 -03002168#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002169 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Paulo Zanoni9bbfd202014-04-29 11:00:22 -03002170/* ULX machines are also considered ULT. */
Chris Wilson87f1f462014-08-09 19:18:42 +01002171#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2172 INTEL_DEVID(dev) == 0x0A1E)
Ben Widawskyb833d682013-08-23 16:00:07 -07002173#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08002174
Jesse Barnes85436692011-04-06 12:11:14 -07002175/*
2176 * The genX designation typically refers to the render engine, so render
2177 * capability related checks should use IS_GEN, while display and other checks
2178 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2179 * chips, etc.).
2180 */
Zou Nan haicae58522010-11-09 17:17:32 +08002181#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2182#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2183#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2184#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2185#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07002186#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Ben Widawskyd2980842013-11-02 21:06:59 -07002187#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
Damien Lespiaub71252d2013-02-13 15:27:24 +00002188#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
Zou Nan haicae58522010-11-09 17:17:32 +08002189
Ben Widawsky73ae4782013-10-15 10:02:57 -07002190#define RENDER_RING (1<<RCS)
2191#define BSD_RING (1<<VCS)
2192#define BLT_RING (1<<BCS)
2193#define VEBOX_RING (1<<VECS)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002194#define BSD2_RING (1<<VCS2)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002195#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002196#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002197#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2198#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2199#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2200#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002201 __I915__(dev)->ellc_size)
Zou Nan haicae58522010-11-09 17:17:32 +08002202#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2203
Ben Widawsky254f9652012-06-04 14:42:42 -07002204#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Oscar Mateod7f621e2014-07-24 17:04:49 +01002205#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
Jesse Barnes692ef702014-08-05 07:51:18 -07002206#define USES_PPGTT(dev) (i915.enable_ppgtt)
2207#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002208
Chris Wilson05394f32010-11-08 19:18:58 +00002209#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08002210#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2211
Daniel Vetterb45305f2012-12-17 16:21:27 +01002212/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2213#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002214/*
2215 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2216 * even when in MSI mode. This results in spurious interrupt warnings if the
2217 * legacy irq no. is shared with another device. The kernel then disables that
2218 * interrupt source and so prevents the other device from working properly.
2219 */
2220#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2221#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
Daniel Vetterb45305f2012-12-17 16:21:27 +01002222
Zou Nan haicae58522010-11-09 17:17:32 +08002223/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2224 * rows, which changed the alignment requirements and fence programming.
2225 */
2226#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2227 IS_I915GM(dev)))
2228#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2229#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2230#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
Zou Nan haicae58522010-11-09 17:17:32 +08002231#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2232#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08002233
2234#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2235#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01002236#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08002237
Damien Lespiaudbf77862014-10-01 20:04:14 +01002238#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01002239
Damien Lespiaudd93be52013-04-22 18:40:39 +01002240#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Damien Lespiau30568c42013-04-22 18:40:41 +01002241#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Ben Widawskyed8546a2013-11-04 22:45:05 -08002242#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03002243#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
Imre Deakfd7f8cc2014-04-14 20:41:30 +03002244 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07002245#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2246#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002247
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002248#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2249#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2250#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2251#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2252#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2253#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302254#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2255#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002256
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002257#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302258#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03002259#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08002260#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2261#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07002262#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03002263#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08002264
Sonika Jindal5fafe292014-07-21 15:23:38 +05302265#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2266
Ben Widawsky040d2ba2013-09-19 11:01:40 -07002267/* DPF == dynamic parity feature */
2268#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2269#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07002270
Ben Widawskyc8735b02012-09-07 19:43:39 -07002271#define GT_FREQUENCY_MULTIPLIER 50
2272
Chris Wilson05394f32010-11-08 19:18:58 +00002273#include "i915_trace.h"
2274
Rob Clarkbaa70942013-08-02 13:27:49 -04002275extern const struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10002276extern int i915_max_ioctl;
2277
Imre Deakfc49b3d2014-10-23 19:23:27 +03002278extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2279extern int i915_resume_legacy(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002280extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2281extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2282
Jani Nikulad330a952014-01-21 11:24:25 +02002283/* i915_params.c */
2284struct i915_params {
2285 int modeset;
2286 int panel_ignore_lid;
2287 unsigned int powersave;
2288 int semaphores;
2289 unsigned int lvds_downclock;
2290 int lvds_channel_mode;
2291 int panel_use_ssc;
2292 int vbt_sdvo_panel_type;
2293 int enable_rc6;
2294 int enable_fbc;
Jani Nikulad330a952014-01-21 11:24:25 +02002295 int enable_ppgtt;
Oscar Mateo127f1002014-07-24 17:04:11 +01002296 int enable_execlists;
Jani Nikulad330a952014-01-21 11:24:25 +02002297 int enable_psr;
2298 unsigned int preliminary_hw_support;
2299 int disable_power_well;
2300 int enable_ips;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002301 int invert_brightness;
Brad Volkin351e3db2014-02-18 10:15:46 -08002302 int enable_cmd_parser;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002303 /* leave bools at the end to not create holes */
2304 bool enable_hangcheck;
2305 bool fastboot;
Jani Nikulad330a952014-01-21 11:24:25 +02002306 bool prefault_disable;
2307 bool reset;
Damien Lespiaua0bae572014-02-10 17:20:55 +00002308 bool disable_display;
Daniel Vetter7a10dfa2014-04-01 09:33:47 +02002309 bool disable_vtd_wa;
Sourab Gupta84c33a62014-06-02 16:47:17 +05302310 int use_mmio_flip;
Paulo Zanoni59781182014-07-16 17:49:29 -03002311 bool mmio_debug;
Jani Nikulad330a952014-01-21 11:24:25 +02002312};
2313extern struct i915_params i915 __read_mostly;
2314
Linus Torvalds1da177e2005-04-16 15:20:36 -07002315 /* i915_dma.c */
Dave Airlie22eae942005-11-10 22:16:34 +11002316extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002317extern int i915_driver_unload(struct drm_device *);
John Harrison2885f6a2014-06-26 18:23:52 +01002318extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002319extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10002320extern void i915_driver_preclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002321 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002322extern void i915_driver_postclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002323 struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002324extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002325#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11002326extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2327 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002328#endif
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07002329extern int intel_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02002330extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002331extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2332extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2333extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2334extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
Imre Deak650ad972014-04-18 16:35:02 +03002335int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
Imre Deak1d0d3432014-08-18 14:42:44 +03002336void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002337
Linus Torvalds1da177e2005-04-16 15:20:36 -07002338/* i915_irq.c */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03002339void i915_queue_hangcheck(struct drm_device *dev);
Mika Kuoppala58174462014-02-25 17:11:26 +02002340__printf(3, 4)
2341void i915_handle_error(struct drm_device *dev, bool wedged,
2342 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002343
Daniel Vetterb9632912014-09-30 10:56:44 +02002344extern void intel_irq_init(struct drm_i915_private *dev_priv);
2345extern void intel_hpd_init(struct drm_i915_private *dev_priv);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02002346int intel_irq_install(struct drm_i915_private *dev_priv);
2347void intel_irq_uninstall(struct drm_i915_private *dev_priv);
Chris Wilson907b28c2013-07-19 20:36:52 +01002348
2349extern void intel_uncore_sanitize(struct drm_device *dev);
Imre Deak10018602014-06-06 12:59:39 +03002350extern void intel_uncore_early_sanitize(struct drm_device *dev,
2351 bool restore_forcewake);
Chris Wilson907b28c2013-07-19 20:36:52 +01002352extern void intel_uncore_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01002353extern void intel_uncore_check_errors(struct drm_device *dev);
Chris Wilsonaec347a2013-08-26 13:46:09 +01002354extern void intel_uncore_fini(struct drm_device *dev);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07002355extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002356
Keith Packard7c463582008-11-04 02:03:27 -08002357void
Jani Nikula50227e12014-03-31 14:27:21 +03002358i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002359 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002360
2361void
Jani Nikula50227e12014-03-31 14:27:21 +03002362i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002363 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002364
Imre Deakf8b79e52014-03-04 19:23:07 +02002365void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2366void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
Daniel Vetter47339cd2014-09-30 10:56:46 +02002367void
2368ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2369void
2370ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2371void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2372 uint32_t interrupt_mask,
2373 uint32_t enabled_irq_mask);
2374#define ibx_enable_display_interrupt(dev_priv, bits) \
2375 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2376#define ibx_disable_display_interrupt(dev_priv, bits) \
2377 ibx_display_interrupt_update((dev_priv), (bits), 0)
Imre Deakf8b79e52014-03-04 19:23:07 +02002378
Eric Anholt673a3942008-07-30 12:06:12 -07002379/* i915_gem.c */
Eric Anholt673a3942008-07-30 12:06:12 -07002380int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2381 struct drm_file *file_priv);
2382int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2383 struct drm_file *file_priv);
2384int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2385 struct drm_file *file_priv);
2386int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2387 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002388int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2389 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002390int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2391 struct drm_file *file_priv);
2392int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2393 struct drm_file *file_priv);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +01002394void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2395 struct intel_engine_cs *ring);
2396void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2397 struct drm_file *file,
2398 struct intel_engine_cs *ring,
2399 struct drm_i915_gem_object *obj);
Oscar Mateoa83014d2014-07-24 17:04:21 +01002400int i915_gem_ringbuffer_submission(struct drm_device *dev,
2401 struct drm_file *file,
2402 struct intel_engine_cs *ring,
2403 struct intel_context *ctx,
2404 struct drm_i915_gem_execbuffer2 *args,
2405 struct list_head *vmas,
2406 struct drm_i915_gem_object *batch_obj,
2407 u64 exec_start, u32 flags);
Eric Anholt673a3942008-07-30 12:06:12 -07002408int i915_gem_execbuffer(struct drm_device *dev, void *data,
2409 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05002410int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2411 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002412int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2413 struct drm_file *file_priv);
2414int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2415 struct drm_file *file_priv);
2416int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2417 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07002418int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2419 struct drm_file *file);
2420int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2421 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002422int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2423 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01002424int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2425 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002426int i915_gem_set_tiling(struct drm_device *dev, void *data,
2427 struct drm_file *file_priv);
2428int i915_gem_get_tiling(struct drm_device *dev, void *data,
2429 struct drm_file *file_priv);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002430int i915_gem_init_userptr(struct drm_device *dev);
2431int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2432 struct drm_file *file);
Eric Anholt5a125c32008-10-22 21:40:13 -07002433int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2434 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002435int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2436 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002437void i915_gem_load(struct drm_device *dev);
Chris Wilson21ab4e72014-09-09 11:16:08 +01002438unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2439 long target,
2440 unsigned flags);
2441#define I915_SHRINK_PURGEABLE 0x1
2442#define I915_SHRINK_UNBOUND 0x2
2443#define I915_SHRINK_BOUND 0x4
Chris Wilson42dcedd2012-11-15 11:32:30 +00002444void *i915_gem_object_alloc(struct drm_device *dev);
2445void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01002446void i915_gem_object_init(struct drm_i915_gem_object *obj,
2447 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00002448struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2449 size_t size);
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08002450void i915_init_vm(struct drm_i915_private *dev_priv,
2451 struct i915_address_space *vm);
Eric Anholt673a3942008-07-30 12:06:12 -07002452void i915_gem_free_object(struct drm_gem_object *obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07002453void i915_gem_vma_destroy(struct i915_vma *vma);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002454
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002455#define PIN_MAPPABLE 0x1
2456#define PIN_NONBLOCK 0x2
Daniel Vetterbf3d1492014-02-14 14:01:12 +01002457#define PIN_GLOBAL 0x4
Chris Wilsond23db882014-05-23 08:48:08 +02002458#define PIN_OFFSET_BIAS 0x8
2459#define PIN_OFFSET_MASK (~4095)
Chris Wilson20217462010-11-23 15:26:33 +00002460int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
Ben Widawskyc37e2202013-07-31 16:59:58 -07002461 struct i915_address_space *vm,
Chris Wilson20217462010-11-23 15:26:33 +00002462 uint32_t alignment,
Chris Wilsond23db882014-05-23 08:48:08 +02002463 uint64_t flags);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07002464int __must_check i915_vma_unbind(struct i915_vma *vma);
Chris Wilsondd624af2013-01-15 12:39:35 +00002465int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Paulo Zanoni48018a52013-12-13 15:22:31 -02002466void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
Chris Wilson05394f32010-11-08 19:18:58 +00002467void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002468
Brad Volkin4c914c02014-02-18 10:15:45 -08002469int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2470 int *needs_clflush);
2471
Chris Wilson37e680a2012-06-07 15:38:42 +01002472int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01002473static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2474{
Imre Deak67d5a502013-02-18 19:28:02 +02002475 struct sg_page_iter sg_iter;
Chris Wilson1cf83782012-10-10 12:11:52 +01002476
Imre Deak67d5a502013-02-18 19:28:02 +02002477 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
Imre Deak2db76d72013-03-26 15:14:18 +02002478 return sg_page_iter_page(&sg_iter);
Imre Deak67d5a502013-02-18 19:28:02 +02002479
2480 return NULL;
Chris Wilson9da3da62012-06-01 15:20:22 +01002481}
Chris Wilsona5570172012-09-04 21:02:54 +01002482static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2483{
2484 BUG_ON(obj->pages == NULL);
2485 obj->pages_pin_count++;
2486}
2487static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2488{
2489 BUG_ON(obj->pages_pin_count == 0);
2490 obj->pages_pin_count--;
2491}
2492
Chris Wilson54cf91d2010-11-25 18:00:26 +00002493int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07002494int i915_gem_object_sync(struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002495 struct intel_engine_cs *to);
Ben Widawskye2d05a82013-09-24 09:57:58 -07002496void i915_vma_move_to_active(struct i915_vma *vma,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002497 struct intel_engine_cs *ring);
Dave Airlieff72145b2011-02-07 12:16:14 +10002498int i915_gem_dumb_create(struct drm_file *file_priv,
2499 struct drm_device *dev,
2500 struct drm_mode_create_dumb *args);
Dave Airlieda6b51d2014-12-24 13:11:17 +10002501int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2502 uint32_t handle, uint64_t *offset);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002503/**
2504 * Returns true if seq1 is later than seq2.
2505 */
2506static inline bool
2507i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2508{
2509 return (int32_t)(seq1 - seq2) >= 0;
2510}
2511
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002512int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2513int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson06d98132012-04-17 15:31:24 +01002514int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00002515int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00002516
Daniel Vetterd8ffa602014-05-13 12:11:26 +02002517bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2518void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002519
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002520struct drm_i915_gem_request *
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002521i915_gem_find_active_request(struct intel_engine_cs *ring);
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002522
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002523bool i915_gem_retire_requests(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002524void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
Daniel Vetter33196de2012-11-14 17:14:05 +01002525int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02002526 bool interruptible);
Sourab Gupta84c33a62014-06-02 16:47:17 +05302527int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2528
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002529static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2530{
2531 return unlikely(atomic_read(&error->reset_counter)
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002532 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002533}
2534
2535static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2536{
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002537 return atomic_read(&error->reset_counter) & I915_WEDGED;
2538}
2539
2540static inline u32 i915_reset_count(struct i915_gpu_error *error)
2541{
2542 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002543}
Chris Wilsona71d8d92012-02-15 11:25:36 +00002544
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02002545static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2546{
2547 return dev_priv->gpu_error.stop_rings == 0 ||
2548 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2549}
2550
2551static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2552{
2553 return dev_priv->gpu_error.stop_rings == 0 ||
2554 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2555}
2556
Chris Wilson069efc12010-09-30 16:53:18 +01002557void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01002558bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilsona8198ee2011-04-13 22:04:09 +01002559int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
Chris Wilson1070a422012-04-24 15:47:41 +01002560int __must_check i915_gem_init(struct drm_device *dev);
Oscar Mateoa83014d2014-07-24 17:04:21 +01002561int i915_gem_init_rings(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002562int __must_check i915_gem_init_hw(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002563int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002564void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002565void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07002566int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01002567int __must_check i915_gem_suspend(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002568int __i915_add_request(struct intel_engine_cs *ring,
Mika Kuoppala0025c072013-06-12 12:35:30 +03002569 struct drm_file *file,
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002570 struct drm_i915_gem_object *batch_obj,
Mika Kuoppala0025c072013-06-12 12:35:30 +03002571 u32 *seqno);
2572#define i915_add_request(ring, seqno) \
Dan Carpenter854c94a2013-06-18 10:29:58 +03002573 __i915_add_request(ring, NULL, NULL, seqno)
Ander Conselvan de Oliveira16e9a212014-11-06 09:26:38 +02002574int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
2575 unsigned reset_counter,
2576 bool interruptible,
2577 s64 *timeout,
2578 struct drm_i915_file_private *file_priv);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002579int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
Ben Widawsky199b2bc2012-05-24 15:03:11 -07002580 uint32_t seqno);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002581int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00002582int __must_check
2583i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2584 bool write);
2585int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02002586i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2587int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002588i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2589 u32 alignment,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002590 struct intel_engine_cs *pipelined);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002591void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
Chris Wilson00731152014-05-21 12:42:56 +01002592int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01002593 int align);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002594int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00002595void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002596
Chris Wilson467cffb2011-03-07 10:42:03 +00002597uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02002598i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2599uint32_t
Imre Deakd8651102013-01-07 21:47:33 +02002600i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2601 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00002602
Chris Wilsone4ffd172011-04-04 09:44:39 +01002603int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2604 enum i915_cache_level cache_level);
2605
Daniel Vetter1286ff72012-05-10 15:25:09 +02002606struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2607 struct dma_buf *dma_buf);
2608
2609struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2610 struct drm_gem_object *gem_obj, int flags);
2611
Chris Wilson19b2dbd2013-06-12 10:15:12 +01002612void i915_gem_restore_fences(struct drm_device *dev);
2613
Ben Widawskya70a3142013-07-31 16:59:56 -07002614unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2615 struct i915_address_space *vm);
2616bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2617bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2618 struct i915_address_space *vm);
2619unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2620 struct i915_address_space *vm);
2621struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2622 struct i915_address_space *vm);
Ben Widawskyaccfef22013-08-14 11:38:35 +02002623struct i915_vma *
2624i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2625 struct i915_address_space *vm);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002626
2627struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08002628static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2629 struct i915_vma *vma;
2630 list_for_each_entry(vma, &obj->vma_list, vma_link)
2631 if (vma->pin_count > 0)
2632 return true;
2633 return false;
2634}
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002635
Ben Widawskya70a3142013-07-31 16:59:56 -07002636/* Some GGTT VM helpers */
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002637#define i915_obj_to_ggtt(obj) \
Ben Widawskya70a3142013-07-31 16:59:56 -07002638 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2639static inline bool i915_is_ggtt(struct i915_address_space *vm)
2640{
2641 struct i915_address_space *ggtt =
2642 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2643 return vm == ggtt;
2644}
2645
Daniel Vetter841cd772014-08-06 15:04:48 +02002646static inline struct i915_hw_ppgtt *
2647i915_vm_to_ppgtt(struct i915_address_space *vm)
2648{
2649 WARN_ON(i915_is_ggtt(vm));
2650
2651 return container_of(vm, struct i915_hw_ppgtt, base);
2652}
2653
2654
Ben Widawskya70a3142013-07-31 16:59:56 -07002655static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2656{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002657 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07002658}
2659
2660static inline unsigned long
2661i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2662{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002663 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07002664}
2665
2666static inline unsigned long
2667i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2668{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002669 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07002670}
Ben Widawskyc37e2202013-07-31 16:59:58 -07002671
2672static inline int __must_check
2673i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2674 uint32_t alignment,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002675 unsigned flags)
Ben Widawskyc37e2202013-07-31 16:59:58 -07002676{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002677 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2678 alignment, flags | PIN_GLOBAL);
Ben Widawskyc37e2202013-07-31 16:59:58 -07002679}
Ben Widawskya70a3142013-07-31 16:59:56 -07002680
Daniel Vetterb2871102014-02-14 14:01:19 +01002681static inline int
2682i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2683{
2684 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2685}
2686
2687void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2688
Ben Widawsky254f9652012-06-04 14:42:42 -07002689/* i915_gem_context.c */
Ben Widawsky8245be32013-11-06 13:56:29 -02002690int __must_check i915_gem_context_init(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07002691void i915_gem_context_fini(struct drm_device *dev);
Ben Widawskyacce9ff2013-12-06 14:11:03 -08002692void i915_gem_context_reset(struct drm_device *dev);
Ben Widawskye422b882013-12-06 14:10:58 -08002693int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
Ben Widawsky2fa48d82013-12-06 14:11:04 -08002694int i915_gem_context_enable(struct drm_i915_private *dev_priv);
Ben Widawsky254f9652012-06-04 14:42:42 -07002695void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002696int i915_switch_context(struct intel_engine_cs *ring,
Oscar Mateo273497e2014-05-22 14:13:37 +01002697 struct intel_context *to);
2698struct intel_context *
Ben Widawsky41bde552013-12-06 14:11:21 -08002699i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002700void i915_gem_context_free(struct kref *ctx_ref);
Oscar Mateo8c8579172014-07-24 17:04:14 +01002701struct drm_i915_gem_object *
2702i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
Oscar Mateo273497e2014-05-22 14:13:37 +01002703static inline void i915_gem_context_reference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03002704{
Chris Wilson691e6412014-04-09 09:07:36 +01002705 kref_get(&ctx->ref);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002706}
2707
Oscar Mateo273497e2014-05-22 14:13:37 +01002708static inline void i915_gem_context_unreference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03002709{
Chris Wilson691e6412014-04-09 09:07:36 +01002710 kref_put(&ctx->ref, i915_gem_context_free);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002711}
2712
Oscar Mateo273497e2014-05-22 14:13:37 +01002713static inline bool i915_gem_context_is_default(const struct intel_context *c)
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002714{
Oscar Mateo821d66d2014-07-03 16:28:00 +01002715 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002716}
2717
Ben Widawsky84624812012-06-04 14:42:54 -07002718int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2719 struct drm_file *file);
2720int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2721 struct drm_file *file);
Daniel Vetter1286ff72012-05-10 15:25:09 +02002722
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002723/* i915_gem_evict.c */
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07002724int __must_check i915_gem_evict_something(struct drm_device *dev,
2725 struct i915_address_space *vm,
2726 int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01002727 unsigned alignment,
2728 unsigned cache_level,
Chris Wilsond23db882014-05-23 08:48:08 +02002729 unsigned long start,
2730 unsigned long end,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002731 unsigned flags);
Ben Widawsky68c8c172013-09-11 14:57:50 -07002732int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilson6c085a72012-08-20 11:40:46 +02002733int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002734
Ben Widawsky0260c422014-03-22 22:47:21 -07002735/* belongs in i915_gem_gtt.h */
Eric Anholt673a3942008-07-30 12:06:12 -07002736static inline void i915_gem_chipset_flush(struct drm_device *dev)
2737{
Chris Wilson05394f32010-11-08 19:18:58 +00002738 if (INTEL_INFO(dev)->gen < 6)
2739 intel_gtt_chipset_flush();
Chris Wilson9797fbf2012-04-24 15:47:39 +01002740}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08002741
Chris Wilson9797fbf2012-04-24 15:47:39 +01002742/* i915_gem_stolen.c */
2743int i915_gem_init_stolen(struct drm_device *dev);
Ben Widawsky5e59f712014-06-30 10:41:24 -07002744int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
Chris Wilson11be49e2012-11-15 11:32:20 +00002745void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002746void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00002747struct drm_i915_gem_object *
2748i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08002749struct drm_i915_gem_object *
2750i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2751 u32 stolen_offset,
2752 u32 gtt_offset,
2753 u32 size);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002754
Eric Anholt673a3942008-07-30 12:06:12 -07002755/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01002756static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00002757{
Jani Nikula50227e12014-03-31 14:27:21 +03002758 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsone9b73c62012-12-03 21:03:14 +00002759
2760 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2761 obj->tiling_mode != I915_TILING_NONE;
2762}
2763
Eric Anholt673a3942008-07-30 12:06:12 -07002764void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Eric Anholt280b7132009-03-12 16:56:27 -07002765void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2766void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002767
2768/* i915_gem_debug.c */
Chris Wilson23bc5982010-09-29 16:10:57 +01002769#if WATCH_LISTS
2770int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002771#else
Chris Wilson23bc5982010-09-29 16:10:57 +01002772#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07002773#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002774
Ben Gamari20172632009-02-17 20:08:50 -05002775/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04002776int i915_debugfs_init(struct drm_minor *minor);
2777void i915_debugfs_cleanup(struct drm_minor *minor);
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002778#ifdef CONFIG_DEBUG_FS
Damien Lespiau07144422013-10-15 18:55:40 +01002779void intel_display_crc_init(struct drm_device *dev);
2780#else
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002781static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01002782#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03002783
2784/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002785__printf(2, 3)
2786void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03002787int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2788 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03002789int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01002790 struct drm_i915_private *i915,
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03002791 size_t count, loff_t pos);
2792static inline void i915_error_state_buf_release(
2793 struct drm_i915_error_state_buf *eb)
2794{
2795 kfree(eb->buf);
2796}
Mika Kuoppala58174462014-02-25 17:11:26 +02002797void i915_capture_error_state(struct drm_device *dev, bool wedge,
2798 const char *error_msg);
Mika Kuoppala84734a02013-07-12 16:50:57 +03002799void i915_error_state_get(struct drm_device *dev,
2800 struct i915_error_state_file_priv *error_priv);
2801void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2802void i915_destroy_error_state(struct drm_device *dev);
2803
2804void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01002805const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
Ben Gamari20172632009-02-17 20:08:50 -05002806
Brad Volkin351e3db2014-02-18 10:15:46 -08002807/* i915_cmd_parser.c */
Brad Volkind728c8e2014-02-18 10:15:56 -08002808int i915_cmd_parser_get_version(void);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002809int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2810void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2811bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2812int i915_parse_cmds(struct intel_engine_cs *ring,
Brad Volkin351e3db2014-02-18 10:15:46 -08002813 struct drm_i915_gem_object *batch_obj,
2814 u32 batch_start_offset,
2815 bool is_master);
2816
Jesse Barnes317c35d2008-08-25 15:11:06 -07002817/* i915_suspend.c */
2818extern int i915_save_state(struct drm_device *dev);
2819extern int i915_restore_state(struct drm_device *dev);
2820
Daniel Vetterd8157a32013-01-25 17:53:20 +01002821/* i915_ums.c */
2822void i915_save_display_reg(struct drm_device *dev);
2823void i915_restore_display_reg(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002824
Ben Widawsky0136db582012-04-10 21:17:01 -07002825/* i915_sysfs.c */
2826void i915_setup_sysfs(struct drm_device *dev_priv);
2827void i915_teardown_sysfs(struct drm_device *dev_priv);
2828
Chris Wilsonf899fc62010-07-20 15:44:45 -07002829/* intel_i2c.c */
2830extern int intel_setup_gmbus(struct drm_device *dev);
2831extern void intel_teardown_gmbus(struct drm_device *dev);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02002832static inline bool intel_gmbus_is_port_valid(unsigned port)
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08002833{
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08002834 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08002835}
2836
2837extern struct i2c_adapter *intel_gmbus_get_adapter(
2838 struct drm_i915_private *dev_priv, unsigned port);
Chris Wilsone957d772010-09-24 12:52:03 +01002839extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2840extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02002841static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01002842{
2843 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2844}
Chris Wilsonf899fc62010-07-20 15:44:45 -07002845extern void intel_i2c_reset(struct drm_device *dev);
2846
Chris Wilson3b617962010-08-24 09:02:58 +01002847/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01002848#ifdef CONFIG_ACPI
Lv Zheng27d50c82013-12-06 16:52:05 +08002849extern int intel_opregion_setup(struct drm_device *dev);
Chris Wilson44834a62010-08-19 16:09:23 +01002850extern void intel_opregion_init(struct drm_device *dev);
2851extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01002852extern void intel_opregion_asle_intr(struct drm_device *dev);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03002853extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2854 bool enable);
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03002855extern int intel_opregion_notify_adapter(struct drm_device *dev,
2856 pci_power_t state);
Len Brown65e082c2008-10-24 17:18:10 -04002857#else
Lv Zheng27d50c82013-12-06 16:52:05 +08002858static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
Chris Wilson44834a62010-08-19 16:09:23 +01002859static inline void intel_opregion_init(struct drm_device *dev) { return; }
2860static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01002861static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Jani Nikula9c4b0a62013-08-30 19:40:30 +03002862static inline int
2863intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2864{
2865 return 0;
2866}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03002867static inline int
2868intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2869{
2870 return 0;
2871}
Len Brown65e082c2008-10-24 17:18:10 -04002872#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01002873
Jesse Barnes723bfd72010-10-07 16:01:13 -07002874/* intel_acpi.c */
2875#ifdef CONFIG_ACPI
2876extern void intel_register_dsm_handler(void);
2877extern void intel_unregister_dsm_handler(void);
2878#else
2879static inline void intel_register_dsm_handler(void) { return; }
2880static inline void intel_unregister_dsm_handler(void) { return; }
2881#endif /* CONFIG_ACPI */
2882
Jesse Barnes79e53942008-11-07 14:24:08 -08002883/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02002884extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002885extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01002886extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002887extern void intel_modeset_cleanup(struct drm_device *dev);
Imre Deak4932e2c2014-02-11 17:12:48 +02002888extern void intel_connector_unregister(struct intel_connector *);
Dave Airlie28d52042009-09-21 14:33:58 +10002889extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01002890extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2891 bool force_restore);
Daniel Vetter44cec742013-01-25 17:53:21 +01002892extern void i915_redisable_vga(struct drm_device *dev);
Imre Deak04098752014-02-18 00:02:16 +02002893extern void i915_redisable_vga_power_on(struct drm_device *dev);
Adam Jacksonee5382a2010-04-23 11:17:39 -04002894extern bool intel_fbc_enabled(struct drm_device *dev);
Rodrigo Vivi1d73c2a2014-09-24 19:50:59 -04002895extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
Chris Wilson43a95392011-07-08 12:22:36 +01002896extern void intel_disable_fbc(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002897extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02002898extern void intel_init_pch_refclk(struct drm_device *dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08002899extern void gen6_set_rps(struct drm_device *dev, u8 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07002900extern void valleyview_set_rps(struct drm_device *dev, u8 val);
Imre Deak5209b1f2014-07-01 12:36:17 +03002901extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2902 bool enable);
Akshay Joshi0206e352011-08-16 15:34:10 -04002903extern void intel_detect_pch(struct drm_device *dev);
2904extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db582012-04-10 21:17:01 -07002905extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08002906
Ben Widawsky2911a352012-04-05 14:47:36 -07002907extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07002908int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2909 struct drm_file *file);
Mika Kuoppalab6359912013-10-30 15:44:16 +02002910int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2911 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07002912
Sourab Gupta84c33a62014-06-02 16:47:17 +05302913void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2914
Chris Wilson6ef3d422010-08-04 20:26:07 +01002915/* overlay */
2916extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002917extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2918 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00002919
2920extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002921extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00002922 struct drm_device *dev,
2923 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01002924
Ben Widawskyb7287d82011-04-25 11:22:22 -07002925/* On SNB platform, before reading ring registers forcewake bit
2926 * must be set to prevent GT core from power down and stale values being
2927 * returned.
2928 */
Deepak Sc8d9a592013-11-23 14:55:42 +05302929void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2930void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
Paulo Zanonie998c402014-02-21 13:52:26 -03002931void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
Ben Widawskyb7287d82011-04-25 11:22:22 -07002932
Tom O'Rourke151a49d2014-11-13 18:50:10 -08002933int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
2934int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03002935
2936/* intel_sideband.c */
Jani Nikula64936252013-05-22 15:36:20 +03002937u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2938void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2939u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Jani Nikulae9f882a2013-08-27 15:12:14 +03002940u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2941void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2942u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2943void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2944u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2945void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08002946u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2947void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03002948u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2949void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002950u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2951void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03002952u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2953 enum intel_sbi_destination destination);
2954void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2955 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05302956u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2957void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07002958
Ville Syrjälä2ec38152013-11-05 22:42:29 +02002959int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2960int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
Ben Widawsky42c05262012-09-26 10:34:00 -07002961
Deepak Sc8d9a592013-11-23 14:55:42 +05302962#define FORCEWAKE_RENDER (1 << 0)
2963#define FORCEWAKE_MEDIA (1 << 1)
Zhe Wang38cff0b2014-11-04 17:07:04 +00002964#define FORCEWAKE_BLITTER (1 << 2)
2965#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
2966 FORCEWAKE_BLITTER)
Deepak Sc8d9a592013-11-23 14:55:42 +05302967
2968
Ben Widawsky0b274482013-10-04 21:22:51 -07002969#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2970#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00002971
Ben Widawsky0b274482013-10-04 21:22:51 -07002972#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2973#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2974#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2975#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00002976
Ben Widawsky0b274482013-10-04 21:22:51 -07002977#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2978#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2979#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2980#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00002981
Chris Wilson698b3132014-03-21 13:16:43 +00002982/* Be very careful with read/write 64-bit values. On 32-bit machines, they
2983 * will be implemented using 2 32-bit writes in an arbitrary order with
2984 * an arbitrary delay between them. This can cause the hardware to
2985 * act upon the intermediate value, possibly leading to corruption and
2986 * machine death. You have been warned.
2987 */
Ben Widawsky0b274482013-10-04 21:22:51 -07002988#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2989#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08002990
Chris Wilson50877442014-03-21 12:41:53 +00002991#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2992 u32 upper = I915_READ(upper_reg); \
2993 u32 lower = I915_READ(lower_reg); \
2994 u32 tmp = I915_READ(upper_reg); \
2995 if (upper != tmp) { \
2996 upper = tmp; \
2997 lower = I915_READ(lower_reg); \
2998 WARN_ON(I915_READ(upper_reg) != upper); \
2999 } \
3000 (u64)upper << 32 | lower; })
3001
Zou Nan haicae58522010-11-09 17:17:32 +08003002#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3003#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3004
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003005/* "Broadcast RGB" property */
3006#define INTEL_BROADCAST_RGB_AUTO 0
3007#define INTEL_BROADCAST_RGB_FULL 1
3008#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08003009
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003010static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3011{
Sonika Jindal92e23b92014-07-21 15:23:40 +05303012 if (IS_VALLEYVIEW(dev))
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003013 return VLV_VGACNTRL;
Sonika Jindal92e23b92014-07-21 15:23:40 +05303014 else if (INTEL_INFO(dev)->gen >= 5)
3015 return CPU_VGACNTRL;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003016 else
3017 return VGACNTRL;
3018}
3019
Ville Syrjälä2bb46292013-02-22 16:12:51 +02003020static inline void __user *to_user_ptr(u64 address)
3021{
3022 return (void __user *)(uintptr_t)address;
3023}
3024
Imre Deakdf977292013-05-21 20:03:17 +03003025static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3026{
3027 unsigned long j = msecs_to_jiffies(m);
3028
3029 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3030}
3031
Daniel Vetter7bd0e222014-12-04 11:12:54 +01003032static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3033{
3034 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3035}
3036
Imre Deakdf977292013-05-21 20:03:17 +03003037static inline unsigned long
3038timespec_to_jiffies_timeout(const struct timespec *value)
3039{
3040 unsigned long j = timespec_to_jiffies(value);
3041
3042 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3043}
3044
Paulo Zanonidce56b32013-12-19 14:29:40 -02003045/*
3046 * If you need to wait X milliseconds between events A and B, but event B
3047 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3048 * when event A happened, then just before event B you call this function and
3049 * pass the timestamp as the first argument, and X as the second argument.
3050 */
3051static inline void
3052wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3053{
Imre Deakec5e0cf2014-01-29 13:25:40 +02003054 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02003055
3056 /*
3057 * Don't re-read the value of "jiffies" every time since it may change
3058 * behind our back and break the math.
3059 */
3060 tmp_jiffies = jiffies;
3061 target_jiffies = timestamp_jiffies +
3062 msecs_to_jiffies_timeout(to_wait_ms);
3063
3064 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02003065 remaining_jiffies = target_jiffies - tmp_jiffies;
3066 while (remaining_jiffies)
3067 remaining_jiffies =
3068 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02003069 }
3070}
3071
Linus Torvalds1da177e2005-04-16 15:20:36 -07003072#endif