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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070042#include <drm/drm_plane_helper.h>
43#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080044#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080045
Matt Roper465c1202014-05-29 08:06:54 -070046/* Primary plane formats supported by all gen */
47#define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53/* Primary plane formats for gen <= 3 */
54static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58};
59
60/* Primary plane formats for gen >= 4 */
61static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69};
70
Matt Roper3d7d6512014-06-10 08:28:13 -070071/* Cursor formats */
72static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74};
75
Chon Ming Leeef9348c2014-04-09 13:28:18 +030076#define DIV_ROUND_CLOSEST_ULL(ll, d) \
Matt Roper465c1202014-05-29 08:06:54 -070077({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
Chon Ming Leeef9348c2014-04-09 13:28:18 +030078
Daniel Vettercc365132014-06-18 13:59:13 +020079static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +010081static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080082
Jesse Barnesf1f644d2013-06-27 00:39:25 +030083static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030085static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030087
Damien Lespiaue7457a92013-08-08 22:28:59 +010088static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080090static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020094static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020096static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -070097 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +020099static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +0200100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +0200102static void vlv_prepare_pll(struct intel_crtc *crtc);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +0300103static void chv_prepare_pll(struct intel_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100104
Dave Airlie0e32b392014-05-02 14:02:48 +1000105static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106{
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111}
112
Jesse Barnes79e53942008-11-07 14:24:08 -0800113typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400114 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800115} intel_range_t;
116
117typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400118 int dot_limit;
119 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800120} intel_p2_t;
121
Ma Lingd4906092009-03-18 20:13:27 +0800122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800126};
Jesse Barnes79e53942008-11-07 14:24:08 -0800127
Daniel Vetterd2acd212012-10-20 20:57:43 +0200128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
Chris Wilson021357a2010-09-07 20:54:59 +0100138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
Chris Wilson8b99e682010-10-13 09:59:17 +0100141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100146}
147
Daniel Vetter5d536e22013-07-06 12:52:06 +0200148static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400149 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200150 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200151 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700159};
160
Daniel Vetter5d536e22013-07-06 12:52:06 +0200161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200163 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200164 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
Keith Packarde4b36692009-06-05 19:22:17 -0700174static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400175 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200176 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200177 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700185};
Eric Anholt273e27c2011-03-30 13:01:10 -0700186
Keith Packarde4b36692009-06-05 19:22:17 -0700187static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700211};
212
Eric Anholt273e27c2011-03-30 13:01:10 -0700213
Keith Packarde4b36692009-06-05 19:22:17 -0700214static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800226 },
Keith Packarde4b36692009-06-05 19:22:17 -0700227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800253 },
Keith Packarde4b36692009-06-05 19:22:17 -0700254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800267 },
Keith Packarde4b36692009-06-05 19:22:17 -0700268};
269
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500270static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700276 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700283};
284
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500285static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700296};
297
Eric Anholt273e27c2011-03-30 13:01:10 -0700298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800303static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700314};
315
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800316static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800340};
341
Eric Anholt273e27c2011-03-30 13:01:10 -0700342/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400351 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400364 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800367};
368
Ville Syrjälädc730512013-09-24 21:26:30 +0300369static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200377 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700378 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300381 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700383};
384
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300401static void vlv_clock(int refclk, intel_clock_t *clock)
402{
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300409}
410
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300411/**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415{
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424}
425
Chris Wilson1b894b52010-12-14 20:04:54 +0000426static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800428{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800429 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800430 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100433 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000434 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000439 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200444 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800445 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800446
447 return limit;
448}
449
Ma Ling044c7c42009-03-18 20:13:23 +0800450static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451{
452 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100456 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700457 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800458 else
Keith Packarde4b36692009-06-05 19:22:17 -0700459 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700462 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700464 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800465 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700466 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800467
468 return limit;
469}
470
Chris Wilson1b894b52010-12-14 20:04:54 +0000471static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800472{
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
Eric Anholtbad720f2009-10-22 16:11:14 -0700476 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000477 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800478 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800479 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500480 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500482 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800483 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500484 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700487 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300488 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700496 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700498 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200499 else
500 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800501 }
502 return limit;
503}
504
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500505/* m1 is reserved as 0 in Pineview, n is a ring counter */
506static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800507{
Shaohua Li21778322009-02-23 15:19:16 +0800508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800514}
515
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200516static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517{
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519}
520
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200521static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800522{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200523 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800524 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800529}
530
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300531static void chv_clock(int refclk, intel_clock_t *clock)
532{
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540}
541
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
Chris Wilson1b894b52010-12-14 20:04:54 +0000548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800551{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400555 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400557 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400559 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
Jesse Barnes79e53942008-11-07 14:24:08 -0800572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400573 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400578 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800579
580 return true;
581}
582
Ma Lingd4906092009-03-18 20:13:27 +0800583static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200584i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800587{
588 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800589 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800590 int err = target;
591
Daniel Vettera210b022012-11-26 17:22:08 +0100592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800593 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800597 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100598 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
Akshay Joshi0206e352011-08-16 15:34:10 -0400609 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800610
Zhao Yakui42158662009-11-20 11:24:18 +0800611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200615 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800621 int this_err;
622
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200623 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800626 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642}
643
Ma Lingd4906092009-03-18 20:13:27 +0800644static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200645pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200648{
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701}
702
Ma Lingd4906092009-03-18 20:13:27 +0800703static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200704g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800707{
708 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800709 intel_clock_t clock;
710 int max_n;
711 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100717 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200730 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200732 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200741 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800744 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000745
746 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800757 return found;
758}
Ma Lingd4906092009-03-18 20:13:27 +0800759
Zhenyu Wang2c072452009-06-05 15:38:42 +0800760static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200761vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700764{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300765 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300766 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300767 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300770 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700771
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700775
776 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300781 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700782 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300784 unsigned int ppm, diff;
785
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300788
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300789 vlv_clock(refclk, &clock);
790
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300793 continue;
794
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300799 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300800 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300801 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300802 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300803
Ville Syrjäläc6861222013-09-24 21:26:21 +0300804 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300805 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300806 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300807 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700808 }
809 }
810 }
811 }
812 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700813
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300814 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700815}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700816
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300817static bool
818chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821{
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867}
868
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300869bool intel_crtc_active(struct drm_crtc *crtc)
870{
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100876 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300877 * as Haswell has gained clock readout/fastboot support.
878 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000879 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300880 * properly reconstruct framebuffers.
881 */
Matt Roperf4510a22014-04-01 15:22:40 -0700882 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100883 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300884}
885
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200886enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888{
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
Daniel Vetter3b117c82013-04-17 20:15:07 +0200892 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200893}
894
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200895static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
Paulo Zanonia928d532012-05-04 17:18:15 -0300896{
897 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
Jesse Barnes93937072014-04-04 16:12:09 -0700903 WARN(1, "vblank wait timed out\n");
Paulo Zanonia928d532012-05-04 17:18:15 -0300904}
905
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700906/**
907 * intel_wait_for_vblank - wait for vblank on a given pipe
908 * @dev: drm device
909 * @pipe: pipe to wait for
910 *
911 * Wait for vblank to occur on a given pipe. Needed for various bits of
912 * mode setting code.
913 */
914void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800915{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700916 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800917 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700918
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200919 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
920 g4x_wait_for_vblank(dev, pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300921 return;
922 }
923
Chris Wilson300387c2010-09-05 20:25:43 +0100924 /* Clear existing vblank status. Note this will clear any other
925 * sticky status fields as well.
926 *
927 * This races with i915_driver_irq_handler() with the result
928 * that either function could miss a vblank event. Here it is not
929 * fatal, as we will either wait upon the next vblank interrupt or
930 * timeout. Generally speaking intel_wait_for_vblank() is only
931 * called during modeset at which time the GPU should be idle and
932 * should *not* be performing page flips and thus not waiting on
933 * vblanks...
934 * Currently, the result of us stealing a vblank from the irq
935 * handler is that a single frame will be skipped during swapbuffers.
936 */
937 I915_WRITE(pipestat_reg,
938 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
939
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700940 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100941 if (wait_for(I915_READ(pipestat_reg) &
942 PIPE_VBLANK_INTERRUPT_STATUS,
943 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700944 DRM_DEBUG_KMS("vblank wait timed out\n");
945}
946
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300947static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
948{
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 reg = PIPEDSL(pipe);
951 u32 line1, line2;
952 u32 line_mask;
953
954 if (IS_GEN2(dev))
955 line_mask = DSL_LINEMASK_GEN2;
956 else
957 line_mask = DSL_LINEMASK_GEN3;
958
959 line1 = I915_READ(reg) & line_mask;
960 mdelay(5);
961 line2 = I915_READ(reg) & line_mask;
962
963 return line1 == line2;
964}
965
Keith Packardab7ad7f2010-10-03 00:33:06 -0700966/*
967 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700968 * @dev: drm device
969 * @pipe: pipe to wait for
970 *
971 * After disabling a pipe, we can't wait for vblank in the usual way,
972 * spinning on the vblank interrupt status bit, since we won't actually
973 * see an interrupt when the pipe is disabled.
974 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700975 * On Gen4 and above:
976 * wait for the pipe register state bit to turn off
977 *
978 * Otherwise:
979 * wait for the display line value to settle (it usually
980 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100981 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700982 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100983void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700984{
985 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200986 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
987 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700988
Keith Packardab7ad7f2010-10-03 00:33:06 -0700989 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200990 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700991
Keith Packardab7ad7f2010-10-03 00:33:06 -0700992 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100993 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
994 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200995 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700996 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700997 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300998 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200999 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001000 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001001}
1002
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001003/*
1004 * ibx_digital_port_connected - is the specified port connected?
1005 * @dev_priv: i915 private structure
1006 * @port: the port to test
1007 *
1008 * Returns true if @port is connected, false otherwise.
1009 */
1010bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1011 struct intel_digital_port *port)
1012{
1013 u32 bit;
1014
Damien Lespiauc36346e2012-12-13 16:09:03 +00001015 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +02001016 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001017 case PORT_B:
1018 bit = SDE_PORTB_HOTPLUG;
1019 break;
1020 case PORT_C:
1021 bit = SDE_PORTC_HOTPLUG;
1022 break;
1023 case PORT_D:
1024 bit = SDE_PORTD_HOTPLUG;
1025 break;
1026 default:
1027 return true;
1028 }
1029 } else {
Robin Schroereba905b2014-05-18 02:24:50 +02001030 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001031 case PORT_B:
1032 bit = SDE_PORTB_HOTPLUG_CPT;
1033 break;
1034 case PORT_C:
1035 bit = SDE_PORTC_HOTPLUG_CPT;
1036 break;
1037 case PORT_D:
1038 bit = SDE_PORTD_HOTPLUG_CPT;
1039 break;
1040 default:
1041 return true;
1042 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001043 }
1044
1045 return I915_READ(SDEISR) & bit;
1046}
1047
Jesse Barnesb24e7172011-01-04 15:09:30 -08001048static const char *state_string(bool enabled)
1049{
1050 return enabled ? "on" : "off";
1051}
1052
1053/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001054void assert_pll(struct drm_i915_private *dev_priv,
1055 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001056{
1057 int reg;
1058 u32 val;
1059 bool cur_state;
1060
1061 reg = DPLL(pipe);
1062 val = I915_READ(reg);
1063 cur_state = !!(val & DPLL_VCO_ENABLE);
1064 WARN(cur_state != state,
1065 "PLL state assertion failure (expected %s, current %s)\n",
1066 state_string(state), state_string(cur_state));
1067}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001068
Jani Nikula23538ef2013-08-27 15:12:22 +03001069/* XXX: the dsi pll is shared between MIPI DSI ports */
1070static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1071{
1072 u32 val;
1073 bool cur_state;
1074
1075 mutex_lock(&dev_priv->dpio_lock);
1076 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1077 mutex_unlock(&dev_priv->dpio_lock);
1078
1079 cur_state = val & DSI_PLL_VCO_EN;
1080 WARN(cur_state != state,
1081 "DSI PLL state assertion failure (expected %s, current %s)\n",
1082 state_string(state), state_string(cur_state));
1083}
1084#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1085#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1086
Daniel Vetter55607e82013-06-16 21:42:39 +02001087struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001088intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001089{
Daniel Vettere2b78262013-06-07 23:10:03 +02001090 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1091
Daniel Vettera43f6e02013-06-07 23:10:32 +02001092 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001093 return NULL;
1094
Daniel Vettera43f6e02013-06-07 23:10:32 +02001095 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001096}
1097
Jesse Barnesb24e7172011-01-04 15:09:30 -08001098/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001099void assert_shared_dpll(struct drm_i915_private *dev_priv,
1100 struct intel_shared_dpll *pll,
1101 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001102{
Jesse Barnes040484a2011-01-03 12:14:26 -08001103 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001104 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001105
Chris Wilson92b27b02012-05-20 18:10:50 +01001106 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001107 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001108 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001109
Daniel Vetter53589012013-06-05 13:34:16 +02001110 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001111 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001112 "%s assertion failure (expected %s, current %s)\n",
1113 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001114}
Jesse Barnes040484a2011-01-03 12:14:26 -08001115
1116static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state)
1118{
1119 int reg;
1120 u32 val;
1121 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1123 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001124
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001125 if (HAS_DDI(dev_priv->dev)) {
1126 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001127 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001128 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001129 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001130 } else {
1131 reg = FDI_TX_CTL(pipe);
1132 val = I915_READ(reg);
1133 cur_state = !!(val & FDI_TX_ENABLE);
1134 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001135 WARN(cur_state != state,
1136 "FDI TX state assertion failure (expected %s, current %s)\n",
1137 state_string(state), state_string(cur_state));
1138}
1139#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1140#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141
1142static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144{
1145 int reg;
1146 u32 val;
1147 bool cur_state;
1148
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001149 reg = FDI_RX_CTL(pipe);
1150 val = I915_READ(reg);
1151 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001152 WARN(cur_state != state,
1153 "FDI RX state assertion failure (expected %s, current %s)\n",
1154 state_string(state), state_string(cur_state));
1155}
1156#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161{
1162 int reg;
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001166 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001167 return;
1168
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001170 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001171 return;
1172
Jesse Barnes040484a2011-01-03 12:14:26 -08001173 reg = FDI_TX_CTL(pipe);
1174 val = I915_READ(reg);
1175 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176}
1177
Daniel Vetter55607e82013-06-16 21:42:39 +02001178void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1179 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001180{
1181 int reg;
1182 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001183 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001184
1185 reg = FDI_RX_CTL(pipe);
1186 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001187 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1188 WARN(cur_state != state,
1189 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001191}
1192
Jesse Barnesea0760c2011-01-04 15:09:32 -08001193static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
1195{
1196 int pp_reg, lvds_reg;
1197 u32 val;
1198 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001199 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001200
1201 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1202 pp_reg = PCH_PP_CONTROL;
1203 lvds_reg = PCH_LVDS;
1204 } else {
1205 pp_reg = PP_CONTROL;
1206 lvds_reg = LVDS;
1207 }
1208
1209 val = I915_READ(pp_reg);
1210 if (!(val & PANEL_POWER_ON) ||
1211 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1212 locked = false;
1213
1214 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216
1217 WARN(panel_pipe == pipe && locked,
1218 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001219 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001220}
1221
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001222static void assert_cursor(struct drm_i915_private *dev_priv,
1223 enum pipe pipe, bool state)
1224{
1225 struct drm_device *dev = dev_priv->dev;
1226 bool cur_state;
1227
Paulo Zanonid9d82082014-02-27 16:30:56 -03001228 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001229 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001230 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001231 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001232
1233 WARN(cur_state != state,
1234 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1235 pipe_name(pipe), state_string(state), state_string(cur_state));
1236}
1237#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1238#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1239
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001240void assert_pipe(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001242{
1243 int reg;
1244 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001245 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1247 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001248
Daniel Vetter8e636782012-01-22 01:36:48 +01001249 /* if we need the pipe A quirk it must be always on */
1250 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1251 state = true;
1252
Imre Deakda7e29b2014-02-18 00:02:02 +02001253 if (!intel_display_power_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001254 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001255 cur_state = false;
1256 } else {
1257 reg = PIPECONF(cpu_transcoder);
1258 val = I915_READ(reg);
1259 cur_state = !!(val & PIPECONF_ENABLE);
1260 }
1261
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001262 WARN(cur_state != state,
1263 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001264 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001265}
1266
Chris Wilson931872f2012-01-16 23:01:13 +00001267static void assert_plane(struct drm_i915_private *dev_priv,
1268 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001269{
1270 int reg;
1271 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001272 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001273
1274 reg = DSPCNTR(plane);
1275 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001276 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1277 WARN(cur_state != state,
1278 "plane %c assertion failure (expected %s, current %s)\n",
1279 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001280}
1281
Chris Wilson931872f2012-01-16 23:01:13 +00001282#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1283#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1284
Jesse Barnesb24e7172011-01-04 15:09:30 -08001285static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe)
1287{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001288 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001289 int reg, i;
1290 u32 val;
1291 int cur_pipe;
1292
Ville Syrjälä653e1022013-06-04 13:49:05 +03001293 /* Primary planes are fixed to pipes on gen4+ */
1294 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001295 reg = DSPCNTR(pipe);
1296 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001297 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001298 "plane %c assertion failure, should be disabled but not\n",
1299 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001300 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001301 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001302
Jesse Barnesb24e7172011-01-04 15:09:30 -08001303 /* Need to check both planes against the pipe */
Damien Lespiau08e2a7d2013-07-11 20:10:54 +01001304 for_each_pipe(i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001305 reg = DSPCNTR(i);
1306 val = I915_READ(reg);
1307 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1308 DISPPLANE_SEL_PIPE_SHIFT;
1309 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001310 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1311 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001312 }
1313}
1314
Jesse Barnes19332d72013-03-28 09:55:38 -07001315static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001318 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001319 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001320 u32 val;
1321
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001322 if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001323 for_each_sprite(pipe, sprite) {
1324 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001325 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001326 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001328 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001329 }
1330 } else if (INTEL_INFO(dev)->gen >= 7) {
1331 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001332 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001333 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001334 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001335 plane_name(pipe), pipe_name(pipe));
1336 } else if (INTEL_INFO(dev)->gen >= 5) {
1337 reg = DVSCNTR(pipe);
1338 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001339 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001340 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1341 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001342 }
1343}
1344
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001345static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001346{
1347 u32 val;
1348 bool enabled;
1349
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001350 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001351
Jesse Barnes92f25842011-01-04 15:09:34 -08001352 val = I915_READ(PCH_DREF_CONTROL);
1353 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1354 DREF_SUPERSPREAD_SOURCE_MASK));
1355 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1356}
1357
Daniel Vetterab9412b2013-05-03 11:49:46 +02001358static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1359 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001360{
1361 int reg;
1362 u32 val;
1363 bool enabled;
1364
Daniel Vetterab9412b2013-05-03 11:49:46 +02001365 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001366 val = I915_READ(reg);
1367 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001368 WARN(enabled,
1369 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1370 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001371}
1372
Keith Packard4e634382011-08-06 10:39:45 -07001373static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001375{
1376 if ((val & DP_PORT_EN) == 0)
1377 return false;
1378
1379 if (HAS_PCH_CPT(dev_priv->dev)) {
1380 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1381 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1382 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1383 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001384 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1385 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001387 } else {
1388 if ((val & DP_PIPE_MASK) != (pipe << 30))
1389 return false;
1390 }
1391 return true;
1392}
1393
Keith Packard1519b992011-08-06 10:35:34 -07001394static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe, u32 val)
1396{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001397 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001398 return false;
1399
1400 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001401 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001402 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001403 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1404 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001406 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001407 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001408 return false;
1409 }
1410 return true;
1411}
1412
1413static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, u32 val)
1415{
1416 if ((val & LVDS_PORT_EN) == 0)
1417 return false;
1418
1419 if (HAS_PCH_CPT(dev_priv->dev)) {
1420 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421 return false;
1422 } else {
1423 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1424 return false;
1425 }
1426 return true;
1427}
1428
1429static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1430 enum pipe pipe, u32 val)
1431{
1432 if ((val & ADPA_DAC_ENABLE) == 0)
1433 return false;
1434 if (HAS_PCH_CPT(dev_priv->dev)) {
1435 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 return false;
1437 } else {
1438 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1439 return false;
1440 }
1441 return true;
1442}
1443
Jesse Barnes291906f2011-02-02 12:28:03 -08001444static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001445 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001446{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001447 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001448 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001449 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001450 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001451
Daniel Vetter75c5da22012-09-10 21:58:29 +02001452 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1453 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001454 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001455}
1456
1457static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1458 enum pipe pipe, int reg)
1459{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001460 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001461 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001462 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001463 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001464
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001465 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001466 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001467 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001468}
1469
1470static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1471 enum pipe pipe)
1472{
1473 int reg;
1474 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001475
Keith Packardf0575e92011-07-25 22:12:43 -07001476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1477 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1478 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001479
1480 reg = PCH_ADPA;
1481 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001482 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001483 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001484 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001485
1486 reg = PCH_LVDS;
1487 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001488 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001489 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001490 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001491
Paulo Zanonie2debe92013-02-18 19:00:27 -03001492 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1493 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1494 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001495}
1496
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001497static void intel_init_dpio(struct drm_device *dev)
1498{
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500
1501 if (!IS_VALLEYVIEW(dev))
1502 return;
1503
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001504 /*
1505 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1506 * CHV x1 PHY (DP/HDMI D)
1507 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1508 */
1509 if (IS_CHERRYVIEW(dev)) {
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1511 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1512 } else {
1513 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1514 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001515}
1516
Daniel Vetter426115c2013-07-11 22:13:42 +02001517static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001518{
Daniel Vetter426115c2013-07-11 22:13:42 +02001519 struct drm_device *dev = crtc->base.dev;
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 int reg = DPLL(crtc->pipe);
1522 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001523
Daniel Vetter426115c2013-07-11 22:13:42 +02001524 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001525
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001526 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001527 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1528
1529 /* PLL is protected by panel, make sure we can write it */
1530 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001531 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001532
Daniel Vetter426115c2013-07-11 22:13:42 +02001533 I915_WRITE(reg, dpll);
1534 POSTING_READ(reg);
1535 udelay(150);
1536
1537 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1538 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1539
1540 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1541 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001542
1543 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001544 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001547 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001548 POSTING_READ(reg);
1549 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001550 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001551 POSTING_READ(reg);
1552 udelay(150); /* wait for warmup */
1553}
1554
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001555static void chv_enable_pll(struct intel_crtc *crtc)
1556{
1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int pipe = crtc->pipe;
1560 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001561 u32 tmp;
1562
1563 assert_pipe_disabled(dev_priv, crtc->pipe);
1564
1565 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1566
1567 mutex_lock(&dev_priv->dpio_lock);
1568
1569 /* Enable back the 10bit clock to display controller */
1570 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1571 tmp |= DPIO_DCLKP_EN;
1572 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1573
1574 /*
1575 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1576 */
1577 udelay(1);
1578
1579 /* Enable PLL */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001580 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001581
1582 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001583 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001584 DRM_ERROR("PLL %d failed to lock\n", pipe);
1585
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001586 /* not sure when this should be written */
1587 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1588 POSTING_READ(DPLL_MD(pipe));
1589
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001590 mutex_unlock(&dev_priv->dpio_lock);
1591}
1592
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001593static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001594{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001595 struct drm_device *dev = crtc->base.dev;
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597 int reg = DPLL(crtc->pipe);
1598 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001599
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001600 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001601
1602 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001603 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001604
1605 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001606 if (IS_MOBILE(dev) && !IS_I830(dev))
1607 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001608
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001609 I915_WRITE(reg, dpll);
1610
1611 /* Wait for the clocks to stabilize. */
1612 POSTING_READ(reg);
1613 udelay(150);
1614
1615 if (INTEL_INFO(dev)->gen >= 4) {
1616 I915_WRITE(DPLL_MD(crtc->pipe),
1617 crtc->config.dpll_hw_state.dpll_md);
1618 } else {
1619 /* The pixel multiplier can only be updated once the
1620 * DPLL is enabled and the clocks are stable.
1621 *
1622 * So write it again.
1623 */
1624 I915_WRITE(reg, dpll);
1625 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001626
1627 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001628 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001631 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001634 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001635 POSTING_READ(reg);
1636 udelay(150); /* wait for warmup */
1637}
1638
1639/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001640 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001641 * @dev_priv: i915 private structure
1642 * @pipe: pipe PLL to disable
1643 *
1644 * Disable the PLL for @pipe, making sure the pipe is off first.
1645 *
1646 * Note! This is for pre-ILK only.
1647 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001648static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001649{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001650 /* Don't disable pipe A or pipe A PLLs if needed */
1651 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1652 return;
1653
1654 /* Make sure the pipe isn't still relying on us */
1655 assert_pipe_disabled(dev_priv, pipe);
1656
Daniel Vetter50b44a42013-06-05 13:34:33 +02001657 I915_WRITE(DPLL(pipe), 0);
1658 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001659}
1660
Jesse Barnesf6071162013-10-01 10:41:38 -07001661static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662{
1663 u32 val = 0;
1664
1665 /* Make sure the pipe isn't still relying on us */
1666 assert_pipe_disabled(dev_priv, pipe);
1667
Imre Deake5cbfbf2014-01-09 17:08:16 +02001668 /*
1669 * Leave integrated clock source and reference clock enabled for pipe B.
1670 * The latter is needed for VGA hotplug / manual detection.
1671 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001672 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001673 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001674 I915_WRITE(DPLL(pipe), val);
1675 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001676
1677}
1678
1679static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1680{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001681 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001682 u32 val;
1683
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001686
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001687 /* Set PLL en = 0 */
Ville Syrjäläd17ec4c2014-06-28 02:03:59 +03001688 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001689 if (pipe != PIPE_A)
1690 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1691 I915_WRITE(DPLL(pipe), val);
1692 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001693
1694 mutex_lock(&dev_priv->dpio_lock);
1695
1696 /* Disable 10bit clock to display controller */
1697 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1698 val &= ~DPIO_DCLKP_EN;
1699 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1700
Ville Syrjälä61407f62014-05-27 16:32:55 +03001701 /* disable left/right clock distribution */
1702 if (pipe != PIPE_B) {
1703 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1704 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1705 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1706 } else {
1707 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1708 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1709 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1710 }
1711
Ville Syrjäläd7520482014-04-09 13:28:59 +03001712 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001713}
1714
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001715void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1716 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001717{
1718 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001719 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001720
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001721 switch (dport->port) {
1722 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001723 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001724 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001725 break;
1726 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001727 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001728 dpll_reg = DPLL(0);
1729 break;
1730 case PORT_D:
1731 port_mask = DPLL_PORTD_READY_MASK;
1732 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001733 break;
1734 default:
1735 BUG();
1736 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001737
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001738 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001739 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001740 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001741}
1742
Daniel Vetterb14b1052014-04-24 23:55:13 +02001743static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1744{
1745 struct drm_device *dev = crtc->base.dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1748
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001749 if (WARN_ON(pll == NULL))
1750 return;
1751
Daniel Vetterb14b1052014-04-24 23:55:13 +02001752 WARN_ON(!pll->refcount);
1753 if (pll->active == 0) {
1754 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1755 WARN_ON(pll->on);
1756 assert_shared_dpll_disabled(dev_priv, pll);
1757
1758 pll->mode_set(dev_priv, pll);
1759 }
1760}
1761
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001762/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001763 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001764 * @dev_priv: i915 private structure
1765 * @pipe: pipe PLL to enable
1766 *
1767 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768 * drives the transcoder clock.
1769 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001770static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001771{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001774 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001775
Daniel Vetter87a875b2013-06-05 13:34:19 +02001776 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001777 return;
1778
1779 if (WARN_ON(pll->refcount == 0))
1780 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001781
Damien Lespiau74dd6922014-07-29 18:06:17 +01001782 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
Daniel Vetter46edb022013-06-05 13:34:12 +02001783 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001784 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001785
Daniel Vettercdbd2312013-06-05 13:34:03 +02001786 if (pll->active++) {
1787 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001788 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001789 return;
1790 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001791 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001792
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001793 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1794
Daniel Vetter46edb022013-06-05 13:34:12 +02001795 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001796 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001797 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001798}
1799
Daniel Vetter716c2e52014-06-25 22:02:02 +03001800void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001801{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001805
Jesse Barnes92f25842011-01-04 15:09:34 -08001806 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001807 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001808 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001809 return;
1810
Chris Wilson48da64a2012-05-13 20:16:12 +01001811 if (WARN_ON(pll->refcount == 0))
1812 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001813
Daniel Vetter46edb022013-06-05 13:34:12 +02001814 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001816 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001817
Chris Wilson48da64a2012-05-13 20:16:12 +01001818 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001819 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001820 return;
1821 }
1822
Daniel Vettere9d69442013-06-05 13:34:15 +02001823 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001824 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001825 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001826 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001827
Daniel Vetter46edb022013-06-05 13:34:12 +02001828 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001829 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001830 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001831
1832 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001833}
1834
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001835static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1836 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001837{
Daniel Vetter23670b322012-11-01 09:15:30 +01001838 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001839 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001841 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001842
1843 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001844 BUG_ON(INTEL_INFO(dev)->gen < 5);
Jesse Barnes040484a2011-01-03 12:14:26 -08001845
1846 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001847 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001848 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001849
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, pipe);
1852 assert_fdi_rx_enabled(dev_priv, pipe);
1853
Daniel Vetter23670b322012-11-01 09:15:30 +01001854 if (HAS_PCH_CPT(dev)) {
1855 /* Workaround: Set the timing override bit before enabling the
1856 * pch transcoder. */
1857 reg = TRANS_CHICKEN2(pipe);
1858 val = I915_READ(reg);
1859 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1860 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001861 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001862
Daniel Vetterab9412b2013-05-03 11:49:46 +02001863 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001864 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001865 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001866
1867 if (HAS_PCH_IBX(dev_priv->dev)) {
1868 /*
1869 * make the BPC in transcoder be consistent with
1870 * that in pipeconf reg.
1871 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001872 val &= ~PIPECONF_BPC_MASK;
1873 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001874 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001875
1876 val &= ~TRANS_INTERLACE_MASK;
1877 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001878 if (HAS_PCH_IBX(dev_priv->dev) &&
1879 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1880 val |= TRANS_LEGACY_INTERLACED_ILK;
1881 else
1882 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001883 else
1884 val |= TRANS_PROGRESSIVE;
1885
Jesse Barnes040484a2011-01-03 12:14:26 -08001886 I915_WRITE(reg, val | TRANS_ENABLE);
1887 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001888 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001889}
1890
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001891static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001892 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001893{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001894 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001895
1896 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001897 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001898
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001899 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001900 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001901 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001902
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001903 /* Workaround: set timing override bit. */
1904 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001905 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001906 I915_WRITE(_TRANSA_CHICKEN2, val);
1907
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001908 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001909 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001910
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001911 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1912 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001913 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001914 else
1915 val |= TRANS_PROGRESSIVE;
1916
Daniel Vetterab9412b2013-05-03 11:49:46 +02001917 I915_WRITE(LPT_TRANSCONF, val);
1918 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001919 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001920}
1921
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001922static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1923 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001924{
Daniel Vetter23670b322012-11-01 09:15:30 +01001925 struct drm_device *dev = dev_priv->dev;
1926 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001927
1928 /* FDI relies on the transcoder */
1929 assert_fdi_tx_disabled(dev_priv, pipe);
1930 assert_fdi_rx_disabled(dev_priv, pipe);
1931
Jesse Barnes291906f2011-02-02 12:28:03 -08001932 /* Ports must be off as well */
1933 assert_pch_ports_disabled(dev_priv, pipe);
1934
Daniel Vetterab9412b2013-05-03 11:49:46 +02001935 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001936 val = I915_READ(reg);
1937 val &= ~TRANS_ENABLE;
1938 I915_WRITE(reg, val);
1939 /* wait for PCH transcoder off, transcoder state */
1940 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001941 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001942
1943 if (!HAS_PCH_IBX(dev)) {
1944 /* Workaround: Clear the timing override chicken bit again. */
1945 reg = TRANS_CHICKEN2(pipe);
1946 val = I915_READ(reg);
1947 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1948 I915_WRITE(reg, val);
1949 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001950}
1951
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001952static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001953{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001954 u32 val;
1955
Daniel Vetterab9412b2013-05-03 11:49:46 +02001956 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001957 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001958 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001959 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001960 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001961 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001962
1963 /* Workaround: clear timing override bit. */
1964 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001965 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001966 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001967}
1968
1969/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001970 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02001971 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001972 *
Paulo Zanoni03722642014-01-17 13:51:09 -02001973 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001974 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08001975 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02001976static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001977{
Paulo Zanoni03722642014-01-17 13:51:09 -02001978 struct drm_device *dev = crtc->base.dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001981 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1982 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001983 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001984 int reg;
1985 u32 val;
1986
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001987 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001988 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001989 assert_sprites_disabled(dev_priv, pipe);
1990
Paulo Zanoni681e5812012-12-06 11:12:38 -02001991 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001992 pch_transcoder = TRANSCODER_A;
1993 else
1994 pch_transcoder = pipe;
1995
Jesse Barnesb24e7172011-01-04 15:09:30 -08001996 /*
1997 * A pipe without a PLL won't actually be able to drive bits from
1998 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1999 * need the check.
2000 */
2001 if (!HAS_PCH_SPLIT(dev_priv->dev))
Paulo Zanonifbf32182014-01-17 13:51:11 -02002002 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002003 assert_dsi_pll_enabled(dev_priv);
2004 else
2005 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002006 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002007 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002008 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002009 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002010 assert_fdi_tx_pll_enabled(dev_priv,
2011 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002012 }
2013 /* FIXME: assert CPU port conditions for SNB+ */
2014 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002015
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002016 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002017 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002018 if (val & PIPECONF_ENABLE) {
2019 WARN_ON(!(pipe == PIPE_A &&
2020 dev_priv->quirks & QUIRK_PIPEA_FORCE));
Chris Wilson00d70b12011-03-17 07:18:29 +00002021 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002022 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002023
2024 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002025 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002026}
2027
2028/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002029 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002030 * @dev_priv: i915 private structure
2031 * @pipe: pipe to disable
2032 *
2033 * Disable @pipe, making sure that various hardware specific requirements
2034 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2035 *
2036 * @pipe should be %PIPE_A or %PIPE_B.
2037 *
2038 * Will wait until the pipe has shut down before returning.
2039 */
2040static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2041 enum pipe pipe)
2042{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002043 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2044 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002045 int reg;
2046 u32 val;
2047
2048 /*
2049 * Make sure planes won't keep trying to pump pixels to us,
2050 * or we might hang the display.
2051 */
2052 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002053 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002054 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002055
2056 /* Don't disable pipe A or pipe A PLLs if needed */
2057 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2058 return;
2059
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002060 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002061 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002062 if ((val & PIPECONF_ENABLE) == 0)
2063 return;
2064
2065 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002066 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2067}
2068
Keith Packardd74362c2011-07-28 14:47:14 -07002069/*
2070 * Plane regs are double buffered, going from enabled->disabled needs a
2071 * trigger in order to latch. The display address reg provides this.
2072 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002073void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2074 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002075{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002076 struct drm_device *dev = dev_priv->dev;
2077 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002078
2079 I915_WRITE(reg, I915_READ(reg));
2080 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002081}
2082
Jesse Barnesb24e7172011-01-04 15:09:30 -08002083/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002084 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002085 * @dev_priv: i915 private structure
2086 * @plane: plane to enable
2087 * @pipe: pipe being fed
2088 *
2089 * Enable @plane on @pipe, making sure that @pipe is running first.
2090 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002091static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2092 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002093{
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002094 struct drm_device *dev = dev_priv->dev;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002095 struct intel_crtc *intel_crtc =
2096 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002097 int reg;
2098 u32 val;
2099
2100 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2101 assert_pipe_enabled(dev_priv, pipe);
2102
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002103 if (intel_crtc->primary_enabled)
2104 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002105
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002106 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002107
Jesse Barnesb24e7172011-01-04 15:09:30 -08002108 reg = DSPCNTR(plane);
2109 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002110 WARN_ON(val & DISPLAY_PLANE_ENABLE);
Chris Wilson00d70b12011-03-17 07:18:29 +00002111
2112 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002113 intel_flush_primary_plane(dev_priv, plane);
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002114
2115 /*
2116 * BDW signals flip done immediately if the plane
2117 * is disabled, even if the plane enable is already
2118 * armed to occur at the next vblank :(
2119 */
2120 if (IS_BROADWELL(dev))
2121 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002122}
2123
Jesse Barnesb24e7172011-01-04 15:09:30 -08002124/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002125 * intel_disable_primary_hw_plane - disable the primary hardware plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002126 * @dev_priv: i915 private structure
2127 * @plane: plane to disable
2128 * @pipe: pipe consuming the data
2129 *
2130 * Disable @plane; should be an independent operation.
2131 */
Matt Roper262ca2b2014-03-18 17:22:55 -07002132static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2133 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002134{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002135 struct intel_crtc *intel_crtc =
2136 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002137 int reg;
2138 u32 val;
2139
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002140 if (!intel_crtc->primary_enabled)
2141 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002142
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002143 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002144
Jesse Barnesb24e7172011-01-04 15:09:30 -08002145 reg = DSPCNTR(plane);
2146 val = I915_READ(reg);
Ville Syrjälä10efa932014-04-28 15:53:25 +03002147 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
Chris Wilson00d70b12011-03-17 07:18:29 +00002148
2149 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002150 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002151}
2152
Chris Wilson693db182013-03-05 14:52:39 +00002153static bool need_vtd_wa(struct drm_device *dev)
2154{
2155#ifdef CONFIG_INTEL_IOMMU
2156 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2157 return true;
2158#endif
2159 return false;
2160}
2161
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002162static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2163{
2164 int tile_height;
2165
2166 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2167 return ALIGN(height, tile_height);
2168}
2169
Chris Wilson127bd2a2010-07-23 23:32:05 +01002170int
Chris Wilson48b956c2010-09-14 12:50:34 +01002171intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002172 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002173 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002174{
Chris Wilsonce453d82011-02-21 14:43:56 +00002175 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002176 u32 alignment;
2177 int ret;
2178
Matt Roperebcdd392014-07-09 16:22:11 -07002179 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2180
Chris Wilson05394f32010-11-08 19:18:58 +00002181 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002182 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002183 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2184 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002185 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002186 alignment = 4 * 1024;
2187 else
2188 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002189 break;
2190 case I915_TILING_X:
2191 /* pin() will align the object as required by fence */
2192 alignment = 0;
2193 break;
2194 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002195 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002196 return -EINVAL;
2197 default:
2198 BUG();
2199 }
2200
Chris Wilson693db182013-03-05 14:52:39 +00002201 /* Note that the w/a also requires 64 PTE of padding following the
2202 * bo. We currently fill all unused PTE with the shadow page and so
2203 * we should always have valid PTE following the scanout preventing
2204 * the VT-d warning.
2205 */
2206 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2207 alignment = 256 * 1024;
2208
Chris Wilsonce453d82011-02-21 14:43:56 +00002209 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002210 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002211 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002212 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002213
2214 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2215 * fence, whereas 965+ only requires a fence if using
2216 * framebuffer compression. For simplicity, we always install
2217 * a fence as the cost is not that onerous.
2218 */
Chris Wilson06d98132012-04-17 15:31:24 +01002219 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002220 if (ret)
2221 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002222
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002223 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002224
Chris Wilsonce453d82011-02-21 14:43:56 +00002225 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002226 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002227
2228err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002229 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002230err_interruptible:
2231 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002232 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002233}
2234
Chris Wilson1690e1e2011-12-14 13:57:08 +01002235void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2236{
Matt Roperebcdd392014-07-09 16:22:11 -07002237 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2238
Chris Wilson1690e1e2011-12-14 13:57:08 +01002239 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002240 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002241}
2242
Daniel Vetterc2c75132012-07-05 12:17:30 +02002243/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2244 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002245unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2246 unsigned int tiling_mode,
2247 unsigned int cpp,
2248 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002249{
Chris Wilsonbc752862013-02-21 20:04:31 +00002250 if (tiling_mode != I915_TILING_NONE) {
2251 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002252
Chris Wilsonbc752862013-02-21 20:04:31 +00002253 tile_rows = *y / 8;
2254 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002255
Chris Wilsonbc752862013-02-21 20:04:31 +00002256 tiles = *x / (512/cpp);
2257 *x %= 512/cpp;
2258
2259 return tile_rows * pitch * 8 + tiles * 4096;
2260 } else {
2261 unsigned int offset;
2262
2263 offset = *y * pitch + *x * cpp;
2264 *y = 0;
2265 *x = (offset & 4095) / cpp;
2266 return offset & -4096;
2267 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002268}
2269
Jesse Barnes46f297f2014-03-07 08:57:48 -08002270int intel_format_to_fourcc(int format)
2271{
2272 switch (format) {
2273 case DISPPLANE_8BPP:
2274 return DRM_FORMAT_C8;
2275 case DISPPLANE_BGRX555:
2276 return DRM_FORMAT_XRGB1555;
2277 case DISPPLANE_BGRX565:
2278 return DRM_FORMAT_RGB565;
2279 default:
2280 case DISPPLANE_BGRX888:
2281 return DRM_FORMAT_XRGB8888;
2282 case DISPPLANE_RGBX888:
2283 return DRM_FORMAT_XBGR8888;
2284 case DISPPLANE_BGRX101010:
2285 return DRM_FORMAT_XRGB2101010;
2286 case DISPPLANE_RGBX101010:
2287 return DRM_FORMAT_XBGR2101010;
2288 }
2289}
2290
Jesse Barnes484b41d2014-03-07 08:57:55 -08002291static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002292 struct intel_plane_config *plane_config)
2293{
2294 struct drm_device *dev = crtc->base.dev;
2295 struct drm_i915_gem_object *obj = NULL;
2296 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2297 u32 base = plane_config->base;
2298
Chris Wilsonff2652e2014-03-10 08:07:02 +00002299 if (plane_config->size == 0)
2300 return false;
2301
Jesse Barnes46f297f2014-03-07 08:57:48 -08002302 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2303 plane_config->size);
2304 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002305 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002306
2307 if (plane_config->tiled) {
2308 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002309 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002310 }
2311
Dave Airlie66e514c2014-04-03 07:51:54 +10002312 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2313 mode_cmd.width = crtc->base.primary->fb->width;
2314 mode_cmd.height = crtc->base.primary->fb->height;
2315 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002316
2317 mutex_lock(&dev->struct_mutex);
2318
Dave Airlie66e514c2014-04-03 07:51:54 +10002319 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002320 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002321 DRM_DEBUG_KMS("intel fb init failed\n");
2322 goto out_unref_obj;
2323 }
2324
Daniel Vettera071fa02014-06-18 23:28:09 +02002325 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002326 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002327
2328 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2329 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002330
2331out_unref_obj:
2332 drm_gem_object_unreference(&obj->base);
2333 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002334 return false;
2335}
2336
2337static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2338 struct intel_plane_config *plane_config)
2339{
2340 struct drm_device *dev = intel_crtc->base.dev;
2341 struct drm_crtc *c;
2342 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002343 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002344
Dave Airlie66e514c2014-04-03 07:51:54 +10002345 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002346 return;
2347
2348 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2349 return;
2350
Dave Airlie66e514c2014-04-03 07:51:54 +10002351 kfree(intel_crtc->base.primary->fb);
2352 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002353
2354 /*
2355 * Failed to alloc the obj, check to see if we should share
2356 * an fb with another CRTC instead
2357 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002358 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002359 i = to_intel_crtc(c);
2360
2361 if (c == &intel_crtc->base)
2362 continue;
2363
Matt Roper2ff8fde2014-07-08 07:50:07 -07002364 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002365 continue;
2366
Matt Roper2ff8fde2014-07-08 07:50:07 -07002367 obj = intel_fb_obj(c->primary->fb);
2368 if (obj == NULL)
2369 continue;
2370
2371 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Dave Airlie66e514c2014-04-03 07:51:54 +10002372 drm_framebuffer_reference(c->primary->fb);
2373 intel_crtc->base.primary->fb = c->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002374 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002375 break;
2376 }
2377 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002378}
2379
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002380static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2381 struct drm_framebuffer *fb,
2382 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002383{
2384 struct drm_device *dev = crtc->dev;
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002387 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Jesse Barnes81255562010-08-02 12:07:50 -07002388 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002389 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002390 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002391 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002392
Chris Wilson5eddb702010-09-11 13:48:45 +01002393 reg = DSPCNTR(plane);
2394 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002395 /* Mask out pixel format bits in case we change it */
2396 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002397 switch (fb->pixel_format) {
2398 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002399 dspcntr |= DISPPLANE_8BPP;
2400 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002401 case DRM_FORMAT_XRGB1555:
2402 case DRM_FORMAT_ARGB1555:
2403 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002404 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002405 case DRM_FORMAT_RGB565:
2406 dspcntr |= DISPPLANE_BGRX565;
2407 break;
2408 case DRM_FORMAT_XRGB8888:
2409 case DRM_FORMAT_ARGB8888:
2410 dspcntr |= DISPPLANE_BGRX888;
2411 break;
2412 case DRM_FORMAT_XBGR8888:
2413 case DRM_FORMAT_ABGR8888:
2414 dspcntr |= DISPPLANE_RGBX888;
2415 break;
2416 case DRM_FORMAT_XRGB2101010:
2417 case DRM_FORMAT_ARGB2101010:
2418 dspcntr |= DISPPLANE_BGRX101010;
2419 break;
2420 case DRM_FORMAT_XBGR2101010:
2421 case DRM_FORMAT_ABGR2101010:
2422 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002423 break;
2424 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002425 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002426 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002427
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002428 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002429 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002430 dspcntr |= DISPPLANE_TILED;
2431 else
2432 dspcntr &= ~DISPPLANE_TILED;
2433 }
2434
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002435 if (IS_G4X(dev))
2436 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2437
Chris Wilson5eddb702010-09-11 13:48:45 +01002438 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002439
Daniel Vettere506a0c2012-07-05 12:17:29 +02002440 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002441
Daniel Vetterc2c75132012-07-05 12:17:30 +02002442 if (INTEL_INFO(dev)->gen >= 4) {
2443 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002444 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2445 fb->bits_per_pixel / 8,
2446 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002447 linear_offset -= intel_crtc->dspaddr_offset;
2448 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002449 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002450 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002451
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002452 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2453 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2454 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002455 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002456 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002457 I915_WRITE(DSPSURF(plane),
2458 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002459 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002460 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002461 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002462 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002463 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002464}
2465
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002466static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2467 struct drm_framebuffer *fb,
2468 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002469{
2470 struct drm_device *dev = crtc->dev;
2471 struct drm_i915_private *dev_priv = dev->dev_private;
2472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002473 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002474 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002475 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002476 u32 dspcntr;
2477 u32 reg;
2478
Jesse Barnes17638cd2011-06-24 12:19:23 -07002479 reg = DSPCNTR(plane);
2480 dspcntr = I915_READ(reg);
2481 /* Mask out pixel format bits in case we change it */
2482 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002483 switch (fb->pixel_format) {
2484 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002485 dspcntr |= DISPPLANE_8BPP;
2486 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002487 case DRM_FORMAT_RGB565:
2488 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002489 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002490 case DRM_FORMAT_XRGB8888:
2491 case DRM_FORMAT_ARGB8888:
2492 dspcntr |= DISPPLANE_BGRX888;
2493 break;
2494 case DRM_FORMAT_XBGR8888:
2495 case DRM_FORMAT_ABGR8888:
2496 dspcntr |= DISPPLANE_RGBX888;
2497 break;
2498 case DRM_FORMAT_XRGB2101010:
2499 case DRM_FORMAT_ARGB2101010:
2500 dspcntr |= DISPPLANE_BGRX101010;
2501 break;
2502 case DRM_FORMAT_XBGR2101010:
2503 case DRM_FORMAT_ABGR2101010:
2504 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002505 break;
2506 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002507 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002508 }
2509
2510 if (obj->tiling_mode != I915_TILING_NONE)
2511 dspcntr |= DISPPLANE_TILED;
2512 else
2513 dspcntr &= ~DISPPLANE_TILED;
2514
Ville Syrjäläb42c6002013-11-03 13:47:27 +02002515 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002516 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2517 else
2518 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002519
2520 I915_WRITE(reg, dspcntr);
2521
Daniel Vettere506a0c2012-07-05 12:17:29 +02002522 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002523 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002524 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525 fb->bits_per_pixel / 8,
2526 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002527 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002528
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002529 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2530 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2531 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002532 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002533 I915_WRITE(DSPSURF(plane),
2534 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002535 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002536 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2537 } else {
2538 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2539 I915_WRITE(DSPLINOFF(plane), linear_offset);
2540 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002541 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002542}
2543
2544/* Assume fb object is pinned & idle & fenced and just update base pointers */
2545static int
2546intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2547 int x, int y, enum mode_set_atomic state)
2548{
2549 struct drm_device *dev = crtc->dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002551
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002552 if (dev_priv->display.disable_fbc)
2553 dev_priv->display.disable_fbc(dev);
Daniel Vettercc365132014-06-18 13:59:13 +02002554 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
Jesse Barnes81255562010-08-02 12:07:50 -07002555
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002556 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2557
2558 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002559}
2560
Ville Syrjälä96a02912013-02-18 19:08:49 +02002561void intel_display_handle_reset(struct drm_device *dev)
2562{
2563 struct drm_i915_private *dev_priv = dev->dev_private;
2564 struct drm_crtc *crtc;
2565
2566 /*
2567 * Flips in the rings have been nuked by the reset,
2568 * so complete all pending flips so that user space
2569 * will get its events and not get stuck.
2570 *
2571 * Also update the base address of all primary
2572 * planes to the the last fb to make sure we're
2573 * showing the correct fb after a reset.
2574 *
2575 * Need to make two loops over the crtcs so that we
2576 * don't try to grab a crtc mutex before the
2577 * pending_flip_queue really got woken up.
2578 */
2579
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002580 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2582 enum plane plane = intel_crtc->plane;
2583
2584 intel_prepare_page_flip(dev, plane);
2585 intel_finish_page_flip_plane(dev, plane);
2586 }
2587
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002588 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2590
Rob Clark51fd3712013-11-19 12:10:12 -05002591 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002592 /*
2593 * FIXME: Once we have proper support for primary planes (and
2594 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002595 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002596 */
Matt Roperf4510a22014-04-01 15:22:40 -07002597 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002598 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002599 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002600 crtc->x,
2601 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05002602 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002603 }
2604}
2605
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002606static int
Chris Wilson14667a42012-04-03 17:58:35 +01002607intel_finish_fb(struct drm_framebuffer *old_fb)
2608{
Matt Roper2ff8fde2014-07-08 07:50:07 -07002609 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
Chris Wilson14667a42012-04-03 17:58:35 +01002610 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2611 bool was_interruptible = dev_priv->mm.interruptible;
2612 int ret;
2613
Chris Wilson14667a42012-04-03 17:58:35 +01002614 /* Big Hammer, we also need to ensure that any pending
2615 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2616 * current scanout is retired before unpinning the old
2617 * framebuffer.
2618 *
2619 * This should only fail upon a hung GPU, in which case we
2620 * can safely continue.
2621 */
2622 dev_priv->mm.interruptible = false;
2623 ret = i915_gem_object_finish_gpu(obj);
2624 dev_priv->mm.interruptible = was_interruptible;
2625
2626 return ret;
2627}
2628
Chris Wilson7d5e3792014-03-04 13:15:08 +00002629static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2630{
2631 struct drm_device *dev = crtc->dev;
2632 struct drm_i915_private *dev_priv = dev->dev_private;
2633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2634 unsigned long flags;
2635 bool pending;
2636
2637 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2638 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2639 return false;
2640
2641 spin_lock_irqsave(&dev->event_lock, flags);
2642 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2643 spin_unlock_irqrestore(&dev->event_lock, flags);
2644
2645 return pending;
2646}
2647
Chris Wilson14667a42012-04-03 17:58:35 +01002648static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002649intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002650 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002651{
2652 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002653 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02002655 enum pipe pipe = intel_crtc->pipe;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002656 struct drm_framebuffer *old_fb = crtc->primary->fb;
2657 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2658 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002659 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002660
Chris Wilson7d5e3792014-03-04 13:15:08 +00002661 if (intel_crtc_has_pending_flip(crtc)) {
2662 DRM_ERROR("pipe is still busy with an old pageflip\n");
2663 return -EBUSY;
2664 }
2665
Jesse Barnes79e53942008-11-07 14:24:08 -08002666 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002667 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002668 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002669 return 0;
2670 }
2671
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002672 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002673 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2674 plane_name(intel_crtc->plane),
2675 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002676 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002677 }
2678
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002679 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02002680 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2681 if (ret == 0)
Matt Roper91565c82014-06-24 17:05:02 -07002682 i915_gem_track_fb(old_obj, obj,
Daniel Vettera071fa02014-06-18 23:28:09 +02002683 INTEL_FRONTBUFFER_PRIMARY(pipe));
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002684 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002685 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002686 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002687 return ret;
2688 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002689
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002690 /*
2691 * Update pipe size and adjust fitter if needed: the reason for this is
2692 * that in compute_mode_changes we check the native mode (not the pfit
2693 * mode) to see if we can flip rather than do a full mode set. In the
2694 * fastboot case, we'll flip, but if we don't update the pipesrc and
2695 * pfit state, we'll end up with a big fb scanned out into the wrong
2696 * sized surface.
2697 *
2698 * To fix this properly, we need to hoist the checks up into
2699 * compute_mode_changes (or above), check the actual pfit state and
2700 * whether the platform allows pfit disable with pipe active, and only
2701 * then update the pipesrc and pfit state, even on the flip path.
2702 */
Jani Nikulad330a952014-01-21 11:24:25 +02002703 if (i915.fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002704 const struct drm_display_mode *adjusted_mode =
2705 &intel_crtc->config.adjusted_mode;
2706
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002707 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002708 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2709 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002710 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002711 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2712 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2713 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2714 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2715 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2716 }
Jesse Barnes0637d602013-12-19 10:48:01 -08002717 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2718 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002719 }
2720
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002721 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002722
Daniel Vetterf99d7062014-06-19 16:01:59 +02002723 if (intel_crtc->active)
2724 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2725
Matt Roperf4510a22014-04-01 15:22:40 -07002726 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002727 crtc->x = x;
2728 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002729
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002730 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002731 if (intel_crtc->active && old_fb != fb)
2732 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002733 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002734 intel_unpin_fb_obj(old_obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002735 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002736 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002737
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002738 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002739 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002740 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002741
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002742 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002743}
2744
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002745static void intel_fdi_normal_train(struct drm_crtc *crtc)
2746{
2747 struct drm_device *dev = crtc->dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2750 int pipe = intel_crtc->pipe;
2751 u32 reg, temp;
2752
2753 /* enable normal train */
2754 reg = FDI_TX_CTL(pipe);
2755 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002756 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002757 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2758 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002759 } else {
2760 temp &= ~FDI_LINK_TRAIN_NONE;
2761 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002762 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002763 I915_WRITE(reg, temp);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 if (HAS_PCH_CPT(dev)) {
2768 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2770 } else {
2771 temp &= ~FDI_LINK_TRAIN_NONE;
2772 temp |= FDI_LINK_TRAIN_NONE;
2773 }
2774 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2775
2776 /* wait one idle pattern time */
2777 POSTING_READ(reg);
2778 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002779
2780 /* IVB wants error correction enabled */
2781 if (IS_IVYBRIDGE(dev))
2782 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2783 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002784}
2785
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002786static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002787{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002788 return crtc->base.enabled && crtc->active &&
2789 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002790}
2791
Daniel Vetter01a415f2012-10-27 15:58:40 +02002792static void ivb_modeset_global_resources(struct drm_device *dev)
2793{
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 struct intel_crtc *pipe_B_crtc =
2796 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2797 struct intel_crtc *pipe_C_crtc =
2798 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2799 uint32_t temp;
2800
Daniel Vetter1e833f42013-02-19 22:31:57 +01002801 /*
2802 * When everything is off disable fdi C so that we could enable fdi B
2803 * with all lanes. Note that we don't care about enabled pipes without
2804 * an enabled pch encoder.
2805 */
2806 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2807 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002808 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2809 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2810
2811 temp = I915_READ(SOUTH_CHICKEN1);
2812 temp &= ~FDI_BC_BIFURCATION_SELECT;
2813 DRM_DEBUG_KMS("disabling fdi C rx\n");
2814 I915_WRITE(SOUTH_CHICKEN1, temp);
2815 }
2816}
2817
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002818/* The FDI link training functions for ILK/Ibexpeak. */
2819static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2820{
2821 struct drm_device *dev = crtc->dev;
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2824 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002825 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002826
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03002827 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002828 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002829
Adam Jacksone1a44742010-06-25 15:32:14 -04002830 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2831 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002832 reg = FDI_RX_IMR(pipe);
2833 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002834 temp &= ~FDI_RX_SYMBOL_LOCK;
2835 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002836 I915_WRITE(reg, temp);
2837 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002838 udelay(150);
2839
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002840 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002843 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2844 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002847 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002848
Chris Wilson5eddb702010-09-11 13:48:45 +01002849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002853 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2854
2855 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002856 udelay(150);
2857
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002858 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002859 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2860 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2861 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002862
Chris Wilson5eddb702010-09-11 13:48:45 +01002863 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002864 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002865 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002866 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2867
2868 if ((temp & FDI_RX_BIT_LOCK)) {
2869 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002870 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002871 break;
2872 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002873 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002874 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002875 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002876
2877 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002878 reg = FDI_TX_CTL(pipe);
2879 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002880 temp &= ~FDI_LINK_TRAIN_NONE;
2881 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002882 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002883
Chris Wilson5eddb702010-09-11 13:48:45 +01002884 reg = FDI_RX_CTL(pipe);
2885 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002886 temp &= ~FDI_LINK_TRAIN_NONE;
2887 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002888 I915_WRITE(reg, temp);
2889
2890 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002891 udelay(150);
2892
Chris Wilson5eddb702010-09-11 13:48:45 +01002893 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002894 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002895 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002896 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2897
2898 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002899 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002900 DRM_DEBUG_KMS("FDI train 2 done.\n");
2901 break;
2902 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002903 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002904 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002905 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002906
2907 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002908
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002909}
2910
Akshay Joshi0206e352011-08-16 15:34:10 -04002911static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002912 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2913 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2914 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2915 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2916};
2917
2918/* The FDI link training functions for SNB/Cougarpoint. */
2919static void gen6_fdi_link_train(struct drm_crtc *crtc)
2920{
2921 struct drm_device *dev = crtc->dev;
2922 struct drm_i915_private *dev_priv = dev->dev_private;
2923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2924 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002925 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002926
Adam Jacksone1a44742010-06-25 15:32:14 -04002927 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2928 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002929 reg = FDI_RX_IMR(pipe);
2930 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002931 temp &= ~FDI_RX_SYMBOL_LOCK;
2932 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002933 I915_WRITE(reg, temp);
2934
2935 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002936 udelay(150);
2937
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002938 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002939 reg = FDI_TX_CTL(pipe);
2940 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002941 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2942 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002943 temp &= ~FDI_LINK_TRAIN_NONE;
2944 temp |= FDI_LINK_TRAIN_PATTERN_1;
2945 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2946 /* SNB-B */
2947 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002948 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002949
Daniel Vetterd74cf322012-10-26 10:58:13 +02002950 I915_WRITE(FDI_RX_MISC(pipe),
2951 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2952
Chris Wilson5eddb702010-09-11 13:48:45 +01002953 reg = FDI_RX_CTL(pipe);
2954 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002955 if (HAS_PCH_CPT(dev)) {
2956 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2957 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2958 } else {
2959 temp &= ~FDI_LINK_TRAIN_NONE;
2960 temp |= FDI_LINK_TRAIN_PATTERN_1;
2961 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002962 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2963
2964 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002965 udelay(150);
2966
Akshay Joshi0206e352011-08-16 15:34:10 -04002967 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002968 reg = FDI_TX_CTL(pipe);
2969 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002970 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2971 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002972 I915_WRITE(reg, temp);
2973
2974 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002975 udelay(500);
2976
Sean Paulfa37d392012-03-02 12:53:39 -05002977 for (retry = 0; retry < 5; retry++) {
2978 reg = FDI_RX_IIR(pipe);
2979 temp = I915_READ(reg);
2980 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2981 if (temp & FDI_RX_BIT_LOCK) {
2982 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2983 DRM_DEBUG_KMS("FDI train 1 done.\n");
2984 break;
2985 }
2986 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002987 }
Sean Paulfa37d392012-03-02 12:53:39 -05002988 if (retry < 5)
2989 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002990 }
2991 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002992 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002993
2994 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002995 reg = FDI_TX_CTL(pipe);
2996 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002997 temp &= ~FDI_LINK_TRAIN_NONE;
2998 temp |= FDI_LINK_TRAIN_PATTERN_2;
2999 if (IS_GEN6(dev)) {
3000 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3001 /* SNB-B */
3002 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3003 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003004 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003005
Chris Wilson5eddb702010-09-11 13:48:45 +01003006 reg = FDI_RX_CTL(pipe);
3007 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003008 if (HAS_PCH_CPT(dev)) {
3009 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3010 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3011 } else {
3012 temp &= ~FDI_LINK_TRAIN_NONE;
3013 temp |= FDI_LINK_TRAIN_PATTERN_2;
3014 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003015 I915_WRITE(reg, temp);
3016
3017 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003018 udelay(150);
3019
Akshay Joshi0206e352011-08-16 15:34:10 -04003020 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003021 reg = FDI_TX_CTL(pipe);
3022 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003023 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3024 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003025 I915_WRITE(reg, temp);
3026
3027 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003028 udelay(500);
3029
Sean Paulfa37d392012-03-02 12:53:39 -05003030 for (retry = 0; retry < 5; retry++) {
3031 reg = FDI_RX_IIR(pipe);
3032 temp = I915_READ(reg);
3033 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3034 if (temp & FDI_RX_SYMBOL_LOCK) {
3035 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3036 DRM_DEBUG_KMS("FDI train 2 done.\n");
3037 break;
3038 }
3039 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003040 }
Sean Paulfa37d392012-03-02 12:53:39 -05003041 if (retry < 5)
3042 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003043 }
3044 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003045 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003046
3047 DRM_DEBUG_KMS("FDI train done.\n");
3048}
3049
Jesse Barnes357555c2011-04-28 15:09:55 -07003050/* Manual link training for Ivy Bridge A0 parts */
3051static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3052{
3053 struct drm_device *dev = crtc->dev;
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3056 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003057 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003058
3059 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3060 for train result */
3061 reg = FDI_RX_IMR(pipe);
3062 temp = I915_READ(reg);
3063 temp &= ~FDI_RX_SYMBOL_LOCK;
3064 temp &= ~FDI_RX_BIT_LOCK;
3065 I915_WRITE(reg, temp);
3066
3067 POSTING_READ(reg);
3068 udelay(150);
3069
Daniel Vetter01a415f2012-10-27 15:58:40 +02003070 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3071 I915_READ(FDI_RX_IIR(pipe)));
3072
Jesse Barnes139ccd32013-08-19 11:04:55 -07003073 /* Try each vswing and preemphasis setting twice before moving on */
3074 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3075 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003076 reg = FDI_TX_CTL(pipe);
3077 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003078 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3079 temp &= ~FDI_TX_ENABLE;
3080 I915_WRITE(reg, temp);
3081
3082 reg = FDI_RX_CTL(pipe);
3083 temp = I915_READ(reg);
3084 temp &= ~FDI_LINK_TRAIN_AUTO;
3085 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3086 temp &= ~FDI_RX_ENABLE;
3087 I915_WRITE(reg, temp);
3088
3089 /* enable CPU FDI TX and PCH FDI RX */
3090 reg = FDI_TX_CTL(pipe);
3091 temp = I915_READ(reg);
3092 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3093 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3094 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003095 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003096 temp |= snb_b_fdi_train_param[j/2];
3097 temp |= FDI_COMPOSITE_SYNC;
3098 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3099
3100 I915_WRITE(FDI_RX_MISC(pipe),
3101 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3102
3103 reg = FDI_RX_CTL(pipe);
3104 temp = I915_READ(reg);
3105 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3106 temp |= FDI_COMPOSITE_SYNC;
3107 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3108
3109 POSTING_READ(reg);
3110 udelay(1); /* should be 0.5us */
3111
3112 for (i = 0; i < 4; i++) {
3113 reg = FDI_RX_IIR(pipe);
3114 temp = I915_READ(reg);
3115 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3116
3117 if (temp & FDI_RX_BIT_LOCK ||
3118 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3119 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3120 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3121 i);
3122 break;
3123 }
3124 udelay(1); /* should be 0.5us */
3125 }
3126 if (i == 4) {
3127 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3128 continue;
3129 }
3130
3131 /* Train 2 */
3132 reg = FDI_TX_CTL(pipe);
3133 temp = I915_READ(reg);
3134 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3135 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3136 I915_WRITE(reg, temp);
3137
3138 reg = FDI_RX_CTL(pipe);
3139 temp = I915_READ(reg);
3140 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3141 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003142 I915_WRITE(reg, temp);
3143
3144 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003145 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003146
Jesse Barnes139ccd32013-08-19 11:04:55 -07003147 for (i = 0; i < 4; i++) {
3148 reg = FDI_RX_IIR(pipe);
3149 temp = I915_READ(reg);
3150 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003151
Jesse Barnes139ccd32013-08-19 11:04:55 -07003152 if (temp & FDI_RX_SYMBOL_LOCK ||
3153 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3154 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3155 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3156 i);
3157 goto train_done;
3158 }
3159 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003160 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003161 if (i == 4)
3162 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003163 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003164
Jesse Barnes139ccd32013-08-19 11:04:55 -07003165train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003166 DRM_DEBUG_KMS("FDI train done.\n");
3167}
3168
Daniel Vetter88cefb62012-08-12 19:27:14 +02003169static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003170{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003171 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003172 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003173 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003174 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003175
Jesse Barnesc64e3112010-09-10 11:27:03 -07003176
Jesse Barnes0e23b992010-09-10 11:10:00 -07003177 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003178 reg = FDI_RX_CTL(pipe);
3179 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003180 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3181 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003182 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003183 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3184
3185 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003186 udelay(200);
3187
3188 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003189 temp = I915_READ(reg);
3190 I915_WRITE(reg, temp | FDI_PCDCLK);
3191
3192 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003193 udelay(200);
3194
Paulo Zanoni20749732012-11-23 15:30:38 -02003195 /* Enable CPU FDI TX PLL, always on for Ironlake */
3196 reg = FDI_TX_CTL(pipe);
3197 temp = I915_READ(reg);
3198 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3199 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003200
Paulo Zanoni20749732012-11-23 15:30:38 -02003201 POSTING_READ(reg);
3202 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003203 }
3204}
3205
Daniel Vetter88cefb62012-08-12 19:27:14 +02003206static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3207{
3208 struct drm_device *dev = intel_crtc->base.dev;
3209 struct drm_i915_private *dev_priv = dev->dev_private;
3210 int pipe = intel_crtc->pipe;
3211 u32 reg, temp;
3212
3213 /* Switch from PCDclk to Rawclk */
3214 reg = FDI_RX_CTL(pipe);
3215 temp = I915_READ(reg);
3216 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3217
3218 /* Disable CPU FDI TX PLL */
3219 reg = FDI_TX_CTL(pipe);
3220 temp = I915_READ(reg);
3221 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3222
3223 POSTING_READ(reg);
3224 udelay(100);
3225
3226 reg = FDI_RX_CTL(pipe);
3227 temp = I915_READ(reg);
3228 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3229
3230 /* Wait for the clocks to turn off. */
3231 POSTING_READ(reg);
3232 udelay(100);
3233}
3234
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003235static void ironlake_fdi_disable(struct drm_crtc *crtc)
3236{
3237 struct drm_device *dev = crtc->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3240 int pipe = intel_crtc->pipe;
3241 u32 reg, temp;
3242
3243 /* disable CPU FDI tx and PCH FDI rx */
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
3246 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3247 POSTING_READ(reg);
3248
3249 reg = FDI_RX_CTL(pipe);
3250 temp = I915_READ(reg);
3251 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003252 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003253 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3254
3255 POSTING_READ(reg);
3256 udelay(100);
3257
3258 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003259 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003260 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003261
3262 /* still set train pattern 1 */
3263 reg = FDI_TX_CTL(pipe);
3264 temp = I915_READ(reg);
3265 temp &= ~FDI_LINK_TRAIN_NONE;
3266 temp |= FDI_LINK_TRAIN_PATTERN_1;
3267 I915_WRITE(reg, temp);
3268
3269 reg = FDI_RX_CTL(pipe);
3270 temp = I915_READ(reg);
3271 if (HAS_PCH_CPT(dev)) {
3272 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3273 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3274 } else {
3275 temp &= ~FDI_LINK_TRAIN_NONE;
3276 temp |= FDI_LINK_TRAIN_PATTERN_1;
3277 }
3278 /* BPC in FDI rx is consistent with that in PIPECONF */
3279 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003280 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003281 I915_WRITE(reg, temp);
3282
3283 POSTING_READ(reg);
3284 udelay(100);
3285}
3286
Chris Wilson5dce5b932014-01-20 10:17:36 +00003287bool intel_has_pending_fb_unpin(struct drm_device *dev)
3288{
3289 struct intel_crtc *crtc;
3290
3291 /* Note that we don't need to be called with mode_config.lock here
3292 * as our list of CRTC objects is static for the lifetime of the
3293 * device and so cannot disappear as we iterate. Similarly, we can
3294 * happily treat the predicates as racy, atomic checks as userspace
3295 * cannot claim and pin a new fb without at least acquring the
3296 * struct_mutex and so serialising with us.
3297 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003298 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003299 if (atomic_read(&crtc->unpin_work_count) == 0)
3300 continue;
3301
3302 if (crtc->unpin_work)
3303 intel_wait_for_vblank(dev, crtc->pipe);
3304
3305 return true;
3306 }
3307
3308 return false;
3309}
3310
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003311void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003312{
Chris Wilson0f911282012-04-17 10:05:38 +01003313 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003314 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003315
Matt Roperf4510a22014-04-01 15:22:40 -07003316 if (crtc->primary->fb == NULL)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003317 return;
3318
Daniel Vetter2c10d572012-12-20 21:24:07 +01003319 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3320
Daniel Vettereed6d672014-05-19 16:09:35 +02003321 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3322 !intel_crtc_has_pending_flip(crtc),
3323 60*HZ) == 0);
Chris Wilson5bb61642012-09-27 21:25:58 +01003324
Chris Wilson0f911282012-04-17 10:05:38 +01003325 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07003326 intel_finish_fb(crtc->primary->fb);
Chris Wilson0f911282012-04-17 10:05:38 +01003327 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003328}
3329
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003330/* Program iCLKIP clock to the desired frequency */
3331static void lpt_program_iclkip(struct drm_crtc *crtc)
3332{
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003335 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003336 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3337 u32 temp;
3338
Daniel Vetter09153002012-12-12 14:06:44 +01003339 mutex_lock(&dev_priv->dpio_lock);
3340
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003341 /* It is necessary to ungate the pixclk gate prior to programming
3342 * the divisors, and gate it back when it is done.
3343 */
3344 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3345
3346 /* Disable SSCCTL */
3347 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003348 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3349 SBI_SSCCTL_DISABLE,
3350 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003351
3352 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003353 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003354 auxdiv = 1;
3355 divsel = 0x41;
3356 phaseinc = 0x20;
3357 } else {
3358 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003359 * but the adjusted_mode->crtc_clock in in KHz. To get the
3360 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003361 * convert the virtual clock precision to KHz here for higher
3362 * precision.
3363 */
3364 u32 iclk_virtual_root_freq = 172800 * 1000;
3365 u32 iclk_pi_range = 64;
3366 u32 desired_divisor, msb_divisor_value, pi_value;
3367
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003368 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003369 msb_divisor_value = desired_divisor / iclk_pi_range;
3370 pi_value = desired_divisor % iclk_pi_range;
3371
3372 auxdiv = 0;
3373 divsel = msb_divisor_value - 2;
3374 phaseinc = pi_value;
3375 }
3376
3377 /* This should not happen with any sane values */
3378 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3379 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3380 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3381 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3382
3383 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003384 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003385 auxdiv,
3386 divsel,
3387 phasedir,
3388 phaseinc);
3389
3390 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003391 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003392 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3393 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3394 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3395 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3396 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3397 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003398 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003399
3400 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003401 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003402 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3403 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003404 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003405
3406 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003407 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003408 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003409 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003410
3411 /* Wait for initialization time */
3412 udelay(24);
3413
3414 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003415
3416 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003417}
3418
Daniel Vetter275f01b22013-05-03 11:49:47 +02003419static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3420 enum pipe pch_transcoder)
3421{
3422 struct drm_device *dev = crtc->base.dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3425
3426 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3427 I915_READ(HTOTAL(cpu_transcoder)));
3428 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3429 I915_READ(HBLANK(cpu_transcoder)));
3430 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3431 I915_READ(HSYNC(cpu_transcoder)));
3432
3433 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3434 I915_READ(VTOTAL(cpu_transcoder)));
3435 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3436 I915_READ(VBLANK(cpu_transcoder)));
3437 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3438 I915_READ(VSYNC(cpu_transcoder)));
3439 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3440 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3441}
3442
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003443static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3444{
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446 uint32_t temp;
3447
3448 temp = I915_READ(SOUTH_CHICKEN1);
3449 if (temp & FDI_BC_BIFURCATION_SELECT)
3450 return;
3451
3452 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3453 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3454
3455 temp |= FDI_BC_BIFURCATION_SELECT;
3456 DRM_DEBUG_KMS("enabling fdi C rx\n");
3457 I915_WRITE(SOUTH_CHICKEN1, temp);
3458 POSTING_READ(SOUTH_CHICKEN1);
3459}
3460
3461static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3462{
3463 struct drm_device *dev = intel_crtc->base.dev;
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465
3466 switch (intel_crtc->pipe) {
3467 case PIPE_A:
3468 break;
3469 case PIPE_B:
3470 if (intel_crtc->config.fdi_lanes > 2)
3471 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3472 else
3473 cpt_enable_fdi_bc_bifurcation(dev);
3474
3475 break;
3476 case PIPE_C:
3477 cpt_enable_fdi_bc_bifurcation(dev);
3478
3479 break;
3480 default:
3481 BUG();
3482 }
3483}
3484
Jesse Barnesf67a5592011-01-05 10:31:48 -08003485/*
3486 * Enable PCH resources required for PCH ports:
3487 * - PCH PLLs
3488 * - FDI training & RX/TX
3489 * - update transcoder timings
3490 * - DP transcoding bits
3491 * - transcoder
3492 */
3493static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003494{
3495 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003499 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003500
Daniel Vetterab9412b2013-05-03 11:49:46 +02003501 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003502
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003503 if (IS_IVYBRIDGE(dev))
3504 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3505
Daniel Vettercd986ab2012-10-26 10:58:12 +02003506 /* Write the TU size bits before fdi link training, so that error
3507 * detection works. */
3508 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3509 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3510
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003511 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003512 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003513
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003514 /* We need to program the right clock selection before writing the pixel
3515 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003516 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003517 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003518
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003519 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003520 temp |= TRANS_DPLL_ENABLE(pipe);
3521 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003522 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003523 temp |= sel;
3524 else
3525 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003526 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003527 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003528
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003529 /* XXX: pch pll's can be enabled any time before we enable the PCH
3530 * transcoder, and we actually should do this to not upset any PCH
3531 * transcoder that already use the clock when we share it.
3532 *
3533 * Note that enable_shared_dpll tries to do the right thing, but
3534 * get_shared_dpll unconditionally resets the pll - we need that to have
3535 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003536 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003537
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003538 /* set transcoder timing, panel must allow it */
3539 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003540 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003541
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003542 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003543
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003544 /* For PCH DP, enable TRANS_DP_CTL */
3545 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003546 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3547 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003548 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003549 reg = TRANS_DP_CTL(pipe);
3550 temp = I915_READ(reg);
3551 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003552 TRANS_DP_SYNC_MASK |
3553 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003554 temp |= (TRANS_DP_OUTPUT_ENABLE |
3555 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003556 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003557
3558 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003559 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003560 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003561 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003562
3563 switch (intel_trans_dp_port_sel(crtc)) {
3564 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003565 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003566 break;
3567 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003568 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003569 break;
3570 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003571 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003572 break;
3573 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003574 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003575 }
3576
Chris Wilson5eddb702010-09-11 13:48:45 +01003577 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003578 }
3579
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003580 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003581}
3582
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003583static void lpt_pch_enable(struct drm_crtc *crtc)
3584{
3585 struct drm_device *dev = crtc->dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003588 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003589
Daniel Vetterab9412b2013-05-03 11:49:46 +02003590 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003591
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003592 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003593
Paulo Zanoni0540e482012-10-31 18:12:40 -02003594 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003595 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003596
Paulo Zanoni937bb612012-10-31 18:12:47 -02003597 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003598}
3599
Daniel Vetter716c2e52014-06-25 22:02:02 +03003600void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003601{
Daniel Vettere2b78262013-06-07 23:10:03 +02003602 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003603
3604 if (pll == NULL)
3605 return;
3606
3607 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003608 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003609 return;
3610 }
3611
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003612 if (--pll->refcount == 0) {
3613 WARN_ON(pll->on);
3614 WARN_ON(pll->active);
3615 }
3616
Daniel Vettera43f6e02013-06-07 23:10:32 +02003617 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003618}
3619
Daniel Vetter716c2e52014-06-25 22:02:02 +03003620struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003621{
Daniel Vettere2b78262013-06-07 23:10:03 +02003622 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3623 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3624 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003625
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003626 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003627 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3628 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003629 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003630 }
3631
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003632 if (HAS_PCH_IBX(dev_priv->dev)) {
3633 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003634 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003635 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003636
Daniel Vetter46edb022013-06-05 13:34:12 +02003637 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3638 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003639
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003640 WARN_ON(pll->refcount);
3641
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003642 goto found;
3643 }
3644
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003645 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3646 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003647
3648 /* Only want to check enabled timings first */
3649 if (pll->refcount == 0)
3650 continue;
3651
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003652 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3653 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003654 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003655 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003656 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003657
3658 goto found;
3659 }
3660 }
3661
3662 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003663 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3664 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003665 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003666 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3667 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003668 goto found;
3669 }
3670 }
3671
3672 return NULL;
3673
3674found:
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003675 if (pll->refcount == 0)
3676 pll->hw_state = crtc->config.dpll_hw_state;
3677
Daniel Vettera43f6e02013-06-07 23:10:32 +02003678 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003679 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3680 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003681
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003682 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003683
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003684 return pll;
3685}
3686
Daniel Vettera1520312013-05-03 11:49:50 +02003687static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003688{
3689 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003690 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003691 u32 temp;
3692
3693 temp = I915_READ(dslreg);
3694 udelay(500);
3695 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003696 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003697 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003698 }
3699}
3700
Jesse Barnesb074cec2013-04-25 12:55:02 -07003701static void ironlake_pfit_enable(struct intel_crtc *crtc)
3702{
3703 struct drm_device *dev = crtc->base.dev;
3704 struct drm_i915_private *dev_priv = dev->dev_private;
3705 int pipe = crtc->pipe;
3706
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003707 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003708 /* Force use of hard-coded filter coefficients
3709 * as some pre-programmed values are broken,
3710 * e.g. x201.
3711 */
3712 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3713 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3714 PF_PIPE_SEL_IVB(pipe));
3715 else
3716 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3717 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3718 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003719 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003720}
3721
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003722static void intel_enable_planes(struct drm_crtc *crtc)
3723{
3724 struct drm_device *dev = crtc->dev;
3725 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003726 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003727 struct intel_plane *intel_plane;
3728
Matt Roperaf2b6532014-04-01 15:22:32 -07003729 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3730 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003731 if (intel_plane->pipe == pipe)
3732 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003733 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003734}
3735
3736static void intel_disable_planes(struct drm_crtc *crtc)
3737{
3738 struct drm_device *dev = crtc->dev;
3739 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003740 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003741 struct intel_plane *intel_plane;
3742
Matt Roperaf2b6532014-04-01 15:22:32 -07003743 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3744 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003745 if (intel_plane->pipe == pipe)
3746 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003747 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003748}
3749
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003750void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003751{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003752 struct drm_device *dev = crtc->base.dev;
3753 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03003754
3755 if (!crtc->config.ips_enabled)
3756 return;
3757
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003758 /* We can only enable IPS after we enable a plane and wait for a vblank */
3759 intel_wait_for_vblank(dev, crtc->pipe);
3760
Paulo Zanonid77e4532013-09-24 13:52:55 -03003761 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003762 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003763 mutex_lock(&dev_priv->rps.hw_lock);
3764 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3765 mutex_unlock(&dev_priv->rps.hw_lock);
3766 /* Quoting Art Runyan: "its not safe to expect any particular
3767 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08003768 * mailbox." Moreover, the mailbox may return a bogus state,
3769 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003770 */
3771 } else {
3772 I915_WRITE(IPS_CTL, IPS_ENABLE);
3773 /* The bit only becomes 1 in the next vblank, so this wait here
3774 * is essentially intel_wait_for_vblank. If we don't have this
3775 * and don't wait for vblanks until the end of crtc_enable, then
3776 * the HW state readout code will complain that the expected
3777 * IPS_CTL value is not the one we read. */
3778 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3779 DRM_ERROR("Timed out waiting for IPS enable\n");
3780 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003781}
3782
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003783void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003784{
3785 struct drm_device *dev = crtc->base.dev;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787
3788 if (!crtc->config.ips_enabled)
3789 return;
3790
3791 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003792 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003793 mutex_lock(&dev_priv->rps.hw_lock);
3794 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3795 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003796 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3797 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3798 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08003799 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003800 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08003801 POSTING_READ(IPS_CTL);
3802 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003803
3804 /* We need to wait for a vblank before we can disable the plane. */
3805 intel_wait_for_vblank(dev, crtc->pipe);
3806}
3807
3808/** Loads the palette/gamma unit for the CRTC with the prepared values */
3809static void intel_crtc_load_lut(struct drm_crtc *crtc)
3810{
3811 struct drm_device *dev = crtc->dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814 enum pipe pipe = intel_crtc->pipe;
3815 int palreg = PALETTE(pipe);
3816 int i;
3817 bool reenable_ips = false;
3818
3819 /* The clocks have to be on to load the palette. */
3820 if (!crtc->enabled || !intel_crtc->active)
3821 return;
3822
3823 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3824 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3825 assert_dsi_pll_enabled(dev_priv);
3826 else
3827 assert_pll_enabled(dev_priv, pipe);
3828 }
3829
3830 /* use legacy palette for Ironlake */
Sonika Jindal7a1db492014-07-22 11:18:27 +05303831 if (!HAS_GMCH_DISPLAY(dev))
Paulo Zanonid77e4532013-09-24 13:52:55 -03003832 palreg = LGC_PALETTE(pipe);
3833
3834 /* Workaround : Do not read or write the pipe palette/gamma data while
3835 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3836 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02003837 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03003838 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3839 GAMMA_MODE_MODE_SPLIT)) {
3840 hsw_disable_ips(intel_crtc);
3841 reenable_ips = true;
3842 }
3843
3844 for (i = 0; i < 256; i++) {
3845 I915_WRITE(palreg + 4 * i,
3846 (intel_crtc->lut_r[i] << 16) |
3847 (intel_crtc->lut_g[i] << 8) |
3848 intel_crtc->lut_b[i]);
3849 }
3850
3851 if (reenable_ips)
3852 hsw_enable_ips(intel_crtc);
3853}
3854
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003855static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3856{
3857 if (!enable && intel_crtc->overlay) {
3858 struct drm_device *dev = intel_crtc->base.dev;
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861 mutex_lock(&dev->struct_mutex);
3862 dev_priv->mm.interruptible = false;
3863 (void) intel_overlay_switch_off(intel_crtc->overlay);
3864 dev_priv->mm.interruptible = true;
3865 mutex_unlock(&dev->struct_mutex);
3866 }
3867
3868 /* Let userspace switch the overlay on again. In most cases userspace
3869 * has to recompute where to put it anyway.
3870 */
3871}
3872
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003873static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003874{
3875 struct drm_device *dev = crtc->dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3878 int pipe = intel_crtc->pipe;
3879 int plane = intel_crtc->plane;
3880
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003881 drm_vblank_on(dev, pipe);
3882
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003883 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3884 intel_enable_planes(crtc);
3885 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003886 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003887
3888 hsw_enable_ips(intel_crtc);
3889
3890 mutex_lock(&dev->struct_mutex);
3891 intel_update_fbc(dev);
3892 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf99d7062014-06-19 16:01:59 +02003893
3894 /*
3895 * FIXME: Once we grow proper nuclear flip support out of this we need
3896 * to compute the mask of flip planes precisely. For the time being
3897 * consider this a flip from a NULL plane.
3898 */
3899 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003900}
3901
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003902static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003903{
3904 struct drm_device *dev = crtc->dev;
3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3907 int pipe = intel_crtc->pipe;
3908 int plane = intel_crtc->plane;
3909
3910 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003911
3912 if (dev_priv->fbc.plane == plane)
3913 intel_disable_fbc(dev);
3914
3915 hsw_disable_ips(intel_crtc);
3916
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003917 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003918 intel_crtc_update_cursor(crtc, false);
3919 intel_disable_planes(crtc);
3920 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003921
Daniel Vetterf99d7062014-06-19 16:01:59 +02003922 /*
3923 * FIXME: Once we grow proper nuclear flip support out of this we need
3924 * to compute the mask of flip planes precisely. For the time being
3925 * consider this a flip to a NULL plane.
3926 */
3927 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3928
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003929 drm_vblank_off(dev, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003930}
3931
Jesse Barnesf67a5592011-01-05 10:31:48 -08003932static void ironlake_crtc_enable(struct drm_crtc *crtc)
3933{
3934 struct drm_device *dev = crtc->dev;
3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003937 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003938 int pipe = intel_crtc->pipe;
Daniel Vetter29407aa2014-04-24 23:55:08 +02003939 enum plane plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003940
Daniel Vetter08a48462012-07-02 11:43:47 +02003941 WARN_ON(!crtc->enabled);
3942
Jesse Barnesf67a5592011-01-05 10:31:48 -08003943 if (intel_crtc->active)
3944 return;
3945
Daniel Vetterb14b1052014-04-24 23:55:13 +02003946 if (intel_crtc->config.has_pch_encoder)
3947 intel_prepare_shared_dpll(intel_crtc);
3948
Daniel Vetter29407aa2014-04-24 23:55:08 +02003949 if (intel_crtc->config.has_dp_encoder)
3950 intel_dp_set_m_n(intel_crtc);
3951
3952 intel_set_pipe_timings(intel_crtc);
3953
3954 if (intel_crtc->config.has_pch_encoder) {
3955 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07003956 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02003957 }
3958
3959 ironlake_set_pipeconf(crtc);
3960
3961 /* Set up the display plane register */
3962 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3963 POSTING_READ(DSPCNTR(plane));
3964
3965 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3966 crtc->x, crtc->y);
3967
Jesse Barnesf67a5592011-01-05 10:31:48 -08003968 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003969
3970 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3971 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3972
Daniel Vetterf6736a12013-06-05 13:34:30 +02003973 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003974 if (encoder->pre_enable)
3975 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003976
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003977 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003978 /* Note: FDI PLL enabling _must_ be done before we enable the
3979 * cpu pipes, hence this is separate from all the other fdi/pch
3980 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003981 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003982 } else {
3983 assert_fdi_tx_disabled(dev_priv, pipe);
3984 assert_fdi_rx_disabled(dev_priv, pipe);
3985 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003986
Jesse Barnesb074cec2013-04-25 12:55:02 -07003987 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003988
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003989 /*
3990 * On ILK+ LUT must be loaded before the pipe is running but with
3991 * clocks enabled
3992 */
3993 intel_crtc_load_lut(crtc);
3994
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03003995 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02003996 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003997
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003998 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08003999 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004000
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004001 for_each_encoder_on_crtc(dev, crtc, encoder)
4002 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004003
4004 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004005 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004006
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004007 intel_crtc_enable_planes(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004008}
4009
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004010/* IPS only exists on ULT machines and is tied to pipe A. */
4011static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4012{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004013 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004014}
4015
Paulo Zanonie4916942013-09-20 16:21:19 -03004016/*
4017 * This implements the workaround described in the "notes" section of the mode
4018 * set sequence documentation. When going from no pipes or single pipe to
4019 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4020 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4021 */
4022static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4023{
4024 struct drm_device *dev = crtc->base.dev;
4025 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4026
4027 /* We want to get the other_active_crtc only if there's only 1 other
4028 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004029 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004030 if (!crtc_it->active || crtc_it == crtc)
4031 continue;
4032
4033 if (other_active_crtc)
4034 return;
4035
4036 other_active_crtc = crtc_it;
4037 }
4038 if (!other_active_crtc)
4039 return;
4040
4041 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4042 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4043}
4044
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004045static void haswell_crtc_enable(struct drm_crtc *crtc)
4046{
4047 struct drm_device *dev = crtc->dev;
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4050 struct intel_encoder *encoder;
4051 int pipe = intel_crtc->pipe;
Daniel Vetter229fca92014-04-24 23:55:09 +02004052 enum plane plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004053
4054 WARN_ON(!crtc->enabled);
4055
4056 if (intel_crtc->active)
4057 return;
4058
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004059 if (intel_crtc_to_shared_dpll(intel_crtc))
4060 intel_enable_shared_dpll(intel_crtc);
4061
Daniel Vetter229fca92014-04-24 23:55:09 +02004062 if (intel_crtc->config.has_dp_encoder)
4063 intel_dp_set_m_n(intel_crtc);
4064
4065 intel_set_pipe_timings(intel_crtc);
4066
4067 if (intel_crtc->config.has_pch_encoder) {
4068 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004069 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02004070 }
4071
4072 haswell_set_pipeconf(crtc);
4073
4074 intel_set_pipe_csc(crtc);
4075
4076 /* Set up the display plane register */
4077 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4078 POSTING_READ(DSPCNTR(plane));
4079
4080 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4081 crtc->x, crtc->y);
4082
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004083 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004084
4085 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004086 for_each_encoder_on_crtc(dev, crtc, encoder)
4087 if (encoder->pre_enable)
4088 encoder->pre_enable(encoder);
4089
Imre Deak4fe94672014-06-25 22:01:49 +03004090 if (intel_crtc->config.has_pch_encoder) {
4091 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4092 dev_priv->display.fdi_link_train(crtc);
4093 }
4094
Paulo Zanoni1f544382012-10-24 11:32:00 -02004095 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004096
Jesse Barnesb074cec2013-04-25 12:55:02 -07004097 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004098
4099 /*
4100 * On ILK+ LUT must be loaded before the pipe is running but with
4101 * clocks enabled
4102 */
4103 intel_crtc_load_lut(crtc);
4104
Paulo Zanoni1f544382012-10-24 11:32:00 -02004105 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004106 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004107
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004108 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004109 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004110
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004111 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004112 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004113
Dave Airlie0e32b392014-05-02 14:02:48 +10004114 if (intel_crtc->config.dp_encoder_is_mst)
4115 intel_ddi_set_vc_payload_alloc(crtc, true);
4116
Jani Nikula8807e552013-08-30 19:40:32 +03004117 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004118 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004119 intel_opregion_notify_encoder(encoder, true);
4120 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004121
Paulo Zanonie4916942013-09-20 16:21:19 -03004122 /* If we change the relative order between pipe/planes enabling, we need
4123 * to change the workaround. */
4124 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004125 intel_crtc_enable_planes(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004126}
4127
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004128static void ironlake_pfit_disable(struct intel_crtc *crtc)
4129{
4130 struct drm_device *dev = crtc->base.dev;
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 int pipe = crtc->pipe;
4133
4134 /* To avoid upsetting the power well on haswell only disable the pfit if
4135 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004136 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004137 I915_WRITE(PF_CTL(pipe), 0);
4138 I915_WRITE(PF_WIN_POS(pipe), 0);
4139 I915_WRITE(PF_WIN_SZ(pipe), 0);
4140 }
4141}
4142
Jesse Barnes6be4a602010-09-10 10:26:01 -07004143static void ironlake_crtc_disable(struct drm_crtc *crtc)
4144{
4145 struct drm_device *dev = crtc->dev;
4146 struct drm_i915_private *dev_priv = dev->dev_private;
4147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004148 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004149 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004150 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004151
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004152 if (!intel_crtc->active)
4153 return;
4154
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004155 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004156
Daniel Vetterea9d7582012-07-10 10:42:52 +02004157 for_each_encoder_on_crtc(dev, crtc, encoder)
4158 encoder->disable(encoder);
4159
Daniel Vetterd925c592013-06-05 13:34:04 +02004160 if (intel_crtc->config.has_pch_encoder)
4161 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4162
Jesse Barnesb24e7172011-01-04 15:09:30 -08004163 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004164
Dave Airlie0e32b392014-05-02 14:02:48 +10004165 if (intel_crtc->config.dp_encoder_is_mst)
4166 intel_ddi_set_vc_payload_alloc(crtc, false);
4167
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004168 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004169
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004170 for_each_encoder_on_crtc(dev, crtc, encoder)
4171 if (encoder->post_disable)
4172 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004173
Daniel Vetterd925c592013-06-05 13:34:04 +02004174 if (intel_crtc->config.has_pch_encoder) {
4175 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004176
Daniel Vetterd925c592013-06-05 13:34:04 +02004177 ironlake_disable_pch_transcoder(dev_priv, pipe);
4178 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004179
Daniel Vetterd925c592013-06-05 13:34:04 +02004180 if (HAS_PCH_CPT(dev)) {
4181 /* disable TRANS_DP_CTL */
4182 reg = TRANS_DP_CTL(pipe);
4183 temp = I915_READ(reg);
4184 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4185 TRANS_DP_PORT_SEL_MASK);
4186 temp |= TRANS_DP_PORT_SEL_NONE;
4187 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004188
Daniel Vetterd925c592013-06-05 13:34:04 +02004189 /* disable DPLL_SEL */
4190 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004191 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004192 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004193 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004194
4195 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004196 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004197
4198 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004199 }
4200
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004201 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004202 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004203
4204 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004205 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004206 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004207}
4208
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004209static void haswell_crtc_disable(struct drm_crtc *crtc)
4210{
4211 struct drm_device *dev = crtc->dev;
4212 struct drm_i915_private *dev_priv = dev->dev_private;
4213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4214 struct intel_encoder *encoder;
4215 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004216 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004217
4218 if (!intel_crtc->active)
4219 return;
4220
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004221 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004222
Jani Nikula8807e552013-08-30 19:40:32 +03004223 for_each_encoder_on_crtc(dev, crtc, encoder) {
4224 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004225 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004226 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004227
Paulo Zanoni86642812013-04-12 17:57:57 -03004228 if (intel_crtc->config.has_pch_encoder)
4229 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004230 intel_disable_pipe(dev_priv, pipe);
4231
Paulo Zanoniad80a812012-10-24 16:06:19 -02004232 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004233
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004234 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004235
Paulo Zanoni1f544382012-10-24 11:32:00 -02004236 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004237
Daniel Vetter88adfff2013-03-28 10:42:01 +01004238 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004239 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03004240 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004241 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004242 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004243
Imre Deak97b040a2014-06-25 22:01:50 +03004244 for_each_encoder_on_crtc(dev, crtc, encoder)
4245 if (encoder->post_disable)
4246 encoder->post_disable(encoder);
4247
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004248 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004249 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004250
4251 mutex_lock(&dev->struct_mutex);
4252 intel_update_fbc(dev);
4253 mutex_unlock(&dev->struct_mutex);
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004254
4255 if (intel_crtc_to_shared_dpll(intel_crtc))
4256 intel_disable_shared_dpll(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004257}
4258
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004259static void ironlake_crtc_off(struct drm_crtc *crtc)
4260{
4261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004262 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004263}
4264
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004265
Jesse Barnes2dd24552013-04-25 12:55:01 -07004266static void i9xx_pfit_enable(struct intel_crtc *crtc)
4267{
4268 struct drm_device *dev = crtc->base.dev;
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4270 struct intel_crtc_config *pipe_config = &crtc->config;
4271
Daniel Vetter328d8e82013-05-08 10:36:31 +02004272 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004273 return;
4274
Daniel Vetterc0b03412013-05-28 12:05:54 +02004275 /*
4276 * The panel fitter should only be adjusted whilst the pipe is disabled,
4277 * according to register description and PRM.
4278 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004279 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4280 assert_pipe_disabled(dev_priv, crtc->pipe);
4281
Jesse Barnesb074cec2013-04-25 12:55:02 -07004282 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4283 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004284
4285 /* Border color in case we don't scale up to the full screen. Black by
4286 * default, change to something else for debugging. */
4287 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004288}
4289
Dave Airlied05410f2014-06-05 13:22:59 +10004290static enum intel_display_power_domain port_to_power_domain(enum port port)
4291{
4292 switch (port) {
4293 case PORT_A:
4294 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4295 case PORT_B:
4296 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4297 case PORT_C:
4298 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4299 case PORT_D:
4300 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4301 default:
4302 WARN_ON_ONCE(1);
4303 return POWER_DOMAIN_PORT_OTHER;
4304 }
4305}
4306
Imre Deak77d22dc2014-03-05 16:20:52 +02004307#define for_each_power_domain(domain, mask) \
4308 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4309 if ((1 << (domain)) & (mask))
4310
Imre Deak319be8a2014-03-04 19:22:57 +02004311enum intel_display_power_domain
4312intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004313{
Imre Deak319be8a2014-03-04 19:22:57 +02004314 struct drm_device *dev = intel_encoder->base.dev;
4315 struct intel_digital_port *intel_dig_port;
4316
4317 switch (intel_encoder->type) {
4318 case INTEL_OUTPUT_UNKNOWN:
4319 /* Only DDI platforms should ever use this output type */
4320 WARN_ON_ONCE(!HAS_DDI(dev));
4321 case INTEL_OUTPUT_DISPLAYPORT:
4322 case INTEL_OUTPUT_HDMI:
4323 case INTEL_OUTPUT_EDP:
4324 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10004325 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10004326 case INTEL_OUTPUT_DP_MST:
4327 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4328 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02004329 case INTEL_OUTPUT_ANALOG:
4330 return POWER_DOMAIN_PORT_CRT;
4331 case INTEL_OUTPUT_DSI:
4332 return POWER_DOMAIN_PORT_DSI;
4333 default:
4334 return POWER_DOMAIN_PORT_OTHER;
4335 }
4336}
4337
4338static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4339{
4340 struct drm_device *dev = crtc->dev;
4341 struct intel_encoder *intel_encoder;
4342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4343 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02004344 unsigned long mask;
4345 enum transcoder transcoder;
4346
4347 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4348
4349 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4350 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Daniel Vetterfabf6e52014-05-29 14:10:22 +02004351 if (intel_crtc->config.pch_pfit.enabled ||
4352 intel_crtc->config.pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02004353 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4354
Imre Deak319be8a2014-03-04 19:22:57 +02004355 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4356 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4357
Imre Deak77d22dc2014-03-05 16:20:52 +02004358 return mask;
4359}
4360
4361void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4362 bool enable)
4363{
4364 if (dev_priv->power_domains.init_power_on == enable)
4365 return;
4366
4367 if (enable)
4368 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4369 else
4370 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4371
4372 dev_priv->power_domains.init_power_on = enable;
4373}
4374
4375static void modeset_update_crtc_power_domains(struct drm_device *dev)
4376{
4377 struct drm_i915_private *dev_priv = dev->dev_private;
4378 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4379 struct intel_crtc *crtc;
4380
4381 /*
4382 * First get all needed power domains, then put all unneeded, to avoid
4383 * any unnecessary toggling of the power wells.
4384 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004385 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004386 enum intel_display_power_domain domain;
4387
4388 if (!crtc->base.enabled)
4389 continue;
4390
Imre Deak319be8a2014-03-04 19:22:57 +02004391 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004392
4393 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4394 intel_display_power_get(dev_priv, domain);
4395 }
4396
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004397 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004398 enum intel_display_power_domain domain;
4399
4400 for_each_power_domain(domain, crtc->enabled_power_domains)
4401 intel_display_power_put(dev_priv, domain);
4402
4403 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4404 }
4405
4406 intel_display_set_init_power(dev_priv, false);
4407}
4408
Ville Syrjälädfcab172014-06-13 13:37:47 +03004409/* returns HPLL frequency in kHz */
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004410static int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004411{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004412 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004413
Jesse Barnes586f49d2013-11-04 16:06:59 -08004414 /* Obtain SKU information */
4415 mutex_lock(&dev_priv->dpio_lock);
4416 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4417 CCK_FUSE_HPLL_FREQ_MASK;
4418 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004419
Ville Syrjälädfcab172014-06-13 13:37:47 +03004420 return vco_freq[hpll_freq] * 1000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004421}
4422
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004423static void vlv_update_cdclk(struct drm_device *dev)
4424{
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426
4427 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4428 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4429 dev_priv->vlv_cdclk_freq);
4430
4431 /*
4432 * Program the gmbus_freq based on the cdclk frequency.
4433 * BSpec erroneously claims we should aim for 4MHz, but
4434 * in fact 1MHz is the correct frequency.
4435 */
4436 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4437}
4438
Jesse Barnes30a970c2013-11-04 13:48:12 -08004439/* Adjust CDclk dividers to allow high res or save power if possible */
4440static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4441{
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 u32 val, cmd;
4444
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03004445 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02004446
Ville Syrjälädfcab172014-06-13 13:37:47 +03004447 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08004448 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03004449 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004450 cmd = 1;
4451 else
4452 cmd = 0;
4453
4454 mutex_lock(&dev_priv->rps.hw_lock);
4455 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4456 val &= ~DSPFREQGUAR_MASK;
4457 val |= (cmd << DSPFREQGUAR_SHIFT);
4458 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4459 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4460 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4461 50)) {
4462 DRM_ERROR("timed out waiting for CDclk change\n");
4463 }
4464 mutex_unlock(&dev_priv->rps.hw_lock);
4465
Ville Syrjälädfcab172014-06-13 13:37:47 +03004466 if (cdclk == 400000) {
Jesse Barnes30a970c2013-11-04 13:48:12 -08004467 u32 divider, vco;
4468
4469 vco = valleyview_get_vco(dev_priv);
Ville Syrjälädfcab172014-06-13 13:37:47 +03004470 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004471
4472 mutex_lock(&dev_priv->dpio_lock);
4473 /* adjust cdclk divider */
4474 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Ville Syrjälä9cf33db2014-06-13 13:37:48 +03004475 val &= ~DISPLAY_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004476 val |= divider;
4477 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03004478
4479 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4480 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4481 50))
4482 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08004483 mutex_unlock(&dev_priv->dpio_lock);
4484 }
4485
4486 mutex_lock(&dev_priv->dpio_lock);
4487 /* adjust self-refresh exit latency value */
4488 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4489 val &= ~0x7f;
4490
4491 /*
4492 * For high bandwidth configs, we set a higher latency in the bunit
4493 * so that the core display fetch happens in time to avoid underruns.
4494 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03004495 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004496 val |= 4500 / 250; /* 4.5 usec */
4497 else
4498 val |= 3000 / 250; /* 3.0 usec */
4499 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4500 mutex_unlock(&dev_priv->dpio_lock);
4501
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004502 vlv_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004503}
4504
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004505static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4506{
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 u32 val, cmd;
4509
4510 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4511
4512 switch (cdclk) {
4513 case 400000:
4514 cmd = 3;
4515 break;
4516 case 333333:
4517 case 320000:
4518 cmd = 2;
4519 break;
4520 case 266667:
4521 cmd = 1;
4522 break;
4523 case 200000:
4524 cmd = 0;
4525 break;
4526 default:
4527 WARN_ON(1);
4528 return;
4529 }
4530
4531 mutex_lock(&dev_priv->rps.hw_lock);
4532 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4533 val &= ~DSPFREQGUAR_MASK_CHV;
4534 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4535 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4536 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4537 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4538 50)) {
4539 DRM_ERROR("timed out waiting for CDclk change\n");
4540 }
4541 mutex_unlock(&dev_priv->rps.hw_lock);
4542
4543 vlv_update_cdclk(dev);
4544}
4545
Jesse Barnes30a970c2013-11-04 13:48:12 -08004546static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4547 int max_pixclk)
4548{
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004549 int vco = valleyview_get_vco(dev_priv);
4550 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4551
Ville Syrjäläd49a3402014-06-28 02:03:58 +03004552 /* FIXME: Punit isn't quite ready yet */
4553 if (IS_CHERRYVIEW(dev_priv->dev))
4554 return 400000;
4555
Jesse Barnes30a970c2013-11-04 13:48:12 -08004556 /*
4557 * Really only a few cases to deal with, as only 4 CDclks are supported:
4558 * 200MHz
4559 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004560 * 320/333MHz (depends on HPLL freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004561 * 400MHz
4562 * So we check to see whether we're above 90% of the lower bin and
4563 * adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004564 *
4565 * We seem to get an unstable or solid color picture at 200MHz.
4566 * Not sure what's wrong. For now use 200MHz only when all pipes
4567 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08004568 */
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004569 if (max_pixclk > freq_320*9/10)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004570 return 400000;
4571 else if (max_pixclk > 266667*9/10)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004572 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004573 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004574 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004575 else
4576 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004577}
4578
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004579/* compute the max pixel clock for new configuration */
4580static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004581{
4582 struct drm_device *dev = dev_priv->dev;
4583 struct intel_crtc *intel_crtc;
4584 int max_pixclk = 0;
4585
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004586 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004587 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004588 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004589 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004590 }
4591
4592 return max_pixclk;
4593}
4594
4595static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004596 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004597{
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004600 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004601
Imre Deakd60c4472014-03-27 17:45:10 +02004602 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4603 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004604 return;
4605
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004606 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004607 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004608 if (intel_crtc->base.enabled)
4609 *prepare_pipes |= (1 << intel_crtc->pipe);
4610}
4611
4612static void valleyview_modeset_global_resources(struct drm_device *dev)
4613{
4614 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004615 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004616 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4617
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004618 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4619 if (IS_CHERRYVIEW(dev))
4620 cherryview_set_cdclk(dev, req_cdclk);
4621 else
4622 valleyview_set_cdclk(dev, req_cdclk);
4623 }
4624
Imre Deak77961eb2014-03-05 16:20:56 +02004625 modeset_update_crtc_power_domains(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004626}
4627
Jesse Barnes89b667f2013-04-18 14:51:36 -07004628static void valleyview_crtc_enable(struct drm_crtc *crtc)
4629{
4630 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004631 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4633 struct intel_encoder *encoder;
4634 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004635 int plane = intel_crtc->plane;
Jani Nikula23538ef2013-08-27 15:12:22 +03004636 bool is_dsi;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004637 u32 dspcntr;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004638
4639 WARN_ON(!crtc->enabled);
4640
4641 if (intel_crtc->active)
4642 return;
4643
Shobhit Kumar8525a232014-06-25 12:20:39 +05304644 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4645
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004646 if (!is_dsi) {
4647 if (IS_CHERRYVIEW(dev))
4648 chv_prepare_pll(intel_crtc);
4649 else
4650 vlv_prepare_pll(intel_crtc);
4651 }
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02004652
Daniel Vetter5b18e572014-04-24 23:55:06 +02004653 /* Set up the display plane register */
4654 dspcntr = DISPPLANE_GAMMA_ENABLE;
4655
4656 if (intel_crtc->config.has_dp_encoder)
4657 intel_dp_set_m_n(intel_crtc);
4658
4659 intel_set_pipe_timings(intel_crtc);
4660
4661 /* pipesrc and dspsize control the size that is scaled from,
4662 * which should always be the user's requested size.
4663 */
4664 I915_WRITE(DSPSIZE(plane),
4665 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4666 (intel_crtc->config.pipe_src_w - 1));
4667 I915_WRITE(DSPPOS(plane), 0);
4668
4669 i9xx_set_pipeconf(intel_crtc);
4670
4671 I915_WRITE(DSPCNTR(plane), dspcntr);
4672 POSTING_READ(DSPCNTR(plane));
4673
4674 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4675 crtc->x, crtc->y);
4676
Jesse Barnes89b667f2013-04-18 14:51:36 -07004677 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004678
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004679 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4680
Jesse Barnes89b667f2013-04-18 14:51:36 -07004681 for_each_encoder_on_crtc(dev, crtc, encoder)
4682 if (encoder->pre_pll_enable)
4683 encoder->pre_pll_enable(encoder);
4684
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004685 if (!is_dsi) {
4686 if (IS_CHERRYVIEW(dev))
4687 chv_enable_pll(intel_crtc);
4688 else
4689 vlv_enable_pll(intel_crtc);
4690 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004691
4692 for_each_encoder_on_crtc(dev, crtc, encoder)
4693 if (encoder->pre_enable)
4694 encoder->pre_enable(encoder);
4695
Jesse Barnes2dd24552013-04-25 12:55:01 -07004696 i9xx_pfit_enable(intel_crtc);
4697
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004698 intel_crtc_load_lut(crtc);
4699
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004700 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004701 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004702
Jani Nikula50049452013-07-30 12:20:32 +03004703 for_each_encoder_on_crtc(dev, crtc, encoder)
4704 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004705
4706 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004707
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004708 /* Underruns don't raise interrupts, so check manually. */
4709 i9xx_check_fifo_underruns(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004710}
4711
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004712static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4713{
4714 struct drm_device *dev = crtc->base.dev;
4715 struct drm_i915_private *dev_priv = dev->dev_private;
4716
4717 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4718 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4719}
4720
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004721static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004722{
4723 struct drm_device *dev = crtc->dev;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004724 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08004725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004726 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004727 int pipe = intel_crtc->pipe;
Daniel Vetter5b18e572014-04-24 23:55:06 +02004728 int plane = intel_crtc->plane;
4729 u32 dspcntr;
Jesse Barnes79e53942008-11-07 14:24:08 -08004730
Daniel Vetter08a48462012-07-02 11:43:47 +02004731 WARN_ON(!crtc->enabled);
4732
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004733 if (intel_crtc->active)
4734 return;
4735
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004736 i9xx_set_pll_dividers(intel_crtc);
4737
Daniel Vetter5b18e572014-04-24 23:55:06 +02004738 /* Set up the display plane register */
4739 dspcntr = DISPPLANE_GAMMA_ENABLE;
4740
4741 if (pipe == 0)
4742 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4743 else
4744 dspcntr |= DISPPLANE_SEL_PIPE_B;
4745
4746 if (intel_crtc->config.has_dp_encoder)
4747 intel_dp_set_m_n(intel_crtc);
4748
4749 intel_set_pipe_timings(intel_crtc);
4750
4751 /* pipesrc and dspsize control the size that is scaled from,
4752 * which should always be the user's requested size.
4753 */
4754 I915_WRITE(DSPSIZE(plane),
4755 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4756 (intel_crtc->config.pipe_src_w - 1));
4757 I915_WRITE(DSPPOS(plane), 0);
4758
4759 i9xx_set_pipeconf(intel_crtc);
4760
4761 I915_WRITE(DSPCNTR(plane), dspcntr);
4762 POSTING_READ(DSPCNTR(plane));
4763
4764 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4765 crtc->x, crtc->y);
4766
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004767 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004768
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004769 if (!IS_GEN2(dev))
4770 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4771
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004772 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004773 if (encoder->pre_enable)
4774 encoder->pre_enable(encoder);
4775
Daniel Vetterf6736a12013-06-05 13:34:30 +02004776 i9xx_enable_pll(intel_crtc);
4777
Jesse Barnes2dd24552013-04-25 12:55:01 -07004778 i9xx_pfit_enable(intel_crtc);
4779
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004780 intel_crtc_load_lut(crtc);
4781
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004782 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004783 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004784
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004785 for_each_encoder_on_crtc(dev, crtc, encoder)
4786 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004787
4788 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004789
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004790 /*
4791 * Gen2 reports pipe underruns whenever all planes are disabled.
4792 * So don't enable underrun reporting before at least some planes
4793 * are enabled.
4794 * FIXME: Need to fix the logic to work when we turn off all planes
4795 * but leave the pipe running.
4796 */
4797 if (IS_GEN2(dev))
4798 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4799
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004800 /* Underruns don't raise interrupts, so check manually. */
4801 i9xx_check_fifo_underruns(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004802}
4803
Daniel Vetter87476d62013-04-11 16:29:06 +02004804static void i9xx_pfit_disable(struct intel_crtc *crtc)
4805{
4806 struct drm_device *dev = crtc->base.dev;
4807 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004808
4809 if (!crtc->config.gmch_pfit.control)
4810 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004811
4812 assert_pipe_disabled(dev_priv, crtc->pipe);
4813
Daniel Vetter328d8e82013-05-08 10:36:31 +02004814 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4815 I915_READ(PFIT_CONTROL));
4816 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004817}
4818
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004819static void i9xx_crtc_disable(struct drm_crtc *crtc)
4820{
4821 struct drm_device *dev = crtc->dev;
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004824 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004825 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004826
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004827 if (!intel_crtc->active)
4828 return;
4829
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004830 /*
4831 * Gen2 reports pipe underruns whenever all planes are disabled.
4832 * So diasble underrun reporting before all the planes get disabled.
4833 * FIXME: Need to fix the logic to work when we turn off all planes
4834 * but leave the pipe running.
4835 */
4836 if (IS_GEN2(dev))
4837 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4838
Imre Deak564ed192014-06-13 14:54:21 +03004839 /*
4840 * Vblank time updates from the shadow to live plane control register
4841 * are blocked if the memory self-refresh mode is active at that
4842 * moment. So to make sure the plane gets truly disabled, disable
4843 * first the self-refresh mode. The self-refresh enable bit in turn
4844 * will be checked/applied by the HW only at the next frame start
4845 * event which is after the vblank start event, so we need to have a
4846 * wait-for-vblank between disabling the plane and the pipe.
4847 */
4848 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004849 intel_crtc_disable_planes(crtc);
4850
Daniel Vetterea9d7582012-07-10 10:42:52 +02004851 for_each_encoder_on_crtc(dev, crtc, encoder)
4852 encoder->disable(encoder);
4853
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004854 /*
4855 * On gen2 planes are double buffered but the pipe isn't, so we must
4856 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03004857 * We also need to wait on all gmch platforms because of the
4858 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004859 */
Imre Deak564ed192014-06-13 14:54:21 +03004860 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004861
Jesse Barnesb24e7172011-01-04 15:09:30 -08004862 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004863
Daniel Vetter87476d62013-04-11 16:29:06 +02004864 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004865
Jesse Barnes89b667f2013-04-18 14:51:36 -07004866 for_each_encoder_on_crtc(dev, crtc, encoder)
4867 if (encoder->post_disable)
4868 encoder->post_disable(encoder);
4869
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03004870 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4871 if (IS_CHERRYVIEW(dev))
4872 chv_disable_pll(dev_priv, pipe);
4873 else if (IS_VALLEYVIEW(dev))
4874 vlv_disable_pll(dev_priv, pipe);
4875 else
4876 i9xx_disable_pll(dev_priv, pipe);
4877 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004878
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004879 if (!IS_GEN2(dev))
4880 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4881
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004882 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004883 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004884
Daniel Vetterefa96242014-04-24 23:55:02 +02004885 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004886 intel_update_fbc(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02004887 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004888}
4889
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004890static void i9xx_crtc_off(struct drm_crtc *crtc)
4891{
4892}
4893
Daniel Vetter976f8a22012-07-08 22:34:21 +02004894static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4895 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004896{
4897 struct drm_device *dev = crtc->dev;
4898 struct drm_i915_master_private *master_priv;
4899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4900 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004901
4902 if (!dev->primary->master)
4903 return;
4904
4905 master_priv = dev->primary->master->driver_priv;
4906 if (!master_priv->sarea_priv)
4907 return;
4908
Jesse Barnes79e53942008-11-07 14:24:08 -08004909 switch (pipe) {
4910 case 0:
4911 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4912 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4913 break;
4914 case 1:
4915 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4916 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4917 break;
4918 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004919 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004920 break;
4921 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004922}
4923
Borun Fub04c5bd2014-07-12 10:02:27 +05304924/* Master function to enable/disable CRTC and corresponding power wells */
4925void intel_crtc_control(struct drm_crtc *crtc, bool enable)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004926{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004927 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004928 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004930 enum intel_display_power_domain domain;
4931 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004932
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004933 if (enable) {
4934 if (!intel_crtc->active) {
Daniel Vettere1e9fb82014-06-25 22:02:04 +03004935 domains = get_crtc_power_domains(crtc);
4936 for_each_power_domain(domain, domains)
4937 intel_display_power_get(dev_priv, domain);
4938 intel_crtc->enabled_power_domains = domains;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004939
4940 dev_priv->display.crtc_enable(crtc);
4941 }
4942 } else {
4943 if (intel_crtc->active) {
4944 dev_priv->display.crtc_disable(crtc);
4945
Daniel Vettere1e9fb82014-06-25 22:02:04 +03004946 domains = intel_crtc->enabled_power_domains;
4947 for_each_power_domain(domain, domains)
4948 intel_display_power_put(dev_priv, domain);
4949 intel_crtc->enabled_power_domains = 0;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004950 }
4951 }
Borun Fub04c5bd2014-07-12 10:02:27 +05304952}
4953
4954/**
4955 * Sets the power management mode of the pipe and plane.
4956 */
4957void intel_crtc_update_dpms(struct drm_crtc *crtc)
4958{
4959 struct drm_device *dev = crtc->dev;
4960 struct intel_encoder *intel_encoder;
4961 bool enable = false;
4962
4963 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4964 enable |= intel_encoder->connectors_active;
4965
4966 intel_crtc_control(crtc, enable);
Daniel Vetter976f8a22012-07-08 22:34:21 +02004967
4968 intel_crtc_update_sarea(crtc, enable);
4969}
4970
Daniel Vetter976f8a22012-07-08 22:34:21 +02004971static void intel_crtc_disable(struct drm_crtc *crtc)
4972{
4973 struct drm_device *dev = crtc->dev;
4974 struct drm_connector *connector;
4975 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper2ff8fde2014-07-08 07:50:07 -07004976 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
Daniel Vettera071fa02014-06-18 23:28:09 +02004977 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004978
4979 /* crtc should still be enabled when we disable it. */
4980 WARN_ON(!crtc->enabled);
4981
4982 dev_priv->display.crtc_disable(crtc);
4983 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004984 dev_priv->display.off(crtc);
4985
Matt Roperf4510a22014-04-01 15:22:40 -07004986 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01004987 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02004988 intel_unpin_fb_obj(old_obj);
4989 i915_gem_track_fb(old_obj, NULL,
4990 INTEL_FRONTBUFFER_PRIMARY(pipe));
Chris Wilsoncdd59982010-09-08 16:30:16 +01004991 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004992 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004993 }
4994
4995 /* Update computed state. */
4996 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4997 if (!connector->encoder || !connector->encoder->crtc)
4998 continue;
4999
5000 if (connector->encoder->crtc != crtc)
5001 continue;
5002
5003 connector->dpms = DRM_MODE_DPMS_OFF;
5004 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01005005 }
5006}
5007
Chris Wilsonea5b2132010-08-04 13:50:23 +01005008void intel_encoder_destroy(struct drm_encoder *encoder)
5009{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005010 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01005011
Chris Wilsonea5b2132010-08-04 13:50:23 +01005012 drm_encoder_cleanup(encoder);
5013 kfree(intel_encoder);
5014}
5015
Damien Lespiau92373292013-08-08 22:28:57 +01005016/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005017 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5018 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01005019static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005020{
5021 if (mode == DRM_MODE_DPMS_ON) {
5022 encoder->connectors_active = true;
5023
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005024 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005025 } else {
5026 encoder->connectors_active = false;
5027
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005028 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005029 }
5030}
5031
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005032/* Cross check the actual hw state with our own modeset state tracking (and it's
5033 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02005034static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005035{
5036 if (connector->get_hw_state(connector)) {
5037 struct intel_encoder *encoder = connector->encoder;
5038 struct drm_crtc *crtc;
5039 bool encoder_enabled;
5040 enum pipe pipe;
5041
5042 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5043 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03005044 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005045
Dave Airlie0e32b392014-05-02 14:02:48 +10005046 /* there is no real hw state for MST connectors */
5047 if (connector->mst_port)
5048 return;
5049
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005050 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5051 "wrong connector dpms state\n");
5052 WARN(connector->base.encoder != &encoder->base,
5053 "active connector not linked to encoder\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005054
Dave Airlie36cd7442014-05-02 13:44:18 +10005055 if (encoder) {
5056 WARN(!encoder->connectors_active,
5057 "encoder->connectors_active not set\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005058
Dave Airlie36cd7442014-05-02 13:44:18 +10005059 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5060 WARN(!encoder_enabled, "encoder not enabled\n");
5061 if (WARN_ON(!encoder->base.crtc))
5062 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005063
Dave Airlie36cd7442014-05-02 13:44:18 +10005064 crtc = encoder->base.crtc;
5065
5066 WARN(!crtc->enabled, "crtc not enabled\n");
5067 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5068 WARN(pipe != to_intel_crtc(crtc)->pipe,
5069 "encoder active on the wrong pipe\n");
5070 }
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005071 }
5072}
5073
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005074/* Even simpler default implementation, if there's really no special case to
5075 * consider. */
5076void intel_connector_dpms(struct drm_connector *connector, int mode)
5077{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005078 /* All the simple cases only support two dpms states. */
5079 if (mode != DRM_MODE_DPMS_ON)
5080 mode = DRM_MODE_DPMS_OFF;
5081
5082 if (mode == connector->dpms)
5083 return;
5084
5085 connector->dpms = mode;
5086
5087 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01005088 if (connector->encoder)
5089 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005090
Daniel Vetterb9805142012-08-31 17:37:33 +02005091 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005092}
5093
Daniel Vetterf0947c32012-07-02 13:10:34 +02005094/* Simple connector->get_hw_state implementation for encoders that support only
5095 * one connector and no cloning and hence the encoder state determines the state
5096 * of the connector. */
5097bool intel_connector_get_hw_state(struct intel_connector *connector)
5098{
Daniel Vetter24929352012-07-02 20:28:59 +02005099 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02005100 struct intel_encoder *encoder = connector->encoder;
5101
5102 return encoder->get_hw_state(encoder, &pipe);
5103}
5104
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005105static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5106 struct intel_crtc_config *pipe_config)
5107{
5108 struct drm_i915_private *dev_priv = dev->dev_private;
5109 struct intel_crtc *pipe_B_crtc =
5110 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5111
5112 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5113 pipe_name(pipe), pipe_config->fdi_lanes);
5114 if (pipe_config->fdi_lanes > 4) {
5115 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5116 pipe_name(pipe), pipe_config->fdi_lanes);
5117 return false;
5118 }
5119
Paulo Zanonibafb6552013-11-02 21:07:44 -07005120 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005121 if (pipe_config->fdi_lanes > 2) {
5122 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5123 pipe_config->fdi_lanes);
5124 return false;
5125 } else {
5126 return true;
5127 }
5128 }
5129
5130 if (INTEL_INFO(dev)->num_pipes == 2)
5131 return true;
5132
5133 /* Ivybridge 3 pipe is really complicated */
5134 switch (pipe) {
5135 case PIPE_A:
5136 return true;
5137 case PIPE_B:
5138 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5139 pipe_config->fdi_lanes > 2) {
5140 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5141 pipe_name(pipe), pipe_config->fdi_lanes);
5142 return false;
5143 }
5144 return true;
5145 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005146 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005147 pipe_B_crtc->config.fdi_lanes <= 2) {
5148 if (pipe_config->fdi_lanes > 2) {
5149 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5150 pipe_name(pipe), pipe_config->fdi_lanes);
5151 return false;
5152 }
5153 } else {
5154 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5155 return false;
5156 }
5157 return true;
5158 default:
5159 BUG();
5160 }
5161}
5162
Daniel Vettere29c22c2013-02-21 00:00:16 +01005163#define RETRY 1
5164static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5165 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005166{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005167 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005168 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005169 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005170 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005171
Daniel Vettere29c22c2013-02-21 00:00:16 +01005172retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005173 /* FDI is a binary signal running at ~2.7GHz, encoding
5174 * each output octet as 10 bits. The actual frequency
5175 * is stored as a divider into a 100MHz clock, and the
5176 * mode pixel clock is stored in units of 1KHz.
5177 * Hence the bw of each lane in terms of the mode signal
5178 * is:
5179 */
5180 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5181
Damien Lespiau241bfc32013-09-25 16:45:37 +01005182 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005183
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005184 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005185 pipe_config->pipe_bpp);
5186
5187 pipe_config->fdi_lanes = lane;
5188
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005189 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005190 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005191
Daniel Vettere29c22c2013-02-21 00:00:16 +01005192 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5193 intel_crtc->pipe, pipe_config);
5194 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5195 pipe_config->pipe_bpp -= 2*3;
5196 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5197 pipe_config->pipe_bpp);
5198 needs_recompute = true;
5199 pipe_config->bw_constrained = true;
5200
5201 goto retry;
5202 }
5203
5204 if (needs_recompute)
5205 return RETRY;
5206
5207 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005208}
5209
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005210static void hsw_compute_ips_config(struct intel_crtc *crtc,
5211 struct intel_crtc_config *pipe_config)
5212{
Jani Nikulad330a952014-01-21 11:24:25 +02005213 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005214 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005215 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005216}
5217
Daniel Vettera43f6e02013-06-07 23:10:32 +02005218static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005219 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005220{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005221 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005222 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005223
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005224 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005225 if (INTEL_INFO(dev)->gen < 4) {
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227 int clock_limit =
5228 dev_priv->display.get_display_clock_speed(dev);
5229
5230 /*
5231 * Enable pixel doubling when the dot clock
5232 * is > 90% of the (display) core speed.
5233 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005234 * GDG double wide on either pipe,
5235 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005236 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005237 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005238 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005239 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005240 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005241 }
5242
Damien Lespiau241bfc32013-09-25 16:45:37 +01005243 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005244 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005245 }
Chris Wilson89749352010-09-12 18:25:19 +01005246
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005247 /*
5248 * Pipe horizontal size must be even in:
5249 * - DVO ganged mode
5250 * - LVDS dual channel mode
5251 * - Double wide pipe
5252 */
5253 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5254 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5255 pipe_config->pipe_src_w &= ~1;
5256
Damien Lespiau8693a822013-05-03 18:48:11 +01005257 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5258 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005259 */
5260 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5261 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005262 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005263
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005264 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005265 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005266 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005267 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5268 * for lvds. */
5269 pipe_config->pipe_bpp = 8*3;
5270 }
5271
Damien Lespiauf5adf942013-06-24 18:29:34 +01005272 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005273 hsw_compute_ips_config(crtc, pipe_config);
5274
Daniel Vetter12030432014-06-25 22:02:00 +03005275 /*
5276 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5277 * old clock survives for now.
5278 */
5279 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005280 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005281
Daniel Vetter877d48d2013-04-19 11:24:43 +02005282 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005283 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005284
Daniel Vettere29c22c2013-02-21 00:00:16 +01005285 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005286}
5287
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005288static int valleyview_get_display_clock_speed(struct drm_device *dev)
5289{
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005290 struct drm_i915_private *dev_priv = dev->dev_private;
5291 int vco = valleyview_get_vco(dev_priv);
5292 u32 val;
5293 int divider;
5294
Ville Syrjäläd49a3402014-06-28 02:03:58 +03005295 /* FIXME: Punit isn't quite ready yet */
5296 if (IS_CHERRYVIEW(dev))
5297 return 400000;
5298
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005299 mutex_lock(&dev_priv->dpio_lock);
5300 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5301 mutex_unlock(&dev_priv->dpio_lock);
5302
5303 divider = val & DISPLAY_FREQUENCY_VALUES;
5304
Ville Syrjälä7d007f42014-06-13 13:37:53 +03005305 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5306 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5307 "cdclk change in progress\n");
5308
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005309 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005310}
5311
Jesse Barnese70236a2009-09-21 10:42:27 -07005312static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005313{
Jesse Barnese70236a2009-09-21 10:42:27 -07005314 return 400000;
5315}
Jesse Barnes79e53942008-11-07 14:24:08 -08005316
Jesse Barnese70236a2009-09-21 10:42:27 -07005317static int i915_get_display_clock_speed(struct drm_device *dev)
5318{
5319 return 333000;
5320}
Jesse Barnes79e53942008-11-07 14:24:08 -08005321
Jesse Barnese70236a2009-09-21 10:42:27 -07005322static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5323{
5324 return 200000;
5325}
Jesse Barnes79e53942008-11-07 14:24:08 -08005326
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005327static int pnv_get_display_clock_speed(struct drm_device *dev)
5328{
5329 u16 gcfgc = 0;
5330
5331 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5332
5333 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5334 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5335 return 267000;
5336 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5337 return 333000;
5338 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5339 return 444000;
5340 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5341 return 200000;
5342 default:
5343 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5344 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5345 return 133000;
5346 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5347 return 167000;
5348 }
5349}
5350
Jesse Barnese70236a2009-09-21 10:42:27 -07005351static int i915gm_get_display_clock_speed(struct drm_device *dev)
5352{
5353 u16 gcfgc = 0;
5354
5355 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5356
5357 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005358 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005359 else {
5360 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5361 case GC_DISPLAY_CLOCK_333_MHZ:
5362 return 333000;
5363 default:
5364 case GC_DISPLAY_CLOCK_190_200_MHZ:
5365 return 190000;
5366 }
5367 }
5368}
Jesse Barnes79e53942008-11-07 14:24:08 -08005369
Jesse Barnese70236a2009-09-21 10:42:27 -07005370static int i865_get_display_clock_speed(struct drm_device *dev)
5371{
5372 return 266000;
5373}
5374
5375static int i855_get_display_clock_speed(struct drm_device *dev)
5376{
5377 u16 hpllcc = 0;
5378 /* Assume that the hardware is in the high speed state. This
5379 * should be the default.
5380 */
5381 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5382 case GC_CLOCK_133_200:
5383 case GC_CLOCK_100_200:
5384 return 200000;
5385 case GC_CLOCK_166_250:
5386 return 250000;
5387 case GC_CLOCK_100_133:
5388 return 133000;
5389 }
5390
5391 /* Shouldn't happen */
5392 return 0;
5393}
5394
5395static int i830_get_display_clock_speed(struct drm_device *dev)
5396{
5397 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005398}
5399
Zhenyu Wang2c072452009-06-05 15:38:42 +08005400static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005401intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005402{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005403 while (*num > DATA_LINK_M_N_MASK ||
5404 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005405 *num >>= 1;
5406 *den >>= 1;
5407 }
5408}
5409
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005410static void compute_m_n(unsigned int m, unsigned int n,
5411 uint32_t *ret_m, uint32_t *ret_n)
5412{
5413 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5414 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5415 intel_reduce_m_n_ratio(ret_m, ret_n);
5416}
5417
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005418void
5419intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5420 int pixel_clock, int link_clock,
5421 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005422{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005423 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005424
5425 compute_m_n(bits_per_pixel * pixel_clock,
5426 link_clock * nlanes * 8,
5427 &m_n->gmch_m, &m_n->gmch_n);
5428
5429 compute_m_n(pixel_clock, link_clock,
5430 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005431}
5432
Chris Wilsona7615032011-01-12 17:04:08 +00005433static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5434{
Jani Nikulad330a952014-01-21 11:24:25 +02005435 if (i915.panel_use_ssc >= 0)
5436 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005437 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005438 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005439}
5440
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005441static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5442{
5443 struct drm_device *dev = crtc->dev;
5444 struct drm_i915_private *dev_priv = dev->dev_private;
5445 int refclk;
5446
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005447 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005448 refclk = 100000;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005449 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005450 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005451 refclk = dev_priv->vbt.lvds_ssc_freq;
5452 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005453 } else if (!IS_GEN2(dev)) {
5454 refclk = 96000;
5455 } else {
5456 refclk = 48000;
5457 }
5458
5459 return refclk;
5460}
5461
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005462static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005463{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005464 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005465}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005466
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005467static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5468{
5469 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005470}
5471
Daniel Vetterf47709a2013-03-28 10:42:02 +01005472static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005473 intel_clock_t *reduced_clock)
5474{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005475 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005476 u32 fp, fp2 = 0;
5477
5478 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005479 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005480 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005481 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005482 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005483 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005484 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005485 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005486 }
5487
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005488 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005489
Daniel Vetterf47709a2013-03-28 10:42:02 +01005490 crtc->lowfreq_avail = false;
5491 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005492 reduced_clock && i915.powersave) {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005493 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005494 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005495 } else {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005496 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005497 }
5498}
5499
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005500static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5501 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005502{
5503 u32 reg_val;
5504
5505 /*
5506 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5507 * and set it to a reasonable value instead.
5508 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005509 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005510 reg_val &= 0xffffff00;
5511 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005512 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005513
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005514 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005515 reg_val &= 0x8cffffff;
5516 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005517 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005518
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005519 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005520 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005521 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005522
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005523 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005524 reg_val &= 0x00ffffff;
5525 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005526 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005527}
5528
Daniel Vetterb5518422013-05-03 11:49:48 +02005529static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5530 struct intel_link_m_n *m_n)
5531{
5532 struct drm_device *dev = crtc->base.dev;
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534 int pipe = crtc->pipe;
5535
Daniel Vettere3b95f12013-05-03 11:49:49 +02005536 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5537 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5538 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5539 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005540}
5541
5542static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07005543 struct intel_link_m_n *m_n,
5544 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02005545{
5546 struct drm_device *dev = crtc->base.dev;
5547 struct drm_i915_private *dev_priv = dev->dev_private;
5548 int pipe = crtc->pipe;
5549 enum transcoder transcoder = crtc->config.cpu_transcoder;
5550
5551 if (INTEL_INFO(dev)->gen >= 5) {
5552 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5553 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5554 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5555 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07005556 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5557 * for gen < 8) and if DRRS is supported (to make sure the
5558 * registers are not unnecessarily accessed).
5559 */
5560 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5561 crtc->config.has_drrs) {
5562 I915_WRITE(PIPE_DATA_M2(transcoder),
5563 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5564 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5565 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5566 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5567 }
Daniel Vetterb5518422013-05-03 11:49:48 +02005568 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005569 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5570 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5571 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5572 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005573 }
5574}
5575
Vandana Kannanf769cd22014-08-05 07:51:22 -07005576void intel_dp_set_m_n(struct intel_crtc *crtc)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005577{
5578 if (crtc->config.has_pch_encoder)
5579 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5580 else
Vandana Kannanf769cd22014-08-05 07:51:22 -07005581 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5582 &crtc->config.dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005583}
5584
Daniel Vetterf47709a2013-03-28 10:42:02 +01005585static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005586{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005587 u32 dpll, dpll_md;
5588
5589 /*
5590 * Enable DPIO clock input. We should never disable the reference
5591 * clock for pipe B, since VGA hotplug / manual detection depends
5592 * on it.
5593 */
5594 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5595 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5596 /* We should never disable this, set it here for state tracking */
5597 if (crtc->pipe == PIPE_B)
5598 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5599 dpll |= DPLL_VCO_ENABLE;
5600 crtc->config.dpll_hw_state.dpll = dpll;
5601
5602 dpll_md = (crtc->config.pixel_multiplier - 1)
5603 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5604 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5605}
5606
5607static void vlv_prepare_pll(struct intel_crtc *crtc)
5608{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005609 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005610 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005611 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005612 u32 mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005613 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005614 u32 coreclk, reg_val;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005615
Daniel Vetter09153002012-12-12 14:06:44 +01005616 mutex_lock(&dev_priv->dpio_lock);
5617
Daniel Vetterf47709a2013-03-28 10:42:02 +01005618 bestn = crtc->config.dpll.n;
5619 bestm1 = crtc->config.dpll.m1;
5620 bestm2 = crtc->config.dpll.m2;
5621 bestp1 = crtc->config.dpll.p1;
5622 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005623
Jesse Barnes89b667f2013-04-18 14:51:36 -07005624 /* See eDP HDMI DPIO driver vbios notes doc */
5625
5626 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005627 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005628 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005629
5630 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005631 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005632
5633 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005634 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005635 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005636 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005637
5638 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005639 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005640
5641 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005642 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5643 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5644 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005645 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005646
5647 /*
5648 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5649 * but we don't support that).
5650 * Note: don't use the DAC post divider as it seems unstable.
5651 */
5652 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005653 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005654
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005655 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005656 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005657
Jesse Barnes89b667f2013-04-18 14:51:36 -07005658 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02005659 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03005660 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07005661 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005662 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03005663 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005664 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005665 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005666 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005667
Jesse Barnes89b667f2013-04-18 14:51:36 -07005668 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5669 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5670 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005671 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005672 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005673 0x0df40000);
5674 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005675 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005676 0x0df70000);
5677 } else { /* HDMI or VGA */
5678 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005679 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005680 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005681 0x0df70000);
5682 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005683 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005684 0x0df40000);
5685 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005686
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005687 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005688 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5689 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5690 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5691 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005692 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005693
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005694 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005695 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005696}
5697
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005698static void chv_update_pll(struct intel_crtc *crtc)
5699{
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005700 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5701 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5702 DPLL_VCO_ENABLE;
5703 if (crtc->pipe != PIPE_A)
5704 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5705
5706 crtc->config.dpll_hw_state.dpll_md =
5707 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5708}
5709
5710static void chv_prepare_pll(struct intel_crtc *crtc)
5711{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005712 struct drm_device *dev = crtc->base.dev;
5713 struct drm_i915_private *dev_priv = dev->dev_private;
5714 int pipe = crtc->pipe;
5715 int dpll_reg = DPLL(crtc->pipe);
5716 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005717 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005718 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5719 int refclk;
5720
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005721 bestn = crtc->config.dpll.n;
5722 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5723 bestm1 = crtc->config.dpll.m1;
5724 bestm2 = crtc->config.dpll.m2 >> 22;
5725 bestp1 = crtc->config.dpll.p1;
5726 bestp2 = crtc->config.dpll.p2;
5727
5728 /*
5729 * Enable Refclk and SSC
5730 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005731 I915_WRITE(dpll_reg,
5732 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5733
5734 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005735
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005736 /* p1 and p2 divider */
5737 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5738 5 << DPIO_CHV_S1_DIV_SHIFT |
5739 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5740 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5741 1 << DPIO_CHV_K_DIV_SHIFT);
5742
5743 /* Feedback post-divider - m2 */
5744 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5745
5746 /* Feedback refclk divider - n and m1 */
5747 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5748 DPIO_CHV_M1_DIV_BY_2 |
5749 1 << DPIO_CHV_N_DIV_SHIFT);
5750
5751 /* M2 fraction division */
5752 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5753
5754 /* M2 fraction division enable */
5755 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5756 DPIO_CHV_FRAC_DIV_EN |
5757 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5758
5759 /* Loop filter */
5760 refclk = i9xx_get_refclk(&crtc->base, 0);
5761 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5762 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5763 if (refclk == 100000)
5764 intcoeff = 11;
5765 else if (refclk == 38400)
5766 intcoeff = 10;
5767 else
5768 intcoeff = 9;
5769 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5770 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5771
5772 /* AFC Recal */
5773 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5774 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5775 DPIO_AFC_RECAL);
5776
5777 mutex_unlock(&dev_priv->dpio_lock);
5778}
5779
Daniel Vetterf47709a2013-03-28 10:42:02 +01005780static void i9xx_update_pll(struct intel_crtc *crtc,
5781 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005782 int num_connectors)
5783{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005784 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005785 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005786 u32 dpll;
5787 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005788 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005789
Daniel Vetterf47709a2013-03-28 10:42:02 +01005790 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305791
Daniel Vetterf47709a2013-03-28 10:42:02 +01005792 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5793 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005794
5795 dpll = DPLL_VGA_MODE_DIS;
5796
Daniel Vetterf47709a2013-03-28 10:42:02 +01005797 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005798 dpll |= DPLLB_MODE_LVDS;
5799 else
5800 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005801
Daniel Vetteref1b4602013-06-01 17:17:04 +02005802 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02005803 dpll |= (crtc->config.pixel_multiplier - 1)
5804 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005805 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02005806
5807 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02005808 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005809
Daniel Vetterf47709a2013-03-28 10:42:02 +01005810 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02005811 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005812
5813 /* compute bitmask from p1 value */
5814 if (IS_PINEVIEW(dev))
5815 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5816 else {
5817 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5818 if (IS_G4X(dev) && reduced_clock)
5819 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5820 }
5821 switch (clock->p2) {
5822 case 5:
5823 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5824 break;
5825 case 7:
5826 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5827 break;
5828 case 10:
5829 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5830 break;
5831 case 14:
5832 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5833 break;
5834 }
5835 if (INTEL_INFO(dev)->gen >= 4)
5836 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5837
Daniel Vetter09ede542013-04-30 14:01:45 +02005838 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005839 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005840 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005841 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5842 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5843 else
5844 dpll |= PLL_REF_INPUT_DREFCLK;
5845
5846 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005847 crtc->config.dpll_hw_state.dpll = dpll;
5848
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005849 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005850 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5851 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005852 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005853 }
5854}
5855
Daniel Vetterf47709a2013-03-28 10:42:02 +01005856static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005857 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005858 int num_connectors)
5859{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005860 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005861 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005862 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005863 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005864
Daniel Vetterf47709a2013-03-28 10:42:02 +01005865 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305866
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005867 dpll = DPLL_VGA_MODE_DIS;
5868
Daniel Vetterf47709a2013-03-28 10:42:02 +01005869 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005870 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5871 } else {
5872 if (clock->p1 == 2)
5873 dpll |= PLL_P1_DIVIDE_BY_TWO;
5874 else
5875 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5876 if (clock->p2 == 4)
5877 dpll |= PLL_P2_DIVIDE_BY_4;
5878 }
5879
Daniel Vetter4a33e482013-07-06 12:52:05 +02005880 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5881 dpll |= DPLL_DVO_2X_MODE;
5882
Daniel Vetterf47709a2013-03-28 10:42:02 +01005883 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005884 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5885 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5886 else
5887 dpll |= PLL_REF_INPUT_DREFCLK;
5888
5889 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005890 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005891}
5892
Daniel Vetter8a654f32013-06-01 17:16:22 +02005893static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005894{
5895 struct drm_device *dev = intel_crtc->base.dev;
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005898 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005899 struct drm_display_mode *adjusted_mode =
5900 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005901 uint32_t crtc_vtotal, crtc_vblank_end;
5902 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005903
5904 /* We need to be careful not to changed the adjusted mode, for otherwise
5905 * the hw state checker will get angry at the mismatch. */
5906 crtc_vtotal = adjusted_mode->crtc_vtotal;
5907 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005908
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005909 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005910 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005911 crtc_vtotal -= 1;
5912 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005913
5914 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5915 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5916 else
5917 vsyncshift = adjusted_mode->crtc_hsync_start -
5918 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005919 if (vsyncshift < 0)
5920 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005921 }
5922
5923 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005924 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005925
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005926 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005927 (adjusted_mode->crtc_hdisplay - 1) |
5928 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005929 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005930 (adjusted_mode->crtc_hblank_start - 1) |
5931 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005932 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005933 (adjusted_mode->crtc_hsync_start - 1) |
5934 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5935
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005936 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005937 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005938 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005939 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005940 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005941 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005942 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005943 (adjusted_mode->crtc_vsync_start - 1) |
5944 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5945
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005946 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5947 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5948 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5949 * bits. */
5950 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5951 (pipe == PIPE_B || pipe == PIPE_C))
5952 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5953
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005954 /* pipesrc controls the size that is scaled from, which should
5955 * always be the user's requested size.
5956 */
5957 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005958 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5959 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005960}
5961
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005962static void intel_get_pipe_timings(struct intel_crtc *crtc,
5963 struct intel_crtc_config *pipe_config)
5964{
5965 struct drm_device *dev = crtc->base.dev;
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5968 uint32_t tmp;
5969
5970 tmp = I915_READ(HTOTAL(cpu_transcoder));
5971 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5972 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5973 tmp = I915_READ(HBLANK(cpu_transcoder));
5974 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5975 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5976 tmp = I915_READ(HSYNC(cpu_transcoder));
5977 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5978 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5979
5980 tmp = I915_READ(VTOTAL(cpu_transcoder));
5981 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5982 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5983 tmp = I915_READ(VBLANK(cpu_transcoder));
5984 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5985 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5986 tmp = I915_READ(VSYNC(cpu_transcoder));
5987 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5988 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5989
5990 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5991 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5992 pipe_config->adjusted_mode.crtc_vtotal += 1;
5993 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5994 }
5995
5996 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005997 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5998 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5999
6000 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6001 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006002}
6003
Daniel Vetterf6a83282014-02-11 15:28:57 -08006004void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6005 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03006006{
Daniel Vetterf6a83282014-02-11 15:28:57 -08006007 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6008 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6009 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6010 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006011
Daniel Vetterf6a83282014-02-11 15:28:57 -08006012 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6013 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6014 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6015 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006016
Daniel Vetterf6a83282014-02-11 15:28:57 -08006017 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006018
Daniel Vetterf6a83282014-02-11 15:28:57 -08006019 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6020 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006021}
6022
Daniel Vetter84b046f2013-02-19 18:48:54 +01006023static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6024{
6025 struct drm_device *dev = intel_crtc->base.dev;
6026 struct drm_i915_private *dev_priv = dev->dev_private;
6027 uint32_t pipeconf;
6028
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006029 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006030
Daniel Vetter67c72a12013-09-24 11:46:14 +02006031 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
6032 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
6033 pipeconf |= PIPECONF_ENABLE;
6034
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006035 if (intel_crtc->config.double_wide)
6036 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006037
Daniel Vetterff9ce462013-04-24 14:57:17 +02006038 /* only g4x and later have fancy bpc/dither controls */
6039 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02006040 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6041 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6042 pipeconf |= PIPECONF_DITHER_EN |
6043 PIPECONF_DITHER_TYPE_SP;
6044
6045 switch (intel_crtc->config.pipe_bpp) {
6046 case 18:
6047 pipeconf |= PIPECONF_6BPC;
6048 break;
6049 case 24:
6050 pipeconf |= PIPECONF_8BPC;
6051 break;
6052 case 30:
6053 pipeconf |= PIPECONF_10BPC;
6054 break;
6055 default:
6056 /* Case prevented by intel_choose_pipe_bpp_dither. */
6057 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01006058 }
6059 }
6060
6061 if (HAS_PIPE_CXSR(dev)) {
6062 if (intel_crtc->lowfreq_avail) {
6063 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6064 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6065 } else {
6066 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01006067 }
6068 }
6069
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006070 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6071 if (INTEL_INFO(dev)->gen < 4 ||
6072 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6073 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6074 else
6075 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6076 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01006077 pipeconf |= PIPECONF_PROGRESSIVE;
6078
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006079 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6080 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03006081
Daniel Vetter84b046f2013-02-19 18:48:54 +01006082 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6083 POSTING_READ(PIPECONF(intel_crtc->pipe));
6084}
6085
Eric Anholtf564048e2011-03-30 13:01:02 -07006086static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07006087 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006088 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006089{
6090 struct drm_device *dev = crtc->dev;
6091 struct drm_i915_private *dev_priv = dev->dev_private;
6092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Eric Anholtc751ce42010-03-25 11:48:48 -07006093 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07006094 intel_clock_t clock, reduced_clock;
Daniel Vettera16af7212013-04-30 14:01:44 +02006095 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006096 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01006097 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08006098 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08006099
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02006100 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01006101 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006102 case INTEL_OUTPUT_LVDS:
6103 is_lvds = true;
6104 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006105 case INTEL_OUTPUT_DSI:
6106 is_dsi = true;
6107 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006108 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006109
Eric Anholtc751ce42010-03-25 11:48:48 -07006110 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08006111 }
6112
Jani Nikulaf2335332013-09-13 11:03:09 +03006113 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02006114 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006115
Jani Nikulaf2335332013-09-13 11:03:09 +03006116 if (!intel_crtc->config.clock_set) {
6117 refclk = i9xx_get_refclk(crtc, num_connectors);
6118
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006119 /*
6120 * Returns a set of divisors for the desired target clock with
6121 * the given refclk, or FALSE. The returned values represent
6122 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6123 * 2) / p1 / p2.
6124 */
6125 limit = intel_limit(crtc, refclk);
6126 ok = dev_priv->display.find_dpll(limit, crtc,
6127 intel_crtc->config.port_clock,
6128 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03006129 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006130 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6131 return -EINVAL;
6132 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006133
Jani Nikulaf2335332013-09-13 11:03:09 +03006134 if (is_lvds && dev_priv->lvds_downclock_avail) {
6135 /*
6136 * Ensure we match the reduced clock's P to the target
6137 * clock. If the clocks don't match, we can't switch
6138 * the display clock by using the FP0/FP1. In such case
6139 * we will disable the LVDS downclock feature.
6140 */
6141 has_reduced_clock =
6142 dev_priv->display.find_dpll(limit, crtc,
6143 dev_priv->lvds_downclock,
6144 refclk, &clock,
6145 &reduced_clock);
6146 }
6147 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01006148 intel_crtc->config.dpll.n = clock.n;
6149 intel_crtc->config.dpll.m1 = clock.m1;
6150 intel_crtc->config.dpll.m2 = clock.m2;
6151 intel_crtc->config.dpll.p1 = clock.p1;
6152 intel_crtc->config.dpll.p2 = clock.p2;
6153 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006154
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006155 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02006156 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306157 has_reduced_clock ? &reduced_clock : NULL,
6158 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006159 } else if (IS_CHERRYVIEW(dev)) {
6160 chv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006161 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03006162 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006163 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01006164 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006165 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006166 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006167 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006168
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006169 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006170}
6171
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006172static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6173 struct intel_crtc_config *pipe_config)
6174{
6175 struct drm_device *dev = crtc->base.dev;
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177 uint32_t tmp;
6178
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006179 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6180 return;
6181
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006182 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006183 if (!(tmp & PFIT_ENABLE))
6184 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006185
Daniel Vetter06922822013-07-11 13:35:40 +02006186 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006187 if (INTEL_INFO(dev)->gen < 4) {
6188 if (crtc->pipe != PIPE_B)
6189 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006190 } else {
6191 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6192 return;
6193 }
6194
Daniel Vetter06922822013-07-11 13:35:40 +02006195 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006196 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6197 if (INTEL_INFO(dev)->gen < 5)
6198 pipe_config->gmch_pfit.lvds_border_bits =
6199 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6200}
6201
Jesse Barnesacbec812013-09-20 11:29:32 -07006202static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6203 struct intel_crtc_config *pipe_config)
6204{
6205 struct drm_device *dev = crtc->base.dev;
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207 int pipe = pipe_config->cpu_transcoder;
6208 intel_clock_t clock;
6209 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006210 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006211
Shobhit Kumarf573de52014-07-30 20:32:37 +05306212 /* In case of MIPI DPLL will not even be used */
6213 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6214 return;
6215
Jesse Barnesacbec812013-09-20 11:29:32 -07006216 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006217 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006218 mutex_unlock(&dev_priv->dpio_lock);
6219
6220 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6221 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6222 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6223 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6224 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6225
Ville Syrjäläf6466282013-10-14 14:50:31 +03006226 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006227
Ville Syrjäläf6466282013-10-14 14:50:31 +03006228 /* clock.dot is the fast clock */
6229 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006230}
6231
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006232static void i9xx_get_plane_config(struct intel_crtc *crtc,
6233 struct intel_plane_config *plane_config)
6234{
6235 struct drm_device *dev = crtc->base.dev;
6236 struct drm_i915_private *dev_priv = dev->dev_private;
6237 u32 val, base, offset;
6238 int pipe = crtc->pipe, plane = crtc->plane;
6239 int fourcc, pixel_format;
6240 int aligned_height;
6241
Dave Airlie66e514c2014-04-03 07:51:54 +10006242 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6243 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006244 DRM_DEBUG_KMS("failed to alloc fb\n");
6245 return;
6246 }
6247
6248 val = I915_READ(DSPCNTR(plane));
6249
6250 if (INTEL_INFO(dev)->gen >= 4)
6251 if (val & DISPPLANE_TILED)
6252 plane_config->tiled = true;
6253
6254 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6255 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006256 crtc->base.primary->fb->pixel_format = fourcc;
6257 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006258 drm_format_plane_cpp(fourcc, 0) * 8;
6259
6260 if (INTEL_INFO(dev)->gen >= 4) {
6261 if (plane_config->tiled)
6262 offset = I915_READ(DSPTILEOFF(plane));
6263 else
6264 offset = I915_READ(DSPLINOFF(plane));
6265 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6266 } else {
6267 base = I915_READ(DSPADDR(plane));
6268 }
6269 plane_config->base = base;
6270
6271 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006272 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6273 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006274
6275 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01006276 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006277
Dave Airlie66e514c2014-04-03 07:51:54 +10006278 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006279 plane_config->tiled);
6280
Fabian Frederick1267a262014-07-01 20:39:41 +02006281 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6282 aligned_height);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006283
6284 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006285 pipe, plane, crtc->base.primary->fb->width,
6286 crtc->base.primary->fb->height,
6287 crtc->base.primary->fb->bits_per_pixel, base,
6288 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006289 plane_config->size);
6290
6291}
6292
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006293static void chv_crtc_clock_get(struct intel_crtc *crtc,
6294 struct intel_crtc_config *pipe_config)
6295{
6296 struct drm_device *dev = crtc->base.dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298 int pipe = pipe_config->cpu_transcoder;
6299 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6300 intel_clock_t clock;
6301 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6302 int refclk = 100000;
6303
6304 mutex_lock(&dev_priv->dpio_lock);
6305 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6306 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6307 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6308 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6309 mutex_unlock(&dev_priv->dpio_lock);
6310
6311 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6312 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6313 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6314 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6315 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6316
6317 chv_clock(refclk, &clock);
6318
6319 /* clock.dot is the fast clock */
6320 pipe_config->port_clock = clock.dot / 5;
6321}
6322
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006323static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6324 struct intel_crtc_config *pipe_config)
6325{
6326 struct drm_device *dev = crtc->base.dev;
6327 struct drm_i915_private *dev_priv = dev->dev_private;
6328 uint32_t tmp;
6329
Imre Deakb5482bd2014-03-05 16:20:55 +02006330 if (!intel_display_power_enabled(dev_priv,
6331 POWER_DOMAIN_PIPE(crtc->pipe)))
6332 return false;
6333
Daniel Vettere143a212013-07-04 12:01:15 +02006334 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006335 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006336
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006337 tmp = I915_READ(PIPECONF(crtc->pipe));
6338 if (!(tmp & PIPECONF_ENABLE))
6339 return false;
6340
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006341 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6342 switch (tmp & PIPECONF_BPC_MASK) {
6343 case PIPECONF_6BPC:
6344 pipe_config->pipe_bpp = 18;
6345 break;
6346 case PIPECONF_8BPC:
6347 pipe_config->pipe_bpp = 24;
6348 break;
6349 case PIPECONF_10BPC:
6350 pipe_config->pipe_bpp = 30;
6351 break;
6352 default:
6353 break;
6354 }
6355 }
6356
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006357 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6358 pipe_config->limited_color_range = true;
6359
Ville Syrjälä282740f2013-09-04 18:30:03 +03006360 if (INTEL_INFO(dev)->gen < 4)
6361 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6362
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006363 intel_get_pipe_timings(crtc, pipe_config);
6364
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006365 i9xx_get_pfit_config(crtc, pipe_config);
6366
Daniel Vetter6c49f242013-06-06 12:45:25 +02006367 if (INTEL_INFO(dev)->gen >= 4) {
6368 tmp = I915_READ(DPLL_MD(crtc->pipe));
6369 pipe_config->pixel_multiplier =
6370 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6371 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006372 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006373 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6374 tmp = I915_READ(DPLL(crtc->pipe));
6375 pipe_config->pixel_multiplier =
6376 ((tmp & SDVO_MULTIPLIER_MASK)
6377 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6378 } else {
6379 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6380 * port and will be fixed up in the encoder->get_config
6381 * function. */
6382 pipe_config->pixel_multiplier = 1;
6383 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006384 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6385 if (!IS_VALLEYVIEW(dev)) {
6386 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6387 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006388 } else {
6389 /* Mask out read-only status bits. */
6390 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6391 DPLL_PORTC_READY_MASK |
6392 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006393 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006394
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006395 if (IS_CHERRYVIEW(dev))
6396 chv_crtc_clock_get(crtc, pipe_config);
6397 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006398 vlv_crtc_clock_get(crtc, pipe_config);
6399 else
6400 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006401
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006402 return true;
6403}
6404
Paulo Zanonidde86e22012-12-01 12:04:25 -02006405static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006406{
6407 struct drm_i915_private *dev_priv = dev->dev_private;
6408 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006409 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006410 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006411 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006412 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006413 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006414 bool has_ck505 = false;
6415 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006416
6417 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07006418 list_for_each_entry(encoder, &mode_config->encoder_list,
6419 base.head) {
6420 switch (encoder->type) {
6421 case INTEL_OUTPUT_LVDS:
6422 has_panel = true;
6423 has_lvds = true;
6424 break;
6425 case INTEL_OUTPUT_EDP:
6426 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006427 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006428 has_cpu_edp = true;
6429 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006430 }
6431 }
6432
Keith Packard99eb6a02011-09-26 14:29:12 -07006433 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006434 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006435 can_ssc = has_ck505;
6436 } else {
6437 has_ck505 = false;
6438 can_ssc = true;
6439 }
6440
Imre Deak2de69052013-05-08 13:14:04 +03006441 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6442 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006443
6444 /* Ironlake: try to setup display ref clock before DPLL
6445 * enabling. This is only under driver's control after
6446 * PCH B stepping, previous chipset stepping should be
6447 * ignoring this setting.
6448 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006449 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006450
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006451 /* As we must carefully and slowly disable/enable each source in turn,
6452 * compute the final state we want first and check if we need to
6453 * make any changes at all.
6454 */
6455 final = val;
6456 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006457 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006458 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006459 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006460 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6461
6462 final &= ~DREF_SSC_SOURCE_MASK;
6463 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6464 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006465
Keith Packard199e5d72011-09-22 12:01:57 -07006466 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006467 final |= DREF_SSC_SOURCE_ENABLE;
6468
6469 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6470 final |= DREF_SSC1_ENABLE;
6471
6472 if (has_cpu_edp) {
6473 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6474 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6475 else
6476 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6477 } else
6478 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6479 } else {
6480 final |= DREF_SSC_SOURCE_DISABLE;
6481 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6482 }
6483
6484 if (final == val)
6485 return;
6486
6487 /* Always enable nonspread source */
6488 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6489
6490 if (has_ck505)
6491 val |= DREF_NONSPREAD_CK505_ENABLE;
6492 else
6493 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6494
6495 if (has_panel) {
6496 val &= ~DREF_SSC_SOURCE_MASK;
6497 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006498
Keith Packard199e5d72011-09-22 12:01:57 -07006499 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006500 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006501 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006502 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006503 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006504 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006505
6506 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006507 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006508 POSTING_READ(PCH_DREF_CONTROL);
6509 udelay(200);
6510
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006511 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006512
6513 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006514 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006515 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006516 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006517 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006518 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006519 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006520 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006521 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006522
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006523 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006524 POSTING_READ(PCH_DREF_CONTROL);
6525 udelay(200);
6526 } else {
6527 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6528
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006529 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006530
6531 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006532 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006533
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006534 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006535 POSTING_READ(PCH_DREF_CONTROL);
6536 udelay(200);
6537
6538 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006539 val &= ~DREF_SSC_SOURCE_MASK;
6540 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006541
6542 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006543 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006544
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006545 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006546 POSTING_READ(PCH_DREF_CONTROL);
6547 udelay(200);
6548 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006549
6550 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006551}
6552
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006553static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006554{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006555 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006556
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006557 tmp = I915_READ(SOUTH_CHICKEN2);
6558 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6559 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006560
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006561 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6562 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6563 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006564
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006565 tmp = I915_READ(SOUTH_CHICKEN2);
6566 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6567 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006568
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006569 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6570 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6571 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006572}
6573
6574/* WaMPhyProgramming:hsw */
6575static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6576{
6577 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006578
6579 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6580 tmp &= ~(0xFF << 24);
6581 tmp |= (0x12 << 24);
6582 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6583
Paulo Zanonidde86e22012-12-01 12:04:25 -02006584 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6585 tmp |= (1 << 11);
6586 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6587
6588 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6589 tmp |= (1 << 11);
6590 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6591
Paulo Zanonidde86e22012-12-01 12:04:25 -02006592 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6593 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6594 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6595
6596 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6597 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6598 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6599
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006600 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6601 tmp &= ~(7 << 13);
6602 tmp |= (5 << 13);
6603 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006604
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006605 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6606 tmp &= ~(7 << 13);
6607 tmp |= (5 << 13);
6608 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006609
6610 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6611 tmp &= ~0xFF;
6612 tmp |= 0x1C;
6613 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6614
6615 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6616 tmp &= ~0xFF;
6617 tmp |= 0x1C;
6618 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6619
6620 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6621 tmp &= ~(0xFF << 16);
6622 tmp |= (0x1C << 16);
6623 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6624
6625 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6626 tmp &= ~(0xFF << 16);
6627 tmp |= (0x1C << 16);
6628 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6629
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006630 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6631 tmp |= (1 << 27);
6632 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006633
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006634 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6635 tmp |= (1 << 27);
6636 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006637
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006638 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6639 tmp &= ~(0xF << 28);
6640 tmp |= (4 << 28);
6641 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006642
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006643 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6644 tmp &= ~(0xF << 28);
6645 tmp |= (4 << 28);
6646 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006647}
6648
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006649/* Implements 3 different sequences from BSpec chapter "Display iCLK
6650 * Programming" based on the parameters passed:
6651 * - Sequence to enable CLKOUT_DP
6652 * - Sequence to enable CLKOUT_DP without spread
6653 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6654 */
6655static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6656 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006657{
6658 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006659 uint32_t reg, tmp;
6660
6661 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6662 with_spread = true;
6663 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6664 with_fdi, "LP PCH doesn't have FDI\n"))
6665 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006666
6667 mutex_lock(&dev_priv->dpio_lock);
6668
6669 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6670 tmp &= ~SBI_SSCCTL_DISABLE;
6671 tmp |= SBI_SSCCTL_PATHALT;
6672 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6673
6674 udelay(24);
6675
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006676 if (with_spread) {
6677 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6678 tmp &= ~SBI_SSCCTL_PATHALT;
6679 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006680
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006681 if (with_fdi) {
6682 lpt_reset_fdi_mphy(dev_priv);
6683 lpt_program_fdi_mphy(dev_priv);
6684 }
6685 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02006686
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006687 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6688 SBI_GEN0 : SBI_DBUFF0;
6689 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6690 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6691 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01006692
6693 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006694}
6695
Paulo Zanoni47701c32013-07-23 11:19:25 -03006696/* Sequence to disable CLKOUT_DP */
6697static void lpt_disable_clkout_dp(struct drm_device *dev)
6698{
6699 struct drm_i915_private *dev_priv = dev->dev_private;
6700 uint32_t reg, tmp;
6701
6702 mutex_lock(&dev_priv->dpio_lock);
6703
6704 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6705 SBI_GEN0 : SBI_DBUFF0;
6706 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6707 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6708 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6709
6710 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6711 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6712 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6713 tmp |= SBI_SSCCTL_PATHALT;
6714 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6715 udelay(32);
6716 }
6717 tmp |= SBI_SSCCTL_DISABLE;
6718 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6719 }
6720
6721 mutex_unlock(&dev_priv->dpio_lock);
6722}
6723
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006724static void lpt_init_pch_refclk(struct drm_device *dev)
6725{
6726 struct drm_mode_config *mode_config = &dev->mode_config;
6727 struct intel_encoder *encoder;
6728 bool has_vga = false;
6729
6730 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6731 switch (encoder->type) {
6732 case INTEL_OUTPUT_ANALOG:
6733 has_vga = true;
6734 break;
6735 }
6736 }
6737
Paulo Zanoni47701c32013-07-23 11:19:25 -03006738 if (has_vga)
6739 lpt_enable_clkout_dp(dev, true, true);
6740 else
6741 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006742}
6743
Paulo Zanonidde86e22012-12-01 12:04:25 -02006744/*
6745 * Initialize reference clocks when the driver loads
6746 */
6747void intel_init_pch_refclk(struct drm_device *dev)
6748{
6749 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6750 ironlake_init_pch_refclk(dev);
6751 else if (HAS_PCH_LPT(dev))
6752 lpt_init_pch_refclk(dev);
6753}
6754
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006755static int ironlake_get_refclk(struct drm_crtc *crtc)
6756{
6757 struct drm_device *dev = crtc->dev;
6758 struct drm_i915_private *dev_priv = dev->dev_private;
6759 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006760 int num_connectors = 0;
6761 bool is_lvds = false;
6762
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02006763 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006764 switch (encoder->type) {
6765 case INTEL_OUTPUT_LVDS:
6766 is_lvds = true;
6767 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006768 }
6769 num_connectors++;
6770 }
6771
6772 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006773 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006774 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006775 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006776 }
6777
6778 return 120000;
6779}
6780
Daniel Vetter6ff93602013-04-19 11:24:36 +02006781static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03006782{
6783 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6785 int pipe = intel_crtc->pipe;
6786 uint32_t val;
6787
Daniel Vetter78114072013-06-13 00:54:57 +02006788 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03006789
Daniel Vetter965e0c42013-03-27 00:44:57 +01006790 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03006791 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006792 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006793 break;
6794 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006795 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006796 break;
6797 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006798 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006799 break;
6800 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006801 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006802 break;
6803 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03006804 /* Case prevented by intel_choose_pipe_bpp_dither. */
6805 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03006806 }
6807
Daniel Vetterd8b32242013-04-25 17:54:44 +02006808 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03006809 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6810
Daniel Vetter6ff93602013-04-19 11:24:36 +02006811 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03006812 val |= PIPECONF_INTERLACED_ILK;
6813 else
6814 val |= PIPECONF_PROGRESSIVE;
6815
Daniel Vetter50f3b012013-03-27 00:44:56 +01006816 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006817 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006818
Paulo Zanonic8203562012-09-12 10:06:29 -03006819 I915_WRITE(PIPECONF(pipe), val);
6820 POSTING_READ(PIPECONF(pipe));
6821}
6822
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006823/*
6824 * Set up the pipe CSC unit.
6825 *
6826 * Currently only full range RGB to limited range RGB conversion
6827 * is supported, but eventually this should handle various
6828 * RGB<->YCbCr scenarios as well.
6829 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01006830static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006831{
6832 struct drm_device *dev = crtc->dev;
6833 struct drm_i915_private *dev_priv = dev->dev_private;
6834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6835 int pipe = intel_crtc->pipe;
6836 uint16_t coeff = 0x7800; /* 1.0 */
6837
6838 /*
6839 * TODO: Check what kind of values actually come out of the pipe
6840 * with these coeff/postoff values and adjust to get the best
6841 * accuracy. Perhaps we even need to take the bpc value into
6842 * consideration.
6843 */
6844
Daniel Vetter50f3b012013-03-27 00:44:56 +01006845 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006846 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6847
6848 /*
6849 * GY/GU and RY/RU should be the other way around according
6850 * to BSpec, but reality doesn't agree. Just set them up in
6851 * a way that results in the correct picture.
6852 */
6853 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6854 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6855
6856 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6857 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6858
6859 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6860 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6861
6862 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6863 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6864 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6865
6866 if (INTEL_INFO(dev)->gen > 6) {
6867 uint16_t postoff = 0;
6868
Daniel Vetter50f3b012013-03-27 00:44:56 +01006869 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02006870 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006871
6872 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6873 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6874 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6875
6876 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6877 } else {
6878 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6879
Daniel Vetter50f3b012013-03-27 00:44:56 +01006880 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006881 mode |= CSC_BLACK_SCREEN_OFFSET;
6882
6883 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6884 }
6885}
6886
Daniel Vetter6ff93602013-04-19 11:24:36 +02006887static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006888{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006889 struct drm_device *dev = crtc->dev;
6890 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006892 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006893 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006894 uint32_t val;
6895
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006896 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006897
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006898 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006899 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6900
Daniel Vetter6ff93602013-04-19 11:24:36 +02006901 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006902 val |= PIPECONF_INTERLACED_ILK;
6903 else
6904 val |= PIPECONF_PROGRESSIVE;
6905
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006906 I915_WRITE(PIPECONF(cpu_transcoder), val);
6907 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006908
6909 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6910 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006911
6912 if (IS_BROADWELL(dev)) {
6913 val = 0;
6914
6915 switch (intel_crtc->config.pipe_bpp) {
6916 case 18:
6917 val |= PIPEMISC_DITHER_6_BPC;
6918 break;
6919 case 24:
6920 val |= PIPEMISC_DITHER_8_BPC;
6921 break;
6922 case 30:
6923 val |= PIPEMISC_DITHER_10_BPC;
6924 break;
6925 case 36:
6926 val |= PIPEMISC_DITHER_12_BPC;
6927 break;
6928 default:
6929 /* Case prevented by pipe_config_set_bpp. */
6930 BUG();
6931 }
6932
6933 if (intel_crtc->config.dither)
6934 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6935
6936 I915_WRITE(PIPEMISC(pipe), val);
6937 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006938}
6939
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006940static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006941 intel_clock_t *clock,
6942 bool *has_reduced_clock,
6943 intel_clock_t *reduced_clock)
6944{
6945 struct drm_device *dev = crtc->dev;
6946 struct drm_i915_private *dev_priv = dev->dev_private;
6947 struct intel_encoder *intel_encoder;
6948 int refclk;
6949 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02006950 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006951
6952 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6953 switch (intel_encoder->type) {
6954 case INTEL_OUTPUT_LVDS:
6955 is_lvds = true;
6956 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006957 }
6958 }
6959
6960 refclk = ironlake_get_refclk(crtc);
6961
6962 /*
6963 * Returns a set of divisors for the desired target clock with the given
6964 * refclk, or FALSE. The returned values represent the clock equation:
6965 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6966 */
6967 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006968 ret = dev_priv->display.find_dpll(limit, crtc,
6969 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006970 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006971 if (!ret)
6972 return false;
6973
6974 if (is_lvds && dev_priv->lvds_downclock_avail) {
6975 /*
6976 * Ensure we match the reduced clock's P to the target clock.
6977 * If the clocks don't match, we can't switch the display clock
6978 * by using the FP0/FP1. In such case we will disable the LVDS
6979 * downclock feature.
6980 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006981 *has_reduced_clock =
6982 dev_priv->display.find_dpll(limit, crtc,
6983 dev_priv->lvds_downclock,
6984 refclk, clock,
6985 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006986 }
6987
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006988 return true;
6989}
6990
Paulo Zanonid4b19312012-11-29 11:29:32 -02006991int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6992{
6993 /*
6994 * Account for spread spectrum to avoid
6995 * oversubscribing the link. Max center spread
6996 * is 2.5%; use 5% for safety's sake.
6997 */
6998 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02006999 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02007000}
7001
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007002static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02007003{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007004 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007005}
7006
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007007static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007008 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007009 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007010{
7011 struct drm_crtc *crtc = &intel_crtc->base;
7012 struct drm_device *dev = crtc->dev;
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 struct intel_encoder *intel_encoder;
7015 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01007016 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02007017 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007018
7019 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7020 switch (intel_encoder->type) {
7021 case INTEL_OUTPUT_LVDS:
7022 is_lvds = true;
7023 break;
7024 case INTEL_OUTPUT_SDVO:
7025 case INTEL_OUTPUT_HDMI:
7026 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007027 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007028 }
7029
7030 num_connectors++;
7031 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007032
Chris Wilsonc1858122010-12-03 21:35:48 +00007033 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07007034 factor = 21;
7035 if (is_lvds) {
7036 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007037 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02007038 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07007039 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02007040 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07007041 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00007042
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007043 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02007044 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00007045
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007046 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7047 *fp2 |= FP_CB_TUNE;
7048
Chris Wilson5eddb702010-09-11 13:48:45 +01007049 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08007050
Eric Anholta07d6782011-03-30 13:01:08 -07007051 if (is_lvds)
7052 dpll |= DPLLB_MODE_LVDS;
7053 else
7054 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007055
Daniel Vetteref1b4602013-06-01 17:17:04 +02007056 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7057 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007058
7059 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007060 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02007061 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007062 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08007063
Eric Anholta07d6782011-03-30 13:01:08 -07007064 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007065 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007066 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007067 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007068
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007069 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07007070 case 5:
7071 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7072 break;
7073 case 7:
7074 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7075 break;
7076 case 10:
7077 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7078 break;
7079 case 14:
7080 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7081 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007082 }
7083
Daniel Vetterb4c09f32013-04-30 14:01:42 +02007084 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05007085 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08007086 else
7087 dpll |= PLL_REF_INPUT_DREFCLK;
7088
Daniel Vetter959e16d2013-06-05 13:34:21 +02007089 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007090}
7091
Jesse Barnes79e53942008-11-07 14:24:08 -08007092static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08007093 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02007094 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08007095{
7096 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007098 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007099 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007100 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03007101 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01007102 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007103 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02007104 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007105
7106 for_each_encoder_on_crtc(dev, crtc, encoder) {
7107 switch (encoder->type) {
7108 case INTEL_OUTPUT_LVDS:
7109 is_lvds = true;
7110 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007111 }
7112
7113 num_connectors++;
7114 }
7115
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007116 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7117 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7118
Daniel Vetterff9a6752013-06-01 17:16:21 +02007119 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007120 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02007121 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007122 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7123 return -EINVAL;
7124 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01007125 /* Compat-code for transition, will disappear. */
7126 if (!intel_crtc->config.clock_set) {
7127 intel_crtc->config.dpll.n = clock.n;
7128 intel_crtc->config.dpll.m1 = clock.m1;
7129 intel_crtc->config.dpll.m2 = clock.m2;
7130 intel_crtc->config.dpll.p1 = clock.p1;
7131 intel_crtc->config.dpll.p2 = clock.p2;
7132 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007133
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007134 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01007135 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007136 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007137 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007138 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007139
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007140 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007141 &fp, &reduced_clock,
7142 has_reduced_clock ? &fp2 : NULL);
7143
Daniel Vetter959e16d2013-06-05 13:34:21 +02007144 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007145 intel_crtc->config.dpll_hw_state.fp0 = fp;
7146 if (has_reduced_clock)
7147 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7148 else
7149 intel_crtc->config.dpll_hw_state.fp1 = fp;
7150
Daniel Vetterb89a1d32013-06-05 13:34:24 +02007151 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007152 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03007153 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Daniel Vetter29407aa2014-04-24 23:55:08 +02007154 pipe_name(intel_crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07007155 return -EINVAL;
7156 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007157 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02007158 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007159
Jani Nikulad330a952014-01-21 11:24:25 +02007160 if (is_lvds && has_reduced_clock && i915.powersave)
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007161 intel_crtc->lowfreq_avail = true;
7162 else
7163 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007164
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007165 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007166}
7167
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007168static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7169 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007170{
7171 struct drm_device *dev = crtc->base.dev;
7172 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007173 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007174
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007175 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7176 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7177 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7178 & ~TU_SIZE_MASK;
7179 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7180 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7181 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7182}
7183
7184static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7185 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007186 struct intel_link_m_n *m_n,
7187 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007188{
7189 struct drm_device *dev = crtc->base.dev;
7190 struct drm_i915_private *dev_priv = dev->dev_private;
7191 enum pipe pipe = crtc->pipe;
7192
7193 if (INTEL_INFO(dev)->gen >= 5) {
7194 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7195 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7196 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7197 & ~TU_SIZE_MASK;
7198 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7199 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7200 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007201 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7202 * gen < 8) and if DRRS is supported (to make sure the
7203 * registers are not unnecessarily read).
7204 */
7205 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7206 crtc->config.has_drrs) {
7207 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7208 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7209 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7210 & ~TU_SIZE_MASK;
7211 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7212 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7213 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7214 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007215 } else {
7216 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7217 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7218 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7219 & ~TU_SIZE_MASK;
7220 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7221 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7222 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7223 }
7224}
7225
7226void intel_dp_get_m_n(struct intel_crtc *crtc,
7227 struct intel_crtc_config *pipe_config)
7228{
7229 if (crtc->config.has_pch_encoder)
7230 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7231 else
7232 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007233 &pipe_config->dp_m_n,
7234 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007235}
7236
Daniel Vetter72419202013-04-04 13:28:53 +02007237static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7238 struct intel_crtc_config *pipe_config)
7239{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007240 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007241 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02007242}
7243
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007244static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7245 struct intel_crtc_config *pipe_config)
7246{
7247 struct drm_device *dev = crtc->base.dev;
7248 struct drm_i915_private *dev_priv = dev->dev_private;
7249 uint32_t tmp;
7250
7251 tmp = I915_READ(PF_CTL(crtc->pipe));
7252
7253 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007254 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007255 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7256 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007257
7258 /* We currently do not free assignements of panel fitters on
7259 * ivb/hsw (since we don't use the higher upscaling modes which
7260 * differentiates them) so just WARN about this case for now. */
7261 if (IS_GEN7(dev)) {
7262 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7263 PF_PIPE_SEL_IVB(crtc->pipe));
7264 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007265 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007266}
7267
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007268static void ironlake_get_plane_config(struct intel_crtc *crtc,
7269 struct intel_plane_config *plane_config)
7270{
7271 struct drm_device *dev = crtc->base.dev;
7272 struct drm_i915_private *dev_priv = dev->dev_private;
7273 u32 val, base, offset;
7274 int pipe = crtc->pipe, plane = crtc->plane;
7275 int fourcc, pixel_format;
7276 int aligned_height;
7277
Dave Airlie66e514c2014-04-03 07:51:54 +10007278 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7279 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007280 DRM_DEBUG_KMS("failed to alloc fb\n");
7281 return;
7282 }
7283
7284 val = I915_READ(DSPCNTR(plane));
7285
7286 if (INTEL_INFO(dev)->gen >= 4)
7287 if (val & DISPPLANE_TILED)
7288 plane_config->tiled = true;
7289
7290 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7291 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007292 crtc->base.primary->fb->pixel_format = fourcc;
7293 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007294 drm_format_plane_cpp(fourcc, 0) * 8;
7295
7296 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7297 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7298 offset = I915_READ(DSPOFFSET(plane));
7299 } else {
7300 if (plane_config->tiled)
7301 offset = I915_READ(DSPTILEOFF(plane));
7302 else
7303 offset = I915_READ(DSPLINOFF(plane));
7304 }
7305 plane_config->base = base;
7306
7307 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007308 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7309 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007310
7311 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01007312 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007313
Dave Airlie66e514c2014-04-03 07:51:54 +10007314 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007315 plane_config->tiled);
7316
Fabian Frederick1267a262014-07-01 20:39:41 +02007317 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7318 aligned_height);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007319
7320 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007321 pipe, plane, crtc->base.primary->fb->width,
7322 crtc->base.primary->fb->height,
7323 crtc->base.primary->fb->bits_per_pixel, base,
7324 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007325 plane_config->size);
7326}
7327
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007328static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7329 struct intel_crtc_config *pipe_config)
7330{
7331 struct drm_device *dev = crtc->base.dev;
7332 struct drm_i915_private *dev_priv = dev->dev_private;
7333 uint32_t tmp;
7334
Paulo Zanoni930e8c92014-07-04 13:38:34 -03007335 if (!intel_display_power_enabled(dev_priv,
7336 POWER_DOMAIN_PIPE(crtc->pipe)))
7337 return false;
7338
Daniel Vettere143a212013-07-04 12:01:15 +02007339 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007340 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007341
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007342 tmp = I915_READ(PIPECONF(crtc->pipe));
7343 if (!(tmp & PIPECONF_ENABLE))
7344 return false;
7345
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007346 switch (tmp & PIPECONF_BPC_MASK) {
7347 case PIPECONF_6BPC:
7348 pipe_config->pipe_bpp = 18;
7349 break;
7350 case PIPECONF_8BPC:
7351 pipe_config->pipe_bpp = 24;
7352 break;
7353 case PIPECONF_10BPC:
7354 pipe_config->pipe_bpp = 30;
7355 break;
7356 case PIPECONF_12BPC:
7357 pipe_config->pipe_bpp = 36;
7358 break;
7359 default:
7360 break;
7361 }
7362
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007363 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7364 pipe_config->limited_color_range = true;
7365
Daniel Vetterab9412b2013-05-03 11:49:46 +02007366 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007367 struct intel_shared_dpll *pll;
7368
Daniel Vetter88adfff2013-03-28 10:42:01 +01007369 pipe_config->has_pch_encoder = true;
7370
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007371 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7372 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7373 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007374
7375 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007376
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007377 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007378 pipe_config->shared_dpll =
7379 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007380 } else {
7381 tmp = I915_READ(PCH_DPLL_SEL);
7382 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7383 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7384 else
7385 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7386 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007387
7388 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7389
7390 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7391 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007392
7393 tmp = pipe_config->dpll_hw_state.dpll;
7394 pipe_config->pixel_multiplier =
7395 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7396 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007397
7398 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007399 } else {
7400 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007401 }
7402
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007403 intel_get_pipe_timings(crtc, pipe_config);
7404
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007405 ironlake_get_pfit_config(crtc, pipe_config);
7406
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007407 return true;
7408}
7409
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007410static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7411{
7412 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007413 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007414
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007415 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007416 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007417 pipe_name(crtc->pipe));
7418
7419 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
Daniel Vetter8cc3e162014-06-25 22:01:46 +03007420 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7421 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7422 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007423 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7424 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7425 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -03007426 if (IS_HASWELL(dev))
7427 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7428 "CPU PWM2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007429 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7430 "PCH PWM1 enabled\n");
7431 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7432 "Utility pin enabled\n");
7433 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7434
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007435 /*
7436 * In theory we can still leave IRQs enabled, as long as only the HPD
7437 * interrupts remain enabled. We used to check for that, but since it's
7438 * gen-specific and since we only disable LCPLL after we fully disable
7439 * the interrupts, the check below should be enough.
7440 */
Jesse Barnes9df7575f2014-06-20 09:29:20 -07007441 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007442}
7443
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007444static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7445{
7446 struct drm_device *dev = dev_priv->dev;
7447
7448 if (IS_HASWELL(dev))
7449 return I915_READ(D_COMP_HSW);
7450 else
7451 return I915_READ(D_COMP_BDW);
7452}
7453
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007454static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7455{
7456 struct drm_device *dev = dev_priv->dev;
7457
7458 if (IS_HASWELL(dev)) {
7459 mutex_lock(&dev_priv->rps.hw_lock);
7460 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7461 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03007462 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007463 mutex_unlock(&dev_priv->rps.hw_lock);
7464 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007465 I915_WRITE(D_COMP_BDW, val);
7466 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007467 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007468}
7469
7470/*
7471 * This function implements pieces of two sequences from BSpec:
7472 * - Sequence for display software to disable LCPLL
7473 * - Sequence for display software to allow package C8+
7474 * The steps implemented here are just the steps that actually touch the LCPLL
7475 * register. Callers should take care of disabling all the display engine
7476 * functions, doing the mode unset, fixing interrupts, etc.
7477 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007478static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7479 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007480{
7481 uint32_t val;
7482
7483 assert_can_disable_lcpll(dev_priv);
7484
7485 val = I915_READ(LCPLL_CTL);
7486
7487 if (switch_to_fclk) {
7488 val |= LCPLL_CD_SOURCE_FCLK;
7489 I915_WRITE(LCPLL_CTL, val);
7490
7491 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7492 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7493 DRM_ERROR("Switching to FCLK failed\n");
7494
7495 val = I915_READ(LCPLL_CTL);
7496 }
7497
7498 val |= LCPLL_PLL_DISABLE;
7499 I915_WRITE(LCPLL_CTL, val);
7500 POSTING_READ(LCPLL_CTL);
7501
7502 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7503 DRM_ERROR("LCPLL still locked\n");
7504
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007505 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007506 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007507 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007508 ndelay(100);
7509
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007510 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7511 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007512 DRM_ERROR("D_COMP RCOMP still in progress\n");
7513
7514 if (allow_power_down) {
7515 val = I915_READ(LCPLL_CTL);
7516 val |= LCPLL_POWER_DOWN_ALLOW;
7517 I915_WRITE(LCPLL_CTL, val);
7518 POSTING_READ(LCPLL_CTL);
7519 }
7520}
7521
7522/*
7523 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7524 * source.
7525 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007526static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007527{
7528 uint32_t val;
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007529 unsigned long irqflags;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007530
7531 val = I915_READ(LCPLL_CTL);
7532
7533 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7534 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7535 return;
7536
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007537 /*
7538 * Make sure we're not on PC8 state before disabling PC8, otherwise
7539 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7540 *
7541 * The other problem is that hsw_restore_lcpll() is called as part of
7542 * the runtime PM resume sequence, so we can't just call
7543 * gen6_gt_force_wake_get() because that function calls
7544 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7545 * while we are on the resume sequence. So to solve this problem we have
7546 * to call special forcewake code that doesn't touch runtime PM and
7547 * doesn't enable the forcewake delayed work.
7548 */
7549 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7550 if (dev_priv->uncore.forcewake_count++ == 0)
7551 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7552 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007553
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007554 if (val & LCPLL_POWER_DOWN_ALLOW) {
7555 val &= ~LCPLL_POWER_DOWN_ALLOW;
7556 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007557 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007558 }
7559
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007560 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007561 val |= D_COMP_COMP_FORCE;
7562 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007563 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007564
7565 val = I915_READ(LCPLL_CTL);
7566 val &= ~LCPLL_PLL_DISABLE;
7567 I915_WRITE(LCPLL_CTL, val);
7568
7569 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7570 DRM_ERROR("LCPLL not locked yet\n");
7571
7572 if (val & LCPLL_CD_SOURCE_FCLK) {
7573 val = I915_READ(LCPLL_CTL);
7574 val &= ~LCPLL_CD_SOURCE_FCLK;
7575 I915_WRITE(LCPLL_CTL, val);
7576
7577 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7578 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7579 DRM_ERROR("Switching back to LCPLL failed\n");
7580 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007581
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007582 /* See the big comment above. */
7583 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7584 if (--dev_priv->uncore.forcewake_count == 0)
7585 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7586 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007587}
7588
Paulo Zanoni765dab62014-03-07 20:08:18 -03007589/*
7590 * Package states C8 and deeper are really deep PC states that can only be
7591 * reached when all the devices on the system allow it, so even if the graphics
7592 * device allows PC8+, it doesn't mean the system will actually get to these
7593 * states. Our driver only allows PC8+ when going into runtime PM.
7594 *
7595 * The requirements for PC8+ are that all the outputs are disabled, the power
7596 * well is disabled and most interrupts are disabled, and these are also
7597 * requirements for runtime PM. When these conditions are met, we manually do
7598 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7599 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7600 * hang the machine.
7601 *
7602 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7603 * the state of some registers, so when we come back from PC8+ we need to
7604 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7605 * need to take care of the registers kept by RC6. Notice that this happens even
7606 * if we don't put the device in PCI D3 state (which is what currently happens
7607 * because of the runtime PM support).
7608 *
7609 * For more, read "Display Sequences for Package C8" on the hardware
7610 * documentation.
7611 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007612void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007613{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007614 struct drm_device *dev = dev_priv->dev;
7615 uint32_t val;
7616
Paulo Zanonic67a4702013-08-19 13:18:09 -03007617 DRM_DEBUG_KMS("Enabling package C8+\n");
7618
Paulo Zanonic67a4702013-08-19 13:18:09 -03007619 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7620 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7621 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7622 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7623 }
7624
7625 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007626 hsw_disable_lcpll(dev_priv, true, true);
7627}
7628
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007629void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007630{
7631 struct drm_device *dev = dev_priv->dev;
7632 uint32_t val;
7633
Paulo Zanonic67a4702013-08-19 13:18:09 -03007634 DRM_DEBUG_KMS("Disabling package C8+\n");
7635
7636 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007637 lpt_init_pch_refclk(dev);
7638
7639 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7640 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7641 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7642 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7643 }
7644
7645 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007646}
7647
Paulo Zanoni9a952a02014-03-07 20:12:34 -03007648static void snb_modeset_global_resources(struct drm_device *dev)
7649{
7650 modeset_update_crtc_power_domains(dev);
7651}
7652
Imre Deak4f074122013-10-16 17:25:51 +03007653static void haswell_modeset_global_resources(struct drm_device *dev)
7654{
Paulo Zanonida723562013-12-19 11:54:51 -02007655 modeset_update_crtc_power_domains(dev);
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02007656}
7657
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007658static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007659 int x, int y,
7660 struct drm_framebuffer *fb)
7661{
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007663
Paulo Zanoni566b7342013-11-25 15:27:08 -02007664 if (!intel_ddi_pll_select(intel_crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007665 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03007666
Daniel Vetter644cef32014-04-24 23:55:07 +02007667 intel_crtc->lowfreq_avail = false;
7668
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007669 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007670}
7671
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007672static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7673 enum port port,
7674 struct intel_crtc_config *pipe_config)
7675{
7676 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7677
7678 switch (pipe_config->ddi_pll_sel) {
7679 case PORT_CLK_SEL_WRPLL1:
7680 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7681 break;
7682 case PORT_CLK_SEL_WRPLL2:
7683 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7684 break;
7685 }
7686}
7687
Daniel Vetter26804af2014-06-25 22:01:55 +03007688static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7689 struct intel_crtc_config *pipe_config)
7690{
7691 struct drm_device *dev = crtc->base.dev;
7692 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007693 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03007694 enum port port;
7695 uint32_t tmp;
7696
7697 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7698
7699 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7700
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007701 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +03007702
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007703 if (pipe_config->shared_dpll >= 0) {
7704 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7705
7706 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7707 &pipe_config->dpll_hw_state));
7708 }
7709
Daniel Vetter26804af2014-06-25 22:01:55 +03007710 /*
7711 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7712 * DDI E. So just check whether this pipe is wired to DDI E and whether
7713 * the PCH transcoder is on.
7714 */
7715 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7716 pipe_config->has_pch_encoder = true;
7717
7718 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7719 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7720 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7721
7722 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7723 }
7724}
7725
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007726static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7727 struct intel_crtc_config *pipe_config)
7728{
7729 struct drm_device *dev = crtc->base.dev;
7730 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007731 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007732 uint32_t tmp;
7733
Imre Deakb5482bd2014-03-05 16:20:55 +02007734 if (!intel_display_power_enabled(dev_priv,
7735 POWER_DOMAIN_PIPE(crtc->pipe)))
7736 return false;
7737
Daniel Vettere143a212013-07-04 12:01:15 +02007738 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007739 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7740
Daniel Vettereccb1402013-05-22 00:50:22 +02007741 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7742 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7743 enum pipe trans_edp_pipe;
7744 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7745 default:
7746 WARN(1, "unknown pipe linked to edp transcoder\n");
7747 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7748 case TRANS_DDI_EDP_INPUT_A_ON:
7749 trans_edp_pipe = PIPE_A;
7750 break;
7751 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7752 trans_edp_pipe = PIPE_B;
7753 break;
7754 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7755 trans_edp_pipe = PIPE_C;
7756 break;
7757 }
7758
7759 if (trans_edp_pipe == crtc->pipe)
7760 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7761 }
7762
Imre Deakda7e29b2014-02-18 00:02:02 +02007763 if (!intel_display_power_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02007764 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03007765 return false;
7766
Daniel Vettereccb1402013-05-22 00:50:22 +02007767 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007768 if (!(tmp & PIPECONF_ENABLE))
7769 return false;
7770
Daniel Vetter26804af2014-06-25 22:01:55 +03007771 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007772
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007773 intel_get_pipe_timings(crtc, pipe_config);
7774
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007775 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Imre Deakda7e29b2014-02-18 00:02:02 +02007776 if (intel_display_power_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007777 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01007778
Jesse Barnese59150d2014-01-07 13:30:45 -08007779 if (IS_HASWELL(dev))
7780 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7781 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007782
Daniel Vetter6c49f242013-06-06 12:45:25 +02007783 pipe_config->pixel_multiplier = 1;
7784
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007785 return true;
7786}
7787
Jani Nikula1a915102013-10-16 12:34:48 +03007788static struct {
7789 int clock;
7790 u32 config;
7791} hdmi_audio_clock[] = {
7792 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7793 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7794 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7795 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7796 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7797 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7798 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7799 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7800 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7801 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7802};
7803
7804/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7805static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7806{
7807 int i;
7808
7809 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7810 if (mode->clock == hdmi_audio_clock[i].clock)
7811 break;
7812 }
7813
7814 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7815 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7816 i = 1;
7817 }
7818
7819 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7820 hdmi_audio_clock[i].clock,
7821 hdmi_audio_clock[i].config);
7822
7823 return hdmi_audio_clock[i].config;
7824}
7825
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007826static bool intel_eld_uptodate(struct drm_connector *connector,
7827 int reg_eldv, uint32_t bits_eldv,
7828 int reg_elda, uint32_t bits_elda,
7829 int reg_edid)
7830{
7831 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7832 uint8_t *eld = connector->eld;
7833 uint32_t i;
7834
7835 i = I915_READ(reg_eldv);
7836 i &= bits_eldv;
7837
7838 if (!eld[0])
7839 return !i;
7840
7841 if (!i)
7842 return false;
7843
7844 i = I915_READ(reg_elda);
7845 i &= ~bits_elda;
7846 I915_WRITE(reg_elda, i);
7847
7848 for (i = 0; i < eld[2]; i++)
7849 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7850 return false;
7851
7852 return true;
7853}
7854
Wu Fengguange0dac652011-09-05 14:25:34 +08007855static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007856 struct drm_crtc *crtc,
7857 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007858{
7859 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7860 uint8_t *eld = connector->eld;
7861 uint32_t eldv;
7862 uint32_t len;
7863 uint32_t i;
7864
7865 i = I915_READ(G4X_AUD_VID_DID);
7866
7867 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7868 eldv = G4X_ELDV_DEVCL_DEVBLC;
7869 else
7870 eldv = G4X_ELDV_DEVCTG;
7871
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007872 if (intel_eld_uptodate(connector,
7873 G4X_AUD_CNTL_ST, eldv,
7874 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7875 G4X_HDMIW_HDMIEDID))
7876 return;
7877
Wu Fengguange0dac652011-09-05 14:25:34 +08007878 i = I915_READ(G4X_AUD_CNTL_ST);
7879 i &= ~(eldv | G4X_ELD_ADDR);
7880 len = (i >> 9) & 0x1f; /* ELD buffer size */
7881 I915_WRITE(G4X_AUD_CNTL_ST, i);
7882
7883 if (!eld[0])
7884 return;
7885
7886 len = min_t(uint8_t, eld[2], len);
7887 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7888 for (i = 0; i < len; i++)
7889 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7890
7891 i = I915_READ(G4X_AUD_CNTL_ST);
7892 i |= eldv;
7893 I915_WRITE(G4X_AUD_CNTL_ST, i);
7894}
7895
Wang Xingchao83358c852012-08-16 22:43:37 +08007896static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007897 struct drm_crtc *crtc,
7898 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007899{
7900 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7901 uint8_t *eld = connector->eld;
Wang Xingchao83358c852012-08-16 22:43:37 +08007902 uint32_t eldv;
7903 uint32_t i;
7904 int len;
7905 int pipe = to_intel_crtc(crtc)->pipe;
7906 int tmp;
7907
7908 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7909 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7910 int aud_config = HSW_AUD_CFG(pipe);
7911 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7912
Wang Xingchao83358c852012-08-16 22:43:37 +08007913 /* Audio output enable */
7914 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7915 tmp = I915_READ(aud_cntrl_st2);
7916 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7917 I915_WRITE(aud_cntrl_st2, tmp);
Daniel Vetterc7905792014-04-16 16:56:09 +02007918 POSTING_READ(aud_cntrl_st2);
Wang Xingchao83358c852012-08-16 22:43:37 +08007919
Daniel Vetterc7905792014-04-16 16:56:09 +02007920 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Wang Xingchao83358c852012-08-16 22:43:37 +08007921
7922 /* Set ELD valid state */
7923 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007924 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007925 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7926 I915_WRITE(aud_cntrl_st2, tmp);
7927 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007928 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007929
7930 /* Enable HDMI mode */
7931 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007932 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007933 /* clear N_programing_enable and N_value_index */
7934 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7935 I915_WRITE(aud_config, tmp);
7936
7937 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7938
7939 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7940
7941 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7942 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7943 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7944 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007945 } else {
7946 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7947 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007948
7949 if (intel_eld_uptodate(connector,
7950 aud_cntrl_st2, eldv,
7951 aud_cntl_st, IBX_ELD_ADDRESS,
7952 hdmiw_hdmiedid))
7953 return;
7954
7955 i = I915_READ(aud_cntrl_st2);
7956 i &= ~eldv;
7957 I915_WRITE(aud_cntrl_st2, i);
7958
7959 if (!eld[0])
7960 return;
7961
7962 i = I915_READ(aud_cntl_st);
7963 i &= ~IBX_ELD_ADDRESS;
7964 I915_WRITE(aud_cntl_st, i);
7965 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7966 DRM_DEBUG_DRIVER("port num:%d\n", i);
7967
7968 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7969 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7970 for (i = 0; i < len; i++)
7971 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7972
7973 i = I915_READ(aud_cntrl_st2);
7974 i |= eldv;
7975 I915_WRITE(aud_cntrl_st2, i);
7976
7977}
7978
Wu Fengguange0dac652011-09-05 14:25:34 +08007979static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007980 struct drm_crtc *crtc,
7981 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007982{
7983 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7984 uint8_t *eld = connector->eld;
7985 uint32_t eldv;
7986 uint32_t i;
7987 int len;
7988 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007989 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007990 int aud_cntl_st;
7991 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007992 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007993
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007994 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007995 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7996 aud_config = IBX_AUD_CFG(pipe);
7997 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007998 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007999 } else if (IS_VALLEYVIEW(connector->dev)) {
8000 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8001 aud_config = VLV_AUD_CFG(pipe);
8002 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8003 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08008004 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08008005 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8006 aud_config = CPT_AUD_CFG(pipe);
8007 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008008 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08008009 }
8010
Wang Xingchao9b138a82012-08-09 16:52:18 +08008011 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08008012
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04008013 if (IS_VALLEYVIEW(connector->dev)) {
8014 struct intel_encoder *intel_encoder;
8015 struct intel_digital_port *intel_dig_port;
8016
8017 intel_encoder = intel_attached_encoder(connector);
8018 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8019 i = intel_dig_port->port;
8020 } else {
8021 i = I915_READ(aud_cntl_st);
8022 i = (i >> 29) & DIP_PORT_SEL_MASK;
8023 /* DIP_Port_Select, 0x1 = PortB */
8024 }
8025
Wu Fengguange0dac652011-09-05 14:25:34 +08008026 if (!i) {
8027 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8028 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008029 eldv = IBX_ELD_VALIDB;
8030 eldv |= IBX_ELD_VALIDB << 4;
8031 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08008032 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03008033 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008034 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08008035 }
8036
Wu Fengguang3a9627f2011-12-09 20:42:19 +08008037 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8038 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8039 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06008040 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03008041 } else {
8042 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8043 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08008044
8045 if (intel_eld_uptodate(connector,
8046 aud_cntrl_st2, eldv,
8047 aud_cntl_st, IBX_ELD_ADDRESS,
8048 hdmiw_hdmiedid))
8049 return;
8050
Wu Fengguange0dac652011-09-05 14:25:34 +08008051 i = I915_READ(aud_cntrl_st2);
8052 i &= ~eldv;
8053 I915_WRITE(aud_cntrl_st2, i);
8054
8055 if (!eld[0])
8056 return;
8057
Wu Fengguange0dac652011-09-05 14:25:34 +08008058 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008059 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08008060 I915_WRITE(aud_cntl_st, i);
8061
8062 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8063 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8064 for (i = 0; i < len; i++)
8065 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8066
8067 i = I915_READ(aud_cntrl_st2);
8068 i |= eldv;
8069 I915_WRITE(aud_cntrl_st2, i);
8070}
8071
8072void intel_write_eld(struct drm_encoder *encoder,
8073 struct drm_display_mode *mode)
8074{
8075 struct drm_crtc *crtc = encoder->crtc;
8076 struct drm_connector *connector;
8077 struct drm_device *dev = encoder->dev;
8078 struct drm_i915_private *dev_priv = dev->dev_private;
8079
8080 connector = drm_select_eld(encoder, mode);
8081 if (!connector)
8082 return;
8083
8084 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8085 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03008086 connector->name,
Wu Fengguange0dac652011-09-05 14:25:34 +08008087 connector->encoder->base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +03008088 connector->encoder->name);
Wu Fengguange0dac652011-09-05 14:25:34 +08008089
8090 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8091
8092 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03008093 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08008094}
8095
Chris Wilson560b85b2010-08-07 11:01:38 +01008096static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8097{
8098 struct drm_device *dev = crtc->dev;
8099 struct drm_i915_private *dev_priv = dev->dev_private;
8100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson4b0e3332014-05-30 16:35:26 +03008101 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01008102
Chris Wilson4b0e3332014-05-30 16:35:26 +03008103 if (base != intel_crtc->cursor_base) {
Chris Wilson560b85b2010-08-07 11:01:38 +01008104 /* On these chipsets we can only modify the base whilst
8105 * the cursor is disabled.
8106 */
Chris Wilson4b0e3332014-05-30 16:35:26 +03008107 if (intel_crtc->cursor_cntl) {
8108 I915_WRITE(_CURACNTR, 0);
8109 POSTING_READ(_CURACNTR);
8110 intel_crtc->cursor_cntl = 0;
8111 }
8112
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008113 I915_WRITE(_CURABASE, base);
Chris Wilson4b0e3332014-05-30 16:35:26 +03008114 POSTING_READ(_CURABASE);
8115 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008116
Chris Wilson4b0e3332014-05-30 16:35:26 +03008117 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8118 cntl = 0;
8119 if (base)
8120 cntl = (CURSOR_ENABLE |
Chris Wilson560b85b2010-08-07 11:01:38 +01008121 CURSOR_GAMMA_ENABLE |
Chris Wilson4b0e3332014-05-30 16:35:26 +03008122 CURSOR_FORMAT_ARGB);
8123 if (intel_crtc->cursor_cntl != cntl) {
8124 I915_WRITE(_CURACNTR, cntl);
8125 POSTING_READ(_CURACNTR);
8126 intel_crtc->cursor_cntl = cntl;
8127 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008128}
8129
8130static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8131{
8132 struct drm_device *dev = crtc->dev;
8133 struct drm_i915_private *dev_priv = dev->dev_private;
8134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8135 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008136 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01008137
Chris Wilson4b0e3332014-05-30 16:35:26 +03008138 cntl = 0;
8139 if (base) {
8140 cntl = MCURSOR_GAMMA_ENABLE;
8141 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308142 case 64:
8143 cntl |= CURSOR_MODE_64_ARGB_AX;
8144 break;
8145 case 128:
8146 cntl |= CURSOR_MODE_128_ARGB_AX;
8147 break;
8148 case 256:
8149 cntl |= CURSOR_MODE_256_ARGB_AX;
8150 break;
8151 default:
8152 WARN_ON(1);
8153 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01008154 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008155 cntl |= pipe << 28; /* Connect to correct pipe */
Chris Wilson560b85b2010-08-07 11:01:38 +01008156 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008157 if (intel_crtc->cursor_cntl != cntl) {
8158 I915_WRITE(CURCNTR(pipe), cntl);
8159 POSTING_READ(CURCNTR(pipe));
8160 intel_crtc->cursor_cntl = cntl;
8161 }
8162
Chris Wilson560b85b2010-08-07 11:01:38 +01008163 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008164 I915_WRITE(CURBASE(pipe), base);
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01008165 POSTING_READ(CURBASE(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01008166}
8167
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008168static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8169{
8170 struct drm_device *dev = crtc->dev;
8171 struct drm_i915_private *dev_priv = dev->dev_private;
8172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8173 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008174 uint32_t cntl;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008175
Chris Wilson4b0e3332014-05-30 16:35:26 +03008176 cntl = 0;
8177 if (base) {
8178 cntl = MCURSOR_GAMMA_ENABLE;
8179 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308180 case 64:
8181 cntl |= CURSOR_MODE_64_ARGB_AX;
8182 break;
8183 case 128:
8184 cntl |= CURSOR_MODE_128_ARGB_AX;
8185 break;
8186 case 256:
8187 cntl |= CURSOR_MODE_256_ARGB_AX;
8188 break;
8189 default:
8190 WARN_ON(1);
8191 return;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008192 }
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008193 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008194 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8195 cntl |= CURSOR_PIPE_CSC_ENABLE;
8196
8197 if (intel_crtc->cursor_cntl != cntl) {
8198 I915_WRITE(CURCNTR(pipe), cntl);
8199 POSTING_READ(CURCNTR(pipe));
8200 intel_crtc->cursor_cntl = cntl;
8201 }
8202
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008203 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008204 I915_WRITE(CURBASE(pipe), base);
8205 POSTING_READ(CURBASE(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008206}
8207
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008208/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01008209static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8210 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008211{
8212 struct drm_device *dev = crtc->dev;
8213 struct drm_i915_private *dev_priv = dev->dev_private;
8214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8215 int pipe = intel_crtc->pipe;
Matt Roper3d7d6512014-06-10 08:28:13 -07008216 int x = crtc->cursor_x;
8217 int y = crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008218 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008219
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008220 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008221 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008222
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008223 if (x >= intel_crtc->config.pipe_src_w)
8224 base = 0;
8225
8226 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008227 base = 0;
8228
8229 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008230 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008231 base = 0;
8232
8233 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8234 x = -x;
8235 }
8236 pos |= x << CURSOR_X_SHIFT;
8237
8238 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008239 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008240 base = 0;
8241
8242 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8243 y = -y;
8244 }
8245 pos |= y << CURSOR_Y_SHIFT;
8246
Chris Wilson4b0e3332014-05-30 16:35:26 +03008247 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008248 return;
8249
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008250 I915_WRITE(CURPOS(pipe), pos);
8251
8252 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008253 ivb_update_cursor(crtc, base);
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008254 else if (IS_845G(dev) || IS_I865G(dev))
8255 i845_update_cursor(crtc, base);
8256 else
8257 i9xx_update_cursor(crtc, base);
Chris Wilson4b0e3332014-05-30 16:35:26 +03008258 intel_crtc->cursor_base = base;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008259}
8260
Matt Ropere3287952014-06-10 08:28:12 -07008261/*
8262 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8263 *
8264 * Note that the object's reference will be consumed if the update fails. If
8265 * the update succeeds, the reference of the old object (if any) will be
8266 * consumed.
8267 */
8268static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8269 struct drm_i915_gem_object *obj,
8270 uint32_t width, uint32_t height)
Jesse Barnes79e53942008-11-07 14:24:08 -08008271{
8272 struct drm_device *dev = crtc->dev;
8273 struct drm_i915_private *dev_priv = dev->dev_private;
8274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02008275 enum pipe pipe = intel_crtc->pipe;
Chris Wilson64f962e2014-03-26 12:38:15 +00008276 unsigned old_width;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008277 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008278 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008279
Jesse Barnes79e53942008-11-07 14:24:08 -08008280 /* if we want to turn off the cursor ignore width and height */
Matt Ropere3287952014-06-10 08:28:12 -07008281 if (!obj) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008282 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008283 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00008284 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008285 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008286 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008287 }
8288
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308289 /* Check for which cursor types we support */
8290 if (!((width == 64 && height == 64) ||
8291 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8292 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8293 DRM_DEBUG("Cursor dimension not supported\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08008294 return -EINVAL;
8295 }
8296
Chris Wilson05394f32010-11-08 19:18:58 +00008297 if (obj->base.size < width * height * 4) {
Matt Ropere3287952014-06-10 08:28:12 -07008298 DRM_DEBUG_KMS("buffer is too small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10008299 ret = -ENOMEM;
8300 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008301 }
8302
Dave Airlie71acb5e2008-12-30 20:31:46 +10008303 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008304 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008305 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008306 unsigned alignment;
8307
Chris Wilsond9e86c02010-11-10 16:40:20 +00008308 if (obj->tiling_mode) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008309 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008310 ret = -EINVAL;
8311 goto fail_locked;
8312 }
8313
Chris Wilson693db182013-03-05 14:52:39 +00008314 /* Note that the w/a also requires 2 PTE of padding following
8315 * the bo. We currently fill all unused PTE with the shadow
8316 * page and so we should always have valid PTE following the
8317 * cursor preventing the VT-d warning.
8318 */
8319 alignment = 0;
8320 if (need_vtd_wa(dev))
8321 alignment = 64*1024;
8322
8323 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008324 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008325 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008326 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008327 }
8328
Chris Wilsond9e86c02010-11-10 16:40:20 +00008329 ret = i915_gem_object_put_fence(obj);
8330 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008331 DRM_DEBUG_KMS("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008332 goto fail_unpin;
8333 }
8334
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008335 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008336 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008337 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson00731152014-05-21 12:42:56 +01008338 ret = i915_gem_object_attach_phys(obj, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008339 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008340 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008341 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008342 }
Chris Wilson00731152014-05-21 12:42:56 +01008343 addr = obj->phys_handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008344 }
8345
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008346 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04008347 I915_WRITE(CURSIZE, (height << 12) | width);
8348
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008349 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008350 if (intel_crtc->cursor_bo) {
Chris Wilson00731152014-05-21 12:42:56 +01008351 if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilsoncc98b412013-08-09 12:25:09 +01008352 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008353 }
Jesse Barnes80824002009-09-10 15:28:06 -07008354
Daniel Vettera071fa02014-06-18 23:28:09 +02008355 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8356 INTEL_FRONTBUFFER_CURSOR(pipe));
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008357 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008358
Chris Wilson64f962e2014-03-26 12:38:15 +00008359 old_width = intel_crtc->cursor_width;
8360
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008361 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008362 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008363 intel_crtc->cursor_width = width;
8364 intel_crtc->cursor_height = height;
8365
Chris Wilson64f962e2014-03-26 12:38:15 +00008366 if (intel_crtc->active) {
8367 if (old_width != width)
8368 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008369 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Chris Wilson64f962e2014-03-26 12:38:15 +00008370 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008371
Daniel Vetterf99d7062014-06-19 16:01:59 +02008372 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8373
Jesse Barnes79e53942008-11-07 14:24:08 -08008374 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008375fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008376 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008377fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008378 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00008379fail:
Chris Wilson05394f32010-11-08 19:18:58 +00008380 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10008381 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008382}
8383
Jesse Barnes79e53942008-11-07 14:24:08 -08008384static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008385 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008386{
James Simmons72034252010-08-03 01:33:19 +01008387 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008389
James Simmons72034252010-08-03 01:33:19 +01008390 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008391 intel_crtc->lut_r[i] = red[i] >> 8;
8392 intel_crtc->lut_g[i] = green[i] >> 8;
8393 intel_crtc->lut_b[i] = blue[i] >> 8;
8394 }
8395
8396 intel_crtc_load_lut(crtc);
8397}
8398
Jesse Barnes79e53942008-11-07 14:24:08 -08008399/* VESA 640x480x72Hz mode to set on the pipe */
8400static struct drm_display_mode load_detect_mode = {
8401 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8402 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8403};
8404
Daniel Vettera8bb6812014-02-10 18:00:39 +01008405struct drm_framebuffer *
8406__intel_framebuffer_create(struct drm_device *dev,
8407 struct drm_mode_fb_cmd2 *mode_cmd,
8408 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008409{
8410 struct intel_framebuffer *intel_fb;
8411 int ret;
8412
8413 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8414 if (!intel_fb) {
8415 drm_gem_object_unreference_unlocked(&obj->base);
8416 return ERR_PTR(-ENOMEM);
8417 }
8418
8419 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008420 if (ret)
8421 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008422
8423 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008424err:
8425 drm_gem_object_unreference_unlocked(&obj->base);
8426 kfree(intel_fb);
8427
8428 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008429}
8430
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008431static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008432intel_framebuffer_create(struct drm_device *dev,
8433 struct drm_mode_fb_cmd2 *mode_cmd,
8434 struct drm_i915_gem_object *obj)
8435{
8436 struct drm_framebuffer *fb;
8437 int ret;
8438
8439 ret = i915_mutex_lock_interruptible(dev);
8440 if (ret)
8441 return ERR_PTR(ret);
8442 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8443 mutex_unlock(&dev->struct_mutex);
8444
8445 return fb;
8446}
8447
Chris Wilsond2dff872011-04-19 08:36:26 +01008448static u32
8449intel_framebuffer_pitch_for_width(int width, int bpp)
8450{
8451 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8452 return ALIGN(pitch, 64);
8453}
8454
8455static u32
8456intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8457{
8458 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +02008459 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +01008460}
8461
8462static struct drm_framebuffer *
8463intel_framebuffer_create_for_mode(struct drm_device *dev,
8464 struct drm_display_mode *mode,
8465 int depth, int bpp)
8466{
8467 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008468 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008469
8470 obj = i915_gem_alloc_object(dev,
8471 intel_framebuffer_size_for_mode(mode, bpp));
8472 if (obj == NULL)
8473 return ERR_PTR(-ENOMEM);
8474
8475 mode_cmd.width = mode->hdisplay;
8476 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008477 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8478 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008479 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008480
8481 return intel_framebuffer_create(dev, &mode_cmd, obj);
8482}
8483
8484static struct drm_framebuffer *
8485mode_fits_in_fbdev(struct drm_device *dev,
8486 struct drm_display_mode *mode)
8487{
Daniel Vetter4520f532013-10-09 09:18:51 +02008488#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008489 struct drm_i915_private *dev_priv = dev->dev_private;
8490 struct drm_i915_gem_object *obj;
8491 struct drm_framebuffer *fb;
8492
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008493 if (!dev_priv->fbdev)
8494 return NULL;
8495
8496 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008497 return NULL;
8498
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008499 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008500 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008501
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008502 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008503 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8504 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008505 return NULL;
8506
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008507 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008508 return NULL;
8509
8510 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008511#else
8512 return NULL;
8513#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008514}
8515
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008516bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008517 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05008518 struct intel_load_detect_pipe *old,
8519 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008520{
8521 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008522 struct intel_encoder *intel_encoder =
8523 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008524 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008525 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008526 struct drm_crtc *crtc = NULL;
8527 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008528 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05008529 struct drm_mode_config *config = &dev->mode_config;
8530 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008531
Chris Wilsond2dff872011-04-19 08:36:26 +01008532 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008533 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008534 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008535
Rob Clark51fd3712013-11-19 12:10:12 -05008536 drm_modeset_acquire_init(ctx, 0);
8537
8538retry:
8539 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8540 if (ret)
8541 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008542
Jesse Barnes79e53942008-11-07 14:24:08 -08008543 /*
8544 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008545 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008546 * - if the connector already has an assigned crtc, use it (but make
8547 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008548 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008549 * - try to find the first unused crtc that can drive this connector,
8550 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008551 */
8552
8553 /* See if we already have a CRTC for this connector */
8554 if (encoder->crtc) {
8555 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008556
Rob Clark51fd3712013-11-19 12:10:12 -05008557 ret = drm_modeset_lock(&crtc->mutex, ctx);
8558 if (ret)
8559 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01008560
Daniel Vetter24218aa2012-08-12 19:27:11 +02008561 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008562 old->load_detect_temp = false;
8563
8564 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008565 if (connector->dpms != DRM_MODE_DPMS_ON)
8566 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008567
Chris Wilson71731882011-04-19 23:10:58 +01008568 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008569 }
8570
8571 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008572 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008573 i++;
8574 if (!(encoder->possible_crtcs & (1 << i)))
8575 continue;
8576 if (!possible_crtc->enabled) {
8577 crtc = possible_crtc;
8578 break;
8579 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008580 }
8581
8582 /*
8583 * If we didn't find an unused CRTC, don't use any.
8584 */
8585 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008586 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05008587 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08008588 }
8589
Rob Clark51fd3712013-11-19 12:10:12 -05008590 ret = drm_modeset_lock(&crtc->mutex, ctx);
8591 if (ret)
8592 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02008593 intel_encoder->new_crtc = to_intel_crtc(crtc);
8594 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008595
8596 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008597 intel_crtc->new_enabled = true;
8598 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008599 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008600 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008601 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008602
Chris Wilson64927112011-04-20 07:25:26 +01008603 if (!mode)
8604 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008605
Chris Wilsond2dff872011-04-19 08:36:26 +01008606 /* We need a framebuffer large enough to accommodate all accesses
8607 * that the plane may generate whilst we perform load detection.
8608 * We can not rely on the fbcon either being present (we get called
8609 * during its initialisation to detect all boot displays, or it may
8610 * not even exist) or that it is large enough to satisfy the
8611 * requested mode.
8612 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008613 fb = mode_fits_in_fbdev(dev, mode);
8614 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008615 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008616 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8617 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008618 } else
8619 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008620 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008621 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008622 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008623 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008624
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008625 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008626 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008627 if (old->release_fb)
8628 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008629 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008630 }
Chris Wilson71731882011-04-19 23:10:58 +01008631
Jesse Barnes79e53942008-11-07 14:24:08 -08008632 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008633 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008634 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008635
8636 fail:
8637 intel_crtc->new_enabled = crtc->enabled;
8638 if (intel_crtc->new_enabled)
8639 intel_crtc->new_config = &intel_crtc->config;
8640 else
8641 intel_crtc->new_config = NULL;
Rob Clark51fd3712013-11-19 12:10:12 -05008642fail_unlock:
8643 if (ret == -EDEADLK) {
8644 drm_modeset_backoff(ctx);
8645 goto retry;
8646 }
8647
8648 drm_modeset_drop_locks(ctx);
8649 drm_modeset_acquire_fini(ctx);
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008650
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008651 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008652}
8653
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008654void intel_release_load_detect_pipe(struct drm_connector *connector,
Rob Clark51fd3712013-11-19 12:10:12 -05008655 struct intel_load_detect_pipe *old,
8656 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008657{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008658 struct intel_encoder *intel_encoder =
8659 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008660 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008661 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008663
Chris Wilsond2dff872011-04-19 08:36:26 +01008664 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008665 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008666 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008667
Chris Wilson8261b192011-04-19 23:18:09 +01008668 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008669 to_intel_connector(connector)->new_encoder = NULL;
8670 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008671 intel_crtc->new_enabled = false;
8672 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008673 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008674
Daniel Vetter36206362012-12-10 20:42:17 +01008675 if (old->release_fb) {
8676 drm_framebuffer_unregister_private(old->release_fb);
8677 drm_framebuffer_unreference(old->release_fb);
8678 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008679
Rob Clark51fd3712013-11-19 12:10:12 -05008680 goto unlock;
Chris Wilson0622a532011-04-21 09:32:11 +01008681 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008682 }
8683
Eric Anholtc751ce42010-03-25 11:48:48 -07008684 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008685 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8686 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01008687
Rob Clark51fd3712013-11-19 12:10:12 -05008688unlock:
8689 drm_modeset_drop_locks(ctx);
8690 drm_modeset_acquire_fini(ctx);
Jesse Barnes79e53942008-11-07 14:24:08 -08008691}
8692
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008693static int i9xx_pll_refclk(struct drm_device *dev,
8694 const struct intel_crtc_config *pipe_config)
8695{
8696 struct drm_i915_private *dev_priv = dev->dev_private;
8697 u32 dpll = pipe_config->dpll_hw_state.dpll;
8698
8699 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008700 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008701 else if (HAS_PCH_SPLIT(dev))
8702 return 120000;
8703 else if (!IS_GEN2(dev))
8704 return 96000;
8705 else
8706 return 48000;
8707}
8708
Jesse Barnes79e53942008-11-07 14:24:08 -08008709/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008710static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8711 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008712{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008713 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008714 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008715 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008716 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008717 u32 fp;
8718 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008719 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008720
8721 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008722 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008723 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008724 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008725
8726 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008727 if (IS_PINEVIEW(dev)) {
8728 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8729 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008730 } else {
8731 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8732 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8733 }
8734
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008735 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008736 if (IS_PINEVIEW(dev))
8737 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8738 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008739 else
8740 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008741 DPLL_FPA01_P1_POST_DIV_SHIFT);
8742
8743 switch (dpll & DPLL_MODE_MASK) {
8744 case DPLLB_MODE_DAC_SERIAL:
8745 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8746 5 : 10;
8747 break;
8748 case DPLLB_MODE_LVDS:
8749 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8750 7 : 14;
8751 break;
8752 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008753 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008754 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008755 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008756 }
8757
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008758 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008759 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008760 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008761 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008762 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008763 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008764 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008765
8766 if (is_lvds) {
8767 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8768 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008769
8770 if (lvds & LVDS_CLKB_POWER_UP)
8771 clock.p2 = 7;
8772 else
8773 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008774 } else {
8775 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8776 clock.p1 = 2;
8777 else {
8778 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8779 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8780 }
8781 if (dpll & PLL_P2_DIVIDE_BY_4)
8782 clock.p2 = 4;
8783 else
8784 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008785 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008786
8787 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008788 }
8789
Ville Syrjälä18442d02013-09-13 16:00:08 +03008790 /*
8791 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008792 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008793 * encoder's get_config() function.
8794 */
8795 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008796}
8797
Ville Syrjälä6878da02013-09-13 15:59:11 +03008798int intel_dotclock_calculate(int link_freq,
8799 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008800{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008801 /*
8802 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008803 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008804 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008805 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008806 *
8807 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008808 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008809 */
8810
Ville Syrjälä6878da02013-09-13 15:59:11 +03008811 if (!m_n->link_n)
8812 return 0;
8813
8814 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8815}
8816
Ville Syrjälä18442d02013-09-13 16:00:08 +03008817static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8818 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008819{
8820 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008821
8822 /* read out port_clock from the DPLL */
8823 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008824
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008825 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008826 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008827 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008828 * agree once we know their relationship in the encoder's
8829 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008830 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008831 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008832 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8833 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008834}
8835
8836/** Returns the currently programmed mode of the given pipe. */
8837struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8838 struct drm_crtc *crtc)
8839{
Jesse Barnes548f2452011-02-17 10:40:53 -08008840 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008842 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008843 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008844 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008845 int htot = I915_READ(HTOTAL(cpu_transcoder));
8846 int hsync = I915_READ(HSYNC(cpu_transcoder));
8847 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8848 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008849 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008850
8851 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8852 if (!mode)
8853 return NULL;
8854
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008855 /*
8856 * Construct a pipe_config sufficient for getting the clock info
8857 * back out of crtc_clock_get.
8858 *
8859 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8860 * to use a real value here instead.
8861 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008862 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008863 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008864 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8865 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8866 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008867 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8868
Ville Syrjälä773ae032013-09-23 17:48:20 +03008869 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008870 mode->hdisplay = (htot & 0xffff) + 1;
8871 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8872 mode->hsync_start = (hsync & 0xffff) + 1;
8873 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8874 mode->vdisplay = (vtot & 0xffff) + 1;
8875 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8876 mode->vsync_start = (vsync & 0xffff) + 1;
8877 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8878
8879 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008880
8881 return mode;
8882}
8883
Daniel Vettercc365132014-06-18 13:59:13 +02008884static void intel_increase_pllclock(struct drm_device *dev,
8885 enum pipe pipe)
Jesse Barnes652c3932009-08-17 13:31:43 -07008886{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008887 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008888 int dpll_reg = DPLL(pipe);
8889 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07008890
Sonika Jindalbaff2962014-07-22 11:16:35 +05308891 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008892 return;
8893
8894 if (!dev_priv->lvds_downclock_avail)
8895 return;
8896
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008897 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008898 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08008899 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008900
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008901 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008902
8903 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8904 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008905 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008906
Jesse Barnes652c3932009-08-17 13:31:43 -07008907 dpll = I915_READ(dpll_reg);
8908 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08008909 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008910 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008911}
8912
8913static void intel_decrease_pllclock(struct drm_crtc *crtc)
8914{
8915 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008916 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008918
Sonika Jindalbaff2962014-07-22 11:16:35 +05308919 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008920 return;
8921
8922 if (!dev_priv->lvds_downclock_avail)
8923 return;
8924
8925 /*
8926 * Since this is called by a timer, we should never get here in
8927 * the manual case.
8928 */
8929 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008930 int pipe = intel_crtc->pipe;
8931 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008932 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008933
Zhao Yakui44d98a62009-10-09 11:39:40 +08008934 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008935
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008936 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008937
Chris Wilson074b5e12012-05-02 12:07:06 +01008938 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008939 dpll |= DISPLAY_RATE_SELECT_FPA1;
8940 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008941 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008942 dpll = I915_READ(dpll_reg);
8943 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008944 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008945 }
8946
8947}
8948
Chris Wilsonf047e392012-07-21 12:31:41 +01008949void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008950{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008951 struct drm_i915_private *dev_priv = dev->dev_private;
8952
Chris Wilsonf62a0072014-02-21 17:55:39 +00008953 if (dev_priv->mm.busy)
8954 return;
8955
Paulo Zanoni43694d62014-03-07 20:08:08 -03008956 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008957 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008958 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008959}
8960
8961void intel_mark_idle(struct drm_device *dev)
8962{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008963 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008964 struct drm_crtc *crtc;
8965
Chris Wilsonf62a0072014-02-21 17:55:39 +00008966 if (!dev_priv->mm.busy)
8967 return;
8968
8969 dev_priv->mm.busy = false;
8970
Jani Nikulad330a952014-01-21 11:24:25 +02008971 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008972 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008973
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008974 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008975 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008976 continue;
8977
8978 intel_decrease_pllclock(crtc);
8979 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008980
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008981 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008982 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008983
8984out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03008985 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008986}
8987
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07008988
Daniel Vetterf99d7062014-06-19 16:01:59 +02008989/**
8990 * intel_mark_fb_busy - mark given planes as busy
8991 * @dev: DRM device
8992 * @frontbuffer_bits: bits for the affected planes
8993 * @ring: optional ring for asynchronous commands
8994 *
8995 * This function gets called every time the screen contents change. It can be
8996 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8997 */
8998static void intel_mark_fb_busy(struct drm_device *dev,
8999 unsigned frontbuffer_bits,
9000 struct intel_engine_cs *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01009001{
Daniel Vettercc365132014-06-18 13:59:13 +02009002 enum pipe pipe;
Jesse Barnes652c3932009-08-17 13:31:43 -07009003
Jani Nikulad330a952014-01-21 11:24:25 +02009004 if (!i915.powersave)
Jesse Barnes652c3932009-08-17 13:31:43 -07009005 return;
9006
Daniel Vettercc365132014-06-18 13:59:13 +02009007 for_each_pipe(pipe) {
Daniel Vetterf99d7062014-06-19 16:01:59 +02009008 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
Jesse Barnes652c3932009-08-17 13:31:43 -07009009 continue;
9010
Daniel Vettercc365132014-06-18 13:59:13 +02009011 intel_increase_pllclock(dev, pipe);
Chris Wilsonc65355b2013-06-06 16:53:41 -03009012 if (ring && intel_fbc_enabled(dev))
9013 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07009014 }
Jesse Barnes652c3932009-08-17 13:31:43 -07009015}
9016
Daniel Vetterf99d7062014-06-19 16:01:59 +02009017/**
9018 * intel_fb_obj_invalidate - invalidate frontbuffer object
9019 * @obj: GEM object to invalidate
9020 * @ring: set for asynchronous rendering
9021 *
9022 * This function gets called every time rendering on the given object starts and
9023 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9024 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9025 * until the rendering completes or a flip on this frontbuffer plane is
9026 * scheduled.
9027 */
9028void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9029 struct intel_engine_cs *ring)
9030{
9031 struct drm_device *dev = obj->base.dev;
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033
9034 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9035
9036 if (!obj->frontbuffer_bits)
9037 return;
9038
9039 if (ring) {
9040 mutex_lock(&dev_priv->fb_tracking.lock);
9041 dev_priv->fb_tracking.busy_bits
9042 |= obj->frontbuffer_bits;
9043 dev_priv->fb_tracking.flip_bits
9044 &= ~obj->frontbuffer_bits;
9045 mutex_unlock(&dev_priv->fb_tracking.lock);
9046 }
9047
9048 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9049
Daniel Vetter9ca15302014-07-11 10:30:16 -07009050 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009051}
9052
9053/**
9054 * intel_frontbuffer_flush - flush frontbuffer
9055 * @dev: DRM device
9056 * @frontbuffer_bits: frontbuffer plane tracking bits
9057 *
9058 * This function gets called every time rendering on the given planes has
9059 * completed and frontbuffer caching can be started again. Flushes will get
9060 * delayed if they're blocked by some oustanding asynchronous rendering.
9061 *
9062 * Can be called without any locks held.
9063 */
9064void intel_frontbuffer_flush(struct drm_device *dev,
9065 unsigned frontbuffer_bits)
9066{
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068
9069 /* Delay flushing when rings are still busy.*/
9070 mutex_lock(&dev_priv->fb_tracking.lock);
9071 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9072 mutex_unlock(&dev_priv->fb_tracking.lock);
9073
9074 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9075
Daniel Vetter9ca15302014-07-11 10:30:16 -07009076 intel_edp_psr_flush(dev, frontbuffer_bits);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009077}
9078
9079/**
9080 * intel_fb_obj_flush - flush frontbuffer object
9081 * @obj: GEM object to flush
9082 * @retire: set when retiring asynchronous rendering
9083 *
9084 * This function gets called every time rendering on the given object has
9085 * completed and frontbuffer caching can be started again. If @retire is true
9086 * then any delayed flushes will be unblocked.
9087 */
9088void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9089 bool retire)
9090{
9091 struct drm_device *dev = obj->base.dev;
9092 struct drm_i915_private *dev_priv = dev->dev_private;
9093 unsigned frontbuffer_bits;
9094
9095 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9096
9097 if (!obj->frontbuffer_bits)
9098 return;
9099
9100 frontbuffer_bits = obj->frontbuffer_bits;
9101
9102 if (retire) {
9103 mutex_lock(&dev_priv->fb_tracking.lock);
9104 /* Filter out new bits since rendering started. */
9105 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9106
9107 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9108 mutex_unlock(&dev_priv->fb_tracking.lock);
9109 }
9110
9111 intel_frontbuffer_flush(dev, frontbuffer_bits);
9112}
9113
9114/**
9115 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9116 * @dev: DRM device
9117 * @frontbuffer_bits: frontbuffer plane tracking bits
9118 *
9119 * This function gets called after scheduling a flip on @obj. The actual
9120 * frontbuffer flushing will be delayed until completion is signalled with
9121 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9122 * flush will be cancelled.
9123 *
9124 * Can be called without any locks held.
9125 */
9126void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9127 unsigned frontbuffer_bits)
9128{
9129 struct drm_i915_private *dev_priv = dev->dev_private;
9130
9131 mutex_lock(&dev_priv->fb_tracking.lock);
9132 dev_priv->fb_tracking.flip_bits
9133 |= frontbuffer_bits;
9134 mutex_unlock(&dev_priv->fb_tracking.lock);
9135}
9136
9137/**
9138 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9139 * @dev: DRM device
9140 * @frontbuffer_bits: frontbuffer plane tracking bits
9141 *
9142 * This function gets called after the flip has been latched and will complete
9143 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9144 *
9145 * Can be called without any locks held.
9146 */
9147void intel_frontbuffer_flip_complete(struct drm_device *dev,
9148 unsigned frontbuffer_bits)
9149{
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9151
9152 mutex_lock(&dev_priv->fb_tracking.lock);
9153 /* Mask any cancelled flips. */
9154 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9155 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9156 mutex_unlock(&dev_priv->fb_tracking.lock);
9157
9158 intel_frontbuffer_flush(dev, frontbuffer_bits);
9159}
9160
Jesse Barnes79e53942008-11-07 14:24:08 -08009161static void intel_crtc_destroy(struct drm_crtc *crtc)
9162{
9163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009164 struct drm_device *dev = crtc->dev;
9165 struct intel_unpin_work *work;
9166 unsigned long flags;
9167
9168 spin_lock_irqsave(&dev->event_lock, flags);
9169 work = intel_crtc->unpin_work;
9170 intel_crtc->unpin_work = NULL;
9171 spin_unlock_irqrestore(&dev->event_lock, flags);
9172
9173 if (work) {
9174 cancel_work_sync(&work->work);
9175 kfree(work);
9176 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009177
9178 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009179
Jesse Barnes79e53942008-11-07 14:24:08 -08009180 kfree(intel_crtc);
9181}
9182
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009183static void intel_unpin_work_fn(struct work_struct *__work)
9184{
9185 struct intel_unpin_work *work =
9186 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009187 struct drm_device *dev = work->crtc->dev;
Daniel Vetterf99d7062014-06-19 16:01:59 +02009188 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009189
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009190 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01009191 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00009192 drm_gem_object_unreference(&work->pending_flip_obj->base);
9193 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00009194
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009195 intel_update_fbc(dev);
9196 mutex_unlock(&dev->struct_mutex);
9197
Daniel Vetterf99d7062014-06-19 16:01:59 +02009198 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9199
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009200 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9201 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9202
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009203 kfree(work);
9204}
9205
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009206static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01009207 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009208{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009209 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9211 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009212 unsigned long flags;
9213
9214 /* Ignore early vblank irqs */
9215 if (intel_crtc == NULL)
9216 return;
9217
9218 spin_lock_irqsave(&dev->event_lock, flags);
9219 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00009220
9221 /* Ensure we don't miss a work->pending update ... */
9222 smp_rmb();
9223
9224 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009225 spin_unlock_irqrestore(&dev->event_lock, flags);
9226 return;
9227 }
9228
Chris Wilsone7d841c2012-12-03 11:36:30 +00009229 /* and that the unpin work is consistent wrt ->pending. */
9230 smp_rmb();
9231
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009232 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009233
Rob Clark45a066e2012-10-08 14:50:40 -05009234 if (work->event)
9235 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009236
Daniel Vetter87b6b102014-05-15 15:33:46 +02009237 drm_crtc_vblank_put(crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01009238
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009239 spin_unlock_irqrestore(&dev->event_lock, flags);
9240
Daniel Vetter2c10d572012-12-20 21:24:07 +01009241 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009242
9243 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07009244
9245 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009246}
9247
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009248void intel_finish_page_flip(struct drm_device *dev, int pipe)
9249{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009250 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009251 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9252
Mario Kleiner49b14a52010-12-09 07:00:07 +01009253 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009254}
9255
9256void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9257{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009258 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009259 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9260
Mario Kleiner49b14a52010-12-09 07:00:07 +01009261 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009262}
9263
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009264/* Is 'a' after or equal to 'b'? */
9265static bool g4x_flip_count_after_eq(u32 a, u32 b)
9266{
9267 return !((a - b) & 0x80000000);
9268}
9269
9270static bool page_flip_finished(struct intel_crtc *crtc)
9271{
9272 struct drm_device *dev = crtc->base.dev;
9273 struct drm_i915_private *dev_priv = dev->dev_private;
9274
9275 /*
9276 * The relevant registers doen't exist on pre-ctg.
9277 * As the flip done interrupt doesn't trigger for mmio
9278 * flips on gmch platforms, a flip count check isn't
9279 * really needed there. But since ctg has the registers,
9280 * include it in the check anyway.
9281 */
9282 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9283 return true;
9284
9285 /*
9286 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9287 * used the same base address. In that case the mmio flip might
9288 * have completed, but the CS hasn't even executed the flip yet.
9289 *
9290 * A flip count check isn't enough as the CS might have updated
9291 * the base address just after start of vblank, but before we
9292 * managed to process the interrupt. This means we'd complete the
9293 * CS flip too soon.
9294 *
9295 * Combining both checks should get us a good enough result. It may
9296 * still happen that the CS flip has been executed, but has not
9297 * yet actually completed. But in case the base address is the same
9298 * anyway, we don't really care.
9299 */
9300 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9301 crtc->unpin_work->gtt_offset &&
9302 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9303 crtc->unpin_work->flip_count);
9304}
9305
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009306void intel_prepare_page_flip(struct drm_device *dev, int plane)
9307{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009308 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009309 struct intel_crtc *intel_crtc =
9310 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9311 unsigned long flags;
9312
Chris Wilsone7d841c2012-12-03 11:36:30 +00009313 /* NB: An MMIO update of the plane base pointer will also
9314 * generate a page-flip completion irq, i.e. every modeset
9315 * is also accompanied by a spurious intel_prepare_page_flip().
9316 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009317 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009318 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00009319 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009320 spin_unlock_irqrestore(&dev->event_lock, flags);
9321}
9322
Robin Schroereba905b2014-05-18 02:24:50 +02009323static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00009324{
9325 /* Ensure that the work item is consistent when activating it ... */
9326 smp_wmb();
9327 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9328 /* and that it is marked active as soon as the irq could fire. */
9329 smp_wmb();
9330}
9331
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009332static int intel_gen2_queue_flip(struct drm_device *dev,
9333 struct drm_crtc *crtc,
9334 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009335 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009336 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009337 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009338{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009340 u32 flip_mask;
9341 int ret;
9342
Daniel Vetter6d90c952012-04-26 23:28:05 +02009343 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009344 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009345 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009346
9347 /* Can't queue multiple flips, so wait for the previous
9348 * one to finish before executing the next.
9349 */
9350 if (intel_crtc->plane)
9351 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9352 else
9353 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009354 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9355 intel_ring_emit(ring, MI_NOOP);
9356 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9357 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9358 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009359 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009360 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00009361
9362 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009363 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009364 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009365}
9366
9367static int intel_gen3_queue_flip(struct drm_device *dev,
9368 struct drm_crtc *crtc,
9369 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009370 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009371 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009372 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009373{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009375 u32 flip_mask;
9376 int ret;
9377
Daniel Vetter6d90c952012-04-26 23:28:05 +02009378 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009379 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009380 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009381
9382 if (intel_crtc->plane)
9383 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9384 else
9385 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009386 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9387 intel_ring_emit(ring, MI_NOOP);
9388 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9389 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9390 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009391 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009392 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009393
Chris Wilsone7d841c2012-12-03 11:36:30 +00009394 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009395 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009396 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009397}
9398
9399static int intel_gen4_queue_flip(struct drm_device *dev,
9400 struct drm_crtc *crtc,
9401 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009402 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009403 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009404 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009405{
9406 struct drm_i915_private *dev_priv = dev->dev_private;
9407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9408 uint32_t pf, pipesrc;
9409 int ret;
9410
Daniel Vetter6d90c952012-04-26 23:28:05 +02009411 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009412 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009413 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009414
9415 /* i965+ uses the linear or tiled offsets from the
9416 * Display Registers (which do not change across a page-flip)
9417 * so we need only reprogram the base address.
9418 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009419 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9420 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9421 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009422 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009423 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009424
9425 /* XXX Enabling the panel-fitter across page-flip is so far
9426 * untested on non-native modes, so ignore it for now.
9427 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9428 */
9429 pf = 0;
9430 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009431 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009432
9433 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009434 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009435 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009436}
9437
9438static int intel_gen6_queue_flip(struct drm_device *dev,
9439 struct drm_crtc *crtc,
9440 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009441 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009442 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009443 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009444{
9445 struct drm_i915_private *dev_priv = dev->dev_private;
9446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9447 uint32_t pf, pipesrc;
9448 int ret;
9449
Daniel Vetter6d90c952012-04-26 23:28:05 +02009450 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009451 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009452 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009453
Daniel Vetter6d90c952012-04-26 23:28:05 +02009454 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9455 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9456 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009457 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009458
Chris Wilson99d9acd2012-04-17 20:37:00 +01009459 /* Contrary to the suggestions in the documentation,
9460 * "Enable Panel Fitter" does not seem to be required when page
9461 * flipping with a non-native mode, and worse causes a normal
9462 * modeset to fail.
9463 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9464 */
9465 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009466 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009467 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009468
9469 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009470 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009471 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009472}
9473
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009474static int intel_gen7_queue_flip(struct drm_device *dev,
9475 struct drm_crtc *crtc,
9476 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009477 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009478 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009479 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009480{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009482 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009483 int len, ret;
9484
Robin Schroereba905b2014-05-18 02:24:50 +02009485 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009486 case PLANE_A:
9487 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9488 break;
9489 case PLANE_B:
9490 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9491 break;
9492 case PLANE_C:
9493 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9494 break;
9495 default:
9496 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009497 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009498 }
9499
Chris Wilsonffe74d72013-08-26 20:58:12 +01009500 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009501 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009502 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009503 /*
9504 * On Gen 8, SRM is now taking an extra dword to accommodate
9505 * 48bits addresses, and we need a NOOP for the batch size to
9506 * stay even.
9507 */
9508 if (IS_GEN8(dev))
9509 len += 2;
9510 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009511
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009512 /*
9513 * BSpec MI_DISPLAY_FLIP for IVB:
9514 * "The full packet must be contained within the same cache line."
9515 *
9516 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9517 * cacheline, if we ever start emitting more commands before
9518 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9519 * then do the cacheline alignment, and finally emit the
9520 * MI_DISPLAY_FLIP.
9521 */
9522 ret = intel_ring_cacheline_align(ring);
9523 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009524 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009525
Chris Wilsonffe74d72013-08-26 20:58:12 +01009526 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009527 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009528 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009529
Chris Wilsonffe74d72013-08-26 20:58:12 +01009530 /* Unmask the flip-done completion message. Note that the bspec says that
9531 * we should do this for both the BCS and RCS, and that we must not unmask
9532 * more than one flip event at any time (or ensure that one flip message
9533 * can be sent by waiting for flip-done prior to queueing new flips).
9534 * Experimentation says that BCS works despite DERRMR masking all
9535 * flip-done completion events and that unmasking all planes at once
9536 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9537 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9538 */
9539 if (ring->id == RCS) {
9540 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9541 intel_ring_emit(ring, DERRMR);
9542 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9543 DERRMR_PIPEB_PRI_FLIP_DONE |
9544 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009545 if (IS_GEN8(dev))
9546 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9547 MI_SRM_LRM_GLOBAL_GTT);
9548 else
9549 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9550 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009551 intel_ring_emit(ring, DERRMR);
9552 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009553 if (IS_GEN8(dev)) {
9554 intel_ring_emit(ring, 0);
9555 intel_ring_emit(ring, MI_NOOP);
9556 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009557 }
9558
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009559 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009560 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009561 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009562 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009563
9564 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009565 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009566 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009567}
9568
Sourab Gupta84c33a62014-06-02 16:47:17 +05309569static bool use_mmio_flip(struct intel_engine_cs *ring,
9570 struct drm_i915_gem_object *obj)
9571{
9572 /*
9573 * This is not being used for older platforms, because
9574 * non-availability of flip done interrupt forces us to use
9575 * CS flips. Older platforms derive flip done using some clever
9576 * tricks involving the flip_pending status bits and vblank irqs.
9577 * So using MMIO flips there would disrupt this mechanism.
9578 */
9579
Chris Wilson8e09bf82014-07-08 10:40:30 +01009580 if (ring == NULL)
9581 return true;
9582
Sourab Gupta84c33a62014-06-02 16:47:17 +05309583 if (INTEL_INFO(ring->dev)->gen < 5)
9584 return false;
9585
9586 if (i915.use_mmio_flip < 0)
9587 return false;
9588 else if (i915.use_mmio_flip > 0)
9589 return true;
9590 else
9591 return ring != obj->ring;
9592}
9593
9594static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9595{
9596 struct drm_device *dev = intel_crtc->base.dev;
9597 struct drm_i915_private *dev_priv = dev->dev_private;
9598 struct intel_framebuffer *intel_fb =
9599 to_intel_framebuffer(intel_crtc->base.primary->fb);
9600 struct drm_i915_gem_object *obj = intel_fb->obj;
9601 u32 dspcntr;
9602 u32 reg;
9603
9604 intel_mark_page_flip_active(intel_crtc);
9605
9606 reg = DSPCNTR(intel_crtc->plane);
9607 dspcntr = I915_READ(reg);
9608
9609 if (INTEL_INFO(dev)->gen >= 4) {
9610 if (obj->tiling_mode != I915_TILING_NONE)
9611 dspcntr |= DISPPLANE_TILED;
9612 else
9613 dspcntr &= ~DISPPLANE_TILED;
9614 }
9615 I915_WRITE(reg, dspcntr);
9616
9617 I915_WRITE(DSPSURF(intel_crtc->plane),
9618 intel_crtc->unpin_work->gtt_offset);
9619 POSTING_READ(DSPSURF(intel_crtc->plane));
9620}
9621
9622static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9623{
9624 struct intel_engine_cs *ring;
9625 int ret;
9626
9627 lockdep_assert_held(&obj->base.dev->struct_mutex);
9628
9629 if (!obj->last_write_seqno)
9630 return 0;
9631
9632 ring = obj->ring;
9633
9634 if (i915_seqno_passed(ring->get_seqno(ring, true),
9635 obj->last_write_seqno))
9636 return 0;
9637
9638 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9639 if (ret)
9640 return ret;
9641
9642 if (WARN_ON(!ring->irq_get(ring)))
9643 return 0;
9644
9645 return 1;
9646}
9647
9648void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9649{
9650 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9651 struct intel_crtc *intel_crtc;
9652 unsigned long irq_flags;
9653 u32 seqno;
9654
9655 seqno = ring->get_seqno(ring, false);
9656
9657 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9658 for_each_intel_crtc(ring->dev, intel_crtc) {
9659 struct intel_mmio_flip *mmio_flip;
9660
9661 mmio_flip = &intel_crtc->mmio_flip;
9662 if (mmio_flip->seqno == 0)
9663 continue;
9664
9665 if (ring->id != mmio_flip->ring_id)
9666 continue;
9667
9668 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9669 intel_do_mmio_flip(intel_crtc);
9670 mmio_flip->seqno = 0;
9671 ring->irq_put(ring);
9672 }
9673 }
9674 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9675}
9676
9677static int intel_queue_mmio_flip(struct drm_device *dev,
9678 struct drm_crtc *crtc,
9679 struct drm_framebuffer *fb,
9680 struct drm_i915_gem_object *obj,
9681 struct intel_engine_cs *ring,
9682 uint32_t flags)
9683{
9684 struct drm_i915_private *dev_priv = dev->dev_private;
9685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9686 unsigned long irq_flags;
9687 int ret;
9688
9689 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9690 return -EBUSY;
9691
9692 ret = intel_postpone_flip(obj);
9693 if (ret < 0)
9694 return ret;
9695 if (ret == 0) {
9696 intel_do_mmio_flip(intel_crtc);
9697 return 0;
9698 }
9699
9700 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9701 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9702 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9703 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9704
9705 /*
9706 * Double check to catch cases where irq fired before
9707 * mmio flip data was ready
9708 */
9709 intel_notify_mmio_flip(obj->ring);
9710 return 0;
9711}
9712
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009713static int intel_default_queue_flip(struct drm_device *dev,
9714 struct drm_crtc *crtc,
9715 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009716 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009717 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009718 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009719{
9720 return -ENODEV;
9721}
9722
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009723static int intel_crtc_page_flip(struct drm_crtc *crtc,
9724 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009725 struct drm_pending_vblank_event *event,
9726 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009727{
9728 struct drm_device *dev = crtc->dev;
9729 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009730 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009731 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02009733 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009734 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009735 struct intel_engine_cs *ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009736 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01009737 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009738
Matt Roper2ff8fde2014-07-08 07:50:07 -07009739 /*
9740 * drm_mode_page_flip_ioctl() should already catch this, but double
9741 * check to be safe. In the future we may enable pageflipping from
9742 * a disabled primary plane.
9743 */
9744 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9745 return -EBUSY;
9746
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009747 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009748 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009749 return -EINVAL;
9750
9751 /*
9752 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9753 * Note that pitch changes could also affect these register.
9754 */
9755 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009756 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9757 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009758 return -EINVAL;
9759
Chris Wilsonf900db42014-02-20 09:26:13 +00009760 if (i915_terminally_wedged(&dev_priv->gpu_error))
9761 goto out_hang;
9762
Daniel Vetterb14c5672013-09-19 12:18:32 +02009763 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009764 if (work == NULL)
9765 return -ENOMEM;
9766
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009767 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009768 work->crtc = crtc;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009769 work->old_fb_obj = intel_fb_obj(old_fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009770 INIT_WORK(&work->work, intel_unpin_work_fn);
9771
Daniel Vetter87b6b102014-05-15 15:33:46 +02009772 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009773 if (ret)
9774 goto free_work;
9775
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009776 /* We borrow the event spin lock for protecting unpin_work */
9777 spin_lock_irqsave(&dev->event_lock, flags);
9778 if (intel_crtc->unpin_work) {
9779 spin_unlock_irqrestore(&dev->event_lock, flags);
9780 kfree(work);
Daniel Vetter87b6b102014-05-15 15:33:46 +02009781 drm_crtc_vblank_put(crtc);
Chris Wilson468f0b42010-05-27 13:18:13 +01009782
9783 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009784 return -EBUSY;
9785 }
9786 intel_crtc->unpin_work = work;
9787 spin_unlock_irqrestore(&dev->event_lock, flags);
9788
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009789 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9790 flush_workqueue(dev_priv->wq);
9791
Chris Wilson79158102012-05-23 11:13:58 +01009792 ret = i915_mutex_lock_interruptible(dev);
9793 if (ret)
9794 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009795
Jesse Barnes75dfca82010-02-10 15:09:44 -08009796 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009797 drm_gem_object_reference(&work->old_fb_obj->base);
9798 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009799
Matt Roperf4510a22014-04-01 15:22:40 -07009800 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009801
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009802 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009803
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01009804 work->enable_stall_check = true;
9805
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009806 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009807 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009808
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009809 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Daniel Vettera071fa02014-06-18 23:28:09 +02009810 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009811
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009812 if (IS_VALLEYVIEW(dev)) {
9813 ring = &dev_priv->ring[BCS];
Chris Wilson8e09bf82014-07-08 10:40:30 +01009814 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9815 /* vlv: DISPLAY_FLIP fails to change tiling */
9816 ring = NULL;
Chris Wilson2a92d5b2014-07-08 10:40:29 +01009817 } else if (IS_IVYBRIDGE(dev)) {
9818 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009819 } else if (INTEL_INFO(dev)->gen >= 7) {
9820 ring = obj->ring;
9821 if (ring == NULL || ring->id != RCS)
9822 ring = &dev_priv->ring[BCS];
9823 } else {
9824 ring = &dev_priv->ring[RCS];
9825 }
9826
9827 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009828 if (ret)
9829 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009830
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009831 work->gtt_offset =
9832 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9833
Sourab Gupta84c33a62014-06-02 16:47:17 +05309834 if (use_mmio_flip(ring, obj))
9835 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9836 page_flip_flags);
9837 else
9838 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9839 page_flip_flags);
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009840 if (ret)
9841 goto cleanup_unpin;
9842
Daniel Vettera071fa02014-06-18 23:28:09 +02009843 i915_gem_track_fb(work->old_fb_obj, obj,
9844 INTEL_FRONTBUFFER_PRIMARY(pipe));
9845
Chris Wilson7782de32011-07-08 12:22:41 +01009846 intel_disable_fbc(dev);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009847 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009848 mutex_unlock(&dev->struct_mutex);
9849
Jesse Barnese5510fa2010-07-01 16:48:37 -07009850 trace_i915_flip_request(intel_crtc->plane, obj);
9851
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009852 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009853
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009854cleanup_unpin:
9855 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009856cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009857 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009858 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009859 drm_gem_object_unreference(&work->old_fb_obj->base);
9860 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009861 mutex_unlock(&dev->struct_mutex);
9862
Chris Wilson79158102012-05-23 11:13:58 +01009863cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01009864 spin_lock_irqsave(&dev->event_lock, flags);
9865 intel_crtc->unpin_work = NULL;
9866 spin_unlock_irqrestore(&dev->event_lock, flags);
9867
Daniel Vetter87b6b102014-05-15 15:33:46 +02009868 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009869free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009870 kfree(work);
9871
Chris Wilsonf900db42014-02-20 09:26:13 +00009872 if (ret == -EIO) {
9873out_hang:
9874 intel_crtc_wait_for_pending_flips(crtc);
9875 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9876 if (ret == 0 && event)
Daniel Vettera071fa02014-06-18 23:28:09 +02009877 drm_send_vblank_event(dev, pipe, event);
Chris Wilsonf900db42014-02-20 09:26:13 +00009878 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009879 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009880}
9881
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009882static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009883 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9884 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009885};
9886
Daniel Vetter9a935852012-07-05 22:34:27 +02009887/**
9888 * intel_modeset_update_staged_output_state
9889 *
9890 * Updates the staged output configuration state, e.g. after we've read out the
9891 * current hw state.
9892 */
9893static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9894{
Ville Syrjälä76688512014-01-10 11:28:06 +02009895 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009896 struct intel_encoder *encoder;
9897 struct intel_connector *connector;
9898
9899 list_for_each_entry(connector, &dev->mode_config.connector_list,
9900 base.head) {
9901 connector->new_encoder =
9902 to_intel_encoder(connector->base.encoder);
9903 }
9904
9905 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9906 base.head) {
9907 encoder->new_crtc =
9908 to_intel_crtc(encoder->base.crtc);
9909 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009910
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009911 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009912 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009913
9914 if (crtc->new_enabled)
9915 crtc->new_config = &crtc->config;
9916 else
9917 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009918 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009919}
9920
9921/**
9922 * intel_modeset_commit_output_state
9923 *
9924 * This function copies the stage display pipe configuration to the real one.
9925 */
9926static void intel_modeset_commit_output_state(struct drm_device *dev)
9927{
Ville Syrjälä76688512014-01-10 11:28:06 +02009928 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009929 struct intel_encoder *encoder;
9930 struct intel_connector *connector;
9931
9932 list_for_each_entry(connector, &dev->mode_config.connector_list,
9933 base.head) {
9934 connector->base.encoder = &connector->new_encoder->base;
9935 }
9936
9937 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9938 base.head) {
9939 encoder->base.crtc = &encoder->new_crtc->base;
9940 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009941
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009942 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009943 crtc->base.enabled = crtc->new_enabled;
9944 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009945}
9946
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009947static void
Robin Schroereba905b2014-05-18 02:24:50 +02009948connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009949 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009950{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009951 int bpp = pipe_config->pipe_bpp;
9952
9953 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9954 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009955 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009956
9957 /* Don't use an invalid EDID bpc value */
9958 if (connector->base.display_info.bpc &&
9959 connector->base.display_info.bpc * 3 < bpp) {
9960 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9961 bpp, connector->base.display_info.bpc*3);
9962 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9963 }
9964
9965 /* Clamp bpp to 8 on screens without EDID 1.4 */
9966 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9967 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9968 bpp);
9969 pipe_config->pipe_bpp = 24;
9970 }
9971}
9972
9973static int
9974compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9975 struct drm_framebuffer *fb,
9976 struct intel_crtc_config *pipe_config)
9977{
9978 struct drm_device *dev = crtc->base.dev;
9979 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009980 int bpp;
9981
Daniel Vetterd42264b2013-03-28 16:38:08 +01009982 switch (fb->pixel_format) {
9983 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009984 bpp = 8*3; /* since we go through a colormap */
9985 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009986 case DRM_FORMAT_XRGB1555:
9987 case DRM_FORMAT_ARGB1555:
9988 /* checked in intel_framebuffer_init already */
9989 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9990 return -EINVAL;
9991 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009992 bpp = 6*3; /* min is 18bpp */
9993 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009994 case DRM_FORMAT_XBGR8888:
9995 case DRM_FORMAT_ABGR8888:
9996 /* checked in intel_framebuffer_init already */
9997 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9998 return -EINVAL;
9999 case DRM_FORMAT_XRGB8888:
10000 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010001 bpp = 8*3;
10002 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +010010003 case DRM_FORMAT_XRGB2101010:
10004 case DRM_FORMAT_ARGB2101010:
10005 case DRM_FORMAT_XBGR2101010:
10006 case DRM_FORMAT_ABGR2101010:
10007 /* checked in intel_framebuffer_init already */
10008 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +010010009 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010010 bpp = 10*3;
10011 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +010010012 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010013 default:
10014 DRM_DEBUG_KMS("unsupported depth\n");
10015 return -EINVAL;
10016 }
10017
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010018 pipe_config->pipe_bpp = bpp;
10019
10020 /* Clamp display bpp to EDID value */
10021 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010022 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +020010023 if (!connector->new_encoder ||
10024 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010025 continue;
10026
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010027 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010028 }
10029
10030 return bpp;
10031}
10032
Daniel Vetter644db712013-09-19 14:53:58 +020010033static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10034{
10035 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10036 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +010010037 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +020010038 mode->crtc_hdisplay, mode->crtc_hsync_start,
10039 mode->crtc_hsync_end, mode->crtc_htotal,
10040 mode->crtc_vdisplay, mode->crtc_vsync_start,
10041 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10042}
10043
Daniel Vetterc0b03412013-05-28 12:05:54 +020010044static void intel_dump_pipe_config(struct intel_crtc *crtc,
10045 struct intel_crtc_config *pipe_config,
10046 const char *context)
10047{
10048 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10049 context, pipe_name(crtc->pipe));
10050
10051 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10052 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10053 pipe_config->pipe_bpp, pipe_config->dither);
10054 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10055 pipe_config->has_pch_encoder,
10056 pipe_config->fdi_lanes,
10057 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10058 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10059 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010060 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10061 pipe_config->has_dp_encoder,
10062 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10063 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10064 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010065
10066 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10067 pipe_config->has_dp_encoder,
10068 pipe_config->dp_m2_n2.gmch_m,
10069 pipe_config->dp_m2_n2.gmch_n,
10070 pipe_config->dp_m2_n2.link_m,
10071 pipe_config->dp_m2_n2.link_n,
10072 pipe_config->dp_m2_n2.tu);
10073
Daniel Vetterc0b03412013-05-28 12:05:54 +020010074 DRM_DEBUG_KMS("requested mode:\n");
10075 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10076 DRM_DEBUG_KMS("adjusted mode:\n");
10077 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +020010078 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +030010079 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010080 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10081 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010082 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10083 pipe_config->gmch_pfit.control,
10084 pipe_config->gmch_pfit.pgm_ratios,
10085 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010086 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +020010087 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010088 pipe_config->pch_pfit.size,
10089 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010090 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +030010091 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010092}
10093
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010094static bool encoders_cloneable(const struct intel_encoder *a,
10095 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010096{
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010097 /* masks could be asymmetric, so check both ways */
10098 return a == b || (a->cloneable & (1 << b->type) &&
10099 b->cloneable & (1 << a->type));
10100}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010101
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010102static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10103 struct intel_encoder *encoder)
10104{
10105 struct drm_device *dev = crtc->base.dev;
10106 struct intel_encoder *source_encoder;
10107
10108 list_for_each_entry(source_encoder,
10109 &dev->mode_config.encoder_list, base.head) {
10110 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010111 continue;
10112
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010113 if (!encoders_cloneable(encoder, source_encoder))
10114 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010115 }
10116
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010117 return true;
10118}
10119
10120static bool check_encoder_cloning(struct intel_crtc *crtc)
10121{
10122 struct drm_device *dev = crtc->base.dev;
10123 struct intel_encoder *encoder;
10124
10125 list_for_each_entry(encoder,
10126 &dev->mode_config.encoder_list, base.head) {
10127 if (encoder->new_crtc != crtc)
10128 continue;
10129
10130 if (!check_single_encoder_cloning(crtc, encoder))
10131 return false;
10132 }
10133
10134 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010135}
10136
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010137static struct intel_crtc_config *
10138intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010139 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010140 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +020010141{
10142 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +020010143 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010144 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +010010145 int plane_bpp, ret = -EINVAL;
10146 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020010147
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010148 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010149 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10150 return ERR_PTR(-EINVAL);
10151 }
10152
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010153 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10154 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020010155 return ERR_PTR(-ENOMEM);
10156
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010157 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10158 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010159
Daniel Vettere143a212013-07-04 12:01:15 +020010160 pipe_config->cpu_transcoder =
10161 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010162 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010163
Imre Deak2960bc92013-07-30 13:36:32 +030010164 /*
10165 * Sanitize sync polarity flags based on requested ones. If neither
10166 * positive or negative polarity is requested, treat this as meaning
10167 * negative polarity.
10168 */
10169 if (!(pipe_config->adjusted_mode.flags &
10170 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10171 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10172
10173 if (!(pipe_config->adjusted_mode.flags &
10174 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10175 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10176
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010177 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10178 * plane pixel format and any sink constraints into account. Returns the
10179 * source plane bpp so that dithering can be selected on mismatches
10180 * after encoders and crtc also have had their say. */
10181 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10182 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010183 if (plane_bpp < 0)
10184 goto fail;
10185
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030010186 /*
10187 * Determine the real pipe dimensions. Note that stereo modes can
10188 * increase the actual pipe size due to the frame doubling and
10189 * insertion of additional space for blanks between the frame. This
10190 * is stored in the crtc timings. We use the requested mode to do this
10191 * computation to clearly distinguish it from the adjusted mode, which
10192 * can be changed by the connectors in the below retry loop.
10193 */
10194 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10195 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10196 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10197
Daniel Vettere29c22c2013-02-21 00:00:16 +010010198encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020010199 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020010200 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020010201 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010202
Daniel Vetter135c81b2013-07-21 21:37:09 +020010203 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +010010204 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020010205
Daniel Vetter7758a112012-07-08 19:40:39 +020010206 /* Pass our mode to the connectors and the CRTC to give them a chance to
10207 * adjust it according to limitations or connector properties, and also
10208 * a chance to reject the mode entirely.
10209 */
10210 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10211 base.head) {
10212
10213 if (&encoder->new_crtc->base != crtc)
10214 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +010010215
Daniel Vetterefea6e82013-07-21 21:36:59 +020010216 if (!(encoder->compute_config(encoder, pipe_config))) {
10217 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020010218 goto fail;
10219 }
10220 }
10221
Daniel Vetterff9a6752013-06-01 17:16:21 +020010222 /* Set default port clock if not overwritten by the encoder. Needs to be
10223 * done afterwards in case the encoder adjusts the mode. */
10224 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +010010225 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10226 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010227
Daniel Vettera43f6e02013-06-07 23:10:32 +020010228 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010229 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010230 DRM_DEBUG_KMS("CRTC fixup failed\n");
10231 goto fail;
10232 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010010233
10234 if (ret == RETRY) {
10235 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10236 ret = -EINVAL;
10237 goto fail;
10238 }
10239
10240 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10241 retry = false;
10242 goto encoder_retry;
10243 }
10244
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010245 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10246 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10247 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10248
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010249 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +020010250fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010251 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010252 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +020010253}
10254
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010255/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10256 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10257static void
10258intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10259 unsigned *prepare_pipes, unsigned *disable_pipes)
10260{
10261 struct intel_crtc *intel_crtc;
10262 struct drm_device *dev = crtc->dev;
10263 struct intel_encoder *encoder;
10264 struct intel_connector *connector;
10265 struct drm_crtc *tmp_crtc;
10266
10267 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10268
10269 /* Check which crtcs have changed outputs connected to them, these need
10270 * to be part of the prepare_pipes mask. We don't (yet) support global
10271 * modeset across multiple crtcs, so modeset_pipes will only have one
10272 * bit set at most. */
10273 list_for_each_entry(connector, &dev->mode_config.connector_list,
10274 base.head) {
10275 if (connector->base.encoder == &connector->new_encoder->base)
10276 continue;
10277
10278 if (connector->base.encoder) {
10279 tmp_crtc = connector->base.encoder->crtc;
10280
10281 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10282 }
10283
10284 if (connector->new_encoder)
10285 *prepare_pipes |=
10286 1 << connector->new_encoder->new_crtc->pipe;
10287 }
10288
10289 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10290 base.head) {
10291 if (encoder->base.crtc == &encoder->new_crtc->base)
10292 continue;
10293
10294 if (encoder->base.crtc) {
10295 tmp_crtc = encoder->base.crtc;
10296
10297 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10298 }
10299
10300 if (encoder->new_crtc)
10301 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10302 }
10303
Ville Syrjälä76688512014-01-10 11:28:06 +020010304 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010305 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010306 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010307 continue;
10308
Ville Syrjälä76688512014-01-10 11:28:06 +020010309 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010310 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +020010311 else
10312 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010313 }
10314
10315
10316 /* set_mode is also used to update properties on life display pipes. */
10317 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +020010318 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010319 *prepare_pipes |= 1 << intel_crtc->pipe;
10320
Daniel Vetterb6c51642013-04-12 18:48:43 +020010321 /*
10322 * For simplicity do a full modeset on any pipe where the output routing
10323 * changed. We could be more clever, but that would require us to be
10324 * more careful with calling the relevant encoder->mode_set functions.
10325 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010326 if (*prepare_pipes)
10327 *modeset_pipes = *prepare_pipes;
10328
10329 /* ... and mask these out. */
10330 *modeset_pipes &= ~(*disable_pipes);
10331 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +020010332
10333 /*
10334 * HACK: We don't (yet) fully support global modesets. intel_set_config
10335 * obies this rule, but the modeset restore mode of
10336 * intel_modeset_setup_hw_state does not.
10337 */
10338 *modeset_pipes &= 1 << intel_crtc->pipe;
10339 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +020010340
10341 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10342 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010343}
10344
Daniel Vetterea9d7582012-07-10 10:42:52 +020010345static bool intel_crtc_in_use(struct drm_crtc *crtc)
10346{
10347 struct drm_encoder *encoder;
10348 struct drm_device *dev = crtc->dev;
10349
10350 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10351 if (encoder->crtc == crtc)
10352 return true;
10353
10354 return false;
10355}
10356
10357static void
10358intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10359{
10360 struct intel_encoder *intel_encoder;
10361 struct intel_crtc *intel_crtc;
10362 struct drm_connector *connector;
10363
10364 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10365 base.head) {
10366 if (!intel_encoder->base.crtc)
10367 continue;
10368
10369 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10370
10371 if (prepare_pipes & (1 << intel_crtc->pipe))
10372 intel_encoder->connectors_active = false;
10373 }
10374
10375 intel_modeset_commit_output_state(dev);
10376
Ville Syrjälä76688512014-01-10 11:28:06 +020010377 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010378 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010379 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010380 WARN_ON(intel_crtc->new_config &&
10381 intel_crtc->new_config != &intel_crtc->config);
10382 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010383 }
10384
10385 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10386 if (!connector->encoder || !connector->encoder->crtc)
10387 continue;
10388
10389 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10390
10391 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +020010392 struct drm_property *dpms_property =
10393 dev->mode_config.dpms_property;
10394
Daniel Vetterea9d7582012-07-10 10:42:52 +020010395 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -050010396 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +020010397 dpms_property,
10398 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010399
10400 intel_encoder = to_intel_encoder(connector->encoder);
10401 intel_encoder->connectors_active = true;
10402 }
10403 }
10404
10405}
10406
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010407static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010408{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010409 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010410
10411 if (clock1 == clock2)
10412 return true;
10413
10414 if (!clock1 || !clock2)
10415 return false;
10416
10417 diff = abs(clock1 - clock2);
10418
10419 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10420 return true;
10421
10422 return false;
10423}
10424
Daniel Vetter25c5b262012-07-08 22:08:04 +020010425#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10426 list_for_each_entry((intel_crtc), \
10427 &(dev)->mode_config.crtc_list, \
10428 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +020010429 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020010430
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010431static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010432intel_pipe_config_compare(struct drm_device *dev,
10433 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010434 struct intel_crtc_config *pipe_config)
10435{
Daniel Vetter66e985c2013-06-05 13:34:20 +020010436#define PIPE_CONF_CHECK_X(name) \
10437 if (current_config->name != pipe_config->name) { \
10438 DRM_ERROR("mismatch in " #name " " \
10439 "(expected 0x%08x, found 0x%08x)\n", \
10440 current_config->name, \
10441 pipe_config->name); \
10442 return false; \
10443 }
10444
Daniel Vetter08a24032013-04-19 11:25:34 +020010445#define PIPE_CONF_CHECK_I(name) \
10446 if (current_config->name != pipe_config->name) { \
10447 DRM_ERROR("mismatch in " #name " " \
10448 "(expected %i, found %i)\n", \
10449 current_config->name, \
10450 pipe_config->name); \
10451 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010010452 }
10453
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010454/* This is required for BDW+ where there is only one set of registers for
10455 * switching between high and low RR.
10456 * This macro can be used whenever a comparison has to be made between one
10457 * hw state and multiple sw state variables.
10458 */
10459#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10460 if ((current_config->name != pipe_config->name) && \
10461 (current_config->alt_name != pipe_config->name)) { \
10462 DRM_ERROR("mismatch in " #name " " \
10463 "(expected %i or %i, found %i)\n", \
10464 current_config->name, \
10465 current_config->alt_name, \
10466 pipe_config->name); \
10467 return false; \
10468 }
10469
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010470#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10471 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -070010472 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010473 "(expected %i, found %i)\n", \
10474 current_config->name & (mask), \
10475 pipe_config->name & (mask)); \
10476 return false; \
10477 }
10478
Ville Syrjälä5e550652013-09-06 23:29:07 +030010479#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10480 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10481 DRM_ERROR("mismatch in " #name " " \
10482 "(expected %i, found %i)\n", \
10483 current_config->name, \
10484 pipe_config->name); \
10485 return false; \
10486 }
10487
Daniel Vetterbb760062013-06-06 14:55:52 +020010488#define PIPE_CONF_QUIRK(quirk) \
10489 ((current_config->quirks | pipe_config->quirks) & (quirk))
10490
Daniel Vettereccb1402013-05-22 00:50:22 +020010491 PIPE_CONF_CHECK_I(cpu_transcoder);
10492
Daniel Vetter08a24032013-04-19 11:25:34 +020010493 PIPE_CONF_CHECK_I(has_pch_encoder);
10494 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +020010495 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10496 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10497 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10498 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10499 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +020010500
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010501 PIPE_CONF_CHECK_I(has_dp_encoder);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010502
10503 if (INTEL_INFO(dev)->gen < 8) {
10504 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10505 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10506 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10507 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10508 PIPE_CONF_CHECK_I(dp_m_n.tu);
10509
10510 if (current_config->has_drrs) {
10511 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10512 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10513 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10514 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10515 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10516 }
10517 } else {
10518 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10519 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10520 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10521 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10522 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10523 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010524
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010525 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10526 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10527 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10528 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10529 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10530 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10531
10532 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10533 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10534 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10535 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10536 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10537 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10538
Daniel Vetterc93f54c2013-06-27 19:47:19 +020010539 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +020010540 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020010541 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10542 IS_VALLEYVIEW(dev))
10543 PIPE_CONF_CHECK_I(limited_color_range);
Daniel Vetter6c49f242013-06-06 12:45:25 +020010544
Daniel Vetter9ed109a2014-04-24 23:54:52 +020010545 PIPE_CONF_CHECK_I(has_audio);
10546
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010547 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10548 DRM_MODE_FLAG_INTERLACE);
10549
Daniel Vetterbb760062013-06-06 14:55:52 +020010550 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10551 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10552 DRM_MODE_FLAG_PHSYNC);
10553 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10554 DRM_MODE_FLAG_NHSYNC);
10555 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10556 DRM_MODE_FLAG_PVSYNC);
10557 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10558 DRM_MODE_FLAG_NVSYNC);
10559 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010560
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010561 PIPE_CONF_CHECK_I(pipe_src_w);
10562 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010563
Daniel Vetter99535992014-04-13 12:00:33 +020010564 /*
10565 * FIXME: BIOS likes to set up a cloned config with lvds+external
10566 * screen. Since we don't yet re-compute the pipe config when moving
10567 * just the lvds port away to another pipe the sw tracking won't match.
10568 *
10569 * Proper atomic modesets with recomputed global state will fix this.
10570 * Until then just don't check gmch state for inherited modes.
10571 */
10572 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10573 PIPE_CONF_CHECK_I(gmch_pfit.control);
10574 /* pfit ratios are autocomputed by the hw on gen4+ */
10575 if (INTEL_INFO(dev)->gen < 4)
10576 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10577 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10578 }
10579
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010580 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10581 if (current_config->pch_pfit.enabled) {
10582 PIPE_CONF_CHECK_I(pch_pfit.pos);
10583 PIPE_CONF_CHECK_I(pch_pfit.size);
10584 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010585
Jesse Barnese59150d2014-01-07 13:30:45 -080010586 /* BDW+ don't expose a synchronous way to read the state */
10587 if (IS_HASWELL(dev))
10588 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010589
Ville Syrjälä282740f2013-09-04 18:30:03 +030010590 PIPE_CONF_CHECK_I(double_wide);
10591
Daniel Vetter26804af2014-06-25 22:01:55 +030010592 PIPE_CONF_CHECK_X(ddi_pll_sel);
10593
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010594 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010595 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010596 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010597 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10598 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010599 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010600
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010601 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10602 PIPE_CONF_CHECK_I(pipe_bpp);
10603
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010604 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10605 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010606
Daniel Vetter66e985c2013-06-05 13:34:20 +020010607#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010608#undef PIPE_CONF_CHECK_I
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010609#undef PIPE_CONF_CHECK_I_ALT
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010610#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010611#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010612#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010613
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010614 return true;
10615}
10616
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010617static void
10618check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010619{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010620 struct intel_connector *connector;
10621
10622 list_for_each_entry(connector, &dev->mode_config.connector_list,
10623 base.head) {
10624 /* This also checks the encoder/connector hw state with the
10625 * ->get_hw_state callbacks. */
10626 intel_connector_check_state(connector);
10627
10628 WARN(&connector->new_encoder->base != connector->base.encoder,
10629 "connector's staged encoder doesn't match current encoder\n");
10630 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010631}
10632
10633static void
10634check_encoder_state(struct drm_device *dev)
10635{
10636 struct intel_encoder *encoder;
10637 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010638
10639 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10640 base.head) {
10641 bool enabled = false;
10642 bool active = false;
10643 enum pipe pipe, tracked_pipe;
10644
10645 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10646 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030010647 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010648
10649 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10650 "encoder's stage crtc doesn't match current crtc\n");
10651 WARN(encoder->connectors_active && !encoder->base.crtc,
10652 "encoder's active_connectors set, but no crtc\n");
10653
10654 list_for_each_entry(connector, &dev->mode_config.connector_list,
10655 base.head) {
10656 if (connector->base.encoder != &encoder->base)
10657 continue;
10658 enabled = true;
10659 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10660 active = true;
10661 }
Dave Airlie0e32b392014-05-02 14:02:48 +100010662 /*
10663 * for MST connectors if we unplug the connector is gone
10664 * away but the encoder is still connected to a crtc
10665 * until a modeset happens in response to the hotplug.
10666 */
10667 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10668 continue;
10669
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010670 WARN(!!encoder->base.crtc != enabled,
10671 "encoder's enabled state mismatch "
10672 "(expected %i, found %i)\n",
10673 !!encoder->base.crtc, enabled);
10674 WARN(active && !encoder->base.crtc,
10675 "active encoder with no crtc\n");
10676
10677 WARN(encoder->connectors_active != active,
10678 "encoder's computed active state doesn't match tracked active state "
10679 "(expected %i, found %i)\n", active, encoder->connectors_active);
10680
10681 active = encoder->get_hw_state(encoder, &pipe);
10682 WARN(active != encoder->connectors_active,
10683 "encoder's hw state doesn't match sw tracking "
10684 "(expected %i, found %i)\n",
10685 encoder->connectors_active, active);
10686
10687 if (!encoder->base.crtc)
10688 continue;
10689
10690 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10691 WARN(active && pipe != tracked_pipe,
10692 "active encoder's pipe doesn't match"
10693 "(expected %i, found %i)\n",
10694 tracked_pipe, pipe);
10695
10696 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010697}
10698
10699static void
10700check_crtc_state(struct drm_device *dev)
10701{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010702 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010703 struct intel_crtc *crtc;
10704 struct intel_encoder *encoder;
10705 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010706
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010707 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010708 bool enabled = false;
10709 bool active = false;
10710
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010711 memset(&pipe_config, 0, sizeof(pipe_config));
10712
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010713 DRM_DEBUG_KMS("[CRTC:%d]\n",
10714 crtc->base.base.id);
10715
10716 WARN(crtc->active && !crtc->base.enabled,
10717 "active crtc, but not enabled in sw tracking\n");
10718
10719 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10720 base.head) {
10721 if (encoder->base.crtc != &crtc->base)
10722 continue;
10723 enabled = true;
10724 if (encoder->connectors_active)
10725 active = true;
10726 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010727
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010728 WARN(active != crtc->active,
10729 "crtc's computed active state doesn't match tracked active state "
10730 "(expected %i, found %i)\n", active, crtc->active);
10731 WARN(enabled != crtc->base.enabled,
10732 "crtc's computed enabled state doesn't match tracked enabled state "
10733 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10734
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010735 active = dev_priv->display.get_pipe_config(crtc,
10736 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010737
10738 /* hw state is inconsistent with the pipe A quirk */
10739 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10740 active = crtc->active;
10741
Daniel Vetter6c49f242013-06-06 12:45:25 +020010742 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10743 base.head) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010744 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010745 if (encoder->base.crtc != &crtc->base)
10746 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010747 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010748 encoder->get_config(encoder, &pipe_config);
10749 }
10750
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010751 WARN(crtc->active != active,
10752 "crtc active state doesn't match with hw state "
10753 "(expected %i, found %i)\n", crtc->active, active);
10754
Daniel Vetterc0b03412013-05-28 12:05:54 +020010755 if (active &&
10756 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10757 WARN(1, "pipe state doesn't match!\n");
10758 intel_dump_pipe_config(crtc, &pipe_config,
10759 "[hw state]");
10760 intel_dump_pipe_config(crtc, &crtc->config,
10761 "[sw state]");
10762 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010763 }
10764}
10765
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010766static void
10767check_shared_dpll_state(struct drm_device *dev)
10768{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010769 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010770 struct intel_crtc *crtc;
10771 struct intel_dpll_hw_state dpll_hw_state;
10772 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010773
10774 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10775 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10776 int enabled_crtcs = 0, active_crtcs = 0;
10777 bool active;
10778
10779 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10780
10781 DRM_DEBUG_KMS("%s\n", pll->name);
10782
10783 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10784
10785 WARN(pll->active > pll->refcount,
10786 "more active pll users than references: %i vs %i\n",
10787 pll->active, pll->refcount);
10788 WARN(pll->active && !pll->on,
10789 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010790 WARN(pll->on && !pll->active,
10791 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010792 WARN(pll->on != active,
10793 "pll on state mismatch (expected %i, found %i)\n",
10794 pll->on, active);
10795
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010796 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010797 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10798 enabled_crtcs++;
10799 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10800 active_crtcs++;
10801 }
10802 WARN(pll->active != active_crtcs,
10803 "pll active crtcs mismatch (expected %i, found %i)\n",
10804 pll->active, active_crtcs);
10805 WARN(pll->refcount != enabled_crtcs,
10806 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10807 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010808
10809 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10810 sizeof(dpll_hw_state)),
10811 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010812 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010813}
10814
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010815void
10816intel_modeset_check_state(struct drm_device *dev)
10817{
10818 check_connector_state(dev);
10819 check_encoder_state(dev);
10820 check_crtc_state(dev);
10821 check_shared_dpll_state(dev);
10822}
10823
Ville Syrjälä18442d02013-09-13 16:00:08 +030010824void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10825 int dotclock)
10826{
10827 /*
10828 * FDI already provided one idea for the dotclock.
10829 * Yell if the encoder disagrees.
10830 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010831 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010832 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010833 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010834}
10835
Ville Syrjälä80715b22014-05-15 20:23:23 +030010836static void update_scanline_offset(struct intel_crtc *crtc)
10837{
10838 struct drm_device *dev = crtc->base.dev;
10839
10840 /*
10841 * The scanline counter increments at the leading edge of hsync.
10842 *
10843 * On most platforms it starts counting from vtotal-1 on the
10844 * first active line. That means the scanline counter value is
10845 * always one less than what we would expect. Ie. just after
10846 * start of vblank, which also occurs at start of hsync (on the
10847 * last active line), the scanline counter will read vblank_start-1.
10848 *
10849 * On gen2 the scanline counter starts counting from 1 instead
10850 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10851 * to keep the value positive), instead of adding one.
10852 *
10853 * On HSW+ the behaviour of the scanline counter depends on the output
10854 * type. For DP ports it behaves like most other platforms, but on HDMI
10855 * there's an extra 1 line difference. So we need to add two instead of
10856 * one to the value.
10857 */
10858 if (IS_GEN2(dev)) {
10859 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10860 int vtotal;
10861
10862 vtotal = mode->crtc_vtotal;
10863 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10864 vtotal /= 2;
10865
10866 crtc->scanline_offset = vtotal - 1;
10867 } else if (HAS_DDI(dev) &&
10868 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10869 crtc->scanline_offset = 2;
10870 } else
10871 crtc->scanline_offset = 1;
10872}
10873
Daniel Vetterf30da182013-04-11 20:22:50 +020010874static int __intel_set_mode(struct drm_crtc *crtc,
10875 struct drm_display_mode *mode,
10876 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +020010877{
10878 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010879 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010880 struct drm_display_mode *saved_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010881 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010882 struct intel_crtc *intel_crtc;
10883 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010884 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010885
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010886 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010887 if (!saved_mode)
10888 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010889
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010890 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +020010891 &prepare_pipes, &disable_pipes);
10892
Tim Gardner3ac18232012-12-07 07:54:26 -070010893 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010894
Daniel Vetter25c5b262012-07-08 22:08:04 +020010895 /* Hack: Because we don't (yet) support global modeset on multiple
10896 * crtcs, we don't keep track of the new mode for more than one crtc.
10897 * Hence simply check whether any bit is set in modeset_pipes in all the
10898 * pieces of code that are not yet converted to deal with mutliple crtcs
10899 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010900 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010901 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010902 if (IS_ERR(pipe_config)) {
10903 ret = PTR_ERR(pipe_config);
10904 pipe_config = NULL;
10905
Tim Gardner3ac18232012-12-07 07:54:26 -070010906 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010907 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020010908 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10909 "[modeset]");
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010910 to_intel_crtc(crtc)->new_config = pipe_config;
Daniel Vettera6778b32012-07-02 09:56:42 +020010911 }
10912
Jesse Barnes30a970c2013-11-04 13:48:12 -080010913 /*
10914 * See if the config requires any additional preparation, e.g.
10915 * to adjust global state with pipes off. We need to do this
10916 * here so we can get the modeset_pipe updated config for the new
10917 * mode set on this crtc. For other crtcs we need to use the
10918 * adjusted_mode bits in the crtc directly.
10919 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010920 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010921 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010922
Ville Syrjäläc164f832013-11-05 22:34:12 +020010923 /* may have added more to prepare_pipes than we should */
10924 prepare_pipes &= ~disable_pipes;
10925 }
10926
Daniel Vetter460da9162013-03-27 00:44:51 +010010927 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10928 intel_crtc_disable(&intel_crtc->base);
10929
Daniel Vetterea9d7582012-07-10 10:42:52 +020010930 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10931 if (intel_crtc->base.enabled)
10932 dev_priv->display.crtc_disable(&intel_crtc->base);
10933 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010934
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010935 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10936 * to set it here already despite that we pass it down the callchain.
10937 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010938 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010939 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010940 /* mode_set/enable/disable functions rely on a correct pipe
10941 * config. */
10942 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010943 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010944
10945 /*
10946 * Calculate and store various constants which
10947 * are later needed by vblank and swap-completion
10948 * timestamping. They are derived from true hwmode.
10949 */
10950 drm_calc_timestamping_constants(crtc,
10951 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010952 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010953
Daniel Vetterea9d7582012-07-10 10:42:52 +020010954 /* Only after disabling all output pipelines that will be changed can we
10955 * update the the output configuration. */
10956 intel_modeset_update_state(dev, prepare_pipes);
10957
Daniel Vetter47fab732012-10-26 10:58:18 +020010958 if (dev_priv->display.modeset_global_resources)
10959 dev_priv->display.modeset_global_resources(dev);
10960
Daniel Vettera6778b32012-07-02 09:56:42 +020010961 /* Set up the DPLL and any encoders state that needs to adjust or depend
10962 * on the DPLL.
10963 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010964 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070010965 struct drm_framebuffer *old_fb = crtc->primary->fb;
10966 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10967 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Daniel Vetter4c107942014-04-24 23:55:05 +020010968
10969 mutex_lock(&dev->struct_mutex);
10970 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vettera071fa02014-06-18 23:28:09 +020010971 obj,
Daniel Vetter4c107942014-04-24 23:55:05 +020010972 NULL);
10973 if (ret != 0) {
10974 DRM_ERROR("pin & fence failed\n");
10975 mutex_unlock(&dev->struct_mutex);
10976 goto done;
10977 }
Matt Roper2ff8fde2014-07-08 07:50:07 -070010978 if (old_fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020010979 intel_unpin_fb_obj(old_obj);
Daniel Vettera071fa02014-06-18 23:28:09 +020010980 i915_gem_track_fb(old_obj, obj,
10981 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Daniel Vetter4c107942014-04-24 23:55:05 +020010982 mutex_unlock(&dev->struct_mutex);
10983
10984 crtc->primary->fb = fb;
10985 crtc->x = x;
10986 crtc->y = y;
10987
Daniel Vetter4271b752014-04-24 23:55:00 +020010988 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10989 x, y, fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010990 if (ret)
10991 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +020010992 }
10993
10994 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030010995 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10996 update_scanline_offset(intel_crtc);
10997
Daniel Vetter25c5b262012-07-08 22:08:04 +020010998 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030010999 }
Daniel Vettera6778b32012-07-02 09:56:42 +020011000
Daniel Vettera6778b32012-07-02 09:56:42 +020011001 /* FIXME: add subpixel order */
11002done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030011003 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070011004 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020011005
Tim Gardner3ac18232012-12-07 07:54:26 -070011006out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010011007 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070011008 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020011009 return ret;
11010}
11011
Damien Lespiaue7457a92013-08-08 22:28:59 +010011012static int intel_set_mode(struct drm_crtc *crtc,
11013 struct drm_display_mode *mode,
11014 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020011015{
11016 int ret;
11017
11018 ret = __intel_set_mode(crtc, mode, x, y, fb);
11019
11020 if (ret == 0)
11021 intel_modeset_check_state(crtc->dev);
11022
11023 return ret;
11024}
11025
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011026void intel_crtc_restore_mode(struct drm_crtc *crtc)
11027{
Matt Roperf4510a22014-04-01 15:22:40 -070011028 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011029}
11030
Daniel Vetter25c5b262012-07-08 22:08:04 +020011031#undef for_each_intel_crtc_masked
11032
Daniel Vetterd9e55602012-07-04 22:16:09 +020011033static void intel_set_config_free(struct intel_set_config *config)
11034{
11035 if (!config)
11036 return;
11037
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011038 kfree(config->save_connector_encoders);
11039 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020011040 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020011041 kfree(config);
11042}
11043
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011044static int intel_set_config_save_state(struct drm_device *dev,
11045 struct intel_set_config *config)
11046{
Ville Syrjälä76688512014-01-10 11:28:06 +020011047 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011048 struct drm_encoder *encoder;
11049 struct drm_connector *connector;
11050 int count;
11051
Ville Syrjälä76688512014-01-10 11:28:06 +020011052 config->save_crtc_enabled =
11053 kcalloc(dev->mode_config.num_crtc,
11054 sizeof(bool), GFP_KERNEL);
11055 if (!config->save_crtc_enabled)
11056 return -ENOMEM;
11057
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011058 config->save_encoder_crtcs =
11059 kcalloc(dev->mode_config.num_encoder,
11060 sizeof(struct drm_crtc *), GFP_KERNEL);
11061 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011062 return -ENOMEM;
11063
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011064 config->save_connector_encoders =
11065 kcalloc(dev->mode_config.num_connector,
11066 sizeof(struct drm_encoder *), GFP_KERNEL);
11067 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011068 return -ENOMEM;
11069
11070 /* Copy data. Note that driver private data is not affected.
11071 * Should anything bad happen only the expected state is
11072 * restored, not the drivers personal bookkeeping.
11073 */
11074 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010011075 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011076 config->save_crtc_enabled[count++] = crtc->enabled;
11077 }
11078
11079 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011080 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011081 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011082 }
11083
11084 count = 0;
11085 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011086 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011087 }
11088
11089 return 0;
11090}
11091
11092static void intel_set_config_restore_state(struct drm_device *dev,
11093 struct intel_set_config *config)
11094{
Ville Syrjälä76688512014-01-10 11:28:06 +020011095 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020011096 struct intel_encoder *encoder;
11097 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011098 int count;
11099
11100 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011101 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011102 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011103
11104 if (crtc->new_enabled)
11105 crtc->new_config = &crtc->config;
11106 else
11107 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011108 }
11109
11110 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011111 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11112 encoder->new_crtc =
11113 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011114 }
11115
11116 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011117 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11118 connector->new_encoder =
11119 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011120 }
11121}
11122
Imre Deake3de42b2013-05-03 19:44:07 +020011123static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010011124is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020011125{
11126 int i;
11127
Chris Wilson2e57f472013-07-17 12:14:40 +010011128 if (set->num_connectors == 0)
11129 return false;
11130
11131 if (WARN_ON(set->connectors == NULL))
11132 return false;
11133
11134 for (i = 0; i < set->num_connectors; i++)
11135 if (set->connectors[i]->encoder &&
11136 set->connectors[i]->encoder->crtc == set->crtc &&
11137 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020011138 return true;
11139
11140 return false;
11141}
11142
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011143static void
11144intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11145 struct intel_set_config *config)
11146{
11147
11148 /* We should be able to check here if the fb has the same properties
11149 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010011150 if (is_crtc_connector_off(set)) {
11151 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070011152 } else if (set->crtc->primary->fb != set->fb) {
Matt Roper3b150f02014-05-29 08:06:53 -070011153 /*
11154 * If we have no fb, we can only flip as long as the crtc is
11155 * active, otherwise we need a full mode set. The crtc may
11156 * be active if we've only disabled the primary plane, or
11157 * in fastboot situations.
11158 */
Matt Roperf4510a22014-04-01 15:22:40 -070011159 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011160 struct intel_crtc *intel_crtc =
11161 to_intel_crtc(set->crtc);
11162
Matt Roper3b150f02014-05-29 08:06:53 -070011163 if (intel_crtc->active) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011164 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11165 config->fb_changed = true;
11166 } else {
11167 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11168 config->mode_changed = true;
11169 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011170 } else if (set->fb == NULL) {
11171 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010011172 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070011173 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011174 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011175 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011176 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011177 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011178 }
11179
Daniel Vetter835c5872012-07-10 18:11:08 +020011180 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011181 config->fb_changed = true;
11182
11183 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11184 DRM_DEBUG_KMS("modes are different, full mode set\n");
11185 drm_mode_debug_printmodeline(&set->crtc->mode);
11186 drm_mode_debug_printmodeline(set->mode);
11187 config->mode_changed = true;
11188 }
Chris Wilsona1d95702013-08-13 18:48:47 +010011189
11190 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11191 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011192}
11193
Daniel Vetter2e431052012-07-04 22:42:15 +020011194static int
Daniel Vetter9a935852012-07-05 22:34:27 +020011195intel_modeset_stage_output_state(struct drm_device *dev,
11196 struct drm_mode_set *set,
11197 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020011198{
Daniel Vetter9a935852012-07-05 22:34:27 +020011199 struct intel_connector *connector;
11200 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020011201 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030011202 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020011203
Damien Lespiau9abdda72013-02-13 13:29:23 +000011204 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020011205 * of connectors. For paranoia, double-check this. */
11206 WARN_ON(!set->fb && (set->num_connectors != 0));
11207 WARN_ON(set->fb && (set->num_connectors == 0));
11208
Daniel Vetter9a935852012-07-05 22:34:27 +020011209 list_for_each_entry(connector, &dev->mode_config.connector_list,
11210 base.head) {
11211 /* Otherwise traverse passed in connector list and get encoders
11212 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020011213 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011214 if (set->connectors[ro] == &connector->base) {
Dave Airlie0e32b392014-05-02 14:02:48 +100011215 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
Daniel Vetter50f56112012-07-02 09:35:43 +020011216 break;
11217 }
11218 }
11219
Daniel Vetter9a935852012-07-05 22:34:27 +020011220 /* If we disable the crtc, disable all its connectors. Also, if
11221 * the connector is on the changing crtc but not on the new
11222 * connector list, disable it. */
11223 if ((!set->fb || ro == set->num_connectors) &&
11224 connector->base.encoder &&
11225 connector->base.encoder->crtc == set->crtc) {
11226 connector->new_encoder = NULL;
11227
11228 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11229 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011230 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020011231 }
11232
11233
11234 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011235 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011236 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011237 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011238 }
11239 /* connector->new_encoder is now updated for all connectors. */
11240
11241 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020011242 list_for_each_entry(connector, &dev->mode_config.connector_list,
11243 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011244 struct drm_crtc *new_crtc;
11245
Daniel Vetter9a935852012-07-05 22:34:27 +020011246 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020011247 continue;
11248
Daniel Vetter9a935852012-07-05 22:34:27 +020011249 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020011250
11251 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011252 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020011253 new_crtc = set->crtc;
11254 }
11255
11256 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010011257 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11258 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011259 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020011260 }
Dave Airlie0e32b392014-05-02 14:02:48 +100011261 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
Daniel Vetter9a935852012-07-05 22:34:27 +020011262
11263 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11264 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011265 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020011266 new_crtc->base.id);
11267 }
11268
11269 /* Check for any encoders that needs to be disabled. */
11270 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11271 base.head) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011272 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011273 list_for_each_entry(connector,
11274 &dev->mode_config.connector_list,
11275 base.head) {
11276 if (connector->new_encoder == encoder) {
11277 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011278 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020011279 }
11280 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011281
11282 if (num_connectors == 0)
11283 encoder->new_crtc = NULL;
11284 else if (num_connectors > 1)
11285 return -EINVAL;
11286
Daniel Vetter9a935852012-07-05 22:34:27 +020011287 /* Only now check for crtc changes so we don't miss encoders
11288 * that will be disabled. */
11289 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011290 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011291 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011292 }
11293 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011294 /* Now we've also updated encoder->new_crtc for all encoders. */
Dave Airlie0e32b392014-05-02 14:02:48 +100011295 list_for_each_entry(connector, &dev->mode_config.connector_list,
11296 base.head) {
11297 if (connector->new_encoder)
11298 if (connector->new_encoder != connector->encoder)
11299 connector->encoder = connector->new_encoder;
11300 }
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011301 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011302 crtc->new_enabled = false;
11303
11304 list_for_each_entry(encoder,
11305 &dev->mode_config.encoder_list,
11306 base.head) {
11307 if (encoder->new_crtc == crtc) {
11308 crtc->new_enabled = true;
11309 break;
11310 }
11311 }
11312
11313 if (crtc->new_enabled != crtc->base.enabled) {
11314 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11315 crtc->new_enabled ? "en" : "dis");
11316 config->mode_changed = true;
11317 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011318
11319 if (crtc->new_enabled)
11320 crtc->new_config = &crtc->config;
11321 else
11322 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011323 }
11324
Daniel Vetter2e431052012-07-04 22:42:15 +020011325 return 0;
11326}
11327
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011328static void disable_crtc_nofb(struct intel_crtc *crtc)
11329{
11330 struct drm_device *dev = crtc->base.dev;
11331 struct intel_encoder *encoder;
11332 struct intel_connector *connector;
11333
11334 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11335 pipe_name(crtc->pipe));
11336
11337 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11338 if (connector->new_encoder &&
11339 connector->new_encoder->new_crtc == crtc)
11340 connector->new_encoder = NULL;
11341 }
11342
11343 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11344 if (encoder->new_crtc == crtc)
11345 encoder->new_crtc = NULL;
11346 }
11347
11348 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011349 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011350}
11351
Daniel Vetter2e431052012-07-04 22:42:15 +020011352static int intel_crtc_set_config(struct drm_mode_set *set)
11353{
11354 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020011355 struct drm_mode_set save_set;
11356 struct intel_set_config *config;
11357 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020011358
Daniel Vetter8d3e3752012-07-05 16:09:09 +020011359 BUG_ON(!set);
11360 BUG_ON(!set->crtc);
11361 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020011362
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010011363 /* Enforce sane interface api - has been abused by the fb helper. */
11364 BUG_ON(!set->mode && set->fb);
11365 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020011366
Daniel Vetter2e431052012-07-04 22:42:15 +020011367 if (set->fb) {
11368 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11369 set->crtc->base.id, set->fb->base.id,
11370 (int)set->num_connectors, set->x, set->y);
11371 } else {
11372 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020011373 }
11374
11375 dev = set->crtc->dev;
11376
11377 ret = -ENOMEM;
11378 config = kzalloc(sizeof(*config), GFP_KERNEL);
11379 if (!config)
11380 goto out_config;
11381
11382 ret = intel_set_config_save_state(dev, config);
11383 if (ret)
11384 goto out_config;
11385
11386 save_set.crtc = set->crtc;
11387 save_set.mode = &set->crtc->mode;
11388 save_set.x = set->crtc->x;
11389 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070011390 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020011391
11392 /* Compute whether we need a full modeset, only an fb base update or no
11393 * change at all. In the future we might also check whether only the
11394 * mode changed, e.g. for LVDS where we only change the panel fitter in
11395 * such cases. */
11396 intel_set_config_compute_mode_changes(set, config);
11397
Daniel Vetter9a935852012-07-05 22:34:27 +020011398 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020011399 if (ret)
11400 goto fail;
11401
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011402 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011403 ret = intel_set_mode(set->crtc, set->mode,
11404 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011405 } else if (config->fb_changed) {
Matt Roper3b150f02014-05-29 08:06:53 -070011406 struct drm_i915_private *dev_priv = dev->dev_private;
11407 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11408
Ville Syrjälä4878cae2013-02-18 19:08:48 +020011409 intel_crtc_wait_for_pending_flips(set->crtc);
11410
Daniel Vetter4f660f42012-07-02 09:47:37 +020011411 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020011412 set->x, set->y, set->fb);
Matt Roper3b150f02014-05-29 08:06:53 -070011413
11414 /*
11415 * We need to make sure the primary plane is re-enabled if it
11416 * has previously been turned off.
11417 */
11418 if (!intel_crtc->primary_enabled && ret == 0) {
11419 WARN_ON(!intel_crtc->active);
11420 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11421 intel_crtc->pipe);
11422 }
11423
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011424 /*
11425 * In the fastboot case this may be our only check of the
11426 * state after boot. It would be better to only do it on
11427 * the first update, but we don't have a nice way of doing that
11428 * (and really, set_config isn't used much for high freq page
11429 * flipping, so increasing its cost here shouldn't be a big
11430 * deal).
11431 */
Jani Nikulad330a952014-01-21 11:24:25 +020011432 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011433 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020011434 }
11435
Chris Wilson2d05eae2013-05-03 17:36:25 +010011436 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020011437 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11438 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020011439fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010011440 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011441
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011442 /*
11443 * HACK: if the pipe was on, but we didn't have a framebuffer,
11444 * force the pipe off to avoid oopsing in the modeset code
11445 * due to fb==NULL. This should only happen during boot since
11446 * we don't yet reconstruct the FB from the hardware state.
11447 */
11448 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11449 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11450
Chris Wilson2d05eae2013-05-03 17:36:25 +010011451 /* Try to restore the config */
11452 if (config->mode_changed &&
11453 intel_set_mode(save_set.crtc, save_set.mode,
11454 save_set.x, save_set.y, save_set.fb))
11455 DRM_ERROR("failed to restore config after modeset failure\n");
11456 }
Daniel Vetter50f56112012-07-02 09:35:43 +020011457
Daniel Vetterd9e55602012-07-04 22:16:09 +020011458out_config:
11459 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011460 return ret;
11461}
11462
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011463static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011464 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020011465 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011466 .destroy = intel_crtc_destroy,
11467 .page_flip = intel_crtc_page_flip,
11468};
11469
Daniel Vetter53589012013-06-05 13:34:16 +020011470static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11471 struct intel_shared_dpll *pll,
11472 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011473{
Daniel Vetter53589012013-06-05 13:34:16 +020011474 uint32_t val;
11475
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030011476 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11477 return false;
11478
Daniel Vetter53589012013-06-05 13:34:16 +020011479 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020011480 hw_state->dpll = val;
11481 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11482 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020011483
11484 return val & DPLL_VCO_ENABLE;
11485}
11486
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011487static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11488 struct intel_shared_dpll *pll)
11489{
11490 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11491 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11492}
11493
Daniel Vettere7b903d2013-06-05 13:34:14 +020011494static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11495 struct intel_shared_dpll *pll)
11496{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011497 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020011498 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020011499
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011500 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11501
11502 /* Wait for the clocks to stabilize. */
11503 POSTING_READ(PCH_DPLL(pll->id));
11504 udelay(150);
11505
11506 /* The pixel multiplier can only be updated once the
11507 * DPLL is enabled and the clocks are stable.
11508 *
11509 * So write it again.
11510 */
11511 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11512 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011513 udelay(200);
11514}
11515
11516static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11517 struct intel_shared_dpll *pll)
11518{
11519 struct drm_device *dev = dev_priv->dev;
11520 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011521
11522 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011523 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020011524 if (intel_crtc_to_shared_dpll(crtc) == pll)
11525 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11526 }
11527
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011528 I915_WRITE(PCH_DPLL(pll->id), 0);
11529 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011530 udelay(200);
11531}
11532
Daniel Vetter46edb022013-06-05 13:34:12 +020011533static char *ibx_pch_dpll_names[] = {
11534 "PCH DPLL A",
11535 "PCH DPLL B",
11536};
11537
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011538static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011539{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011540 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011541 int i;
11542
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011543 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011544
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011545 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020011546 dev_priv->shared_dplls[i].id = i;
11547 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011548 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011549 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11550 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020011551 dev_priv->shared_dplls[i].get_hw_state =
11552 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011553 }
11554}
11555
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011556static void intel_shared_dpll_init(struct drm_device *dev)
11557{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011558 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011559
Daniel Vetter9cd86932014-06-25 22:01:57 +030011560 if (HAS_DDI(dev))
11561 intel_ddi_pll_init(dev);
11562 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011563 ibx_pch_dpll_init(dev);
11564 else
11565 dev_priv->num_shared_dpll = 0;
11566
11567 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011568}
11569
Matt Roper465c1202014-05-29 08:06:54 -070011570static int
11571intel_primary_plane_disable(struct drm_plane *plane)
11572{
11573 struct drm_device *dev = plane->dev;
11574 struct drm_i915_private *dev_priv = dev->dev_private;
11575 struct intel_plane *intel_plane = to_intel_plane(plane);
11576 struct intel_crtc *intel_crtc;
11577
11578 if (!plane->fb)
11579 return 0;
11580
11581 BUG_ON(!plane->crtc);
11582
11583 intel_crtc = to_intel_crtc(plane->crtc);
11584
11585 /*
11586 * Even though we checked plane->fb above, it's still possible that
11587 * the primary plane has been implicitly disabled because the crtc
11588 * coordinates given weren't visible, or because we detected
11589 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11590 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11591 * In either case, we need to unpin the FB and let the fb pointer get
11592 * updated, but otherwise we don't need to touch the hardware.
11593 */
11594 if (!intel_crtc->primary_enabled)
11595 goto disable_unpin;
11596
11597 intel_crtc_wait_for_pending_flips(plane->crtc);
11598 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11599 intel_plane->pipe);
Matt Roper465c1202014-05-29 08:06:54 -070011600disable_unpin:
Matt Roper4c345742014-07-09 16:22:10 -070011601 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011602 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
Daniel Vettera071fa02014-06-18 23:28:09 +020011603 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper2ff8fde2014-07-08 07:50:07 -070011604 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
Matt Roper4c345742014-07-09 16:22:10 -070011605 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011606 plane->fb = NULL;
11607
11608 return 0;
11609}
11610
11611static int
11612intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11613 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11614 unsigned int crtc_w, unsigned int crtc_h,
11615 uint32_t src_x, uint32_t src_y,
11616 uint32_t src_w, uint32_t src_h)
11617{
11618 struct drm_device *dev = crtc->dev;
11619 struct drm_i915_private *dev_priv = dev->dev_private;
11620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11621 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011622 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11623 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
Matt Roper465c1202014-05-29 08:06:54 -070011624 struct drm_rect dest = {
11625 /* integer pixels */
11626 .x1 = crtc_x,
11627 .y1 = crtc_y,
11628 .x2 = crtc_x + crtc_w,
11629 .y2 = crtc_y + crtc_h,
11630 };
11631 struct drm_rect src = {
11632 /* 16.16 fixed point */
11633 .x1 = src_x,
11634 .y1 = src_y,
11635 .x2 = src_x + src_w,
11636 .y2 = src_y + src_h,
11637 };
11638 const struct drm_rect clip = {
11639 /* integer pixels */
11640 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11641 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11642 };
11643 bool visible;
11644 int ret;
11645
11646 ret = drm_plane_helper_check_update(plane, crtc, fb,
11647 &src, &dest, &clip,
11648 DRM_PLANE_HELPER_NO_SCALING,
11649 DRM_PLANE_HELPER_NO_SCALING,
11650 false, true, &visible);
11651
11652 if (ret)
11653 return ret;
11654
11655 /*
11656 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11657 * updating the fb pointer, and returning without touching the
11658 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11659 * turn on the display with all planes setup as desired.
11660 */
11661 if (!crtc->enabled) {
Matt Roper4c345742014-07-09 16:22:10 -070011662 mutex_lock(&dev->struct_mutex);
11663
Matt Roper465c1202014-05-29 08:06:54 -070011664 /*
11665 * If we already called setplane while the crtc was disabled,
11666 * we may have an fb pinned; unpin it.
11667 */
11668 if (plane->fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011669 intel_unpin_fb_obj(old_obj);
11670
11671 i915_gem_track_fb(old_obj, obj,
11672 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper465c1202014-05-29 08:06:54 -070011673
11674 /* Pin and return without programming hardware */
Matt Roper4c345742014-07-09 16:22:10 -070011675 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11676 mutex_unlock(&dev->struct_mutex);
11677
11678 return ret;
Matt Roper465c1202014-05-29 08:06:54 -070011679 }
11680
11681 intel_crtc_wait_for_pending_flips(crtc);
11682
11683 /*
11684 * If clipping results in a non-visible primary plane, we'll disable
11685 * the primary plane. Note that this is a bit different than what
11686 * happens if userspace explicitly disables the plane by passing fb=0
11687 * because plane->fb still gets set and pinned.
11688 */
11689 if (!visible) {
Matt Roper4c345742014-07-09 16:22:10 -070011690 mutex_lock(&dev->struct_mutex);
11691
Matt Roper465c1202014-05-29 08:06:54 -070011692 /*
11693 * Try to pin the new fb first so that we can bail out if we
11694 * fail.
11695 */
11696 if (plane->fb != fb) {
Daniel Vettera071fa02014-06-18 23:28:09 +020011697 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
Matt Roper4c345742014-07-09 16:22:10 -070011698 if (ret) {
11699 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011700 return ret;
Matt Roper4c345742014-07-09 16:22:10 -070011701 }
Matt Roper465c1202014-05-29 08:06:54 -070011702 }
11703
Daniel Vettera071fa02014-06-18 23:28:09 +020011704 i915_gem_track_fb(old_obj, obj,
11705 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11706
Matt Roper465c1202014-05-29 08:06:54 -070011707 if (intel_crtc->primary_enabled)
11708 intel_disable_primary_hw_plane(dev_priv,
11709 intel_plane->plane,
11710 intel_plane->pipe);
11711
11712
11713 if (plane->fb != fb)
11714 if (plane->fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011715 intel_unpin_fb_obj(old_obj);
Matt Roper465c1202014-05-29 08:06:54 -070011716
Matt Roper4c345742014-07-09 16:22:10 -070011717 mutex_unlock(&dev->struct_mutex);
11718
Matt Roper465c1202014-05-29 08:06:54 -070011719 return 0;
11720 }
11721
11722 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11723 if (ret)
11724 return ret;
11725
11726 if (!intel_crtc->primary_enabled)
11727 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11728 intel_crtc->pipe);
11729
11730 return 0;
11731}
11732
Matt Roper3d7d6512014-06-10 08:28:13 -070011733/* Common destruction function for both primary and cursor planes */
11734static void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070011735{
11736 struct intel_plane *intel_plane = to_intel_plane(plane);
11737 drm_plane_cleanup(plane);
11738 kfree(intel_plane);
11739}
11740
11741static const struct drm_plane_funcs intel_primary_plane_funcs = {
11742 .update_plane = intel_primary_plane_setplane,
11743 .disable_plane = intel_primary_plane_disable,
Matt Roper3d7d6512014-06-10 08:28:13 -070011744 .destroy = intel_plane_destroy,
Matt Roper465c1202014-05-29 08:06:54 -070011745};
11746
11747static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11748 int pipe)
11749{
11750 struct intel_plane *primary;
11751 const uint32_t *intel_primary_formats;
11752 int num_formats;
11753
11754 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11755 if (primary == NULL)
11756 return NULL;
11757
11758 primary->can_scale = false;
11759 primary->max_downscale = 1;
11760 primary->pipe = pipe;
11761 primary->plane = pipe;
11762 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11763 primary->plane = !pipe;
11764
11765 if (INTEL_INFO(dev)->gen <= 3) {
11766 intel_primary_formats = intel_primary_formats_gen2;
11767 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11768 } else {
11769 intel_primary_formats = intel_primary_formats_gen4;
11770 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11771 }
11772
11773 drm_universal_plane_init(dev, &primary->base, 0,
11774 &intel_primary_plane_funcs,
11775 intel_primary_formats, num_formats,
11776 DRM_PLANE_TYPE_PRIMARY);
11777 return &primary->base;
11778}
11779
Matt Roper3d7d6512014-06-10 08:28:13 -070011780static int
11781intel_cursor_plane_disable(struct drm_plane *plane)
11782{
11783 if (!plane->fb)
11784 return 0;
11785
11786 BUG_ON(!plane->crtc);
11787
11788 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11789}
11790
11791static int
11792intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11793 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11794 unsigned int crtc_w, unsigned int crtc_h,
11795 uint32_t src_x, uint32_t src_y,
11796 uint32_t src_w, uint32_t src_h)
11797{
11798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11799 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11800 struct drm_i915_gem_object *obj = intel_fb->obj;
11801 struct drm_rect dest = {
11802 /* integer pixels */
11803 .x1 = crtc_x,
11804 .y1 = crtc_y,
11805 .x2 = crtc_x + crtc_w,
11806 .y2 = crtc_y + crtc_h,
11807 };
11808 struct drm_rect src = {
11809 /* 16.16 fixed point */
11810 .x1 = src_x,
11811 .y1 = src_y,
11812 .x2 = src_x + src_w,
11813 .y2 = src_y + src_h,
11814 };
11815 const struct drm_rect clip = {
11816 /* integer pixels */
11817 .x2 = intel_crtc->config.pipe_src_w,
11818 .y2 = intel_crtc->config.pipe_src_h,
11819 };
11820 bool visible;
11821 int ret;
11822
11823 ret = drm_plane_helper_check_update(plane, crtc, fb,
11824 &src, &dest, &clip,
11825 DRM_PLANE_HELPER_NO_SCALING,
11826 DRM_PLANE_HELPER_NO_SCALING,
11827 true, true, &visible);
11828 if (ret)
11829 return ret;
11830
11831 crtc->cursor_x = crtc_x;
11832 crtc->cursor_y = crtc_y;
11833 if (fb != crtc->cursor->fb) {
11834 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11835 } else {
11836 intel_crtc_update_cursor(crtc, visible);
11837 return 0;
11838 }
11839}
11840static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11841 .update_plane = intel_cursor_plane_update,
11842 .disable_plane = intel_cursor_plane_disable,
11843 .destroy = intel_plane_destroy,
11844};
11845
11846static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11847 int pipe)
11848{
11849 struct intel_plane *cursor;
11850
11851 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11852 if (cursor == NULL)
11853 return NULL;
11854
11855 cursor->can_scale = false;
11856 cursor->max_downscale = 1;
11857 cursor->pipe = pipe;
11858 cursor->plane = pipe;
11859
11860 drm_universal_plane_init(dev, &cursor->base, 0,
11861 &intel_cursor_plane_funcs,
11862 intel_cursor_formats,
11863 ARRAY_SIZE(intel_cursor_formats),
11864 DRM_PLANE_TYPE_CURSOR);
11865 return &cursor->base;
11866}
11867
Hannes Ederb358d0a2008-12-18 21:18:47 +010011868static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080011869{
Jani Nikulafbee40d2014-03-31 14:27:18 +030011870 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080011871 struct intel_crtc *intel_crtc;
Matt Roper3d7d6512014-06-10 08:28:13 -070011872 struct drm_plane *primary = NULL;
11873 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070011874 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080011875
Daniel Vetter955382f2013-09-19 14:05:45 +020011876 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080011877 if (intel_crtc == NULL)
11878 return;
11879
Matt Roper465c1202014-05-29 08:06:54 -070011880 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011881 if (!primary)
11882 goto fail;
11883
11884 cursor = intel_cursor_plane_create(dev, pipe);
11885 if (!cursor)
11886 goto fail;
11887
Matt Roper465c1202014-05-29 08:06:54 -070011888 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070011889 cursor, &intel_crtc_funcs);
11890 if (ret)
11891 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011892
11893 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080011894 for (i = 0; i < 256; i++) {
11895 intel_crtc->lut_r[i] = i;
11896 intel_crtc->lut_g[i] = i;
11897 intel_crtc->lut_b[i] = i;
11898 }
11899
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011900 /*
11901 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020011902 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011903 */
Jesse Barnes80824002009-09-10 15:28:06 -070011904 intel_crtc->pipe = pipe;
11905 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010011906 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080011907 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010011908 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070011909 }
11910
Chris Wilson4b0e3332014-05-30 16:35:26 +030011911 intel_crtc->cursor_base = ~0;
11912 intel_crtc->cursor_cntl = ~0;
11913
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080011914 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11915 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11916 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11917 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11918
Jesse Barnes79e53942008-11-07 14:24:08 -080011919 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020011920
11921 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011922 return;
11923
11924fail:
11925 if (primary)
11926 drm_plane_cleanup(primary);
11927 if (cursor)
11928 drm_plane_cleanup(cursor);
11929 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080011930}
11931
Jesse Barnes752aa882013-10-31 18:55:49 +020011932enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11933{
11934 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011935 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020011936
Rob Clark51fd3712013-11-19 12:10:12 -050011937 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020011938
11939 if (!encoder)
11940 return INVALID_PIPE;
11941
11942 return to_intel_crtc(encoder->crtc)->pipe;
11943}
11944
Carl Worth08d7b3d2009-04-29 14:43:54 -070011945int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000011946 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070011947{
Carl Worth08d7b3d2009-04-29 14:43:54 -070011948 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040011949 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020011950 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011951
Daniel Vetter1cff8f62012-04-24 09:55:08 +020011952 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11953 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011954
Rob Clark7707e652014-07-17 23:30:04 -040011955 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Carl Worth08d7b3d2009-04-29 14:43:54 -070011956
Rob Clark7707e652014-07-17 23:30:04 -040011957 if (!drmmode_crtc) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070011958 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030011959 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011960 }
11961
Rob Clark7707e652014-07-17 23:30:04 -040011962 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020011963 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011964
Daniel Vetterc05422d2009-08-11 16:05:30 +020011965 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011966}
11967
Daniel Vetter66a92782012-07-12 20:08:18 +020011968static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080011969{
Daniel Vetter66a92782012-07-12 20:08:18 +020011970 struct drm_device *dev = encoder->base.dev;
11971 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080011972 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080011973 int entry = 0;
11974
Daniel Vetter66a92782012-07-12 20:08:18 +020011975 list_for_each_entry(source_encoder,
11976 &dev->mode_config.encoder_list, base.head) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020011977 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020011978 index_mask |= (1 << entry);
11979
Jesse Barnes79e53942008-11-07 14:24:08 -080011980 entry++;
11981 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010011982
Jesse Barnes79e53942008-11-07 14:24:08 -080011983 return index_mask;
11984}
11985
Chris Wilson4d302442010-12-14 19:21:29 +000011986static bool has_edp_a(struct drm_device *dev)
11987{
11988 struct drm_i915_private *dev_priv = dev->dev_private;
11989
11990 if (!IS_MOBILE(dev))
11991 return false;
11992
11993 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11994 return false;
11995
Damien Lespiaue3589902014-02-07 19:12:50 +000011996 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000011997 return false;
11998
11999 return true;
12000}
12001
Damien Lespiauba0fbca2014-01-08 14:18:23 +000012002const char *intel_output_name(int output)
12003{
12004 static const char *names[] = {
12005 [INTEL_OUTPUT_UNUSED] = "Unused",
12006 [INTEL_OUTPUT_ANALOG] = "Analog",
12007 [INTEL_OUTPUT_DVO] = "DVO",
12008 [INTEL_OUTPUT_SDVO] = "SDVO",
12009 [INTEL_OUTPUT_LVDS] = "LVDS",
12010 [INTEL_OUTPUT_TVOUT] = "TV",
12011 [INTEL_OUTPUT_HDMI] = "HDMI",
12012 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12013 [INTEL_OUTPUT_EDP] = "eDP",
12014 [INTEL_OUTPUT_DSI] = "DSI",
12015 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12016 };
12017
12018 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12019 return "Invalid";
12020
12021 return names[output];
12022}
12023
Jesse Barnes84b4e042014-06-25 08:24:29 -070012024static bool intel_crt_present(struct drm_device *dev)
12025{
12026 struct drm_i915_private *dev_priv = dev->dev_private;
12027
12028 if (IS_ULT(dev))
12029 return false;
12030
12031 if (IS_CHERRYVIEW(dev))
12032 return false;
12033
12034 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12035 return false;
12036
12037 return true;
12038}
12039
Jesse Barnes79e53942008-11-07 14:24:08 -080012040static void intel_setup_outputs(struct drm_device *dev)
12041{
Eric Anholt725e30a2009-01-22 13:01:02 -080012042 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010012043 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012044 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080012045
Daniel Vetterc9093352013-06-06 22:22:47 +020012046 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012047
Jesse Barnes84b4e042014-06-25 08:24:29 -070012048 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020012049 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012050
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012051 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030012052 int found;
12053
12054 /* Haswell uses DDI functions to detect digital outputs */
12055 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12056 /* DDI A only supports eDP */
12057 if (found)
12058 intel_ddi_init(dev, PORT_A);
12059
12060 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12061 * register */
12062 found = I915_READ(SFUSE_STRAP);
12063
12064 if (found & SFUSE_STRAP_DDIB_DETECTED)
12065 intel_ddi_init(dev, PORT_B);
12066 if (found & SFUSE_STRAP_DDIC_DETECTED)
12067 intel_ddi_init(dev, PORT_C);
12068 if (found & SFUSE_STRAP_DDID_DETECTED)
12069 intel_ddi_init(dev, PORT_D);
12070 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012071 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012072 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020012073
12074 if (has_edp_a(dev))
12075 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012076
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012077 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080012078 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010012079 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012080 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012081 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012082 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012083 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012084 }
12085
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012086 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012087 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012088
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012089 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012090 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012091
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012092 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012093 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012094
Daniel Vetter270b3042012-10-27 15:52:05 +020012095 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012096 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070012097 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012098 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12099 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12100 PORT_B);
12101 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12102 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12103 }
12104
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012105 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12106 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12107 PORT_C);
12108 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012109 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012110 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053012111
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012112 if (IS_CHERRYVIEW(dev)) {
12113 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12114 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12115 PORT_D);
12116 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12117 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12118 }
12119 }
12120
Jani Nikula3cfca972013-08-27 15:12:26 +030012121 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080012122 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012123 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080012124
Paulo Zanonie2debe92013-02-18 19:00:27 -030012125 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012126 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012127 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012128 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12129 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012130 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012131 }
Ma Ling27185ae2009-08-24 13:50:23 +080012132
Imre Deake7281ea2013-05-08 13:14:08 +030012133 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012134 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080012135 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012136
12137 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012138
Paulo Zanonie2debe92013-02-18 19:00:27 -030012139 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012140 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012141 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012142 }
Ma Ling27185ae2009-08-24 13:50:23 +080012143
Paulo Zanonie2debe92013-02-18 19:00:27 -030012144 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012145
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012146 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12147 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012148 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012149 }
Imre Deake7281ea2013-05-08 13:14:08 +030012150 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012151 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080012152 }
Ma Ling27185ae2009-08-24 13:50:23 +080012153
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012154 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030012155 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012156 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070012157 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012158 intel_dvo_init(dev);
12159
Zhenyu Wang103a1962009-11-27 11:44:36 +080012160 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012161 intel_tv_init(dev);
12162
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070012163 intel_edp_psr_init(dev);
12164
Chris Wilson4ef69c72010-09-09 15:14:28 +010012165 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12166 encoder->base.possible_crtcs = encoder->crtc_mask;
12167 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020012168 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080012169 }
Chris Wilson47356eb2011-01-11 17:06:04 +000012170
Paulo Zanonidde86e22012-12-01 12:04:25 -020012171 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020012172
12173 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012174}
12175
12176static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12177{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012178 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080012179 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080012180
Daniel Vetteref2d6332014-02-10 18:00:38 +010012181 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012182 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010012183 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012184 drm_gem_object_unreference(&intel_fb->obj->base);
12185 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012186 kfree(intel_fb);
12187}
12188
12189static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000012190 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080012191 unsigned int *handle)
12192{
12193 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000012194 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012195
Chris Wilson05394f32010-11-08 19:18:58 +000012196 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080012197}
12198
12199static const struct drm_framebuffer_funcs intel_fb_funcs = {
12200 .destroy = intel_user_framebuffer_destroy,
12201 .create_handle = intel_user_framebuffer_create_handle,
12202};
12203
Daniel Vetterb5ea6422014-03-02 21:18:00 +010012204static int intel_framebuffer_init(struct drm_device *dev,
12205 struct intel_framebuffer *intel_fb,
12206 struct drm_mode_fb_cmd2 *mode_cmd,
12207 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080012208{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012209 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012210 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080012211 int ret;
12212
Daniel Vetterdd4916c2013-10-09 21:23:51 +020012213 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12214
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012215 if (obj->tiling_mode == I915_TILING_Y) {
12216 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010012217 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012218 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012219
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012220 if (mode_cmd->pitches[0] & 63) {
12221 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12222 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010012223 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012224 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012225
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012226 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12227 pitch_limit = 32*1024;
12228 } else if (INTEL_INFO(dev)->gen >= 4) {
12229 if (obj->tiling_mode)
12230 pitch_limit = 16*1024;
12231 else
12232 pitch_limit = 32*1024;
12233 } else if (INTEL_INFO(dev)->gen >= 3) {
12234 if (obj->tiling_mode)
12235 pitch_limit = 8*1024;
12236 else
12237 pitch_limit = 16*1024;
12238 } else
12239 /* XXX DSPC is limited to 4k tiled */
12240 pitch_limit = 8*1024;
12241
12242 if (mode_cmd->pitches[0] > pitch_limit) {
12243 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12244 obj->tiling_mode ? "tiled" : "linear",
12245 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012246 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012247 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012248
12249 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012250 mode_cmd->pitches[0] != obj->stride) {
12251 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12252 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012253 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012254 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012255
Ville Syrjälä57779d02012-10-31 17:50:14 +020012256 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012257 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020012258 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012259 case DRM_FORMAT_RGB565:
12260 case DRM_FORMAT_XRGB8888:
12261 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012262 break;
12263 case DRM_FORMAT_XRGB1555:
12264 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012265 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012266 DRM_DEBUG("unsupported pixel format: %s\n",
12267 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012268 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012269 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020012270 break;
12271 case DRM_FORMAT_XBGR8888:
12272 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012273 case DRM_FORMAT_XRGB2101010:
12274 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012275 case DRM_FORMAT_XBGR2101010:
12276 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012277 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012278 DRM_DEBUG("unsupported pixel format: %s\n",
12279 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012280 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012281 }
Jesse Barnesb5626742011-06-24 12:19:27 -070012282 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020012283 case DRM_FORMAT_YUYV:
12284 case DRM_FORMAT_UYVY:
12285 case DRM_FORMAT_YVYU:
12286 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012287 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012288 DRM_DEBUG("unsupported pixel format: %s\n",
12289 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012290 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012291 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012292 break;
12293 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012294 DRM_DEBUG("unsupported pixel format: %s\n",
12295 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010012296 return -EINVAL;
12297 }
12298
Ville Syrjälä90f9a332012-10-31 17:50:19 +020012299 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12300 if (mode_cmd->offsets[0] != 0)
12301 return -EINVAL;
12302
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012303 aligned_height = intel_align_height(dev, mode_cmd->height,
12304 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020012305 /* FIXME drm helper for size checks (especially planar formats)? */
12306 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12307 return -EINVAL;
12308
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012309 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12310 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020012311 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012312
Jesse Barnes79e53942008-11-07 14:24:08 -080012313 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12314 if (ret) {
12315 DRM_ERROR("framebuffer init failed %d\n", ret);
12316 return ret;
12317 }
12318
Jesse Barnes79e53942008-11-07 14:24:08 -080012319 return 0;
12320}
12321
Jesse Barnes79e53942008-11-07 14:24:08 -080012322static struct drm_framebuffer *
12323intel_user_framebuffer_create(struct drm_device *dev,
12324 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012325 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080012326{
Chris Wilson05394f32010-11-08 19:18:58 +000012327 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012328
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012329 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12330 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000012331 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010012332 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080012333
Chris Wilsond2dff872011-04-19 08:36:26 +010012334 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080012335}
12336
Daniel Vetter4520f532013-10-09 09:18:51 +020012337#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020012338static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020012339{
12340}
12341#endif
12342
Jesse Barnes79e53942008-11-07 14:24:08 -080012343static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080012344 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020012345 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080012346};
12347
Jesse Barnese70236a2009-09-21 10:42:27 -070012348/* Set up chip specific display functions */
12349static void intel_init_display(struct drm_device *dev)
12350{
12351 struct drm_i915_private *dev_priv = dev->dev_private;
12352
Daniel Vetteree9300b2013-06-03 22:40:22 +020012353 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12354 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030012355 else if (IS_CHERRYVIEW(dev))
12356 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020012357 else if (IS_VALLEYVIEW(dev))
12358 dev_priv->display.find_dpll = vlv_find_best_dpll;
12359 else if (IS_PINEVIEW(dev))
12360 dev_priv->display.find_dpll = pnv_find_best_dpll;
12361 else
12362 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12363
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012364 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012365 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012366 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012367 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020012368 dev_priv->display.crtc_enable = haswell_crtc_enable;
12369 dev_priv->display.crtc_disable = haswell_crtc_disable;
Daniel Vetterdf8ad702014-06-25 22:02:03 +030012370 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012371 dev_priv->display.update_primary_plane =
12372 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012373 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012374 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012375 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070012376 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012377 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12378 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012379 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012380 dev_priv->display.update_primary_plane =
12381 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012382 } else if (IS_VALLEYVIEW(dev)) {
12383 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012384 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012385 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12386 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12387 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12388 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012389 dev_priv->display.update_primary_plane =
12390 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012391 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012392 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012393 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070012394 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012395 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12396 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012397 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012398 dev_priv->display.update_primary_plane =
12399 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012400 }
Jesse Barnese70236a2009-09-21 10:42:27 -070012401
Jesse Barnese70236a2009-09-21 10:42:27 -070012402 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070012403 if (IS_VALLEYVIEW(dev))
12404 dev_priv->display.get_display_clock_speed =
12405 valleyview_get_display_clock_speed;
12406 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070012407 dev_priv->display.get_display_clock_speed =
12408 i945_get_display_clock_speed;
12409 else if (IS_I915G(dev))
12410 dev_priv->display.get_display_clock_speed =
12411 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012412 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012413 dev_priv->display.get_display_clock_speed =
12414 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012415 else if (IS_PINEVIEW(dev))
12416 dev_priv->display.get_display_clock_speed =
12417 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070012418 else if (IS_I915GM(dev))
12419 dev_priv->display.get_display_clock_speed =
12420 i915gm_get_display_clock_speed;
12421 else if (IS_I865G(dev))
12422 dev_priv->display.get_display_clock_speed =
12423 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020012424 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012425 dev_priv->display.get_display_clock_speed =
12426 i855_get_display_clock_speed;
12427 else /* 852, 830 */
12428 dev_priv->display.get_display_clock_speed =
12429 i830_get_display_clock_speed;
12430
Zhenyu Wang7f8a8562010-04-01 13:07:53 +080012431 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +010012432 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070012433 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080012434 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +080012435 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070012436 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080012437 dev_priv->display.write_eld = ironlake_write_eld;
Paulo Zanoni9a952a02014-03-07 20:12:34 -030012438 dev_priv->display.modeset_global_resources =
12439 snb_modeset_global_resources;
Jesse Barnes357555c2011-04-28 15:09:55 -070012440 } else if (IS_IVYBRIDGE(dev)) {
12441 /* FIXME: detect B0+ stepping and use auto training */
12442 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080012443 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +020012444 dev_priv->display.modeset_global_resources =
12445 ivb_modeset_global_resources;
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012446 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -030012447 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +080012448 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -020012449 dev_priv->display.modeset_global_resources =
12450 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -020012451 }
Jesse Barnes6067aae2011-04-28 15:04:31 -070012452 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080012453 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnes30a970c2013-11-04 13:48:12 -080012454 } else if (IS_VALLEYVIEW(dev)) {
12455 dev_priv->display.modeset_global_resources =
12456 valleyview_modeset_global_resources;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -040012457 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -070012458 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012459
12460 /* Default just returns -ENODEV to indicate unsupported */
12461 dev_priv->display.queue_flip = intel_default_queue_flip;
12462
12463 switch (INTEL_INFO(dev)->gen) {
12464 case 2:
12465 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12466 break;
12467
12468 case 3:
12469 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12470 break;
12471
12472 case 4:
12473 case 5:
12474 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12475 break;
12476
12477 case 6:
12478 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12479 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012480 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012481 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012482 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12483 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012484 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020012485
12486 intel_panel_init_backlight_funcs(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012487}
12488
Jesse Barnesb690e962010-07-19 13:53:12 -070012489/*
12490 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12491 * resume, or other times. This quirk makes sure that's the case for
12492 * affected systems.
12493 */
Akshay Joshi0206e352011-08-16 15:34:10 -040012494static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070012495{
12496 struct drm_i915_private *dev_priv = dev->dev_private;
12497
12498 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012499 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012500}
12501
Keith Packard435793d2011-07-12 14:56:22 -070012502/*
12503 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12504 */
12505static void quirk_ssc_force_disable(struct drm_device *dev)
12506{
12507 struct drm_i915_private *dev_priv = dev->dev_private;
12508 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012509 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070012510}
12511
Carsten Emde4dca20e2012-03-15 15:56:26 +010012512/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010012513 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12514 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010012515 */
12516static void quirk_invert_brightness(struct drm_device *dev)
12517{
12518 struct drm_i915_private *dev_priv = dev->dev_private;
12519 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012520 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012521}
12522
Scot Doyle9c72cc62014-07-03 23:27:50 +000012523/* Some VBT's incorrectly indicate no backlight is present */
12524static void quirk_backlight_present(struct drm_device *dev)
12525{
12526 struct drm_i915_private *dev_priv = dev->dev_private;
12527 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12528 DRM_INFO("applying backlight present quirk\n");
12529}
12530
Jesse Barnesb690e962010-07-19 13:53:12 -070012531struct intel_quirk {
12532 int device;
12533 int subsystem_vendor;
12534 int subsystem_device;
12535 void (*hook)(struct drm_device *dev);
12536};
12537
Egbert Eich5f85f1762012-10-14 15:46:38 +020012538/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12539struct intel_dmi_quirk {
12540 void (*hook)(struct drm_device *dev);
12541 const struct dmi_system_id (*dmi_id_list)[];
12542};
12543
12544static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12545{
12546 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12547 return 1;
12548}
12549
12550static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12551 {
12552 .dmi_id_list = &(const struct dmi_system_id[]) {
12553 {
12554 .callback = intel_dmi_reverse_brightness,
12555 .ident = "NCR Corporation",
12556 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12557 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12558 },
12559 },
12560 { } /* terminating entry */
12561 },
12562 .hook = quirk_invert_brightness,
12563 },
12564};
12565
Ben Widawskyc43b5632012-04-16 14:07:40 -070012566static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070012567 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040012568 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070012569
Jesse Barnesb690e962010-07-19 13:53:12 -070012570 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12571 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12572
Jesse Barnesb690e962010-07-19 13:53:12 -070012573 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12574 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12575
Keith Packard435793d2011-07-12 14:56:22 -070012576 /* Lenovo U160 cannot use SSC on LVDS */
12577 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020012578
12579 /* Sony Vaio Y cannot use SSC on LVDS */
12580 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010012581
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010012582 /* Acer Aspire 5734Z must invert backlight brightness */
12583 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12584
12585 /* Acer/eMachines G725 */
12586 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12587
12588 /* Acer/eMachines e725 */
12589 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12590
12591 /* Acer/Packard Bell NCL20 */
12592 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12593
12594 /* Acer Aspire 4736Z */
12595 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020012596
12597 /* Acer Aspire 5336 */
12598 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000012599
12600 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12601 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000012602
12603 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12604 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000012605
12606 /* HP Chromebook 14 (Celeron 2955U) */
12607 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070012608};
12609
12610static void intel_init_quirks(struct drm_device *dev)
12611{
12612 struct pci_dev *d = dev->pdev;
12613 int i;
12614
12615 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12616 struct intel_quirk *q = &intel_quirks[i];
12617
12618 if (d->device == q->device &&
12619 (d->subsystem_vendor == q->subsystem_vendor ||
12620 q->subsystem_vendor == PCI_ANY_ID) &&
12621 (d->subsystem_device == q->subsystem_device ||
12622 q->subsystem_device == PCI_ANY_ID))
12623 q->hook(dev);
12624 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020012625 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12626 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12627 intel_dmi_quirks[i].hook(dev);
12628 }
Jesse Barnesb690e962010-07-19 13:53:12 -070012629}
12630
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012631/* Disable the VGA plane that we never use */
12632static void i915_disable_vga(struct drm_device *dev)
12633{
12634 struct drm_i915_private *dev_priv = dev->dev_private;
12635 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012636 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012637
Ville Syrjälä2b37c612014-01-22 21:32:38 +020012638 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012639 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070012640 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012641 sr1 = inb(VGA_SR_DATA);
12642 outb(sr1 | 1<<5, VGA_SR_DATA);
12643 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12644 udelay(300);
12645
12646 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12647 POSTING_READ(vga_reg);
12648}
12649
Daniel Vetterf8175862012-04-10 15:50:11 +020012650void intel_modeset_init_hw(struct drm_device *dev)
12651{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030012652 intel_prepare_ddi(dev);
12653
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +030012654 if (IS_VALLEYVIEW(dev))
12655 vlv_update_cdclk(dev);
12656
Daniel Vetterf8175862012-04-10 15:50:11 +020012657 intel_init_clock_gating(dev);
12658
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012659 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020012660}
12661
Imre Deak7d708ee2013-04-17 14:04:50 +030012662void intel_modeset_suspend_hw(struct drm_device *dev)
12663{
12664 intel_suspend_hw(dev);
12665}
12666
Jesse Barnes79e53942008-11-07 14:24:08 -080012667void intel_modeset_init(struct drm_device *dev)
12668{
Jesse Barnes652c3932009-08-17 13:31:43 -070012669 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000012670 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012671 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080012672 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080012673
12674 drm_mode_config_init(dev);
12675
12676 dev->mode_config.min_width = 0;
12677 dev->mode_config.min_height = 0;
12678
Dave Airlie019d96c2011-09-29 16:20:42 +010012679 dev->mode_config.preferred_depth = 24;
12680 dev->mode_config.prefer_shadow = 1;
12681
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020012682 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080012683
Jesse Barnesb690e962010-07-19 13:53:12 -070012684 intel_init_quirks(dev);
12685
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030012686 intel_init_pm(dev);
12687
Ben Widawskye3c74752013-04-05 13:12:39 -070012688 if (INTEL_INFO(dev)->num_pipes == 0)
12689 return;
12690
Jesse Barnese70236a2009-09-21 10:42:27 -070012691 intel_init_display(dev);
12692
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012693 if (IS_GEN2(dev)) {
12694 dev->mode_config.max_width = 2048;
12695 dev->mode_config.max_height = 2048;
12696 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070012697 dev->mode_config.max_width = 4096;
12698 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080012699 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012700 dev->mode_config.max_width = 8192;
12701 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080012702 }
Damien Lespiau068be562014-03-28 14:17:49 +000012703
12704 if (IS_GEN2(dev)) {
12705 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12706 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12707 } else {
12708 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12709 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12710 }
12711
Ben Widawsky5d4545a2013-01-17 12:45:15 -080012712 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080012713
Zhao Yakui28c97732009-10-09 11:39:41 +080012714 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012715 INTEL_INFO(dev)->num_pipes,
12716 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080012717
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012718 for_each_pipe(pipe) {
12719 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000012720 for_each_sprite(pipe, sprite) {
12721 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012722 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030012723 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000012724 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012725 }
Jesse Barnes79e53942008-11-07 14:24:08 -080012726 }
12727
Jesse Barnesf42bb702013-12-16 16:34:23 -080012728 intel_init_dpio(dev);
12729
Daniel Vettere72f9fb2013-06-05 13:34:06 +020012730 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012731
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012732 /* Just disable it once at startup */
12733 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012734 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000012735
12736 /* Just in case the BIOS is doing something questionable. */
12737 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012738
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012739 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012740 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012741 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012742
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012743 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080012744 if (!crtc->active)
12745 continue;
12746
Jesse Barnes46f297f2014-03-07 08:57:48 -080012747 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080012748 * Note that reserving the BIOS fb up front prevents us
12749 * from stuffing other stolen allocations like the ring
12750 * on top. This prevents some ugliness at boot time, and
12751 * can even allow for smooth boot transitions if the BIOS
12752 * fb is large enough for the active pipe configuration.
12753 */
12754 if (dev_priv->display.get_plane_config) {
12755 dev_priv->display.get_plane_config(crtc,
12756 &crtc->plane_config);
12757 /*
12758 * If the fb is shared between multiple heads, we'll
12759 * just get the first one.
12760 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080012761 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012762 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080012763 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010012764}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080012765
Daniel Vetter7fad7982012-07-04 17:51:47 +020012766static void intel_enable_pipe_a(struct drm_device *dev)
12767{
12768 struct intel_connector *connector;
12769 struct drm_connector *crt = NULL;
12770 struct intel_load_detect_pipe load_detect_temp;
Rob Clark51fd3712013-11-19 12:10:12 -050012771 struct drm_modeset_acquire_ctx ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020012772
12773 /* We can't just switch on the pipe A, we need to set things up with a
12774 * proper mode and output configuration. As a gross hack, enable pipe A
12775 * by enabling the load detect pipe once. */
12776 list_for_each_entry(connector,
12777 &dev->mode_config.connector_list,
12778 base.head) {
12779 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12780 crt = &connector->base;
12781 break;
12782 }
12783 }
12784
12785 if (!crt)
12786 return;
12787
Rob Clark51fd3712013-11-19 12:10:12 -050012788 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12789 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
Daniel Vetter7fad7982012-07-04 17:51:47 +020012790
12791
12792}
12793
Daniel Vetterfa555832012-10-10 23:14:00 +020012794static bool
12795intel_check_plane_mapping(struct intel_crtc *crtc)
12796{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012797 struct drm_device *dev = crtc->base.dev;
12798 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012799 u32 reg, val;
12800
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012801 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020012802 return true;
12803
12804 reg = DSPCNTR(!crtc->plane);
12805 val = I915_READ(reg);
12806
12807 if ((val & DISPLAY_PLANE_ENABLE) &&
12808 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12809 return false;
12810
12811 return true;
12812}
12813
Daniel Vetter24929352012-07-02 20:28:59 +020012814static void intel_sanitize_crtc(struct intel_crtc *crtc)
12815{
12816 struct drm_device *dev = crtc->base.dev;
12817 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012818 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020012819
Daniel Vetter24929352012-07-02 20:28:59 +020012820 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020012821 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020012822 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12823
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012824 /* restore vblank interrupts to correct state */
12825 if (crtc->active)
12826 drm_vblank_on(dev, crtc->pipe);
12827 else
12828 drm_vblank_off(dev, crtc->pipe);
12829
Daniel Vetter24929352012-07-02 20:28:59 +020012830 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020012831 * disable the crtc (and hence change the state) if it is wrong. Note
12832 * that gen4+ has a fixed plane -> pipe mapping. */
12833 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020012834 struct intel_connector *connector;
12835 bool plane;
12836
Daniel Vetter24929352012-07-02 20:28:59 +020012837 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12838 crtc->base.base.id);
12839
12840 /* Pipe has the wrong plane attached and the plane is active.
12841 * Temporarily change the plane mapping and disable everything
12842 * ... */
12843 plane = crtc->plane;
12844 crtc->plane = !plane;
Daniel Vetter9c8958b2014-07-14 19:35:31 +020012845 crtc->primary_enabled = true;
Daniel Vetter24929352012-07-02 20:28:59 +020012846 dev_priv->display.crtc_disable(&crtc->base);
12847 crtc->plane = plane;
12848
12849 /* ... and break all links. */
12850 list_for_each_entry(connector, &dev->mode_config.connector_list,
12851 base.head) {
12852 if (connector->encoder->base.crtc != &crtc->base)
12853 continue;
12854
Egbert Eich7f1950f2014-04-25 10:56:22 +020012855 connector->base.dpms = DRM_MODE_DPMS_OFF;
12856 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020012857 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020012858 /* multiple connectors may have the same encoder:
12859 * handle them and break crtc link separately */
12860 list_for_each_entry(connector, &dev->mode_config.connector_list,
12861 base.head)
12862 if (connector->encoder->base.crtc == &crtc->base) {
12863 connector->encoder->base.crtc = NULL;
12864 connector->encoder->connectors_active = false;
12865 }
Daniel Vetter24929352012-07-02 20:28:59 +020012866
12867 WARN_ON(crtc->active);
12868 crtc->base.enabled = false;
12869 }
Daniel Vetter24929352012-07-02 20:28:59 +020012870
Daniel Vetter7fad7982012-07-04 17:51:47 +020012871 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12872 crtc->pipe == PIPE_A && !crtc->active) {
12873 /* BIOS forgot to enable pipe A, this mostly happens after
12874 * resume. Force-enable the pipe to fix this, the update_dpms
12875 * call below we restore the pipe to the right state, but leave
12876 * the required bits on. */
12877 intel_enable_pipe_a(dev);
12878 }
12879
Daniel Vetter24929352012-07-02 20:28:59 +020012880 /* Adjust the state of the output pipe according to whether we
12881 * have active connectors/encoders. */
12882 intel_crtc_update_dpms(&crtc->base);
12883
12884 if (crtc->active != crtc->base.enabled) {
12885 struct intel_encoder *encoder;
12886
12887 /* This can happen either due to bugs in the get_hw_state
12888 * functions or because the pipe is force-enabled due to the
12889 * pipe A quirk. */
12890 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12891 crtc->base.base.id,
12892 crtc->base.enabled ? "enabled" : "disabled",
12893 crtc->active ? "enabled" : "disabled");
12894
12895 crtc->base.enabled = crtc->active;
12896
12897 /* Because we only establish the connector -> encoder ->
12898 * crtc links if something is active, this means the
12899 * crtc is now deactivated. Break the links. connector
12900 * -> encoder links are only establish when things are
12901 * actually up, hence no need to break them. */
12902 WARN_ON(crtc->active);
12903
12904 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12905 WARN_ON(encoder->connectors_active);
12906 encoder->base.crtc = NULL;
12907 }
12908 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020012909
12910 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010012911 /*
12912 * We start out with underrun reporting disabled to avoid races.
12913 * For correct bookkeeping mark this on active crtcs.
12914 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020012915 * Also on gmch platforms we dont have any hardware bits to
12916 * disable the underrun reporting. Which means we need to start
12917 * out with underrun reporting disabled also on inactive pipes,
12918 * since otherwise we'll complain about the garbage we read when
12919 * e.g. coming up after runtime pm.
12920 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010012921 * No protection against concurrent access is required - at
12922 * worst a fifo underrun happens which also sets this to false.
12923 */
12924 crtc->cpu_fifo_underrun_disabled = true;
12925 crtc->pch_fifo_underrun_disabled = true;
Ville Syrjälä80715b22014-05-15 20:23:23 +030012926
12927 update_scanline_offset(crtc);
Daniel Vetter4cc31482014-03-24 00:01:41 +010012928 }
Daniel Vetter24929352012-07-02 20:28:59 +020012929}
12930
12931static void intel_sanitize_encoder(struct intel_encoder *encoder)
12932{
12933 struct intel_connector *connector;
12934 struct drm_device *dev = encoder->base.dev;
12935
12936 /* We need to check both for a crtc link (meaning that the
12937 * encoder is active and trying to read from a pipe) and the
12938 * pipe itself being active. */
12939 bool has_active_crtc = encoder->base.crtc &&
12940 to_intel_crtc(encoder->base.crtc)->active;
12941
12942 if (encoder->connectors_active && !has_active_crtc) {
12943 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12944 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012945 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020012946
12947 /* Connector is active, but has no active pipe. This is
12948 * fallout from our resume register restoring. Disable
12949 * the encoder manually again. */
12950 if (encoder->base.crtc) {
12951 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12952 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012953 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020012954 encoder->disable(encoder);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030012955 if (encoder->post_disable)
12956 encoder->post_disable(encoder);
Daniel Vetter24929352012-07-02 20:28:59 +020012957 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020012958 encoder->base.crtc = NULL;
12959 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020012960
12961 /* Inconsistent output/port/pipe state happens presumably due to
12962 * a bug in one of the get_hw_state functions. Or someplace else
12963 * in our code, like the register restore mess on resume. Clamp
12964 * things to off as a safer default. */
12965 list_for_each_entry(connector,
12966 &dev->mode_config.connector_list,
12967 base.head) {
12968 if (connector->encoder != encoder)
12969 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020012970 connector->base.dpms = DRM_MODE_DPMS_OFF;
12971 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020012972 }
12973 }
12974 /* Enabled encoders without active connectors will be fixed in
12975 * the crtc fixup. */
12976}
12977
Imre Deak04098752014-02-18 00:02:16 +020012978void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012979{
12980 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012981 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010012982
Imre Deak04098752014-02-18 00:02:16 +020012983 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12984 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12985 i915_disable_vga(dev);
12986 }
12987}
12988
12989void i915_redisable_vga(struct drm_device *dev)
12990{
12991 struct drm_i915_private *dev_priv = dev->dev_private;
12992
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030012993 /* This function can be called both from intel_modeset_setup_hw_state or
12994 * at a very early point in our resume sequence, where the power well
12995 * structures are not yet restored. Since this function is at a very
12996 * paranoid "someone might have enabled VGA while we were not looking"
12997 * level, just check if the power well is enabled instead of trying to
12998 * follow the "don't touch the power well if we don't need it" policy
12999 * the rest of the driver uses. */
Imre Deak04098752014-02-18 00:02:16 +020013000 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013001 return;
13002
Imre Deak04098752014-02-18 00:02:16 +020013003 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013004}
13005
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013006static bool primary_get_hw_state(struct intel_crtc *crtc)
13007{
13008 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13009
13010 if (!crtc->active)
13011 return false;
13012
13013 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13014}
13015
Daniel Vetter30e984d2013-06-05 13:34:17 +020013016static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020013017{
13018 struct drm_i915_private *dev_priv = dev->dev_private;
13019 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020013020 struct intel_crtc *crtc;
13021 struct intel_encoder *encoder;
13022 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020013023 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020013024
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013025 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010013026 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020013027
Daniel Vetter99535992014-04-13 12:00:33 +020013028 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13029
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013030 crtc->active = dev_priv->display.get_pipe_config(crtc,
13031 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013032
13033 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013034 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020013035
13036 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13037 crtc->base.base.id,
13038 crtc->active ? "enabled" : "disabled");
13039 }
13040
Daniel Vetter53589012013-06-05 13:34:16 +020013041 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13042 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13043
13044 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13045 pll->active = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013046 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020013047 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13048 pll->active++;
13049 }
13050 pll->refcount = pll->active;
13051
Daniel Vetter35c95372013-07-17 06:55:04 +020013052 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13053 pll->name, pll->refcount, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013054
13055 if (pll->refcount)
13056 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020013057 }
13058
Daniel Vetter24929352012-07-02 20:28:59 +020013059 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
13060 base.head) {
13061 pipe = 0;
13062
13063 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070013064 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13065 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010013066 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013067 } else {
13068 encoder->base.crtc = NULL;
13069 }
13070
13071 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013072 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020013073 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013074 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013075 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013076 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020013077 }
13078
13079 list_for_each_entry(connector, &dev->mode_config.connector_list,
13080 base.head) {
13081 if (connector->get_hw_state(connector)) {
13082 connector->base.dpms = DRM_MODE_DPMS_ON;
13083 connector->encoder->connectors_active = true;
13084 connector->base.encoder = &connector->encoder->base;
13085 } else {
13086 connector->base.dpms = DRM_MODE_DPMS_OFF;
13087 connector->base.encoder = NULL;
13088 }
13089 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13090 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030013091 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013092 connector->base.encoder ? "enabled" : "disabled");
13093 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020013094}
13095
13096/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13097 * and i915 state tracking structures. */
13098void intel_modeset_setup_hw_state(struct drm_device *dev,
13099 bool force_restore)
13100{
13101 struct drm_i915_private *dev_priv = dev->dev_private;
13102 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013103 struct intel_crtc *crtc;
13104 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020013105 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013106
13107 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020013108
Jesse Barnesbabea612013-06-26 18:57:38 +030013109 /*
13110 * Now that we have the config, copy it to each CRTC struct
13111 * Note that this could go away if we move to using crtc_config
13112 * checking everywhere.
13113 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013114 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020013115 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080013116 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030013117 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13118 crtc->base.base.id);
13119 drm_mode_debug_printmodeline(&crtc->base.mode);
13120 }
13121 }
13122
Daniel Vetter24929352012-07-02 20:28:59 +020013123 /* HW state is read out, now we need to sanitize this mess. */
13124 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
13125 base.head) {
13126 intel_sanitize_encoder(encoder);
13127 }
13128
13129 for_each_pipe(pipe) {
13130 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13131 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020013132 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020013133 }
Daniel Vetter9a935852012-07-05 22:34:27 +020013134
Daniel Vetter35c95372013-07-17 06:55:04 +020013135 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13136 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13137
13138 if (!pll->on || pll->active)
13139 continue;
13140
13141 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13142
13143 pll->disable(dev_priv, pll);
13144 pll->on = false;
13145 }
13146
Ville Syrjälä96f90c52013-12-05 15:51:38 +020013147 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030013148 ilk_wm_get_hw_state(dev);
13149
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013150 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030013151 i915_redisable_vga(dev);
13152
Daniel Vetterf30da182013-04-11 20:22:50 +020013153 /*
13154 * We need to use raw interfaces for restoring state to avoid
13155 * checking (bogus) intermediate states.
13156 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013157 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070013158 struct drm_crtc *crtc =
13159 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020013160
13161 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
Matt Roperf4510a22014-04-01 15:22:40 -070013162 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013163 }
13164 } else {
13165 intel_modeset_update_staged_output_state(dev);
13166 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013167
13168 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010013169}
13170
13171void intel_modeset_gem_init(struct drm_device *dev)
13172{
Jesse Barnes484b41d2014-03-07 08:57:55 -080013173 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070013174 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013175
Imre Deakae484342014-03-31 15:10:44 +030013176 mutex_lock(&dev->struct_mutex);
13177 intel_init_gt_powersave(dev);
13178 mutex_unlock(&dev->struct_mutex);
13179
Chris Wilson1833b132012-05-09 11:56:28 +010013180 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020013181
13182 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080013183
13184 /*
13185 * Make sure any fbs we allocated at startup are properly
13186 * pinned & fenced. When we do the allocation it's too early
13187 * for this.
13188 */
13189 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010013190 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070013191 obj = intel_fb_obj(c->primary->fb);
13192 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080013193 continue;
13194
Matt Roper2ff8fde2014-07-08 07:50:07 -070013195 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080013196 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13197 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100013198 drm_framebuffer_unreference(c->primary->fb);
13199 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013200 }
13201 }
13202 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013203}
13204
Imre Deak4932e2c2014-02-11 17:12:48 +020013205void intel_connector_unregister(struct intel_connector *intel_connector)
13206{
13207 struct drm_connector *connector = &intel_connector->base;
13208
13209 intel_panel_destroy_backlight(connector);
Thomas Wood34ea3d32014-05-29 16:57:41 +010013210 drm_connector_unregister(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020013211}
13212
Jesse Barnes79e53942008-11-07 14:24:08 -080013213void intel_modeset_cleanup(struct drm_device *dev)
13214{
Jesse Barnes652c3932009-08-17 13:31:43 -070013215 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid9255d52013-09-26 20:05:59 -030013216 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070013217
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013218 /*
13219 * Interrupts and polling as the first thing to avoid creating havoc.
13220 * Too much stuff here (turning of rps, connectors, ...) would
13221 * experience fancy races otherwise.
13222 */
13223 drm_irq_uninstall(dev);
13224 cancel_work_sync(&dev_priv->hotplug_work);
Jesse Barneseb21b922014-06-20 11:57:33 -070013225 dev_priv->pm._irqs_disabled = true;
13226
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013227 /*
13228 * Due to the hpd irq storm handling the hotplug work can re-arm the
13229 * poll handlers. Hence disable polling after hpd handling is shut down.
13230 */
Keith Packardf87ea762010-10-03 19:36:26 -070013231 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013232
Jesse Barnes652c3932009-08-17 13:31:43 -070013233 mutex_lock(&dev->struct_mutex);
13234
Jesse Barnes723bfd72010-10-07 16:01:13 -070013235 intel_unregister_dsm_handler();
13236
Chris Wilson973d04f2011-07-08 12:22:37 +010013237 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070013238
Daniel Vetter8090c6b2012-06-24 16:42:32 +020013239 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000013240
Daniel Vetter930ebb42012-06-29 23:32:16 +020013241 ironlake_teardown_rc6(dev);
13242
Kristian Høgsberg69341a52009-11-11 12:19:17 -050013243 mutex_unlock(&dev->struct_mutex);
13244
Chris Wilson1630fe72011-07-08 12:22:42 +010013245 /* flush any delayed tasks or pending work */
13246 flush_scheduled_work();
13247
Jani Nikuladb31af12013-11-08 16:48:53 +020013248 /* destroy the backlight and sysfs files before encoders/connectors */
13249 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020013250 struct intel_connector *intel_connector;
13251
13252 intel_connector = to_intel_connector(connector);
13253 intel_connector->unregister(intel_connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020013254 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030013255
Jesse Barnes79e53942008-11-07 14:24:08 -080013256 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010013257
13258 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030013259
13260 mutex_lock(&dev->struct_mutex);
13261 intel_cleanup_gt_powersave(dev);
13262 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013263}
13264
Dave Airlie28d52042009-09-21 14:33:58 +100013265/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080013266 * Return which encoder is currently attached for connector.
13267 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010013268struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080013269{
Chris Wilsondf0e9242010-09-09 16:20:55 +010013270 return &intel_attached_encoder(connector)->base;
13271}
Jesse Barnes79e53942008-11-07 14:24:08 -080013272
Chris Wilsondf0e9242010-09-09 16:20:55 +010013273void intel_connector_attach_encoder(struct intel_connector *connector,
13274 struct intel_encoder *encoder)
13275{
13276 connector->encoder = encoder;
13277 drm_mode_connector_attach_encoder(&connector->base,
13278 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080013279}
Dave Airlie28d52042009-09-21 14:33:58 +100013280
13281/*
13282 * set vga decode state - true == enable VGA decode
13283 */
13284int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13285{
13286 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000013287 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100013288 u16 gmch_ctrl;
13289
Chris Wilson75fa0412014-02-07 18:37:02 -020013290 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13291 DRM_ERROR("failed to read control word\n");
13292 return -EIO;
13293 }
13294
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020013295 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13296 return 0;
13297
Dave Airlie28d52042009-09-21 14:33:58 +100013298 if (state)
13299 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13300 else
13301 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020013302
13303 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13304 DRM_ERROR("failed to write control word\n");
13305 return -EIO;
13306 }
13307
Dave Airlie28d52042009-09-21 14:33:58 +100013308 return 0;
13309}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013310
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013311struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013312
13313 u32 power_well_driver;
13314
Chris Wilson63b66e52013-08-08 15:12:06 +020013315 int num_transcoders;
13316
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013317 struct intel_cursor_error_state {
13318 u32 control;
13319 u32 position;
13320 u32 base;
13321 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010013322 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013323
13324 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013325 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013326 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030013327 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010013328 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013329
13330 struct intel_plane_error_state {
13331 u32 control;
13332 u32 stride;
13333 u32 size;
13334 u32 pos;
13335 u32 addr;
13336 u32 surface;
13337 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010013338 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020013339
13340 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013341 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020013342 enum transcoder cpu_transcoder;
13343
13344 u32 conf;
13345
13346 u32 htotal;
13347 u32 hblank;
13348 u32 hsync;
13349 u32 vtotal;
13350 u32 vblank;
13351 u32 vsync;
13352 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013353};
13354
13355struct intel_display_error_state *
13356intel_display_capture_error_state(struct drm_device *dev)
13357{
Jani Nikulafbee40d2014-03-31 14:27:18 +030013358 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013359 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020013360 int transcoders[] = {
13361 TRANSCODER_A,
13362 TRANSCODER_B,
13363 TRANSCODER_C,
13364 TRANSCODER_EDP,
13365 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013366 int i;
13367
Chris Wilson63b66e52013-08-08 15:12:06 +020013368 if (INTEL_INFO(dev)->num_pipes == 0)
13369 return NULL;
13370
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013371 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013372 if (error == NULL)
13373 return NULL;
13374
Imre Deak190be112013-11-25 17:15:31 +020013375 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013376 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13377
Damien Lespiau52331302012-08-15 19:23:25 +010013378 for_each_pipe(i) {
Imre Deakddf9c532013-11-27 22:02:02 +020013379 error->pipe[i].power_domain_on =
Imre Deakbfafe932014-06-05 20:31:47 +030013380 intel_display_power_enabled_unlocked(dev_priv,
13381 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020013382 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013383 continue;
13384
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030013385 error->cursor[i].control = I915_READ(CURCNTR(i));
13386 error->cursor[i].position = I915_READ(CURPOS(i));
13387 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013388
13389 error->plane[i].control = I915_READ(DSPCNTR(i));
13390 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013391 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030013392 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013393 error->plane[i].pos = I915_READ(DSPPOS(i));
13394 }
Paulo Zanonica291362013-03-06 20:03:14 -030013395 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13396 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013397 if (INTEL_INFO(dev)->gen >= 4) {
13398 error->plane[i].surface = I915_READ(DSPSURF(i));
13399 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13400 }
13401
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013402 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030013403
Sonika Jindal3abfce72014-07-21 15:23:43 +053013404 if (HAS_GMCH_DISPLAY(dev))
Imre Deakf301b1e2014-04-18 15:55:04 +030013405 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020013406 }
13407
13408 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13409 if (HAS_DDI(dev_priv->dev))
13410 error->num_transcoders++; /* Account for eDP. */
13411
13412 for (i = 0; i < error->num_transcoders; i++) {
13413 enum transcoder cpu_transcoder = transcoders[i];
13414
Imre Deakddf9c532013-11-27 22:02:02 +020013415 error->transcoder[i].power_domain_on =
Imre Deakbfafe932014-06-05 20:31:47 +030013416 intel_display_power_enabled_unlocked(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020013417 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013418 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013419 continue;
13420
Chris Wilson63b66e52013-08-08 15:12:06 +020013421 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13422
13423 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13424 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13425 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13426 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13427 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13428 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13429 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013430 }
13431
13432 return error;
13433}
13434
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013435#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13436
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013437void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013438intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013439 struct drm_device *dev,
13440 struct intel_display_error_state *error)
13441{
13442 int i;
13443
Chris Wilson63b66e52013-08-08 15:12:06 +020013444 if (!error)
13445 return;
13446
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013447 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020013448 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013449 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013450 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010013451 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013452 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020013453 err_printf(m, " Power: %s\n",
13454 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013455 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030013456 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013457
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013458 err_printf(m, "Plane [%d]:\n", i);
13459 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13460 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013461 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013462 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13463 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013464 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030013465 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013466 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013467 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013468 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13469 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013470 }
13471
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013472 err_printf(m, "Cursor [%d]:\n", i);
13473 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13474 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13475 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013476 }
Chris Wilson63b66e52013-08-08 15:12:06 +020013477
13478 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010013479 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020013480 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013481 err_printf(m, " Power: %s\n",
13482 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020013483 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13484 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13485 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13486 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13487 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13488 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13489 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13490 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013491}