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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070042#include <drm/drm_plane_helper.h>
43#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080044#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080045
Matt Roper465c1202014-05-29 08:06:54 -070046/* Primary plane formats supported by all gen */
47#define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53/* Primary plane formats for gen <= 3 */
54static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58};
59
60/* Primary plane formats for gen >= 4 */
61static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69};
70
Matt Roper3d7d6512014-06-10 08:28:13 -070071/* Cursor formats */
72static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74};
75
Chon Ming Leeef9348c2014-04-09 13:28:18 +030076#define DIV_ROUND_CLOSEST_ULL(ll, d) \
Matt Roper465c1202014-05-29 08:06:54 -070077({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
Chon Ming Leeef9348c2014-04-09 13:28:18 +030078
Daniel Vettercc365132014-06-18 13:59:13 +020079static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +010081static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080082
Jesse Barnesf1f644d2013-06-27 00:39:25 +030083static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030085static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030087
Damien Lespiaue7457a92013-08-08 22:28:59 +010088static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080090static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020094static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020096static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -070097 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +020099static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +0200100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +0200102static void vlv_prepare_pll(struct intel_crtc *crtc);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +0300103static void chv_prepare_pll(struct intel_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100104
Dave Airlie0e32b392014-05-02 14:02:48 +1000105static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106{
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111}
112
Jesse Barnes79e53942008-11-07 14:24:08 -0800113typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400114 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800115} intel_range_t;
116
117typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400118 int dot_limit;
119 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800120} intel_p2_t;
121
Ma Lingd4906092009-03-18 20:13:27 +0800122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800126};
Jesse Barnes79e53942008-11-07 14:24:08 -0800127
Daniel Vetterd2acd212012-10-20 20:57:43 +0200128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
Chris Wilson021357a2010-09-07 20:54:59 +0100138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
Chris Wilson8b99e682010-10-13 09:59:17 +0100141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100146}
147
Daniel Vetter5d536e22013-07-06 12:52:06 +0200148static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400149 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200150 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200151 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700159};
160
Daniel Vetter5d536e22013-07-06 12:52:06 +0200161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200163 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200164 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
Keith Packarde4b36692009-06-05 19:22:17 -0700174static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400175 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200176 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200177 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700185};
Eric Anholt273e27c2011-03-30 13:01:10 -0700186
Keith Packarde4b36692009-06-05 19:22:17 -0700187static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700211};
212
Eric Anholt273e27c2011-03-30 13:01:10 -0700213
Keith Packarde4b36692009-06-05 19:22:17 -0700214static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800226 },
Keith Packarde4b36692009-06-05 19:22:17 -0700227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800253 },
Keith Packarde4b36692009-06-05 19:22:17 -0700254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800267 },
Keith Packarde4b36692009-06-05 19:22:17 -0700268};
269
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500270static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700276 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700283};
284
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500285static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700296};
297
Eric Anholt273e27c2011-03-30 13:01:10 -0700298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800303static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700314};
315
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800316static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800340};
341
Eric Anholt273e27c2011-03-30 13:01:10 -0700342/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400351 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400364 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800367};
368
Ville Syrjälädc730512013-09-24 21:26:30 +0300369static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200377 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700378 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300381 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700383};
384
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300401static void vlv_clock(int refclk, intel_clock_t *clock)
402{
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300409}
410
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300411/**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415{
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424}
425
Chris Wilson1b894b52010-12-14 20:04:54 +0000426static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800428{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800429 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800430 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100433 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000434 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000439 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200444 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800445 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800446
447 return limit;
448}
449
Ma Ling044c7c42009-03-18 20:13:23 +0800450static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451{
452 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100456 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700457 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800458 else
Keith Packarde4b36692009-06-05 19:22:17 -0700459 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700462 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700464 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800465 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700466 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800467
468 return limit;
469}
470
Chris Wilson1b894b52010-12-14 20:04:54 +0000471static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800472{
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
Eric Anholtbad720f2009-10-22 16:11:14 -0700476 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000477 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800478 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800479 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500480 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500482 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800483 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500484 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700487 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300488 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700496 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700498 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200499 else
500 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800501 }
502 return limit;
503}
504
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500505/* m1 is reserved as 0 in Pineview, n is a ring counter */
506static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800507{
Shaohua Li21778322009-02-23 15:19:16 +0800508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800514}
515
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200516static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517{
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519}
520
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200521static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800522{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200523 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800524 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800529}
530
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300531static void chv_clock(int refclk, intel_clock_t *clock)
532{
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540}
541
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
Chris Wilson1b894b52010-12-14 20:04:54 +0000548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800551{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400555 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400557 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400559 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
Jesse Barnes79e53942008-11-07 14:24:08 -0800572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400573 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400578 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800579
580 return true;
581}
582
Ma Lingd4906092009-03-18 20:13:27 +0800583static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200584i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800587{
588 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800589 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800590 int err = target;
591
Daniel Vettera210b022012-11-26 17:22:08 +0100592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800593 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800597 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100598 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
Akshay Joshi0206e352011-08-16 15:34:10 -0400609 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800610
Zhao Yakui42158662009-11-20 11:24:18 +0800611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200615 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800621 int this_err;
622
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200623 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800626 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642}
643
Ma Lingd4906092009-03-18 20:13:27 +0800644static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200645pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200648{
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701}
702
Ma Lingd4906092009-03-18 20:13:27 +0800703static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200704g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800707{
708 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800709 intel_clock_t clock;
710 int max_n;
711 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100717 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200730 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200732 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200741 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800744 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000745
746 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800757 return found;
758}
Ma Lingd4906092009-03-18 20:13:27 +0800759
Zhenyu Wang2c072452009-06-05 15:38:42 +0800760static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200761vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700764{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300765 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300766 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300767 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300770 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700771
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700775
776 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300781 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700782 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300784 unsigned int ppm, diff;
785
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300788
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300789 vlv_clock(refclk, &clock);
790
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300793 continue;
794
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300799 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300800 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300801 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300802 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300803
Ville Syrjäläc6861222013-09-24 21:26:21 +0300804 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300805 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300806 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300807 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700808 }
809 }
810 }
811 }
812 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700813
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300814 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700815}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700816
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300817static bool
818chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821{
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867}
868
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300869bool intel_crtc_active(struct drm_crtc *crtc)
870{
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100876 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300877 * as Haswell has gained clock readout/fastboot support.
878 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000879 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300880 * properly reconstruct framebuffers.
881 */
Matt Roperf4510a22014-04-01 15:22:40 -0700882 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100883 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300884}
885
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200886enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888{
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
Daniel Vetter3b117c82013-04-17 20:15:07 +0200892 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200893}
894
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200895static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
Paulo Zanonia928d532012-05-04 17:18:15 -0300896{
897 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
Jesse Barnes93937072014-04-04 16:12:09 -0700903 WARN(1, "vblank wait timed out\n");
Paulo Zanonia928d532012-05-04 17:18:15 -0300904}
905
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700906/**
907 * intel_wait_for_vblank - wait for vblank on a given pipe
908 * @dev: drm device
909 * @pipe: pipe to wait for
910 *
911 * Wait for vblank to occur on a given pipe. Needed for various bits of
912 * mode setting code.
913 */
914void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800915{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700916 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800917 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700918
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200919 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
920 g4x_wait_for_vblank(dev, pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300921 return;
922 }
923
Chris Wilson300387c2010-09-05 20:25:43 +0100924 /* Clear existing vblank status. Note this will clear any other
925 * sticky status fields as well.
926 *
927 * This races with i915_driver_irq_handler() with the result
928 * that either function could miss a vblank event. Here it is not
929 * fatal, as we will either wait upon the next vblank interrupt or
930 * timeout. Generally speaking intel_wait_for_vblank() is only
931 * called during modeset at which time the GPU should be idle and
932 * should *not* be performing page flips and thus not waiting on
933 * vblanks...
934 * Currently, the result of us stealing a vblank from the irq
935 * handler is that a single frame will be skipped during swapbuffers.
936 */
937 I915_WRITE(pipestat_reg,
938 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
939
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700940 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100941 if (wait_for(I915_READ(pipestat_reg) &
942 PIPE_VBLANK_INTERRUPT_STATUS,
943 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700944 DRM_DEBUG_KMS("vblank wait timed out\n");
945}
946
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300947static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
948{
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 reg = PIPEDSL(pipe);
951 u32 line1, line2;
952 u32 line_mask;
953
954 if (IS_GEN2(dev))
955 line_mask = DSL_LINEMASK_GEN2;
956 else
957 line_mask = DSL_LINEMASK_GEN3;
958
959 line1 = I915_READ(reg) & line_mask;
960 mdelay(5);
961 line2 = I915_READ(reg) & line_mask;
962
963 return line1 == line2;
964}
965
Keith Packardab7ad7f2010-10-03 00:33:06 -0700966/*
967 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700968 * @dev: drm device
969 * @pipe: pipe to wait for
970 *
971 * After disabling a pipe, we can't wait for vblank in the usual way,
972 * spinning on the vblank interrupt status bit, since we won't actually
973 * see an interrupt when the pipe is disabled.
974 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700975 * On Gen4 and above:
976 * wait for the pipe register state bit to turn off
977 *
978 * Otherwise:
979 * wait for the display line value to settle (it usually
980 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100981 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700982 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100983void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700984{
985 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200986 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
987 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700988
Keith Packardab7ad7f2010-10-03 00:33:06 -0700989 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200990 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700991
Keith Packardab7ad7f2010-10-03 00:33:06 -0700992 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100993 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
994 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200995 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700996 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700997 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300998 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200999 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001000 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001001}
1002
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001003/*
1004 * ibx_digital_port_connected - is the specified port connected?
1005 * @dev_priv: i915 private structure
1006 * @port: the port to test
1007 *
1008 * Returns true if @port is connected, false otherwise.
1009 */
1010bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1011 struct intel_digital_port *port)
1012{
1013 u32 bit;
1014
Damien Lespiauc36346e2012-12-13 16:09:03 +00001015 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +02001016 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001017 case PORT_B:
1018 bit = SDE_PORTB_HOTPLUG;
1019 break;
1020 case PORT_C:
1021 bit = SDE_PORTC_HOTPLUG;
1022 break;
1023 case PORT_D:
1024 bit = SDE_PORTD_HOTPLUG;
1025 break;
1026 default:
1027 return true;
1028 }
1029 } else {
Robin Schroereba905b2014-05-18 02:24:50 +02001030 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +00001031 case PORT_B:
1032 bit = SDE_PORTB_HOTPLUG_CPT;
1033 break;
1034 case PORT_C:
1035 bit = SDE_PORTC_HOTPLUG_CPT;
1036 break;
1037 case PORT_D:
1038 bit = SDE_PORTD_HOTPLUG_CPT;
1039 break;
1040 default:
1041 return true;
1042 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001043 }
1044
1045 return I915_READ(SDEISR) & bit;
1046}
1047
Jesse Barnesb24e7172011-01-04 15:09:30 -08001048static const char *state_string(bool enabled)
1049{
1050 return enabled ? "on" : "off";
1051}
1052
1053/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001054void assert_pll(struct drm_i915_private *dev_priv,
1055 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001056{
1057 int reg;
1058 u32 val;
1059 bool cur_state;
1060
1061 reg = DPLL(pipe);
1062 val = I915_READ(reg);
1063 cur_state = !!(val & DPLL_VCO_ENABLE);
1064 WARN(cur_state != state,
1065 "PLL state assertion failure (expected %s, current %s)\n",
1066 state_string(state), state_string(cur_state));
1067}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001068
Jani Nikula23538ef2013-08-27 15:12:22 +03001069/* XXX: the dsi pll is shared between MIPI DSI ports */
1070static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1071{
1072 u32 val;
1073 bool cur_state;
1074
1075 mutex_lock(&dev_priv->dpio_lock);
1076 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1077 mutex_unlock(&dev_priv->dpio_lock);
1078
1079 cur_state = val & DSI_PLL_VCO_EN;
1080 WARN(cur_state != state,
1081 "DSI PLL state assertion failure (expected %s, current %s)\n",
1082 state_string(state), state_string(cur_state));
1083}
1084#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1085#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1086
Daniel Vetter55607e82013-06-16 21:42:39 +02001087struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001088intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001089{
Daniel Vettere2b78262013-06-07 23:10:03 +02001090 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1091
Daniel Vettera43f6e02013-06-07 23:10:32 +02001092 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001093 return NULL;
1094
Daniel Vettera43f6e02013-06-07 23:10:32 +02001095 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001096}
1097
Jesse Barnesb24e7172011-01-04 15:09:30 -08001098/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001099void assert_shared_dpll(struct drm_i915_private *dev_priv,
1100 struct intel_shared_dpll *pll,
1101 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001102{
Jesse Barnes040484a2011-01-03 12:14:26 -08001103 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001104 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001105
Chris Wilson92b27b02012-05-20 18:10:50 +01001106 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001107 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001108 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001109
Daniel Vetter53589012013-06-05 13:34:16 +02001110 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001111 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001112 "%s assertion failure (expected %s, current %s)\n",
1113 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001114}
Jesse Barnes040484a2011-01-03 12:14:26 -08001115
1116static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state)
1118{
1119 int reg;
1120 u32 val;
1121 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1123 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001124
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001125 if (HAS_DDI(dev_priv->dev)) {
1126 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001127 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001128 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001129 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001130 } else {
1131 reg = FDI_TX_CTL(pipe);
1132 val = I915_READ(reg);
1133 cur_state = !!(val & FDI_TX_ENABLE);
1134 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001135 WARN(cur_state != state,
1136 "FDI TX state assertion failure (expected %s, current %s)\n",
1137 state_string(state), state_string(cur_state));
1138}
1139#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1140#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141
1142static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144{
1145 int reg;
1146 u32 val;
1147 bool cur_state;
1148
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001149 reg = FDI_RX_CTL(pipe);
1150 val = I915_READ(reg);
1151 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001152 WARN(cur_state != state,
1153 "FDI RX state assertion failure (expected %s, current %s)\n",
1154 state_string(state), state_string(cur_state));
1155}
1156#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161{
1162 int reg;
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001166 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001167 return;
1168
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001170 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001171 return;
1172
Jesse Barnes040484a2011-01-03 12:14:26 -08001173 reg = FDI_TX_CTL(pipe);
1174 val = I915_READ(reg);
1175 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176}
1177
Daniel Vetter55607e82013-06-16 21:42:39 +02001178void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1179 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001180{
1181 int reg;
1182 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001183 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001184
1185 reg = FDI_RX_CTL(pipe);
1186 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001187 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1188 WARN(cur_state != state,
1189 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001191}
1192
Jesse Barnesea0760c2011-01-04 15:09:32 -08001193static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
1195{
1196 int pp_reg, lvds_reg;
1197 u32 val;
1198 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001199 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001200
1201 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1202 pp_reg = PCH_PP_CONTROL;
1203 lvds_reg = PCH_LVDS;
1204 } else {
1205 pp_reg = PP_CONTROL;
1206 lvds_reg = LVDS;
1207 }
1208
1209 val = I915_READ(pp_reg);
1210 if (!(val & PANEL_POWER_ON) ||
1211 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1212 locked = false;
1213
1214 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216
1217 WARN(panel_pipe == pipe && locked,
1218 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001219 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001220}
1221
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001222static void assert_cursor(struct drm_i915_private *dev_priv,
1223 enum pipe pipe, bool state)
1224{
1225 struct drm_device *dev = dev_priv->dev;
1226 bool cur_state;
1227
Paulo Zanonid9d82082014-02-27 16:30:56 -03001228 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001229 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001230 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001231 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001232
1233 WARN(cur_state != state,
1234 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1235 pipe_name(pipe), state_string(state), state_string(cur_state));
1236}
1237#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1238#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1239
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001240void assert_pipe(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001242{
1243 int reg;
1244 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001245 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1247 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001248
Daniel Vetter8e636782012-01-22 01:36:48 +01001249 /* if we need the pipe A quirk it must be always on */
1250 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1251 state = true;
1252
Imre Deakda7e29b2014-02-18 00:02:02 +02001253 if (!intel_display_power_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001254 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001255 cur_state = false;
1256 } else {
1257 reg = PIPECONF(cpu_transcoder);
1258 val = I915_READ(reg);
1259 cur_state = !!(val & PIPECONF_ENABLE);
1260 }
1261
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001262 WARN(cur_state != state,
1263 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001264 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001265}
1266
Chris Wilson931872f2012-01-16 23:01:13 +00001267static void assert_plane(struct drm_i915_private *dev_priv,
1268 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001269{
1270 int reg;
1271 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001272 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001273
1274 reg = DSPCNTR(plane);
1275 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001276 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1277 WARN(cur_state != state,
1278 "plane %c assertion failure (expected %s, current %s)\n",
1279 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001280}
1281
Chris Wilson931872f2012-01-16 23:01:13 +00001282#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1283#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1284
Jesse Barnesb24e7172011-01-04 15:09:30 -08001285static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe)
1287{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001288 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001289 int reg, i;
1290 u32 val;
1291 int cur_pipe;
1292
Ville Syrjälä653e1022013-06-04 13:49:05 +03001293 /* Primary planes are fixed to pipes on gen4+ */
1294 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001295 reg = DSPCNTR(pipe);
1296 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001297 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001298 "plane %c assertion failure, should be disabled but not\n",
1299 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001300 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001301 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001302
Jesse Barnesb24e7172011-01-04 15:09:30 -08001303 /* Need to check both planes against the pipe */
Damien Lespiau055e3932014-08-18 13:49:10 +01001304 for_each_pipe(dev_priv, i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001305 reg = DSPCNTR(i);
1306 val = I915_READ(reg);
1307 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1308 DISPPLANE_SEL_PIPE_SHIFT;
1309 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001310 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1311 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001312 }
1313}
1314
Jesse Barnes19332d72013-03-28 09:55:38 -07001315static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001318 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001319 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001320 u32 val;
1321
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001322 if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001323 for_each_sprite(pipe, sprite) {
1324 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001325 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001326 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001328 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001329 }
1330 } else if (INTEL_INFO(dev)->gen >= 7) {
1331 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001332 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001333 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001334 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001335 plane_name(pipe), pipe_name(pipe));
1336 } else if (INTEL_INFO(dev)->gen >= 5) {
1337 reg = DVSCNTR(pipe);
1338 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001339 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001340 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1341 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001342 }
1343}
1344
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001345static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001346{
1347 u32 val;
1348 bool enabled;
1349
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001350 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001351
Jesse Barnes92f25842011-01-04 15:09:34 -08001352 val = I915_READ(PCH_DREF_CONTROL);
1353 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1354 DREF_SUPERSPREAD_SOURCE_MASK));
1355 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1356}
1357
Daniel Vetterab9412b2013-05-03 11:49:46 +02001358static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1359 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001360{
1361 int reg;
1362 u32 val;
1363 bool enabled;
1364
Daniel Vetterab9412b2013-05-03 11:49:46 +02001365 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001366 val = I915_READ(reg);
1367 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001368 WARN(enabled,
1369 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1370 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001371}
1372
Keith Packard4e634382011-08-06 10:39:45 -07001373static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001375{
1376 if ((val & DP_PORT_EN) == 0)
1377 return false;
1378
1379 if (HAS_PCH_CPT(dev_priv->dev)) {
1380 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1381 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1382 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1383 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001384 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1385 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001387 } else {
1388 if ((val & DP_PIPE_MASK) != (pipe << 30))
1389 return false;
1390 }
1391 return true;
1392}
1393
Keith Packard1519b992011-08-06 10:35:34 -07001394static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe, u32 val)
1396{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001397 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001398 return false;
1399
1400 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001401 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001402 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001403 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1404 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001406 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001407 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001408 return false;
1409 }
1410 return true;
1411}
1412
1413static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, u32 val)
1415{
1416 if ((val & LVDS_PORT_EN) == 0)
1417 return false;
1418
1419 if (HAS_PCH_CPT(dev_priv->dev)) {
1420 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421 return false;
1422 } else {
1423 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1424 return false;
1425 }
1426 return true;
1427}
1428
1429static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1430 enum pipe pipe, u32 val)
1431{
1432 if ((val & ADPA_DAC_ENABLE) == 0)
1433 return false;
1434 if (HAS_PCH_CPT(dev_priv->dev)) {
1435 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 return false;
1437 } else {
1438 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1439 return false;
1440 }
1441 return true;
1442}
1443
Jesse Barnes291906f2011-02-02 12:28:03 -08001444static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001445 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001446{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001447 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001448 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001449 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001450 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001451
Daniel Vetter75c5da22012-09-10 21:58:29 +02001452 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1453 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001454 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001455}
1456
1457static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1458 enum pipe pipe, int reg)
1459{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001460 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001461 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001462 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001463 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001464
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001465 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001466 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001467 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001468}
1469
1470static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1471 enum pipe pipe)
1472{
1473 int reg;
1474 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001475
Keith Packardf0575e92011-07-25 22:12:43 -07001476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1477 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1478 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001479
1480 reg = PCH_ADPA;
1481 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001482 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001483 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001484 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001485
1486 reg = PCH_LVDS;
1487 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001488 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001489 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001490 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001491
Paulo Zanonie2debe92013-02-18 19:00:27 -03001492 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1493 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1494 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001495}
1496
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001497static void intel_init_dpio(struct drm_device *dev)
1498{
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500
1501 if (!IS_VALLEYVIEW(dev))
1502 return;
1503
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001504 /*
1505 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1506 * CHV x1 PHY (DP/HDMI D)
1507 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1508 */
1509 if (IS_CHERRYVIEW(dev)) {
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1511 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1512 } else {
1513 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1514 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001515}
1516
Daniel Vetter426115c2013-07-11 22:13:42 +02001517static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001518{
Daniel Vetter426115c2013-07-11 22:13:42 +02001519 struct drm_device *dev = crtc->base.dev;
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 int reg = DPLL(crtc->pipe);
1522 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001523
Daniel Vetter426115c2013-07-11 22:13:42 +02001524 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001525
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001526 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001527 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1528
1529 /* PLL is protected by panel, make sure we can write it */
Jani Nikula6a9e7362014-08-22 15:06:35 +03001530 if (IS_MOBILE(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001531 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001532
Daniel Vetter426115c2013-07-11 22:13:42 +02001533 I915_WRITE(reg, dpll);
1534 POSTING_READ(reg);
1535 udelay(150);
1536
1537 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1538 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1539
1540 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1541 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001542
1543 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001544 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001547 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001548 POSTING_READ(reg);
1549 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001550 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001551 POSTING_READ(reg);
1552 udelay(150); /* wait for warmup */
1553}
1554
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001555static void chv_enable_pll(struct intel_crtc *crtc)
1556{
1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int pipe = crtc->pipe;
1560 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001561 u32 tmp;
1562
1563 assert_pipe_disabled(dev_priv, crtc->pipe);
1564
1565 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1566
1567 mutex_lock(&dev_priv->dpio_lock);
1568
1569 /* Enable back the 10bit clock to display controller */
1570 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1571 tmp |= DPIO_DCLKP_EN;
1572 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1573
1574 /*
1575 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1576 */
1577 udelay(1);
1578
1579 /* Enable PLL */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001580 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001581
1582 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001583 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001584 DRM_ERROR("PLL %d failed to lock\n", pipe);
1585
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001586 /* not sure when this should be written */
1587 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1588 POSTING_READ(DPLL_MD(pipe));
1589
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001590 mutex_unlock(&dev_priv->dpio_lock);
1591}
1592
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001593static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001594{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001595 struct drm_device *dev = crtc->base.dev;
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597 int reg = DPLL(crtc->pipe);
1598 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001599
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001600 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001601
1602 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001603 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001604
1605 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001606 if (IS_MOBILE(dev) && !IS_I830(dev))
1607 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001608
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001609 I915_WRITE(reg, dpll);
1610
1611 /* Wait for the clocks to stabilize. */
1612 POSTING_READ(reg);
1613 udelay(150);
1614
1615 if (INTEL_INFO(dev)->gen >= 4) {
1616 I915_WRITE(DPLL_MD(crtc->pipe),
1617 crtc->config.dpll_hw_state.dpll_md);
1618 } else {
1619 /* The pixel multiplier can only be updated once the
1620 * DPLL is enabled and the clocks are stable.
1621 *
1622 * So write it again.
1623 */
1624 I915_WRITE(reg, dpll);
1625 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001626
1627 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001628 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001631 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001634 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001635 POSTING_READ(reg);
1636 udelay(150); /* wait for warmup */
1637}
1638
1639/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001640 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001641 * @dev_priv: i915 private structure
1642 * @pipe: pipe PLL to disable
1643 *
1644 * Disable the PLL for @pipe, making sure the pipe is off first.
1645 *
1646 * Note! This is for pre-ILK only.
1647 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001648static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001649{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001650 /* Don't disable pipe A or pipe A PLLs if needed */
1651 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1652 return;
1653
1654 /* Make sure the pipe isn't still relying on us */
1655 assert_pipe_disabled(dev_priv, pipe);
1656
Daniel Vetter50b44a42013-06-05 13:34:33 +02001657 I915_WRITE(DPLL(pipe), 0);
1658 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001659}
1660
Jesse Barnesf6071162013-10-01 10:41:38 -07001661static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662{
1663 u32 val = 0;
1664
1665 /* Make sure the pipe isn't still relying on us */
1666 assert_pipe_disabled(dev_priv, pipe);
1667
Imre Deake5cbfbf2014-01-09 17:08:16 +02001668 /*
1669 * Leave integrated clock source and reference clock enabled for pipe B.
1670 * The latter is needed for VGA hotplug / manual detection.
1671 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001672 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001673 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001674 I915_WRITE(DPLL(pipe), val);
1675 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001676
1677}
1678
1679static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1680{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001681 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001682 u32 val;
1683
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001686
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001687 /* Set PLL en = 0 */
Ville Syrjäläd17ec4c2014-06-28 02:03:59 +03001688 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001689 if (pipe != PIPE_A)
1690 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1691 I915_WRITE(DPLL(pipe), val);
1692 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001693
1694 mutex_lock(&dev_priv->dpio_lock);
1695
1696 /* Disable 10bit clock to display controller */
1697 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1698 val &= ~DPIO_DCLKP_EN;
1699 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1700
Ville Syrjälä61407f62014-05-27 16:32:55 +03001701 /* disable left/right clock distribution */
1702 if (pipe != PIPE_B) {
1703 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1704 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1705 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1706 } else {
1707 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1708 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1709 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1710 }
1711
Ville Syrjäläd7520482014-04-09 13:28:59 +03001712 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001713}
1714
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001715void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1716 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001717{
1718 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001719 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001720
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001721 switch (dport->port) {
1722 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001723 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001724 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001725 break;
1726 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001727 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001728 dpll_reg = DPLL(0);
1729 break;
1730 case PORT_D:
1731 port_mask = DPLL_PORTD_READY_MASK;
1732 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001733 break;
1734 default:
1735 BUG();
1736 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001737
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001738 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001739 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001740 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001741}
1742
Daniel Vetterb14b1052014-04-24 23:55:13 +02001743static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1744{
1745 struct drm_device *dev = crtc->base.dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1748
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001749 if (WARN_ON(pll == NULL))
1750 return;
1751
Daniel Vetterb14b1052014-04-24 23:55:13 +02001752 WARN_ON(!pll->refcount);
1753 if (pll->active == 0) {
1754 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1755 WARN_ON(pll->on);
1756 assert_shared_dpll_disabled(dev_priv, pll);
1757
1758 pll->mode_set(dev_priv, pll);
1759 }
1760}
1761
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001762/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001763 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001764 * @dev_priv: i915 private structure
1765 * @pipe: pipe PLL to enable
1766 *
1767 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768 * drives the transcoder clock.
1769 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001770static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001771{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001774 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001775
Daniel Vetter87a875b2013-06-05 13:34:19 +02001776 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001777 return;
1778
1779 if (WARN_ON(pll->refcount == 0))
1780 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001781
Damien Lespiau74dd6922014-07-29 18:06:17 +01001782 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
Daniel Vetter46edb022013-06-05 13:34:12 +02001783 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001784 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001785
Daniel Vettercdbd2312013-06-05 13:34:03 +02001786 if (pll->active++) {
1787 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001788 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001789 return;
1790 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001791 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001792
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001793 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1794
Daniel Vetter46edb022013-06-05 13:34:12 +02001795 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001796 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001797 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001798}
1799
Damien Lespiauf6daaec2014-08-09 23:00:56 +01001800static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001801{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001805
Jesse Barnes92f25842011-01-04 15:09:34 -08001806 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001807 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001808 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001809 return;
1810
Chris Wilson48da64a2012-05-13 20:16:12 +01001811 if (WARN_ON(pll->refcount == 0))
1812 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001813
Daniel Vetter46edb022013-06-05 13:34:12 +02001814 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001816 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001817
Chris Wilson48da64a2012-05-13 20:16:12 +01001818 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001819 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001820 return;
1821 }
1822
Daniel Vettere9d69442013-06-05 13:34:15 +02001823 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001824 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001825 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001826 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001827
Daniel Vetter46edb022013-06-05 13:34:12 +02001828 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001829 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001830 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001831
1832 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001833}
1834
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001835static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1836 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001837{
Daniel Vetter23670b322012-11-01 09:15:30 +01001838 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001839 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001841 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001842
1843 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001844 BUG_ON(INTEL_INFO(dev)->gen < 5);
Jesse Barnes040484a2011-01-03 12:14:26 -08001845
1846 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001847 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001848 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001849
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, pipe);
1852 assert_fdi_rx_enabled(dev_priv, pipe);
1853
Daniel Vetter23670b322012-11-01 09:15:30 +01001854 if (HAS_PCH_CPT(dev)) {
1855 /* Workaround: Set the timing override bit before enabling the
1856 * pch transcoder. */
1857 reg = TRANS_CHICKEN2(pipe);
1858 val = I915_READ(reg);
1859 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1860 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001861 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001862
Daniel Vetterab9412b2013-05-03 11:49:46 +02001863 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001864 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001865 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001866
1867 if (HAS_PCH_IBX(dev_priv->dev)) {
1868 /*
1869 * make the BPC in transcoder be consistent with
1870 * that in pipeconf reg.
1871 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001872 val &= ~PIPECONF_BPC_MASK;
1873 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001874 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001875
1876 val &= ~TRANS_INTERLACE_MASK;
1877 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001878 if (HAS_PCH_IBX(dev_priv->dev) &&
1879 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1880 val |= TRANS_LEGACY_INTERLACED_ILK;
1881 else
1882 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001883 else
1884 val |= TRANS_PROGRESSIVE;
1885
Jesse Barnes040484a2011-01-03 12:14:26 -08001886 I915_WRITE(reg, val | TRANS_ENABLE);
1887 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001888 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001889}
1890
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001891static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001892 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001893{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001894 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001895
1896 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001897 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001898
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001899 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001900 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001901 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001902
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001903 /* Workaround: set timing override bit. */
1904 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001905 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001906 I915_WRITE(_TRANSA_CHICKEN2, val);
1907
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001908 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001909 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001910
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001911 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1912 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001913 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001914 else
1915 val |= TRANS_PROGRESSIVE;
1916
Daniel Vetterab9412b2013-05-03 11:49:46 +02001917 I915_WRITE(LPT_TRANSCONF, val);
1918 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001919 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001920}
1921
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001922static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1923 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001924{
Daniel Vetter23670b322012-11-01 09:15:30 +01001925 struct drm_device *dev = dev_priv->dev;
1926 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001927
1928 /* FDI relies on the transcoder */
1929 assert_fdi_tx_disabled(dev_priv, pipe);
1930 assert_fdi_rx_disabled(dev_priv, pipe);
1931
Jesse Barnes291906f2011-02-02 12:28:03 -08001932 /* Ports must be off as well */
1933 assert_pch_ports_disabled(dev_priv, pipe);
1934
Daniel Vetterab9412b2013-05-03 11:49:46 +02001935 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001936 val = I915_READ(reg);
1937 val &= ~TRANS_ENABLE;
1938 I915_WRITE(reg, val);
1939 /* wait for PCH transcoder off, transcoder state */
1940 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001941 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001942
1943 if (!HAS_PCH_IBX(dev)) {
1944 /* Workaround: Clear the timing override chicken bit again. */
1945 reg = TRANS_CHICKEN2(pipe);
1946 val = I915_READ(reg);
1947 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1948 I915_WRITE(reg, val);
1949 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001950}
1951
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001952static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001953{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001954 u32 val;
1955
Daniel Vetterab9412b2013-05-03 11:49:46 +02001956 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001957 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001958 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001959 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001960 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001961 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001962
1963 /* Workaround: clear timing override bit. */
1964 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001965 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001966 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001967}
1968
1969/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001970 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02001971 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001972 *
Paulo Zanoni03722642014-01-17 13:51:09 -02001973 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001974 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08001975 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02001976static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001977{
Paulo Zanoni03722642014-01-17 13:51:09 -02001978 struct drm_device *dev = crtc->base.dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001981 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1982 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001983 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001984 int reg;
1985 u32 val;
1986
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001987 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001988 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001989 assert_sprites_disabled(dev_priv, pipe);
1990
Paulo Zanoni681e5812012-12-06 11:12:38 -02001991 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001992 pch_transcoder = TRANSCODER_A;
1993 else
1994 pch_transcoder = pipe;
1995
Jesse Barnesb24e7172011-01-04 15:09:30 -08001996 /*
1997 * A pipe without a PLL won't actually be able to drive bits from
1998 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1999 * need the check.
2000 */
2001 if (!HAS_PCH_SPLIT(dev_priv->dev))
Paulo Zanonifbf32182014-01-17 13:51:11 -02002002 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002003 assert_dsi_pll_enabled(dev_priv);
2004 else
2005 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002006 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002007 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002008 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002009 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002010 assert_fdi_tx_pll_enabled(dev_priv,
2011 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002012 }
2013 /* FIXME: assert CPU port conditions for SNB+ */
2014 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002015
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002016 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002017 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002018 if (val & PIPECONF_ENABLE) {
2019 WARN_ON(!(pipe == PIPE_A &&
2020 dev_priv->quirks & QUIRK_PIPEA_FORCE));
Chris Wilson00d70b12011-03-17 07:18:29 +00002021 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002022 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002023
2024 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002025 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002026}
2027
2028/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002029 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002030 * @dev_priv: i915 private structure
2031 * @pipe: pipe to disable
2032 *
2033 * Disable @pipe, making sure that various hardware specific requirements
2034 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2035 *
2036 * @pipe should be %PIPE_A or %PIPE_B.
2037 *
2038 * Will wait until the pipe has shut down before returning.
2039 */
2040static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2041 enum pipe pipe)
2042{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002043 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2044 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002045 int reg;
2046 u32 val;
2047
2048 /*
2049 * Make sure planes won't keep trying to pump pixels to us,
2050 * or we might hang the display.
2051 */
2052 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002053 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002054 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002055
2056 /* Don't disable pipe A or pipe A PLLs if needed */
2057 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2058 return;
2059
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002060 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002061 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002062 if ((val & PIPECONF_ENABLE) == 0)
2063 return;
2064
2065 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002066 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2067}
2068
Keith Packardd74362c2011-07-28 14:47:14 -07002069/*
2070 * Plane regs are double buffered, going from enabled->disabled needs a
2071 * trigger in order to latch. The display address reg provides this.
2072 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002073void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2074 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002075{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002076 struct drm_device *dev = dev_priv->dev;
2077 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002078
2079 I915_WRITE(reg, I915_READ(reg));
2080 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002081}
2082
Jesse Barnesb24e7172011-01-04 15:09:30 -08002083/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002084 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002085 * @plane: plane to be enabled
2086 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002087 *
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002088 * Enable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002089 */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002090static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2091 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002092{
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002093 struct drm_device *dev = plane->dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002096
2097 /* If the pipe isn't enabled, we can't pump pixels and may hang */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002098 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002099
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002100 if (intel_crtc->primary_enabled)
2101 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002102
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002103 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002104
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002105 dev_priv->display.update_primary_plane(crtc, plane->fb,
2106 crtc->x, crtc->y);
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002107
2108 /*
2109 * BDW signals flip done immediately if the plane
2110 * is disabled, even if the plane enable is already
2111 * armed to occur at the next vblank :(
2112 */
2113 if (IS_BROADWELL(dev))
2114 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002115}
2116
Jesse Barnesb24e7172011-01-04 15:09:30 -08002117/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002118 * intel_disable_primary_hw_plane - disable the primary hardware plane
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002119 * @plane: plane to be disabled
2120 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002121 *
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002122 * Disable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002123 */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002124static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2125 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002126{
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002127 struct drm_device *dev = plane->dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130
2131 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002132
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002133 if (!intel_crtc->primary_enabled)
2134 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002135
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002136 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002137
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002138 dev_priv->display.update_primary_plane(crtc, plane->fb,
2139 crtc->x, crtc->y);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002140}
2141
Chris Wilson693db182013-03-05 14:52:39 +00002142static bool need_vtd_wa(struct drm_device *dev)
2143{
2144#ifdef CONFIG_INTEL_IOMMU
2145 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2146 return true;
2147#endif
2148 return false;
2149}
2150
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002151static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2152{
2153 int tile_height;
2154
2155 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2156 return ALIGN(height, tile_height);
2157}
2158
Chris Wilson127bd2a2010-07-23 23:32:05 +01002159int
Chris Wilson48b956c2010-09-14 12:50:34 +01002160intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002161 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002162 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002163{
Chris Wilsonce453d82011-02-21 14:43:56 +00002164 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002165 u32 alignment;
2166 int ret;
2167
Matt Roperebcdd392014-07-09 16:22:11 -07002168 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2169
Chris Wilson05394f32010-11-08 19:18:58 +00002170 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002171 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002172 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2173 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002174 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002175 alignment = 4 * 1024;
2176 else
2177 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002178 break;
2179 case I915_TILING_X:
2180 /* pin() will align the object as required by fence */
2181 alignment = 0;
2182 break;
2183 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002184 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002185 return -EINVAL;
2186 default:
2187 BUG();
2188 }
2189
Chris Wilson693db182013-03-05 14:52:39 +00002190 /* Note that the w/a also requires 64 PTE of padding following the
2191 * bo. We currently fill all unused PTE with the shadow page and so
2192 * we should always have valid PTE following the scanout preventing
2193 * the VT-d warning.
2194 */
2195 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2196 alignment = 256 * 1024;
2197
Chris Wilsonce453d82011-02-21 14:43:56 +00002198 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002199 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002200 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002201 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002202
2203 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2204 * fence, whereas 965+ only requires a fence if using
2205 * framebuffer compression. For simplicity, we always install
2206 * a fence as the cost is not that onerous.
2207 */
Chris Wilson06d98132012-04-17 15:31:24 +01002208 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002209 if (ret)
2210 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002211
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002212 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002213
Chris Wilsonce453d82011-02-21 14:43:56 +00002214 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002215 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002216
2217err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002218 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002219err_interruptible:
2220 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002221 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002222}
2223
Chris Wilson1690e1e2011-12-14 13:57:08 +01002224void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2225{
Matt Roperebcdd392014-07-09 16:22:11 -07002226 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2227
Chris Wilson1690e1e2011-12-14 13:57:08 +01002228 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002229 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002230}
2231
Daniel Vetterc2c75132012-07-05 12:17:30 +02002232/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2233 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002234unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2235 unsigned int tiling_mode,
2236 unsigned int cpp,
2237 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002238{
Chris Wilsonbc752862013-02-21 20:04:31 +00002239 if (tiling_mode != I915_TILING_NONE) {
2240 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002241
Chris Wilsonbc752862013-02-21 20:04:31 +00002242 tile_rows = *y / 8;
2243 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002244
Chris Wilsonbc752862013-02-21 20:04:31 +00002245 tiles = *x / (512/cpp);
2246 *x %= 512/cpp;
2247
2248 return tile_rows * pitch * 8 + tiles * 4096;
2249 } else {
2250 unsigned int offset;
2251
2252 offset = *y * pitch + *x * cpp;
2253 *y = 0;
2254 *x = (offset & 4095) / cpp;
2255 return offset & -4096;
2256 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002257}
2258
Jesse Barnes46f297f2014-03-07 08:57:48 -08002259int intel_format_to_fourcc(int format)
2260{
2261 switch (format) {
2262 case DISPPLANE_8BPP:
2263 return DRM_FORMAT_C8;
2264 case DISPPLANE_BGRX555:
2265 return DRM_FORMAT_XRGB1555;
2266 case DISPPLANE_BGRX565:
2267 return DRM_FORMAT_RGB565;
2268 default:
2269 case DISPPLANE_BGRX888:
2270 return DRM_FORMAT_XRGB8888;
2271 case DISPPLANE_RGBX888:
2272 return DRM_FORMAT_XBGR8888;
2273 case DISPPLANE_BGRX101010:
2274 return DRM_FORMAT_XRGB2101010;
2275 case DISPPLANE_RGBX101010:
2276 return DRM_FORMAT_XBGR2101010;
2277 }
2278}
2279
Jesse Barnes484b41d2014-03-07 08:57:55 -08002280static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002281 struct intel_plane_config *plane_config)
2282{
2283 struct drm_device *dev = crtc->base.dev;
2284 struct drm_i915_gem_object *obj = NULL;
2285 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2286 u32 base = plane_config->base;
2287
Chris Wilsonff2652e2014-03-10 08:07:02 +00002288 if (plane_config->size == 0)
2289 return false;
2290
Jesse Barnes46f297f2014-03-07 08:57:48 -08002291 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2292 plane_config->size);
2293 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002294 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002295
2296 if (plane_config->tiled) {
2297 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002298 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002299 }
2300
Dave Airlie66e514c2014-04-03 07:51:54 +10002301 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2302 mode_cmd.width = crtc->base.primary->fb->width;
2303 mode_cmd.height = crtc->base.primary->fb->height;
2304 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002305
2306 mutex_lock(&dev->struct_mutex);
2307
Dave Airlie66e514c2014-04-03 07:51:54 +10002308 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002309 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002310 DRM_DEBUG_KMS("intel fb init failed\n");
2311 goto out_unref_obj;
2312 }
2313
Daniel Vettera071fa02014-06-18 23:28:09 +02002314 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002315 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002316
2317 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2318 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002319
2320out_unref_obj:
2321 drm_gem_object_unreference(&obj->base);
2322 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002323 return false;
2324}
2325
2326static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2327 struct intel_plane_config *plane_config)
2328{
2329 struct drm_device *dev = intel_crtc->base.dev;
2330 struct drm_crtc *c;
2331 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002332 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002333
Dave Airlie66e514c2014-04-03 07:51:54 +10002334 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002335 return;
2336
2337 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2338 return;
2339
Dave Airlie66e514c2014-04-03 07:51:54 +10002340 kfree(intel_crtc->base.primary->fb);
2341 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002342
2343 /*
2344 * Failed to alloc the obj, check to see if we should share
2345 * an fb with another CRTC instead
2346 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002347 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002348 i = to_intel_crtc(c);
2349
2350 if (c == &intel_crtc->base)
2351 continue;
2352
Matt Roper2ff8fde2014-07-08 07:50:07 -07002353 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002354 continue;
2355
Matt Roper2ff8fde2014-07-08 07:50:07 -07002356 obj = intel_fb_obj(c->primary->fb);
2357 if (obj == NULL)
2358 continue;
2359
2360 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Dave Airlie66e514c2014-04-03 07:51:54 +10002361 drm_framebuffer_reference(c->primary->fb);
2362 intel_crtc->base.primary->fb = c->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002363 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002364 break;
2365 }
2366 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002367}
2368
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002369static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2370 struct drm_framebuffer *fb,
2371 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002372{
2373 struct drm_device *dev = crtc->dev;
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002376 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Jesse Barnes81255562010-08-02 12:07:50 -07002377 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002378 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002379 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002380 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302381 int pixel_size;
2382
2383 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
Jesse Barnes81255562010-08-02 12:07:50 -07002384
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002385 if (!intel_crtc->primary_enabled) {
2386 I915_WRITE(reg, 0);
2387 if (INTEL_INFO(dev)->gen >= 4)
2388 I915_WRITE(DSPSURF(plane), 0);
2389 else
2390 I915_WRITE(DSPADDR(plane), 0);
2391 POSTING_READ(reg);
2392 return;
2393 }
2394
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002395 dspcntr = DISPPLANE_GAMMA_ENABLE;
2396
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002397 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002398
2399 if (INTEL_INFO(dev)->gen < 4) {
2400 if (intel_crtc->pipe == PIPE_B)
2401 dspcntr |= DISPPLANE_SEL_PIPE_B;
2402
2403 /* pipesrc and dspsize control the size that is scaled from,
2404 * which should always be the user's requested size.
2405 */
2406 I915_WRITE(DSPSIZE(plane),
2407 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2408 (intel_crtc->config.pipe_src_w - 1));
2409 I915_WRITE(DSPPOS(plane), 0);
2410 }
2411
Ville Syrjälä57779d02012-10-31 17:50:14 +02002412 switch (fb->pixel_format) {
2413 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002414 dspcntr |= DISPPLANE_8BPP;
2415 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002416 case DRM_FORMAT_XRGB1555:
2417 case DRM_FORMAT_ARGB1555:
2418 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002419 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002420 case DRM_FORMAT_RGB565:
2421 dspcntr |= DISPPLANE_BGRX565;
2422 break;
2423 case DRM_FORMAT_XRGB8888:
2424 case DRM_FORMAT_ARGB8888:
2425 dspcntr |= DISPPLANE_BGRX888;
2426 break;
2427 case DRM_FORMAT_XBGR8888:
2428 case DRM_FORMAT_ABGR8888:
2429 dspcntr |= DISPPLANE_RGBX888;
2430 break;
2431 case DRM_FORMAT_XRGB2101010:
2432 case DRM_FORMAT_ARGB2101010:
2433 dspcntr |= DISPPLANE_BGRX101010;
2434 break;
2435 case DRM_FORMAT_XBGR2101010:
2436 case DRM_FORMAT_ABGR2101010:
2437 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002438 break;
2439 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002440 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002441 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002442
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002443 if (INTEL_INFO(dev)->gen >= 4 &&
2444 obj->tiling_mode != I915_TILING_NONE)
2445 dspcntr |= DISPPLANE_TILED;
Jesse Barnes81255562010-08-02 12:07:50 -07002446
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002447 if (IS_G4X(dev))
2448 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2449
Daniel Vettere506a0c2012-07-05 12:17:29 +02002450 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002451
Daniel Vetterc2c75132012-07-05 12:17:30 +02002452 if (INTEL_INFO(dev)->gen >= 4) {
2453 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002454 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2455 fb->bits_per_pixel / 8,
2456 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002457 linear_offset -= intel_crtc->dspaddr_offset;
2458 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002459 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002460 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002461
Sonika Jindal48404c12014-08-22 14:06:04 +05302462 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2463 dspcntr |= DISPPLANE_ROTATE_180;
2464
2465 x += (intel_crtc->config.pipe_src_w - 1);
2466 y += (intel_crtc->config.pipe_src_h - 1);
2467
2468 /* Finding the last pixel of the last line of the display
2469 data and adding to linear_offset*/
2470 linear_offset +=
2471 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2472 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2473 }
2474
2475 I915_WRITE(reg, dspcntr);
2476
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002477 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2478 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2479 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002480 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002481 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002482 I915_WRITE(DSPSURF(plane),
2483 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002484 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002485 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002486 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002487 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002488 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002489}
2490
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002491static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2492 struct drm_framebuffer *fb,
2493 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002494{
2495 struct drm_device *dev = crtc->dev;
2496 struct drm_i915_private *dev_priv = dev->dev_private;
2497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002498 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002499 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002500 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002501 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002502 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302503 int pixel_size;
2504
2505 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002506
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002507 if (!intel_crtc->primary_enabled) {
2508 I915_WRITE(reg, 0);
2509 I915_WRITE(DSPSURF(plane), 0);
2510 POSTING_READ(reg);
2511 return;
2512 }
2513
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002514 dspcntr = DISPPLANE_GAMMA_ENABLE;
2515
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002516 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002517
2518 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2519 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2520
Ville Syrjälä57779d02012-10-31 17:50:14 +02002521 switch (fb->pixel_format) {
2522 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002523 dspcntr |= DISPPLANE_8BPP;
2524 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002525 case DRM_FORMAT_RGB565:
2526 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002527 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002528 case DRM_FORMAT_XRGB8888:
2529 case DRM_FORMAT_ARGB8888:
2530 dspcntr |= DISPPLANE_BGRX888;
2531 break;
2532 case DRM_FORMAT_XBGR8888:
2533 case DRM_FORMAT_ABGR8888:
2534 dspcntr |= DISPPLANE_RGBX888;
2535 break;
2536 case DRM_FORMAT_XRGB2101010:
2537 case DRM_FORMAT_ARGB2101010:
2538 dspcntr |= DISPPLANE_BGRX101010;
2539 break;
2540 case DRM_FORMAT_XBGR2101010:
2541 case DRM_FORMAT_ABGR2101010:
2542 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002543 break;
2544 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002545 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002546 }
2547
2548 if (obj->tiling_mode != I915_TILING_NONE)
2549 dspcntr |= DISPPLANE_TILED;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002550
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002551 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002552 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002553
Daniel Vettere506a0c2012-07-05 12:17:29 +02002554 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002555 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002556 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2557 fb->bits_per_pixel / 8,
2558 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002559 linear_offset -= intel_crtc->dspaddr_offset;
Sonika Jindal48404c12014-08-22 14:06:04 +05302560 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2561 dspcntr |= DISPPLANE_ROTATE_180;
2562
2563 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2564 x += (intel_crtc->config.pipe_src_w - 1);
2565 y += (intel_crtc->config.pipe_src_h - 1);
2566
2567 /* Finding the last pixel of the last line of the display
2568 data and adding to linear_offset*/
2569 linear_offset +=
2570 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2571 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2572 }
2573 }
2574
2575 I915_WRITE(reg, dspcntr);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002576
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002577 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2578 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2579 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002580 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002581 I915_WRITE(DSPSURF(plane),
2582 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002583 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002584 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2585 } else {
2586 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2587 I915_WRITE(DSPLINOFF(plane), linear_offset);
2588 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002589 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002590}
2591
2592/* Assume fb object is pinned & idle & fenced and just update base pointers */
2593static int
2594intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2595 int x, int y, enum mode_set_atomic state)
2596{
2597 struct drm_device *dev = crtc->dev;
2598 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002599
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002600 if (dev_priv->display.disable_fbc)
2601 dev_priv->display.disable_fbc(dev);
Daniel Vettercc365132014-06-18 13:59:13 +02002602 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
Jesse Barnes81255562010-08-02 12:07:50 -07002603
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002604 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2605
2606 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002607}
2608
Ville Syrjälä96a02912013-02-18 19:08:49 +02002609void intel_display_handle_reset(struct drm_device *dev)
2610{
2611 struct drm_i915_private *dev_priv = dev->dev_private;
2612 struct drm_crtc *crtc;
2613
2614 /*
2615 * Flips in the rings have been nuked by the reset,
2616 * so complete all pending flips so that user space
2617 * will get its events and not get stuck.
2618 *
2619 * Also update the base address of all primary
2620 * planes to the the last fb to make sure we're
2621 * showing the correct fb after a reset.
2622 *
2623 * Need to make two loops over the crtcs so that we
2624 * don't try to grab a crtc mutex before the
2625 * pending_flip_queue really got woken up.
2626 */
2627
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002628 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2630 enum plane plane = intel_crtc->plane;
2631
2632 intel_prepare_page_flip(dev, plane);
2633 intel_finish_page_flip_plane(dev, plane);
2634 }
2635
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002636 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638
Rob Clark51fd3712013-11-19 12:10:12 -05002639 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002640 /*
2641 * FIXME: Once we have proper support for primary planes (and
2642 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002643 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002644 */
Matt Roperf4510a22014-04-01 15:22:40 -07002645 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002646 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002647 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002648 crtc->x,
2649 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05002650 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002651 }
2652}
2653
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002654static int
Chris Wilson14667a42012-04-03 17:58:35 +01002655intel_finish_fb(struct drm_framebuffer *old_fb)
2656{
Matt Roper2ff8fde2014-07-08 07:50:07 -07002657 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
Chris Wilson14667a42012-04-03 17:58:35 +01002658 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2659 bool was_interruptible = dev_priv->mm.interruptible;
2660 int ret;
2661
Chris Wilson14667a42012-04-03 17:58:35 +01002662 /* Big Hammer, we also need to ensure that any pending
2663 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2664 * current scanout is retired before unpinning the old
2665 * framebuffer.
2666 *
2667 * This should only fail upon a hung GPU, in which case we
2668 * can safely continue.
2669 */
2670 dev_priv->mm.interruptible = false;
2671 ret = i915_gem_object_finish_gpu(obj);
2672 dev_priv->mm.interruptible = was_interruptible;
2673
2674 return ret;
2675}
2676
Chris Wilson7d5e3792014-03-04 13:15:08 +00002677static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2678{
2679 struct drm_device *dev = crtc->dev;
2680 struct drm_i915_private *dev_priv = dev->dev_private;
2681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2682 unsigned long flags;
2683 bool pending;
2684
2685 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2686 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2687 return false;
2688
2689 spin_lock_irqsave(&dev->event_lock, flags);
2690 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2691 spin_unlock_irqrestore(&dev->event_lock, flags);
2692
2693 return pending;
2694}
2695
Chris Wilson14667a42012-04-03 17:58:35 +01002696static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002697intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002698 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002699{
2700 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002701 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02002703 enum pipe pipe = intel_crtc->pipe;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002704 struct drm_framebuffer *old_fb = crtc->primary->fb;
2705 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2706 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002707 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002708
Chris Wilson7d5e3792014-03-04 13:15:08 +00002709 if (intel_crtc_has_pending_flip(crtc)) {
2710 DRM_ERROR("pipe is still busy with an old pageflip\n");
2711 return -EBUSY;
2712 }
2713
Jesse Barnes79e53942008-11-07 14:24:08 -08002714 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002715 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002716 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002717 return 0;
2718 }
2719
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002720 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002721 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2722 plane_name(intel_crtc->plane),
2723 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002724 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002725 }
2726
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002727 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02002728 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2729 if (ret == 0)
Matt Roper91565c82014-06-24 17:05:02 -07002730 i915_gem_track_fb(old_obj, obj,
Daniel Vettera071fa02014-06-18 23:28:09 +02002731 INTEL_FRONTBUFFER_PRIMARY(pipe));
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002732 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002733 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002734 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002735 return ret;
2736 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002737
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002738 /*
2739 * Update pipe size and adjust fitter if needed: the reason for this is
2740 * that in compute_mode_changes we check the native mode (not the pfit
2741 * mode) to see if we can flip rather than do a full mode set. In the
2742 * fastboot case, we'll flip, but if we don't update the pipesrc and
2743 * pfit state, we'll end up with a big fb scanned out into the wrong
2744 * sized surface.
2745 *
2746 * To fix this properly, we need to hoist the checks up into
2747 * compute_mode_changes (or above), check the actual pfit state and
2748 * whether the platform allows pfit disable with pipe active, and only
2749 * then update the pipesrc and pfit state, even on the flip path.
2750 */
Jani Nikulad330a952014-01-21 11:24:25 +02002751 if (i915.fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002752 const struct drm_display_mode *adjusted_mode =
2753 &intel_crtc->config.adjusted_mode;
2754
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002755 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002756 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2757 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002758 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002759 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2760 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2761 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2762 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2763 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2764 }
Jesse Barnes0637d602013-12-19 10:48:01 -08002765 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2766 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002767 }
2768
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002769 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002770
Daniel Vetterf99d7062014-06-19 16:01:59 +02002771 if (intel_crtc->active)
2772 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2773
Matt Roperf4510a22014-04-01 15:22:40 -07002774 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002775 crtc->x = x;
2776 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002777
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002778 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002779 if (intel_crtc->active && old_fb != fb)
2780 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002781 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002782 intel_unpin_fb_obj(old_obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002783 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002784 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002785
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002786 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002787 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002788 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002789
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002790 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002791}
2792
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002793static void intel_fdi_normal_train(struct drm_crtc *crtc)
2794{
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2798 int pipe = intel_crtc->pipe;
2799 u32 reg, temp;
2800
2801 /* enable normal train */
2802 reg = FDI_TX_CTL(pipe);
2803 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002804 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002805 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2806 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002807 } else {
2808 temp &= ~FDI_LINK_TRAIN_NONE;
2809 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002810 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002811 I915_WRITE(reg, temp);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 if (HAS_PCH_CPT(dev)) {
2816 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2818 } else {
2819 temp &= ~FDI_LINK_TRAIN_NONE;
2820 temp |= FDI_LINK_TRAIN_NONE;
2821 }
2822 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2823
2824 /* wait one idle pattern time */
2825 POSTING_READ(reg);
2826 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002827
2828 /* IVB wants error correction enabled */
2829 if (IS_IVYBRIDGE(dev))
2830 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2831 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002832}
2833
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002834static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002835{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002836 return crtc->base.enabled && crtc->active &&
2837 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002838}
2839
Daniel Vetter01a415f2012-10-27 15:58:40 +02002840static void ivb_modeset_global_resources(struct drm_device *dev)
2841{
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843 struct intel_crtc *pipe_B_crtc =
2844 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2845 struct intel_crtc *pipe_C_crtc =
2846 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2847 uint32_t temp;
2848
Daniel Vetter1e833f42013-02-19 22:31:57 +01002849 /*
2850 * When everything is off disable fdi C so that we could enable fdi B
2851 * with all lanes. Note that we don't care about enabled pipes without
2852 * an enabled pch encoder.
2853 */
2854 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2855 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002856 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2857 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2858
2859 temp = I915_READ(SOUTH_CHICKEN1);
2860 temp &= ~FDI_BC_BIFURCATION_SELECT;
2861 DRM_DEBUG_KMS("disabling fdi C rx\n");
2862 I915_WRITE(SOUTH_CHICKEN1, temp);
2863 }
2864}
2865
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002866/* The FDI link training functions for ILK/Ibexpeak. */
2867static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2868{
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2872 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002873 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002874
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03002875 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002876 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002877
Adam Jacksone1a44742010-06-25 15:32:14 -04002878 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2879 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002880 reg = FDI_RX_IMR(pipe);
2881 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002882 temp &= ~FDI_RX_SYMBOL_LOCK;
2883 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002884 I915_WRITE(reg, temp);
2885 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002886 udelay(150);
2887
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002888 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002889 reg = FDI_TX_CTL(pipe);
2890 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002891 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2892 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002893 temp &= ~FDI_LINK_TRAIN_NONE;
2894 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002895 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002896
Chris Wilson5eddb702010-09-11 13:48:45 +01002897 reg = FDI_RX_CTL(pipe);
2898 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002899 temp &= ~FDI_LINK_TRAIN_NONE;
2900 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002901 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2902
2903 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002904 udelay(150);
2905
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002906 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002907 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2908 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2909 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002910
Chris Wilson5eddb702010-09-11 13:48:45 +01002911 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002912 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002913 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002914 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2915
2916 if ((temp & FDI_RX_BIT_LOCK)) {
2917 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002918 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002919 break;
2920 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002921 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002922 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002923 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002924
2925 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002926 reg = FDI_TX_CTL(pipe);
2927 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002928 temp &= ~FDI_LINK_TRAIN_NONE;
2929 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002930 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002931
Chris Wilson5eddb702010-09-11 13:48:45 +01002932 reg = FDI_RX_CTL(pipe);
2933 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002934 temp &= ~FDI_LINK_TRAIN_NONE;
2935 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002936 I915_WRITE(reg, temp);
2937
2938 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002939 udelay(150);
2940
Chris Wilson5eddb702010-09-11 13:48:45 +01002941 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002942 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002943 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002944 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2945
2946 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002947 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002948 DRM_DEBUG_KMS("FDI train 2 done.\n");
2949 break;
2950 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002951 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002952 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002953 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002954
2955 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002956
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002957}
2958
Akshay Joshi0206e352011-08-16 15:34:10 -04002959static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002960 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2961 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2962 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2963 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2964};
2965
2966/* The FDI link training functions for SNB/Cougarpoint. */
2967static void gen6_fdi_link_train(struct drm_crtc *crtc)
2968{
2969 struct drm_device *dev = crtc->dev;
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002973 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002974
Adam Jacksone1a44742010-06-25 15:32:14 -04002975 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2976 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002977 reg = FDI_RX_IMR(pipe);
2978 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002979 temp &= ~FDI_RX_SYMBOL_LOCK;
2980 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002981 I915_WRITE(reg, temp);
2982
2983 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002984 udelay(150);
2985
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002986 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002987 reg = FDI_TX_CTL(pipe);
2988 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002989 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2990 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002991 temp &= ~FDI_LINK_TRAIN_NONE;
2992 temp |= FDI_LINK_TRAIN_PATTERN_1;
2993 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2994 /* SNB-B */
2995 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002996 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002997
Daniel Vetterd74cf322012-10-26 10:58:13 +02002998 I915_WRITE(FDI_RX_MISC(pipe),
2999 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3000
Chris Wilson5eddb702010-09-11 13:48:45 +01003001 reg = FDI_RX_CTL(pipe);
3002 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003003 if (HAS_PCH_CPT(dev)) {
3004 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3005 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3006 } else {
3007 temp &= ~FDI_LINK_TRAIN_NONE;
3008 temp |= FDI_LINK_TRAIN_PATTERN_1;
3009 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003010 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3011
3012 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003013 udelay(150);
3014
Akshay Joshi0206e352011-08-16 15:34:10 -04003015 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003016 reg = FDI_TX_CTL(pipe);
3017 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003018 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3019 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003020 I915_WRITE(reg, temp);
3021
3022 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003023 udelay(500);
3024
Sean Paulfa37d392012-03-02 12:53:39 -05003025 for (retry = 0; retry < 5; retry++) {
3026 reg = FDI_RX_IIR(pipe);
3027 temp = I915_READ(reg);
3028 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3029 if (temp & FDI_RX_BIT_LOCK) {
3030 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3031 DRM_DEBUG_KMS("FDI train 1 done.\n");
3032 break;
3033 }
3034 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003035 }
Sean Paulfa37d392012-03-02 12:53:39 -05003036 if (retry < 5)
3037 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003038 }
3039 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003040 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003041
3042 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003043 reg = FDI_TX_CTL(pipe);
3044 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003045 temp &= ~FDI_LINK_TRAIN_NONE;
3046 temp |= FDI_LINK_TRAIN_PATTERN_2;
3047 if (IS_GEN6(dev)) {
3048 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3049 /* SNB-B */
3050 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3051 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003052 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003053
Chris Wilson5eddb702010-09-11 13:48:45 +01003054 reg = FDI_RX_CTL(pipe);
3055 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003056 if (HAS_PCH_CPT(dev)) {
3057 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3058 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3059 } else {
3060 temp &= ~FDI_LINK_TRAIN_NONE;
3061 temp |= FDI_LINK_TRAIN_PATTERN_2;
3062 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003063 I915_WRITE(reg, temp);
3064
3065 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003066 udelay(150);
3067
Akshay Joshi0206e352011-08-16 15:34:10 -04003068 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003069 reg = FDI_TX_CTL(pipe);
3070 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003071 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3072 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003073 I915_WRITE(reg, temp);
3074
3075 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003076 udelay(500);
3077
Sean Paulfa37d392012-03-02 12:53:39 -05003078 for (retry = 0; retry < 5; retry++) {
3079 reg = FDI_RX_IIR(pipe);
3080 temp = I915_READ(reg);
3081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082 if (temp & FDI_RX_SYMBOL_LOCK) {
3083 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3084 DRM_DEBUG_KMS("FDI train 2 done.\n");
3085 break;
3086 }
3087 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003088 }
Sean Paulfa37d392012-03-02 12:53:39 -05003089 if (retry < 5)
3090 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003091 }
3092 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003093 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003094
3095 DRM_DEBUG_KMS("FDI train done.\n");
3096}
3097
Jesse Barnes357555c2011-04-28 15:09:55 -07003098/* Manual link training for Ivy Bridge A0 parts */
3099static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3100{
3101 struct drm_device *dev = crtc->dev;
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3104 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003105 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003106
3107 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3108 for train result */
3109 reg = FDI_RX_IMR(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_RX_SYMBOL_LOCK;
3112 temp &= ~FDI_RX_BIT_LOCK;
3113 I915_WRITE(reg, temp);
3114
3115 POSTING_READ(reg);
3116 udelay(150);
3117
Daniel Vetter01a415f2012-10-27 15:58:40 +02003118 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3119 I915_READ(FDI_RX_IIR(pipe)));
3120
Jesse Barnes139ccd32013-08-19 11:04:55 -07003121 /* Try each vswing and preemphasis setting twice before moving on */
3122 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3123 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003124 reg = FDI_TX_CTL(pipe);
3125 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003126 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3127 temp &= ~FDI_TX_ENABLE;
3128 I915_WRITE(reg, temp);
3129
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 temp &= ~FDI_LINK_TRAIN_AUTO;
3133 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3134 temp &= ~FDI_RX_ENABLE;
3135 I915_WRITE(reg, temp);
3136
3137 /* enable CPU FDI TX and PCH FDI RX */
3138 reg = FDI_TX_CTL(pipe);
3139 temp = I915_READ(reg);
3140 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3141 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3142 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003143 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003144 temp |= snb_b_fdi_train_param[j/2];
3145 temp |= FDI_COMPOSITE_SYNC;
3146 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3147
3148 I915_WRITE(FDI_RX_MISC(pipe),
3149 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3150
3151 reg = FDI_RX_CTL(pipe);
3152 temp = I915_READ(reg);
3153 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3154 temp |= FDI_COMPOSITE_SYNC;
3155 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3156
3157 POSTING_READ(reg);
3158 udelay(1); /* should be 0.5us */
3159
3160 for (i = 0; i < 4; i++) {
3161 reg = FDI_RX_IIR(pipe);
3162 temp = I915_READ(reg);
3163 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3164
3165 if (temp & FDI_RX_BIT_LOCK ||
3166 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3167 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3168 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3169 i);
3170 break;
3171 }
3172 udelay(1); /* should be 0.5us */
3173 }
3174 if (i == 4) {
3175 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3176 continue;
3177 }
3178
3179 /* Train 2 */
3180 reg = FDI_TX_CTL(pipe);
3181 temp = I915_READ(reg);
3182 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3183 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3184 I915_WRITE(reg, temp);
3185
3186 reg = FDI_RX_CTL(pipe);
3187 temp = I915_READ(reg);
3188 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3189 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003190 I915_WRITE(reg, temp);
3191
3192 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003193 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003194
Jesse Barnes139ccd32013-08-19 11:04:55 -07003195 for (i = 0; i < 4; i++) {
3196 reg = FDI_RX_IIR(pipe);
3197 temp = I915_READ(reg);
3198 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003199
Jesse Barnes139ccd32013-08-19 11:04:55 -07003200 if (temp & FDI_RX_SYMBOL_LOCK ||
3201 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3202 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3203 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3204 i);
3205 goto train_done;
3206 }
3207 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003208 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003209 if (i == 4)
3210 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003211 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003212
Jesse Barnes139ccd32013-08-19 11:04:55 -07003213train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003214 DRM_DEBUG_KMS("FDI train done.\n");
3215}
3216
Daniel Vetter88cefb62012-08-12 19:27:14 +02003217static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003218{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003219 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003220 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003221 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003222 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003223
Jesse Barnesc64e3112010-09-10 11:27:03 -07003224
Jesse Barnes0e23b992010-09-10 11:10:00 -07003225 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003226 reg = FDI_RX_CTL(pipe);
3227 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003228 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3229 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003230 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003231 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3232
3233 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003234 udelay(200);
3235
3236 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003237 temp = I915_READ(reg);
3238 I915_WRITE(reg, temp | FDI_PCDCLK);
3239
3240 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003241 udelay(200);
3242
Paulo Zanoni20749732012-11-23 15:30:38 -02003243 /* Enable CPU FDI TX PLL, always on for Ironlake */
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
3246 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3247 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003248
Paulo Zanoni20749732012-11-23 15:30:38 -02003249 POSTING_READ(reg);
3250 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003251 }
3252}
3253
Daniel Vetter88cefb62012-08-12 19:27:14 +02003254static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3255{
3256 struct drm_device *dev = intel_crtc->base.dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 int pipe = intel_crtc->pipe;
3259 u32 reg, temp;
3260
3261 /* Switch from PCDclk to Rawclk */
3262 reg = FDI_RX_CTL(pipe);
3263 temp = I915_READ(reg);
3264 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3265
3266 /* Disable CPU FDI TX PLL */
3267 reg = FDI_TX_CTL(pipe);
3268 temp = I915_READ(reg);
3269 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3270
3271 POSTING_READ(reg);
3272 udelay(100);
3273
3274 reg = FDI_RX_CTL(pipe);
3275 temp = I915_READ(reg);
3276 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3277
3278 /* Wait for the clocks to turn off. */
3279 POSTING_READ(reg);
3280 udelay(100);
3281}
3282
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003283static void ironlake_fdi_disable(struct drm_crtc *crtc)
3284{
3285 struct drm_device *dev = crtc->dev;
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288 int pipe = intel_crtc->pipe;
3289 u32 reg, temp;
3290
3291 /* disable CPU FDI tx and PCH FDI rx */
3292 reg = FDI_TX_CTL(pipe);
3293 temp = I915_READ(reg);
3294 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3295 POSTING_READ(reg);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003300 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003301 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3302
3303 POSTING_READ(reg);
3304 udelay(100);
3305
3306 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003307 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003308 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003309
3310 /* still set train pattern 1 */
3311 reg = FDI_TX_CTL(pipe);
3312 temp = I915_READ(reg);
3313 temp &= ~FDI_LINK_TRAIN_NONE;
3314 temp |= FDI_LINK_TRAIN_PATTERN_1;
3315 I915_WRITE(reg, temp);
3316
3317 reg = FDI_RX_CTL(pipe);
3318 temp = I915_READ(reg);
3319 if (HAS_PCH_CPT(dev)) {
3320 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3321 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3322 } else {
3323 temp &= ~FDI_LINK_TRAIN_NONE;
3324 temp |= FDI_LINK_TRAIN_PATTERN_1;
3325 }
3326 /* BPC in FDI rx is consistent with that in PIPECONF */
3327 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003328 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003329 I915_WRITE(reg, temp);
3330
3331 POSTING_READ(reg);
3332 udelay(100);
3333}
3334
Chris Wilson5dce5b932014-01-20 10:17:36 +00003335bool intel_has_pending_fb_unpin(struct drm_device *dev)
3336{
3337 struct intel_crtc *crtc;
3338
3339 /* Note that we don't need to be called with mode_config.lock here
3340 * as our list of CRTC objects is static for the lifetime of the
3341 * device and so cannot disappear as we iterate. Similarly, we can
3342 * happily treat the predicates as racy, atomic checks as userspace
3343 * cannot claim and pin a new fb without at least acquring the
3344 * struct_mutex and so serialising with us.
3345 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003346 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003347 if (atomic_read(&crtc->unpin_work_count) == 0)
3348 continue;
3349
3350 if (crtc->unpin_work)
3351 intel_wait_for_vblank(dev, crtc->pipe);
3352
3353 return true;
3354 }
3355
3356 return false;
3357}
3358
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003359void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003360{
Chris Wilson0f911282012-04-17 10:05:38 +01003361 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003362 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003363
Matt Roperf4510a22014-04-01 15:22:40 -07003364 if (crtc->primary->fb == NULL)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003365 return;
3366
Daniel Vetter2c10d572012-12-20 21:24:07 +01003367 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3368
Daniel Vettereed6d672014-05-19 16:09:35 +02003369 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3370 !intel_crtc_has_pending_flip(crtc),
3371 60*HZ) == 0);
Chris Wilson5bb61642012-09-27 21:25:58 +01003372
Chris Wilson0f911282012-04-17 10:05:38 +01003373 mutex_lock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07003374 intel_finish_fb(crtc->primary->fb);
Chris Wilson0f911282012-04-17 10:05:38 +01003375 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003376}
3377
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003378/* Program iCLKIP clock to the desired frequency */
3379static void lpt_program_iclkip(struct drm_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003383 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003384 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3385 u32 temp;
3386
Daniel Vetter09153002012-12-12 14:06:44 +01003387 mutex_lock(&dev_priv->dpio_lock);
3388
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003389 /* It is necessary to ungate the pixclk gate prior to programming
3390 * the divisors, and gate it back when it is done.
3391 */
3392 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3393
3394 /* Disable SSCCTL */
3395 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003396 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3397 SBI_SSCCTL_DISABLE,
3398 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003399
3400 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003401 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003402 auxdiv = 1;
3403 divsel = 0x41;
3404 phaseinc = 0x20;
3405 } else {
3406 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003407 * but the adjusted_mode->crtc_clock in in KHz. To get the
3408 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003409 * convert the virtual clock precision to KHz here for higher
3410 * precision.
3411 */
3412 u32 iclk_virtual_root_freq = 172800 * 1000;
3413 u32 iclk_pi_range = 64;
3414 u32 desired_divisor, msb_divisor_value, pi_value;
3415
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003416 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003417 msb_divisor_value = desired_divisor / iclk_pi_range;
3418 pi_value = desired_divisor % iclk_pi_range;
3419
3420 auxdiv = 0;
3421 divsel = msb_divisor_value - 2;
3422 phaseinc = pi_value;
3423 }
3424
3425 /* This should not happen with any sane values */
3426 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3427 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3428 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3429 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3430
3431 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003432 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003433 auxdiv,
3434 divsel,
3435 phasedir,
3436 phaseinc);
3437
3438 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003439 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003440 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3441 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3442 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3443 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3444 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3445 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003446 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003447
3448 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003449 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003450 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3451 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003452 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003453
3454 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003455 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003456 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003457 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003458
3459 /* Wait for initialization time */
3460 udelay(24);
3461
3462 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003463
3464 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003465}
3466
Daniel Vetter275f01b22013-05-03 11:49:47 +02003467static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3468 enum pipe pch_transcoder)
3469{
3470 struct drm_device *dev = crtc->base.dev;
3471 struct drm_i915_private *dev_priv = dev->dev_private;
3472 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3473
3474 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3475 I915_READ(HTOTAL(cpu_transcoder)));
3476 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3477 I915_READ(HBLANK(cpu_transcoder)));
3478 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3479 I915_READ(HSYNC(cpu_transcoder)));
3480
3481 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3482 I915_READ(VTOTAL(cpu_transcoder)));
3483 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3484 I915_READ(VBLANK(cpu_transcoder)));
3485 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3486 I915_READ(VSYNC(cpu_transcoder)));
3487 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3488 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3489}
3490
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003491static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3492{
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 uint32_t temp;
3495
3496 temp = I915_READ(SOUTH_CHICKEN1);
3497 if (temp & FDI_BC_BIFURCATION_SELECT)
3498 return;
3499
3500 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3501 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3502
3503 temp |= FDI_BC_BIFURCATION_SELECT;
3504 DRM_DEBUG_KMS("enabling fdi C rx\n");
3505 I915_WRITE(SOUTH_CHICKEN1, temp);
3506 POSTING_READ(SOUTH_CHICKEN1);
3507}
3508
3509static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3510{
3511 struct drm_device *dev = intel_crtc->base.dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513
3514 switch (intel_crtc->pipe) {
3515 case PIPE_A:
3516 break;
3517 case PIPE_B:
3518 if (intel_crtc->config.fdi_lanes > 2)
3519 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3520 else
3521 cpt_enable_fdi_bc_bifurcation(dev);
3522
3523 break;
3524 case PIPE_C:
3525 cpt_enable_fdi_bc_bifurcation(dev);
3526
3527 break;
3528 default:
3529 BUG();
3530 }
3531}
3532
Jesse Barnesf67a5592011-01-05 10:31:48 -08003533/*
3534 * Enable PCH resources required for PCH ports:
3535 * - PCH PLLs
3536 * - FDI training & RX/TX
3537 * - update transcoder timings
3538 * - DP transcoding bits
3539 * - transcoder
3540 */
3541static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003542{
3543 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003547 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003548
Daniel Vetterab9412b2013-05-03 11:49:46 +02003549 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003550
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003551 if (IS_IVYBRIDGE(dev))
3552 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3553
Daniel Vettercd986ab2012-10-26 10:58:12 +02003554 /* Write the TU size bits before fdi link training, so that error
3555 * detection works. */
3556 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3557 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3558
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003559 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003560 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003561
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003562 /* We need to program the right clock selection before writing the pixel
3563 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003564 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003565 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003566
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003567 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003568 temp |= TRANS_DPLL_ENABLE(pipe);
3569 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003570 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003571 temp |= sel;
3572 else
3573 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003574 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003575 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003576
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003577 /* XXX: pch pll's can be enabled any time before we enable the PCH
3578 * transcoder, and we actually should do this to not upset any PCH
3579 * transcoder that already use the clock when we share it.
3580 *
3581 * Note that enable_shared_dpll tries to do the right thing, but
3582 * get_shared_dpll unconditionally resets the pll - we need that to have
3583 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003584 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003585
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003586 /* set transcoder timing, panel must allow it */
3587 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003588 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003589
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003590 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003591
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003592 /* For PCH DP, enable TRANS_DP_CTL */
3593 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003594 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3595 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003596 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003597 reg = TRANS_DP_CTL(pipe);
3598 temp = I915_READ(reg);
3599 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003600 TRANS_DP_SYNC_MASK |
3601 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003602 temp |= (TRANS_DP_OUTPUT_ENABLE |
3603 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003604 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003605
3606 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003607 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003608 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003609 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003610
3611 switch (intel_trans_dp_port_sel(crtc)) {
3612 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003613 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003614 break;
3615 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003616 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003617 break;
3618 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003619 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003620 break;
3621 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003622 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003623 }
3624
Chris Wilson5eddb702010-09-11 13:48:45 +01003625 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003626 }
3627
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003628 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003629}
3630
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003631static void lpt_pch_enable(struct drm_crtc *crtc)
3632{
3633 struct drm_device *dev = crtc->dev;
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003636 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003637
Daniel Vetterab9412b2013-05-03 11:49:46 +02003638 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003639
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003640 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003641
Paulo Zanoni0540e482012-10-31 18:12:40 -02003642 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003643 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003644
Paulo Zanoni937bb612012-10-31 18:12:47 -02003645 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003646}
3647
Daniel Vetter716c2e52014-06-25 22:02:02 +03003648void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003649{
Daniel Vettere2b78262013-06-07 23:10:03 +02003650 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003651
3652 if (pll == NULL)
3653 return;
3654
3655 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003656 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003657 return;
3658 }
3659
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003660 if (--pll->refcount == 0) {
3661 WARN_ON(pll->on);
3662 WARN_ON(pll->active);
3663 }
3664
Daniel Vettera43f6e02013-06-07 23:10:32 +02003665 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003666}
3667
Daniel Vetter716c2e52014-06-25 22:02:02 +03003668struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003669{
Daniel Vettere2b78262013-06-07 23:10:03 +02003670 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3671 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3672 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003673
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003674 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003675 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3676 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003677 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003678 }
3679
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003680 if (HAS_PCH_IBX(dev_priv->dev)) {
3681 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003682 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003683 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003684
Daniel Vetter46edb022013-06-05 13:34:12 +02003685 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3686 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003687
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003688 WARN_ON(pll->refcount);
3689
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003690 goto found;
3691 }
3692
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003693 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3694 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003695
3696 /* Only want to check enabled timings first */
3697 if (pll->refcount == 0)
3698 continue;
3699
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003700 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3701 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003702 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003703 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003704 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003705
3706 goto found;
3707 }
3708 }
3709
3710 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003711 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3712 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003713 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003714 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3715 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003716 goto found;
3717 }
3718 }
3719
3720 return NULL;
3721
3722found:
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003723 if (pll->refcount == 0)
3724 pll->hw_state = crtc->config.dpll_hw_state;
3725
Daniel Vettera43f6e02013-06-07 23:10:32 +02003726 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003727 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3728 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003729
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003730 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003731
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003732 return pll;
3733}
3734
Daniel Vettera1520312013-05-03 11:49:50 +02003735static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003736{
3737 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003738 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003739 u32 temp;
3740
3741 temp = I915_READ(dslreg);
3742 udelay(500);
3743 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003744 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003745 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003746 }
3747}
3748
Jesse Barnesb074cec2013-04-25 12:55:02 -07003749static void ironlake_pfit_enable(struct intel_crtc *crtc)
3750{
3751 struct drm_device *dev = crtc->base.dev;
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753 int pipe = crtc->pipe;
3754
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003755 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003756 /* Force use of hard-coded filter coefficients
3757 * as some pre-programmed values are broken,
3758 * e.g. x201.
3759 */
3760 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3761 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3762 PF_PIPE_SEL_IVB(pipe));
3763 else
3764 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3765 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3766 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003767 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003768}
3769
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003770static void intel_enable_planes(struct drm_crtc *crtc)
3771{
3772 struct drm_device *dev = crtc->dev;
3773 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003774 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003775 struct intel_plane *intel_plane;
3776
Matt Roperaf2b6532014-04-01 15:22:32 -07003777 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3778 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003779 if (intel_plane->pipe == pipe)
3780 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003781 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003782}
3783
3784static void intel_disable_planes(struct drm_crtc *crtc)
3785{
3786 struct drm_device *dev = crtc->dev;
3787 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07003788 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003789 struct intel_plane *intel_plane;
3790
Matt Roperaf2b6532014-04-01 15:22:32 -07003791 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3792 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003793 if (intel_plane->pipe == pipe)
3794 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07003795 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003796}
3797
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003798void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003799{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003800 struct drm_device *dev = crtc->base.dev;
3801 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03003802
3803 if (!crtc->config.ips_enabled)
3804 return;
3805
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003806 /* We can only enable IPS after we enable a plane and wait for a vblank */
3807 intel_wait_for_vblank(dev, crtc->pipe);
3808
Paulo Zanonid77e4532013-09-24 13:52:55 -03003809 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03003810 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003811 mutex_lock(&dev_priv->rps.hw_lock);
3812 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3813 mutex_unlock(&dev_priv->rps.hw_lock);
3814 /* Quoting Art Runyan: "its not safe to expect any particular
3815 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08003816 * mailbox." Moreover, the mailbox may return a bogus state,
3817 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003818 */
3819 } else {
3820 I915_WRITE(IPS_CTL, IPS_ENABLE);
3821 /* The bit only becomes 1 in the next vblank, so this wait here
3822 * is essentially intel_wait_for_vblank. If we don't have this
3823 * and don't wait for vblanks until the end of crtc_enable, then
3824 * the HW state readout code will complain that the expected
3825 * IPS_CTL value is not the one we read. */
3826 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3827 DRM_ERROR("Timed out waiting for IPS enable\n");
3828 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003829}
3830
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003831void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003832{
3833 struct drm_device *dev = crtc->base.dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835
3836 if (!crtc->config.ips_enabled)
3837 return;
3838
3839 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003840 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003841 mutex_lock(&dev_priv->rps.hw_lock);
3842 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3843 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07003844 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3845 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3846 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08003847 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003848 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08003849 POSTING_READ(IPS_CTL);
3850 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003851
3852 /* We need to wait for a vblank before we can disable the plane. */
3853 intel_wait_for_vblank(dev, crtc->pipe);
3854}
3855
3856/** Loads the palette/gamma unit for the CRTC with the prepared values */
3857static void intel_crtc_load_lut(struct drm_crtc *crtc)
3858{
3859 struct drm_device *dev = crtc->dev;
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862 enum pipe pipe = intel_crtc->pipe;
3863 int palreg = PALETTE(pipe);
3864 int i;
3865 bool reenable_ips = false;
3866
3867 /* The clocks have to be on to load the palette. */
3868 if (!crtc->enabled || !intel_crtc->active)
3869 return;
3870
3871 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3872 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3873 assert_dsi_pll_enabled(dev_priv);
3874 else
3875 assert_pll_enabled(dev_priv, pipe);
3876 }
3877
3878 /* use legacy palette for Ironlake */
Sonika Jindal7a1db492014-07-22 11:18:27 +05303879 if (!HAS_GMCH_DISPLAY(dev))
Paulo Zanonid77e4532013-09-24 13:52:55 -03003880 palreg = LGC_PALETTE(pipe);
3881
3882 /* Workaround : Do not read or write the pipe palette/gamma data while
3883 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3884 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02003885 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03003886 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3887 GAMMA_MODE_MODE_SPLIT)) {
3888 hsw_disable_ips(intel_crtc);
3889 reenable_ips = true;
3890 }
3891
3892 for (i = 0; i < 256; i++) {
3893 I915_WRITE(palreg + 4 * i,
3894 (intel_crtc->lut_r[i] << 16) |
3895 (intel_crtc->lut_g[i] << 8) |
3896 intel_crtc->lut_b[i]);
3897 }
3898
3899 if (reenable_ips)
3900 hsw_enable_ips(intel_crtc);
3901}
3902
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003903static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3904{
3905 if (!enable && intel_crtc->overlay) {
3906 struct drm_device *dev = intel_crtc->base.dev;
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909 mutex_lock(&dev->struct_mutex);
3910 dev_priv->mm.interruptible = false;
3911 (void) intel_overlay_switch_off(intel_crtc->overlay);
3912 dev_priv->mm.interruptible = true;
3913 mutex_unlock(&dev->struct_mutex);
3914 }
3915
3916 /* Let userspace switch the overlay on again. In most cases userspace
3917 * has to recompute where to put it anyway.
3918 */
3919}
3920
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003921static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003922{
3923 struct drm_device *dev = crtc->dev;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3925 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003926
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003927 drm_vblank_on(dev, pipe);
3928
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03003929 intel_enable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003930 intel_enable_planes(crtc);
3931 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003932 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003933
3934 hsw_enable_ips(intel_crtc);
3935
3936 mutex_lock(&dev->struct_mutex);
3937 intel_update_fbc(dev);
3938 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf99d7062014-06-19 16:01:59 +02003939
3940 /*
3941 * FIXME: Once we grow proper nuclear flip support out of this we need
3942 * to compute the mask of flip planes precisely. For the time being
3943 * consider this a flip from a NULL plane.
3944 */
3945 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003946}
3947
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003948static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003949{
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3953 int pipe = intel_crtc->pipe;
3954 int plane = intel_crtc->plane;
3955
3956 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003957
3958 if (dev_priv->fbc.plane == plane)
3959 intel_disable_fbc(dev);
3960
3961 hsw_disable_ips(intel_crtc);
3962
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03003963 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003964 intel_crtc_update_cursor(crtc, false);
3965 intel_disable_planes(crtc);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03003966 intel_disable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003967
Daniel Vetterf99d7062014-06-19 16:01:59 +02003968 /*
3969 * FIXME: Once we grow proper nuclear flip support out of this we need
3970 * to compute the mask of flip planes precisely. For the time being
3971 * consider this a flip to a NULL plane.
3972 */
3973 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3974
Ville Syrjäläf98551a2014-05-22 17:48:06 +03003975 drm_vblank_off(dev, pipe);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02003976}
3977
Jesse Barnesf67a5592011-01-05 10:31:48 -08003978static void ironlake_crtc_enable(struct drm_crtc *crtc)
3979{
3980 struct drm_device *dev = crtc->dev;
3981 struct drm_i915_private *dev_priv = dev->dev_private;
3982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003983 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003984 int pipe = intel_crtc->pipe;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003985
Daniel Vetter08a48462012-07-02 11:43:47 +02003986 WARN_ON(!crtc->enabled);
3987
Jesse Barnesf67a5592011-01-05 10:31:48 -08003988 if (intel_crtc->active)
3989 return;
3990
Daniel Vetterb14b1052014-04-24 23:55:13 +02003991 if (intel_crtc->config.has_pch_encoder)
3992 intel_prepare_shared_dpll(intel_crtc);
3993
Daniel Vetter29407aa2014-04-24 23:55:08 +02003994 if (intel_crtc->config.has_dp_encoder)
3995 intel_dp_set_m_n(intel_crtc);
3996
3997 intel_set_pipe_timings(intel_crtc);
3998
3999 if (intel_crtc->config.has_pch_encoder) {
4000 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004001 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004002 }
4003
4004 ironlake_set_pipeconf(crtc);
4005
Jesse Barnesf67a5592011-01-05 10:31:48 -08004006 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004007
4008 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4009 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4010
Daniel Vetterf6736a12013-06-05 13:34:30 +02004011 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02004012 if (encoder->pre_enable)
4013 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004014
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004015 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02004016 /* Note: FDI PLL enabling _must_ be done before we enable the
4017 * cpu pipes, hence this is separate from all the other fdi/pch
4018 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02004019 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02004020 } else {
4021 assert_fdi_tx_disabled(dev_priv, pipe);
4022 assert_fdi_rx_disabled(dev_priv, pipe);
4023 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004024
Jesse Barnesb074cec2013-04-25 12:55:02 -07004025 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004026
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02004027 /*
4028 * On ILK+ LUT must be loaded before the pipe is running but with
4029 * clocks enabled
4030 */
4031 intel_crtc_load_lut(crtc);
4032
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004033 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004034 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004035
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004036 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004037 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004038
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004039 for_each_encoder_on_crtc(dev, crtc, encoder)
4040 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004041
4042 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004043 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004044
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004045 intel_crtc_enable_planes(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004046}
4047
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004048/* IPS only exists on ULT machines and is tied to pipe A. */
4049static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4050{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004051 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004052}
4053
Paulo Zanonie4916942013-09-20 16:21:19 -03004054/*
4055 * This implements the workaround described in the "notes" section of the mode
4056 * set sequence documentation. When going from no pipes or single pipe to
4057 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4058 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4059 */
4060static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4061{
4062 struct drm_device *dev = crtc->base.dev;
4063 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4064
4065 /* We want to get the other_active_crtc only if there's only 1 other
4066 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004067 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004068 if (!crtc_it->active || crtc_it == crtc)
4069 continue;
4070
4071 if (other_active_crtc)
4072 return;
4073
4074 other_active_crtc = crtc_it;
4075 }
4076 if (!other_active_crtc)
4077 return;
4078
4079 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4080 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4081}
4082
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004083static void haswell_crtc_enable(struct drm_crtc *crtc)
4084{
4085 struct drm_device *dev = crtc->dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088 struct intel_encoder *encoder;
4089 int pipe = intel_crtc->pipe;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004090
4091 WARN_ON(!crtc->enabled);
4092
4093 if (intel_crtc->active)
4094 return;
4095
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004096 if (intel_crtc_to_shared_dpll(intel_crtc))
4097 intel_enable_shared_dpll(intel_crtc);
4098
Daniel Vetter229fca92014-04-24 23:55:09 +02004099 if (intel_crtc->config.has_dp_encoder)
4100 intel_dp_set_m_n(intel_crtc);
4101
4102 intel_set_pipe_timings(intel_crtc);
4103
4104 if (intel_crtc->config.has_pch_encoder) {
4105 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004106 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02004107 }
4108
4109 haswell_set_pipeconf(crtc);
4110
4111 intel_set_pipe_csc(crtc);
4112
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004113 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004114
4115 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004116 for_each_encoder_on_crtc(dev, crtc, encoder)
4117 if (encoder->pre_enable)
4118 encoder->pre_enable(encoder);
4119
Imre Deak4fe94672014-06-25 22:01:49 +03004120 if (intel_crtc->config.has_pch_encoder) {
4121 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4122 dev_priv->display.fdi_link_train(crtc);
4123 }
4124
Paulo Zanoni1f544382012-10-24 11:32:00 -02004125 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004126
Jesse Barnesb074cec2013-04-25 12:55:02 -07004127 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004128
4129 /*
4130 * On ILK+ LUT must be loaded before the pipe is running but with
4131 * clocks enabled
4132 */
4133 intel_crtc_load_lut(crtc);
4134
Paulo Zanoni1f544382012-10-24 11:32:00 -02004135 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004136 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004137
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004138 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004139 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004140
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004141 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004142 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004143
Dave Airlie0e32b392014-05-02 14:02:48 +10004144 if (intel_crtc->config.dp_encoder_is_mst)
4145 intel_ddi_set_vc_payload_alloc(crtc, true);
4146
Jani Nikula8807e552013-08-30 19:40:32 +03004147 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004148 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004149 intel_opregion_notify_encoder(encoder, true);
4150 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004151
Paulo Zanonie4916942013-09-20 16:21:19 -03004152 /* If we change the relative order between pipe/planes enabling, we need
4153 * to change the workaround. */
4154 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004155 intel_crtc_enable_planes(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004156}
4157
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004158static void ironlake_pfit_disable(struct intel_crtc *crtc)
4159{
4160 struct drm_device *dev = crtc->base.dev;
4161 struct drm_i915_private *dev_priv = dev->dev_private;
4162 int pipe = crtc->pipe;
4163
4164 /* To avoid upsetting the power well on haswell only disable the pfit if
4165 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004166 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004167 I915_WRITE(PF_CTL(pipe), 0);
4168 I915_WRITE(PF_WIN_POS(pipe), 0);
4169 I915_WRITE(PF_WIN_SZ(pipe), 0);
4170 }
4171}
4172
Jesse Barnes6be4a602010-09-10 10:26:01 -07004173static void ironlake_crtc_disable(struct drm_crtc *crtc)
4174{
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004178 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004179 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004180 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004181
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004182 if (!intel_crtc->active)
4183 return;
4184
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004185 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004186
Daniel Vetterea9d7582012-07-10 10:42:52 +02004187 for_each_encoder_on_crtc(dev, crtc, encoder)
4188 encoder->disable(encoder);
4189
Daniel Vetterd925c592013-06-05 13:34:04 +02004190 if (intel_crtc->config.has_pch_encoder)
4191 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4192
Jesse Barnesb24e7172011-01-04 15:09:30 -08004193 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004194
Dave Airlie0e32b392014-05-02 14:02:48 +10004195 if (intel_crtc->config.dp_encoder_is_mst)
4196 intel_ddi_set_vc_payload_alloc(crtc, false);
4197
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004198 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004199
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004200 for_each_encoder_on_crtc(dev, crtc, encoder)
4201 if (encoder->post_disable)
4202 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004203
Daniel Vetterd925c592013-06-05 13:34:04 +02004204 if (intel_crtc->config.has_pch_encoder) {
4205 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004206
Daniel Vetterd925c592013-06-05 13:34:04 +02004207 ironlake_disable_pch_transcoder(dev_priv, pipe);
4208 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004209
Daniel Vetterd925c592013-06-05 13:34:04 +02004210 if (HAS_PCH_CPT(dev)) {
4211 /* disable TRANS_DP_CTL */
4212 reg = TRANS_DP_CTL(pipe);
4213 temp = I915_READ(reg);
4214 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4215 TRANS_DP_PORT_SEL_MASK);
4216 temp |= TRANS_DP_PORT_SEL_NONE;
4217 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004218
Daniel Vetterd925c592013-06-05 13:34:04 +02004219 /* disable DPLL_SEL */
4220 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004221 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004222 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004223 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004224
4225 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004226 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004227
4228 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004229 }
4230
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004231 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004232 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004233
4234 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004235 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004236 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004237}
4238
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004239static void haswell_crtc_disable(struct drm_crtc *crtc)
4240{
4241 struct drm_device *dev = crtc->dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4244 struct intel_encoder *encoder;
4245 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004246 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004247
4248 if (!intel_crtc->active)
4249 return;
4250
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004251 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004252
Jani Nikula8807e552013-08-30 19:40:32 +03004253 for_each_encoder_on_crtc(dev, crtc, encoder) {
4254 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004255 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004256 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004257
Paulo Zanoni86642812013-04-12 17:57:57 -03004258 if (intel_crtc->config.has_pch_encoder)
4259 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004260 intel_disable_pipe(dev_priv, pipe);
4261
Paulo Zanoniad80a812012-10-24 16:06:19 -02004262 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004263
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004264 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004265
Paulo Zanoni1f544382012-10-24 11:32:00 -02004266 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004267
Daniel Vetter88adfff2013-03-28 10:42:01 +01004268 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004269 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03004270 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004271 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004272 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004273
Imre Deak97b040a2014-06-25 22:01:50 +03004274 for_each_encoder_on_crtc(dev, crtc, encoder)
4275 if (encoder->post_disable)
4276 encoder->post_disable(encoder);
4277
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004278 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004279 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004280
4281 mutex_lock(&dev->struct_mutex);
4282 intel_update_fbc(dev);
4283 mutex_unlock(&dev->struct_mutex);
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004284
4285 if (intel_crtc_to_shared_dpll(intel_crtc))
4286 intel_disable_shared_dpll(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004287}
4288
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004289static void ironlake_crtc_off(struct drm_crtc *crtc)
4290{
4291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004292 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004293}
4294
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004295
Jesse Barnes2dd24552013-04-25 12:55:01 -07004296static void i9xx_pfit_enable(struct intel_crtc *crtc)
4297{
4298 struct drm_device *dev = crtc->base.dev;
4299 struct drm_i915_private *dev_priv = dev->dev_private;
4300 struct intel_crtc_config *pipe_config = &crtc->config;
4301
Daniel Vetter328d8e82013-05-08 10:36:31 +02004302 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004303 return;
4304
Daniel Vetterc0b03412013-05-28 12:05:54 +02004305 /*
4306 * The panel fitter should only be adjusted whilst the pipe is disabled,
4307 * according to register description and PRM.
4308 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004309 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4310 assert_pipe_disabled(dev_priv, crtc->pipe);
4311
Jesse Barnesb074cec2013-04-25 12:55:02 -07004312 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4313 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004314
4315 /* Border color in case we don't scale up to the full screen. Black by
4316 * default, change to something else for debugging. */
4317 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004318}
4319
Dave Airlied05410f2014-06-05 13:22:59 +10004320static enum intel_display_power_domain port_to_power_domain(enum port port)
4321{
4322 switch (port) {
4323 case PORT_A:
4324 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4325 case PORT_B:
4326 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4327 case PORT_C:
4328 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4329 case PORT_D:
4330 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4331 default:
4332 WARN_ON_ONCE(1);
4333 return POWER_DOMAIN_PORT_OTHER;
4334 }
4335}
4336
Imre Deak77d22dc2014-03-05 16:20:52 +02004337#define for_each_power_domain(domain, mask) \
4338 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4339 if ((1 << (domain)) & (mask))
4340
Imre Deak319be8a2014-03-04 19:22:57 +02004341enum intel_display_power_domain
4342intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004343{
Imre Deak319be8a2014-03-04 19:22:57 +02004344 struct drm_device *dev = intel_encoder->base.dev;
4345 struct intel_digital_port *intel_dig_port;
4346
4347 switch (intel_encoder->type) {
4348 case INTEL_OUTPUT_UNKNOWN:
4349 /* Only DDI platforms should ever use this output type */
4350 WARN_ON_ONCE(!HAS_DDI(dev));
4351 case INTEL_OUTPUT_DISPLAYPORT:
4352 case INTEL_OUTPUT_HDMI:
4353 case INTEL_OUTPUT_EDP:
4354 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10004355 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10004356 case INTEL_OUTPUT_DP_MST:
4357 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4358 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02004359 case INTEL_OUTPUT_ANALOG:
4360 return POWER_DOMAIN_PORT_CRT;
4361 case INTEL_OUTPUT_DSI:
4362 return POWER_DOMAIN_PORT_DSI;
4363 default:
4364 return POWER_DOMAIN_PORT_OTHER;
4365 }
4366}
4367
4368static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4369{
4370 struct drm_device *dev = crtc->dev;
4371 struct intel_encoder *intel_encoder;
4372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4373 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02004374 unsigned long mask;
4375 enum transcoder transcoder;
4376
4377 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4378
4379 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4380 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Daniel Vetterfabf6e52014-05-29 14:10:22 +02004381 if (intel_crtc->config.pch_pfit.enabled ||
4382 intel_crtc->config.pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02004383 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4384
Imre Deak319be8a2014-03-04 19:22:57 +02004385 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4386 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4387
Imre Deak77d22dc2014-03-05 16:20:52 +02004388 return mask;
4389}
4390
4391void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4392 bool enable)
4393{
4394 if (dev_priv->power_domains.init_power_on == enable)
4395 return;
4396
4397 if (enable)
4398 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4399 else
4400 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4401
4402 dev_priv->power_domains.init_power_on = enable;
4403}
4404
4405static void modeset_update_crtc_power_domains(struct drm_device *dev)
4406{
4407 struct drm_i915_private *dev_priv = dev->dev_private;
4408 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4409 struct intel_crtc *crtc;
4410
4411 /*
4412 * First get all needed power domains, then put all unneeded, to avoid
4413 * any unnecessary toggling of the power wells.
4414 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004415 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004416 enum intel_display_power_domain domain;
4417
4418 if (!crtc->base.enabled)
4419 continue;
4420
Imre Deak319be8a2014-03-04 19:22:57 +02004421 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004422
4423 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4424 intel_display_power_get(dev_priv, domain);
4425 }
4426
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004427 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004428 enum intel_display_power_domain domain;
4429
4430 for_each_power_domain(domain, crtc->enabled_power_domains)
4431 intel_display_power_put(dev_priv, domain);
4432
4433 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4434 }
4435
4436 intel_display_set_init_power(dev_priv, false);
4437}
4438
Ville Syrjälädfcab172014-06-13 13:37:47 +03004439/* returns HPLL frequency in kHz */
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004440static int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004441{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004442 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004443
Jesse Barnes586f49d2013-11-04 16:06:59 -08004444 /* Obtain SKU information */
4445 mutex_lock(&dev_priv->dpio_lock);
4446 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4447 CCK_FUSE_HPLL_FREQ_MASK;
4448 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004449
Ville Syrjälädfcab172014-06-13 13:37:47 +03004450 return vco_freq[hpll_freq] * 1000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004451}
4452
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004453static void vlv_update_cdclk(struct drm_device *dev)
4454{
4455 struct drm_i915_private *dev_priv = dev->dev_private;
4456
4457 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4458 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4459 dev_priv->vlv_cdclk_freq);
4460
4461 /*
4462 * Program the gmbus_freq based on the cdclk frequency.
4463 * BSpec erroneously claims we should aim for 4MHz, but
4464 * in fact 1MHz is the correct frequency.
4465 */
4466 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4467}
4468
Jesse Barnes30a970c2013-11-04 13:48:12 -08004469/* Adjust CDclk dividers to allow high res or save power if possible */
4470static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4471{
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 u32 val, cmd;
4474
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03004475 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02004476
Ville Syrjälädfcab172014-06-13 13:37:47 +03004477 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08004478 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03004479 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004480 cmd = 1;
4481 else
4482 cmd = 0;
4483
4484 mutex_lock(&dev_priv->rps.hw_lock);
4485 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4486 val &= ~DSPFREQGUAR_MASK;
4487 val |= (cmd << DSPFREQGUAR_SHIFT);
4488 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4489 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4490 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4491 50)) {
4492 DRM_ERROR("timed out waiting for CDclk change\n");
4493 }
4494 mutex_unlock(&dev_priv->rps.hw_lock);
4495
Ville Syrjälädfcab172014-06-13 13:37:47 +03004496 if (cdclk == 400000) {
Jesse Barnes30a970c2013-11-04 13:48:12 -08004497 u32 divider, vco;
4498
4499 vco = valleyview_get_vco(dev_priv);
Ville Syrjälädfcab172014-06-13 13:37:47 +03004500 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004501
4502 mutex_lock(&dev_priv->dpio_lock);
4503 /* adjust cdclk divider */
4504 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Ville Syrjälä9cf33db2014-06-13 13:37:48 +03004505 val &= ~DISPLAY_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004506 val |= divider;
4507 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03004508
4509 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4510 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4511 50))
4512 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08004513 mutex_unlock(&dev_priv->dpio_lock);
4514 }
4515
4516 mutex_lock(&dev_priv->dpio_lock);
4517 /* adjust self-refresh exit latency value */
4518 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4519 val &= ~0x7f;
4520
4521 /*
4522 * For high bandwidth configs, we set a higher latency in the bunit
4523 * so that the core display fetch happens in time to avoid underruns.
4524 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03004525 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004526 val |= 4500 / 250; /* 4.5 usec */
4527 else
4528 val |= 3000 / 250; /* 3.0 usec */
4529 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4530 mutex_unlock(&dev_priv->dpio_lock);
4531
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004532 vlv_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004533}
4534
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004535static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4536{
4537 struct drm_i915_private *dev_priv = dev->dev_private;
4538 u32 val, cmd;
4539
4540 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4541
4542 switch (cdclk) {
4543 case 400000:
4544 cmd = 3;
4545 break;
4546 case 333333:
4547 case 320000:
4548 cmd = 2;
4549 break;
4550 case 266667:
4551 cmd = 1;
4552 break;
4553 case 200000:
4554 cmd = 0;
4555 break;
4556 default:
4557 WARN_ON(1);
4558 return;
4559 }
4560
4561 mutex_lock(&dev_priv->rps.hw_lock);
4562 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4563 val &= ~DSPFREQGUAR_MASK_CHV;
4564 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4565 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4566 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4567 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4568 50)) {
4569 DRM_ERROR("timed out waiting for CDclk change\n");
4570 }
4571 mutex_unlock(&dev_priv->rps.hw_lock);
4572
4573 vlv_update_cdclk(dev);
4574}
4575
Jesse Barnes30a970c2013-11-04 13:48:12 -08004576static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4577 int max_pixclk)
4578{
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004579 int vco = valleyview_get_vco(dev_priv);
4580 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4581
Ville Syrjäläd49a3402014-06-28 02:03:58 +03004582 /* FIXME: Punit isn't quite ready yet */
4583 if (IS_CHERRYVIEW(dev_priv->dev))
4584 return 400000;
4585
Jesse Barnes30a970c2013-11-04 13:48:12 -08004586 /*
4587 * Really only a few cases to deal with, as only 4 CDclks are supported:
4588 * 200MHz
4589 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004590 * 320/333MHz (depends on HPLL freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004591 * 400MHz
4592 * So we check to see whether we're above 90% of the lower bin and
4593 * adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004594 *
4595 * We seem to get an unstable or solid color picture at 200MHz.
4596 * Not sure what's wrong. For now use 200MHz only when all pipes
4597 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08004598 */
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004599 if (max_pixclk > freq_320*9/10)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004600 return 400000;
4601 else if (max_pixclk > 266667*9/10)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004602 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004603 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004604 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004605 else
4606 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004607}
4608
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004609/* compute the max pixel clock for new configuration */
4610static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004611{
4612 struct drm_device *dev = dev_priv->dev;
4613 struct intel_crtc *intel_crtc;
4614 int max_pixclk = 0;
4615
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004616 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004617 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004618 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004619 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004620 }
4621
4622 return max_pixclk;
4623}
4624
4625static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004626 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004627{
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004630 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004631
Imre Deakd60c4472014-03-27 17:45:10 +02004632 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4633 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004634 return;
4635
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004636 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004637 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004638 if (intel_crtc->base.enabled)
4639 *prepare_pipes |= (1 << intel_crtc->pipe);
4640}
4641
4642static void valleyview_modeset_global_resources(struct drm_device *dev)
4643{
4644 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004645 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004646 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4647
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004648 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4649 if (IS_CHERRYVIEW(dev))
4650 cherryview_set_cdclk(dev, req_cdclk);
4651 else
4652 valleyview_set_cdclk(dev, req_cdclk);
4653 }
4654
Imre Deak77961eb2014-03-05 16:20:56 +02004655 modeset_update_crtc_power_domains(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004656}
4657
Jesse Barnes89b667f2013-04-18 14:51:36 -07004658static void valleyview_crtc_enable(struct drm_crtc *crtc)
4659{
4660 struct drm_device *dev = crtc->dev;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4662 struct intel_encoder *encoder;
4663 int pipe = intel_crtc->pipe;
Jani Nikula23538ef2013-08-27 15:12:22 +03004664 bool is_dsi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004665
4666 WARN_ON(!crtc->enabled);
4667
4668 if (intel_crtc->active)
4669 return;
4670
Shobhit Kumar8525a232014-06-25 12:20:39 +05304671 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4672
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004673 if (!is_dsi) {
4674 if (IS_CHERRYVIEW(dev))
4675 chv_prepare_pll(intel_crtc);
4676 else
4677 vlv_prepare_pll(intel_crtc);
4678 }
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02004679
Daniel Vetter5b18e572014-04-24 23:55:06 +02004680 if (intel_crtc->config.has_dp_encoder)
4681 intel_dp_set_m_n(intel_crtc);
4682
4683 intel_set_pipe_timings(intel_crtc);
4684
Daniel Vetter5b18e572014-04-24 23:55:06 +02004685 i9xx_set_pipeconf(intel_crtc);
4686
Jesse Barnes89b667f2013-04-18 14:51:36 -07004687 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004688
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004689 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4690
Jesse Barnes89b667f2013-04-18 14:51:36 -07004691 for_each_encoder_on_crtc(dev, crtc, encoder)
4692 if (encoder->pre_pll_enable)
4693 encoder->pre_pll_enable(encoder);
4694
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004695 if (!is_dsi) {
4696 if (IS_CHERRYVIEW(dev))
4697 chv_enable_pll(intel_crtc);
4698 else
4699 vlv_enable_pll(intel_crtc);
4700 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004701
4702 for_each_encoder_on_crtc(dev, crtc, encoder)
4703 if (encoder->pre_enable)
4704 encoder->pre_enable(encoder);
4705
Jesse Barnes2dd24552013-04-25 12:55:01 -07004706 i9xx_pfit_enable(intel_crtc);
4707
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004708 intel_crtc_load_lut(crtc);
4709
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004710 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004711 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004712
Jani Nikula50049452013-07-30 12:20:32 +03004713 for_each_encoder_on_crtc(dev, crtc, encoder)
4714 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004715
4716 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004717
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004718 /* Underruns don't raise interrupts, so check manually. */
4719 i9xx_check_fifo_underruns(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004720}
4721
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004722static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4723{
4724 struct drm_device *dev = crtc->base.dev;
4725 struct drm_i915_private *dev_priv = dev->dev_private;
4726
4727 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4728 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4729}
4730
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004731static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004732{
4733 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08004734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004735 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004736 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004737
Daniel Vetter08a48462012-07-02 11:43:47 +02004738 WARN_ON(!crtc->enabled);
4739
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004740 if (intel_crtc->active)
4741 return;
4742
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004743 i9xx_set_pll_dividers(intel_crtc);
4744
Daniel Vetter5b18e572014-04-24 23:55:06 +02004745 if (intel_crtc->config.has_dp_encoder)
4746 intel_dp_set_m_n(intel_crtc);
4747
4748 intel_set_pipe_timings(intel_crtc);
4749
Daniel Vetter5b18e572014-04-24 23:55:06 +02004750 i9xx_set_pipeconf(intel_crtc);
4751
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004752 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004753
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004754 if (!IS_GEN2(dev))
4755 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4756
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004757 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004758 if (encoder->pre_enable)
4759 encoder->pre_enable(encoder);
4760
Daniel Vetterf6736a12013-06-05 13:34:30 +02004761 i9xx_enable_pll(intel_crtc);
4762
Jesse Barnes2dd24552013-04-25 12:55:01 -07004763 i9xx_pfit_enable(intel_crtc);
4764
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004765 intel_crtc_load_lut(crtc);
4766
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004767 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004768 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004769
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004770 for_each_encoder_on_crtc(dev, crtc, encoder)
4771 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004772
4773 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004774
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004775 /*
4776 * Gen2 reports pipe underruns whenever all planes are disabled.
4777 * So don't enable underrun reporting before at least some planes
4778 * are enabled.
4779 * FIXME: Need to fix the logic to work when we turn off all planes
4780 * but leave the pipe running.
4781 */
4782 if (IS_GEN2(dev))
4783 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4784
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004785 /* Underruns don't raise interrupts, so check manually. */
4786 i9xx_check_fifo_underruns(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004787}
4788
Daniel Vetter87476d62013-04-11 16:29:06 +02004789static void i9xx_pfit_disable(struct intel_crtc *crtc)
4790{
4791 struct drm_device *dev = crtc->base.dev;
4792 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004793
4794 if (!crtc->config.gmch_pfit.control)
4795 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004796
4797 assert_pipe_disabled(dev_priv, crtc->pipe);
4798
Daniel Vetter328d8e82013-05-08 10:36:31 +02004799 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4800 I915_READ(PFIT_CONTROL));
4801 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004802}
4803
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004804static void i9xx_crtc_disable(struct drm_crtc *crtc)
4805{
4806 struct drm_device *dev = crtc->dev;
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004809 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004810 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004811
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004812 if (!intel_crtc->active)
4813 return;
4814
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004815 /*
4816 * Gen2 reports pipe underruns whenever all planes are disabled.
4817 * So diasble underrun reporting before all the planes get disabled.
4818 * FIXME: Need to fix the logic to work when we turn off all planes
4819 * but leave the pipe running.
4820 */
4821 if (IS_GEN2(dev))
4822 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4823
Imre Deak564ed192014-06-13 14:54:21 +03004824 /*
4825 * Vblank time updates from the shadow to live plane control register
4826 * are blocked if the memory self-refresh mode is active at that
4827 * moment. So to make sure the plane gets truly disabled, disable
4828 * first the self-refresh mode. The self-refresh enable bit in turn
4829 * will be checked/applied by the HW only at the next frame start
4830 * event which is after the vblank start event, so we need to have a
4831 * wait-for-vblank between disabling the plane and the pipe.
4832 */
4833 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004834 intel_crtc_disable_planes(crtc);
4835
Daniel Vetterea9d7582012-07-10 10:42:52 +02004836 for_each_encoder_on_crtc(dev, crtc, encoder)
4837 encoder->disable(encoder);
4838
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004839 /*
4840 * On gen2 planes are double buffered but the pipe isn't, so we must
4841 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03004842 * We also need to wait on all gmch platforms because of the
4843 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004844 */
Imre Deak564ed192014-06-13 14:54:21 +03004845 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03004846
Jesse Barnesb24e7172011-01-04 15:09:30 -08004847 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004848
Daniel Vetter87476d62013-04-11 16:29:06 +02004849 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004850
Jesse Barnes89b667f2013-04-18 14:51:36 -07004851 for_each_encoder_on_crtc(dev, crtc, encoder)
4852 if (encoder->post_disable)
4853 encoder->post_disable(encoder);
4854
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03004855 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4856 if (IS_CHERRYVIEW(dev))
4857 chv_disable_pll(dev_priv, pipe);
4858 else if (IS_VALLEYVIEW(dev))
4859 vlv_disable_pll(dev_priv, pipe);
4860 else
4861 i9xx_disable_pll(dev_priv, pipe);
4862 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004863
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004864 if (!IS_GEN2(dev))
4865 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4866
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004867 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004868 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004869
Daniel Vetterefa96242014-04-24 23:55:02 +02004870 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004871 intel_update_fbc(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02004872 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004873}
4874
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004875static void i9xx_crtc_off(struct drm_crtc *crtc)
4876{
4877}
4878
Daniel Vetter976f8a22012-07-08 22:34:21 +02004879static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4880 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004881{
4882 struct drm_device *dev = crtc->dev;
4883 struct drm_i915_master_private *master_priv;
4884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4885 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004886
4887 if (!dev->primary->master)
4888 return;
4889
4890 master_priv = dev->primary->master->driver_priv;
4891 if (!master_priv->sarea_priv)
4892 return;
4893
Jesse Barnes79e53942008-11-07 14:24:08 -08004894 switch (pipe) {
4895 case 0:
4896 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4897 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4898 break;
4899 case 1:
4900 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4901 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4902 break;
4903 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004904 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004905 break;
4906 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004907}
4908
Borun Fub04c5bd2014-07-12 10:02:27 +05304909/* Master function to enable/disable CRTC and corresponding power wells */
4910void intel_crtc_control(struct drm_crtc *crtc, bool enable)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004911{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004912 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004913 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004915 enum intel_display_power_domain domain;
4916 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004917
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004918 if (enable) {
4919 if (!intel_crtc->active) {
Daniel Vettere1e9fb82014-06-25 22:02:04 +03004920 domains = get_crtc_power_domains(crtc);
4921 for_each_power_domain(domain, domains)
4922 intel_display_power_get(dev_priv, domain);
4923 intel_crtc->enabled_power_domains = domains;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004924
4925 dev_priv->display.crtc_enable(crtc);
4926 }
4927 } else {
4928 if (intel_crtc->active) {
4929 dev_priv->display.crtc_disable(crtc);
4930
Daniel Vettere1e9fb82014-06-25 22:02:04 +03004931 domains = intel_crtc->enabled_power_domains;
4932 for_each_power_domain(domain, domains)
4933 intel_display_power_put(dev_priv, domain);
4934 intel_crtc->enabled_power_domains = 0;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02004935 }
4936 }
Borun Fub04c5bd2014-07-12 10:02:27 +05304937}
4938
4939/**
4940 * Sets the power management mode of the pipe and plane.
4941 */
4942void intel_crtc_update_dpms(struct drm_crtc *crtc)
4943{
4944 struct drm_device *dev = crtc->dev;
4945 struct intel_encoder *intel_encoder;
4946 bool enable = false;
4947
4948 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4949 enable |= intel_encoder->connectors_active;
4950
4951 intel_crtc_control(crtc, enable);
Daniel Vetter976f8a22012-07-08 22:34:21 +02004952
4953 intel_crtc_update_sarea(crtc, enable);
4954}
4955
Daniel Vetter976f8a22012-07-08 22:34:21 +02004956static void intel_crtc_disable(struct drm_crtc *crtc)
4957{
4958 struct drm_device *dev = crtc->dev;
4959 struct drm_connector *connector;
4960 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper2ff8fde2014-07-08 07:50:07 -07004961 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
Daniel Vettera071fa02014-06-18 23:28:09 +02004962 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004963
4964 /* crtc should still be enabled when we disable it. */
4965 WARN_ON(!crtc->enabled);
4966
4967 dev_priv->display.crtc_disable(crtc);
4968 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004969 dev_priv->display.off(crtc);
4970
Matt Roperf4510a22014-04-01 15:22:40 -07004971 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01004972 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02004973 intel_unpin_fb_obj(old_obj);
4974 i915_gem_track_fb(old_obj, NULL,
4975 INTEL_FRONTBUFFER_PRIMARY(pipe));
Chris Wilsoncdd59982010-09-08 16:30:16 +01004976 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07004977 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004978 }
4979
4980 /* Update computed state. */
4981 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4982 if (!connector->encoder || !connector->encoder->crtc)
4983 continue;
4984
4985 if (connector->encoder->crtc != crtc)
4986 continue;
4987
4988 connector->dpms = DRM_MODE_DPMS_OFF;
4989 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004990 }
4991}
4992
Chris Wilsonea5b2132010-08-04 13:50:23 +01004993void intel_encoder_destroy(struct drm_encoder *encoder)
4994{
Chris Wilson4ef69c72010-09-09 15:14:28 +01004995 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01004996
Chris Wilsonea5b2132010-08-04 13:50:23 +01004997 drm_encoder_cleanup(encoder);
4998 kfree(intel_encoder);
4999}
5000
Damien Lespiau92373292013-08-08 22:28:57 +01005001/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005002 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5003 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01005004static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005005{
5006 if (mode == DRM_MODE_DPMS_ON) {
5007 encoder->connectors_active = true;
5008
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005009 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005010 } else {
5011 encoder->connectors_active = false;
5012
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005013 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005014 }
5015}
5016
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005017/* Cross check the actual hw state with our own modeset state tracking (and it's
5018 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02005019static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005020{
5021 if (connector->get_hw_state(connector)) {
5022 struct intel_encoder *encoder = connector->encoder;
5023 struct drm_crtc *crtc;
5024 bool encoder_enabled;
5025 enum pipe pipe;
5026
5027 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5028 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03005029 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005030
Dave Airlie0e32b392014-05-02 14:02:48 +10005031 /* there is no real hw state for MST connectors */
5032 if (connector->mst_port)
5033 return;
5034
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005035 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5036 "wrong connector dpms state\n");
5037 WARN(connector->base.encoder != &encoder->base,
5038 "active connector not linked to encoder\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005039
Dave Airlie36cd7442014-05-02 13:44:18 +10005040 if (encoder) {
5041 WARN(!encoder->connectors_active,
5042 "encoder->connectors_active not set\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005043
Dave Airlie36cd7442014-05-02 13:44:18 +10005044 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5045 WARN(!encoder_enabled, "encoder not enabled\n");
5046 if (WARN_ON(!encoder->base.crtc))
5047 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005048
Dave Airlie36cd7442014-05-02 13:44:18 +10005049 crtc = encoder->base.crtc;
5050
5051 WARN(!crtc->enabled, "crtc not enabled\n");
5052 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5053 WARN(pipe != to_intel_crtc(crtc)->pipe,
5054 "encoder active on the wrong pipe\n");
5055 }
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005056 }
5057}
5058
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005059/* Even simpler default implementation, if there's really no special case to
5060 * consider. */
5061void intel_connector_dpms(struct drm_connector *connector, int mode)
5062{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005063 /* All the simple cases only support two dpms states. */
5064 if (mode != DRM_MODE_DPMS_ON)
5065 mode = DRM_MODE_DPMS_OFF;
5066
5067 if (mode == connector->dpms)
5068 return;
5069
5070 connector->dpms = mode;
5071
5072 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01005073 if (connector->encoder)
5074 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005075
Daniel Vetterb9805142012-08-31 17:37:33 +02005076 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005077}
5078
Daniel Vetterf0947c32012-07-02 13:10:34 +02005079/* Simple connector->get_hw_state implementation for encoders that support only
5080 * one connector and no cloning and hence the encoder state determines the state
5081 * of the connector. */
5082bool intel_connector_get_hw_state(struct intel_connector *connector)
5083{
Daniel Vetter24929352012-07-02 20:28:59 +02005084 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02005085 struct intel_encoder *encoder = connector->encoder;
5086
5087 return encoder->get_hw_state(encoder, &pipe);
5088}
5089
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005090static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5091 struct intel_crtc_config *pipe_config)
5092{
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_crtc *pipe_B_crtc =
5095 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5096
5097 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5098 pipe_name(pipe), pipe_config->fdi_lanes);
5099 if (pipe_config->fdi_lanes > 4) {
5100 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5101 pipe_name(pipe), pipe_config->fdi_lanes);
5102 return false;
5103 }
5104
Paulo Zanonibafb6552013-11-02 21:07:44 -07005105 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005106 if (pipe_config->fdi_lanes > 2) {
5107 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5108 pipe_config->fdi_lanes);
5109 return false;
5110 } else {
5111 return true;
5112 }
5113 }
5114
5115 if (INTEL_INFO(dev)->num_pipes == 2)
5116 return true;
5117
5118 /* Ivybridge 3 pipe is really complicated */
5119 switch (pipe) {
5120 case PIPE_A:
5121 return true;
5122 case PIPE_B:
5123 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5124 pipe_config->fdi_lanes > 2) {
5125 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5126 pipe_name(pipe), pipe_config->fdi_lanes);
5127 return false;
5128 }
5129 return true;
5130 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005131 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005132 pipe_B_crtc->config.fdi_lanes <= 2) {
5133 if (pipe_config->fdi_lanes > 2) {
5134 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5135 pipe_name(pipe), pipe_config->fdi_lanes);
5136 return false;
5137 }
5138 } else {
5139 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5140 return false;
5141 }
5142 return true;
5143 default:
5144 BUG();
5145 }
5146}
5147
Daniel Vettere29c22c2013-02-21 00:00:16 +01005148#define RETRY 1
5149static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5150 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005151{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005152 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005153 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005154 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005155 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005156
Daniel Vettere29c22c2013-02-21 00:00:16 +01005157retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005158 /* FDI is a binary signal running at ~2.7GHz, encoding
5159 * each output octet as 10 bits. The actual frequency
5160 * is stored as a divider into a 100MHz clock, and the
5161 * mode pixel clock is stored in units of 1KHz.
5162 * Hence the bw of each lane in terms of the mode signal
5163 * is:
5164 */
5165 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5166
Damien Lespiau241bfc32013-09-25 16:45:37 +01005167 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005168
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005169 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005170 pipe_config->pipe_bpp);
5171
5172 pipe_config->fdi_lanes = lane;
5173
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005174 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005175 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005176
Daniel Vettere29c22c2013-02-21 00:00:16 +01005177 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5178 intel_crtc->pipe, pipe_config);
5179 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5180 pipe_config->pipe_bpp -= 2*3;
5181 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5182 pipe_config->pipe_bpp);
5183 needs_recompute = true;
5184 pipe_config->bw_constrained = true;
5185
5186 goto retry;
5187 }
5188
5189 if (needs_recompute)
5190 return RETRY;
5191
5192 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005193}
5194
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005195static void hsw_compute_ips_config(struct intel_crtc *crtc,
5196 struct intel_crtc_config *pipe_config)
5197{
Jani Nikulad330a952014-01-21 11:24:25 +02005198 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005199 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005200 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005201}
5202
Daniel Vettera43f6e02013-06-07 23:10:32 +02005203static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005204 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005205{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005206 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005207 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005208
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005209 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005210 if (INTEL_INFO(dev)->gen < 4) {
5211 struct drm_i915_private *dev_priv = dev->dev_private;
5212 int clock_limit =
5213 dev_priv->display.get_display_clock_speed(dev);
5214
5215 /*
5216 * Enable pixel doubling when the dot clock
5217 * is > 90% of the (display) core speed.
5218 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005219 * GDG double wide on either pipe,
5220 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005221 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005222 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005223 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005224 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005225 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005226 }
5227
Damien Lespiau241bfc32013-09-25 16:45:37 +01005228 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005229 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005230 }
Chris Wilson89749352010-09-12 18:25:19 +01005231
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005232 /*
5233 * Pipe horizontal size must be even in:
5234 * - DVO ganged mode
5235 * - LVDS dual channel mode
5236 * - Double wide pipe
5237 */
5238 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5239 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5240 pipe_config->pipe_src_w &= ~1;
5241
Damien Lespiau8693a822013-05-03 18:48:11 +01005242 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5243 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005244 */
5245 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5246 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005247 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005248
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005249 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005250 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005251 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005252 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5253 * for lvds. */
5254 pipe_config->pipe_bpp = 8*3;
5255 }
5256
Damien Lespiauf5adf942013-06-24 18:29:34 +01005257 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005258 hsw_compute_ips_config(crtc, pipe_config);
5259
Daniel Vetter12030432014-06-25 22:02:00 +03005260 /*
5261 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5262 * old clock survives for now.
5263 */
5264 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005265 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005266
Daniel Vetter877d48d2013-04-19 11:24:43 +02005267 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005268 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005269
Daniel Vettere29c22c2013-02-21 00:00:16 +01005270 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005271}
5272
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005273static int valleyview_get_display_clock_speed(struct drm_device *dev)
5274{
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005275 struct drm_i915_private *dev_priv = dev->dev_private;
5276 int vco = valleyview_get_vco(dev_priv);
5277 u32 val;
5278 int divider;
5279
Ville Syrjäläd49a3402014-06-28 02:03:58 +03005280 /* FIXME: Punit isn't quite ready yet */
5281 if (IS_CHERRYVIEW(dev))
5282 return 400000;
5283
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005284 mutex_lock(&dev_priv->dpio_lock);
5285 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5286 mutex_unlock(&dev_priv->dpio_lock);
5287
5288 divider = val & DISPLAY_FREQUENCY_VALUES;
5289
Ville Syrjälä7d007f42014-06-13 13:37:53 +03005290 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5291 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5292 "cdclk change in progress\n");
5293
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005294 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005295}
5296
Jesse Barnese70236a2009-09-21 10:42:27 -07005297static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005298{
Jesse Barnese70236a2009-09-21 10:42:27 -07005299 return 400000;
5300}
Jesse Barnes79e53942008-11-07 14:24:08 -08005301
Jesse Barnese70236a2009-09-21 10:42:27 -07005302static int i915_get_display_clock_speed(struct drm_device *dev)
5303{
5304 return 333000;
5305}
Jesse Barnes79e53942008-11-07 14:24:08 -08005306
Jesse Barnese70236a2009-09-21 10:42:27 -07005307static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5308{
5309 return 200000;
5310}
Jesse Barnes79e53942008-11-07 14:24:08 -08005311
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005312static int pnv_get_display_clock_speed(struct drm_device *dev)
5313{
5314 u16 gcfgc = 0;
5315
5316 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5317
5318 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5319 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5320 return 267000;
5321 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5322 return 333000;
5323 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5324 return 444000;
5325 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5326 return 200000;
5327 default:
5328 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5329 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5330 return 133000;
5331 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5332 return 167000;
5333 }
5334}
5335
Jesse Barnese70236a2009-09-21 10:42:27 -07005336static int i915gm_get_display_clock_speed(struct drm_device *dev)
5337{
5338 u16 gcfgc = 0;
5339
5340 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5341
5342 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005343 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005344 else {
5345 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5346 case GC_DISPLAY_CLOCK_333_MHZ:
5347 return 333000;
5348 default:
5349 case GC_DISPLAY_CLOCK_190_200_MHZ:
5350 return 190000;
5351 }
5352 }
5353}
Jesse Barnes79e53942008-11-07 14:24:08 -08005354
Jesse Barnese70236a2009-09-21 10:42:27 -07005355static int i865_get_display_clock_speed(struct drm_device *dev)
5356{
5357 return 266000;
5358}
5359
5360static int i855_get_display_clock_speed(struct drm_device *dev)
5361{
5362 u16 hpllcc = 0;
5363 /* Assume that the hardware is in the high speed state. This
5364 * should be the default.
5365 */
5366 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5367 case GC_CLOCK_133_200:
5368 case GC_CLOCK_100_200:
5369 return 200000;
5370 case GC_CLOCK_166_250:
5371 return 250000;
5372 case GC_CLOCK_100_133:
5373 return 133000;
5374 }
5375
5376 /* Shouldn't happen */
5377 return 0;
5378}
5379
5380static int i830_get_display_clock_speed(struct drm_device *dev)
5381{
5382 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005383}
5384
Zhenyu Wang2c072452009-06-05 15:38:42 +08005385static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005386intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005387{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005388 while (*num > DATA_LINK_M_N_MASK ||
5389 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005390 *num >>= 1;
5391 *den >>= 1;
5392 }
5393}
5394
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005395static void compute_m_n(unsigned int m, unsigned int n,
5396 uint32_t *ret_m, uint32_t *ret_n)
5397{
5398 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5399 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5400 intel_reduce_m_n_ratio(ret_m, ret_n);
5401}
5402
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005403void
5404intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5405 int pixel_clock, int link_clock,
5406 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005407{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005408 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005409
5410 compute_m_n(bits_per_pixel * pixel_clock,
5411 link_clock * nlanes * 8,
5412 &m_n->gmch_m, &m_n->gmch_n);
5413
5414 compute_m_n(pixel_clock, link_clock,
5415 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005416}
5417
Chris Wilsona7615032011-01-12 17:04:08 +00005418static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5419{
Jani Nikulad330a952014-01-21 11:24:25 +02005420 if (i915.panel_use_ssc >= 0)
5421 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005422 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005423 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005424}
5425
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005426static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5427{
5428 struct drm_device *dev = crtc->dev;
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5430 int refclk;
5431
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005432 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005433 refclk = 100000;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005434 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005435 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005436 refclk = dev_priv->vbt.lvds_ssc_freq;
5437 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005438 } else if (!IS_GEN2(dev)) {
5439 refclk = 96000;
5440 } else {
5441 refclk = 48000;
5442 }
5443
5444 return refclk;
5445}
5446
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005447static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005448{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005449 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005450}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005451
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005452static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5453{
5454 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005455}
5456
Daniel Vetterf47709a2013-03-28 10:42:02 +01005457static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005458 intel_clock_t *reduced_clock)
5459{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005460 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005461 u32 fp, fp2 = 0;
5462
5463 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005464 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005465 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005466 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005467 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005468 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005469 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005470 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005471 }
5472
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005473 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005474
Daniel Vetterf47709a2013-03-28 10:42:02 +01005475 crtc->lowfreq_avail = false;
5476 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005477 reduced_clock && i915.powersave) {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005478 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005479 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005480 } else {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005481 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005482 }
5483}
5484
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005485static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5486 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005487{
5488 u32 reg_val;
5489
5490 /*
5491 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5492 * and set it to a reasonable value instead.
5493 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005494 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005495 reg_val &= 0xffffff00;
5496 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005497 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005498
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005499 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005500 reg_val &= 0x8cffffff;
5501 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005502 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005503
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005504 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005505 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005506 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005507
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005508 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005509 reg_val &= 0x00ffffff;
5510 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005511 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005512}
5513
Daniel Vetterb5518422013-05-03 11:49:48 +02005514static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5515 struct intel_link_m_n *m_n)
5516{
5517 struct drm_device *dev = crtc->base.dev;
5518 struct drm_i915_private *dev_priv = dev->dev_private;
5519 int pipe = crtc->pipe;
5520
Daniel Vettere3b95f12013-05-03 11:49:49 +02005521 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5522 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5523 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5524 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005525}
5526
5527static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07005528 struct intel_link_m_n *m_n,
5529 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02005530{
5531 struct drm_device *dev = crtc->base.dev;
5532 struct drm_i915_private *dev_priv = dev->dev_private;
5533 int pipe = crtc->pipe;
5534 enum transcoder transcoder = crtc->config.cpu_transcoder;
5535
5536 if (INTEL_INFO(dev)->gen >= 5) {
5537 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5538 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5539 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5540 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07005541 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5542 * for gen < 8) and if DRRS is supported (to make sure the
5543 * registers are not unnecessarily accessed).
5544 */
5545 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5546 crtc->config.has_drrs) {
5547 I915_WRITE(PIPE_DATA_M2(transcoder),
5548 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5549 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5550 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5551 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5552 }
Daniel Vetterb5518422013-05-03 11:49:48 +02005553 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005554 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5555 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5556 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5557 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005558 }
5559}
5560
Vandana Kannanf769cd22014-08-05 07:51:22 -07005561void intel_dp_set_m_n(struct intel_crtc *crtc)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005562{
5563 if (crtc->config.has_pch_encoder)
5564 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5565 else
Vandana Kannanf769cd22014-08-05 07:51:22 -07005566 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5567 &crtc->config.dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005568}
5569
Daniel Vetterf47709a2013-03-28 10:42:02 +01005570static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005571{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005572 u32 dpll, dpll_md;
5573
5574 /*
5575 * Enable DPIO clock input. We should never disable the reference
5576 * clock for pipe B, since VGA hotplug / manual detection depends
5577 * on it.
5578 */
5579 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5580 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5581 /* We should never disable this, set it here for state tracking */
5582 if (crtc->pipe == PIPE_B)
5583 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5584 dpll |= DPLL_VCO_ENABLE;
5585 crtc->config.dpll_hw_state.dpll = dpll;
5586
5587 dpll_md = (crtc->config.pixel_multiplier - 1)
5588 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5589 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5590}
5591
5592static void vlv_prepare_pll(struct intel_crtc *crtc)
5593{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005594 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005595 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005596 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005597 u32 mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005598 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005599 u32 coreclk, reg_val;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005600
Daniel Vetter09153002012-12-12 14:06:44 +01005601 mutex_lock(&dev_priv->dpio_lock);
5602
Daniel Vetterf47709a2013-03-28 10:42:02 +01005603 bestn = crtc->config.dpll.n;
5604 bestm1 = crtc->config.dpll.m1;
5605 bestm2 = crtc->config.dpll.m2;
5606 bestp1 = crtc->config.dpll.p1;
5607 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005608
Jesse Barnes89b667f2013-04-18 14:51:36 -07005609 /* See eDP HDMI DPIO driver vbios notes doc */
5610
5611 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005612 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005613 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005614
5615 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005616 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005617
5618 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005619 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005620 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005621 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005622
5623 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005624 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005625
5626 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005627 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5628 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5629 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005630 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005631
5632 /*
5633 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5634 * but we don't support that).
5635 * Note: don't use the DAC post divider as it seems unstable.
5636 */
5637 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005638 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005639
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005640 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005641 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005642
Jesse Barnes89b667f2013-04-18 14:51:36 -07005643 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02005644 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03005645 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07005646 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005647 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03005648 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005649 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005650 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005651 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005652
Jesse Barnes89b667f2013-04-18 14:51:36 -07005653 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5654 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5655 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005656 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005657 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005658 0x0df40000);
5659 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005660 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005661 0x0df70000);
5662 } else { /* HDMI or VGA */
5663 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005664 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005665 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005666 0x0df70000);
5667 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005668 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005669 0x0df40000);
5670 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005671
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005672 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005673 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5674 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5675 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5676 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005677 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005678
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005679 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005680 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005681}
5682
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005683static void chv_update_pll(struct intel_crtc *crtc)
5684{
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005685 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5686 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5687 DPLL_VCO_ENABLE;
5688 if (crtc->pipe != PIPE_A)
5689 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5690
5691 crtc->config.dpll_hw_state.dpll_md =
5692 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5693}
5694
5695static void chv_prepare_pll(struct intel_crtc *crtc)
5696{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005697 struct drm_device *dev = crtc->base.dev;
5698 struct drm_i915_private *dev_priv = dev->dev_private;
5699 int pipe = crtc->pipe;
5700 int dpll_reg = DPLL(crtc->pipe);
5701 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005702 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005703 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5704 int refclk;
5705
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005706 bestn = crtc->config.dpll.n;
5707 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5708 bestm1 = crtc->config.dpll.m1;
5709 bestm2 = crtc->config.dpll.m2 >> 22;
5710 bestp1 = crtc->config.dpll.p1;
5711 bestp2 = crtc->config.dpll.p2;
5712
5713 /*
5714 * Enable Refclk and SSC
5715 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005716 I915_WRITE(dpll_reg,
5717 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5718
5719 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005720
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005721 /* p1 and p2 divider */
5722 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5723 5 << DPIO_CHV_S1_DIV_SHIFT |
5724 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5725 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5726 1 << DPIO_CHV_K_DIV_SHIFT);
5727
5728 /* Feedback post-divider - m2 */
5729 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5730
5731 /* Feedback refclk divider - n and m1 */
5732 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5733 DPIO_CHV_M1_DIV_BY_2 |
5734 1 << DPIO_CHV_N_DIV_SHIFT);
5735
5736 /* M2 fraction division */
5737 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5738
5739 /* M2 fraction division enable */
5740 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5741 DPIO_CHV_FRAC_DIV_EN |
5742 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5743
5744 /* Loop filter */
5745 refclk = i9xx_get_refclk(&crtc->base, 0);
5746 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5747 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5748 if (refclk == 100000)
5749 intcoeff = 11;
5750 else if (refclk == 38400)
5751 intcoeff = 10;
5752 else
5753 intcoeff = 9;
5754 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5755 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5756
5757 /* AFC Recal */
5758 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5759 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5760 DPIO_AFC_RECAL);
5761
5762 mutex_unlock(&dev_priv->dpio_lock);
5763}
5764
Daniel Vetterf47709a2013-03-28 10:42:02 +01005765static void i9xx_update_pll(struct intel_crtc *crtc,
5766 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005767 int num_connectors)
5768{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005769 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005770 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005771 u32 dpll;
5772 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005773 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005774
Daniel Vetterf47709a2013-03-28 10:42:02 +01005775 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305776
Daniel Vetterf47709a2013-03-28 10:42:02 +01005777 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5778 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005779
5780 dpll = DPLL_VGA_MODE_DIS;
5781
Daniel Vetterf47709a2013-03-28 10:42:02 +01005782 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005783 dpll |= DPLLB_MODE_LVDS;
5784 else
5785 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005786
Daniel Vetteref1b4602013-06-01 17:17:04 +02005787 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02005788 dpll |= (crtc->config.pixel_multiplier - 1)
5789 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005790 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02005791
5792 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02005793 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005794
Daniel Vetterf47709a2013-03-28 10:42:02 +01005795 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02005796 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005797
5798 /* compute bitmask from p1 value */
5799 if (IS_PINEVIEW(dev))
5800 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5801 else {
5802 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5803 if (IS_G4X(dev) && reduced_clock)
5804 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5805 }
5806 switch (clock->p2) {
5807 case 5:
5808 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5809 break;
5810 case 7:
5811 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5812 break;
5813 case 10:
5814 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5815 break;
5816 case 14:
5817 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5818 break;
5819 }
5820 if (INTEL_INFO(dev)->gen >= 4)
5821 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5822
Daniel Vetter09ede542013-04-30 14:01:45 +02005823 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005824 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005825 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005826 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5827 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5828 else
5829 dpll |= PLL_REF_INPUT_DREFCLK;
5830
5831 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005832 crtc->config.dpll_hw_state.dpll = dpll;
5833
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005834 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005835 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5836 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005837 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005838 }
5839}
5840
Daniel Vetterf47709a2013-03-28 10:42:02 +01005841static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005842 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005843 int num_connectors)
5844{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005845 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005846 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005847 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005848 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005849
Daniel Vetterf47709a2013-03-28 10:42:02 +01005850 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305851
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005852 dpll = DPLL_VGA_MODE_DIS;
5853
Daniel Vetterf47709a2013-03-28 10:42:02 +01005854 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005855 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5856 } else {
5857 if (clock->p1 == 2)
5858 dpll |= PLL_P1_DIVIDE_BY_TWO;
5859 else
5860 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5861 if (clock->p2 == 4)
5862 dpll |= PLL_P2_DIVIDE_BY_4;
5863 }
5864
Daniel Vetter4a33e482013-07-06 12:52:05 +02005865 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5866 dpll |= DPLL_DVO_2X_MODE;
5867
Daniel Vetterf47709a2013-03-28 10:42:02 +01005868 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005869 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5870 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5871 else
5872 dpll |= PLL_REF_INPUT_DREFCLK;
5873
5874 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005875 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005876}
5877
Daniel Vetter8a654f32013-06-01 17:16:22 +02005878static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005879{
5880 struct drm_device *dev = intel_crtc->base.dev;
5881 struct drm_i915_private *dev_priv = dev->dev_private;
5882 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005883 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005884 struct drm_display_mode *adjusted_mode =
5885 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005886 uint32_t crtc_vtotal, crtc_vblank_end;
5887 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005888
5889 /* We need to be careful not to changed the adjusted mode, for otherwise
5890 * the hw state checker will get angry at the mismatch. */
5891 crtc_vtotal = adjusted_mode->crtc_vtotal;
5892 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005893
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005894 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005895 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005896 crtc_vtotal -= 1;
5897 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02005898
5899 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5900 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5901 else
5902 vsyncshift = adjusted_mode->crtc_hsync_start -
5903 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02005904 if (vsyncshift < 0)
5905 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005906 }
5907
5908 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005909 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005910
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005911 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005912 (adjusted_mode->crtc_hdisplay - 1) |
5913 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005914 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005915 (adjusted_mode->crtc_hblank_start - 1) |
5916 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005917 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005918 (adjusted_mode->crtc_hsync_start - 1) |
5919 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5920
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005921 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005922 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005923 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005924 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005925 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005926 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005927 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005928 (adjusted_mode->crtc_vsync_start - 1) |
5929 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5930
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005931 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5932 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5933 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5934 * bits. */
5935 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5936 (pipe == PIPE_B || pipe == PIPE_C))
5937 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5938
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005939 /* pipesrc controls the size that is scaled from, which should
5940 * always be the user's requested size.
5941 */
5942 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005943 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5944 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005945}
5946
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005947static void intel_get_pipe_timings(struct intel_crtc *crtc,
5948 struct intel_crtc_config *pipe_config)
5949{
5950 struct drm_device *dev = crtc->base.dev;
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5953 uint32_t tmp;
5954
5955 tmp = I915_READ(HTOTAL(cpu_transcoder));
5956 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5957 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5958 tmp = I915_READ(HBLANK(cpu_transcoder));
5959 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5960 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5961 tmp = I915_READ(HSYNC(cpu_transcoder));
5962 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5963 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5964
5965 tmp = I915_READ(VTOTAL(cpu_transcoder));
5966 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5967 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5968 tmp = I915_READ(VBLANK(cpu_transcoder));
5969 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5970 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5971 tmp = I915_READ(VSYNC(cpu_transcoder));
5972 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5973 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5974
5975 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5976 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5977 pipe_config->adjusted_mode.crtc_vtotal += 1;
5978 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5979 }
5980
5981 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005982 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5983 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5984
5985 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5986 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005987}
5988
Daniel Vetterf6a83282014-02-11 15:28:57 -08005989void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5990 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03005991{
Daniel Vetterf6a83282014-02-11 15:28:57 -08005992 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5993 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5994 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5995 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03005996
Daniel Vetterf6a83282014-02-11 15:28:57 -08005997 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5998 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5999 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6000 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006001
Daniel Vetterf6a83282014-02-11 15:28:57 -08006002 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006003
Daniel Vetterf6a83282014-02-11 15:28:57 -08006004 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6005 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006006}
6007
Daniel Vetter84b046f2013-02-19 18:48:54 +01006008static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6009{
6010 struct drm_device *dev = intel_crtc->base.dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 uint32_t pipeconf;
6013
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006014 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006015
Daniel Vetter67c72a12013-09-24 11:46:14 +02006016 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
6017 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
6018 pipeconf |= PIPECONF_ENABLE;
6019
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006020 if (intel_crtc->config.double_wide)
6021 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006022
Daniel Vetterff9ce462013-04-24 14:57:17 +02006023 /* only g4x and later have fancy bpc/dither controls */
6024 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02006025 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6026 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6027 pipeconf |= PIPECONF_DITHER_EN |
6028 PIPECONF_DITHER_TYPE_SP;
6029
6030 switch (intel_crtc->config.pipe_bpp) {
6031 case 18:
6032 pipeconf |= PIPECONF_6BPC;
6033 break;
6034 case 24:
6035 pipeconf |= PIPECONF_8BPC;
6036 break;
6037 case 30:
6038 pipeconf |= PIPECONF_10BPC;
6039 break;
6040 default:
6041 /* Case prevented by intel_choose_pipe_bpp_dither. */
6042 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01006043 }
6044 }
6045
6046 if (HAS_PIPE_CXSR(dev)) {
6047 if (intel_crtc->lowfreq_avail) {
6048 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6049 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6050 } else {
6051 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01006052 }
6053 }
6054
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006055 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6056 if (INTEL_INFO(dev)->gen < 4 ||
6057 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6058 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6059 else
6060 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6061 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01006062 pipeconf |= PIPECONF_PROGRESSIVE;
6063
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006064 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6065 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03006066
Daniel Vetter84b046f2013-02-19 18:48:54 +01006067 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6068 POSTING_READ(PIPECONF(intel_crtc->pipe));
6069}
6070
Eric Anholtf564048e2011-03-30 13:01:02 -07006071static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07006072 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006073 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006074{
6075 struct drm_device *dev = crtc->dev;
6076 struct drm_i915_private *dev_priv = dev->dev_private;
6077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Eric Anholtc751ce42010-03-25 11:48:48 -07006078 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07006079 intel_clock_t clock, reduced_clock;
Daniel Vettera16af7212013-04-30 14:01:44 +02006080 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006081 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01006082 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08006083 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08006084
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02006085 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01006086 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006087 case INTEL_OUTPUT_LVDS:
6088 is_lvds = true;
6089 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006090 case INTEL_OUTPUT_DSI:
6091 is_dsi = true;
6092 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006093 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006094
Eric Anholtc751ce42010-03-25 11:48:48 -07006095 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08006096 }
6097
Jani Nikulaf2335332013-09-13 11:03:09 +03006098 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02006099 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006100
Jani Nikulaf2335332013-09-13 11:03:09 +03006101 if (!intel_crtc->config.clock_set) {
6102 refclk = i9xx_get_refclk(crtc, num_connectors);
6103
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006104 /*
6105 * Returns a set of divisors for the desired target clock with
6106 * the given refclk, or FALSE. The returned values represent
6107 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6108 * 2) / p1 / p2.
6109 */
6110 limit = intel_limit(crtc, refclk);
6111 ok = dev_priv->display.find_dpll(limit, crtc,
6112 intel_crtc->config.port_clock,
6113 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03006114 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006115 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6116 return -EINVAL;
6117 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006118
Jani Nikulaf2335332013-09-13 11:03:09 +03006119 if (is_lvds && dev_priv->lvds_downclock_avail) {
6120 /*
6121 * Ensure we match the reduced clock's P to the target
6122 * clock. If the clocks don't match, we can't switch
6123 * the display clock by using the FP0/FP1. In such case
6124 * we will disable the LVDS downclock feature.
6125 */
6126 has_reduced_clock =
6127 dev_priv->display.find_dpll(limit, crtc,
6128 dev_priv->lvds_downclock,
6129 refclk, &clock,
6130 &reduced_clock);
6131 }
6132 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01006133 intel_crtc->config.dpll.n = clock.n;
6134 intel_crtc->config.dpll.m1 = clock.m1;
6135 intel_crtc->config.dpll.m2 = clock.m2;
6136 intel_crtc->config.dpll.p1 = clock.p1;
6137 intel_crtc->config.dpll.p2 = clock.p2;
6138 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006139
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006140 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02006141 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306142 has_reduced_clock ? &reduced_clock : NULL,
6143 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006144 } else if (IS_CHERRYVIEW(dev)) {
6145 chv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006146 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03006147 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006148 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01006149 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006150 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006151 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006152 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006153
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006154 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006155}
6156
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006157static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6158 struct intel_crtc_config *pipe_config)
6159{
6160 struct drm_device *dev = crtc->base.dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 uint32_t tmp;
6163
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006164 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6165 return;
6166
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006167 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006168 if (!(tmp & PFIT_ENABLE))
6169 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006170
Daniel Vetter06922822013-07-11 13:35:40 +02006171 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006172 if (INTEL_INFO(dev)->gen < 4) {
6173 if (crtc->pipe != PIPE_B)
6174 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006175 } else {
6176 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6177 return;
6178 }
6179
Daniel Vetter06922822013-07-11 13:35:40 +02006180 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006181 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6182 if (INTEL_INFO(dev)->gen < 5)
6183 pipe_config->gmch_pfit.lvds_border_bits =
6184 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6185}
6186
Jesse Barnesacbec812013-09-20 11:29:32 -07006187static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6188 struct intel_crtc_config *pipe_config)
6189{
6190 struct drm_device *dev = crtc->base.dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6192 int pipe = pipe_config->cpu_transcoder;
6193 intel_clock_t clock;
6194 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006195 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006196
Shobhit Kumarf573de52014-07-30 20:32:37 +05306197 /* In case of MIPI DPLL will not even be used */
6198 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6199 return;
6200
Jesse Barnesacbec812013-09-20 11:29:32 -07006201 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006202 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006203 mutex_unlock(&dev_priv->dpio_lock);
6204
6205 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6206 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6207 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6208 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6209 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6210
Ville Syrjäläf6466282013-10-14 14:50:31 +03006211 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006212
Ville Syrjäläf6466282013-10-14 14:50:31 +03006213 /* clock.dot is the fast clock */
6214 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006215}
6216
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006217static void i9xx_get_plane_config(struct intel_crtc *crtc,
6218 struct intel_plane_config *plane_config)
6219{
6220 struct drm_device *dev = crtc->base.dev;
6221 struct drm_i915_private *dev_priv = dev->dev_private;
6222 u32 val, base, offset;
6223 int pipe = crtc->pipe, plane = crtc->plane;
6224 int fourcc, pixel_format;
6225 int aligned_height;
6226
Dave Airlie66e514c2014-04-03 07:51:54 +10006227 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6228 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006229 DRM_DEBUG_KMS("failed to alloc fb\n");
6230 return;
6231 }
6232
6233 val = I915_READ(DSPCNTR(plane));
6234
6235 if (INTEL_INFO(dev)->gen >= 4)
6236 if (val & DISPPLANE_TILED)
6237 plane_config->tiled = true;
6238
6239 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6240 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006241 crtc->base.primary->fb->pixel_format = fourcc;
6242 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006243 drm_format_plane_cpp(fourcc, 0) * 8;
6244
6245 if (INTEL_INFO(dev)->gen >= 4) {
6246 if (plane_config->tiled)
6247 offset = I915_READ(DSPTILEOFF(plane));
6248 else
6249 offset = I915_READ(DSPLINOFF(plane));
6250 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6251 } else {
6252 base = I915_READ(DSPADDR(plane));
6253 }
6254 plane_config->base = base;
6255
6256 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006257 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6258 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006259
6260 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01006261 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006262
Dave Airlie66e514c2014-04-03 07:51:54 +10006263 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006264 plane_config->tiled);
6265
Fabian Frederick1267a262014-07-01 20:39:41 +02006266 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6267 aligned_height);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006268
6269 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006270 pipe, plane, crtc->base.primary->fb->width,
6271 crtc->base.primary->fb->height,
6272 crtc->base.primary->fb->bits_per_pixel, base,
6273 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006274 plane_config->size);
6275
6276}
6277
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006278static void chv_crtc_clock_get(struct intel_crtc *crtc,
6279 struct intel_crtc_config *pipe_config)
6280{
6281 struct drm_device *dev = crtc->base.dev;
6282 struct drm_i915_private *dev_priv = dev->dev_private;
6283 int pipe = pipe_config->cpu_transcoder;
6284 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6285 intel_clock_t clock;
6286 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6287 int refclk = 100000;
6288
6289 mutex_lock(&dev_priv->dpio_lock);
6290 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6291 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6292 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6293 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6294 mutex_unlock(&dev_priv->dpio_lock);
6295
6296 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6297 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6298 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6299 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6300 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6301
6302 chv_clock(refclk, &clock);
6303
6304 /* clock.dot is the fast clock */
6305 pipe_config->port_clock = clock.dot / 5;
6306}
6307
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006308static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6309 struct intel_crtc_config *pipe_config)
6310{
6311 struct drm_device *dev = crtc->base.dev;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 uint32_t tmp;
6314
Imre Deakb5482bd2014-03-05 16:20:55 +02006315 if (!intel_display_power_enabled(dev_priv,
6316 POWER_DOMAIN_PIPE(crtc->pipe)))
6317 return false;
6318
Daniel Vettere143a212013-07-04 12:01:15 +02006319 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006320 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006321
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006322 tmp = I915_READ(PIPECONF(crtc->pipe));
6323 if (!(tmp & PIPECONF_ENABLE))
6324 return false;
6325
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006326 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6327 switch (tmp & PIPECONF_BPC_MASK) {
6328 case PIPECONF_6BPC:
6329 pipe_config->pipe_bpp = 18;
6330 break;
6331 case PIPECONF_8BPC:
6332 pipe_config->pipe_bpp = 24;
6333 break;
6334 case PIPECONF_10BPC:
6335 pipe_config->pipe_bpp = 30;
6336 break;
6337 default:
6338 break;
6339 }
6340 }
6341
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006342 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6343 pipe_config->limited_color_range = true;
6344
Ville Syrjälä282740f2013-09-04 18:30:03 +03006345 if (INTEL_INFO(dev)->gen < 4)
6346 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6347
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006348 intel_get_pipe_timings(crtc, pipe_config);
6349
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006350 i9xx_get_pfit_config(crtc, pipe_config);
6351
Daniel Vetter6c49f242013-06-06 12:45:25 +02006352 if (INTEL_INFO(dev)->gen >= 4) {
6353 tmp = I915_READ(DPLL_MD(crtc->pipe));
6354 pipe_config->pixel_multiplier =
6355 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6356 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006357 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006358 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6359 tmp = I915_READ(DPLL(crtc->pipe));
6360 pipe_config->pixel_multiplier =
6361 ((tmp & SDVO_MULTIPLIER_MASK)
6362 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6363 } else {
6364 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6365 * port and will be fixed up in the encoder->get_config
6366 * function. */
6367 pipe_config->pixel_multiplier = 1;
6368 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006369 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6370 if (!IS_VALLEYVIEW(dev)) {
6371 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6372 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006373 } else {
6374 /* Mask out read-only status bits. */
6375 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6376 DPLL_PORTC_READY_MASK |
6377 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006378 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006379
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006380 if (IS_CHERRYVIEW(dev))
6381 chv_crtc_clock_get(crtc, pipe_config);
6382 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006383 vlv_crtc_clock_get(crtc, pipe_config);
6384 else
6385 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006386
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006387 return true;
6388}
6389
Paulo Zanonidde86e22012-12-01 12:04:25 -02006390static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006391{
6392 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006393 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006394 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006395 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006396 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006397 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006398 bool has_ck505 = false;
6399 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006400
6401 /* We need to take the global config into account */
Damien Lespiaub2784e12014-08-05 11:29:37 +01006402 for_each_intel_encoder(dev, encoder) {
Keith Packard199e5d72011-09-22 12:01:57 -07006403 switch (encoder->type) {
6404 case INTEL_OUTPUT_LVDS:
6405 has_panel = true;
6406 has_lvds = true;
6407 break;
6408 case INTEL_OUTPUT_EDP:
6409 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006410 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006411 has_cpu_edp = true;
6412 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006413 }
6414 }
6415
Keith Packard99eb6a02011-09-26 14:29:12 -07006416 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006417 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006418 can_ssc = has_ck505;
6419 } else {
6420 has_ck505 = false;
6421 can_ssc = true;
6422 }
6423
Imre Deak2de69052013-05-08 13:14:04 +03006424 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6425 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006426
6427 /* Ironlake: try to setup display ref clock before DPLL
6428 * enabling. This is only under driver's control after
6429 * PCH B stepping, previous chipset stepping should be
6430 * ignoring this setting.
6431 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006432 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006433
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006434 /* As we must carefully and slowly disable/enable each source in turn,
6435 * compute the final state we want first and check if we need to
6436 * make any changes at all.
6437 */
6438 final = val;
6439 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006440 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006441 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006442 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006443 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6444
6445 final &= ~DREF_SSC_SOURCE_MASK;
6446 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6447 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006448
Keith Packard199e5d72011-09-22 12:01:57 -07006449 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006450 final |= DREF_SSC_SOURCE_ENABLE;
6451
6452 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6453 final |= DREF_SSC1_ENABLE;
6454
6455 if (has_cpu_edp) {
6456 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6457 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6458 else
6459 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6460 } else
6461 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6462 } else {
6463 final |= DREF_SSC_SOURCE_DISABLE;
6464 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6465 }
6466
6467 if (final == val)
6468 return;
6469
6470 /* Always enable nonspread source */
6471 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6472
6473 if (has_ck505)
6474 val |= DREF_NONSPREAD_CK505_ENABLE;
6475 else
6476 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6477
6478 if (has_panel) {
6479 val &= ~DREF_SSC_SOURCE_MASK;
6480 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006481
Keith Packard199e5d72011-09-22 12:01:57 -07006482 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006483 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006484 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006485 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006486 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006487 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006488
6489 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006490 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006491 POSTING_READ(PCH_DREF_CONTROL);
6492 udelay(200);
6493
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006494 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006495
6496 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006497 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006498 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006499 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006500 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006501 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006502 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006503 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006504 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006505
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006506 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006507 POSTING_READ(PCH_DREF_CONTROL);
6508 udelay(200);
6509 } else {
6510 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6511
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006512 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006513
6514 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006515 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006516
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006517 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006518 POSTING_READ(PCH_DREF_CONTROL);
6519 udelay(200);
6520
6521 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006522 val &= ~DREF_SSC_SOURCE_MASK;
6523 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006524
6525 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006526 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006527
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006528 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006529 POSTING_READ(PCH_DREF_CONTROL);
6530 udelay(200);
6531 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006532
6533 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006534}
6535
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006536static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006537{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006538 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006539
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006540 tmp = I915_READ(SOUTH_CHICKEN2);
6541 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6542 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006543
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006544 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6545 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6546 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006547
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006548 tmp = I915_READ(SOUTH_CHICKEN2);
6549 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6550 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006551
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006552 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6553 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6554 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006555}
6556
6557/* WaMPhyProgramming:hsw */
6558static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6559{
6560 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006561
6562 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6563 tmp &= ~(0xFF << 24);
6564 tmp |= (0x12 << 24);
6565 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6566
Paulo Zanonidde86e22012-12-01 12:04:25 -02006567 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6568 tmp |= (1 << 11);
6569 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6570
6571 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6572 tmp |= (1 << 11);
6573 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6574
Paulo Zanonidde86e22012-12-01 12:04:25 -02006575 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6576 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6577 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6578
6579 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6580 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6581 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6582
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006583 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6584 tmp &= ~(7 << 13);
6585 tmp |= (5 << 13);
6586 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006587
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006588 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6589 tmp &= ~(7 << 13);
6590 tmp |= (5 << 13);
6591 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006592
6593 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6594 tmp &= ~0xFF;
6595 tmp |= 0x1C;
6596 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6597
6598 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6599 tmp &= ~0xFF;
6600 tmp |= 0x1C;
6601 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6602
6603 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6604 tmp &= ~(0xFF << 16);
6605 tmp |= (0x1C << 16);
6606 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6607
6608 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6609 tmp &= ~(0xFF << 16);
6610 tmp |= (0x1C << 16);
6611 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6612
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006613 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6614 tmp |= (1 << 27);
6615 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006616
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006617 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6618 tmp |= (1 << 27);
6619 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006620
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006621 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6622 tmp &= ~(0xF << 28);
6623 tmp |= (4 << 28);
6624 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006625
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006626 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6627 tmp &= ~(0xF << 28);
6628 tmp |= (4 << 28);
6629 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006630}
6631
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006632/* Implements 3 different sequences from BSpec chapter "Display iCLK
6633 * Programming" based on the parameters passed:
6634 * - Sequence to enable CLKOUT_DP
6635 * - Sequence to enable CLKOUT_DP without spread
6636 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6637 */
6638static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6639 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006640{
6641 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006642 uint32_t reg, tmp;
6643
6644 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6645 with_spread = true;
6646 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6647 with_fdi, "LP PCH doesn't have FDI\n"))
6648 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006649
6650 mutex_lock(&dev_priv->dpio_lock);
6651
6652 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6653 tmp &= ~SBI_SSCCTL_DISABLE;
6654 tmp |= SBI_SSCCTL_PATHALT;
6655 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6656
6657 udelay(24);
6658
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006659 if (with_spread) {
6660 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6661 tmp &= ~SBI_SSCCTL_PATHALT;
6662 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006663
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006664 if (with_fdi) {
6665 lpt_reset_fdi_mphy(dev_priv);
6666 lpt_program_fdi_mphy(dev_priv);
6667 }
6668 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02006669
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006670 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6671 SBI_GEN0 : SBI_DBUFF0;
6672 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6673 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6674 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01006675
6676 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006677}
6678
Paulo Zanoni47701c32013-07-23 11:19:25 -03006679/* Sequence to disable CLKOUT_DP */
6680static void lpt_disable_clkout_dp(struct drm_device *dev)
6681{
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 uint32_t reg, tmp;
6684
6685 mutex_lock(&dev_priv->dpio_lock);
6686
6687 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6688 SBI_GEN0 : SBI_DBUFF0;
6689 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6690 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6691 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6692
6693 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6694 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6695 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6696 tmp |= SBI_SSCCTL_PATHALT;
6697 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6698 udelay(32);
6699 }
6700 tmp |= SBI_SSCCTL_DISABLE;
6701 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6702 }
6703
6704 mutex_unlock(&dev_priv->dpio_lock);
6705}
6706
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006707static void lpt_init_pch_refclk(struct drm_device *dev)
6708{
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006709 struct intel_encoder *encoder;
6710 bool has_vga = false;
6711
Damien Lespiaub2784e12014-08-05 11:29:37 +01006712 for_each_intel_encoder(dev, encoder) {
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006713 switch (encoder->type) {
6714 case INTEL_OUTPUT_ANALOG:
6715 has_vga = true;
6716 break;
6717 }
6718 }
6719
Paulo Zanoni47701c32013-07-23 11:19:25 -03006720 if (has_vga)
6721 lpt_enable_clkout_dp(dev, true, true);
6722 else
6723 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03006724}
6725
Paulo Zanonidde86e22012-12-01 12:04:25 -02006726/*
6727 * Initialize reference clocks when the driver loads
6728 */
6729void intel_init_pch_refclk(struct drm_device *dev)
6730{
6731 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6732 ironlake_init_pch_refclk(dev);
6733 else if (HAS_PCH_LPT(dev))
6734 lpt_init_pch_refclk(dev);
6735}
6736
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006737static int ironlake_get_refclk(struct drm_crtc *crtc)
6738{
6739 struct drm_device *dev = crtc->dev;
6740 struct drm_i915_private *dev_priv = dev->dev_private;
6741 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006742 int num_connectors = 0;
6743 bool is_lvds = false;
6744
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02006745 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006746 switch (encoder->type) {
6747 case INTEL_OUTPUT_LVDS:
6748 is_lvds = true;
6749 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006750 }
6751 num_connectors++;
6752 }
6753
6754 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006755 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006756 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006757 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07006758 }
6759
6760 return 120000;
6761}
6762
Daniel Vetter6ff93602013-04-19 11:24:36 +02006763static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03006764{
6765 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6767 int pipe = intel_crtc->pipe;
6768 uint32_t val;
6769
Daniel Vetter78114072013-06-13 00:54:57 +02006770 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03006771
Daniel Vetter965e0c42013-03-27 00:44:57 +01006772 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03006773 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006774 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006775 break;
6776 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006777 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006778 break;
6779 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006780 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006781 break;
6782 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01006783 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03006784 break;
6785 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03006786 /* Case prevented by intel_choose_pipe_bpp_dither. */
6787 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03006788 }
6789
Daniel Vetterd8b32242013-04-25 17:54:44 +02006790 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03006791 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6792
Daniel Vetter6ff93602013-04-19 11:24:36 +02006793 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03006794 val |= PIPECONF_INTERLACED_ILK;
6795 else
6796 val |= PIPECONF_PROGRESSIVE;
6797
Daniel Vetter50f3b012013-03-27 00:44:56 +01006798 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006799 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02006800
Paulo Zanonic8203562012-09-12 10:06:29 -03006801 I915_WRITE(PIPECONF(pipe), val);
6802 POSTING_READ(PIPECONF(pipe));
6803}
6804
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006805/*
6806 * Set up the pipe CSC unit.
6807 *
6808 * Currently only full range RGB to limited range RGB conversion
6809 * is supported, but eventually this should handle various
6810 * RGB<->YCbCr scenarios as well.
6811 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01006812static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006813{
6814 struct drm_device *dev = crtc->dev;
6815 struct drm_i915_private *dev_priv = dev->dev_private;
6816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6817 int pipe = intel_crtc->pipe;
6818 uint16_t coeff = 0x7800; /* 1.0 */
6819
6820 /*
6821 * TODO: Check what kind of values actually come out of the pipe
6822 * with these coeff/postoff values and adjust to get the best
6823 * accuracy. Perhaps we even need to take the bpc value into
6824 * consideration.
6825 */
6826
Daniel Vetter50f3b012013-03-27 00:44:56 +01006827 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006828 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6829
6830 /*
6831 * GY/GU and RY/RU should be the other way around according
6832 * to BSpec, but reality doesn't agree. Just set them up in
6833 * a way that results in the correct picture.
6834 */
6835 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6836 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6837
6838 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6839 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6840
6841 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6842 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6843
6844 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6845 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6846 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6847
6848 if (INTEL_INFO(dev)->gen > 6) {
6849 uint16_t postoff = 0;
6850
Daniel Vetter50f3b012013-03-27 00:44:56 +01006851 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02006852 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006853
6854 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6855 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6856 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6857
6858 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6859 } else {
6860 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6861
Daniel Vetter50f3b012013-03-27 00:44:56 +01006862 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006863 mode |= CSC_BLACK_SCREEN_OFFSET;
6864
6865 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6866 }
6867}
6868
Daniel Vetter6ff93602013-04-19 11:24:36 +02006869static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006870{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006871 struct drm_device *dev = crtc->dev;
6872 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006874 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006875 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006876 uint32_t val;
6877
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006878 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006879
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006880 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006881 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6882
Daniel Vetter6ff93602013-04-19 11:24:36 +02006883 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006884 val |= PIPECONF_INTERLACED_ILK;
6885 else
6886 val |= PIPECONF_PROGRESSIVE;
6887
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006888 I915_WRITE(PIPECONF(cpu_transcoder), val);
6889 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006890
6891 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6892 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006893
6894 if (IS_BROADWELL(dev)) {
6895 val = 0;
6896
6897 switch (intel_crtc->config.pipe_bpp) {
6898 case 18:
6899 val |= PIPEMISC_DITHER_6_BPC;
6900 break;
6901 case 24:
6902 val |= PIPEMISC_DITHER_8_BPC;
6903 break;
6904 case 30:
6905 val |= PIPEMISC_DITHER_10_BPC;
6906 break;
6907 case 36:
6908 val |= PIPEMISC_DITHER_12_BPC;
6909 break;
6910 default:
6911 /* Case prevented by pipe_config_set_bpp. */
6912 BUG();
6913 }
6914
6915 if (intel_crtc->config.dither)
6916 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6917
6918 I915_WRITE(PIPEMISC(pipe), val);
6919 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006920}
6921
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006922static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006923 intel_clock_t *clock,
6924 bool *has_reduced_clock,
6925 intel_clock_t *reduced_clock)
6926{
6927 struct drm_device *dev = crtc->dev;
6928 struct drm_i915_private *dev_priv = dev->dev_private;
6929 struct intel_encoder *intel_encoder;
6930 int refclk;
6931 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02006932 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006933
6934 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6935 switch (intel_encoder->type) {
6936 case INTEL_OUTPUT_LVDS:
6937 is_lvds = true;
6938 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006939 }
6940 }
6941
6942 refclk = ironlake_get_refclk(crtc);
6943
6944 /*
6945 * Returns a set of divisors for the desired target clock with the given
6946 * refclk, or FALSE. The returned values represent the clock equation:
6947 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6948 */
6949 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006950 ret = dev_priv->display.find_dpll(limit, crtc,
6951 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006952 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006953 if (!ret)
6954 return false;
6955
6956 if (is_lvds && dev_priv->lvds_downclock_avail) {
6957 /*
6958 * Ensure we match the reduced clock's P to the target clock.
6959 * If the clocks don't match, we can't switch the display clock
6960 * by using the FP0/FP1. In such case we will disable the LVDS
6961 * downclock feature.
6962 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006963 *has_reduced_clock =
6964 dev_priv->display.find_dpll(limit, crtc,
6965 dev_priv->lvds_downclock,
6966 refclk, clock,
6967 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006968 }
6969
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006970 return true;
6971}
6972
Paulo Zanonid4b19312012-11-29 11:29:32 -02006973int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6974{
6975 /*
6976 * Account for spread spectrum to avoid
6977 * oversubscribing the link. Max center spread
6978 * is 2.5%; use 5% for safety's sake.
6979 */
6980 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02006981 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02006982}
6983
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006984static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02006985{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006986 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006987}
6988
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006989static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006990 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006991 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006992{
6993 struct drm_crtc *crtc = &intel_crtc->base;
6994 struct drm_device *dev = crtc->dev;
6995 struct drm_i915_private *dev_priv = dev->dev_private;
6996 struct intel_encoder *intel_encoder;
6997 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006998 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02006999 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007000
7001 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7002 switch (intel_encoder->type) {
7003 case INTEL_OUTPUT_LVDS:
7004 is_lvds = true;
7005 break;
7006 case INTEL_OUTPUT_SDVO:
7007 case INTEL_OUTPUT_HDMI:
7008 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007009 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007010 }
7011
7012 num_connectors++;
7013 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007014
Chris Wilsonc1858122010-12-03 21:35:48 +00007015 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07007016 factor = 21;
7017 if (is_lvds) {
7018 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007019 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02007020 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07007021 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02007022 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07007023 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00007024
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007025 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02007026 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00007027
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007028 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7029 *fp2 |= FP_CB_TUNE;
7030
Chris Wilson5eddb702010-09-11 13:48:45 +01007031 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08007032
Eric Anholta07d6782011-03-30 13:01:08 -07007033 if (is_lvds)
7034 dpll |= DPLLB_MODE_LVDS;
7035 else
7036 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007037
Daniel Vetteref1b4602013-06-01 17:17:04 +02007038 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7039 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007040
7041 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007042 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02007043 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007044 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08007045
Eric Anholta07d6782011-03-30 13:01:08 -07007046 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007047 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007048 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007049 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007050
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007051 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07007052 case 5:
7053 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7054 break;
7055 case 7:
7056 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7057 break;
7058 case 10:
7059 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7060 break;
7061 case 14:
7062 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7063 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007064 }
7065
Daniel Vetterb4c09f32013-04-30 14:01:42 +02007066 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05007067 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08007068 else
7069 dpll |= PLL_REF_INPUT_DREFCLK;
7070
Daniel Vetter959e16d2013-06-05 13:34:21 +02007071 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007072}
7073
Jesse Barnes79e53942008-11-07 14:24:08 -08007074static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08007075 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02007076 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08007077{
7078 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007080 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007081 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007082 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03007083 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01007084 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007085 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02007086 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007087
7088 for_each_encoder_on_crtc(dev, crtc, encoder) {
7089 switch (encoder->type) {
7090 case INTEL_OUTPUT_LVDS:
7091 is_lvds = true;
7092 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007093 }
7094
7095 num_connectors++;
7096 }
7097
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007098 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7099 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7100
Daniel Vetterff9a6752013-06-01 17:16:21 +02007101 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007102 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02007103 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007104 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7105 return -EINVAL;
7106 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01007107 /* Compat-code for transition, will disappear. */
7108 if (!intel_crtc->config.clock_set) {
7109 intel_crtc->config.dpll.n = clock.n;
7110 intel_crtc->config.dpll.m1 = clock.m1;
7111 intel_crtc->config.dpll.m2 = clock.m2;
7112 intel_crtc->config.dpll.p1 = clock.p1;
7113 intel_crtc->config.dpll.p2 = clock.p2;
7114 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007115
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007116 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01007117 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007118 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007119 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007120 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007121
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007122 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007123 &fp, &reduced_clock,
7124 has_reduced_clock ? &fp2 : NULL);
7125
Daniel Vetter959e16d2013-06-05 13:34:21 +02007126 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007127 intel_crtc->config.dpll_hw_state.fp0 = fp;
7128 if (has_reduced_clock)
7129 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7130 else
7131 intel_crtc->config.dpll_hw_state.fp1 = fp;
7132
Daniel Vetterb89a1d32013-06-05 13:34:24 +02007133 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007134 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03007135 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Daniel Vetter29407aa2014-04-24 23:55:08 +02007136 pipe_name(intel_crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07007137 return -EINVAL;
7138 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007139 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02007140 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007141
Jani Nikulad330a952014-01-21 11:24:25 +02007142 if (is_lvds && has_reduced_clock && i915.powersave)
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007143 intel_crtc->lowfreq_avail = true;
7144 else
7145 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007146
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007147 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007148}
7149
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007150static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7151 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007152{
7153 struct drm_device *dev = crtc->base.dev;
7154 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007155 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007156
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007157 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7158 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7159 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7160 & ~TU_SIZE_MASK;
7161 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7162 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7163 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7164}
7165
7166static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7167 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007168 struct intel_link_m_n *m_n,
7169 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007170{
7171 struct drm_device *dev = crtc->base.dev;
7172 struct drm_i915_private *dev_priv = dev->dev_private;
7173 enum pipe pipe = crtc->pipe;
7174
7175 if (INTEL_INFO(dev)->gen >= 5) {
7176 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7177 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7178 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7179 & ~TU_SIZE_MASK;
7180 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7181 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7182 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007183 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7184 * gen < 8) and if DRRS is supported (to make sure the
7185 * registers are not unnecessarily read).
7186 */
7187 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7188 crtc->config.has_drrs) {
7189 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7190 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7191 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7192 & ~TU_SIZE_MASK;
7193 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7194 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7195 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7196 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007197 } else {
7198 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7199 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7200 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7201 & ~TU_SIZE_MASK;
7202 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7203 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7204 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7205 }
7206}
7207
7208void intel_dp_get_m_n(struct intel_crtc *crtc,
7209 struct intel_crtc_config *pipe_config)
7210{
7211 if (crtc->config.has_pch_encoder)
7212 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7213 else
7214 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007215 &pipe_config->dp_m_n,
7216 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007217}
7218
Daniel Vetter72419202013-04-04 13:28:53 +02007219static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7220 struct intel_crtc_config *pipe_config)
7221{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007222 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007223 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02007224}
7225
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007226static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7227 struct intel_crtc_config *pipe_config)
7228{
7229 struct drm_device *dev = crtc->base.dev;
7230 struct drm_i915_private *dev_priv = dev->dev_private;
7231 uint32_t tmp;
7232
7233 tmp = I915_READ(PF_CTL(crtc->pipe));
7234
7235 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007236 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007237 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7238 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007239
7240 /* We currently do not free assignements of panel fitters on
7241 * ivb/hsw (since we don't use the higher upscaling modes which
7242 * differentiates them) so just WARN about this case for now. */
7243 if (IS_GEN7(dev)) {
7244 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7245 PF_PIPE_SEL_IVB(crtc->pipe));
7246 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007247 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007248}
7249
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007250static void ironlake_get_plane_config(struct intel_crtc *crtc,
7251 struct intel_plane_config *plane_config)
7252{
7253 struct drm_device *dev = crtc->base.dev;
7254 struct drm_i915_private *dev_priv = dev->dev_private;
7255 u32 val, base, offset;
7256 int pipe = crtc->pipe, plane = crtc->plane;
7257 int fourcc, pixel_format;
7258 int aligned_height;
7259
Dave Airlie66e514c2014-04-03 07:51:54 +10007260 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7261 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007262 DRM_DEBUG_KMS("failed to alloc fb\n");
7263 return;
7264 }
7265
7266 val = I915_READ(DSPCNTR(plane));
7267
7268 if (INTEL_INFO(dev)->gen >= 4)
7269 if (val & DISPPLANE_TILED)
7270 plane_config->tiled = true;
7271
7272 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7273 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007274 crtc->base.primary->fb->pixel_format = fourcc;
7275 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007276 drm_format_plane_cpp(fourcc, 0) * 8;
7277
7278 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7279 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7280 offset = I915_READ(DSPOFFSET(plane));
7281 } else {
7282 if (plane_config->tiled)
7283 offset = I915_READ(DSPTILEOFF(plane));
7284 else
7285 offset = I915_READ(DSPLINOFF(plane));
7286 }
7287 plane_config->base = base;
7288
7289 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007290 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7291 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007292
7293 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01007294 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007295
Dave Airlie66e514c2014-04-03 07:51:54 +10007296 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007297 plane_config->tiled);
7298
Fabian Frederick1267a262014-07-01 20:39:41 +02007299 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7300 aligned_height);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007301
7302 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007303 pipe, plane, crtc->base.primary->fb->width,
7304 crtc->base.primary->fb->height,
7305 crtc->base.primary->fb->bits_per_pixel, base,
7306 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007307 plane_config->size);
7308}
7309
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007310static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7311 struct intel_crtc_config *pipe_config)
7312{
7313 struct drm_device *dev = crtc->base.dev;
7314 struct drm_i915_private *dev_priv = dev->dev_private;
7315 uint32_t tmp;
7316
Paulo Zanoni930e8c92014-07-04 13:38:34 -03007317 if (!intel_display_power_enabled(dev_priv,
7318 POWER_DOMAIN_PIPE(crtc->pipe)))
7319 return false;
7320
Daniel Vettere143a212013-07-04 12:01:15 +02007321 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007322 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007323
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007324 tmp = I915_READ(PIPECONF(crtc->pipe));
7325 if (!(tmp & PIPECONF_ENABLE))
7326 return false;
7327
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007328 switch (tmp & PIPECONF_BPC_MASK) {
7329 case PIPECONF_6BPC:
7330 pipe_config->pipe_bpp = 18;
7331 break;
7332 case PIPECONF_8BPC:
7333 pipe_config->pipe_bpp = 24;
7334 break;
7335 case PIPECONF_10BPC:
7336 pipe_config->pipe_bpp = 30;
7337 break;
7338 case PIPECONF_12BPC:
7339 pipe_config->pipe_bpp = 36;
7340 break;
7341 default:
7342 break;
7343 }
7344
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007345 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7346 pipe_config->limited_color_range = true;
7347
Daniel Vetterab9412b2013-05-03 11:49:46 +02007348 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007349 struct intel_shared_dpll *pll;
7350
Daniel Vetter88adfff2013-03-28 10:42:01 +01007351 pipe_config->has_pch_encoder = true;
7352
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007353 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7354 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7355 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007356
7357 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007358
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007359 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007360 pipe_config->shared_dpll =
7361 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007362 } else {
7363 tmp = I915_READ(PCH_DPLL_SEL);
7364 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7365 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7366 else
7367 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7368 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007369
7370 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7371
7372 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7373 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007374
7375 tmp = pipe_config->dpll_hw_state.dpll;
7376 pipe_config->pixel_multiplier =
7377 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7378 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007379
7380 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007381 } else {
7382 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007383 }
7384
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007385 intel_get_pipe_timings(crtc, pipe_config);
7386
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007387 ironlake_get_pfit_config(crtc, pipe_config);
7388
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007389 return true;
7390}
7391
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007392static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7393{
7394 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007395 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007396
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007397 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007398 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007399 pipe_name(crtc->pipe));
7400
7401 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
Daniel Vetter8cc3e162014-06-25 22:01:46 +03007402 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7403 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7404 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007405 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7406 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7407 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -03007408 if (IS_HASWELL(dev))
7409 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7410 "CPU PWM2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007411 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7412 "PCH PWM1 enabled\n");
7413 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7414 "Utility pin enabled\n");
7415 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7416
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007417 /*
7418 * In theory we can still leave IRQs enabled, as long as only the HPD
7419 * interrupts remain enabled. We used to check for that, but since it's
7420 * gen-specific and since we only disable LCPLL after we fully disable
7421 * the interrupts, the check below should be enough.
7422 */
Jesse Barnes9df7575f2014-06-20 09:29:20 -07007423 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007424}
7425
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007426static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7427{
7428 struct drm_device *dev = dev_priv->dev;
7429
7430 if (IS_HASWELL(dev))
7431 return I915_READ(D_COMP_HSW);
7432 else
7433 return I915_READ(D_COMP_BDW);
7434}
7435
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007436static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7437{
7438 struct drm_device *dev = dev_priv->dev;
7439
7440 if (IS_HASWELL(dev)) {
7441 mutex_lock(&dev_priv->rps.hw_lock);
7442 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7443 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03007444 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007445 mutex_unlock(&dev_priv->rps.hw_lock);
7446 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007447 I915_WRITE(D_COMP_BDW, val);
7448 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007449 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007450}
7451
7452/*
7453 * This function implements pieces of two sequences from BSpec:
7454 * - Sequence for display software to disable LCPLL
7455 * - Sequence for display software to allow package C8+
7456 * The steps implemented here are just the steps that actually touch the LCPLL
7457 * register. Callers should take care of disabling all the display engine
7458 * functions, doing the mode unset, fixing interrupts, etc.
7459 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007460static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7461 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007462{
7463 uint32_t val;
7464
7465 assert_can_disable_lcpll(dev_priv);
7466
7467 val = I915_READ(LCPLL_CTL);
7468
7469 if (switch_to_fclk) {
7470 val |= LCPLL_CD_SOURCE_FCLK;
7471 I915_WRITE(LCPLL_CTL, val);
7472
7473 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7474 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7475 DRM_ERROR("Switching to FCLK failed\n");
7476
7477 val = I915_READ(LCPLL_CTL);
7478 }
7479
7480 val |= LCPLL_PLL_DISABLE;
7481 I915_WRITE(LCPLL_CTL, val);
7482 POSTING_READ(LCPLL_CTL);
7483
7484 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7485 DRM_ERROR("LCPLL still locked\n");
7486
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007487 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007488 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007489 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007490 ndelay(100);
7491
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007492 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7493 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007494 DRM_ERROR("D_COMP RCOMP still in progress\n");
7495
7496 if (allow_power_down) {
7497 val = I915_READ(LCPLL_CTL);
7498 val |= LCPLL_POWER_DOWN_ALLOW;
7499 I915_WRITE(LCPLL_CTL, val);
7500 POSTING_READ(LCPLL_CTL);
7501 }
7502}
7503
7504/*
7505 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7506 * source.
7507 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007508static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007509{
7510 uint32_t val;
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007511 unsigned long irqflags;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007512
7513 val = I915_READ(LCPLL_CTL);
7514
7515 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7516 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7517 return;
7518
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007519 /*
7520 * Make sure we're not on PC8 state before disabling PC8, otherwise
7521 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7522 *
7523 * The other problem is that hsw_restore_lcpll() is called as part of
7524 * the runtime PM resume sequence, so we can't just call
7525 * gen6_gt_force_wake_get() because that function calls
7526 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7527 * while we are on the resume sequence. So to solve this problem we have
7528 * to call special forcewake code that doesn't touch runtime PM and
7529 * doesn't enable the forcewake delayed work.
7530 */
7531 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7532 if (dev_priv->uncore.forcewake_count++ == 0)
7533 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7534 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007535
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007536 if (val & LCPLL_POWER_DOWN_ALLOW) {
7537 val &= ~LCPLL_POWER_DOWN_ALLOW;
7538 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007539 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007540 }
7541
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007542 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007543 val |= D_COMP_COMP_FORCE;
7544 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007545 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007546
7547 val = I915_READ(LCPLL_CTL);
7548 val &= ~LCPLL_PLL_DISABLE;
7549 I915_WRITE(LCPLL_CTL, val);
7550
7551 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7552 DRM_ERROR("LCPLL not locked yet\n");
7553
7554 if (val & LCPLL_CD_SOURCE_FCLK) {
7555 val = I915_READ(LCPLL_CTL);
7556 val &= ~LCPLL_CD_SOURCE_FCLK;
7557 I915_WRITE(LCPLL_CTL, val);
7558
7559 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7560 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7561 DRM_ERROR("Switching back to LCPLL failed\n");
7562 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007563
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007564 /* See the big comment above. */
7565 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7566 if (--dev_priv->uncore.forcewake_count == 0)
7567 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7568 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007569}
7570
Paulo Zanoni765dab62014-03-07 20:08:18 -03007571/*
7572 * Package states C8 and deeper are really deep PC states that can only be
7573 * reached when all the devices on the system allow it, so even if the graphics
7574 * device allows PC8+, it doesn't mean the system will actually get to these
7575 * states. Our driver only allows PC8+ when going into runtime PM.
7576 *
7577 * The requirements for PC8+ are that all the outputs are disabled, the power
7578 * well is disabled and most interrupts are disabled, and these are also
7579 * requirements for runtime PM. When these conditions are met, we manually do
7580 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7581 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7582 * hang the machine.
7583 *
7584 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7585 * the state of some registers, so when we come back from PC8+ we need to
7586 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7587 * need to take care of the registers kept by RC6. Notice that this happens even
7588 * if we don't put the device in PCI D3 state (which is what currently happens
7589 * because of the runtime PM support).
7590 *
7591 * For more, read "Display Sequences for Package C8" on the hardware
7592 * documentation.
7593 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007594void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007595{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007596 struct drm_device *dev = dev_priv->dev;
7597 uint32_t val;
7598
Paulo Zanonic67a4702013-08-19 13:18:09 -03007599 DRM_DEBUG_KMS("Enabling package C8+\n");
7600
Paulo Zanonic67a4702013-08-19 13:18:09 -03007601 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7602 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7603 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7604 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7605 }
7606
7607 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007608 hsw_disable_lcpll(dev_priv, true, true);
7609}
7610
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007611void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007612{
7613 struct drm_device *dev = dev_priv->dev;
7614 uint32_t val;
7615
Paulo Zanonic67a4702013-08-19 13:18:09 -03007616 DRM_DEBUG_KMS("Disabling package C8+\n");
7617
7618 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007619 lpt_init_pch_refclk(dev);
7620
7621 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7622 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7623 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7624 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7625 }
7626
7627 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007628}
7629
Paulo Zanoni9a952a02014-03-07 20:12:34 -03007630static void snb_modeset_global_resources(struct drm_device *dev)
7631{
7632 modeset_update_crtc_power_domains(dev);
7633}
7634
Imre Deak4f074122013-10-16 17:25:51 +03007635static void haswell_modeset_global_resources(struct drm_device *dev)
7636{
Paulo Zanonida723562013-12-19 11:54:51 -02007637 modeset_update_crtc_power_domains(dev);
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02007638}
7639
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007640static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007641 int x, int y,
7642 struct drm_framebuffer *fb)
7643{
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007645
Paulo Zanoni566b7342013-11-25 15:27:08 -02007646 if (!intel_ddi_pll_select(intel_crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007647 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03007648
Daniel Vetter644cef32014-04-24 23:55:07 +02007649 intel_crtc->lowfreq_avail = false;
7650
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007651 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007652}
7653
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007654static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7655 enum port port,
7656 struct intel_crtc_config *pipe_config)
7657{
7658 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7659
7660 switch (pipe_config->ddi_pll_sel) {
7661 case PORT_CLK_SEL_WRPLL1:
7662 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7663 break;
7664 case PORT_CLK_SEL_WRPLL2:
7665 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7666 break;
7667 }
7668}
7669
Daniel Vetter26804af2014-06-25 22:01:55 +03007670static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7671 struct intel_crtc_config *pipe_config)
7672{
7673 struct drm_device *dev = crtc->base.dev;
7674 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007675 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03007676 enum port port;
7677 uint32_t tmp;
7678
7679 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7680
7681 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7682
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007683 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +03007684
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007685 if (pipe_config->shared_dpll >= 0) {
7686 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7687
7688 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7689 &pipe_config->dpll_hw_state));
7690 }
7691
Daniel Vetter26804af2014-06-25 22:01:55 +03007692 /*
7693 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7694 * DDI E. So just check whether this pipe is wired to DDI E and whether
7695 * the PCH transcoder is on.
7696 */
7697 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7698 pipe_config->has_pch_encoder = true;
7699
7700 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7701 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7702 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7703
7704 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7705 }
7706}
7707
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007708static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7709 struct intel_crtc_config *pipe_config)
7710{
7711 struct drm_device *dev = crtc->base.dev;
7712 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007713 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007714 uint32_t tmp;
7715
Imre Deakb5482bd2014-03-05 16:20:55 +02007716 if (!intel_display_power_enabled(dev_priv,
7717 POWER_DOMAIN_PIPE(crtc->pipe)))
7718 return false;
7719
Daniel Vettere143a212013-07-04 12:01:15 +02007720 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007721 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7722
Daniel Vettereccb1402013-05-22 00:50:22 +02007723 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7724 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7725 enum pipe trans_edp_pipe;
7726 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7727 default:
7728 WARN(1, "unknown pipe linked to edp transcoder\n");
7729 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7730 case TRANS_DDI_EDP_INPUT_A_ON:
7731 trans_edp_pipe = PIPE_A;
7732 break;
7733 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7734 trans_edp_pipe = PIPE_B;
7735 break;
7736 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7737 trans_edp_pipe = PIPE_C;
7738 break;
7739 }
7740
7741 if (trans_edp_pipe == crtc->pipe)
7742 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7743 }
7744
Imre Deakda7e29b2014-02-18 00:02:02 +02007745 if (!intel_display_power_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02007746 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03007747 return false;
7748
Daniel Vettereccb1402013-05-22 00:50:22 +02007749 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007750 if (!(tmp & PIPECONF_ENABLE))
7751 return false;
7752
Daniel Vetter26804af2014-06-25 22:01:55 +03007753 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007754
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007755 intel_get_pipe_timings(crtc, pipe_config);
7756
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007757 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Imre Deakda7e29b2014-02-18 00:02:02 +02007758 if (intel_display_power_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007759 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01007760
Jesse Barnese59150d2014-01-07 13:30:45 -08007761 if (IS_HASWELL(dev))
7762 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7763 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007764
Daniel Vetter6c49f242013-06-06 12:45:25 +02007765 pipe_config->pixel_multiplier = 1;
7766
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007767 return true;
7768}
7769
Jani Nikula1a915102013-10-16 12:34:48 +03007770static struct {
7771 int clock;
7772 u32 config;
7773} hdmi_audio_clock[] = {
7774 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7775 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7776 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7777 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7778 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7779 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7780 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7781 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7782 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7783 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7784};
7785
7786/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7787static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7788{
7789 int i;
7790
7791 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7792 if (mode->clock == hdmi_audio_clock[i].clock)
7793 break;
7794 }
7795
7796 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7797 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7798 i = 1;
7799 }
7800
7801 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7802 hdmi_audio_clock[i].clock,
7803 hdmi_audio_clock[i].config);
7804
7805 return hdmi_audio_clock[i].config;
7806}
7807
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007808static bool intel_eld_uptodate(struct drm_connector *connector,
7809 int reg_eldv, uint32_t bits_eldv,
7810 int reg_elda, uint32_t bits_elda,
7811 int reg_edid)
7812{
7813 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7814 uint8_t *eld = connector->eld;
7815 uint32_t i;
7816
7817 i = I915_READ(reg_eldv);
7818 i &= bits_eldv;
7819
7820 if (!eld[0])
7821 return !i;
7822
7823 if (!i)
7824 return false;
7825
7826 i = I915_READ(reg_elda);
7827 i &= ~bits_elda;
7828 I915_WRITE(reg_elda, i);
7829
7830 for (i = 0; i < eld[2]; i++)
7831 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7832 return false;
7833
7834 return true;
7835}
7836
Wu Fengguange0dac652011-09-05 14:25:34 +08007837static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007838 struct drm_crtc *crtc,
7839 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007840{
7841 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7842 uint8_t *eld = connector->eld;
7843 uint32_t eldv;
7844 uint32_t len;
7845 uint32_t i;
7846
7847 i = I915_READ(G4X_AUD_VID_DID);
7848
7849 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7850 eldv = G4X_ELDV_DEVCL_DEVBLC;
7851 else
7852 eldv = G4X_ELDV_DEVCTG;
7853
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007854 if (intel_eld_uptodate(connector,
7855 G4X_AUD_CNTL_ST, eldv,
7856 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7857 G4X_HDMIW_HDMIEDID))
7858 return;
7859
Wu Fengguange0dac652011-09-05 14:25:34 +08007860 i = I915_READ(G4X_AUD_CNTL_ST);
7861 i &= ~(eldv | G4X_ELD_ADDR);
7862 len = (i >> 9) & 0x1f; /* ELD buffer size */
7863 I915_WRITE(G4X_AUD_CNTL_ST, i);
7864
7865 if (!eld[0])
7866 return;
7867
7868 len = min_t(uint8_t, eld[2], len);
7869 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7870 for (i = 0; i < len; i++)
7871 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7872
7873 i = I915_READ(G4X_AUD_CNTL_ST);
7874 i |= eldv;
7875 I915_WRITE(G4X_AUD_CNTL_ST, i);
7876}
7877
Wang Xingchao83358c852012-08-16 22:43:37 +08007878static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007879 struct drm_crtc *crtc,
7880 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007881{
7882 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7883 uint8_t *eld = connector->eld;
Wang Xingchao83358c852012-08-16 22:43:37 +08007884 uint32_t eldv;
7885 uint32_t i;
7886 int len;
7887 int pipe = to_intel_crtc(crtc)->pipe;
7888 int tmp;
7889
7890 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7891 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7892 int aud_config = HSW_AUD_CFG(pipe);
7893 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7894
Wang Xingchao83358c852012-08-16 22:43:37 +08007895 /* Audio output enable */
7896 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7897 tmp = I915_READ(aud_cntrl_st2);
7898 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7899 I915_WRITE(aud_cntrl_st2, tmp);
Daniel Vetterc7905792014-04-16 16:56:09 +02007900 POSTING_READ(aud_cntrl_st2);
Wang Xingchao83358c852012-08-16 22:43:37 +08007901
Daniel Vetterc7905792014-04-16 16:56:09 +02007902 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Wang Xingchao83358c852012-08-16 22:43:37 +08007903
7904 /* Set ELD valid state */
7905 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007906 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007907 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7908 I915_WRITE(aud_cntrl_st2, tmp);
7909 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007910 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007911
7912 /* Enable HDMI mode */
7913 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007914 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007915 /* clear N_programing_enable and N_value_index */
7916 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7917 I915_WRITE(aud_config, tmp);
7918
7919 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7920
7921 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7922
7923 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7924 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7925 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7926 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007927 } else {
7928 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7929 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007930
7931 if (intel_eld_uptodate(connector,
7932 aud_cntrl_st2, eldv,
7933 aud_cntl_st, IBX_ELD_ADDRESS,
7934 hdmiw_hdmiedid))
7935 return;
7936
7937 i = I915_READ(aud_cntrl_st2);
7938 i &= ~eldv;
7939 I915_WRITE(aud_cntrl_st2, i);
7940
7941 if (!eld[0])
7942 return;
7943
7944 i = I915_READ(aud_cntl_st);
7945 i &= ~IBX_ELD_ADDRESS;
7946 I915_WRITE(aud_cntl_st, i);
7947 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7948 DRM_DEBUG_DRIVER("port num:%d\n", i);
7949
7950 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7951 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7952 for (i = 0; i < len; i++)
7953 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7954
7955 i = I915_READ(aud_cntrl_st2);
7956 i |= eldv;
7957 I915_WRITE(aud_cntrl_st2, i);
7958
7959}
7960
Wu Fengguange0dac652011-09-05 14:25:34 +08007961static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007962 struct drm_crtc *crtc,
7963 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007964{
7965 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7966 uint8_t *eld = connector->eld;
7967 uint32_t eldv;
7968 uint32_t i;
7969 int len;
7970 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007971 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007972 int aud_cntl_st;
7973 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007974 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007975
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007976 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007977 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7978 aud_config = IBX_AUD_CFG(pipe);
7979 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007980 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007981 } else if (IS_VALLEYVIEW(connector->dev)) {
7982 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7983 aud_config = VLV_AUD_CFG(pipe);
7984 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7985 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007986 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007987 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7988 aud_config = CPT_AUD_CFG(pipe);
7989 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007990 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007991 }
7992
Wang Xingchao9b138a82012-08-09 16:52:18 +08007993 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08007994
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007995 if (IS_VALLEYVIEW(connector->dev)) {
7996 struct intel_encoder *intel_encoder;
7997 struct intel_digital_port *intel_dig_port;
7998
7999 intel_encoder = intel_attached_encoder(connector);
8000 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8001 i = intel_dig_port->port;
8002 } else {
8003 i = I915_READ(aud_cntl_st);
8004 i = (i >> 29) & DIP_PORT_SEL_MASK;
8005 /* DIP_Port_Select, 0x1 = PortB */
8006 }
8007
Wu Fengguange0dac652011-09-05 14:25:34 +08008008 if (!i) {
8009 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8010 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008011 eldv = IBX_ELD_VALIDB;
8012 eldv |= IBX_ELD_VALIDB << 4;
8013 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08008014 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03008015 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008016 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08008017 }
8018
Wu Fengguang3a9627f2011-12-09 20:42:19 +08008019 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8020 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8021 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06008022 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03008023 } else {
8024 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8025 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08008026
8027 if (intel_eld_uptodate(connector,
8028 aud_cntrl_st2, eldv,
8029 aud_cntl_st, IBX_ELD_ADDRESS,
8030 hdmiw_hdmiedid))
8031 return;
8032
Wu Fengguange0dac652011-09-05 14:25:34 +08008033 i = I915_READ(aud_cntrl_st2);
8034 i &= ~eldv;
8035 I915_WRITE(aud_cntrl_st2, i);
8036
8037 if (!eld[0])
8038 return;
8039
Wu Fengguange0dac652011-09-05 14:25:34 +08008040 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08008041 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08008042 I915_WRITE(aud_cntl_st, i);
8043
8044 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8045 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8046 for (i = 0; i < len; i++)
8047 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8048
8049 i = I915_READ(aud_cntrl_st2);
8050 i |= eldv;
8051 I915_WRITE(aud_cntrl_st2, i);
8052}
8053
8054void intel_write_eld(struct drm_encoder *encoder,
8055 struct drm_display_mode *mode)
8056{
8057 struct drm_crtc *crtc = encoder->crtc;
8058 struct drm_connector *connector;
8059 struct drm_device *dev = encoder->dev;
8060 struct drm_i915_private *dev_priv = dev->dev_private;
8061
8062 connector = drm_select_eld(encoder, mode);
8063 if (!connector)
8064 return;
8065
8066 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8067 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03008068 connector->name,
Wu Fengguange0dac652011-09-05 14:25:34 +08008069 connector->encoder->base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +03008070 connector->encoder->name);
Wu Fengguange0dac652011-09-05 14:25:34 +08008071
8072 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8073
8074 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03008075 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08008076}
8077
Chris Wilson560b85b2010-08-07 11:01:38 +01008078static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8079{
8080 struct drm_device *dev = crtc->dev;
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälädc41c152014-08-13 11:57:05 +03008083 uint32_t cntl = 0, size = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01008084
Ville Syrjälädc41c152014-08-13 11:57:05 +03008085 if (base) {
8086 unsigned int width = intel_crtc->cursor_width;
8087 unsigned int height = intel_crtc->cursor_height;
8088 unsigned int stride = roundup_pow_of_two(width) * 4;
8089
8090 switch (stride) {
8091 default:
8092 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8093 width, stride);
8094 stride = 256;
8095 /* fallthrough */
8096 case 256:
8097 case 512:
8098 case 1024:
8099 case 2048:
8100 break;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008101 }
8102
Ville Syrjälädc41c152014-08-13 11:57:05 +03008103 cntl |= CURSOR_ENABLE |
8104 CURSOR_GAMMA_ENABLE |
8105 CURSOR_FORMAT_ARGB |
8106 CURSOR_STRIDE(stride);
8107
8108 size = (height << 12) | width;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008109 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008110
Ville Syrjälädc41c152014-08-13 11:57:05 +03008111 if (intel_crtc->cursor_cntl != 0 &&
8112 (intel_crtc->cursor_base != base ||
8113 intel_crtc->cursor_size != size ||
8114 intel_crtc->cursor_cntl != cntl)) {
8115 /* On these chipsets we can only modify the base/size/stride
8116 * whilst the cursor is disabled.
8117 */
8118 I915_WRITE(_CURACNTR, 0);
8119 POSTING_READ(_CURACNTR);
8120 intel_crtc->cursor_cntl = 0;
8121 }
8122
8123 if (intel_crtc->cursor_base != base)
8124 I915_WRITE(_CURABASE, base);
8125
8126 if (intel_crtc->cursor_size != size) {
8127 I915_WRITE(CURSIZE, size);
8128 intel_crtc->cursor_size = size;
8129 }
8130
Chris Wilson4b0e3332014-05-30 16:35:26 +03008131 if (intel_crtc->cursor_cntl != cntl) {
8132 I915_WRITE(_CURACNTR, cntl);
8133 POSTING_READ(_CURACNTR);
8134 intel_crtc->cursor_cntl = cntl;
8135 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008136}
8137
8138static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8139{
8140 struct drm_device *dev = crtc->dev;
8141 struct drm_i915_private *dev_priv = dev->dev_private;
8142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8143 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008144 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01008145
Chris Wilson4b0e3332014-05-30 16:35:26 +03008146 cntl = 0;
8147 if (base) {
8148 cntl = MCURSOR_GAMMA_ENABLE;
8149 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308150 case 64:
8151 cntl |= CURSOR_MODE_64_ARGB_AX;
8152 break;
8153 case 128:
8154 cntl |= CURSOR_MODE_128_ARGB_AX;
8155 break;
8156 case 256:
8157 cntl |= CURSOR_MODE_256_ARGB_AX;
8158 break;
8159 default:
8160 WARN_ON(1);
8161 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01008162 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008163 cntl |= pipe << 28; /* Connect to correct pipe */
Chris Wilson560b85b2010-08-07 11:01:38 +01008164 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008165 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8166 cntl |= CURSOR_PIPE_CSC_ENABLE;
8167
8168 if (intel_crtc->cursor_cntl != cntl) {
8169 I915_WRITE(CURCNTR(pipe), cntl);
8170 POSTING_READ(CURCNTR(pipe));
8171 intel_crtc->cursor_cntl = cntl;
8172 }
8173
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008174 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008175 I915_WRITE(CURBASE(pipe), base);
8176 POSTING_READ(CURBASE(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008177}
8178
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008179/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01008180static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8181 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008182{
8183 struct drm_device *dev = crtc->dev;
8184 struct drm_i915_private *dev_priv = dev->dev_private;
8185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8186 int pipe = intel_crtc->pipe;
Matt Roper3d7d6512014-06-10 08:28:13 -07008187 int x = crtc->cursor_x;
8188 int y = crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008189 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008190
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008191 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008192 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008193
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008194 if (x >= intel_crtc->config.pipe_src_w)
8195 base = 0;
8196
8197 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008198 base = 0;
8199
8200 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008201 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008202 base = 0;
8203
8204 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8205 x = -x;
8206 }
8207 pos |= x << CURSOR_X_SHIFT;
8208
8209 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008210 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008211 base = 0;
8212
8213 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8214 y = -y;
8215 }
8216 pos |= y << CURSOR_Y_SHIFT;
8217
Chris Wilson4b0e3332014-05-30 16:35:26 +03008218 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008219 return;
8220
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008221 I915_WRITE(CURPOS(pipe), pos);
8222
Ville Syrjälä8ac54662014-08-12 19:39:54 +03008223 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008224 i845_update_cursor(crtc, base);
8225 else
8226 i9xx_update_cursor(crtc, base);
Chris Wilson4b0e3332014-05-30 16:35:26 +03008227 intel_crtc->cursor_base = base;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008228}
8229
Ville Syrjälädc41c152014-08-13 11:57:05 +03008230static bool cursor_size_ok(struct drm_device *dev,
8231 uint32_t width, uint32_t height)
8232{
8233 if (width == 0 || height == 0)
8234 return false;
8235
8236 /*
8237 * 845g/865g are special in that they are only limited by
8238 * the width of their cursors, the height is arbitrary up to
8239 * the precision of the register. Everything else requires
8240 * square cursors, limited to a few power-of-two sizes.
8241 */
8242 if (IS_845G(dev) || IS_I865G(dev)) {
8243 if ((width & 63) != 0)
8244 return false;
8245
8246 if (width > (IS_845G(dev) ? 64 : 512))
8247 return false;
8248
8249 if (height > 1023)
8250 return false;
8251 } else {
8252 switch (width | height) {
8253 case 256:
8254 case 128:
8255 if (IS_GEN2(dev))
8256 return false;
8257 case 64:
8258 break;
8259 default:
8260 return false;
8261 }
8262 }
8263
8264 return true;
8265}
8266
Matt Ropere3287952014-06-10 08:28:12 -07008267/*
8268 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8269 *
8270 * Note that the object's reference will be consumed if the update fails. If
8271 * the update succeeds, the reference of the old object (if any) will be
8272 * consumed.
8273 */
8274static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8275 struct drm_i915_gem_object *obj,
8276 uint32_t width, uint32_t height)
Jesse Barnes79e53942008-11-07 14:24:08 -08008277{
8278 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02008280 enum pipe pipe = intel_crtc->pipe;
Ville Syrjälädc41c152014-08-13 11:57:05 +03008281 unsigned old_width, stride;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008282 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008283 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008284
Jesse Barnes79e53942008-11-07 14:24:08 -08008285 /* if we want to turn off the cursor ignore width and height */
Matt Ropere3287952014-06-10 08:28:12 -07008286 if (!obj) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008287 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008288 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00008289 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008290 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008291 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008292 }
8293
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308294 /* Check for which cursor types we support */
Ville Syrjälädc41c152014-08-13 11:57:05 +03008295 if (!cursor_size_ok(dev, width, height)) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308296 DRM_DEBUG("Cursor dimension not supported\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08008297 return -EINVAL;
8298 }
8299
Ville Syrjälädc41c152014-08-13 11:57:05 +03008300 stride = roundup_pow_of_two(width) * 4;
8301 if (obj->base.size < stride * height) {
Matt Ropere3287952014-06-10 08:28:12 -07008302 DRM_DEBUG_KMS("buffer is too small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10008303 ret = -ENOMEM;
8304 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008305 }
8306
Dave Airlie71acb5e2008-12-30 20:31:46 +10008307 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008308 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008309 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008310 unsigned alignment;
8311
Chris Wilsond9e86c02010-11-10 16:40:20 +00008312 if (obj->tiling_mode) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008313 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008314 ret = -EINVAL;
8315 goto fail_locked;
8316 }
8317
Chris Wilson693db182013-03-05 14:52:39 +00008318 /* Note that the w/a also requires 2 PTE of padding following
8319 * the bo. We currently fill all unused PTE with the shadow
8320 * page and so we should always have valid PTE following the
8321 * cursor preventing the VT-d warning.
8322 */
8323 alignment = 0;
8324 if (need_vtd_wa(dev))
8325 alignment = 64*1024;
8326
8327 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008328 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008329 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008330 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008331 }
8332
Chris Wilsond9e86c02010-11-10 16:40:20 +00008333 ret = i915_gem_object_put_fence(obj);
8334 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008335 DRM_DEBUG_KMS("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00008336 goto fail_unpin;
8337 }
8338
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008339 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008340 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008341 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson00731152014-05-21 12:42:56 +01008342 ret = i915_gem_object_attach_phys(obj, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008343 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008344 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008345 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008346 }
Chris Wilson00731152014-05-21 12:42:56 +01008347 addr = obj->phys_handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008348 }
8349
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008350 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008351 if (intel_crtc->cursor_bo) {
Chris Wilson00731152014-05-21 12:42:56 +01008352 if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilsoncc98b412013-08-09 12:25:09 +01008353 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008354 }
Jesse Barnes80824002009-09-10 15:28:06 -07008355
Daniel Vettera071fa02014-06-18 23:28:09 +02008356 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8357 INTEL_FRONTBUFFER_CURSOR(pipe));
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008358 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008359
Chris Wilson64f962e2014-03-26 12:38:15 +00008360 old_width = intel_crtc->cursor_width;
8361
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008362 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008363 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008364 intel_crtc->cursor_width = width;
8365 intel_crtc->cursor_height = height;
8366
Chris Wilson64f962e2014-03-26 12:38:15 +00008367 if (intel_crtc->active) {
8368 if (old_width != width)
8369 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008370 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Chris Wilson64f962e2014-03-26 12:38:15 +00008371 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008372
Daniel Vetterf99d7062014-06-19 16:01:59 +02008373 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8374
Jesse Barnes79e53942008-11-07 14:24:08 -08008375 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008376fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008377 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008378fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008379 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00008380fail:
Chris Wilson05394f32010-11-08 19:18:58 +00008381 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10008382 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008383}
8384
Jesse Barnes79e53942008-11-07 14:24:08 -08008385static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008386 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008387{
James Simmons72034252010-08-03 01:33:19 +01008388 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008390
James Simmons72034252010-08-03 01:33:19 +01008391 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008392 intel_crtc->lut_r[i] = red[i] >> 8;
8393 intel_crtc->lut_g[i] = green[i] >> 8;
8394 intel_crtc->lut_b[i] = blue[i] >> 8;
8395 }
8396
8397 intel_crtc_load_lut(crtc);
8398}
8399
Jesse Barnes79e53942008-11-07 14:24:08 -08008400/* VESA 640x480x72Hz mode to set on the pipe */
8401static struct drm_display_mode load_detect_mode = {
8402 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8403 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8404};
8405
Daniel Vettera8bb6812014-02-10 18:00:39 +01008406struct drm_framebuffer *
8407__intel_framebuffer_create(struct drm_device *dev,
8408 struct drm_mode_fb_cmd2 *mode_cmd,
8409 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008410{
8411 struct intel_framebuffer *intel_fb;
8412 int ret;
8413
8414 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8415 if (!intel_fb) {
8416 drm_gem_object_unreference_unlocked(&obj->base);
8417 return ERR_PTR(-ENOMEM);
8418 }
8419
8420 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008421 if (ret)
8422 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008423
8424 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008425err:
8426 drm_gem_object_unreference_unlocked(&obj->base);
8427 kfree(intel_fb);
8428
8429 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008430}
8431
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008432static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008433intel_framebuffer_create(struct drm_device *dev,
8434 struct drm_mode_fb_cmd2 *mode_cmd,
8435 struct drm_i915_gem_object *obj)
8436{
8437 struct drm_framebuffer *fb;
8438 int ret;
8439
8440 ret = i915_mutex_lock_interruptible(dev);
8441 if (ret)
8442 return ERR_PTR(ret);
8443 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8444 mutex_unlock(&dev->struct_mutex);
8445
8446 return fb;
8447}
8448
Chris Wilsond2dff872011-04-19 08:36:26 +01008449static u32
8450intel_framebuffer_pitch_for_width(int width, int bpp)
8451{
8452 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8453 return ALIGN(pitch, 64);
8454}
8455
8456static u32
8457intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8458{
8459 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +02008460 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +01008461}
8462
8463static struct drm_framebuffer *
8464intel_framebuffer_create_for_mode(struct drm_device *dev,
8465 struct drm_display_mode *mode,
8466 int depth, int bpp)
8467{
8468 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008469 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008470
8471 obj = i915_gem_alloc_object(dev,
8472 intel_framebuffer_size_for_mode(mode, bpp));
8473 if (obj == NULL)
8474 return ERR_PTR(-ENOMEM);
8475
8476 mode_cmd.width = mode->hdisplay;
8477 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008478 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8479 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008480 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008481
8482 return intel_framebuffer_create(dev, &mode_cmd, obj);
8483}
8484
8485static struct drm_framebuffer *
8486mode_fits_in_fbdev(struct drm_device *dev,
8487 struct drm_display_mode *mode)
8488{
Daniel Vetter4520f532013-10-09 09:18:51 +02008489#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008490 struct drm_i915_private *dev_priv = dev->dev_private;
8491 struct drm_i915_gem_object *obj;
8492 struct drm_framebuffer *fb;
8493
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008494 if (!dev_priv->fbdev)
8495 return NULL;
8496
8497 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008498 return NULL;
8499
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008500 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008501 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008502
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008503 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008504 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8505 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008506 return NULL;
8507
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008508 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008509 return NULL;
8510
8511 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008512#else
8513 return NULL;
8514#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008515}
8516
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008517bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008518 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05008519 struct intel_load_detect_pipe *old,
8520 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008521{
8522 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008523 struct intel_encoder *intel_encoder =
8524 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008525 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008526 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008527 struct drm_crtc *crtc = NULL;
8528 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008529 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05008530 struct drm_mode_config *config = &dev->mode_config;
8531 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008532
Chris Wilsond2dff872011-04-19 08:36:26 +01008533 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008534 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008535 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008536
Rob Clark51fd3712013-11-19 12:10:12 -05008537retry:
8538 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8539 if (ret)
8540 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008541
Jesse Barnes79e53942008-11-07 14:24:08 -08008542 /*
8543 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008544 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008545 * - if the connector already has an assigned crtc, use it (but make
8546 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008547 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008548 * - try to find the first unused crtc that can drive this connector,
8549 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008550 */
8551
8552 /* See if we already have a CRTC for this connector */
8553 if (encoder->crtc) {
8554 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008555
Rob Clark51fd3712013-11-19 12:10:12 -05008556 ret = drm_modeset_lock(&crtc->mutex, ctx);
8557 if (ret)
8558 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01008559
Daniel Vetter24218aa2012-08-12 19:27:11 +02008560 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008561 old->load_detect_temp = false;
8562
8563 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008564 if (connector->dpms != DRM_MODE_DPMS_ON)
8565 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008566
Chris Wilson71731882011-04-19 23:10:58 +01008567 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008568 }
8569
8570 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008571 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008572 i++;
8573 if (!(encoder->possible_crtcs & (1 << i)))
8574 continue;
Ville Syrjäläa4592492014-08-11 13:15:36 +03008575 if (possible_crtc->enabled)
8576 continue;
8577 /* This can occur when applying the pipe A quirk on resume. */
8578 if (to_intel_crtc(possible_crtc)->new_enabled)
8579 continue;
8580
8581 crtc = possible_crtc;
8582 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08008583 }
8584
8585 /*
8586 * If we didn't find an unused CRTC, don't use any.
8587 */
8588 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008589 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05008590 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08008591 }
8592
Rob Clark51fd3712013-11-19 12:10:12 -05008593 ret = drm_modeset_lock(&crtc->mutex, ctx);
8594 if (ret)
8595 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02008596 intel_encoder->new_crtc = to_intel_crtc(crtc);
8597 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008598
8599 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008600 intel_crtc->new_enabled = true;
8601 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008602 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008603 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008604 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008605
Chris Wilson64927112011-04-20 07:25:26 +01008606 if (!mode)
8607 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008608
Chris Wilsond2dff872011-04-19 08:36:26 +01008609 /* We need a framebuffer large enough to accommodate all accesses
8610 * that the plane may generate whilst we perform load detection.
8611 * We can not rely on the fbcon either being present (we get called
8612 * during its initialisation to detect all boot displays, or it may
8613 * not even exist) or that it is large enough to satisfy the
8614 * requested mode.
8615 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008616 fb = mode_fits_in_fbdev(dev, mode);
8617 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008618 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008619 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8620 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008621 } else
8622 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008623 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008624 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008625 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008626 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008627
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008628 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008629 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008630 if (old->release_fb)
8631 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008632 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008633 }
Chris Wilson71731882011-04-19 23:10:58 +01008634
Jesse Barnes79e53942008-11-07 14:24:08 -08008635 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008636 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008637 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008638
8639 fail:
8640 intel_crtc->new_enabled = crtc->enabled;
8641 if (intel_crtc->new_enabled)
8642 intel_crtc->new_config = &intel_crtc->config;
8643 else
8644 intel_crtc->new_config = NULL;
Rob Clark51fd3712013-11-19 12:10:12 -05008645fail_unlock:
8646 if (ret == -EDEADLK) {
8647 drm_modeset_backoff(ctx);
8648 goto retry;
8649 }
8650
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008651 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008652}
8653
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008654void intel_release_load_detect_pipe(struct drm_connector *connector,
Ville Syrjälä208bf9f2014-08-11 13:15:35 +03008655 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008656{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008657 struct intel_encoder *intel_encoder =
8658 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008659 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008660 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008662
Chris Wilsond2dff872011-04-19 08:36:26 +01008663 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008664 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008665 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008666
Chris Wilson8261b192011-04-19 23:18:09 +01008667 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008668 to_intel_connector(connector)->new_encoder = NULL;
8669 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008670 intel_crtc->new_enabled = false;
8671 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008672 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008673
Daniel Vetter36206362012-12-10 20:42:17 +01008674 if (old->release_fb) {
8675 drm_framebuffer_unregister_private(old->release_fb);
8676 drm_framebuffer_unreference(old->release_fb);
8677 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008678
Chris Wilson0622a532011-04-21 09:32:11 +01008679 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008680 }
8681
Eric Anholtc751ce42010-03-25 11:48:48 -07008682 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008683 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8684 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008685}
8686
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008687static int i9xx_pll_refclk(struct drm_device *dev,
8688 const struct intel_crtc_config *pipe_config)
8689{
8690 struct drm_i915_private *dev_priv = dev->dev_private;
8691 u32 dpll = pipe_config->dpll_hw_state.dpll;
8692
8693 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008694 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008695 else if (HAS_PCH_SPLIT(dev))
8696 return 120000;
8697 else if (!IS_GEN2(dev))
8698 return 96000;
8699 else
8700 return 48000;
8701}
8702
Jesse Barnes79e53942008-11-07 14:24:08 -08008703/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008704static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8705 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008706{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008707 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008708 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008709 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008710 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008711 u32 fp;
8712 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008713 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008714
8715 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008716 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008717 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008718 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008719
8720 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008721 if (IS_PINEVIEW(dev)) {
8722 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8723 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008724 } else {
8725 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8726 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8727 }
8728
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008729 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008730 if (IS_PINEVIEW(dev))
8731 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8732 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008733 else
8734 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008735 DPLL_FPA01_P1_POST_DIV_SHIFT);
8736
8737 switch (dpll & DPLL_MODE_MASK) {
8738 case DPLLB_MODE_DAC_SERIAL:
8739 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8740 5 : 10;
8741 break;
8742 case DPLLB_MODE_LVDS:
8743 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8744 7 : 14;
8745 break;
8746 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008747 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008748 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008749 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008750 }
8751
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008752 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008753 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008754 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008755 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008756 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008757 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008758 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008759
8760 if (is_lvds) {
8761 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8762 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008763
8764 if (lvds & LVDS_CLKB_POWER_UP)
8765 clock.p2 = 7;
8766 else
8767 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008768 } else {
8769 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8770 clock.p1 = 2;
8771 else {
8772 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8773 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8774 }
8775 if (dpll & PLL_P2_DIVIDE_BY_4)
8776 clock.p2 = 4;
8777 else
8778 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008779 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008780
8781 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008782 }
8783
Ville Syrjälä18442d02013-09-13 16:00:08 +03008784 /*
8785 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008786 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008787 * encoder's get_config() function.
8788 */
8789 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008790}
8791
Ville Syrjälä6878da02013-09-13 15:59:11 +03008792int intel_dotclock_calculate(int link_freq,
8793 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008794{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008795 /*
8796 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008797 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008798 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008799 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008800 *
8801 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008802 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008803 */
8804
Ville Syrjälä6878da02013-09-13 15:59:11 +03008805 if (!m_n->link_n)
8806 return 0;
8807
8808 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8809}
8810
Ville Syrjälä18442d02013-09-13 16:00:08 +03008811static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8812 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008813{
8814 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008815
8816 /* read out port_clock from the DPLL */
8817 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008818
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008819 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008820 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008821 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008822 * agree once we know their relationship in the encoder's
8823 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008824 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008825 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008826 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8827 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008828}
8829
8830/** Returns the currently programmed mode of the given pipe. */
8831struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8832 struct drm_crtc *crtc)
8833{
Jesse Barnes548f2452011-02-17 10:40:53 -08008834 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008836 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008837 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008838 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008839 int htot = I915_READ(HTOTAL(cpu_transcoder));
8840 int hsync = I915_READ(HSYNC(cpu_transcoder));
8841 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8842 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008843 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008844
8845 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8846 if (!mode)
8847 return NULL;
8848
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008849 /*
8850 * Construct a pipe_config sufficient for getting the clock info
8851 * back out of crtc_clock_get.
8852 *
8853 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8854 * to use a real value here instead.
8855 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008856 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008857 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008858 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8859 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8860 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008861 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8862
Ville Syrjälä773ae032013-09-23 17:48:20 +03008863 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008864 mode->hdisplay = (htot & 0xffff) + 1;
8865 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8866 mode->hsync_start = (hsync & 0xffff) + 1;
8867 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8868 mode->vdisplay = (vtot & 0xffff) + 1;
8869 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8870 mode->vsync_start = (vsync & 0xffff) + 1;
8871 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8872
8873 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008874
8875 return mode;
8876}
8877
Daniel Vettercc365132014-06-18 13:59:13 +02008878static void intel_increase_pllclock(struct drm_device *dev,
8879 enum pipe pipe)
Jesse Barnes652c3932009-08-17 13:31:43 -07008880{
Jani Nikulafbee40d2014-03-31 14:27:18 +03008881 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008882 int dpll_reg = DPLL(pipe);
8883 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07008884
Sonika Jindalbaff2962014-07-22 11:16:35 +05308885 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008886 return;
8887
8888 if (!dev_priv->lvds_downclock_avail)
8889 return;
8890
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008891 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008892 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08008893 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008894
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008895 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008896
8897 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8898 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008899 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008900
Jesse Barnes652c3932009-08-17 13:31:43 -07008901 dpll = I915_READ(dpll_reg);
8902 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08008903 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008904 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008905}
8906
8907static void intel_decrease_pllclock(struct drm_crtc *crtc)
8908{
8909 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008910 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008912
Sonika Jindalbaff2962014-07-22 11:16:35 +05308913 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008914 return;
8915
8916 if (!dev_priv->lvds_downclock_avail)
8917 return;
8918
8919 /*
8920 * Since this is called by a timer, we should never get here in
8921 * the manual case.
8922 */
8923 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008924 int pipe = intel_crtc->pipe;
8925 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008926 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008927
Zhao Yakui44d98a62009-10-09 11:39:40 +08008928 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008929
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008930 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008931
Chris Wilson074b5e12012-05-02 12:07:06 +01008932 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008933 dpll |= DISPLAY_RATE_SELECT_FPA1;
8934 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008935 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008936 dpll = I915_READ(dpll_reg);
8937 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008938 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008939 }
8940
8941}
8942
Chris Wilsonf047e392012-07-21 12:31:41 +01008943void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008944{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008945 struct drm_i915_private *dev_priv = dev->dev_private;
8946
Chris Wilsonf62a0072014-02-21 17:55:39 +00008947 if (dev_priv->mm.busy)
8948 return;
8949
Paulo Zanoni43694d62014-03-07 20:08:08 -03008950 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008951 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008952 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008953}
8954
8955void intel_mark_idle(struct drm_device *dev)
8956{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008957 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008958 struct drm_crtc *crtc;
8959
Chris Wilsonf62a0072014-02-21 17:55:39 +00008960 if (!dev_priv->mm.busy)
8961 return;
8962
8963 dev_priv->mm.busy = false;
8964
Jani Nikulad330a952014-01-21 11:24:25 +02008965 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008966 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008967
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008968 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008969 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008970 continue;
8971
8972 intel_decrease_pllclock(crtc);
8973 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008974
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008975 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008976 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008977
8978out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03008979 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008980}
8981
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -07008982
Daniel Vetterf99d7062014-06-19 16:01:59 +02008983/**
8984 * intel_mark_fb_busy - mark given planes as busy
8985 * @dev: DRM device
8986 * @frontbuffer_bits: bits for the affected planes
8987 * @ring: optional ring for asynchronous commands
8988 *
8989 * This function gets called every time the screen contents change. It can be
8990 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8991 */
8992static void intel_mark_fb_busy(struct drm_device *dev,
8993 unsigned frontbuffer_bits,
8994 struct intel_engine_cs *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01008995{
Damien Lespiau055e3932014-08-18 13:49:10 +01008996 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettercc365132014-06-18 13:59:13 +02008997 enum pipe pipe;
Jesse Barnes652c3932009-08-17 13:31:43 -07008998
Jani Nikulad330a952014-01-21 11:24:25 +02008999 if (!i915.powersave)
Jesse Barnes652c3932009-08-17 13:31:43 -07009000 return;
9001
Damien Lespiau055e3932014-08-18 13:49:10 +01009002 for_each_pipe(dev_priv, pipe) {
Daniel Vetterf99d7062014-06-19 16:01:59 +02009003 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
Jesse Barnes652c3932009-08-17 13:31:43 -07009004 continue;
9005
Daniel Vettercc365132014-06-18 13:59:13 +02009006 intel_increase_pllclock(dev, pipe);
Chris Wilsonc65355b2013-06-06 16:53:41 -03009007 if (ring && intel_fbc_enabled(dev))
9008 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07009009 }
Jesse Barnes652c3932009-08-17 13:31:43 -07009010}
9011
Daniel Vetterf99d7062014-06-19 16:01:59 +02009012/**
9013 * intel_fb_obj_invalidate - invalidate frontbuffer object
9014 * @obj: GEM object to invalidate
9015 * @ring: set for asynchronous rendering
9016 *
9017 * This function gets called every time rendering on the given object starts and
9018 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9019 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9020 * until the rendering completes or a flip on this frontbuffer plane is
9021 * scheduled.
9022 */
9023void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9024 struct intel_engine_cs *ring)
9025{
9026 struct drm_device *dev = obj->base.dev;
9027 struct drm_i915_private *dev_priv = dev->dev_private;
9028
9029 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9030
9031 if (!obj->frontbuffer_bits)
9032 return;
9033
9034 if (ring) {
9035 mutex_lock(&dev_priv->fb_tracking.lock);
9036 dev_priv->fb_tracking.busy_bits
9037 |= obj->frontbuffer_bits;
9038 dev_priv->fb_tracking.flip_bits
9039 &= ~obj->frontbuffer_bits;
9040 mutex_unlock(&dev_priv->fb_tracking.lock);
9041 }
9042
9043 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9044
Daniel Vetter9ca15302014-07-11 10:30:16 -07009045 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009046}
9047
9048/**
9049 * intel_frontbuffer_flush - flush frontbuffer
9050 * @dev: DRM device
9051 * @frontbuffer_bits: frontbuffer plane tracking bits
9052 *
9053 * This function gets called every time rendering on the given planes has
9054 * completed and frontbuffer caching can be started again. Flushes will get
9055 * delayed if they're blocked by some oustanding asynchronous rendering.
9056 *
9057 * Can be called without any locks held.
9058 */
9059void intel_frontbuffer_flush(struct drm_device *dev,
9060 unsigned frontbuffer_bits)
9061{
9062 struct drm_i915_private *dev_priv = dev->dev_private;
9063
9064 /* Delay flushing when rings are still busy.*/
9065 mutex_lock(&dev_priv->fb_tracking.lock);
9066 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9067 mutex_unlock(&dev_priv->fb_tracking.lock);
9068
9069 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9070
Daniel Vetter9ca15302014-07-11 10:30:16 -07009071 intel_edp_psr_flush(dev, frontbuffer_bits);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009072}
9073
9074/**
9075 * intel_fb_obj_flush - flush frontbuffer object
9076 * @obj: GEM object to flush
9077 * @retire: set when retiring asynchronous rendering
9078 *
9079 * This function gets called every time rendering on the given object has
9080 * completed and frontbuffer caching can be started again. If @retire is true
9081 * then any delayed flushes will be unblocked.
9082 */
9083void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9084 bool retire)
9085{
9086 struct drm_device *dev = obj->base.dev;
9087 struct drm_i915_private *dev_priv = dev->dev_private;
9088 unsigned frontbuffer_bits;
9089
9090 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9091
9092 if (!obj->frontbuffer_bits)
9093 return;
9094
9095 frontbuffer_bits = obj->frontbuffer_bits;
9096
9097 if (retire) {
9098 mutex_lock(&dev_priv->fb_tracking.lock);
9099 /* Filter out new bits since rendering started. */
9100 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9101
9102 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9103 mutex_unlock(&dev_priv->fb_tracking.lock);
9104 }
9105
9106 intel_frontbuffer_flush(dev, frontbuffer_bits);
9107}
9108
9109/**
9110 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9111 * @dev: DRM device
9112 * @frontbuffer_bits: frontbuffer plane tracking bits
9113 *
9114 * This function gets called after scheduling a flip on @obj. The actual
9115 * frontbuffer flushing will be delayed until completion is signalled with
9116 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9117 * flush will be cancelled.
9118 *
9119 * Can be called without any locks held.
9120 */
9121void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9122 unsigned frontbuffer_bits)
9123{
9124 struct drm_i915_private *dev_priv = dev->dev_private;
9125
9126 mutex_lock(&dev_priv->fb_tracking.lock);
9127 dev_priv->fb_tracking.flip_bits
9128 |= frontbuffer_bits;
9129 mutex_unlock(&dev_priv->fb_tracking.lock);
9130}
9131
9132/**
9133 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9134 * @dev: DRM device
9135 * @frontbuffer_bits: frontbuffer plane tracking bits
9136 *
9137 * This function gets called after the flip has been latched and will complete
9138 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9139 *
9140 * Can be called without any locks held.
9141 */
9142void intel_frontbuffer_flip_complete(struct drm_device *dev,
9143 unsigned frontbuffer_bits)
9144{
9145 struct drm_i915_private *dev_priv = dev->dev_private;
9146
9147 mutex_lock(&dev_priv->fb_tracking.lock);
9148 /* Mask any cancelled flips. */
9149 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9150 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9151 mutex_unlock(&dev_priv->fb_tracking.lock);
9152
9153 intel_frontbuffer_flush(dev, frontbuffer_bits);
9154}
9155
Jesse Barnes79e53942008-11-07 14:24:08 -08009156static void intel_crtc_destroy(struct drm_crtc *crtc)
9157{
9158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009159 struct drm_device *dev = crtc->dev;
9160 struct intel_unpin_work *work;
9161 unsigned long flags;
9162
9163 spin_lock_irqsave(&dev->event_lock, flags);
9164 work = intel_crtc->unpin_work;
9165 intel_crtc->unpin_work = NULL;
9166 spin_unlock_irqrestore(&dev->event_lock, flags);
9167
9168 if (work) {
9169 cancel_work_sync(&work->work);
9170 kfree(work);
9171 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009172
9173 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009174
Jesse Barnes79e53942008-11-07 14:24:08 -08009175 kfree(intel_crtc);
9176}
9177
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009178static void intel_unpin_work_fn(struct work_struct *__work)
9179{
9180 struct intel_unpin_work *work =
9181 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009182 struct drm_device *dev = work->crtc->dev;
Daniel Vetterf99d7062014-06-19 16:01:59 +02009183 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009184
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009185 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01009186 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00009187 drm_gem_object_unreference(&work->pending_flip_obj->base);
9188 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00009189
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009190 intel_update_fbc(dev);
9191 mutex_unlock(&dev->struct_mutex);
9192
Daniel Vetterf99d7062014-06-19 16:01:59 +02009193 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9194
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009195 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9196 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9197
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009198 kfree(work);
9199}
9200
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009201static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01009202 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009203{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009204 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9206 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009207 unsigned long flags;
9208
9209 /* Ignore early vblank irqs */
9210 if (intel_crtc == NULL)
9211 return;
9212
9213 spin_lock_irqsave(&dev->event_lock, flags);
9214 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00009215
9216 /* Ensure we don't miss a work->pending update ... */
9217 smp_rmb();
9218
9219 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009220 spin_unlock_irqrestore(&dev->event_lock, flags);
9221 return;
9222 }
9223
Chris Wilsone7d841c2012-12-03 11:36:30 +00009224 /* and that the unpin work is consistent wrt ->pending. */
9225 smp_rmb();
9226
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009227 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009228
Rob Clark45a066e2012-10-08 14:50:40 -05009229 if (work->event)
9230 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009231
Daniel Vetter87b6b102014-05-15 15:33:46 +02009232 drm_crtc_vblank_put(crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01009233
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009234 spin_unlock_irqrestore(&dev->event_lock, flags);
9235
Daniel Vetter2c10d572012-12-20 21:24:07 +01009236 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009237
9238 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07009239
9240 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009241}
9242
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009243void intel_finish_page_flip(struct drm_device *dev, int pipe)
9244{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009245 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009246 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9247
Mario Kleiner49b14a52010-12-09 07:00:07 +01009248 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009249}
9250
9251void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9252{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009253 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009254 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9255
Mario Kleiner49b14a52010-12-09 07:00:07 +01009256 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009257}
9258
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009259/* Is 'a' after or equal to 'b'? */
9260static bool g4x_flip_count_after_eq(u32 a, u32 b)
9261{
9262 return !((a - b) & 0x80000000);
9263}
9264
9265static bool page_flip_finished(struct intel_crtc *crtc)
9266{
9267 struct drm_device *dev = crtc->base.dev;
9268 struct drm_i915_private *dev_priv = dev->dev_private;
9269
9270 /*
9271 * The relevant registers doen't exist on pre-ctg.
9272 * As the flip done interrupt doesn't trigger for mmio
9273 * flips on gmch platforms, a flip count check isn't
9274 * really needed there. But since ctg has the registers,
9275 * include it in the check anyway.
9276 */
9277 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9278 return true;
9279
9280 /*
9281 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9282 * used the same base address. In that case the mmio flip might
9283 * have completed, but the CS hasn't even executed the flip yet.
9284 *
9285 * A flip count check isn't enough as the CS might have updated
9286 * the base address just after start of vblank, but before we
9287 * managed to process the interrupt. This means we'd complete the
9288 * CS flip too soon.
9289 *
9290 * Combining both checks should get us a good enough result. It may
9291 * still happen that the CS flip has been executed, but has not
9292 * yet actually completed. But in case the base address is the same
9293 * anyway, we don't really care.
9294 */
9295 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9296 crtc->unpin_work->gtt_offset &&
9297 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9298 crtc->unpin_work->flip_count);
9299}
9300
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009301void intel_prepare_page_flip(struct drm_device *dev, int plane)
9302{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009303 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009304 struct intel_crtc *intel_crtc =
9305 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9306 unsigned long flags;
9307
Chris Wilsone7d841c2012-12-03 11:36:30 +00009308 /* NB: An MMIO update of the plane base pointer will also
9309 * generate a page-flip completion irq, i.e. every modeset
9310 * is also accompanied by a spurious intel_prepare_page_flip().
9311 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009312 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009313 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00009314 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009315 spin_unlock_irqrestore(&dev->event_lock, flags);
9316}
9317
Robin Schroereba905b2014-05-18 02:24:50 +02009318static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00009319{
9320 /* Ensure that the work item is consistent when activating it ... */
9321 smp_wmb();
9322 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9323 /* and that it is marked active as soon as the irq could fire. */
9324 smp_wmb();
9325}
9326
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009327static int intel_gen2_queue_flip(struct drm_device *dev,
9328 struct drm_crtc *crtc,
9329 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009330 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009331 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009332 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009333{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009335 u32 flip_mask;
9336 int ret;
9337
Daniel Vetter6d90c952012-04-26 23:28:05 +02009338 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009339 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009340 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009341
9342 /* Can't queue multiple flips, so wait for the previous
9343 * one to finish before executing the next.
9344 */
9345 if (intel_crtc->plane)
9346 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9347 else
9348 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009349 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9350 intel_ring_emit(ring, MI_NOOP);
9351 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9352 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9353 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009354 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009355 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00009356
9357 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009358 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009359 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009360}
9361
9362static int intel_gen3_queue_flip(struct drm_device *dev,
9363 struct drm_crtc *crtc,
9364 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009365 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009366 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009367 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009368{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009370 u32 flip_mask;
9371 int ret;
9372
Daniel Vetter6d90c952012-04-26 23:28:05 +02009373 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009374 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009375 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009376
9377 if (intel_crtc->plane)
9378 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9379 else
9380 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009381 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9382 intel_ring_emit(ring, MI_NOOP);
9383 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9384 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9385 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009386 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009387 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009388
Chris Wilsone7d841c2012-12-03 11:36:30 +00009389 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009390 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009391 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009392}
9393
9394static int intel_gen4_queue_flip(struct drm_device *dev,
9395 struct drm_crtc *crtc,
9396 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009397 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009398 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009399 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009400{
9401 struct drm_i915_private *dev_priv = dev->dev_private;
9402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9403 uint32_t pf, pipesrc;
9404 int ret;
9405
Daniel Vetter6d90c952012-04-26 23:28:05 +02009406 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009407 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009408 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009409
9410 /* i965+ uses the linear or tiled offsets from the
9411 * Display Registers (which do not change across a page-flip)
9412 * so we need only reprogram the base address.
9413 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009414 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9415 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9416 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009417 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009418 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009419
9420 /* XXX Enabling the panel-fitter across page-flip is so far
9421 * untested on non-native modes, so ignore it for now.
9422 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9423 */
9424 pf = 0;
9425 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009426 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009427
9428 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009429 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009430 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009431}
9432
9433static int intel_gen6_queue_flip(struct drm_device *dev,
9434 struct drm_crtc *crtc,
9435 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009436 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009437 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009438 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009439{
9440 struct drm_i915_private *dev_priv = dev->dev_private;
9441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9442 uint32_t pf, pipesrc;
9443 int ret;
9444
Daniel Vetter6d90c952012-04-26 23:28:05 +02009445 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009446 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009447 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009448
Daniel Vetter6d90c952012-04-26 23:28:05 +02009449 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9450 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9451 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009452 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009453
Chris Wilson99d9acd2012-04-17 20:37:00 +01009454 /* Contrary to the suggestions in the documentation,
9455 * "Enable Panel Fitter" does not seem to be required when page
9456 * flipping with a non-native mode, and worse causes a normal
9457 * modeset to fail.
9458 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9459 */
9460 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009461 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009462 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009463
9464 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009465 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009466 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009467}
9468
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009469static int intel_gen7_queue_flip(struct drm_device *dev,
9470 struct drm_crtc *crtc,
9471 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009472 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009473 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009474 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009475{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009477 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009478 int len, ret;
9479
Robin Schroereba905b2014-05-18 02:24:50 +02009480 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009481 case PLANE_A:
9482 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9483 break;
9484 case PLANE_B:
9485 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9486 break;
9487 case PLANE_C:
9488 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9489 break;
9490 default:
9491 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009492 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009493 }
9494
Chris Wilsonffe74d72013-08-26 20:58:12 +01009495 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009496 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009497 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009498 /*
9499 * On Gen 8, SRM is now taking an extra dword to accommodate
9500 * 48bits addresses, and we need a NOOP for the batch size to
9501 * stay even.
9502 */
9503 if (IS_GEN8(dev))
9504 len += 2;
9505 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009506
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009507 /*
9508 * BSpec MI_DISPLAY_FLIP for IVB:
9509 * "The full packet must be contained within the same cache line."
9510 *
9511 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9512 * cacheline, if we ever start emitting more commands before
9513 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9514 * then do the cacheline alignment, and finally emit the
9515 * MI_DISPLAY_FLIP.
9516 */
9517 ret = intel_ring_cacheline_align(ring);
9518 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009519 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009520
Chris Wilsonffe74d72013-08-26 20:58:12 +01009521 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009522 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009523 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009524
Chris Wilsonffe74d72013-08-26 20:58:12 +01009525 /* Unmask the flip-done completion message. Note that the bspec says that
9526 * we should do this for both the BCS and RCS, and that we must not unmask
9527 * more than one flip event at any time (or ensure that one flip message
9528 * can be sent by waiting for flip-done prior to queueing new flips).
9529 * Experimentation says that BCS works despite DERRMR masking all
9530 * flip-done completion events and that unmasking all planes at once
9531 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9532 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9533 */
9534 if (ring->id == RCS) {
9535 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9536 intel_ring_emit(ring, DERRMR);
9537 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9538 DERRMR_PIPEB_PRI_FLIP_DONE |
9539 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009540 if (IS_GEN8(dev))
9541 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9542 MI_SRM_LRM_GLOBAL_GTT);
9543 else
9544 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9545 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009546 intel_ring_emit(ring, DERRMR);
9547 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009548 if (IS_GEN8(dev)) {
9549 intel_ring_emit(ring, 0);
9550 intel_ring_emit(ring, MI_NOOP);
9551 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009552 }
9553
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009554 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009555 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009556 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009557 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009558
9559 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009560 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009561 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009562}
9563
Sourab Gupta84c33a62014-06-02 16:47:17 +05309564static bool use_mmio_flip(struct intel_engine_cs *ring,
9565 struct drm_i915_gem_object *obj)
9566{
9567 /*
9568 * This is not being used for older platforms, because
9569 * non-availability of flip done interrupt forces us to use
9570 * CS flips. Older platforms derive flip done using some clever
9571 * tricks involving the flip_pending status bits and vblank irqs.
9572 * So using MMIO flips there would disrupt this mechanism.
9573 */
9574
Chris Wilson8e09bf82014-07-08 10:40:30 +01009575 if (ring == NULL)
9576 return true;
9577
Sourab Gupta84c33a62014-06-02 16:47:17 +05309578 if (INTEL_INFO(ring->dev)->gen < 5)
9579 return false;
9580
9581 if (i915.use_mmio_flip < 0)
9582 return false;
9583 else if (i915.use_mmio_flip > 0)
9584 return true;
Oscar Mateo14bf9932014-07-24 17:04:34 +01009585 else if (i915.enable_execlists)
9586 return true;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309587 else
9588 return ring != obj->ring;
9589}
9590
9591static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9592{
9593 struct drm_device *dev = intel_crtc->base.dev;
9594 struct drm_i915_private *dev_priv = dev->dev_private;
9595 struct intel_framebuffer *intel_fb =
9596 to_intel_framebuffer(intel_crtc->base.primary->fb);
9597 struct drm_i915_gem_object *obj = intel_fb->obj;
9598 u32 dspcntr;
9599 u32 reg;
9600
9601 intel_mark_page_flip_active(intel_crtc);
9602
9603 reg = DSPCNTR(intel_crtc->plane);
9604 dspcntr = I915_READ(reg);
9605
9606 if (INTEL_INFO(dev)->gen >= 4) {
9607 if (obj->tiling_mode != I915_TILING_NONE)
9608 dspcntr |= DISPPLANE_TILED;
9609 else
9610 dspcntr &= ~DISPPLANE_TILED;
9611 }
9612 I915_WRITE(reg, dspcntr);
9613
9614 I915_WRITE(DSPSURF(intel_crtc->plane),
9615 intel_crtc->unpin_work->gtt_offset);
9616 POSTING_READ(DSPSURF(intel_crtc->plane));
9617}
9618
9619static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9620{
9621 struct intel_engine_cs *ring;
9622 int ret;
9623
9624 lockdep_assert_held(&obj->base.dev->struct_mutex);
9625
9626 if (!obj->last_write_seqno)
9627 return 0;
9628
9629 ring = obj->ring;
9630
9631 if (i915_seqno_passed(ring->get_seqno(ring, true),
9632 obj->last_write_seqno))
9633 return 0;
9634
9635 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9636 if (ret)
9637 return ret;
9638
9639 if (WARN_ON(!ring->irq_get(ring)))
9640 return 0;
9641
9642 return 1;
9643}
9644
9645void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9646{
9647 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9648 struct intel_crtc *intel_crtc;
9649 unsigned long irq_flags;
9650 u32 seqno;
9651
9652 seqno = ring->get_seqno(ring, false);
9653
9654 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9655 for_each_intel_crtc(ring->dev, intel_crtc) {
9656 struct intel_mmio_flip *mmio_flip;
9657
9658 mmio_flip = &intel_crtc->mmio_flip;
9659 if (mmio_flip->seqno == 0)
9660 continue;
9661
9662 if (ring->id != mmio_flip->ring_id)
9663 continue;
9664
9665 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9666 intel_do_mmio_flip(intel_crtc);
9667 mmio_flip->seqno = 0;
9668 ring->irq_put(ring);
9669 }
9670 }
9671 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9672}
9673
9674static int intel_queue_mmio_flip(struct drm_device *dev,
9675 struct drm_crtc *crtc,
9676 struct drm_framebuffer *fb,
9677 struct drm_i915_gem_object *obj,
9678 struct intel_engine_cs *ring,
9679 uint32_t flags)
9680{
9681 struct drm_i915_private *dev_priv = dev->dev_private;
9682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9683 unsigned long irq_flags;
9684 int ret;
9685
9686 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9687 return -EBUSY;
9688
9689 ret = intel_postpone_flip(obj);
9690 if (ret < 0)
9691 return ret;
9692 if (ret == 0) {
9693 intel_do_mmio_flip(intel_crtc);
9694 return 0;
9695 }
9696
9697 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9698 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9699 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9700 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9701
9702 /*
9703 * Double check to catch cases where irq fired before
9704 * mmio flip data was ready
9705 */
9706 intel_notify_mmio_flip(obj->ring);
9707 return 0;
9708}
9709
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009710static int intel_default_queue_flip(struct drm_device *dev,
9711 struct drm_crtc *crtc,
9712 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009713 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009714 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009715 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009716{
9717 return -ENODEV;
9718}
9719
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009720static int intel_crtc_page_flip(struct drm_crtc *crtc,
9721 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009722 struct drm_pending_vblank_event *event,
9723 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009724{
9725 struct drm_device *dev = crtc->dev;
9726 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009727 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009728 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02009730 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009731 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009732 struct intel_engine_cs *ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009733 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01009734 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009735
Matt Roper2ff8fde2014-07-08 07:50:07 -07009736 /*
9737 * drm_mode_page_flip_ioctl() should already catch this, but double
9738 * check to be safe. In the future we may enable pageflipping from
9739 * a disabled primary plane.
9740 */
9741 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9742 return -EBUSY;
9743
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009744 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009745 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009746 return -EINVAL;
9747
9748 /*
9749 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9750 * Note that pitch changes could also affect these register.
9751 */
9752 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009753 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9754 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009755 return -EINVAL;
9756
Chris Wilsonf900db42014-02-20 09:26:13 +00009757 if (i915_terminally_wedged(&dev_priv->gpu_error))
9758 goto out_hang;
9759
Daniel Vetterb14c5672013-09-19 12:18:32 +02009760 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009761 if (work == NULL)
9762 return -ENOMEM;
9763
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009764 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009765 work->crtc = crtc;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009766 work->old_fb_obj = intel_fb_obj(old_fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009767 INIT_WORK(&work->work, intel_unpin_work_fn);
9768
Daniel Vetter87b6b102014-05-15 15:33:46 +02009769 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009770 if (ret)
9771 goto free_work;
9772
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009773 /* We borrow the event spin lock for protecting unpin_work */
9774 spin_lock_irqsave(&dev->event_lock, flags);
9775 if (intel_crtc->unpin_work) {
9776 spin_unlock_irqrestore(&dev->event_lock, flags);
9777 kfree(work);
Daniel Vetter87b6b102014-05-15 15:33:46 +02009778 drm_crtc_vblank_put(crtc);
Chris Wilson468f0b42010-05-27 13:18:13 +01009779
9780 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009781 return -EBUSY;
9782 }
9783 intel_crtc->unpin_work = work;
9784 spin_unlock_irqrestore(&dev->event_lock, flags);
9785
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009786 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9787 flush_workqueue(dev_priv->wq);
9788
Chris Wilson79158102012-05-23 11:13:58 +01009789 ret = i915_mutex_lock_interruptible(dev);
9790 if (ret)
9791 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009792
Jesse Barnes75dfca82010-02-10 15:09:44 -08009793 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009794 drm_gem_object_reference(&work->old_fb_obj->base);
9795 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009796
Matt Roperf4510a22014-04-01 15:22:40 -07009797 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009798
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009799 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009800
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01009801 work->enable_stall_check = true;
9802
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009803 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009804 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009805
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009806 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Daniel Vettera071fa02014-06-18 23:28:09 +02009807 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009808
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009809 if (IS_VALLEYVIEW(dev)) {
9810 ring = &dev_priv->ring[BCS];
Chris Wilson8e09bf82014-07-08 10:40:30 +01009811 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9812 /* vlv: DISPLAY_FLIP fails to change tiling */
9813 ring = NULL;
Chris Wilson2a92d5b2014-07-08 10:40:29 +01009814 } else if (IS_IVYBRIDGE(dev)) {
9815 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009816 } else if (INTEL_INFO(dev)->gen >= 7) {
9817 ring = obj->ring;
9818 if (ring == NULL || ring->id != RCS)
9819 ring = &dev_priv->ring[BCS];
9820 } else {
9821 ring = &dev_priv->ring[RCS];
9822 }
9823
9824 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009825 if (ret)
9826 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009827
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009828 work->gtt_offset =
9829 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9830
Sourab Gupta84c33a62014-06-02 16:47:17 +05309831 if (use_mmio_flip(ring, obj))
9832 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9833 page_flip_flags);
9834 else
9835 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9836 page_flip_flags);
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009837 if (ret)
9838 goto cleanup_unpin;
9839
Daniel Vettera071fa02014-06-18 23:28:09 +02009840 i915_gem_track_fb(work->old_fb_obj, obj,
9841 INTEL_FRONTBUFFER_PRIMARY(pipe));
9842
Chris Wilson7782de32011-07-08 12:22:41 +01009843 intel_disable_fbc(dev);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009844 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009845 mutex_unlock(&dev->struct_mutex);
9846
Jesse Barnese5510fa2010-07-01 16:48:37 -07009847 trace_i915_flip_request(intel_crtc->plane, obj);
9848
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009849 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009850
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009851cleanup_unpin:
9852 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009853cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009854 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009855 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009856 drm_gem_object_unreference(&work->old_fb_obj->base);
9857 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009858 mutex_unlock(&dev->struct_mutex);
9859
Chris Wilson79158102012-05-23 11:13:58 +01009860cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01009861 spin_lock_irqsave(&dev->event_lock, flags);
9862 intel_crtc->unpin_work = NULL;
9863 spin_unlock_irqrestore(&dev->event_lock, flags);
9864
Daniel Vetter87b6b102014-05-15 15:33:46 +02009865 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009866free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009867 kfree(work);
9868
Chris Wilsonf900db42014-02-20 09:26:13 +00009869 if (ret == -EIO) {
9870out_hang:
9871 intel_crtc_wait_for_pending_flips(crtc);
9872 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9873 if (ret == 0 && event)
Daniel Vettera071fa02014-06-18 23:28:09 +02009874 drm_send_vblank_event(dev, pipe, event);
Chris Wilsonf900db42014-02-20 09:26:13 +00009875 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009876 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009877}
9878
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009879static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009880 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9881 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009882};
9883
Daniel Vetter9a935852012-07-05 22:34:27 +02009884/**
9885 * intel_modeset_update_staged_output_state
9886 *
9887 * Updates the staged output configuration state, e.g. after we've read out the
9888 * current hw state.
9889 */
9890static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9891{
Ville Syrjälä76688512014-01-10 11:28:06 +02009892 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009893 struct intel_encoder *encoder;
9894 struct intel_connector *connector;
9895
9896 list_for_each_entry(connector, &dev->mode_config.connector_list,
9897 base.head) {
9898 connector->new_encoder =
9899 to_intel_encoder(connector->base.encoder);
9900 }
9901
Damien Lespiaub2784e12014-08-05 11:29:37 +01009902 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009903 encoder->new_crtc =
9904 to_intel_crtc(encoder->base.crtc);
9905 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009906
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009907 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009908 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009909
9910 if (crtc->new_enabled)
9911 crtc->new_config = &crtc->config;
9912 else
9913 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009914 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009915}
9916
9917/**
9918 * intel_modeset_commit_output_state
9919 *
9920 * This function copies the stage display pipe configuration to the real one.
9921 */
9922static void intel_modeset_commit_output_state(struct drm_device *dev)
9923{
Ville Syrjälä76688512014-01-10 11:28:06 +02009924 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009925 struct intel_encoder *encoder;
9926 struct intel_connector *connector;
9927
9928 list_for_each_entry(connector, &dev->mode_config.connector_list,
9929 base.head) {
9930 connector->base.encoder = &connector->new_encoder->base;
9931 }
9932
Damien Lespiaub2784e12014-08-05 11:29:37 +01009933 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009934 encoder->base.crtc = &encoder->new_crtc->base;
9935 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009936
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009937 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009938 crtc->base.enabled = crtc->new_enabled;
9939 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009940}
9941
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009942static void
Robin Schroereba905b2014-05-18 02:24:50 +02009943connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009944 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009945{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009946 int bpp = pipe_config->pipe_bpp;
9947
9948 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9949 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009950 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009951
9952 /* Don't use an invalid EDID bpc value */
9953 if (connector->base.display_info.bpc &&
9954 connector->base.display_info.bpc * 3 < bpp) {
9955 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9956 bpp, connector->base.display_info.bpc*3);
9957 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9958 }
9959
9960 /* Clamp bpp to 8 on screens without EDID 1.4 */
9961 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9962 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9963 bpp);
9964 pipe_config->pipe_bpp = 24;
9965 }
9966}
9967
9968static int
9969compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9970 struct drm_framebuffer *fb,
9971 struct intel_crtc_config *pipe_config)
9972{
9973 struct drm_device *dev = crtc->base.dev;
9974 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009975 int bpp;
9976
Daniel Vetterd42264b2013-03-28 16:38:08 +01009977 switch (fb->pixel_format) {
9978 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009979 bpp = 8*3; /* since we go through a colormap */
9980 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009981 case DRM_FORMAT_XRGB1555:
9982 case DRM_FORMAT_ARGB1555:
9983 /* checked in intel_framebuffer_init already */
9984 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9985 return -EINVAL;
9986 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009987 bpp = 6*3; /* min is 18bpp */
9988 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009989 case DRM_FORMAT_XBGR8888:
9990 case DRM_FORMAT_ABGR8888:
9991 /* checked in intel_framebuffer_init already */
9992 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9993 return -EINVAL;
9994 case DRM_FORMAT_XRGB8888:
9995 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009996 bpp = 8*3;
9997 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009998 case DRM_FORMAT_XRGB2101010:
9999 case DRM_FORMAT_ARGB2101010:
10000 case DRM_FORMAT_XBGR2101010:
10001 case DRM_FORMAT_ABGR2101010:
10002 /* checked in intel_framebuffer_init already */
10003 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +010010004 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010005 bpp = 10*3;
10006 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +010010007 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010008 default:
10009 DRM_DEBUG_KMS("unsupported depth\n");
10010 return -EINVAL;
10011 }
10012
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010013 pipe_config->pipe_bpp = bpp;
10014
10015 /* Clamp display bpp to EDID value */
10016 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010017 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +020010018 if (!connector->new_encoder ||
10019 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010020 continue;
10021
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010022 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010023 }
10024
10025 return bpp;
10026}
10027
Daniel Vetter644db712013-09-19 14:53:58 +020010028static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10029{
10030 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10031 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +010010032 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +020010033 mode->crtc_hdisplay, mode->crtc_hsync_start,
10034 mode->crtc_hsync_end, mode->crtc_htotal,
10035 mode->crtc_vdisplay, mode->crtc_vsync_start,
10036 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10037}
10038
Daniel Vetterc0b03412013-05-28 12:05:54 +020010039static void intel_dump_pipe_config(struct intel_crtc *crtc,
10040 struct intel_crtc_config *pipe_config,
10041 const char *context)
10042{
10043 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10044 context, pipe_name(crtc->pipe));
10045
10046 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10047 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10048 pipe_config->pipe_bpp, pipe_config->dither);
10049 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10050 pipe_config->has_pch_encoder,
10051 pipe_config->fdi_lanes,
10052 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10053 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10054 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010055 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10056 pipe_config->has_dp_encoder,
10057 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10058 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10059 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010060
10061 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10062 pipe_config->has_dp_encoder,
10063 pipe_config->dp_m2_n2.gmch_m,
10064 pipe_config->dp_m2_n2.gmch_n,
10065 pipe_config->dp_m2_n2.link_m,
10066 pipe_config->dp_m2_n2.link_n,
10067 pipe_config->dp_m2_n2.tu);
10068
Daniel Vetterc0b03412013-05-28 12:05:54 +020010069 DRM_DEBUG_KMS("requested mode:\n");
10070 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10071 DRM_DEBUG_KMS("adjusted mode:\n");
10072 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +020010073 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +030010074 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010075 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10076 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010077 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10078 pipe_config->gmch_pfit.control,
10079 pipe_config->gmch_pfit.pgm_ratios,
10080 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010081 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +020010082 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010083 pipe_config->pch_pfit.size,
10084 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010085 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +030010086 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010087}
10088
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010089static bool encoders_cloneable(const struct intel_encoder *a,
10090 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010091{
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010092 /* masks could be asymmetric, so check both ways */
10093 return a == b || (a->cloneable & (1 << b->type) &&
10094 b->cloneable & (1 << a->type));
10095}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010096
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010097static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10098 struct intel_encoder *encoder)
10099{
10100 struct drm_device *dev = crtc->base.dev;
10101 struct intel_encoder *source_encoder;
10102
Damien Lespiaub2784e12014-08-05 11:29:37 +010010103 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010104 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010105 continue;
10106
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010107 if (!encoders_cloneable(encoder, source_encoder))
10108 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010109 }
10110
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010111 return true;
10112}
10113
10114static bool check_encoder_cloning(struct intel_crtc *crtc)
10115{
10116 struct drm_device *dev = crtc->base.dev;
10117 struct intel_encoder *encoder;
10118
Damien Lespiaub2784e12014-08-05 11:29:37 +010010119 for_each_intel_encoder(dev, encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010120 if (encoder->new_crtc != crtc)
10121 continue;
10122
10123 if (!check_single_encoder_cloning(crtc, encoder))
10124 return false;
10125 }
10126
10127 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010128}
10129
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010130static struct intel_crtc_config *
10131intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010132 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010133 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +020010134{
10135 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +020010136 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010137 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +010010138 int plane_bpp, ret = -EINVAL;
10139 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020010140
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010141 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010142 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10143 return ERR_PTR(-EINVAL);
10144 }
10145
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010146 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10147 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020010148 return ERR_PTR(-ENOMEM);
10149
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010150 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10151 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010152
Daniel Vettere143a212013-07-04 12:01:15 +020010153 pipe_config->cpu_transcoder =
10154 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010155 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010156
Imre Deak2960bc92013-07-30 13:36:32 +030010157 /*
10158 * Sanitize sync polarity flags based on requested ones. If neither
10159 * positive or negative polarity is requested, treat this as meaning
10160 * negative polarity.
10161 */
10162 if (!(pipe_config->adjusted_mode.flags &
10163 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10164 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10165
10166 if (!(pipe_config->adjusted_mode.flags &
10167 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10168 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10169
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010170 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10171 * plane pixel format and any sink constraints into account. Returns the
10172 * source plane bpp so that dithering can be selected on mismatches
10173 * after encoders and crtc also have had their say. */
10174 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10175 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010176 if (plane_bpp < 0)
10177 goto fail;
10178
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030010179 /*
10180 * Determine the real pipe dimensions. Note that stereo modes can
10181 * increase the actual pipe size due to the frame doubling and
10182 * insertion of additional space for blanks between the frame. This
10183 * is stored in the crtc timings. We use the requested mode to do this
10184 * computation to clearly distinguish it from the adjusted mode, which
10185 * can be changed by the connectors in the below retry loop.
10186 */
10187 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10188 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10189 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10190
Daniel Vettere29c22c2013-02-21 00:00:16 +010010191encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020010192 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020010193 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020010194 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010195
Daniel Vetter135c81b2013-07-21 21:37:09 +020010196 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +010010197 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020010198
Daniel Vetter7758a112012-07-08 19:40:39 +020010199 /* Pass our mode to the connectors and the CRTC to give them a chance to
10200 * adjust it according to limitations or connector properties, and also
10201 * a chance to reject the mode entirely.
10202 */
Damien Lespiaub2784e12014-08-05 11:29:37 +010010203 for_each_intel_encoder(dev, encoder) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010204
10205 if (&encoder->new_crtc->base != crtc)
10206 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +010010207
Daniel Vetterefea6e82013-07-21 21:36:59 +020010208 if (!(encoder->compute_config(encoder, pipe_config))) {
10209 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020010210 goto fail;
10211 }
10212 }
10213
Daniel Vetterff9a6752013-06-01 17:16:21 +020010214 /* Set default port clock if not overwritten by the encoder. Needs to be
10215 * done afterwards in case the encoder adjusts the mode. */
10216 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +010010217 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10218 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010219
Daniel Vettera43f6e02013-06-07 23:10:32 +020010220 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010221 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010222 DRM_DEBUG_KMS("CRTC fixup failed\n");
10223 goto fail;
10224 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010010225
10226 if (ret == RETRY) {
10227 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10228 ret = -EINVAL;
10229 goto fail;
10230 }
10231
10232 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10233 retry = false;
10234 goto encoder_retry;
10235 }
10236
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010237 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10238 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10239 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10240
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010241 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +020010242fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010243 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010244 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +020010245}
10246
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010247/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10248 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10249static void
10250intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10251 unsigned *prepare_pipes, unsigned *disable_pipes)
10252{
10253 struct intel_crtc *intel_crtc;
10254 struct drm_device *dev = crtc->dev;
10255 struct intel_encoder *encoder;
10256 struct intel_connector *connector;
10257 struct drm_crtc *tmp_crtc;
10258
10259 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10260
10261 /* Check which crtcs have changed outputs connected to them, these need
10262 * to be part of the prepare_pipes mask. We don't (yet) support global
10263 * modeset across multiple crtcs, so modeset_pipes will only have one
10264 * bit set at most. */
10265 list_for_each_entry(connector, &dev->mode_config.connector_list,
10266 base.head) {
10267 if (connector->base.encoder == &connector->new_encoder->base)
10268 continue;
10269
10270 if (connector->base.encoder) {
10271 tmp_crtc = connector->base.encoder->crtc;
10272
10273 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10274 }
10275
10276 if (connector->new_encoder)
10277 *prepare_pipes |=
10278 1 << connector->new_encoder->new_crtc->pipe;
10279 }
10280
Damien Lespiaub2784e12014-08-05 11:29:37 +010010281 for_each_intel_encoder(dev, encoder) {
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010282 if (encoder->base.crtc == &encoder->new_crtc->base)
10283 continue;
10284
10285 if (encoder->base.crtc) {
10286 tmp_crtc = encoder->base.crtc;
10287
10288 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10289 }
10290
10291 if (encoder->new_crtc)
10292 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10293 }
10294
Ville Syrjälä76688512014-01-10 11:28:06 +020010295 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010296 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010297 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010298 continue;
10299
Ville Syrjälä76688512014-01-10 11:28:06 +020010300 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010301 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +020010302 else
10303 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010304 }
10305
10306
10307 /* set_mode is also used to update properties on life display pipes. */
10308 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +020010309 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010310 *prepare_pipes |= 1 << intel_crtc->pipe;
10311
Daniel Vetterb6c51642013-04-12 18:48:43 +020010312 /*
10313 * For simplicity do a full modeset on any pipe where the output routing
10314 * changed. We could be more clever, but that would require us to be
10315 * more careful with calling the relevant encoder->mode_set functions.
10316 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010317 if (*prepare_pipes)
10318 *modeset_pipes = *prepare_pipes;
10319
10320 /* ... and mask these out. */
10321 *modeset_pipes &= ~(*disable_pipes);
10322 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +020010323
10324 /*
10325 * HACK: We don't (yet) fully support global modesets. intel_set_config
10326 * obies this rule, but the modeset restore mode of
10327 * intel_modeset_setup_hw_state does not.
10328 */
10329 *modeset_pipes &= 1 << intel_crtc->pipe;
10330 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +020010331
10332 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10333 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010334}
10335
Daniel Vetterea9d7582012-07-10 10:42:52 +020010336static bool intel_crtc_in_use(struct drm_crtc *crtc)
10337{
10338 struct drm_encoder *encoder;
10339 struct drm_device *dev = crtc->dev;
10340
10341 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10342 if (encoder->crtc == crtc)
10343 return true;
10344
10345 return false;
10346}
10347
10348static void
10349intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10350{
10351 struct intel_encoder *intel_encoder;
10352 struct intel_crtc *intel_crtc;
10353 struct drm_connector *connector;
10354
Damien Lespiaub2784e12014-08-05 11:29:37 +010010355 for_each_intel_encoder(dev, intel_encoder) {
Daniel Vetterea9d7582012-07-10 10:42:52 +020010356 if (!intel_encoder->base.crtc)
10357 continue;
10358
10359 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10360
10361 if (prepare_pipes & (1 << intel_crtc->pipe))
10362 intel_encoder->connectors_active = false;
10363 }
10364
10365 intel_modeset_commit_output_state(dev);
10366
Ville Syrjälä76688512014-01-10 11:28:06 +020010367 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010368 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010369 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010370 WARN_ON(intel_crtc->new_config &&
10371 intel_crtc->new_config != &intel_crtc->config);
10372 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010373 }
10374
10375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10376 if (!connector->encoder || !connector->encoder->crtc)
10377 continue;
10378
10379 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10380
10381 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +020010382 struct drm_property *dpms_property =
10383 dev->mode_config.dpms_property;
10384
Daniel Vetterea9d7582012-07-10 10:42:52 +020010385 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -050010386 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +020010387 dpms_property,
10388 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010389
10390 intel_encoder = to_intel_encoder(connector->encoder);
10391 intel_encoder->connectors_active = true;
10392 }
10393 }
10394
10395}
10396
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010397static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010398{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010399 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010400
10401 if (clock1 == clock2)
10402 return true;
10403
10404 if (!clock1 || !clock2)
10405 return false;
10406
10407 diff = abs(clock1 - clock2);
10408
10409 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10410 return true;
10411
10412 return false;
10413}
10414
Daniel Vetter25c5b262012-07-08 22:08:04 +020010415#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10416 list_for_each_entry((intel_crtc), \
10417 &(dev)->mode_config.crtc_list, \
10418 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +020010419 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020010420
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010421static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010422intel_pipe_config_compare(struct drm_device *dev,
10423 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010424 struct intel_crtc_config *pipe_config)
10425{
Daniel Vetter66e985c2013-06-05 13:34:20 +020010426#define PIPE_CONF_CHECK_X(name) \
10427 if (current_config->name != pipe_config->name) { \
10428 DRM_ERROR("mismatch in " #name " " \
10429 "(expected 0x%08x, found 0x%08x)\n", \
10430 current_config->name, \
10431 pipe_config->name); \
10432 return false; \
10433 }
10434
Daniel Vetter08a24032013-04-19 11:25:34 +020010435#define PIPE_CONF_CHECK_I(name) \
10436 if (current_config->name != pipe_config->name) { \
10437 DRM_ERROR("mismatch in " #name " " \
10438 "(expected %i, found %i)\n", \
10439 current_config->name, \
10440 pipe_config->name); \
10441 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010010442 }
10443
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010444/* This is required for BDW+ where there is only one set of registers for
10445 * switching between high and low RR.
10446 * This macro can be used whenever a comparison has to be made between one
10447 * hw state and multiple sw state variables.
10448 */
10449#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10450 if ((current_config->name != pipe_config->name) && \
10451 (current_config->alt_name != pipe_config->name)) { \
10452 DRM_ERROR("mismatch in " #name " " \
10453 "(expected %i or %i, found %i)\n", \
10454 current_config->name, \
10455 current_config->alt_name, \
10456 pipe_config->name); \
10457 return false; \
10458 }
10459
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010460#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10461 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -070010462 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010463 "(expected %i, found %i)\n", \
10464 current_config->name & (mask), \
10465 pipe_config->name & (mask)); \
10466 return false; \
10467 }
10468
Ville Syrjälä5e550652013-09-06 23:29:07 +030010469#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10470 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10471 DRM_ERROR("mismatch in " #name " " \
10472 "(expected %i, found %i)\n", \
10473 current_config->name, \
10474 pipe_config->name); \
10475 return false; \
10476 }
10477
Daniel Vetterbb760062013-06-06 14:55:52 +020010478#define PIPE_CONF_QUIRK(quirk) \
10479 ((current_config->quirks | pipe_config->quirks) & (quirk))
10480
Daniel Vettereccb1402013-05-22 00:50:22 +020010481 PIPE_CONF_CHECK_I(cpu_transcoder);
10482
Daniel Vetter08a24032013-04-19 11:25:34 +020010483 PIPE_CONF_CHECK_I(has_pch_encoder);
10484 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +020010485 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10486 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10487 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10488 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10489 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +020010490
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010491 PIPE_CONF_CHECK_I(has_dp_encoder);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010492
10493 if (INTEL_INFO(dev)->gen < 8) {
10494 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10495 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10496 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10497 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10498 PIPE_CONF_CHECK_I(dp_m_n.tu);
10499
10500 if (current_config->has_drrs) {
10501 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10502 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10503 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10504 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10505 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10506 }
10507 } else {
10508 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10509 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10510 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10511 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10512 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10513 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010514
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010515 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10516 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10517 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10518 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10519 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10520 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10521
10522 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10523 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10524 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10525 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10526 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10527 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10528
Daniel Vetterc93f54c2013-06-27 19:47:19 +020010529 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +020010530 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020010531 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10532 IS_VALLEYVIEW(dev))
10533 PIPE_CONF_CHECK_I(limited_color_range);
Daniel Vetter6c49f242013-06-06 12:45:25 +020010534
Daniel Vetter9ed109a2014-04-24 23:54:52 +020010535 PIPE_CONF_CHECK_I(has_audio);
10536
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010537 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10538 DRM_MODE_FLAG_INTERLACE);
10539
Daniel Vetterbb760062013-06-06 14:55:52 +020010540 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10541 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10542 DRM_MODE_FLAG_PHSYNC);
10543 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10544 DRM_MODE_FLAG_NHSYNC);
10545 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10546 DRM_MODE_FLAG_PVSYNC);
10547 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10548 DRM_MODE_FLAG_NVSYNC);
10549 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010550
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010551 PIPE_CONF_CHECK_I(pipe_src_w);
10552 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010553
Daniel Vetter99535992014-04-13 12:00:33 +020010554 /*
10555 * FIXME: BIOS likes to set up a cloned config with lvds+external
10556 * screen. Since we don't yet re-compute the pipe config when moving
10557 * just the lvds port away to another pipe the sw tracking won't match.
10558 *
10559 * Proper atomic modesets with recomputed global state will fix this.
10560 * Until then just don't check gmch state for inherited modes.
10561 */
10562 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10563 PIPE_CONF_CHECK_I(gmch_pfit.control);
10564 /* pfit ratios are autocomputed by the hw on gen4+ */
10565 if (INTEL_INFO(dev)->gen < 4)
10566 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10567 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10568 }
10569
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010570 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10571 if (current_config->pch_pfit.enabled) {
10572 PIPE_CONF_CHECK_I(pch_pfit.pos);
10573 PIPE_CONF_CHECK_I(pch_pfit.size);
10574 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010575
Jesse Barnese59150d2014-01-07 13:30:45 -080010576 /* BDW+ don't expose a synchronous way to read the state */
10577 if (IS_HASWELL(dev))
10578 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010579
Ville Syrjälä282740f2013-09-04 18:30:03 +030010580 PIPE_CONF_CHECK_I(double_wide);
10581
Daniel Vetter26804af2014-06-25 22:01:55 +030010582 PIPE_CONF_CHECK_X(ddi_pll_sel);
10583
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010584 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010585 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010586 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010587 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10588 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010589 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010590
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010591 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10592 PIPE_CONF_CHECK_I(pipe_bpp);
10593
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010594 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10595 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010596
Daniel Vetter66e985c2013-06-05 13:34:20 +020010597#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010598#undef PIPE_CONF_CHECK_I
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010599#undef PIPE_CONF_CHECK_I_ALT
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010600#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010601#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010602#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010603
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010604 return true;
10605}
10606
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010607static void
10608check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010609{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010610 struct intel_connector *connector;
10611
10612 list_for_each_entry(connector, &dev->mode_config.connector_list,
10613 base.head) {
10614 /* This also checks the encoder/connector hw state with the
10615 * ->get_hw_state callbacks. */
10616 intel_connector_check_state(connector);
10617
10618 WARN(&connector->new_encoder->base != connector->base.encoder,
10619 "connector's staged encoder doesn't match current encoder\n");
10620 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010621}
10622
10623static void
10624check_encoder_state(struct drm_device *dev)
10625{
10626 struct intel_encoder *encoder;
10627 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010628
Damien Lespiaub2784e12014-08-05 11:29:37 +010010629 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010630 bool enabled = false;
10631 bool active = false;
10632 enum pipe pipe, tracked_pipe;
10633
10634 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10635 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030010636 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010637
10638 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10639 "encoder's stage crtc doesn't match current crtc\n");
10640 WARN(encoder->connectors_active && !encoder->base.crtc,
10641 "encoder's active_connectors set, but no crtc\n");
10642
10643 list_for_each_entry(connector, &dev->mode_config.connector_list,
10644 base.head) {
10645 if (connector->base.encoder != &encoder->base)
10646 continue;
10647 enabled = true;
10648 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10649 active = true;
10650 }
Dave Airlie0e32b392014-05-02 14:02:48 +100010651 /*
10652 * for MST connectors if we unplug the connector is gone
10653 * away but the encoder is still connected to a crtc
10654 * until a modeset happens in response to the hotplug.
10655 */
10656 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10657 continue;
10658
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010659 WARN(!!encoder->base.crtc != enabled,
10660 "encoder's enabled state mismatch "
10661 "(expected %i, found %i)\n",
10662 !!encoder->base.crtc, enabled);
10663 WARN(active && !encoder->base.crtc,
10664 "active encoder with no crtc\n");
10665
10666 WARN(encoder->connectors_active != active,
10667 "encoder's computed active state doesn't match tracked active state "
10668 "(expected %i, found %i)\n", active, encoder->connectors_active);
10669
10670 active = encoder->get_hw_state(encoder, &pipe);
10671 WARN(active != encoder->connectors_active,
10672 "encoder's hw state doesn't match sw tracking "
10673 "(expected %i, found %i)\n",
10674 encoder->connectors_active, active);
10675
10676 if (!encoder->base.crtc)
10677 continue;
10678
10679 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10680 WARN(active && pipe != tracked_pipe,
10681 "active encoder's pipe doesn't match"
10682 "(expected %i, found %i)\n",
10683 tracked_pipe, pipe);
10684
10685 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010686}
10687
10688static void
10689check_crtc_state(struct drm_device *dev)
10690{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010691 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010692 struct intel_crtc *crtc;
10693 struct intel_encoder *encoder;
10694 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010695
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010696 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010697 bool enabled = false;
10698 bool active = false;
10699
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010700 memset(&pipe_config, 0, sizeof(pipe_config));
10701
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010702 DRM_DEBUG_KMS("[CRTC:%d]\n",
10703 crtc->base.base.id);
10704
10705 WARN(crtc->active && !crtc->base.enabled,
10706 "active crtc, but not enabled in sw tracking\n");
10707
Damien Lespiaub2784e12014-08-05 11:29:37 +010010708 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010709 if (encoder->base.crtc != &crtc->base)
10710 continue;
10711 enabled = true;
10712 if (encoder->connectors_active)
10713 active = true;
10714 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010715
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010716 WARN(active != crtc->active,
10717 "crtc's computed active state doesn't match tracked active state "
10718 "(expected %i, found %i)\n", active, crtc->active);
10719 WARN(enabled != crtc->base.enabled,
10720 "crtc's computed enabled state doesn't match tracked enabled state "
10721 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10722
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010723 active = dev_priv->display.get_pipe_config(crtc,
10724 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010725
10726 /* hw state is inconsistent with the pipe A quirk */
10727 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10728 active = crtc->active;
10729
Damien Lespiaub2784e12014-08-05 11:29:37 +010010730 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010731 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010732 if (encoder->base.crtc != &crtc->base)
10733 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010734 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010735 encoder->get_config(encoder, &pipe_config);
10736 }
10737
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010738 WARN(crtc->active != active,
10739 "crtc active state doesn't match with hw state "
10740 "(expected %i, found %i)\n", crtc->active, active);
10741
Daniel Vetterc0b03412013-05-28 12:05:54 +020010742 if (active &&
10743 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10744 WARN(1, "pipe state doesn't match!\n");
10745 intel_dump_pipe_config(crtc, &pipe_config,
10746 "[hw state]");
10747 intel_dump_pipe_config(crtc, &crtc->config,
10748 "[sw state]");
10749 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010750 }
10751}
10752
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010753static void
10754check_shared_dpll_state(struct drm_device *dev)
10755{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010756 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010757 struct intel_crtc *crtc;
10758 struct intel_dpll_hw_state dpll_hw_state;
10759 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010760
10761 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10762 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10763 int enabled_crtcs = 0, active_crtcs = 0;
10764 bool active;
10765
10766 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10767
10768 DRM_DEBUG_KMS("%s\n", pll->name);
10769
10770 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10771
10772 WARN(pll->active > pll->refcount,
10773 "more active pll users than references: %i vs %i\n",
10774 pll->active, pll->refcount);
10775 WARN(pll->active && !pll->on,
10776 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010777 WARN(pll->on && !pll->active,
10778 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010779 WARN(pll->on != active,
10780 "pll on state mismatch (expected %i, found %i)\n",
10781 pll->on, active);
10782
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010783 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010784 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10785 enabled_crtcs++;
10786 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10787 active_crtcs++;
10788 }
10789 WARN(pll->active != active_crtcs,
10790 "pll active crtcs mismatch (expected %i, found %i)\n",
10791 pll->active, active_crtcs);
10792 WARN(pll->refcount != enabled_crtcs,
10793 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10794 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010795
10796 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10797 sizeof(dpll_hw_state)),
10798 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010799 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010800}
10801
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010802void
10803intel_modeset_check_state(struct drm_device *dev)
10804{
10805 check_connector_state(dev);
10806 check_encoder_state(dev);
10807 check_crtc_state(dev);
10808 check_shared_dpll_state(dev);
10809}
10810
Ville Syrjälä18442d02013-09-13 16:00:08 +030010811void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10812 int dotclock)
10813{
10814 /*
10815 * FDI already provided one idea for the dotclock.
10816 * Yell if the encoder disagrees.
10817 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010818 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010819 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010820 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010821}
10822
Ville Syrjälä80715b22014-05-15 20:23:23 +030010823static void update_scanline_offset(struct intel_crtc *crtc)
10824{
10825 struct drm_device *dev = crtc->base.dev;
10826
10827 /*
10828 * The scanline counter increments at the leading edge of hsync.
10829 *
10830 * On most platforms it starts counting from vtotal-1 on the
10831 * first active line. That means the scanline counter value is
10832 * always one less than what we would expect. Ie. just after
10833 * start of vblank, which also occurs at start of hsync (on the
10834 * last active line), the scanline counter will read vblank_start-1.
10835 *
10836 * On gen2 the scanline counter starts counting from 1 instead
10837 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10838 * to keep the value positive), instead of adding one.
10839 *
10840 * On HSW+ the behaviour of the scanline counter depends on the output
10841 * type. For DP ports it behaves like most other platforms, but on HDMI
10842 * there's an extra 1 line difference. So we need to add two instead of
10843 * one to the value.
10844 */
10845 if (IS_GEN2(dev)) {
10846 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10847 int vtotal;
10848
10849 vtotal = mode->crtc_vtotal;
10850 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10851 vtotal /= 2;
10852
10853 crtc->scanline_offset = vtotal - 1;
10854 } else if (HAS_DDI(dev) &&
10855 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10856 crtc->scanline_offset = 2;
10857 } else
10858 crtc->scanline_offset = 1;
10859}
10860
Daniel Vetterf30da182013-04-11 20:22:50 +020010861static int __intel_set_mode(struct drm_crtc *crtc,
10862 struct drm_display_mode *mode,
10863 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +020010864{
10865 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010866 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010867 struct drm_display_mode *saved_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010868 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010869 struct intel_crtc *intel_crtc;
10870 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010871 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010872
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010873 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010874 if (!saved_mode)
10875 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010876
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010877 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +020010878 &prepare_pipes, &disable_pipes);
10879
Tim Gardner3ac18232012-12-07 07:54:26 -070010880 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010881
Daniel Vetter25c5b262012-07-08 22:08:04 +020010882 /* Hack: Because we don't (yet) support global modeset on multiple
10883 * crtcs, we don't keep track of the new mode for more than one crtc.
10884 * Hence simply check whether any bit is set in modeset_pipes in all the
10885 * pieces of code that are not yet converted to deal with mutliple crtcs
10886 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010887 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010888 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010889 if (IS_ERR(pipe_config)) {
10890 ret = PTR_ERR(pipe_config);
10891 pipe_config = NULL;
10892
Tim Gardner3ac18232012-12-07 07:54:26 -070010893 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010894 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020010895 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10896 "[modeset]");
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010897 to_intel_crtc(crtc)->new_config = pipe_config;
Daniel Vettera6778b32012-07-02 09:56:42 +020010898 }
10899
Jesse Barnes30a970c2013-11-04 13:48:12 -080010900 /*
10901 * See if the config requires any additional preparation, e.g.
10902 * to adjust global state with pipes off. We need to do this
10903 * here so we can get the modeset_pipe updated config for the new
10904 * mode set on this crtc. For other crtcs we need to use the
10905 * adjusted_mode bits in the crtc directly.
10906 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010907 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010908 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010909
Ville Syrjäläc164f832013-11-05 22:34:12 +020010910 /* may have added more to prepare_pipes than we should */
10911 prepare_pipes &= ~disable_pipes;
10912 }
10913
Daniel Vetter460da9162013-03-27 00:44:51 +010010914 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10915 intel_crtc_disable(&intel_crtc->base);
10916
Daniel Vetterea9d7582012-07-10 10:42:52 +020010917 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10918 if (intel_crtc->base.enabled)
10919 dev_priv->display.crtc_disable(&intel_crtc->base);
10920 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010921
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010922 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10923 * to set it here already despite that we pass it down the callchain.
10924 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010925 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010926 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010927 /* mode_set/enable/disable functions rely on a correct pipe
10928 * config. */
10929 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010930 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010931
10932 /*
10933 * Calculate and store various constants which
10934 * are later needed by vblank and swap-completion
10935 * timestamping. They are derived from true hwmode.
10936 */
10937 drm_calc_timestamping_constants(crtc,
10938 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010939 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010940
Daniel Vetterea9d7582012-07-10 10:42:52 +020010941 /* Only after disabling all output pipelines that will be changed can we
10942 * update the the output configuration. */
10943 intel_modeset_update_state(dev, prepare_pipes);
10944
Daniel Vetter47fab732012-10-26 10:58:18 +020010945 if (dev_priv->display.modeset_global_resources)
10946 dev_priv->display.modeset_global_resources(dev);
10947
Daniel Vettera6778b32012-07-02 09:56:42 +020010948 /* Set up the DPLL and any encoders state that needs to adjust or depend
10949 * on the DPLL.
10950 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010951 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070010952 struct drm_framebuffer *old_fb = crtc->primary->fb;
10953 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10954 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Daniel Vetter4c107942014-04-24 23:55:05 +020010955
10956 mutex_lock(&dev->struct_mutex);
10957 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vettera071fa02014-06-18 23:28:09 +020010958 obj,
Daniel Vetter4c107942014-04-24 23:55:05 +020010959 NULL);
10960 if (ret != 0) {
10961 DRM_ERROR("pin & fence failed\n");
10962 mutex_unlock(&dev->struct_mutex);
10963 goto done;
10964 }
Matt Roper2ff8fde2014-07-08 07:50:07 -070010965 if (old_fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020010966 intel_unpin_fb_obj(old_obj);
Daniel Vettera071fa02014-06-18 23:28:09 +020010967 i915_gem_track_fb(old_obj, obj,
10968 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Daniel Vetter4c107942014-04-24 23:55:05 +020010969 mutex_unlock(&dev->struct_mutex);
10970
10971 crtc->primary->fb = fb;
10972 crtc->x = x;
10973 crtc->y = y;
10974
Daniel Vetter4271b752014-04-24 23:55:00 +020010975 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10976 x, y, fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010977 if (ret)
10978 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +020010979 }
10980
10981 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030010982 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10983 update_scanline_offset(intel_crtc);
10984
Daniel Vetter25c5b262012-07-08 22:08:04 +020010985 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030010986 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010987
Daniel Vettera6778b32012-07-02 09:56:42 +020010988 /* FIXME: add subpixel order */
10989done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010990 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070010991 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010992
Tim Gardner3ac18232012-12-07 07:54:26 -070010993out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010994 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070010995 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020010996 return ret;
10997}
10998
Damien Lespiaue7457a92013-08-08 22:28:59 +010010999static int intel_set_mode(struct drm_crtc *crtc,
11000 struct drm_display_mode *mode,
11001 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020011002{
11003 int ret;
11004
11005 ret = __intel_set_mode(crtc, mode, x, y, fb);
11006
11007 if (ret == 0)
11008 intel_modeset_check_state(crtc->dev);
11009
11010 return ret;
11011}
11012
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011013void intel_crtc_restore_mode(struct drm_crtc *crtc)
11014{
Matt Roperf4510a22014-04-01 15:22:40 -070011015 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011016}
11017
Daniel Vetter25c5b262012-07-08 22:08:04 +020011018#undef for_each_intel_crtc_masked
11019
Daniel Vetterd9e55602012-07-04 22:16:09 +020011020static void intel_set_config_free(struct intel_set_config *config)
11021{
11022 if (!config)
11023 return;
11024
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011025 kfree(config->save_connector_encoders);
11026 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020011027 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020011028 kfree(config);
11029}
11030
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011031static int intel_set_config_save_state(struct drm_device *dev,
11032 struct intel_set_config *config)
11033{
Ville Syrjälä76688512014-01-10 11:28:06 +020011034 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011035 struct drm_encoder *encoder;
11036 struct drm_connector *connector;
11037 int count;
11038
Ville Syrjälä76688512014-01-10 11:28:06 +020011039 config->save_crtc_enabled =
11040 kcalloc(dev->mode_config.num_crtc,
11041 sizeof(bool), GFP_KERNEL);
11042 if (!config->save_crtc_enabled)
11043 return -ENOMEM;
11044
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011045 config->save_encoder_crtcs =
11046 kcalloc(dev->mode_config.num_encoder,
11047 sizeof(struct drm_crtc *), GFP_KERNEL);
11048 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011049 return -ENOMEM;
11050
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011051 config->save_connector_encoders =
11052 kcalloc(dev->mode_config.num_connector,
11053 sizeof(struct drm_encoder *), GFP_KERNEL);
11054 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011055 return -ENOMEM;
11056
11057 /* Copy data. Note that driver private data is not affected.
11058 * Should anything bad happen only the expected state is
11059 * restored, not the drivers personal bookkeeping.
11060 */
11061 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010011062 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011063 config->save_crtc_enabled[count++] = crtc->enabled;
11064 }
11065
11066 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011067 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011068 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011069 }
11070
11071 count = 0;
11072 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011073 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011074 }
11075
11076 return 0;
11077}
11078
11079static void intel_set_config_restore_state(struct drm_device *dev,
11080 struct intel_set_config *config)
11081{
Ville Syrjälä76688512014-01-10 11:28:06 +020011082 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020011083 struct intel_encoder *encoder;
11084 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011085 int count;
11086
11087 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011088 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011089 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011090
11091 if (crtc->new_enabled)
11092 crtc->new_config = &crtc->config;
11093 else
11094 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011095 }
11096
11097 count = 0;
Damien Lespiaub2784e12014-08-05 11:29:37 +010011098 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011099 encoder->new_crtc =
11100 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011101 }
11102
11103 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011104 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11105 connector->new_encoder =
11106 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011107 }
11108}
11109
Imre Deake3de42b2013-05-03 19:44:07 +020011110static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010011111is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020011112{
11113 int i;
11114
Chris Wilson2e57f472013-07-17 12:14:40 +010011115 if (set->num_connectors == 0)
11116 return false;
11117
11118 if (WARN_ON(set->connectors == NULL))
11119 return false;
11120
11121 for (i = 0; i < set->num_connectors; i++)
11122 if (set->connectors[i]->encoder &&
11123 set->connectors[i]->encoder->crtc == set->crtc &&
11124 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020011125 return true;
11126
11127 return false;
11128}
11129
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011130static void
11131intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11132 struct intel_set_config *config)
11133{
11134
11135 /* We should be able to check here if the fb has the same properties
11136 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010011137 if (is_crtc_connector_off(set)) {
11138 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070011139 } else if (set->crtc->primary->fb != set->fb) {
Matt Roper3b150f02014-05-29 08:06:53 -070011140 /*
11141 * If we have no fb, we can only flip as long as the crtc is
11142 * active, otherwise we need a full mode set. The crtc may
11143 * be active if we've only disabled the primary plane, or
11144 * in fastboot situations.
11145 */
Matt Roperf4510a22014-04-01 15:22:40 -070011146 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011147 struct intel_crtc *intel_crtc =
11148 to_intel_crtc(set->crtc);
11149
Matt Roper3b150f02014-05-29 08:06:53 -070011150 if (intel_crtc->active) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011151 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11152 config->fb_changed = true;
11153 } else {
11154 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11155 config->mode_changed = true;
11156 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011157 } else if (set->fb == NULL) {
11158 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010011159 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070011160 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011161 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011162 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011163 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011164 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011165 }
11166
Daniel Vetter835c5872012-07-10 18:11:08 +020011167 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011168 config->fb_changed = true;
11169
11170 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11171 DRM_DEBUG_KMS("modes are different, full mode set\n");
11172 drm_mode_debug_printmodeline(&set->crtc->mode);
11173 drm_mode_debug_printmodeline(set->mode);
11174 config->mode_changed = true;
11175 }
Chris Wilsona1d95702013-08-13 18:48:47 +010011176
11177 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11178 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011179}
11180
Daniel Vetter2e431052012-07-04 22:42:15 +020011181static int
Daniel Vetter9a935852012-07-05 22:34:27 +020011182intel_modeset_stage_output_state(struct drm_device *dev,
11183 struct drm_mode_set *set,
11184 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020011185{
Daniel Vetter9a935852012-07-05 22:34:27 +020011186 struct intel_connector *connector;
11187 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020011188 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030011189 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020011190
Damien Lespiau9abdda72013-02-13 13:29:23 +000011191 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020011192 * of connectors. For paranoia, double-check this. */
11193 WARN_ON(!set->fb && (set->num_connectors != 0));
11194 WARN_ON(set->fb && (set->num_connectors == 0));
11195
Daniel Vetter9a935852012-07-05 22:34:27 +020011196 list_for_each_entry(connector, &dev->mode_config.connector_list,
11197 base.head) {
11198 /* Otherwise traverse passed in connector list and get encoders
11199 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020011200 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011201 if (set->connectors[ro] == &connector->base) {
Dave Airlie0e32b392014-05-02 14:02:48 +100011202 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
Daniel Vetter50f56112012-07-02 09:35:43 +020011203 break;
11204 }
11205 }
11206
Daniel Vetter9a935852012-07-05 22:34:27 +020011207 /* If we disable the crtc, disable all its connectors. Also, if
11208 * the connector is on the changing crtc but not on the new
11209 * connector list, disable it. */
11210 if ((!set->fb || ro == set->num_connectors) &&
11211 connector->base.encoder &&
11212 connector->base.encoder->crtc == set->crtc) {
11213 connector->new_encoder = NULL;
11214
11215 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11216 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011217 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020011218 }
11219
11220
11221 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011222 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011223 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011224 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011225 }
11226 /* connector->new_encoder is now updated for all connectors. */
11227
11228 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020011229 list_for_each_entry(connector, &dev->mode_config.connector_list,
11230 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011231 struct drm_crtc *new_crtc;
11232
Daniel Vetter9a935852012-07-05 22:34:27 +020011233 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020011234 continue;
11235
Daniel Vetter9a935852012-07-05 22:34:27 +020011236 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020011237
11238 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011239 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020011240 new_crtc = set->crtc;
11241 }
11242
11243 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010011244 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11245 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011246 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020011247 }
Dave Airlie0e32b392014-05-02 14:02:48 +100011248 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
Daniel Vetter9a935852012-07-05 22:34:27 +020011249
11250 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11251 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011252 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020011253 new_crtc->base.id);
11254 }
11255
11256 /* Check for any encoders that needs to be disabled. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010011257 for_each_intel_encoder(dev, encoder) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011258 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011259 list_for_each_entry(connector,
11260 &dev->mode_config.connector_list,
11261 base.head) {
11262 if (connector->new_encoder == encoder) {
11263 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011264 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020011265 }
11266 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011267
11268 if (num_connectors == 0)
11269 encoder->new_crtc = NULL;
11270 else if (num_connectors > 1)
11271 return -EINVAL;
11272
Daniel Vetter9a935852012-07-05 22:34:27 +020011273 /* Only now check for crtc changes so we don't miss encoders
11274 * that will be disabled. */
11275 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011276 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011277 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011278 }
11279 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011280 /* Now we've also updated encoder->new_crtc for all encoders. */
Dave Airlie0e32b392014-05-02 14:02:48 +100011281 list_for_each_entry(connector, &dev->mode_config.connector_list,
11282 base.head) {
11283 if (connector->new_encoder)
11284 if (connector->new_encoder != connector->encoder)
11285 connector->encoder = connector->new_encoder;
11286 }
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011287 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011288 crtc->new_enabled = false;
11289
Damien Lespiaub2784e12014-08-05 11:29:37 +010011290 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011291 if (encoder->new_crtc == crtc) {
11292 crtc->new_enabled = true;
11293 break;
11294 }
11295 }
11296
11297 if (crtc->new_enabled != crtc->base.enabled) {
11298 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11299 crtc->new_enabled ? "en" : "dis");
11300 config->mode_changed = true;
11301 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011302
11303 if (crtc->new_enabled)
11304 crtc->new_config = &crtc->config;
11305 else
11306 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011307 }
11308
Daniel Vetter2e431052012-07-04 22:42:15 +020011309 return 0;
11310}
11311
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011312static void disable_crtc_nofb(struct intel_crtc *crtc)
11313{
11314 struct drm_device *dev = crtc->base.dev;
11315 struct intel_encoder *encoder;
11316 struct intel_connector *connector;
11317
11318 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11319 pipe_name(crtc->pipe));
11320
11321 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11322 if (connector->new_encoder &&
11323 connector->new_encoder->new_crtc == crtc)
11324 connector->new_encoder = NULL;
11325 }
11326
Damien Lespiaub2784e12014-08-05 11:29:37 +010011327 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011328 if (encoder->new_crtc == crtc)
11329 encoder->new_crtc = NULL;
11330 }
11331
11332 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011333 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011334}
11335
Daniel Vetter2e431052012-07-04 22:42:15 +020011336static int intel_crtc_set_config(struct drm_mode_set *set)
11337{
11338 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020011339 struct drm_mode_set save_set;
11340 struct intel_set_config *config;
11341 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020011342
Daniel Vetter8d3e3752012-07-05 16:09:09 +020011343 BUG_ON(!set);
11344 BUG_ON(!set->crtc);
11345 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020011346
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010011347 /* Enforce sane interface api - has been abused by the fb helper. */
11348 BUG_ON(!set->mode && set->fb);
11349 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020011350
Daniel Vetter2e431052012-07-04 22:42:15 +020011351 if (set->fb) {
11352 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11353 set->crtc->base.id, set->fb->base.id,
11354 (int)set->num_connectors, set->x, set->y);
11355 } else {
11356 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020011357 }
11358
11359 dev = set->crtc->dev;
11360
11361 ret = -ENOMEM;
11362 config = kzalloc(sizeof(*config), GFP_KERNEL);
11363 if (!config)
11364 goto out_config;
11365
11366 ret = intel_set_config_save_state(dev, config);
11367 if (ret)
11368 goto out_config;
11369
11370 save_set.crtc = set->crtc;
11371 save_set.mode = &set->crtc->mode;
11372 save_set.x = set->crtc->x;
11373 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070011374 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020011375
11376 /* Compute whether we need a full modeset, only an fb base update or no
11377 * change at all. In the future we might also check whether only the
11378 * mode changed, e.g. for LVDS where we only change the panel fitter in
11379 * such cases. */
11380 intel_set_config_compute_mode_changes(set, config);
11381
Daniel Vetter9a935852012-07-05 22:34:27 +020011382 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020011383 if (ret)
11384 goto fail;
11385
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011386 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011387 ret = intel_set_mode(set->crtc, set->mode,
11388 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011389 } else if (config->fb_changed) {
Matt Roper3b150f02014-05-29 08:06:53 -070011390 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11391
Ville Syrjälä4878cae2013-02-18 19:08:48 +020011392 intel_crtc_wait_for_pending_flips(set->crtc);
11393
Daniel Vetter4f660f42012-07-02 09:47:37 +020011394 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020011395 set->x, set->y, set->fb);
Matt Roper3b150f02014-05-29 08:06:53 -070011396
11397 /*
11398 * We need to make sure the primary plane is re-enabled if it
11399 * has previously been turned off.
11400 */
11401 if (!intel_crtc->primary_enabled && ret == 0) {
11402 WARN_ON(!intel_crtc->active);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011403 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
Matt Roper3b150f02014-05-29 08:06:53 -070011404 }
11405
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011406 /*
11407 * In the fastboot case this may be our only check of the
11408 * state after boot. It would be better to only do it on
11409 * the first update, but we don't have a nice way of doing that
11410 * (and really, set_config isn't used much for high freq page
11411 * flipping, so increasing its cost here shouldn't be a big
11412 * deal).
11413 */
Jani Nikulad330a952014-01-21 11:24:25 +020011414 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011415 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020011416 }
11417
Chris Wilson2d05eae2013-05-03 17:36:25 +010011418 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020011419 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11420 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020011421fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010011422 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011423
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011424 /*
11425 * HACK: if the pipe was on, but we didn't have a framebuffer,
11426 * force the pipe off to avoid oopsing in the modeset code
11427 * due to fb==NULL. This should only happen during boot since
11428 * we don't yet reconstruct the FB from the hardware state.
11429 */
11430 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11431 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11432
Chris Wilson2d05eae2013-05-03 17:36:25 +010011433 /* Try to restore the config */
11434 if (config->mode_changed &&
11435 intel_set_mode(save_set.crtc, save_set.mode,
11436 save_set.x, save_set.y, save_set.fb))
11437 DRM_ERROR("failed to restore config after modeset failure\n");
11438 }
Daniel Vetter50f56112012-07-02 09:35:43 +020011439
Daniel Vetterd9e55602012-07-04 22:16:09 +020011440out_config:
11441 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011442 return ret;
11443}
11444
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011445static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011446 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020011447 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011448 .destroy = intel_crtc_destroy,
11449 .page_flip = intel_crtc_page_flip,
11450};
11451
Daniel Vetter53589012013-06-05 13:34:16 +020011452static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11453 struct intel_shared_dpll *pll,
11454 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011455{
Daniel Vetter53589012013-06-05 13:34:16 +020011456 uint32_t val;
11457
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030011458 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11459 return false;
11460
Daniel Vetter53589012013-06-05 13:34:16 +020011461 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020011462 hw_state->dpll = val;
11463 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11464 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020011465
11466 return val & DPLL_VCO_ENABLE;
11467}
11468
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011469static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11470 struct intel_shared_dpll *pll)
11471{
11472 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11473 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11474}
11475
Daniel Vettere7b903d2013-06-05 13:34:14 +020011476static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11477 struct intel_shared_dpll *pll)
11478{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011479 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020011480 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020011481
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011482 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11483
11484 /* Wait for the clocks to stabilize. */
11485 POSTING_READ(PCH_DPLL(pll->id));
11486 udelay(150);
11487
11488 /* The pixel multiplier can only be updated once the
11489 * DPLL is enabled and the clocks are stable.
11490 *
11491 * So write it again.
11492 */
11493 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11494 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011495 udelay(200);
11496}
11497
11498static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11499 struct intel_shared_dpll *pll)
11500{
11501 struct drm_device *dev = dev_priv->dev;
11502 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011503
11504 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011505 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020011506 if (intel_crtc_to_shared_dpll(crtc) == pll)
11507 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11508 }
11509
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011510 I915_WRITE(PCH_DPLL(pll->id), 0);
11511 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011512 udelay(200);
11513}
11514
Daniel Vetter46edb022013-06-05 13:34:12 +020011515static char *ibx_pch_dpll_names[] = {
11516 "PCH DPLL A",
11517 "PCH DPLL B",
11518};
11519
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011520static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011521{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011522 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011523 int i;
11524
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011525 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011526
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011527 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020011528 dev_priv->shared_dplls[i].id = i;
11529 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011530 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011531 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11532 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020011533 dev_priv->shared_dplls[i].get_hw_state =
11534 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011535 }
11536}
11537
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011538static void intel_shared_dpll_init(struct drm_device *dev)
11539{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011540 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011541
Daniel Vetter9cd86932014-06-25 22:01:57 +030011542 if (HAS_DDI(dev))
11543 intel_ddi_pll_init(dev);
11544 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011545 ibx_pch_dpll_init(dev);
11546 else
11547 dev_priv->num_shared_dpll = 0;
11548
11549 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011550}
11551
Matt Roper465c1202014-05-29 08:06:54 -070011552static int
11553intel_primary_plane_disable(struct drm_plane *plane)
11554{
11555 struct drm_device *dev = plane->dev;
Matt Roper465c1202014-05-29 08:06:54 -070011556 struct intel_crtc *intel_crtc;
11557
11558 if (!plane->fb)
11559 return 0;
11560
11561 BUG_ON(!plane->crtc);
11562
11563 intel_crtc = to_intel_crtc(plane->crtc);
11564
11565 /*
11566 * Even though we checked plane->fb above, it's still possible that
11567 * the primary plane has been implicitly disabled because the crtc
11568 * coordinates given weren't visible, or because we detected
11569 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11570 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11571 * In either case, we need to unpin the FB and let the fb pointer get
11572 * updated, but otherwise we don't need to touch the hardware.
11573 */
11574 if (!intel_crtc->primary_enabled)
11575 goto disable_unpin;
11576
11577 intel_crtc_wait_for_pending_flips(plane->crtc);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011578 intel_disable_primary_hw_plane(plane, plane->crtc);
11579
Matt Roper465c1202014-05-29 08:06:54 -070011580disable_unpin:
Matt Roper4c345742014-07-09 16:22:10 -070011581 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011582 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
Daniel Vettera071fa02014-06-18 23:28:09 +020011583 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper2ff8fde2014-07-08 07:50:07 -070011584 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
Matt Roper4c345742014-07-09 16:22:10 -070011585 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011586 plane->fb = NULL;
11587
11588 return 0;
11589}
11590
11591static int
11592intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11593 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11594 unsigned int crtc_w, unsigned int crtc_h,
11595 uint32_t src_x, uint32_t src_y,
11596 uint32_t src_w, uint32_t src_h)
11597{
11598 struct drm_device *dev = crtc->dev;
Sonika Jindal48404c12014-08-22 14:06:04 +053011599 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper465c1202014-05-29 08:06:54 -070011600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011601 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11602 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
Matt Roper465c1202014-05-29 08:06:54 -070011603 struct drm_rect dest = {
11604 /* integer pixels */
11605 .x1 = crtc_x,
11606 .y1 = crtc_y,
11607 .x2 = crtc_x + crtc_w,
11608 .y2 = crtc_y + crtc_h,
11609 };
11610 struct drm_rect src = {
11611 /* 16.16 fixed point */
11612 .x1 = src_x,
11613 .y1 = src_y,
11614 .x2 = src_x + src_w,
11615 .y2 = src_y + src_h,
11616 };
11617 const struct drm_rect clip = {
11618 /* integer pixels */
11619 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11620 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11621 };
Sonika Jindalce54d852014-08-21 11:44:39 +053011622 const struct {
11623 int crtc_x, crtc_y;
11624 unsigned int crtc_w, crtc_h;
11625 uint32_t src_x, src_y, src_w, src_h;
11626 } orig = {
11627 .crtc_x = crtc_x,
11628 .crtc_y = crtc_y,
11629 .crtc_w = crtc_w,
11630 .crtc_h = crtc_h,
11631 .src_x = src_x,
11632 .src_y = src_y,
11633 .src_w = src_w,
11634 .src_h = src_h,
11635 };
11636 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper465c1202014-05-29 08:06:54 -070011637 bool visible;
11638 int ret;
11639
11640 ret = drm_plane_helper_check_update(plane, crtc, fb,
11641 &src, &dest, &clip,
11642 DRM_PLANE_HELPER_NO_SCALING,
11643 DRM_PLANE_HELPER_NO_SCALING,
11644 false, true, &visible);
11645
11646 if (ret)
11647 return ret;
11648
11649 /*
11650 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11651 * updating the fb pointer, and returning without touching the
11652 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11653 * turn on the display with all planes setup as desired.
11654 */
11655 if (!crtc->enabled) {
Matt Roper4c345742014-07-09 16:22:10 -070011656 mutex_lock(&dev->struct_mutex);
11657
Matt Roper465c1202014-05-29 08:06:54 -070011658 /*
11659 * If we already called setplane while the crtc was disabled,
11660 * we may have an fb pinned; unpin it.
11661 */
11662 if (plane->fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011663 intel_unpin_fb_obj(old_obj);
11664
11665 i915_gem_track_fb(old_obj, obj,
11666 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper465c1202014-05-29 08:06:54 -070011667
11668 /* Pin and return without programming hardware */
Matt Roper4c345742014-07-09 16:22:10 -070011669 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11670 mutex_unlock(&dev->struct_mutex);
11671
11672 return ret;
Matt Roper465c1202014-05-29 08:06:54 -070011673 }
11674
11675 intel_crtc_wait_for_pending_flips(crtc);
11676
11677 /*
11678 * If clipping results in a non-visible primary plane, we'll disable
11679 * the primary plane. Note that this is a bit different than what
11680 * happens if userspace explicitly disables the plane by passing fb=0
11681 * because plane->fb still gets set and pinned.
11682 */
11683 if (!visible) {
Matt Roper4c345742014-07-09 16:22:10 -070011684 mutex_lock(&dev->struct_mutex);
11685
Matt Roper465c1202014-05-29 08:06:54 -070011686 /*
11687 * Try to pin the new fb first so that we can bail out if we
11688 * fail.
11689 */
11690 if (plane->fb != fb) {
Daniel Vettera071fa02014-06-18 23:28:09 +020011691 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
Matt Roper4c345742014-07-09 16:22:10 -070011692 if (ret) {
11693 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011694 return ret;
Matt Roper4c345742014-07-09 16:22:10 -070011695 }
Matt Roper465c1202014-05-29 08:06:54 -070011696 }
11697
Daniel Vettera071fa02014-06-18 23:28:09 +020011698 i915_gem_track_fb(old_obj, obj,
11699 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11700
Matt Roper465c1202014-05-29 08:06:54 -070011701 if (intel_crtc->primary_enabled)
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011702 intel_disable_primary_hw_plane(plane, crtc);
Matt Roper465c1202014-05-29 08:06:54 -070011703
11704
11705 if (plane->fb != fb)
11706 if (plane->fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011707 intel_unpin_fb_obj(old_obj);
Matt Roper465c1202014-05-29 08:06:54 -070011708
Matt Roper4c345742014-07-09 16:22:10 -070011709 mutex_unlock(&dev->struct_mutex);
11710
Sonika Jindalce54d852014-08-21 11:44:39 +053011711 } else {
Sonika Jindal48404c12014-08-22 14:06:04 +053011712 if (intel_crtc && intel_crtc->active &&
11713 intel_crtc->primary_enabled) {
11714 /*
11715 * FBC does not work on some platforms for rotated
11716 * planes, so disable it when rotation is not 0 and
11717 * update it when rotation is set back to 0.
11718 *
11719 * FIXME: This is redundant with the fbc update done in
11720 * the primary plane enable function except that that
11721 * one is done too late. We eventually need to unify
11722 * this.
11723 */
11724 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11725 dev_priv->fbc.plane == intel_crtc->plane &&
11726 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11727 intel_disable_fbc(dev);
11728 }
11729 }
Sonika Jindalce54d852014-08-21 11:44:39 +053011730 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11731 if (ret)
11732 return ret;
11733
11734 if (!intel_crtc->primary_enabled)
11735 intel_enable_primary_hw_plane(plane, crtc);
Matt Roper465c1202014-05-29 08:06:54 -070011736 }
11737
Sonika Jindalce54d852014-08-21 11:44:39 +053011738 intel_plane->crtc_x = orig.crtc_x;
11739 intel_plane->crtc_y = orig.crtc_y;
11740 intel_plane->crtc_w = orig.crtc_w;
11741 intel_plane->crtc_h = orig.crtc_h;
11742 intel_plane->src_x = orig.src_x;
11743 intel_plane->src_y = orig.src_y;
11744 intel_plane->src_w = orig.src_w;
11745 intel_plane->src_h = orig.src_h;
11746 intel_plane->obj = obj;
Matt Roper465c1202014-05-29 08:06:54 -070011747
11748 return 0;
11749}
11750
Matt Roper3d7d6512014-06-10 08:28:13 -070011751/* Common destruction function for both primary and cursor planes */
11752static void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070011753{
11754 struct intel_plane *intel_plane = to_intel_plane(plane);
11755 drm_plane_cleanup(plane);
11756 kfree(intel_plane);
11757}
11758
11759static const struct drm_plane_funcs intel_primary_plane_funcs = {
11760 .update_plane = intel_primary_plane_setplane,
11761 .disable_plane = intel_primary_plane_disable,
Matt Roper3d7d6512014-06-10 08:28:13 -070011762 .destroy = intel_plane_destroy,
Sonika Jindal48404c12014-08-22 14:06:04 +053011763 .set_property = intel_plane_set_property
Matt Roper465c1202014-05-29 08:06:54 -070011764};
11765
11766static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11767 int pipe)
11768{
11769 struct intel_plane *primary;
11770 const uint32_t *intel_primary_formats;
11771 int num_formats;
11772
11773 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11774 if (primary == NULL)
11775 return NULL;
11776
11777 primary->can_scale = false;
11778 primary->max_downscale = 1;
11779 primary->pipe = pipe;
11780 primary->plane = pipe;
Sonika Jindal48404c12014-08-22 14:06:04 +053011781 primary->rotation = BIT(DRM_ROTATE_0);
Matt Roper465c1202014-05-29 08:06:54 -070011782 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11783 primary->plane = !pipe;
11784
11785 if (INTEL_INFO(dev)->gen <= 3) {
11786 intel_primary_formats = intel_primary_formats_gen2;
11787 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11788 } else {
11789 intel_primary_formats = intel_primary_formats_gen4;
11790 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11791 }
11792
11793 drm_universal_plane_init(dev, &primary->base, 0,
11794 &intel_primary_plane_funcs,
11795 intel_primary_formats, num_formats,
11796 DRM_PLANE_TYPE_PRIMARY);
Sonika Jindal48404c12014-08-22 14:06:04 +053011797
11798 if (INTEL_INFO(dev)->gen >= 4) {
11799 if (!dev->mode_config.rotation_property)
11800 dev->mode_config.rotation_property =
11801 drm_mode_create_rotation_property(dev,
11802 BIT(DRM_ROTATE_0) |
11803 BIT(DRM_ROTATE_180));
11804 if (dev->mode_config.rotation_property)
11805 drm_object_attach_property(&primary->base.base,
11806 dev->mode_config.rotation_property,
11807 primary->rotation);
11808 }
11809
Matt Roper465c1202014-05-29 08:06:54 -070011810 return &primary->base;
11811}
11812
Matt Roper3d7d6512014-06-10 08:28:13 -070011813static int
11814intel_cursor_plane_disable(struct drm_plane *plane)
11815{
11816 if (!plane->fb)
11817 return 0;
11818
11819 BUG_ON(!plane->crtc);
11820
11821 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11822}
11823
11824static int
11825intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11826 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11827 unsigned int crtc_w, unsigned int crtc_h,
11828 uint32_t src_x, uint32_t src_y,
11829 uint32_t src_w, uint32_t src_h)
11830{
11831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11832 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11833 struct drm_i915_gem_object *obj = intel_fb->obj;
11834 struct drm_rect dest = {
11835 /* integer pixels */
11836 .x1 = crtc_x,
11837 .y1 = crtc_y,
11838 .x2 = crtc_x + crtc_w,
11839 .y2 = crtc_y + crtc_h,
11840 };
11841 struct drm_rect src = {
11842 /* 16.16 fixed point */
11843 .x1 = src_x,
11844 .y1 = src_y,
11845 .x2 = src_x + src_w,
11846 .y2 = src_y + src_h,
11847 };
11848 const struct drm_rect clip = {
11849 /* integer pixels */
Ville Syrjälä1add1432014-08-12 19:39:52 +030011850 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11851 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
Matt Roper3d7d6512014-06-10 08:28:13 -070011852 };
11853 bool visible;
11854 int ret;
11855
11856 ret = drm_plane_helper_check_update(plane, crtc, fb,
11857 &src, &dest, &clip,
11858 DRM_PLANE_HELPER_NO_SCALING,
11859 DRM_PLANE_HELPER_NO_SCALING,
11860 true, true, &visible);
11861 if (ret)
11862 return ret;
11863
11864 crtc->cursor_x = crtc_x;
11865 crtc->cursor_y = crtc_y;
11866 if (fb != crtc->cursor->fb) {
11867 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11868 } else {
11869 intel_crtc_update_cursor(crtc, visible);
Daniel Vetter4ed91092014-08-08 20:27:01 +020011870
11871 intel_frontbuffer_flip(crtc->dev,
11872 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11873
Matt Roper3d7d6512014-06-10 08:28:13 -070011874 return 0;
11875 }
11876}
11877static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11878 .update_plane = intel_cursor_plane_update,
11879 .disable_plane = intel_cursor_plane_disable,
11880 .destroy = intel_plane_destroy,
11881};
11882
11883static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11884 int pipe)
11885{
11886 struct intel_plane *cursor;
11887
11888 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11889 if (cursor == NULL)
11890 return NULL;
11891
11892 cursor->can_scale = false;
11893 cursor->max_downscale = 1;
11894 cursor->pipe = pipe;
11895 cursor->plane = pipe;
11896
11897 drm_universal_plane_init(dev, &cursor->base, 0,
11898 &intel_cursor_plane_funcs,
11899 intel_cursor_formats,
11900 ARRAY_SIZE(intel_cursor_formats),
11901 DRM_PLANE_TYPE_CURSOR);
11902 return &cursor->base;
11903}
11904
Hannes Ederb358d0a2008-12-18 21:18:47 +010011905static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080011906{
Jani Nikulafbee40d2014-03-31 14:27:18 +030011907 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080011908 struct intel_crtc *intel_crtc;
Matt Roper3d7d6512014-06-10 08:28:13 -070011909 struct drm_plane *primary = NULL;
11910 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070011911 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080011912
Daniel Vetter955382f2013-09-19 14:05:45 +020011913 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080011914 if (intel_crtc == NULL)
11915 return;
11916
Matt Roper465c1202014-05-29 08:06:54 -070011917 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011918 if (!primary)
11919 goto fail;
11920
11921 cursor = intel_cursor_plane_create(dev, pipe);
11922 if (!cursor)
11923 goto fail;
11924
Matt Roper465c1202014-05-29 08:06:54 -070011925 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070011926 cursor, &intel_crtc_funcs);
11927 if (ret)
11928 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011929
11930 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080011931 for (i = 0; i < 256; i++) {
11932 intel_crtc->lut_r[i] = i;
11933 intel_crtc->lut_g[i] = i;
11934 intel_crtc->lut_b[i] = i;
11935 }
11936
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011937 /*
11938 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020011939 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011940 */
Jesse Barnes80824002009-09-10 15:28:06 -070011941 intel_crtc->pipe = pipe;
11942 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010011943 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080011944 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010011945 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070011946 }
11947
Chris Wilson4b0e3332014-05-30 16:35:26 +030011948 intel_crtc->cursor_base = ~0;
11949 intel_crtc->cursor_cntl = ~0;
Ville Syrjälädc41c152014-08-13 11:57:05 +030011950 intel_crtc->cursor_size = ~0;
Chris Wilson4b0e3332014-05-30 16:35:26 +030011951
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080011952 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11953 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11954 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11955 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11956
Jesse Barnes79e53942008-11-07 14:24:08 -080011957 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020011958
11959 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011960 return;
11961
11962fail:
11963 if (primary)
11964 drm_plane_cleanup(primary);
11965 if (cursor)
11966 drm_plane_cleanup(cursor);
11967 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080011968}
11969
Jesse Barnes752aa882013-10-31 18:55:49 +020011970enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11971{
11972 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020011973 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020011974
Rob Clark51fd3712013-11-19 12:10:12 -050011975 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020011976
11977 if (!encoder)
11978 return INVALID_PIPE;
11979
11980 return to_intel_crtc(encoder->crtc)->pipe;
11981}
11982
Carl Worth08d7b3d2009-04-29 14:43:54 -070011983int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000011984 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070011985{
Carl Worth08d7b3d2009-04-29 14:43:54 -070011986 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040011987 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020011988 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011989
Daniel Vetter1cff8f62012-04-24 09:55:08 +020011990 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11991 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011992
Rob Clark7707e652014-07-17 23:30:04 -040011993 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Carl Worth08d7b3d2009-04-29 14:43:54 -070011994
Rob Clark7707e652014-07-17 23:30:04 -040011995 if (!drmmode_crtc) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070011996 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030011997 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070011998 }
11999
Rob Clark7707e652014-07-17 23:30:04 -040012000 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020012001 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012002
Daniel Vetterc05422d2009-08-11 16:05:30 +020012003 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012004}
12005
Daniel Vetter66a92782012-07-12 20:08:18 +020012006static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080012007{
Daniel Vetter66a92782012-07-12 20:08:18 +020012008 struct drm_device *dev = encoder->base.dev;
12009 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080012010 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080012011 int entry = 0;
12012
Damien Lespiaub2784e12014-08-05 11:29:37 +010012013 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020012014 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020012015 index_mask |= (1 << entry);
12016
Jesse Barnes79e53942008-11-07 14:24:08 -080012017 entry++;
12018 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010012019
Jesse Barnes79e53942008-11-07 14:24:08 -080012020 return index_mask;
12021}
12022
Chris Wilson4d302442010-12-14 19:21:29 +000012023static bool has_edp_a(struct drm_device *dev)
12024{
12025 struct drm_i915_private *dev_priv = dev->dev_private;
12026
12027 if (!IS_MOBILE(dev))
12028 return false;
12029
12030 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12031 return false;
12032
Damien Lespiaue3589902014-02-07 19:12:50 +000012033 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000012034 return false;
12035
12036 return true;
12037}
12038
Damien Lespiauba0fbca2014-01-08 14:18:23 +000012039const char *intel_output_name(int output)
12040{
12041 static const char *names[] = {
12042 [INTEL_OUTPUT_UNUSED] = "Unused",
12043 [INTEL_OUTPUT_ANALOG] = "Analog",
12044 [INTEL_OUTPUT_DVO] = "DVO",
12045 [INTEL_OUTPUT_SDVO] = "SDVO",
12046 [INTEL_OUTPUT_LVDS] = "LVDS",
12047 [INTEL_OUTPUT_TVOUT] = "TV",
12048 [INTEL_OUTPUT_HDMI] = "HDMI",
12049 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12050 [INTEL_OUTPUT_EDP] = "eDP",
12051 [INTEL_OUTPUT_DSI] = "DSI",
12052 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12053 };
12054
12055 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12056 return "Invalid";
12057
12058 return names[output];
12059}
12060
Jesse Barnes84b4e042014-06-25 08:24:29 -070012061static bool intel_crt_present(struct drm_device *dev)
12062{
12063 struct drm_i915_private *dev_priv = dev->dev_private;
12064
12065 if (IS_ULT(dev))
12066 return false;
12067
12068 if (IS_CHERRYVIEW(dev))
12069 return false;
12070
12071 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12072 return false;
12073
12074 return true;
12075}
12076
Jesse Barnes79e53942008-11-07 14:24:08 -080012077static void intel_setup_outputs(struct drm_device *dev)
12078{
Eric Anholt725e30a2009-01-22 13:01:02 -080012079 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010012080 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012081 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080012082
Daniel Vetterc9093352013-06-06 22:22:47 +020012083 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012084
Jesse Barnes84b4e042014-06-25 08:24:29 -070012085 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020012086 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012087
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012088 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030012089 int found;
12090
12091 /* Haswell uses DDI functions to detect digital outputs */
12092 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12093 /* DDI A only supports eDP */
12094 if (found)
12095 intel_ddi_init(dev, PORT_A);
12096
12097 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12098 * register */
12099 found = I915_READ(SFUSE_STRAP);
12100
12101 if (found & SFUSE_STRAP_DDIB_DETECTED)
12102 intel_ddi_init(dev, PORT_B);
12103 if (found & SFUSE_STRAP_DDIC_DETECTED)
12104 intel_ddi_init(dev, PORT_C);
12105 if (found & SFUSE_STRAP_DDID_DETECTED)
12106 intel_ddi_init(dev, PORT_D);
12107 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012108 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012109 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020012110
12111 if (has_edp_a(dev))
12112 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012113
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012114 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080012115 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010012116 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012117 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012118 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012119 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012120 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012121 }
12122
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012123 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012124 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012125
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012126 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012127 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012128
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012129 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012130 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012131
Daniel Vetter270b3042012-10-27 15:52:05 +020012132 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012133 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070012134 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012135 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12136 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12137 PORT_B);
12138 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12139 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12140 }
12141
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012142 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12143 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12144 PORT_C);
12145 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012146 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012147 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053012148
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012149 if (IS_CHERRYVIEW(dev)) {
12150 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12151 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12152 PORT_D);
12153 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12154 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12155 }
12156 }
12157
Jani Nikula3cfca972013-08-27 15:12:26 +030012158 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080012159 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012160 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080012161
Paulo Zanonie2debe92013-02-18 19:00:27 -030012162 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012163 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012164 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012165 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12166 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012167 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012168 }
Ma Ling27185ae2009-08-24 13:50:23 +080012169
Imre Deake7281ea2013-05-08 13:14:08 +030012170 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012171 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080012172 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012173
12174 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012175
Paulo Zanonie2debe92013-02-18 19:00:27 -030012176 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012177 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012178 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012179 }
Ma Ling27185ae2009-08-24 13:50:23 +080012180
Paulo Zanonie2debe92013-02-18 19:00:27 -030012181 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012182
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012183 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12184 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012185 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012186 }
Imre Deake7281ea2013-05-08 13:14:08 +030012187 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012188 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080012189 }
Ma Ling27185ae2009-08-24 13:50:23 +080012190
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012191 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030012192 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012193 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070012194 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012195 intel_dvo_init(dev);
12196
Zhenyu Wang103a1962009-11-27 11:44:36 +080012197 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012198 intel_tv_init(dev);
12199
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070012200 intel_edp_psr_init(dev);
12201
Damien Lespiaub2784e12014-08-05 11:29:37 +010012202 for_each_intel_encoder(dev, encoder) {
Chris Wilson4ef69c72010-09-09 15:14:28 +010012203 encoder->base.possible_crtcs = encoder->crtc_mask;
12204 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020012205 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080012206 }
Chris Wilson47356eb2011-01-11 17:06:04 +000012207
Paulo Zanonidde86e22012-12-01 12:04:25 -020012208 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020012209
12210 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012211}
12212
12213static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12214{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012215 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080012216 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080012217
Daniel Vetteref2d6332014-02-10 18:00:38 +010012218 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012219 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010012220 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012221 drm_gem_object_unreference(&intel_fb->obj->base);
12222 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012223 kfree(intel_fb);
12224}
12225
12226static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000012227 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080012228 unsigned int *handle)
12229{
12230 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000012231 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012232
Chris Wilson05394f32010-11-08 19:18:58 +000012233 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080012234}
12235
12236static const struct drm_framebuffer_funcs intel_fb_funcs = {
12237 .destroy = intel_user_framebuffer_destroy,
12238 .create_handle = intel_user_framebuffer_create_handle,
12239};
12240
Daniel Vetterb5ea6422014-03-02 21:18:00 +010012241static int intel_framebuffer_init(struct drm_device *dev,
12242 struct intel_framebuffer *intel_fb,
12243 struct drm_mode_fb_cmd2 *mode_cmd,
12244 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080012245{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012246 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012247 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080012248 int ret;
12249
Daniel Vetterdd4916c2013-10-09 21:23:51 +020012250 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12251
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012252 if (obj->tiling_mode == I915_TILING_Y) {
12253 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010012254 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012255 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012256
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012257 if (mode_cmd->pitches[0] & 63) {
12258 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12259 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010012260 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012261 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012262
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012263 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12264 pitch_limit = 32*1024;
12265 } else if (INTEL_INFO(dev)->gen >= 4) {
12266 if (obj->tiling_mode)
12267 pitch_limit = 16*1024;
12268 else
12269 pitch_limit = 32*1024;
12270 } else if (INTEL_INFO(dev)->gen >= 3) {
12271 if (obj->tiling_mode)
12272 pitch_limit = 8*1024;
12273 else
12274 pitch_limit = 16*1024;
12275 } else
12276 /* XXX DSPC is limited to 4k tiled */
12277 pitch_limit = 8*1024;
12278
12279 if (mode_cmd->pitches[0] > pitch_limit) {
12280 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12281 obj->tiling_mode ? "tiled" : "linear",
12282 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012283 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012284 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012285
12286 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012287 mode_cmd->pitches[0] != obj->stride) {
12288 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12289 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012290 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012291 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012292
Ville Syrjälä57779d02012-10-31 17:50:14 +020012293 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012294 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020012295 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012296 case DRM_FORMAT_RGB565:
12297 case DRM_FORMAT_XRGB8888:
12298 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012299 break;
12300 case DRM_FORMAT_XRGB1555:
12301 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012302 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012303 DRM_DEBUG("unsupported pixel format: %s\n",
12304 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012305 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012306 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020012307 break;
12308 case DRM_FORMAT_XBGR8888:
12309 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012310 case DRM_FORMAT_XRGB2101010:
12311 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012312 case DRM_FORMAT_XBGR2101010:
12313 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012314 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012315 DRM_DEBUG("unsupported pixel format: %s\n",
12316 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012317 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012318 }
Jesse Barnesb5626742011-06-24 12:19:27 -070012319 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020012320 case DRM_FORMAT_YUYV:
12321 case DRM_FORMAT_UYVY:
12322 case DRM_FORMAT_YVYU:
12323 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012324 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012325 DRM_DEBUG("unsupported pixel format: %s\n",
12326 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012327 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012328 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012329 break;
12330 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012331 DRM_DEBUG("unsupported pixel format: %s\n",
12332 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010012333 return -EINVAL;
12334 }
12335
Ville Syrjälä90f9a332012-10-31 17:50:19 +020012336 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12337 if (mode_cmd->offsets[0] != 0)
12338 return -EINVAL;
12339
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012340 aligned_height = intel_align_height(dev, mode_cmd->height,
12341 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020012342 /* FIXME drm helper for size checks (especially planar formats)? */
12343 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12344 return -EINVAL;
12345
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012346 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12347 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020012348 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012349
Jesse Barnes79e53942008-11-07 14:24:08 -080012350 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12351 if (ret) {
12352 DRM_ERROR("framebuffer init failed %d\n", ret);
12353 return ret;
12354 }
12355
Jesse Barnes79e53942008-11-07 14:24:08 -080012356 return 0;
12357}
12358
Jesse Barnes79e53942008-11-07 14:24:08 -080012359static struct drm_framebuffer *
12360intel_user_framebuffer_create(struct drm_device *dev,
12361 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012362 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080012363{
Chris Wilson05394f32010-11-08 19:18:58 +000012364 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012365
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012366 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12367 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000012368 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010012369 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080012370
Chris Wilsond2dff872011-04-19 08:36:26 +010012371 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080012372}
12373
Daniel Vetter4520f532013-10-09 09:18:51 +020012374#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020012375static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020012376{
12377}
12378#endif
12379
Jesse Barnes79e53942008-11-07 14:24:08 -080012380static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080012381 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020012382 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080012383};
12384
Jesse Barnese70236a2009-09-21 10:42:27 -070012385/* Set up chip specific display functions */
12386static void intel_init_display(struct drm_device *dev)
12387{
12388 struct drm_i915_private *dev_priv = dev->dev_private;
12389
Daniel Vetteree9300b2013-06-03 22:40:22 +020012390 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12391 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030012392 else if (IS_CHERRYVIEW(dev))
12393 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020012394 else if (IS_VALLEYVIEW(dev))
12395 dev_priv->display.find_dpll = vlv_find_best_dpll;
12396 else if (IS_PINEVIEW(dev))
12397 dev_priv->display.find_dpll = pnv_find_best_dpll;
12398 else
12399 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12400
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012401 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012402 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012403 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012404 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020012405 dev_priv->display.crtc_enable = haswell_crtc_enable;
12406 dev_priv->display.crtc_disable = haswell_crtc_disable;
Daniel Vetterdf8ad702014-06-25 22:02:03 +030012407 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012408 dev_priv->display.update_primary_plane =
12409 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012410 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012411 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012412 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070012413 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012414 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12415 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012416 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012417 dev_priv->display.update_primary_plane =
12418 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012419 } else if (IS_VALLEYVIEW(dev)) {
12420 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012421 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012422 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12423 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12424 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12425 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012426 dev_priv->display.update_primary_plane =
12427 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012428 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012429 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012430 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070012431 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012432 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12433 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012434 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012435 dev_priv->display.update_primary_plane =
12436 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012437 }
Jesse Barnese70236a2009-09-21 10:42:27 -070012438
Jesse Barnese70236a2009-09-21 10:42:27 -070012439 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070012440 if (IS_VALLEYVIEW(dev))
12441 dev_priv->display.get_display_clock_speed =
12442 valleyview_get_display_clock_speed;
12443 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070012444 dev_priv->display.get_display_clock_speed =
12445 i945_get_display_clock_speed;
12446 else if (IS_I915G(dev))
12447 dev_priv->display.get_display_clock_speed =
12448 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012449 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012450 dev_priv->display.get_display_clock_speed =
12451 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012452 else if (IS_PINEVIEW(dev))
12453 dev_priv->display.get_display_clock_speed =
12454 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070012455 else if (IS_I915GM(dev))
12456 dev_priv->display.get_display_clock_speed =
12457 i915gm_get_display_clock_speed;
12458 else if (IS_I865G(dev))
12459 dev_priv->display.get_display_clock_speed =
12460 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020012461 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012462 dev_priv->display.get_display_clock_speed =
12463 i855_get_display_clock_speed;
12464 else /* 852, 830 */
12465 dev_priv->display.get_display_clock_speed =
12466 i830_get_display_clock_speed;
12467
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012468 if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080012469 dev_priv->display.write_eld = g4x_write_eld;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012470 } else if (IS_GEN5(dev)) {
12471 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12472 dev_priv->display.write_eld = ironlake_write_eld;
12473 } else if (IS_GEN6(dev)) {
12474 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12475 dev_priv->display.write_eld = ironlake_write_eld;
12476 dev_priv->display.modeset_global_resources =
12477 snb_modeset_global_resources;
12478 } else if (IS_IVYBRIDGE(dev)) {
12479 /* FIXME: detect B0+ stepping and use auto training */
12480 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12481 dev_priv->display.write_eld = ironlake_write_eld;
12482 dev_priv->display.modeset_global_resources =
12483 ivb_modeset_global_resources;
12484 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12485 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12486 dev_priv->display.write_eld = haswell_write_eld;
12487 dev_priv->display.modeset_global_resources =
12488 haswell_modeset_global_resources;
Jesse Barnes30a970c2013-11-04 13:48:12 -080012489 } else if (IS_VALLEYVIEW(dev)) {
12490 dev_priv->display.modeset_global_resources =
12491 valleyview_modeset_global_resources;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -040012492 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -070012493 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012494
12495 /* Default just returns -ENODEV to indicate unsupported */
12496 dev_priv->display.queue_flip = intel_default_queue_flip;
12497
12498 switch (INTEL_INFO(dev)->gen) {
12499 case 2:
12500 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12501 break;
12502
12503 case 3:
12504 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12505 break;
12506
12507 case 4:
12508 case 5:
12509 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12510 break;
12511
12512 case 6:
12513 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12514 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012515 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012516 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012517 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12518 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012519 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020012520
12521 intel_panel_init_backlight_funcs(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012522}
12523
Jesse Barnesb690e962010-07-19 13:53:12 -070012524/*
12525 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12526 * resume, or other times. This quirk makes sure that's the case for
12527 * affected systems.
12528 */
Akshay Joshi0206e352011-08-16 15:34:10 -040012529static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070012530{
12531 struct drm_i915_private *dev_priv = dev->dev_private;
12532
12533 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012534 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012535}
12536
Keith Packard435793d2011-07-12 14:56:22 -070012537/*
12538 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12539 */
12540static void quirk_ssc_force_disable(struct drm_device *dev)
12541{
12542 struct drm_i915_private *dev_priv = dev->dev_private;
12543 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012544 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070012545}
12546
Carsten Emde4dca20e2012-03-15 15:56:26 +010012547/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010012548 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12549 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010012550 */
12551static void quirk_invert_brightness(struct drm_device *dev)
12552{
12553 struct drm_i915_private *dev_priv = dev->dev_private;
12554 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012555 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012556}
12557
Scot Doyle9c72cc62014-07-03 23:27:50 +000012558/* Some VBT's incorrectly indicate no backlight is present */
12559static void quirk_backlight_present(struct drm_device *dev)
12560{
12561 struct drm_i915_private *dev_priv = dev->dev_private;
12562 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12563 DRM_INFO("applying backlight present quirk\n");
12564}
12565
Jesse Barnesb690e962010-07-19 13:53:12 -070012566struct intel_quirk {
12567 int device;
12568 int subsystem_vendor;
12569 int subsystem_device;
12570 void (*hook)(struct drm_device *dev);
12571};
12572
Egbert Eich5f85f1762012-10-14 15:46:38 +020012573/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12574struct intel_dmi_quirk {
12575 void (*hook)(struct drm_device *dev);
12576 const struct dmi_system_id (*dmi_id_list)[];
12577};
12578
12579static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12580{
12581 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12582 return 1;
12583}
12584
12585static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12586 {
12587 .dmi_id_list = &(const struct dmi_system_id[]) {
12588 {
12589 .callback = intel_dmi_reverse_brightness,
12590 .ident = "NCR Corporation",
12591 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12592 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12593 },
12594 },
12595 { } /* terminating entry */
12596 },
12597 .hook = quirk_invert_brightness,
12598 },
12599};
12600
Ben Widawskyc43b5632012-04-16 14:07:40 -070012601static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070012602 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040012603 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070012604
Jesse Barnesb690e962010-07-19 13:53:12 -070012605 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12606 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12607
Jesse Barnesb690e962010-07-19 13:53:12 -070012608 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12609 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12610
Keith Packard435793d2011-07-12 14:56:22 -070012611 /* Lenovo U160 cannot use SSC on LVDS */
12612 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020012613
12614 /* Sony Vaio Y cannot use SSC on LVDS */
12615 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010012616
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010012617 /* Acer Aspire 5734Z must invert backlight brightness */
12618 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12619
12620 /* Acer/eMachines G725 */
12621 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12622
12623 /* Acer/eMachines e725 */
12624 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12625
12626 /* Acer/Packard Bell NCL20 */
12627 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12628
12629 /* Acer Aspire 4736Z */
12630 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020012631
12632 /* Acer Aspire 5336 */
12633 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000012634
12635 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12636 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000012637
12638 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12639 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000012640
12641 /* HP Chromebook 14 (Celeron 2955U) */
12642 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070012643};
12644
12645static void intel_init_quirks(struct drm_device *dev)
12646{
12647 struct pci_dev *d = dev->pdev;
12648 int i;
12649
12650 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12651 struct intel_quirk *q = &intel_quirks[i];
12652
12653 if (d->device == q->device &&
12654 (d->subsystem_vendor == q->subsystem_vendor ||
12655 q->subsystem_vendor == PCI_ANY_ID) &&
12656 (d->subsystem_device == q->subsystem_device ||
12657 q->subsystem_device == PCI_ANY_ID))
12658 q->hook(dev);
12659 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020012660 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12661 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12662 intel_dmi_quirks[i].hook(dev);
12663 }
Jesse Barnesb690e962010-07-19 13:53:12 -070012664}
12665
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012666/* Disable the VGA plane that we never use */
12667static void i915_disable_vga(struct drm_device *dev)
12668{
12669 struct drm_i915_private *dev_priv = dev->dev_private;
12670 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012671 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012672
Ville Syrjälä2b37c612014-01-22 21:32:38 +020012673 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012674 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070012675 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012676 sr1 = inb(VGA_SR_DATA);
12677 outb(sr1 | 1<<5, VGA_SR_DATA);
12678 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12679 udelay(300);
12680
12681 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12682 POSTING_READ(vga_reg);
12683}
12684
Daniel Vetterf8175862012-04-10 15:50:11 +020012685void intel_modeset_init_hw(struct drm_device *dev)
12686{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030012687 intel_prepare_ddi(dev);
12688
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +030012689 if (IS_VALLEYVIEW(dev))
12690 vlv_update_cdclk(dev);
12691
Daniel Vetterf8175862012-04-10 15:50:11 +020012692 intel_init_clock_gating(dev);
12693
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012694 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020012695}
12696
Imre Deak7d708ee2013-04-17 14:04:50 +030012697void intel_modeset_suspend_hw(struct drm_device *dev)
12698{
12699 intel_suspend_hw(dev);
12700}
12701
Jesse Barnes79e53942008-11-07 14:24:08 -080012702void intel_modeset_init(struct drm_device *dev)
12703{
Jesse Barnes652c3932009-08-17 13:31:43 -070012704 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000012705 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012706 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080012707 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080012708
12709 drm_mode_config_init(dev);
12710
12711 dev->mode_config.min_width = 0;
12712 dev->mode_config.min_height = 0;
12713
Dave Airlie019d96c2011-09-29 16:20:42 +010012714 dev->mode_config.preferred_depth = 24;
12715 dev->mode_config.prefer_shadow = 1;
12716
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020012717 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080012718
Jesse Barnesb690e962010-07-19 13:53:12 -070012719 intel_init_quirks(dev);
12720
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030012721 intel_init_pm(dev);
12722
Ben Widawskye3c74752013-04-05 13:12:39 -070012723 if (INTEL_INFO(dev)->num_pipes == 0)
12724 return;
12725
Jesse Barnese70236a2009-09-21 10:42:27 -070012726 intel_init_display(dev);
12727
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012728 if (IS_GEN2(dev)) {
12729 dev->mode_config.max_width = 2048;
12730 dev->mode_config.max_height = 2048;
12731 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070012732 dev->mode_config.max_width = 4096;
12733 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080012734 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012735 dev->mode_config.max_width = 8192;
12736 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080012737 }
Damien Lespiau068be562014-03-28 14:17:49 +000012738
Ville Syrjälädc41c152014-08-13 11:57:05 +030012739 if (IS_845G(dev) || IS_I865G(dev)) {
12740 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12741 dev->mode_config.cursor_height = 1023;
12742 } else if (IS_GEN2(dev)) {
Damien Lespiau068be562014-03-28 14:17:49 +000012743 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12744 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12745 } else {
12746 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12747 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12748 }
12749
Ben Widawsky5d4545a2013-01-17 12:45:15 -080012750 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080012751
Zhao Yakui28c97732009-10-09 11:39:41 +080012752 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012753 INTEL_INFO(dev)->num_pipes,
12754 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080012755
Damien Lespiau055e3932014-08-18 13:49:10 +010012756 for_each_pipe(dev_priv, pipe) {
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012757 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000012758 for_each_sprite(pipe, sprite) {
12759 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012760 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030012761 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000012762 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012763 }
Jesse Barnes79e53942008-11-07 14:24:08 -080012764 }
12765
Jesse Barnesf42bb702013-12-16 16:34:23 -080012766 intel_init_dpio(dev);
12767
Daniel Vettere72f9fb2013-06-05 13:34:06 +020012768 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012769
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012770 /* Just disable it once at startup */
12771 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012772 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000012773
12774 /* Just in case the BIOS is doing something questionable. */
12775 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012776
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012777 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012778 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012779 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012780
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012781 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080012782 if (!crtc->active)
12783 continue;
12784
Jesse Barnes46f297f2014-03-07 08:57:48 -080012785 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080012786 * Note that reserving the BIOS fb up front prevents us
12787 * from stuffing other stolen allocations like the ring
12788 * on top. This prevents some ugliness at boot time, and
12789 * can even allow for smooth boot transitions if the BIOS
12790 * fb is large enough for the active pipe configuration.
12791 */
12792 if (dev_priv->display.get_plane_config) {
12793 dev_priv->display.get_plane_config(crtc,
12794 &crtc->plane_config);
12795 /*
12796 * If the fb is shared between multiple heads, we'll
12797 * just get the first one.
12798 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080012799 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012800 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080012801 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010012802}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080012803
Daniel Vetter7fad7982012-07-04 17:51:47 +020012804static void intel_enable_pipe_a(struct drm_device *dev)
12805{
12806 struct intel_connector *connector;
12807 struct drm_connector *crt = NULL;
12808 struct intel_load_detect_pipe load_detect_temp;
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030012809 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020012810
12811 /* We can't just switch on the pipe A, we need to set things up with a
12812 * proper mode and output configuration. As a gross hack, enable pipe A
12813 * by enabling the load detect pipe once. */
12814 list_for_each_entry(connector,
12815 &dev->mode_config.connector_list,
12816 base.head) {
12817 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12818 crt = &connector->base;
12819 break;
12820 }
12821 }
12822
12823 if (!crt)
12824 return;
12825
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030012826 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12827 intel_release_load_detect_pipe(crt, &load_detect_temp);
Daniel Vetter7fad7982012-07-04 17:51:47 +020012828}
12829
Daniel Vetterfa555832012-10-10 23:14:00 +020012830static bool
12831intel_check_plane_mapping(struct intel_crtc *crtc)
12832{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012833 struct drm_device *dev = crtc->base.dev;
12834 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012835 u32 reg, val;
12836
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012837 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020012838 return true;
12839
12840 reg = DSPCNTR(!crtc->plane);
12841 val = I915_READ(reg);
12842
12843 if ((val & DISPLAY_PLANE_ENABLE) &&
12844 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12845 return false;
12846
12847 return true;
12848}
12849
Daniel Vetter24929352012-07-02 20:28:59 +020012850static void intel_sanitize_crtc(struct intel_crtc *crtc)
12851{
12852 struct drm_device *dev = crtc->base.dev;
12853 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012854 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020012855
Daniel Vetter24929352012-07-02 20:28:59 +020012856 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020012857 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020012858 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12859
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012860 /* restore vblank interrupts to correct state */
12861 if (crtc->active)
12862 drm_vblank_on(dev, crtc->pipe);
12863 else
12864 drm_vblank_off(dev, crtc->pipe);
12865
Daniel Vetter24929352012-07-02 20:28:59 +020012866 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020012867 * disable the crtc (and hence change the state) if it is wrong. Note
12868 * that gen4+ has a fixed plane -> pipe mapping. */
12869 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020012870 struct intel_connector *connector;
12871 bool plane;
12872
Daniel Vetter24929352012-07-02 20:28:59 +020012873 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12874 crtc->base.base.id);
12875
12876 /* Pipe has the wrong plane attached and the plane is active.
12877 * Temporarily change the plane mapping and disable everything
12878 * ... */
12879 plane = crtc->plane;
12880 crtc->plane = !plane;
Daniel Vetter9c8958b2014-07-14 19:35:31 +020012881 crtc->primary_enabled = true;
Daniel Vetter24929352012-07-02 20:28:59 +020012882 dev_priv->display.crtc_disable(&crtc->base);
12883 crtc->plane = plane;
12884
12885 /* ... and break all links. */
12886 list_for_each_entry(connector, &dev->mode_config.connector_list,
12887 base.head) {
12888 if (connector->encoder->base.crtc != &crtc->base)
12889 continue;
12890
Egbert Eich7f1950f2014-04-25 10:56:22 +020012891 connector->base.dpms = DRM_MODE_DPMS_OFF;
12892 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020012893 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020012894 /* multiple connectors may have the same encoder:
12895 * handle them and break crtc link separately */
12896 list_for_each_entry(connector, &dev->mode_config.connector_list,
12897 base.head)
12898 if (connector->encoder->base.crtc == &crtc->base) {
12899 connector->encoder->base.crtc = NULL;
12900 connector->encoder->connectors_active = false;
12901 }
Daniel Vetter24929352012-07-02 20:28:59 +020012902
12903 WARN_ON(crtc->active);
12904 crtc->base.enabled = false;
12905 }
Daniel Vetter24929352012-07-02 20:28:59 +020012906
Daniel Vetter7fad7982012-07-04 17:51:47 +020012907 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12908 crtc->pipe == PIPE_A && !crtc->active) {
12909 /* BIOS forgot to enable pipe A, this mostly happens after
12910 * resume. Force-enable the pipe to fix this, the update_dpms
12911 * call below we restore the pipe to the right state, but leave
12912 * the required bits on. */
12913 intel_enable_pipe_a(dev);
12914 }
12915
Daniel Vetter24929352012-07-02 20:28:59 +020012916 /* Adjust the state of the output pipe according to whether we
12917 * have active connectors/encoders. */
12918 intel_crtc_update_dpms(&crtc->base);
12919
12920 if (crtc->active != crtc->base.enabled) {
12921 struct intel_encoder *encoder;
12922
12923 /* This can happen either due to bugs in the get_hw_state
12924 * functions or because the pipe is force-enabled due to the
12925 * pipe A quirk. */
12926 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12927 crtc->base.base.id,
12928 crtc->base.enabled ? "enabled" : "disabled",
12929 crtc->active ? "enabled" : "disabled");
12930
12931 crtc->base.enabled = crtc->active;
12932
12933 /* Because we only establish the connector -> encoder ->
12934 * crtc links if something is active, this means the
12935 * crtc is now deactivated. Break the links. connector
12936 * -> encoder links are only establish when things are
12937 * actually up, hence no need to break them. */
12938 WARN_ON(crtc->active);
12939
12940 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12941 WARN_ON(encoder->connectors_active);
12942 encoder->base.crtc = NULL;
12943 }
12944 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020012945
12946 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010012947 /*
12948 * We start out with underrun reporting disabled to avoid races.
12949 * For correct bookkeeping mark this on active crtcs.
12950 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020012951 * Also on gmch platforms we dont have any hardware bits to
12952 * disable the underrun reporting. Which means we need to start
12953 * out with underrun reporting disabled also on inactive pipes,
12954 * since otherwise we'll complain about the garbage we read when
12955 * e.g. coming up after runtime pm.
12956 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010012957 * No protection against concurrent access is required - at
12958 * worst a fifo underrun happens which also sets this to false.
12959 */
12960 crtc->cpu_fifo_underrun_disabled = true;
12961 crtc->pch_fifo_underrun_disabled = true;
Ville Syrjälä80715b22014-05-15 20:23:23 +030012962
12963 update_scanline_offset(crtc);
Daniel Vetter4cc31482014-03-24 00:01:41 +010012964 }
Daniel Vetter24929352012-07-02 20:28:59 +020012965}
12966
12967static void intel_sanitize_encoder(struct intel_encoder *encoder)
12968{
12969 struct intel_connector *connector;
12970 struct drm_device *dev = encoder->base.dev;
12971
12972 /* We need to check both for a crtc link (meaning that the
12973 * encoder is active and trying to read from a pipe) and the
12974 * pipe itself being active. */
12975 bool has_active_crtc = encoder->base.crtc &&
12976 to_intel_crtc(encoder->base.crtc)->active;
12977
12978 if (encoder->connectors_active && !has_active_crtc) {
12979 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12980 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012981 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020012982
12983 /* Connector is active, but has no active pipe. This is
12984 * fallout from our resume register restoring. Disable
12985 * the encoder manually again. */
12986 if (encoder->base.crtc) {
12987 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12988 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030012989 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020012990 encoder->disable(encoder);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030012991 if (encoder->post_disable)
12992 encoder->post_disable(encoder);
Daniel Vetter24929352012-07-02 20:28:59 +020012993 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020012994 encoder->base.crtc = NULL;
12995 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020012996
12997 /* Inconsistent output/port/pipe state happens presumably due to
12998 * a bug in one of the get_hw_state functions. Or someplace else
12999 * in our code, like the register restore mess on resume. Clamp
13000 * things to off as a safer default. */
13001 list_for_each_entry(connector,
13002 &dev->mode_config.connector_list,
13003 base.head) {
13004 if (connector->encoder != encoder)
13005 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020013006 connector->base.dpms = DRM_MODE_DPMS_OFF;
13007 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020013008 }
13009 }
13010 /* Enabled encoders without active connectors will be fixed in
13011 * the crtc fixup. */
13012}
13013
Imre Deak04098752014-02-18 00:02:16 +020013014void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013015{
13016 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020013017 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013018
Imre Deak04098752014-02-18 00:02:16 +020013019 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13020 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13021 i915_disable_vga(dev);
13022 }
13023}
13024
13025void i915_redisable_vga(struct drm_device *dev)
13026{
13027 struct drm_i915_private *dev_priv = dev->dev_private;
13028
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013029 /* This function can be called both from intel_modeset_setup_hw_state or
13030 * at a very early point in our resume sequence, where the power well
13031 * structures are not yet restored. Since this function is at a very
13032 * paranoid "someone might have enabled VGA while we were not looking"
13033 * level, just check if the power well is enabled instead of trying to
13034 * follow the "don't touch the power well if we don't need it" policy
13035 * the rest of the driver uses. */
Imre Deak04098752014-02-18 00:02:16 +020013036 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013037 return;
13038
Imre Deak04098752014-02-18 00:02:16 +020013039 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013040}
13041
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013042static bool primary_get_hw_state(struct intel_crtc *crtc)
13043{
13044 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13045
13046 if (!crtc->active)
13047 return false;
13048
13049 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13050}
13051
Daniel Vetter30e984d2013-06-05 13:34:17 +020013052static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020013053{
13054 struct drm_i915_private *dev_priv = dev->dev_private;
13055 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020013056 struct intel_crtc *crtc;
13057 struct intel_encoder *encoder;
13058 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020013059 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020013060
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013061 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010013062 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020013063
Daniel Vetter99535992014-04-13 12:00:33 +020013064 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13065
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013066 crtc->active = dev_priv->display.get_pipe_config(crtc,
13067 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013068
13069 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013070 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020013071
13072 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13073 crtc->base.base.id,
13074 crtc->active ? "enabled" : "disabled");
13075 }
13076
Daniel Vetter53589012013-06-05 13:34:16 +020013077 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13078 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13079
13080 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13081 pll->active = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013082 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020013083 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13084 pll->active++;
13085 }
13086 pll->refcount = pll->active;
13087
Daniel Vetter35c95372013-07-17 06:55:04 +020013088 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13089 pll->name, pll->refcount, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013090
13091 if (pll->refcount)
13092 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020013093 }
13094
Damien Lespiaub2784e12014-08-05 11:29:37 +010013095 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013096 pipe = 0;
13097
13098 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070013099 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13100 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010013101 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013102 } else {
13103 encoder->base.crtc = NULL;
13104 }
13105
13106 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013107 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020013108 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013109 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013110 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013111 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020013112 }
13113
13114 list_for_each_entry(connector, &dev->mode_config.connector_list,
13115 base.head) {
13116 if (connector->get_hw_state(connector)) {
13117 connector->base.dpms = DRM_MODE_DPMS_ON;
13118 connector->encoder->connectors_active = true;
13119 connector->base.encoder = &connector->encoder->base;
13120 } else {
13121 connector->base.dpms = DRM_MODE_DPMS_OFF;
13122 connector->base.encoder = NULL;
13123 }
13124 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13125 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030013126 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013127 connector->base.encoder ? "enabled" : "disabled");
13128 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020013129}
13130
13131/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13132 * and i915 state tracking structures. */
13133void intel_modeset_setup_hw_state(struct drm_device *dev,
13134 bool force_restore)
13135{
13136 struct drm_i915_private *dev_priv = dev->dev_private;
13137 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013138 struct intel_crtc *crtc;
13139 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020013140 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013141
13142 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020013143
Jesse Barnesbabea612013-06-26 18:57:38 +030013144 /*
13145 * Now that we have the config, copy it to each CRTC struct
13146 * Note that this could go away if we move to using crtc_config
13147 * checking everywhere.
13148 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013149 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020013150 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080013151 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030013152 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13153 crtc->base.base.id);
13154 drm_mode_debug_printmodeline(&crtc->base.mode);
13155 }
13156 }
13157
Daniel Vetter24929352012-07-02 20:28:59 +020013158 /* HW state is read out, now we need to sanitize this mess. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010013159 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013160 intel_sanitize_encoder(encoder);
13161 }
13162
Damien Lespiau055e3932014-08-18 13:49:10 +010013163 for_each_pipe(dev_priv, pipe) {
Daniel Vetter24929352012-07-02 20:28:59 +020013164 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13165 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020013166 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020013167 }
Daniel Vetter9a935852012-07-05 22:34:27 +020013168
Daniel Vetter35c95372013-07-17 06:55:04 +020013169 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13170 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13171
13172 if (!pll->on || pll->active)
13173 continue;
13174
13175 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13176
13177 pll->disable(dev_priv, pll);
13178 pll->on = false;
13179 }
13180
Ville Syrjälä96f90c52013-12-05 15:51:38 +020013181 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030013182 ilk_wm_get_hw_state(dev);
13183
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013184 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030013185 i915_redisable_vga(dev);
13186
Daniel Vetterf30da182013-04-11 20:22:50 +020013187 /*
13188 * We need to use raw interfaces for restoring state to avoid
13189 * checking (bogus) intermediate states.
13190 */
Damien Lespiau055e3932014-08-18 13:49:10 +010013191 for_each_pipe(dev_priv, pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070013192 struct drm_crtc *crtc =
13193 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020013194
13195 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
Matt Roperf4510a22014-04-01 15:22:40 -070013196 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013197 }
13198 } else {
13199 intel_modeset_update_staged_output_state(dev);
13200 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013201
13202 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010013203}
13204
13205void intel_modeset_gem_init(struct drm_device *dev)
13206{
Jesse Barnes484b41d2014-03-07 08:57:55 -080013207 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070013208 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013209
Imre Deakae484342014-03-31 15:10:44 +030013210 mutex_lock(&dev->struct_mutex);
13211 intel_init_gt_powersave(dev);
13212 mutex_unlock(&dev->struct_mutex);
13213
Chris Wilson1833b132012-05-09 11:56:28 +010013214 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020013215
13216 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080013217
13218 /*
13219 * Make sure any fbs we allocated at startup are properly
13220 * pinned & fenced. When we do the allocation it's too early
13221 * for this.
13222 */
13223 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010013224 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070013225 obj = intel_fb_obj(c->primary->fb);
13226 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080013227 continue;
13228
Matt Roper2ff8fde2014-07-08 07:50:07 -070013229 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080013230 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13231 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100013232 drm_framebuffer_unreference(c->primary->fb);
13233 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013234 }
13235 }
13236 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013237}
13238
Imre Deak4932e2c2014-02-11 17:12:48 +020013239void intel_connector_unregister(struct intel_connector *intel_connector)
13240{
13241 struct drm_connector *connector = &intel_connector->base;
13242
13243 intel_panel_destroy_backlight(connector);
Thomas Wood34ea3d32014-05-29 16:57:41 +010013244 drm_connector_unregister(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020013245}
13246
Jesse Barnes79e53942008-11-07 14:24:08 -080013247void intel_modeset_cleanup(struct drm_device *dev)
13248{
Jesse Barnes652c3932009-08-17 13:31:43 -070013249 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid9255d52013-09-26 20:05:59 -030013250 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070013251
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013252 /*
13253 * Interrupts and polling as the first thing to avoid creating havoc.
13254 * Too much stuff here (turning of rps, connectors, ...) would
13255 * experience fancy races otherwise.
13256 */
13257 drm_irq_uninstall(dev);
Imre Deak1d0d3432014-08-18 14:42:44 +030013258 intel_hpd_cancel_work(dev_priv);
Jesse Barneseb21b922014-06-20 11:57:33 -070013259 dev_priv->pm._irqs_disabled = true;
13260
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013261 /*
13262 * Due to the hpd irq storm handling the hotplug work can re-arm the
13263 * poll handlers. Hence disable polling after hpd handling is shut down.
13264 */
Keith Packardf87ea762010-10-03 19:36:26 -070013265 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013266
Jesse Barnes652c3932009-08-17 13:31:43 -070013267 mutex_lock(&dev->struct_mutex);
13268
Jesse Barnes723bfd72010-10-07 16:01:13 -070013269 intel_unregister_dsm_handler();
13270
Chris Wilson973d04f2011-07-08 12:22:37 +010013271 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070013272
Daniel Vetter8090c6b2012-06-24 16:42:32 +020013273 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000013274
Daniel Vetter930ebb42012-06-29 23:32:16 +020013275 ironlake_teardown_rc6(dev);
13276
Kristian Høgsberg69341a52009-11-11 12:19:17 -050013277 mutex_unlock(&dev->struct_mutex);
13278
Chris Wilson1630fe72011-07-08 12:22:42 +010013279 /* flush any delayed tasks or pending work */
13280 flush_scheduled_work();
13281
Jani Nikuladb31af12013-11-08 16:48:53 +020013282 /* destroy the backlight and sysfs files before encoders/connectors */
13283 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020013284 struct intel_connector *intel_connector;
13285
13286 intel_connector = to_intel_connector(connector);
13287 intel_connector->unregister(intel_connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020013288 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030013289
Jesse Barnes79e53942008-11-07 14:24:08 -080013290 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010013291
13292 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030013293
13294 mutex_lock(&dev->struct_mutex);
13295 intel_cleanup_gt_powersave(dev);
13296 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013297}
13298
Dave Airlie28d52042009-09-21 14:33:58 +100013299/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080013300 * Return which encoder is currently attached for connector.
13301 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010013302struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080013303{
Chris Wilsondf0e9242010-09-09 16:20:55 +010013304 return &intel_attached_encoder(connector)->base;
13305}
Jesse Barnes79e53942008-11-07 14:24:08 -080013306
Chris Wilsondf0e9242010-09-09 16:20:55 +010013307void intel_connector_attach_encoder(struct intel_connector *connector,
13308 struct intel_encoder *encoder)
13309{
13310 connector->encoder = encoder;
13311 drm_mode_connector_attach_encoder(&connector->base,
13312 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080013313}
Dave Airlie28d52042009-09-21 14:33:58 +100013314
13315/*
13316 * set vga decode state - true == enable VGA decode
13317 */
13318int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13319{
13320 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000013321 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100013322 u16 gmch_ctrl;
13323
Chris Wilson75fa0412014-02-07 18:37:02 -020013324 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13325 DRM_ERROR("failed to read control word\n");
13326 return -EIO;
13327 }
13328
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020013329 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13330 return 0;
13331
Dave Airlie28d52042009-09-21 14:33:58 +100013332 if (state)
13333 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13334 else
13335 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020013336
13337 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13338 DRM_ERROR("failed to write control word\n");
13339 return -EIO;
13340 }
13341
Dave Airlie28d52042009-09-21 14:33:58 +100013342 return 0;
13343}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013344
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013345struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013346
13347 u32 power_well_driver;
13348
Chris Wilson63b66e52013-08-08 15:12:06 +020013349 int num_transcoders;
13350
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013351 struct intel_cursor_error_state {
13352 u32 control;
13353 u32 position;
13354 u32 base;
13355 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010013356 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013357
13358 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013359 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013360 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030013361 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010013362 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013363
13364 struct intel_plane_error_state {
13365 u32 control;
13366 u32 stride;
13367 u32 size;
13368 u32 pos;
13369 u32 addr;
13370 u32 surface;
13371 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010013372 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020013373
13374 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013375 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020013376 enum transcoder cpu_transcoder;
13377
13378 u32 conf;
13379
13380 u32 htotal;
13381 u32 hblank;
13382 u32 hsync;
13383 u32 vtotal;
13384 u32 vblank;
13385 u32 vsync;
13386 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013387};
13388
13389struct intel_display_error_state *
13390intel_display_capture_error_state(struct drm_device *dev)
13391{
Jani Nikulafbee40d2014-03-31 14:27:18 +030013392 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013393 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020013394 int transcoders[] = {
13395 TRANSCODER_A,
13396 TRANSCODER_B,
13397 TRANSCODER_C,
13398 TRANSCODER_EDP,
13399 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013400 int i;
13401
Chris Wilson63b66e52013-08-08 15:12:06 +020013402 if (INTEL_INFO(dev)->num_pipes == 0)
13403 return NULL;
13404
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013405 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013406 if (error == NULL)
13407 return NULL;
13408
Imre Deak190be112013-11-25 17:15:31 +020013409 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013410 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13411
Damien Lespiau055e3932014-08-18 13:49:10 +010013412 for_each_pipe(dev_priv, i) {
Imre Deakddf9c532013-11-27 22:02:02 +020013413 error->pipe[i].power_domain_on =
Imre Deakbfafe932014-06-05 20:31:47 +030013414 intel_display_power_enabled_unlocked(dev_priv,
13415 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020013416 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013417 continue;
13418
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030013419 error->cursor[i].control = I915_READ(CURCNTR(i));
13420 error->cursor[i].position = I915_READ(CURPOS(i));
13421 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013422
13423 error->plane[i].control = I915_READ(DSPCNTR(i));
13424 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013425 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030013426 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013427 error->plane[i].pos = I915_READ(DSPPOS(i));
13428 }
Paulo Zanonica291362013-03-06 20:03:14 -030013429 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13430 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013431 if (INTEL_INFO(dev)->gen >= 4) {
13432 error->plane[i].surface = I915_READ(DSPSURF(i));
13433 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13434 }
13435
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013436 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030013437
Sonika Jindal3abfce72014-07-21 15:23:43 +053013438 if (HAS_GMCH_DISPLAY(dev))
Imre Deakf301b1e2014-04-18 15:55:04 +030013439 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020013440 }
13441
13442 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13443 if (HAS_DDI(dev_priv->dev))
13444 error->num_transcoders++; /* Account for eDP. */
13445
13446 for (i = 0; i < error->num_transcoders; i++) {
13447 enum transcoder cpu_transcoder = transcoders[i];
13448
Imre Deakddf9c532013-11-27 22:02:02 +020013449 error->transcoder[i].power_domain_on =
Imre Deakbfafe932014-06-05 20:31:47 +030013450 intel_display_power_enabled_unlocked(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020013451 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013452 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013453 continue;
13454
Chris Wilson63b66e52013-08-08 15:12:06 +020013455 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13456
13457 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13458 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13459 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13460 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13461 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13462 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13463 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013464 }
13465
13466 return error;
13467}
13468
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013469#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13470
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013471void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013472intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013473 struct drm_device *dev,
13474 struct intel_display_error_state *error)
13475{
Damien Lespiau055e3932014-08-18 13:49:10 +010013476 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013477 int i;
13478
Chris Wilson63b66e52013-08-08 15:12:06 +020013479 if (!error)
13480 return;
13481
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013482 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020013483 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013484 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013485 error->power_well_driver);
Damien Lespiau055e3932014-08-18 13:49:10 +010013486 for_each_pipe(dev_priv, i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013487 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020013488 err_printf(m, " Power: %s\n",
13489 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013490 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030013491 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013492
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013493 err_printf(m, "Plane [%d]:\n", i);
13494 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13495 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013496 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013497 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13498 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013499 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030013500 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013501 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013502 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013503 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13504 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013505 }
13506
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013507 err_printf(m, "Cursor [%d]:\n", i);
13508 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13509 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13510 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013511 }
Chris Wilson63b66e52013-08-08 15:12:06 +020013512
13513 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010013514 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020013515 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013516 err_printf(m, " Power: %s\n",
13517 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020013518 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13519 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13520 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13521 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13522 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13523 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13524 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13525 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013526}
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013527
13528void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13529{
13530 struct intel_crtc *crtc;
13531
13532 for_each_intel_crtc(dev, crtc) {
13533 struct intel_unpin_work *work;
13534 unsigned long irqflags;
13535
13536 spin_lock_irqsave(&dev->event_lock, irqflags);
13537
13538 work = crtc->unpin_work;
13539
13540 if (work && work->event &&
13541 work->event->base.file_priv == file) {
13542 kfree(work->event);
13543 work->event = NULL;
13544 }
13545
13546 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13547 }
13548}