Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
Daniel Vetter | be6a037 | 2015-03-18 10:46:04 +0100 | [diff] [blame] | 2 | * Copyright © 2008-2015 Intel Corporation |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 29 | #include <drm/drm_vma_manager.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
Yu Zhang | eb82289 | 2015-02-10 19:05:49 +0800 | [diff] [blame] | 32 | #include "i915_vgpu.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 33 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 34 | #include "intel_drv.h" |
Peter Antoine | 0ccdacf | 2016-04-13 15:03:25 +0100 | [diff] [blame] | 35 | #include "intel_mocs.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 36 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 37 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 39 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 40 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 41 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 42 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 43 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 44 | static void |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 45 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
| 46 | static void |
| 47 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 48 | |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 49 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 50 | enum i915_cache_level level) |
| 51 | { |
| 52 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 53 | } |
| 54 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 55 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 56 | { |
| 57 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 58 | return true; |
| 59 | |
| 60 | return obj->pin_display; |
| 61 | } |
| 62 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 63 | /* some bookkeeping */ |
| 64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 65 | size_t size) |
| 66 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 67 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 68 | dev_priv->mm.object_count++; |
| 69 | dev_priv->mm.object_memory += size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 70 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 74 | size_t size) |
| 75 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 76 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 77 | dev_priv->mm.object_count--; |
| 78 | dev_priv->mm.object_memory -= size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 79 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 80 | } |
| 81 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 82 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 83 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 84 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 85 | int ret; |
| 86 | |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 87 | if (!i915_reset_in_progress(error)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 88 | return 0; |
| 89 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 90 | /* |
| 91 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 92 | * userspace. If it takes that long something really bad is going on and |
| 93 | * we should simply try to bail out and fail as gracefully as possible. |
| 94 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 95 | ret = wait_event_interruptible_timeout(error->reset_queue, |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 96 | !i915_reset_in_progress(error), |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 97 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 98 | if (ret == 0) { |
| 99 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 100 | return -EIO; |
| 101 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 102 | return ret; |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 103 | } else { |
| 104 | return 0; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 105 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 106 | } |
| 107 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 108 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 109 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 110 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 111 | int ret; |
| 112 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 113 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 114 | if (ret) |
| 115 | return ret; |
| 116 | |
| 117 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 118 | if (ret) |
| 119 | return ret; |
| 120 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 121 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 122 | return 0; |
| 123 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 124 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 125 | int |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 126 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 127 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 128 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 129 | struct drm_i915_private *dev_priv = to_i915(dev); |
Joonas Lahtinen | 62106b4 | 2016-03-18 10:42:57 +0200 | [diff] [blame] | 130 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 131 | struct drm_i915_gem_get_aperture *args = data; |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 132 | struct i915_vma *vma; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 133 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 134 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 135 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 136 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 137 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 138 | if (vma->pin_count) |
| 139 | pinned += vma->node.size; |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 140 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 141 | if (vma->pin_count) |
| 142 | pinned += vma->node.size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 143 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 144 | |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 145 | args->aper_size = ggtt->base.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 146 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 147 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 148 | return 0; |
| 149 | } |
| 150 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 151 | static int |
| 152 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 153 | { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 154 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 155 | char *vaddr = obj->phys_handle->vaddr; |
| 156 | struct sg_table *st; |
| 157 | struct scatterlist *sg; |
| 158 | int i; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 159 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 160 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
| 161 | return -EINVAL; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 162 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 163 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 164 | struct page *page; |
| 165 | char *src; |
| 166 | |
| 167 | page = shmem_read_mapping_page(mapping, i); |
| 168 | if (IS_ERR(page)) |
| 169 | return PTR_ERR(page); |
| 170 | |
| 171 | src = kmap_atomic(page); |
| 172 | memcpy(vaddr, src, PAGE_SIZE); |
| 173 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 174 | kunmap_atomic(src); |
| 175 | |
Kirill A. Shutemov | 09cbfea | 2016-04-01 15:29:47 +0300 | [diff] [blame] | 176 | put_page(page); |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 177 | vaddr += PAGE_SIZE; |
| 178 | } |
| 179 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 180 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 181 | |
| 182 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 183 | if (st == NULL) |
| 184 | return -ENOMEM; |
| 185 | |
| 186 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { |
| 187 | kfree(st); |
| 188 | return -ENOMEM; |
| 189 | } |
| 190 | |
| 191 | sg = st->sgl; |
| 192 | sg->offset = 0; |
| 193 | sg->length = obj->base.size; |
| 194 | |
| 195 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
| 196 | sg_dma_len(sg) = obj->base.size; |
| 197 | |
| 198 | obj->pages = st; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static void |
| 203 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) |
| 204 | { |
| 205 | int ret; |
| 206 | |
| 207 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 208 | |
| 209 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 210 | if (WARN_ON(ret)) { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 211 | /* In the event of a disaster, abandon all caches and |
| 212 | * hope for the best. |
| 213 | */ |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 214 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 215 | } |
| 216 | |
| 217 | if (obj->madv == I915_MADV_DONTNEED) |
| 218 | obj->dirty = 0; |
| 219 | |
| 220 | if (obj->dirty) { |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 221 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 222 | char *vaddr = obj->phys_handle->vaddr; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 223 | int i; |
| 224 | |
| 225 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 226 | struct page *page; |
| 227 | char *dst; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 228 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 229 | page = shmem_read_mapping_page(mapping, i); |
| 230 | if (IS_ERR(page)) |
| 231 | continue; |
| 232 | |
| 233 | dst = kmap_atomic(page); |
| 234 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 235 | memcpy(dst, vaddr, PAGE_SIZE); |
| 236 | kunmap_atomic(dst); |
| 237 | |
| 238 | set_page_dirty(page); |
| 239 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 240 | mark_page_accessed(page); |
Kirill A. Shutemov | 09cbfea | 2016-04-01 15:29:47 +0300 | [diff] [blame] | 241 | put_page(page); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 242 | vaddr += PAGE_SIZE; |
| 243 | } |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 244 | obj->dirty = 0; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 245 | } |
| 246 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 247 | sg_free_table(obj->pages); |
| 248 | kfree(obj->pages); |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | static void |
| 252 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) |
| 253 | { |
| 254 | drm_pci_free(obj->base.dev, obj->phys_handle); |
| 255 | } |
| 256 | |
| 257 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { |
| 258 | .get_pages = i915_gem_object_get_pages_phys, |
| 259 | .put_pages = i915_gem_object_put_pages_phys, |
| 260 | .release = i915_gem_object_release_phys, |
| 261 | }; |
| 262 | |
| 263 | static int |
| 264 | drop_pages(struct drm_i915_gem_object *obj) |
| 265 | { |
| 266 | struct i915_vma *vma, *next; |
| 267 | int ret; |
| 268 | |
| 269 | drm_gem_object_reference(&obj->base); |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 270 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 271 | if (i915_vma_unbind(vma)) |
| 272 | break; |
| 273 | |
| 274 | ret = i915_gem_object_put_pages(obj); |
| 275 | drm_gem_object_unreference(&obj->base); |
| 276 | |
| 277 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | int |
| 281 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
| 282 | int align) |
| 283 | { |
| 284 | drm_dma_handle_t *phys; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 285 | int ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 286 | |
| 287 | if (obj->phys_handle) { |
| 288 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) |
| 289 | return -EBUSY; |
| 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | if (obj->madv != I915_MADV_WILLNEED) |
| 295 | return -EFAULT; |
| 296 | |
| 297 | if (obj->base.filp == NULL) |
| 298 | return -EINVAL; |
| 299 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 300 | ret = drop_pages(obj); |
| 301 | if (ret) |
| 302 | return ret; |
| 303 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 304 | /* create a new object */ |
| 305 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); |
| 306 | if (!phys) |
| 307 | return -ENOMEM; |
| 308 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 309 | obj->phys_handle = phys; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 310 | obj->ops = &i915_gem_phys_ops; |
| 311 | |
| 312 | return i915_gem_object_get_pages(obj); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | static int |
| 316 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, |
| 317 | struct drm_i915_gem_pwrite *args, |
| 318 | struct drm_file *file_priv) |
| 319 | { |
| 320 | struct drm_device *dev = obj->base.dev; |
| 321 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
Gustavo Padovan | 3ed605b | 2016-04-26 12:32:27 -0300 | [diff] [blame] | 322 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 323 | int ret = 0; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 324 | |
| 325 | /* We manually control the domain here and pretend that it |
| 326 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. |
| 327 | */ |
| 328 | ret = i915_gem_object_wait_rendering(obj, false); |
| 329 | if (ret) |
| 330 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 331 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 332 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 333 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 334 | unsigned long unwritten; |
| 335 | |
| 336 | /* The physical object once assigned is fixed for the lifetime |
| 337 | * of the obj, so we can safely drop the lock and continue |
| 338 | * to access vaddr. |
| 339 | */ |
| 340 | mutex_unlock(&dev->struct_mutex); |
| 341 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 342 | mutex_lock(&dev->struct_mutex); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 343 | if (unwritten) { |
| 344 | ret = -EFAULT; |
| 345 | goto out; |
| 346 | } |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 347 | } |
| 348 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 349 | drm_clflush_virt_range(vaddr, args->size); |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 350 | i915_gem_chipset_flush(to_i915(dev)); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 351 | |
| 352 | out: |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 353 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 354 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 355 | } |
| 356 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 357 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 358 | { |
| 359 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 360 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 364 | { |
| 365 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 366 | kmem_cache_free(dev_priv->objects, obj); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 367 | } |
| 368 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 369 | static int |
| 370 | i915_gem_create(struct drm_file *file, |
| 371 | struct drm_device *dev, |
| 372 | uint64_t size, |
| 373 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 374 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 375 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 376 | int ret; |
| 377 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 378 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 379 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 380 | if (size == 0) |
| 381 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 382 | |
| 383 | /* Allocate the new object */ |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 384 | obj = i915_gem_object_create(dev, size); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 385 | if (IS_ERR(obj)) |
| 386 | return PTR_ERR(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 387 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 388 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 389 | /* drop reference from allocate - handle holds it now */ |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 390 | drm_gem_object_unreference_unlocked(&obj->base); |
| 391 | if (ret) |
| 392 | return ret; |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 393 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 394 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 395 | return 0; |
| 396 | } |
| 397 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 398 | int |
| 399 | i915_gem_dumb_create(struct drm_file *file, |
| 400 | struct drm_device *dev, |
| 401 | struct drm_mode_create_dumb *args) |
| 402 | { |
| 403 | /* have to work out size/pitch and return them */ |
Paulo Zanoni | de45eaf | 2013-10-18 18:48:24 -0300 | [diff] [blame] | 404 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 405 | args->size = args->pitch * args->height; |
| 406 | return i915_gem_create(file, dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 407 | args->size, &args->handle); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 408 | } |
| 409 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 410 | /** |
| 411 | * Creates a new mm object and returns a handle to it. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 412 | * @dev: drm device pointer |
| 413 | * @data: ioctl data blob |
| 414 | * @file: drm file pointer |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 415 | */ |
| 416 | int |
| 417 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 418 | struct drm_file *file) |
| 419 | { |
| 420 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 421 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 422 | return i915_gem_create(file, dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 423 | args->size, &args->handle); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 424 | } |
| 425 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 426 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 427 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 428 | const char *gpu_vaddr, int gpu_offset, |
| 429 | int length) |
| 430 | { |
| 431 | int ret, cpu_offset = 0; |
| 432 | |
| 433 | while (length > 0) { |
| 434 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 435 | int this_length = min(cacheline_end - gpu_offset, length); |
| 436 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 437 | |
| 438 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 439 | gpu_vaddr + swizzled_gpu_offset, |
| 440 | this_length); |
| 441 | if (ret) |
| 442 | return ret + length; |
| 443 | |
| 444 | cpu_offset += this_length; |
| 445 | gpu_offset += this_length; |
| 446 | length -= this_length; |
| 447 | } |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 453 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 454 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 455 | int length) |
| 456 | { |
| 457 | int ret, cpu_offset = 0; |
| 458 | |
| 459 | while (length > 0) { |
| 460 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 461 | int this_length = min(cacheline_end - gpu_offset, length); |
| 462 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 463 | |
| 464 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 465 | cpu_vaddr + cpu_offset, |
| 466 | this_length); |
| 467 | if (ret) |
| 468 | return ret + length; |
| 469 | |
| 470 | cpu_offset += this_length; |
| 471 | gpu_offset += this_length; |
| 472 | length -= this_length; |
| 473 | } |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 478 | /* |
| 479 | * Pins the specified object's pages and synchronizes the object with |
| 480 | * GPU accesses. Sets needs_clflush to non-zero if the caller should |
| 481 | * flush the object from the CPU cache. |
| 482 | */ |
| 483 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 484 | int *needs_clflush) |
| 485 | { |
| 486 | int ret; |
| 487 | |
| 488 | *needs_clflush = 0; |
| 489 | |
Ben Widawsky | 1db6e2e | 2016-02-09 11:44:12 -0800 | [diff] [blame] | 490 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 491 | return -EINVAL; |
| 492 | |
| 493 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 494 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 495 | * read domain and manually flush cachelines (if required). This |
| 496 | * optimizes for the case when the gpu will dirty the data |
| 497 | * anyway again before the next pread happens. */ |
| 498 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
| 499 | obj->cache_level); |
| 500 | ret = i915_gem_object_wait_rendering(obj, true); |
| 501 | if (ret) |
| 502 | return ret; |
| 503 | } |
| 504 | |
| 505 | ret = i915_gem_object_get_pages(obj); |
| 506 | if (ret) |
| 507 | return ret; |
| 508 | |
| 509 | i915_gem_object_pin_pages(obj); |
| 510 | |
| 511 | return ret; |
| 512 | } |
| 513 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 514 | /* Per-page copy function for the shmem pread fastpath. |
| 515 | * Flushes invalid cachelines before reading the target if |
| 516 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 517 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 518 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 519 | char __user *user_data, |
| 520 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 521 | { |
| 522 | char *vaddr; |
| 523 | int ret; |
| 524 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 525 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 526 | return -EINVAL; |
| 527 | |
| 528 | vaddr = kmap_atomic(page); |
| 529 | if (needs_clflush) |
| 530 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 531 | page_length); |
| 532 | ret = __copy_to_user_inatomic(user_data, |
| 533 | vaddr + shmem_page_offset, |
| 534 | page_length); |
| 535 | kunmap_atomic(vaddr); |
| 536 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 537 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 538 | } |
| 539 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 540 | static void |
| 541 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 542 | bool swizzled) |
| 543 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 544 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 545 | unsigned long start = (unsigned long) addr; |
| 546 | unsigned long end = (unsigned long) addr + length; |
| 547 | |
| 548 | /* For swizzling simply ensure that we always flush both |
| 549 | * channels. Lame, but simple and it works. Swizzled |
| 550 | * pwrite/pread is far from a hotpath - current userspace |
| 551 | * doesn't use it at all. */ |
| 552 | start = round_down(start, 128); |
| 553 | end = round_up(end, 128); |
| 554 | |
| 555 | drm_clflush_virt_range((void *)start, end - start); |
| 556 | } else { |
| 557 | drm_clflush_virt_range(addr, length); |
| 558 | } |
| 559 | |
| 560 | } |
| 561 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 562 | /* Only difference to the fast-path function is that this can handle bit17 |
| 563 | * and uses non-atomic copy and kmap functions. */ |
| 564 | static int |
| 565 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 566 | char __user *user_data, |
| 567 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 568 | { |
| 569 | char *vaddr; |
| 570 | int ret; |
| 571 | |
| 572 | vaddr = kmap(page); |
| 573 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 574 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 575 | page_length, |
| 576 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 577 | |
| 578 | if (page_do_bit17_swizzling) |
| 579 | ret = __copy_to_user_swizzled(user_data, |
| 580 | vaddr, shmem_page_offset, |
| 581 | page_length); |
| 582 | else |
| 583 | ret = __copy_to_user(user_data, |
| 584 | vaddr + shmem_page_offset, |
| 585 | page_length); |
| 586 | kunmap(page); |
| 587 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 588 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 589 | } |
| 590 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 591 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 592 | i915_gem_shmem_pread(struct drm_device *dev, |
| 593 | struct drm_i915_gem_object *obj, |
| 594 | struct drm_i915_gem_pread *args, |
| 595 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 596 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 597 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 598 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 599 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 600 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 601 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 602 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 603 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 604 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 605 | |
Gustavo Padovan | 3ed605b | 2016-04-26 12:32:27 -0300 | [diff] [blame] | 606 | user_data = u64_to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 607 | remain = args->size; |
| 608 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 609 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 610 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 611 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 612 | if (ret) |
| 613 | return ret; |
| 614 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 615 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 616 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 617 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 618 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 619 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 620 | |
| 621 | if (remain <= 0) |
| 622 | break; |
| 623 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 624 | /* Operation in this page |
| 625 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 626 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 627 | * page_length = bytes to copy for this page |
| 628 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 629 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 630 | page_length = remain; |
| 631 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 632 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 633 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 634 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 635 | (page_to_phys(page) & (1 << 17)) != 0; |
| 636 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 637 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 638 | user_data, page_do_bit17_swizzling, |
| 639 | needs_clflush); |
| 640 | if (ret == 0) |
| 641 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 642 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 643 | mutex_unlock(&dev->struct_mutex); |
| 644 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 645 | if (likely(!i915.prefault_disable) && !prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 646 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 647 | /* Userspace is tricking us, but we've already clobbered |
| 648 | * its pages with the prefault and promised to write the |
| 649 | * data up to the first fault. Hence ignore any errors |
| 650 | * and just continue. */ |
| 651 | (void)ret; |
| 652 | prefaulted = 1; |
| 653 | } |
| 654 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 655 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 656 | user_data, page_do_bit17_swizzling, |
| 657 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 658 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 659 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 660 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 661 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 662 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 663 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 664 | next_page: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 665 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 666 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 667 | offset += page_length; |
| 668 | } |
| 669 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 670 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 671 | i915_gem_object_unpin_pages(obj); |
| 672 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 673 | return ret; |
| 674 | } |
| 675 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 676 | /** |
| 677 | * Reads data from the object referenced by handle. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 678 | * @dev: drm device pointer |
| 679 | * @data: ioctl data blob |
| 680 | * @file: drm file pointer |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 681 | * |
| 682 | * On error, the contents of *data are undefined. |
| 683 | */ |
| 684 | int |
| 685 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 686 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 687 | { |
| 688 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 689 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 690 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 691 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 692 | if (args->size == 0) |
| 693 | return 0; |
| 694 | |
| 695 | if (!access_ok(VERIFY_WRITE, |
Gustavo Padovan | 3ed605b | 2016-04-26 12:32:27 -0300 | [diff] [blame] | 696 | u64_to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 697 | args->size)) |
| 698 | return -EFAULT; |
| 699 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 700 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 701 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 702 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 703 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 704 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 705 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 706 | ret = -ENOENT; |
| 707 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 708 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 709 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 710 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 711 | if (args->offset > obj->base.size || |
| 712 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 713 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 714 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 715 | } |
| 716 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 717 | /* prime objects have no backing filp to GEM pread/pwrite |
| 718 | * pages from. |
| 719 | */ |
| 720 | if (!obj->base.filp) { |
| 721 | ret = -EINVAL; |
| 722 | goto out; |
| 723 | } |
| 724 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 725 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 726 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 727 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 728 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 729 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 730 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 731 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 732 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 733 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 734 | } |
| 735 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 736 | /* This is the fast write path which cannot handle |
| 737 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 738 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 739 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 740 | static inline int |
| 741 | fast_user_write(struct io_mapping *mapping, |
| 742 | loff_t page_base, int page_offset, |
| 743 | char __user *user_data, |
| 744 | int length) |
| 745 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 746 | void __iomem *vaddr_atomic; |
| 747 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 748 | unsigned long unwritten; |
| 749 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 750 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 751 | /* We can use the cpu mem copy function because this is X86. */ |
| 752 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 753 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 754 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 755 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 756 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 757 | } |
| 758 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 759 | /** |
| 760 | * This is the fast pwrite path, where we copy the data directly from the |
| 761 | * user into the GTT, uncached. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 762 | * @dev: drm device pointer |
| 763 | * @obj: i915 gem object |
| 764 | * @args: pwrite arguments structure |
| 765 | * @file: drm file pointer |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 766 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 767 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 768 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 769 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 770 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 771 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 772 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 773 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 774 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 775 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 776 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 777 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 778 | int page_offset, page_length, ret; |
| 779 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 780 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 781 | if (ret) |
| 782 | goto out; |
| 783 | |
| 784 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 785 | if (ret) |
| 786 | goto out_unpin; |
| 787 | |
| 788 | ret = i915_gem_object_put_fence(obj); |
| 789 | if (ret) |
| 790 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 791 | |
Gustavo Padovan | 3ed605b | 2016-04-26 12:32:27 -0300 | [diff] [blame] | 792 | user_data = u64_to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 793 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 794 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 795 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 796 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 797 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 798 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 799 | while (remain > 0) { |
| 800 | /* Operation in this page |
| 801 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 802 | * page_base = page offset within aperture |
| 803 | * page_offset = offset within page |
| 804 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 805 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 806 | page_base = offset & PAGE_MASK; |
| 807 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 808 | page_length = remain; |
| 809 | if ((page_offset + remain) > PAGE_SIZE) |
| 810 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 811 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 812 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 813 | * source page isn't available. Return the error and we'll |
| 814 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 815 | */ |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 816 | if (fast_user_write(ggtt->mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 817 | page_offset, user_data, page_length)) { |
| 818 | ret = -EFAULT; |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 819 | goto out_flush; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 820 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 821 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 822 | remain -= page_length; |
| 823 | user_data += page_length; |
| 824 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 825 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 826 | |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 827 | out_flush: |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 828 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 829 | out_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 830 | i915_gem_object_ggtt_unpin(obj); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 831 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 832 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 833 | } |
| 834 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 835 | /* Per-page copy function for the shmem pwrite fastpath. |
| 836 | * Flushes invalid cachelines before writing to the target if |
| 837 | * needs_clflush_before is set and flushes out any written cachelines after |
| 838 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 839 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 840 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 841 | char __user *user_data, |
| 842 | bool page_do_bit17_swizzling, |
| 843 | bool needs_clflush_before, |
| 844 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 845 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 846 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 847 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 848 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 849 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 850 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 851 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 852 | vaddr = kmap_atomic(page); |
| 853 | if (needs_clflush_before) |
| 854 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 855 | page_length); |
Chris Wilson | c2831a9 | 2014-03-07 08:30:37 +0000 | [diff] [blame] | 856 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
| 857 | user_data, page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 858 | if (needs_clflush_after) |
| 859 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 860 | page_length); |
| 861 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 862 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 863 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 864 | } |
| 865 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 866 | /* Only difference to the fast-path function is that this can handle bit17 |
| 867 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 868 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 869 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 870 | char __user *user_data, |
| 871 | bool page_do_bit17_swizzling, |
| 872 | bool needs_clflush_before, |
| 873 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 874 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 875 | char *vaddr; |
| 876 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 877 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 878 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 879 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 880 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 881 | page_length, |
| 882 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 883 | if (page_do_bit17_swizzling) |
| 884 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 885 | user_data, |
| 886 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 887 | else |
| 888 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 889 | user_data, |
| 890 | page_length); |
| 891 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 892 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 893 | page_length, |
| 894 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 895 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 896 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 897 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 898 | } |
| 899 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 900 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 901 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 902 | struct drm_i915_gem_object *obj, |
| 903 | struct drm_i915_gem_pwrite *args, |
| 904 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 905 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 906 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 907 | loff_t offset; |
| 908 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 909 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 910 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 911 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 912 | int needs_clflush_after = 0; |
| 913 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 914 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 915 | |
Gustavo Padovan | 3ed605b | 2016-04-26 12:32:27 -0300 | [diff] [blame] | 916 | user_data = u64_to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 917 | remain = args->size; |
| 918 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 919 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 920 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 921 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 922 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 923 | * write domain and manually flush cachelines (if required). This |
| 924 | * optimizes for the case when the gpu will use the data |
| 925 | * right away and we therefore have to clflush anyway. */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 926 | needs_clflush_after = cpu_write_needs_clflush(obj); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 927 | ret = i915_gem_object_wait_rendering(obj, false); |
| 928 | if (ret) |
| 929 | return ret; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 930 | } |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 931 | /* Same trick applies to invalidate partially written cachelines read |
| 932 | * before writing. */ |
| 933 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 934 | needs_clflush_before = |
| 935 | !cpu_cache_is_coherent(dev, obj->cache_level); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 936 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 937 | ret = i915_gem_object_get_pages(obj); |
| 938 | if (ret) |
| 939 | return ret; |
| 940 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 941 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 942 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 943 | i915_gem_object_pin_pages(obj); |
| 944 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 945 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 946 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 947 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 948 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 949 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 950 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 951 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 952 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 953 | if (remain <= 0) |
| 954 | break; |
| 955 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 956 | /* Operation in this page |
| 957 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 958 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 959 | * page_length = bytes to copy for this page |
| 960 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 961 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 962 | |
| 963 | page_length = remain; |
| 964 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 965 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 966 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 967 | /* If we don't overwrite a cacheline completely we need to be |
| 968 | * careful to have up-to-date data by first clflushing. Don't |
| 969 | * overcomplicate things and flush the entire patch. */ |
| 970 | partial_cacheline_write = needs_clflush_before && |
| 971 | ((shmem_page_offset | page_length) |
| 972 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 973 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 974 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 975 | (page_to_phys(page) & (1 << 17)) != 0; |
| 976 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 977 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 978 | user_data, page_do_bit17_swizzling, |
| 979 | partial_cacheline_write, |
| 980 | needs_clflush_after); |
| 981 | if (ret == 0) |
| 982 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 983 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 984 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 985 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 986 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 987 | user_data, page_do_bit17_swizzling, |
| 988 | partial_cacheline_write, |
| 989 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 990 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 991 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 992 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 993 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 994 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 995 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 996 | next_page: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 997 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 998 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 999 | offset += page_length; |
| 1000 | } |
| 1001 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1002 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 1003 | i915_gem_object_unpin_pages(obj); |
| 1004 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1005 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 1006 | /* |
| 1007 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 1008 | * cachelines in-line while writing and the object moved |
| 1009 | * out of the cpu write domain while we've dropped the lock. |
| 1010 | */ |
| 1011 | if (!needs_clflush_after && |
| 1012 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 1013 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 1014 | needs_clflush_after = true; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1015 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1016 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1017 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 1018 | if (needs_clflush_after) |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1019 | i915_gem_chipset_flush(to_i915(dev)); |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 1020 | else |
| 1021 | obj->cache_dirty = true; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 1022 | |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 1023 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1024 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1025 | } |
| 1026 | |
| 1027 | /** |
| 1028 | * Writes data to the object referenced by handle. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 1029 | * @dev: drm device |
| 1030 | * @data: ioctl data blob |
| 1031 | * @file: drm file |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1032 | * |
| 1033 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1034 | */ |
| 1035 | int |
| 1036 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1037 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1038 | { |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1039 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1040 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1041 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1042 | int ret; |
| 1043 | |
| 1044 | if (args->size == 0) |
| 1045 | return 0; |
| 1046 | |
| 1047 | if (!access_ok(VERIFY_READ, |
Gustavo Padovan | 3ed605b | 2016-04-26 12:32:27 -0300 | [diff] [blame] | 1048 | u64_to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1049 | args->size)) |
| 1050 | return -EFAULT; |
| 1051 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1052 | if (likely(!i915.prefault_disable)) { |
Gustavo Padovan | 3ed605b | 2016-04-26 12:32:27 -0300 | [diff] [blame] | 1053 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 1054 | args->size); |
| 1055 | if (ret) |
| 1056 | return -EFAULT; |
| 1057 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1058 | |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1059 | intel_runtime_pm_get(dev_priv); |
| 1060 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1061 | ret = i915_mutex_lock_interruptible(dev); |
| 1062 | if (ret) |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1063 | goto put_rpm; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1064 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 1065 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1066 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1067 | ret = -ENOENT; |
| 1068 | goto unlock; |
| 1069 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1070 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1071 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1072 | if (args->offset > obj->base.size || |
| 1073 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1074 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1075 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1076 | } |
| 1077 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1078 | /* prime objects have no backing filp to GEM pread/pwrite |
| 1079 | * pages from. |
| 1080 | */ |
| 1081 | if (!obj->base.filp) { |
| 1082 | ret = -EINVAL; |
| 1083 | goto out; |
| 1084 | } |
| 1085 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1086 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 1087 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1088 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1089 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1090 | * it would end up going through the fenced access, and we'll get |
| 1091 | * different detiling behavior between reading and writing. |
| 1092 | * pread/pwrite currently are reading and writing from the CPU |
| 1093 | * perspective, requiring manual detiling by the client. |
| 1094 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1095 | if (obj->tiling_mode == I915_TILING_NONE && |
| 1096 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 1097 | cpu_write_needs_clflush(obj)) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1098 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1099 | /* Note that the gtt paths might fail with non-page-backed user |
| 1100 | * pointers (e.g. gtt mappings when moving data between |
| 1101 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1102 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1103 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 1104 | if (ret == -EFAULT || ret == -ENOSPC) { |
| 1105 | if (obj->phys_handle) |
| 1106 | ret = i915_gem_phys_pwrite(obj, args, file); |
| 1107 | else |
| 1108 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
| 1109 | } |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 1110 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1111 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1112 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1113 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1114 | mutex_unlock(&dev->struct_mutex); |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1115 | put_rpm: |
| 1116 | intel_runtime_pm_put(dev_priv); |
| 1117 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1118 | return ret; |
| 1119 | } |
| 1120 | |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1121 | static int |
| 1122 | i915_gem_check_wedge(unsigned reset_counter, bool interruptible) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1123 | { |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1124 | if (__i915_terminally_wedged(reset_counter)) |
| 1125 | return -EIO; |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 1126 | |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1127 | if (__i915_reset_in_progress(reset_counter)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1128 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1129 | * -EIO unconditionally for these. */ |
| 1130 | if (!interruptible) |
| 1131 | return -EIO; |
| 1132 | |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 1133 | return -EAGAIN; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1134 | } |
| 1135 | |
| 1136 | return 0; |
| 1137 | } |
| 1138 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1139 | static void fake_irq(unsigned long data) |
| 1140 | { |
| 1141 | wake_up_process((struct task_struct *)data); |
| 1142 | } |
| 1143 | |
| 1144 | static bool missed_irq(struct drm_i915_private *dev_priv, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1145 | struct intel_engine_cs *engine) |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1146 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1147 | return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1148 | } |
| 1149 | |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1150 | static unsigned long local_clock_us(unsigned *cpu) |
| 1151 | { |
| 1152 | unsigned long t; |
| 1153 | |
| 1154 | /* Cheaply and approximately convert from nanoseconds to microseconds. |
| 1155 | * The result and subsequent calculations are also defined in the same |
| 1156 | * approximate microseconds units. The principal source of timing |
| 1157 | * error here is from the simple truncation. |
| 1158 | * |
| 1159 | * Note that local_clock() is only defined wrt to the current CPU; |
| 1160 | * the comparisons are no longer valid if we switch CPUs. Instead of |
| 1161 | * blocking preemption for the entire busywait, we can detect the CPU |
| 1162 | * switch and use that as indicator of system load and a reason to |
| 1163 | * stop busywaiting, see busywait_stop(). |
| 1164 | */ |
| 1165 | *cpu = get_cpu(); |
| 1166 | t = local_clock() >> 10; |
| 1167 | put_cpu(); |
| 1168 | |
| 1169 | return t; |
| 1170 | } |
| 1171 | |
| 1172 | static bool busywait_stop(unsigned long timeout, unsigned cpu) |
| 1173 | { |
| 1174 | unsigned this_cpu; |
| 1175 | |
| 1176 | if (time_after(local_clock_us(&this_cpu), timeout)) |
| 1177 | return true; |
| 1178 | |
| 1179 | return this_cpu != cpu; |
| 1180 | } |
| 1181 | |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1182 | static int __i915_spin_request(struct drm_i915_gem_request *req, int state) |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1183 | { |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1184 | unsigned long timeout; |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1185 | unsigned cpu; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1186 | |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1187 | /* When waiting for high frequency requests, e.g. during synchronous |
| 1188 | * rendering split between the CPU and GPU, the finite amount of time |
| 1189 | * required to set up the irq and wait upon it limits the response |
| 1190 | * rate. By busywaiting on the request completion for a short while we |
| 1191 | * can service the high frequency waits as quick as possible. However, |
| 1192 | * if it is a slow request, we want to sleep as quickly as possible. |
| 1193 | * The tradeoff between waiting and sleeping is roughly the time it |
| 1194 | * takes to sleep on a request, on the order of a microsecond. |
| 1195 | */ |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1196 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1197 | if (req->engine->irq_refcount) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1198 | return -EBUSY; |
| 1199 | |
Chris Wilson | 821485d | 2015-12-11 11:32:59 +0000 | [diff] [blame] | 1200 | /* Only spin if we know the GPU is processing this request */ |
| 1201 | if (!i915_gem_request_started(req, true)) |
| 1202 | return -EAGAIN; |
| 1203 | |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1204 | timeout = local_clock_us(&cpu) + 5; |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1205 | while (!need_resched()) { |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 1206 | if (i915_gem_request_completed(req, true)) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1207 | return 0; |
| 1208 | |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1209 | if (signal_pending_state(state, current)) |
| 1210 | break; |
| 1211 | |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1212 | if (busywait_stop(timeout, cpu)) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1213 | break; |
| 1214 | |
| 1215 | cpu_relax_lowlatency(); |
| 1216 | } |
Chris Wilson | 821485d | 2015-12-11 11:32:59 +0000 | [diff] [blame] | 1217 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 1218 | if (i915_gem_request_completed(req, false)) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1219 | return 0; |
| 1220 | |
| 1221 | return -EAGAIN; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1222 | } |
| 1223 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1224 | /** |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1225 | * __i915_wait_request - wait until execution of request has finished |
| 1226 | * @req: duh! |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1227 | * @interruptible: do an interruptible wait (normally yes) |
| 1228 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 1229 | * @rps: RPS client |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1230 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1231 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1232 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1233 | * locks are involved, it is sufficient to read the reset_counter before |
| 1234 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1235 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1236 | * inserted. |
| 1237 | * |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1238 | * Returns 0 if the request was found within the alloted time. Else returns the |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1239 | * errno with remaining time filled in timeout argument. |
| 1240 | */ |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1241 | int __i915_wait_request(struct drm_i915_gem_request *req, |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1242 | bool interruptible, |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1243 | s64 *timeout, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1244 | struct intel_rps_client *rps) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1245 | { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1246 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1247 | struct drm_i915_private *dev_priv = req->i915; |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1248 | const bool irq_test_in_progress = |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1249 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine); |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1250 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1251 | DEFINE_WAIT(wait); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1252 | unsigned long timeout_expire; |
Tvrtko Ursulin | e0313db | 2016-01-15 15:11:12 +0000 | [diff] [blame] | 1253 | s64 before = 0; /* Only to silence a compiler warning. */ |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1254 | int ret; |
| 1255 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 1256 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1257 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1258 | if (list_empty(&req->list)) |
| 1259 | return 0; |
| 1260 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 1261 | if (i915_gem_request_completed(req, true)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1262 | return 0; |
| 1263 | |
Chris Wilson | bb6d198 | 2015-11-26 13:31:42 +0000 | [diff] [blame] | 1264 | timeout_expire = 0; |
| 1265 | if (timeout) { |
| 1266 | if (WARN_ON(*timeout < 0)) |
| 1267 | return -EINVAL; |
| 1268 | |
| 1269 | if (*timeout == 0) |
| 1270 | return -ETIME; |
| 1271 | |
| 1272 | timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout); |
Tvrtko Ursulin | e0313db | 2016-01-15 15:11:12 +0000 | [diff] [blame] | 1273 | |
| 1274 | /* |
| 1275 | * Record current time in case interrupted by signal, or wedged. |
| 1276 | */ |
| 1277 | before = ktime_get_raw_ns(); |
Chris Wilson | bb6d198 | 2015-11-26 13:31:42 +0000 | [diff] [blame] | 1278 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1279 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1280 | if (INTEL_INFO(dev_priv)->gen >= 6) |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 1281 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1282 | |
John Harrison | 74328ee | 2014-11-24 18:49:38 +0000 | [diff] [blame] | 1283 | trace_i915_gem_request_wait_begin(req); |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1284 | |
| 1285 | /* Optimistic spin for the next jiffie before touching IRQs */ |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1286 | ret = __i915_spin_request(req, state); |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1287 | if (ret == 0) |
| 1288 | goto out; |
| 1289 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1290 | if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) { |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1291 | ret = -ENODEV; |
| 1292 | goto out; |
| 1293 | } |
| 1294 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1295 | for (;;) { |
| 1296 | struct timer_list timer; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1297 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1298 | prepare_to_wait(&engine->irq_queue, &wait, state); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1299 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1300 | /* We need to check whether any gpu reset happened in between |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1301 | * the request being submitted and now. If a reset has occurred, |
| 1302 | * the request is effectively complete (we either are in the |
| 1303 | * process of or have discarded the rendering and completely |
| 1304 | * reset the GPU. The results of the request are lost and we |
| 1305 | * are free to continue on with the original operation. |
| 1306 | */ |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 1307 | if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) { |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1308 | ret = 0; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1309 | break; |
| 1310 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1311 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 1312 | if (i915_gem_request_completed(req, false)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1313 | ret = 0; |
| 1314 | break; |
| 1315 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1316 | |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1317 | if (signal_pending_state(state, current)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1318 | ret = -ERESTARTSYS; |
| 1319 | break; |
| 1320 | } |
| 1321 | |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1322 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1323 | ret = -ETIME; |
| 1324 | break; |
| 1325 | } |
| 1326 | |
| 1327 | timer.function = NULL; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1328 | if (timeout || missed_irq(dev_priv, engine)) { |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1329 | unsigned long expire; |
| 1330 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1331 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1332 | expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1333 | mod_timer(&timer, expire); |
| 1334 | } |
| 1335 | |
Chris Wilson | 5035c27 | 2013-10-04 09:58:46 +0100 | [diff] [blame] | 1336 | io_schedule(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1337 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1338 | if (timer.function) { |
| 1339 | del_singleshot_timer_sync(&timer); |
| 1340 | destroy_timer_on_stack(&timer); |
| 1341 | } |
| 1342 | } |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1343 | if (!irq_test_in_progress) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1344 | engine->irq_put(engine); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1345 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1346 | finish_wait(&engine->irq_queue, &wait); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1347 | |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1348 | out: |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1349 | trace_i915_gem_request_wait_end(req); |
| 1350 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1351 | if (timeout) { |
Tvrtko Ursulin | e0313db | 2016-01-15 15:11:12 +0000 | [diff] [blame] | 1352 | s64 tres = *timeout - (ktime_get_raw_ns() - before); |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1353 | |
| 1354 | *timeout = tres < 0 ? 0 : tres; |
Daniel Vetter | 9cca306 | 2014-11-28 10:29:55 +0100 | [diff] [blame] | 1355 | |
| 1356 | /* |
| 1357 | * Apparently ktime isn't accurate enough and occasionally has a |
| 1358 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch |
| 1359 | * things up to make the test happy. We allow up to 1 jiffy. |
| 1360 | * |
| 1361 | * This is a regrssion from the timespec->ktime conversion. |
| 1362 | */ |
| 1363 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) |
| 1364 | *timeout = 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1365 | } |
| 1366 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1367 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1368 | } |
| 1369 | |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 1370 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
| 1371 | struct drm_file *file) |
| 1372 | { |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 1373 | struct drm_i915_file_private *file_priv; |
| 1374 | |
| 1375 | WARN_ON(!req || !file || req->file_priv); |
| 1376 | |
| 1377 | if (!req || !file) |
| 1378 | return -EINVAL; |
| 1379 | |
| 1380 | if (req->file_priv) |
| 1381 | return -EINVAL; |
| 1382 | |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 1383 | file_priv = file->driver_priv; |
| 1384 | |
| 1385 | spin_lock(&file_priv->mm.lock); |
| 1386 | req->file_priv = file_priv; |
| 1387 | list_add_tail(&req->client_list, &file_priv->mm.request_list); |
| 1388 | spin_unlock(&file_priv->mm.lock); |
| 1389 | |
| 1390 | req->pid = get_pid(task_pid(current)); |
| 1391 | |
| 1392 | return 0; |
| 1393 | } |
| 1394 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1395 | static inline void |
| 1396 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
| 1397 | { |
| 1398 | struct drm_i915_file_private *file_priv = request->file_priv; |
| 1399 | |
| 1400 | if (!file_priv) |
| 1401 | return; |
| 1402 | |
| 1403 | spin_lock(&file_priv->mm.lock); |
| 1404 | list_del(&request->client_list); |
| 1405 | request->file_priv = NULL; |
| 1406 | spin_unlock(&file_priv->mm.lock); |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 1407 | |
| 1408 | put_pid(request->pid); |
| 1409 | request->pid = NULL; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1410 | } |
| 1411 | |
| 1412 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) |
| 1413 | { |
| 1414 | trace_i915_gem_request_retire(request); |
| 1415 | |
| 1416 | /* We know the GPU must have read the request to have |
| 1417 | * sent us the seqno + interrupt, so use the position |
| 1418 | * of tail of the request to update the last known position |
| 1419 | * of the GPU head. |
| 1420 | * |
| 1421 | * Note this requires that we are always called in request |
| 1422 | * completion order. |
| 1423 | */ |
| 1424 | request->ringbuf->last_retired_head = request->postfix; |
| 1425 | |
| 1426 | list_del_init(&request->list); |
| 1427 | i915_gem_request_remove_from_client(request); |
| 1428 | |
Chris Wilson | a16a405 | 2016-04-28 09:56:56 +0100 | [diff] [blame] | 1429 | if (request->previous_context) { |
Chris Wilson | 73db04c | 2016-04-28 09:56:55 +0100 | [diff] [blame] | 1430 | if (i915.enable_execlists) |
Chris Wilson | a16a405 | 2016-04-28 09:56:56 +0100 | [diff] [blame] | 1431 | intel_lr_context_unpin(request->previous_context, |
| 1432 | request->engine); |
Chris Wilson | 73db04c | 2016-04-28 09:56:55 +0100 | [diff] [blame] | 1433 | } |
| 1434 | |
Chris Wilson | a16a405 | 2016-04-28 09:56:56 +0100 | [diff] [blame] | 1435 | i915_gem_context_unreference(request->ctx); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1436 | i915_gem_request_unreference(request); |
| 1437 | } |
| 1438 | |
| 1439 | static void |
| 1440 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) |
| 1441 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1442 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1443 | struct drm_i915_gem_request *tmp; |
| 1444 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 1445 | lockdep_assert_held(&engine->i915->dev->struct_mutex); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1446 | |
| 1447 | if (list_empty(&req->list)) |
| 1448 | return; |
| 1449 | |
| 1450 | do { |
| 1451 | tmp = list_first_entry(&engine->request_list, |
| 1452 | typeof(*tmp), list); |
| 1453 | |
| 1454 | i915_gem_request_retire(tmp); |
| 1455 | } while (tmp != req); |
| 1456 | |
| 1457 | WARN_ON(i915_verify_lists(engine->dev)); |
| 1458 | } |
| 1459 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1460 | /** |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1461 | * Waits for a request to be signaled, and cleans up the |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1462 | * request and object lists appropriately for that event. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 1463 | * @req: request to wait on |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1464 | */ |
| 1465 | int |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1466 | i915_wait_request(struct drm_i915_gem_request *req) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1467 | { |
Tvrtko Ursulin | 791bee1 | 2016-04-19 16:46:09 +0100 | [diff] [blame] | 1468 | struct drm_i915_private *dev_priv = req->i915; |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1469 | bool interruptible; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1470 | int ret; |
| 1471 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1472 | interruptible = dev_priv->mm.interruptible; |
| 1473 | |
Tvrtko Ursulin | 791bee1 | 2016-04-19 16:46:09 +0100 | [diff] [blame] | 1474 | BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1475 | |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 1476 | ret = __i915_wait_request(req, interruptible, NULL, NULL); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1477 | if (ret) |
| 1478 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1479 | |
Chris Wilson | e075a32 | 2016-05-13 11:57:22 +0100 | [diff] [blame] | 1480 | /* If the GPU hung, we want to keep the requests to find the guilty. */ |
| 1481 | if (req->reset_counter == i915_reset_counter(&dev_priv->gpu_error)) |
| 1482 | __i915_gem_request_retire__upto(req); |
| 1483 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1484 | return 0; |
| 1485 | } |
| 1486 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1487 | /** |
| 1488 | * Ensures that all rendering to the object has completed and the object is |
| 1489 | * safe to unbind from the GTT or access from the CPU. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 1490 | * @obj: i915 gem object |
| 1491 | * @readonly: waiting for read access or write |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1492 | */ |
Chris Wilson | 2e2f351 | 2015-04-27 13:41:14 +0100 | [diff] [blame] | 1493 | int |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1494 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1495 | bool readonly) |
| 1496 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1497 | int ret, i; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1498 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1499 | if (!obj->active) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1500 | return 0; |
| 1501 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1502 | if (readonly) { |
| 1503 | if (obj->last_write_req != NULL) { |
| 1504 | ret = i915_wait_request(obj->last_write_req); |
| 1505 | if (ret) |
| 1506 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1507 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1508 | i = obj->last_write_req->engine->id; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1509 | if (obj->last_read_req[i] == obj->last_write_req) |
| 1510 | i915_gem_object_retire__read(obj, i); |
| 1511 | else |
| 1512 | i915_gem_object_retire__write(obj); |
| 1513 | } |
| 1514 | } else { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1515 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1516 | if (obj->last_read_req[i] == NULL) |
| 1517 | continue; |
| 1518 | |
| 1519 | ret = i915_wait_request(obj->last_read_req[i]); |
| 1520 | if (ret) |
| 1521 | return ret; |
| 1522 | |
| 1523 | i915_gem_object_retire__read(obj, i); |
| 1524 | } |
Chris Wilson | d501b1d | 2016-04-13 17:35:02 +0100 | [diff] [blame] | 1525 | GEM_BUG_ON(obj->active); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1526 | } |
| 1527 | |
| 1528 | return 0; |
| 1529 | } |
| 1530 | |
| 1531 | static void |
| 1532 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, |
| 1533 | struct drm_i915_gem_request *req) |
| 1534 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1535 | int ring = req->engine->id; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1536 | |
| 1537 | if (obj->last_read_req[ring] == req) |
| 1538 | i915_gem_object_retire__read(obj, ring); |
| 1539 | else if (obj->last_write_req == req) |
| 1540 | i915_gem_object_retire__write(obj); |
| 1541 | |
Chris Wilson | e075a32 | 2016-05-13 11:57:22 +0100 | [diff] [blame] | 1542 | if (req->reset_counter == i915_reset_counter(&req->i915->gpu_error)) |
| 1543 | __i915_gem_request_retire__upto(req); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1544 | } |
| 1545 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1546 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1547 | * as the object state may change during this call. |
| 1548 | */ |
| 1549 | static __must_check int |
| 1550 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1551 | struct intel_rps_client *rps, |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1552 | bool readonly) |
| 1553 | { |
| 1554 | struct drm_device *dev = obj->base.dev; |
| 1555 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1556 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1557 | int ret, i, n = 0; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1558 | |
| 1559 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1560 | BUG_ON(!dev_priv->mm.interruptible); |
| 1561 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1562 | if (!obj->active) |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1563 | return 0; |
| 1564 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1565 | if (readonly) { |
| 1566 | struct drm_i915_gem_request *req; |
| 1567 | |
| 1568 | req = obj->last_write_req; |
| 1569 | if (req == NULL) |
| 1570 | return 0; |
| 1571 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1572 | requests[n++] = i915_gem_request_reference(req); |
| 1573 | } else { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1574 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1575 | struct drm_i915_gem_request *req; |
| 1576 | |
| 1577 | req = obj->last_read_req[i]; |
| 1578 | if (req == NULL) |
| 1579 | continue; |
| 1580 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1581 | requests[n++] = i915_gem_request_reference(req); |
| 1582 | } |
| 1583 | } |
| 1584 | |
| 1585 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 1586 | ret = 0; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1587 | for (i = 0; ret == 0 && i < n; i++) |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 1588 | ret = __i915_wait_request(requests[i], true, NULL, rps); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1589 | mutex_lock(&dev->struct_mutex); |
| 1590 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1591 | for (i = 0; i < n; i++) { |
| 1592 | if (ret == 0) |
| 1593 | i915_gem_object_retire_request(obj, requests[i]); |
| 1594 | i915_gem_request_unreference(requests[i]); |
| 1595 | } |
| 1596 | |
| 1597 | return ret; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1598 | } |
| 1599 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1600 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
| 1601 | { |
| 1602 | struct drm_i915_file_private *fpriv = file->driver_priv; |
| 1603 | return &fpriv->rps; |
| 1604 | } |
| 1605 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1606 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1607 | * Called when user space prepares to use an object with the CPU, either |
| 1608 | * through the mmap ioctl's mapping or a GTT mapping. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 1609 | * @dev: drm device |
| 1610 | * @data: ioctl data blob |
| 1611 | * @file: drm file |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1612 | */ |
| 1613 | int |
| 1614 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1615 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1616 | { |
| 1617 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1618 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1619 | uint32_t read_domains = args->read_domains; |
| 1620 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1621 | int ret; |
| 1622 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1623 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1624 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1625 | return -EINVAL; |
| 1626 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1627 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1628 | return -EINVAL; |
| 1629 | |
| 1630 | /* Having something in the write domain implies it's in the read |
| 1631 | * domain, and only that read domain. Enforce that in the request. |
| 1632 | */ |
| 1633 | if (write_domain != 0 && read_domains != write_domain) |
| 1634 | return -EINVAL; |
| 1635 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1636 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1637 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1638 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1639 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 1640 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1641 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1642 | ret = -ENOENT; |
| 1643 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1644 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1645 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1646 | /* Try to flush the object off the GPU without holding the lock. |
| 1647 | * We will repeat the flush holding the lock in the normal manner |
| 1648 | * to catch cases where we are gazumped. |
| 1649 | */ |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1650 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1651 | to_rps_client(file), |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1652 | !write_domain); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1653 | if (ret) |
| 1654 | goto unref; |
| 1655 | |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 1656 | if (read_domains & I915_GEM_DOMAIN_GTT) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1657 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 1658 | else |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1659 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1660 | |
Daniel Vetter | 031b698 | 2015-06-26 19:35:16 +0200 | [diff] [blame] | 1661 | if (write_domain != 0) |
| 1662 | intel_fb_obj_invalidate(obj, |
| 1663 | write_domain == I915_GEM_DOMAIN_GTT ? |
| 1664 | ORIGIN_GTT : ORIGIN_CPU); |
| 1665 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1666 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1667 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1668 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1669 | mutex_unlock(&dev->struct_mutex); |
| 1670 | return ret; |
| 1671 | } |
| 1672 | |
| 1673 | /** |
| 1674 | * Called when user space has done writes to this buffer |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 1675 | * @dev: drm device |
| 1676 | * @data: ioctl data blob |
| 1677 | * @file: drm file |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1678 | */ |
| 1679 | int |
| 1680 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1681 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1682 | { |
| 1683 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1684 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1685 | int ret = 0; |
| 1686 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1687 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1688 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1689 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1690 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 1691 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1692 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1693 | ret = -ENOENT; |
| 1694 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1695 | } |
| 1696 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1697 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1698 | if (obj->pin_display) |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 1699 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1700 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1701 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1702 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1703 | mutex_unlock(&dev->struct_mutex); |
| 1704 | return ret; |
| 1705 | } |
| 1706 | |
| 1707 | /** |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 1708 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
| 1709 | * it is mapped to. |
| 1710 | * @dev: drm device |
| 1711 | * @data: ioctl data blob |
| 1712 | * @file: drm file |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1713 | * |
| 1714 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1715 | * imply a ref on the object itself. |
Daniel Vetter | 3436738 | 2014-10-16 12:28:18 +0200 | [diff] [blame] | 1716 | * |
| 1717 | * IMPORTANT: |
| 1718 | * |
| 1719 | * DRM driver writers who look a this function as an example for how to do GEM |
| 1720 | * mmap support, please don't implement mmap support like here. The modern way |
| 1721 | * to implement DRM mmap support is with an mmap offset ioctl (like |
| 1722 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. |
| 1723 | * That way debug tooling like valgrind will understand what's going on, hiding |
| 1724 | * the mmap call in a driver private ioctl will break that. The i915 driver only |
| 1725 | * does cpu mmaps this way because we didn't know better. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1726 | */ |
| 1727 | int |
| 1728 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1729 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1730 | { |
| 1731 | struct drm_i915_gem_mmap *args = data; |
| 1732 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1733 | unsigned long addr; |
| 1734 | |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 1735 | if (args->flags & ~(I915_MMAP_WC)) |
| 1736 | return -EINVAL; |
| 1737 | |
Borislav Petkov | 568a58e | 2016-03-29 17:42:01 +0200 | [diff] [blame] | 1738 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 1739 | return -ENODEV; |
| 1740 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 1741 | obj = drm_gem_object_lookup(file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1742 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1743 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1744 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1745 | /* prime objects have no backing filp to GEM mmap |
| 1746 | * pages from. |
| 1747 | */ |
| 1748 | if (!obj->filp) { |
| 1749 | drm_gem_object_unreference_unlocked(obj); |
| 1750 | return -EINVAL; |
| 1751 | } |
| 1752 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1753 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1754 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1755 | args->offset); |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 1756 | if (args->flags & I915_MMAP_WC) { |
| 1757 | struct mm_struct *mm = current->mm; |
| 1758 | struct vm_area_struct *vma; |
| 1759 | |
Michal Hocko | 80a89a5 | 2016-05-23 16:26:11 -0700 | [diff] [blame] | 1760 | if (down_write_killable(&mm->mmap_sem)) { |
| 1761 | drm_gem_object_unreference_unlocked(obj); |
| 1762 | return -EINTR; |
| 1763 | } |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 1764 | vma = find_vma(mm, addr); |
| 1765 | if (vma) |
| 1766 | vma->vm_page_prot = |
| 1767 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); |
| 1768 | else |
| 1769 | addr = -ENOMEM; |
| 1770 | up_write(&mm->mmap_sem); |
| 1771 | } |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1772 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1773 | if (IS_ERR((void *)addr)) |
| 1774 | return addr; |
| 1775 | |
| 1776 | args->addr_ptr = (uint64_t) addr; |
| 1777 | |
| 1778 | return 0; |
| 1779 | } |
| 1780 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1781 | /** |
| 1782 | * i915_gem_fault - fault a page into the GTT |
Geliang Tang | d9072a3 | 2015-09-15 05:58:44 -0700 | [diff] [blame] | 1783 | * @vma: VMA in question |
| 1784 | * @vmf: fault info |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1785 | * |
| 1786 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1787 | * from userspace. The fault handler takes care of binding the object to |
| 1788 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1789 | * only if needed based on whether the old reg is still valid or the object |
| 1790 | * is tiled) and inserting a new PTE into the faulting process. |
| 1791 | * |
| 1792 | * Note that the faulting process may involve evicting existing objects |
| 1793 | * from the GTT and/or fence registers to make room. So performance may |
| 1794 | * suffer if the GTT working set is large or there are few fence registers |
| 1795 | * left. |
| 1796 | */ |
| 1797 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1798 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1799 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1800 | struct drm_device *dev = obj->base.dev; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 1801 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1802 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1803 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1804 | pgoff_t page_offset; |
| 1805 | unsigned long pfn; |
| 1806 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1807 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1808 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1809 | intel_runtime_pm_get(dev_priv); |
| 1810 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1811 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1812 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1813 | PAGE_SHIFT; |
| 1814 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1815 | ret = i915_mutex_lock_interruptible(dev); |
| 1816 | if (ret) |
| 1817 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1818 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1819 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1820 | |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1821 | /* Try to flush the object off the GPU first without holding the lock. |
| 1822 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1823 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1824 | * where we are gazumped. |
| 1825 | */ |
| 1826 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1827 | if (ret) |
| 1828 | goto unlock; |
| 1829 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1830 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1831 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
Chris Wilson | ddeff6e | 2014-05-28 16:16:41 +0100 | [diff] [blame] | 1832 | ret = -EFAULT; |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1833 | goto unlock; |
| 1834 | } |
| 1835 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1836 | /* Use a partial view if the object is bigger than the aperture. */ |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 1837 | if (obj->base.size >= ggtt->mappable_end && |
Joonas Lahtinen | e7ded2d | 2015-05-08 14:37:39 +0300 | [diff] [blame] | 1838 | obj->tiling_mode == I915_TILING_NONE) { |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1839 | static const unsigned int chunk_size = 256; // 1 MiB |
Joonas Lahtinen | e7ded2d | 2015-05-08 14:37:39 +0300 | [diff] [blame] | 1840 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1841 | memset(&view, 0, sizeof(view)); |
| 1842 | view.type = I915_GGTT_VIEW_PARTIAL; |
| 1843 | view.params.partial.offset = rounddown(page_offset, chunk_size); |
| 1844 | view.params.partial.size = |
| 1845 | min_t(unsigned int, |
| 1846 | chunk_size, |
| 1847 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - |
| 1848 | view.params.partial.offset); |
| 1849 | } |
| 1850 | |
| 1851 | /* Now pin it into the GTT if needed */ |
| 1852 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1853 | if (ret) |
| 1854 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1855 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1856 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1857 | if (ret) |
| 1858 | goto unpin; |
| 1859 | |
| 1860 | ret = i915_gem_object_get_fence(obj); |
| 1861 | if (ret) |
| 1862 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1863 | |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1864 | /* Finally, remap it using the new GTT offset */ |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 1865 | pfn = ggtt->mappable_base + |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1866 | i915_gem_obj_ggtt_offset_view(obj, &view); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1867 | pfn >>= PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1868 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1869 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
| 1870 | /* Overriding existing pages in partial view does not cause |
| 1871 | * us any trouble as TLBs are still valid because the fault |
| 1872 | * is due to userspace losing part of the mapping or never |
| 1873 | * having accessed it before (at this partials' range). |
| 1874 | */ |
| 1875 | unsigned long base = vma->vm_start + |
| 1876 | (view.params.partial.offset << PAGE_SHIFT); |
| 1877 | unsigned int i; |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1878 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1879 | for (i = 0; i < view.params.partial.size; i++) { |
| 1880 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1881 | if (ret) |
| 1882 | break; |
| 1883 | } |
| 1884 | |
| 1885 | obj->fault_mappable = true; |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1886 | } else { |
| 1887 | if (!obj->fault_mappable) { |
| 1888 | unsigned long size = min_t(unsigned long, |
| 1889 | vma->vm_end - vma->vm_start, |
| 1890 | obj->base.size); |
| 1891 | int i; |
| 1892 | |
| 1893 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
| 1894 | ret = vm_insert_pfn(vma, |
| 1895 | (unsigned long)vma->vm_start + i * PAGE_SIZE, |
| 1896 | pfn + i); |
| 1897 | if (ret) |
| 1898 | break; |
| 1899 | } |
| 1900 | |
| 1901 | obj->fault_mappable = true; |
| 1902 | } else |
| 1903 | ret = vm_insert_pfn(vma, |
| 1904 | (unsigned long)vmf->virtual_address, |
| 1905 | pfn + page_offset); |
| 1906 | } |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1907 | unpin: |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1908 | i915_gem_object_ggtt_unpin_view(obj, &view); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1909 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1910 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1911 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1912 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1913 | case -EIO: |
Daniel Vetter | 2232f03 | 2014-09-04 09:36:18 +0200 | [diff] [blame] | 1914 | /* |
| 1915 | * We eat errors when the gpu is terminally wedged to avoid |
| 1916 | * userspace unduly crashing (gl has no provisions for mmaps to |
| 1917 | * fail). But any other -EIO isn't ours (e.g. swap in failure) |
| 1918 | * and so needs to be reported. |
| 1919 | */ |
| 1920 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1921 | ret = VM_FAULT_SIGBUS; |
| 1922 | break; |
| 1923 | } |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1924 | case -EAGAIN: |
Daniel Vetter | 571c608 | 2013-09-12 17:57:28 +0200 | [diff] [blame] | 1925 | /* |
| 1926 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1927 | * handler to reset everything when re-faulting in |
| 1928 | * i915_mutex_lock_interruptible. |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1929 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1930 | case 0: |
| 1931 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1932 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1933 | case -EBUSY: |
| 1934 | /* |
| 1935 | * EBUSY is ok: this just means that another thread |
| 1936 | * already did the job. |
| 1937 | */ |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1938 | ret = VM_FAULT_NOPAGE; |
| 1939 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1940 | case -ENOMEM: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1941 | ret = VM_FAULT_OOM; |
| 1942 | break; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1943 | case -ENOSPC: |
Chris Wilson | 45d6781 | 2014-01-31 11:34:57 +0000 | [diff] [blame] | 1944 | case -EFAULT: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1945 | ret = VM_FAULT_SIGBUS; |
| 1946 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1947 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1948 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1949 | ret = VM_FAULT_SIGBUS; |
| 1950 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1951 | } |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1952 | |
| 1953 | intel_runtime_pm_put(dev_priv); |
| 1954 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1955 | } |
| 1956 | |
| 1957 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1958 | * i915_gem_release_mmap - remove physical page mappings |
| 1959 | * @obj: obj in question |
| 1960 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1961 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1962 | * relinquish ownership of the pages back to the system. |
| 1963 | * |
| 1964 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1965 | * object through the GTT and then lose the fence register due to |
| 1966 | * resource pressure. Similarly if the object has been moved out of the |
| 1967 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1968 | * mapping will then trigger a page fault on the next user access, allowing |
| 1969 | * fixup by i915_gem_fault(). |
| 1970 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1971 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1972 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1973 | { |
Chris Wilson | 349f2cc | 2016-04-13 17:35:12 +0100 | [diff] [blame] | 1974 | /* Serialisation between user GTT access and our code depends upon |
| 1975 | * revoking the CPU's PTE whilst the mutex is held. The next user |
| 1976 | * pagefault then has to wait until we release the mutex. |
| 1977 | */ |
| 1978 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
| 1979 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1980 | if (!obj->fault_mappable) |
| 1981 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1982 | |
David Herrmann | 6796cb1 | 2014-01-03 14:24:19 +0100 | [diff] [blame] | 1983 | drm_vma_node_unmap(&obj->base.vma_node, |
| 1984 | obj->base.dev->anon_inode->i_mapping); |
Chris Wilson | 349f2cc | 2016-04-13 17:35:12 +0100 | [diff] [blame] | 1985 | |
| 1986 | /* Ensure that the CPU's PTE are revoked and there are not outstanding |
| 1987 | * memory transactions from userspace before we return. The TLB |
| 1988 | * flushing implied above by changing the PTE above *should* be |
| 1989 | * sufficient, an extra barrier here just provides us with a bit |
| 1990 | * of paranoid documentation about our requirement to serialise |
| 1991 | * memory writes before touching registers / GSM. |
| 1992 | */ |
| 1993 | wmb(); |
| 1994 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1995 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1996 | } |
| 1997 | |
Chris Wilson | eedd10f | 2014-06-16 08:57:44 +0100 | [diff] [blame] | 1998 | void |
| 1999 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 2000 | { |
| 2001 | struct drm_i915_gem_object *obj; |
| 2002 | |
| 2003 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 2004 | i915_gem_release_mmap(obj); |
| 2005 | } |
| 2006 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 2007 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2008 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 2009 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2010 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 2011 | |
| 2012 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2013 | tiling_mode == I915_TILING_NONE) |
| 2014 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 2015 | |
| 2016 | /* Previous chips need a power-of-two fence region when tiling */ |
Tvrtko Ursulin | 7e22dbb | 2016-05-10 10:57:06 +0100 | [diff] [blame] | 2017 | if (IS_GEN3(dev)) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2018 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 2019 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2020 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 2021 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2022 | while (gtt_size < size) |
| 2023 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 2024 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2025 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 2026 | } |
| 2027 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2028 | /** |
| 2029 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 2030 | * @dev: drm device |
| 2031 | * @size: object size |
| 2032 | * @tiling_mode: tiling mode |
| 2033 | * @fenced: is fenced alignemned required or not |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2034 | * |
| 2035 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2036 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2037 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2038 | uint32_t |
| 2039 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 2040 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2041 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2042 | /* |
| 2043 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 2044 | * if a fence register is needed for the object. |
| 2045 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2046 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2047 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2048 | return 4096; |
| 2049 | |
| 2050 | /* |
| 2051 | * Previous chips need to be aligned to the size of the smallest |
| 2052 | * fence register that can contain the object. |
| 2053 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2054 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2055 | } |
| 2056 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2057 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 2058 | { |
| 2059 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2060 | int ret; |
| 2061 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2062 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 2063 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2064 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2065 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2066 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2067 | |
| 2068 | /* Badly fragmented mmap space? The only way we can recover |
| 2069 | * space is by destroying unwanted objects. We can't randomly release |
| 2070 | * mmap_offsets as userspace expects them to be persistent for the |
| 2071 | * lifetime of the objects. The closest we can is to release the |
| 2072 | * offsets on purgeable objects by truncating it and marking it purged, |
| 2073 | * which prevents userspace from ever using that object again. |
| 2074 | */ |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2075 | i915_gem_shrink(dev_priv, |
| 2076 | obj->base.size >> PAGE_SHIFT, |
| 2077 | I915_SHRINK_BOUND | |
| 2078 | I915_SHRINK_UNBOUND | |
| 2079 | I915_SHRINK_PURGEABLE); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2080 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2081 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2082 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2083 | |
| 2084 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2085 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2086 | out: |
| 2087 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 2088 | |
| 2089 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2090 | } |
| 2091 | |
| 2092 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 2093 | { |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2094 | drm_gem_free_mmap_offset(&obj->base); |
| 2095 | } |
| 2096 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2097 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2098 | i915_gem_mmap_gtt(struct drm_file *file, |
| 2099 | struct drm_device *dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2100 | uint32_t handle, |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2101 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2102 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2103 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2104 | int ret; |
| 2105 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 2106 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2107 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 2108 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2109 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 2110 | obj = to_intel_bo(drm_gem_object_lookup(file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 2111 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2112 | ret = -ENOENT; |
| 2113 | goto unlock; |
| 2114 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2115 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2116 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 2117 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 2118 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2119 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 2120 | } |
| 2121 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2122 | ret = i915_gem_object_create_mmap_offset(obj); |
| 2123 | if (ret) |
| 2124 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2125 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 2126 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2127 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2128 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2129 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2130 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2131 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2132 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2133 | } |
| 2134 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2135 | /** |
| 2136 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 2137 | * @dev: DRM device |
| 2138 | * @data: GTT mapping ioctl data |
| 2139 | * @file: GEM object info |
| 2140 | * |
| 2141 | * Simply returns the fake offset to userspace so it can mmap it. |
| 2142 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 2143 | * up so we can get faults in the handler above. |
| 2144 | * |
| 2145 | * The fault handler will take care of binding the object into the GTT |
| 2146 | * (since it may have been evicted to make room for something), allocating |
| 2147 | * a fence register, and mapping the appropriate aperture address into |
| 2148 | * userspace. |
| 2149 | */ |
| 2150 | int |
| 2151 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 2152 | struct drm_file *file) |
| 2153 | { |
| 2154 | struct drm_i915_gem_mmap_gtt *args = data; |
| 2155 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2156 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2157 | } |
| 2158 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2159 | /* Immediately discard the backing storage */ |
| 2160 | static void |
| 2161 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2162 | { |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 2163 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2164 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 2165 | if (obj->base.filp == NULL) |
| 2166 | return; |
| 2167 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2168 | /* Our goal here is to return as much of the memory as |
| 2169 | * is possible back to the system as we are called from OOM. |
| 2170 | * To do this we must instruct the shmfs to drop all of its |
| 2171 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2172 | */ |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2173 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2174 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2175 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2176 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2177 | /* Try to discard unwanted pages */ |
| 2178 | static void |
| 2179 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2180 | { |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2181 | struct address_space *mapping; |
| 2182 | |
| 2183 | switch (obj->madv) { |
| 2184 | case I915_MADV_DONTNEED: |
| 2185 | i915_gem_object_truncate(obj); |
| 2186 | case __I915_MADV_PURGED: |
| 2187 | return; |
| 2188 | } |
| 2189 | |
| 2190 | if (obj->base.filp == NULL) |
| 2191 | return; |
| 2192 | |
| 2193 | mapping = file_inode(obj->base.filp)->i_mapping, |
| 2194 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2195 | } |
| 2196 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 2197 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2198 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2199 | { |
Dave Gordon | 85d1225 | 2016-05-20 11:54:06 +0100 | [diff] [blame] | 2200 | struct sgt_iter sgt_iter; |
| 2201 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2202 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2203 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2204 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2205 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2206 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 2207 | if (WARN_ON(ret)) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2208 | /* In the event of a disaster, abandon all caches and |
| 2209 | * hope for the best. |
| 2210 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 2211 | i915_gem_clflush_object(obj, true); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2212 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2213 | } |
| 2214 | |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2215 | i915_gem_gtt_finish_object(obj); |
| 2216 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 2217 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2218 | i915_gem_object_save_bit_17_swizzle(obj); |
| 2219 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2220 | if (obj->madv == I915_MADV_DONTNEED) |
| 2221 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2222 | |
Dave Gordon | 85d1225 | 2016-05-20 11:54:06 +0100 | [diff] [blame] | 2223 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2224 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2225 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2226 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2227 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2228 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2229 | |
Kirill A. Shutemov | 09cbfea | 2016-04-01 15:29:47 +0300 | [diff] [blame] | 2230 | put_page(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2231 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2232 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2233 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2234 | sg_free_table(obj->pages); |
| 2235 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2236 | } |
| 2237 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2238 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2239 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 2240 | { |
| 2241 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2242 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 2243 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2244 | return 0; |
| 2245 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2246 | if (obj->pages_pin_count) |
| 2247 | return -EBUSY; |
| 2248 | |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 2249 | BUG_ON(i915_gem_obj_bound_any(obj)); |
Ben Widawsky | 3e12302 | 2013-07-31 17:00:04 -0700 | [diff] [blame] | 2250 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 2251 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 2252 | * array, hence protect them from being reaped by removing them from gtt |
| 2253 | * lists early. */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2254 | list_del(&obj->global_list); |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 2255 | |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2256 | if (obj->mapping) { |
Chris Wilson | fb8621d | 2016-04-08 12:11:14 +0100 | [diff] [blame] | 2257 | if (is_vmalloc_addr(obj->mapping)) |
| 2258 | vunmap(obj->mapping); |
| 2259 | else |
| 2260 | kunmap(kmap_to_page(obj->mapping)); |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2261 | obj->mapping = NULL; |
| 2262 | } |
| 2263 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2264 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2265 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2266 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2267 | i915_gem_object_invalidate(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2268 | |
| 2269 | return 0; |
| 2270 | } |
| 2271 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2272 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2273 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2274 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2275 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2276 | int page_count, i; |
| 2277 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2278 | struct sg_table *st; |
| 2279 | struct scatterlist *sg; |
Dave Gordon | 85d1225 | 2016-05-20 11:54:06 +0100 | [diff] [blame] | 2280 | struct sgt_iter sgt_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2281 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2282 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2283 | int ret; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2284 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2285 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2286 | /* Assert that the object is not currently in any GPU domain. As it |
| 2287 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2288 | * a GPU cache |
| 2289 | */ |
| 2290 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2291 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 2292 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2293 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2294 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2295 | return -ENOMEM; |
| 2296 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2297 | page_count = obj->base.size / PAGE_SIZE; |
| 2298 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2299 | kfree(st); |
| 2300 | return -ENOMEM; |
| 2301 | } |
| 2302 | |
| 2303 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2304 | * at this point until we release them. |
| 2305 | * |
| 2306 | * Fail silently without starting the shrinker |
| 2307 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 2308 | mapping = file_inode(obj->base.filp)->i_mapping; |
Michal Hocko | c62d255 | 2015-11-06 16:28:49 -0800 | [diff] [blame] | 2309 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
Mel Gorman | d0164ad | 2015-11-06 16:28:21 -0800 | [diff] [blame] | 2310 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2311 | sg = st->sgl; |
| 2312 | st->nents = 0; |
| 2313 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2314 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2315 | if (IS_ERR(page)) { |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2316 | i915_gem_shrink(dev_priv, |
| 2317 | page_count, |
| 2318 | I915_SHRINK_BOUND | |
| 2319 | I915_SHRINK_UNBOUND | |
| 2320 | I915_SHRINK_PURGEABLE); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2321 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2322 | } |
| 2323 | if (IS_ERR(page)) { |
| 2324 | /* We've tried hard to allocate the memory by reaping |
| 2325 | * our own buffer, now let the real VM do its job and |
| 2326 | * go down in flames if truly OOM. |
| 2327 | */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2328 | i915_gem_shrink_all(dev_priv); |
David Herrmann | f461d1b | 2014-05-25 14:34:10 +0200 | [diff] [blame] | 2329 | page = shmem_read_mapping_page(mapping, i); |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2330 | if (IS_ERR(page)) { |
| 2331 | ret = PTR_ERR(page); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2332 | goto err_pages; |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2333 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2334 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2335 | #ifdef CONFIG_SWIOTLB |
| 2336 | if (swiotlb_nr_tbl()) { |
| 2337 | st->nents++; |
| 2338 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2339 | sg = sg_next(sg); |
| 2340 | continue; |
| 2341 | } |
| 2342 | #endif |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2343 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 2344 | if (i) |
| 2345 | sg = sg_next(sg); |
| 2346 | st->nents++; |
| 2347 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2348 | } else { |
| 2349 | sg->length += PAGE_SIZE; |
| 2350 | } |
| 2351 | last_pfn = page_to_pfn(page); |
Daniel Vetter | 3bbbe70 | 2013-10-07 17:15:45 -0300 | [diff] [blame] | 2352 | |
| 2353 | /* Check that the i965g/gm workaround works. */ |
| 2354 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2355 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2356 | #ifdef CONFIG_SWIOTLB |
| 2357 | if (!swiotlb_nr_tbl()) |
| 2358 | #endif |
| 2359 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 2360 | obj->pages = st; |
| 2361 | |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2362 | ret = i915_gem_gtt_prepare_object(obj); |
| 2363 | if (ret) |
| 2364 | goto err_pages; |
| 2365 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2366 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2367 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2368 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2369 | if (obj->tiling_mode != I915_TILING_NONE && |
| 2370 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2371 | i915_gem_object_pin_pages(obj); |
| 2372 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2373 | return 0; |
| 2374 | |
| 2375 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2376 | sg_mark_end(sg); |
Dave Gordon | 85d1225 | 2016-05-20 11:54:06 +0100 | [diff] [blame] | 2377 | for_each_sgt_page(page, sgt_iter, st) |
| 2378 | put_page(page); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2379 | sg_free_table(st); |
| 2380 | kfree(st); |
Chris Wilson | 0820baf | 2014-03-25 13:23:03 +0000 | [diff] [blame] | 2381 | |
| 2382 | /* shmemfs first checks if there is enough memory to allocate the page |
| 2383 | * and reports ENOSPC should there be insufficient, along with the usual |
| 2384 | * ENOMEM for a genuine allocation failure. |
| 2385 | * |
| 2386 | * We use ENOSPC in our driver to mean that we have run out of aperture |
| 2387 | * space and so want to translate the error from shmemfs back to our |
| 2388 | * usual understanding of ENOMEM. |
| 2389 | */ |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2390 | if (ret == -ENOSPC) |
| 2391 | ret = -ENOMEM; |
| 2392 | |
| 2393 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2394 | } |
| 2395 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2396 | /* Ensure that the associated pages are gathered from the backing storage |
| 2397 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 2398 | * multiple times before they are released by a single call to |
| 2399 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 2400 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 2401 | * or as the object is itself released. |
| 2402 | */ |
| 2403 | int |
| 2404 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 2405 | { |
| 2406 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2407 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2408 | int ret; |
| 2409 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 2410 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2411 | return 0; |
| 2412 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2413 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 2414 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 2415 | return -EFAULT; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2416 | } |
| 2417 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2418 | BUG_ON(obj->pages_pin_count); |
| 2419 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2420 | ret = ops->get_pages(obj); |
| 2421 | if (ret) |
| 2422 | return ret; |
| 2423 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2424 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Chris Wilson | ee28637 | 2015-04-07 16:20:25 +0100 | [diff] [blame] | 2425 | |
| 2426 | obj->get_page.sg = obj->pages->sgl; |
| 2427 | obj->get_page.last = 0; |
| 2428 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2429 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2430 | } |
| 2431 | |
Dave Gordon | dd6034c | 2016-05-20 11:54:04 +0100 | [diff] [blame] | 2432 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
| 2433 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj) |
| 2434 | { |
| 2435 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; |
| 2436 | struct sg_table *sgt = obj->pages; |
Dave Gordon | 85d1225 | 2016-05-20 11:54:06 +0100 | [diff] [blame] | 2437 | struct sgt_iter sgt_iter; |
| 2438 | struct page *page; |
Dave Gordon | b338fa4 | 2016-05-20 11:54:05 +0100 | [diff] [blame] | 2439 | struct page *stack_pages[32]; |
| 2440 | struct page **pages = stack_pages; |
Dave Gordon | dd6034c | 2016-05-20 11:54:04 +0100 | [diff] [blame] | 2441 | unsigned long i = 0; |
| 2442 | void *addr; |
| 2443 | |
| 2444 | /* A single page can always be kmapped */ |
| 2445 | if (n_pages == 1) |
| 2446 | return kmap(sg_page(sgt->sgl)); |
| 2447 | |
Dave Gordon | b338fa4 | 2016-05-20 11:54:05 +0100 | [diff] [blame] | 2448 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
| 2449 | /* Too big for stack -- allocate temporary array instead */ |
| 2450 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); |
| 2451 | if (!pages) |
| 2452 | return NULL; |
| 2453 | } |
Dave Gordon | dd6034c | 2016-05-20 11:54:04 +0100 | [diff] [blame] | 2454 | |
Dave Gordon | 85d1225 | 2016-05-20 11:54:06 +0100 | [diff] [blame] | 2455 | for_each_sgt_page(page, sgt_iter, sgt) |
| 2456 | pages[i++] = page; |
Dave Gordon | dd6034c | 2016-05-20 11:54:04 +0100 | [diff] [blame] | 2457 | |
| 2458 | /* Check that we have the expected number of pages */ |
| 2459 | GEM_BUG_ON(i != n_pages); |
| 2460 | |
| 2461 | addr = vmap(pages, n_pages, 0, PAGE_KERNEL); |
| 2462 | |
Dave Gordon | b338fa4 | 2016-05-20 11:54:05 +0100 | [diff] [blame] | 2463 | if (pages != stack_pages) |
| 2464 | drm_free_large(pages); |
Dave Gordon | dd6034c | 2016-05-20 11:54:04 +0100 | [diff] [blame] | 2465 | |
| 2466 | return addr; |
| 2467 | } |
| 2468 | |
| 2469 | /* get, pin, and map the pages of the object into kernel space */ |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2470 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
| 2471 | { |
| 2472 | int ret; |
| 2473 | |
| 2474 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
| 2475 | |
| 2476 | ret = i915_gem_object_get_pages(obj); |
| 2477 | if (ret) |
| 2478 | return ERR_PTR(ret); |
| 2479 | |
| 2480 | i915_gem_object_pin_pages(obj); |
| 2481 | |
Dave Gordon | dd6034c | 2016-05-20 11:54:04 +0100 | [diff] [blame] | 2482 | if (!obj->mapping) { |
| 2483 | obj->mapping = i915_gem_object_map(obj); |
| 2484 | if (!obj->mapping) { |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2485 | i915_gem_object_unpin_pages(obj); |
| 2486 | return ERR_PTR(-ENOMEM); |
| 2487 | } |
| 2488 | } |
| 2489 | |
| 2490 | return obj->mapping; |
| 2491 | } |
| 2492 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2493 | void i915_vma_move_to_active(struct i915_vma *vma, |
John Harrison | b2af037 | 2015-05-29 17:43:50 +0100 | [diff] [blame] | 2494 | struct drm_i915_gem_request *req) |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2495 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2496 | struct drm_i915_gem_object *obj = vma->obj; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2497 | struct intel_engine_cs *engine; |
John Harrison | b2af037 | 2015-05-29 17:43:50 +0100 | [diff] [blame] | 2498 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2499 | engine = i915_gem_request_get_engine(req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2500 | |
| 2501 | /* Add a reference if we're newly entering the active list. */ |
| 2502 | if (obj->active == 0) |
| 2503 | drm_gem_object_reference(&obj->base); |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2504 | obj->active |= intel_engine_flag(engine); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2505 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2506 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2507 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2508 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 2509 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2510 | } |
| 2511 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2512 | static void |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2513 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) |
| 2514 | { |
Chris Wilson | d501b1d | 2016-04-13 17:35:02 +0100 | [diff] [blame] | 2515 | GEM_BUG_ON(obj->last_write_req == NULL); |
| 2516 | GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2517 | |
| 2518 | i915_gem_request_assign(&obj->last_write_req, NULL); |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 2519 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2520 | } |
| 2521 | |
| 2522 | static void |
| 2523 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2524 | { |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2525 | struct i915_vma *vma; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2526 | |
Chris Wilson | d501b1d | 2016-04-13 17:35:02 +0100 | [diff] [blame] | 2527 | GEM_BUG_ON(obj->last_read_req[ring] == NULL); |
| 2528 | GEM_BUG_ON(!(obj->active & (1 << ring))); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2529 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2530 | list_del_init(&obj->engine_list[ring]); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2531 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
| 2532 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2533 | if (obj->last_write_req && obj->last_write_req->engine->id == ring) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2534 | i915_gem_object_retire__write(obj); |
| 2535 | |
| 2536 | obj->active &= ~(1 << ring); |
| 2537 | if (obj->active) |
| 2538 | return; |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2539 | |
Chris Wilson | 6c24695 | 2015-07-27 10:26:26 +0100 | [diff] [blame] | 2540 | /* Bump our place on the bound list to keep it roughly in LRU order |
| 2541 | * so that we don't steal from recently used but inactive objects |
| 2542 | * (unless we are forced to ofc!) |
| 2543 | */ |
| 2544 | list_move_tail(&obj->global_list, |
| 2545 | &to_i915(obj->base.dev)->mm.bound_list); |
| 2546 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 2547 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
| 2548 | if (!list_empty(&vma->vm_link)) |
| 2549 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2550 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2551 | |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 2552 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2553 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2554 | } |
| 2555 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2556 | static int |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2557 | i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2558 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2559 | struct intel_engine_cs *engine; |
Chris Wilson | 29dcb57 | 2016-04-07 07:29:13 +0100 | [diff] [blame] | 2560 | int ret; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2561 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2562 | /* Carefully retire all requests without writing to the rings */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2563 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2564 | ret = intel_engine_idle(engine); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2565 | if (ret) |
| 2566 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2567 | } |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2568 | i915_gem_retire_requests(dev_priv); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2569 | |
| 2570 | /* Finally reset hw state */ |
Chris Wilson | 29dcb57 | 2016-04-07 07:29:13 +0100 | [diff] [blame] | 2571 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2572 | intel_ring_init_seqno(engine, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2573 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2574 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2575 | } |
| 2576 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2577 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2578 | { |
| 2579 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2580 | int ret; |
| 2581 | |
| 2582 | if (seqno == 0) |
| 2583 | return -EINVAL; |
| 2584 | |
| 2585 | /* HWS page needs to be set less than what we |
| 2586 | * will inject to ring |
| 2587 | */ |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2588 | ret = i915_gem_init_seqno(dev_priv, seqno - 1); |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2589 | if (ret) |
| 2590 | return ret; |
| 2591 | |
| 2592 | /* Carefully set the last_seqno value so that wrap |
| 2593 | * detection still works |
| 2594 | */ |
| 2595 | dev_priv->next_seqno = seqno; |
| 2596 | dev_priv->last_seqno = seqno - 1; |
| 2597 | if (dev_priv->last_seqno == 0) |
| 2598 | dev_priv->last_seqno--; |
| 2599 | |
| 2600 | return 0; |
| 2601 | } |
| 2602 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2603 | int |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2604 | i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2605 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2606 | /* reserve 0 for non-seqno */ |
| 2607 | if (dev_priv->next_seqno == 0) { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2608 | int ret = i915_gem_init_seqno(dev_priv, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2609 | if (ret) |
| 2610 | return ret; |
| 2611 | |
| 2612 | dev_priv->next_seqno = 1; |
| 2613 | } |
| 2614 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 2615 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2616 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2617 | } |
| 2618 | |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2619 | /* |
| 2620 | * NB: This function is not allowed to fail. Doing so would mean the the |
| 2621 | * request is not being tracked for completion but the work itself is |
| 2622 | * going to happen on the hardware. This would be a Bad Thing(tm). |
| 2623 | */ |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 2624 | void __i915_add_request(struct drm_i915_gem_request *request, |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2625 | struct drm_i915_gem_object *obj, |
| 2626 | bool flush_caches) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2627 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2628 | struct intel_engine_cs *engine; |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 2629 | struct drm_i915_private *dev_priv; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2630 | struct intel_ringbuffer *ringbuf; |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2631 | u32 request_start; |
Chris Wilson | 0251a96 | 2016-04-28 09:56:47 +0100 | [diff] [blame] | 2632 | u32 reserved_tail; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2633 | int ret; |
| 2634 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2635 | if (WARN_ON(request == NULL)) |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2636 | return; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2637 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2638 | engine = request->engine; |
Tvrtko Ursulin | 39dabec | 2016-03-17 13:04:10 +0000 | [diff] [blame] | 2639 | dev_priv = request->i915; |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 2640 | ringbuf = request->ringbuf; |
| 2641 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2642 | /* |
| 2643 | * To ensure that this call will not fail, space for its emissions |
| 2644 | * should already have been reserved in the ring buffer. Let the ring |
| 2645 | * know that it is time to use that space up. |
| 2646 | */ |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2647 | request_start = intel_ring_get_tail(ringbuf); |
Chris Wilson | 0251a96 | 2016-04-28 09:56:47 +0100 | [diff] [blame] | 2648 | reserved_tail = request->reserved_space; |
| 2649 | request->reserved_space = 0; |
| 2650 | |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2651 | /* |
| 2652 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2653 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2654 | * things up similar to emitting the lazy request. The difference here |
| 2655 | * is that the flush _must_ happen before the next request, no matter |
| 2656 | * what. |
| 2657 | */ |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2658 | if (flush_caches) { |
| 2659 | if (i915.enable_execlists) |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 2660 | ret = logical_ring_flush_all_caches(request); |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2661 | else |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 2662 | ret = intel_ring_flush_all_caches(request); |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2663 | /* Not allowed to fail! */ |
| 2664 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); |
| 2665 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2666 | |
Chris Wilson | 7c90b7d | 2016-04-07 07:29:17 +0100 | [diff] [blame] | 2667 | trace_i915_gem_request_add(request); |
| 2668 | |
| 2669 | request->head = request_start; |
| 2670 | |
| 2671 | /* Whilst this request exists, batch_obj will be on the |
| 2672 | * active_list, and so will hold the active reference. Only when this |
| 2673 | * request is retired will the the batch_obj be moved onto the |
| 2674 | * inactive_list and lose its active reference. Hence we do not need |
| 2675 | * to explicitly hold another reference here. |
| 2676 | */ |
| 2677 | request->batch_obj = obj; |
| 2678 | |
| 2679 | /* Seal the request and mark it as pending execution. Note that |
| 2680 | * we may inspect this state, without holding any locks, during |
| 2681 | * hangcheck. Hence we apply the barrier to ensure that we do not |
| 2682 | * see a more recent value in the hws than we are tracking. |
| 2683 | */ |
| 2684 | request->emitted_jiffies = jiffies; |
| 2685 | request->previous_seqno = engine->last_submitted_seqno; |
| 2686 | smp_store_mb(engine->last_submitted_seqno, request->seqno); |
| 2687 | list_add_tail(&request->list, &engine->request_list); |
| 2688 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2689 | /* Record the position of the start of the request so that |
| 2690 | * should we detect the updated seqno part-way through the |
| 2691 | * GPU processing the request, we never over-estimate the |
| 2692 | * position of the head. |
| 2693 | */ |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2694 | request->postfix = intel_ring_get_tail(ringbuf); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2695 | |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2696 | if (i915.enable_execlists) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2697 | ret = engine->emit_request(request); |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2698 | else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2699 | ret = engine->add_request(request); |
Michel Thierry | 53292cd | 2015-04-15 18:11:33 +0100 | [diff] [blame] | 2700 | |
| 2701 | request->tail = intel_ring_get_tail(ringbuf); |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2702 | } |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2703 | /* Not allowed to fail! */ |
| 2704 | WARN(ret, "emit|add_request failed: %d!\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2705 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2706 | i915_queue_hangcheck(engine->i915); |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2707 | |
Daniel Vetter | 8725548 | 2014-11-19 20:36:48 +0100 | [diff] [blame] | 2708 | queue_delayed_work(dev_priv->wq, |
| 2709 | &dev_priv->mm.retire_work, |
| 2710 | round_jiffies_up_relative(HZ)); |
Tvrtko Ursulin | 7d99373 | 2016-04-28 12:57:00 +0100 | [diff] [blame] | 2711 | intel_mark_busy(dev_priv); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2712 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2713 | /* Sanity check that the reserved size was large enough. */ |
Chris Wilson | 0251a96 | 2016-04-28 09:56:47 +0100 | [diff] [blame] | 2714 | ret = intel_ring_get_tail(ringbuf) - request_start; |
| 2715 | if (ret < 0) |
| 2716 | ret += ringbuf->size; |
| 2717 | WARN_ONCE(ret > reserved_tail, |
| 2718 | "Not enough space reserved (%d bytes) " |
| 2719 | "for adding the request (%d bytes)\n", |
| 2720 | reserved_tail, ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2721 | } |
| 2722 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2723 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 2724 | const struct i915_gem_context *ctx) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2725 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2726 | unsigned long elapsed; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2727 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2728 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2729 | |
| 2730 | if (ctx->hang_stats.banned) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2731 | return true; |
| 2732 | |
Chris Wilson | 676fa57 | 2014-12-24 08:13:39 -0800 | [diff] [blame] | 2733 | if (ctx->hang_stats.ban_period_seconds && |
| 2734 | elapsed <= ctx->hang_stats.ban_period_seconds) { |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2735 | if (!i915_gem_context_is_default(ctx)) { |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2736 | DRM_DEBUG("context hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2737 | return true; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 2738 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
| 2739 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 2740 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2741 | return true; |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2742 | } |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2743 | } |
| 2744 | |
| 2745 | return false; |
| 2746 | } |
| 2747 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2748 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 2749 | struct i915_gem_context *ctx, |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2750 | const bool guilty) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2751 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2752 | struct i915_ctx_hang_stats *hs; |
| 2753 | |
| 2754 | if (WARN_ON(!ctx)) |
| 2755 | return; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2756 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2757 | hs = &ctx->hang_stats; |
| 2758 | |
| 2759 | if (guilty) { |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2760 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2761 | hs->batch_active++; |
| 2762 | hs->guilty_ts = get_seconds(); |
| 2763 | } else { |
| 2764 | hs->batch_pending++; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2765 | } |
| 2766 | } |
| 2767 | |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2768 | void i915_gem_request_free(struct kref *req_ref) |
| 2769 | { |
| 2770 | struct drm_i915_gem_request *req = container_of(req_ref, |
| 2771 | typeof(*req), ref); |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 2772 | kmem_cache_free(req->i915->requests, req); |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2773 | } |
| 2774 | |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2775 | static inline int |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2776 | __i915_gem_request_alloc(struct intel_engine_cs *engine, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 2777 | struct i915_gem_context *ctx, |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2778 | struct drm_i915_gem_request **req_out) |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2779 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2780 | struct drm_i915_private *dev_priv = engine->i915; |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 2781 | unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2782 | struct drm_i915_gem_request *req; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2783 | int ret; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2784 | |
John Harrison | 217e46b | 2015-05-29 17:43:29 +0100 | [diff] [blame] | 2785 | if (!req_out) |
| 2786 | return -EINVAL; |
| 2787 | |
John Harrison | bccca49 | 2015-05-29 17:44:11 +0100 | [diff] [blame] | 2788 | *req_out = NULL; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2789 | |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 2790 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
| 2791 | * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex |
| 2792 | * and restart. |
| 2793 | */ |
| 2794 | ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 2795 | if (ret) |
| 2796 | return ret; |
| 2797 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2798 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
| 2799 | if (req == NULL) |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2800 | return -ENOMEM; |
| 2801 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2802 | ret = i915_gem_get_seqno(engine->i915, &req->seqno); |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2803 | if (ret) |
| 2804 | goto err; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2805 | |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2806 | kref_init(&req->ref); |
| 2807 | req->i915 = dev_priv; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2808 | req->engine = engine; |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 2809 | req->reset_counter = reset_counter; |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2810 | req->ctx = ctx; |
| 2811 | i915_gem_context_reference(req->ctx); |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2812 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2813 | /* |
| 2814 | * Reserve space in the ring buffer for all the commands required to |
| 2815 | * eventually emit this request. This is to guarantee that the |
| 2816 | * i915_add_request() call can't fail. Note that the reserve may need |
| 2817 | * to be redone if the request is not actually submitted straight |
| 2818 | * away, e.g. because a GPU scheduler has deferred it. |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2819 | */ |
Chris Wilson | 0251a96 | 2016-04-28 09:56:47 +0100 | [diff] [blame] | 2820 | req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; |
Chris Wilson | bfa0120 | 2016-04-28 09:56:48 +0100 | [diff] [blame] | 2821 | |
| 2822 | if (i915.enable_execlists) |
| 2823 | ret = intel_logical_ring_alloc_request_extras(req); |
| 2824 | else |
| 2825 | ret = intel_ring_alloc_request_extras(req); |
| 2826 | if (ret) |
| 2827 | goto err_ctx; |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2828 | |
John Harrison | bccca49 | 2015-05-29 17:44:11 +0100 | [diff] [blame] | 2829 | *req_out = req; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2830 | return 0; |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2831 | |
Chris Wilson | bfa0120 | 2016-04-28 09:56:48 +0100 | [diff] [blame] | 2832 | err_ctx: |
| 2833 | i915_gem_context_unreference(ctx); |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2834 | err: |
| 2835 | kmem_cache_free(dev_priv->requests, req); |
| 2836 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2837 | } |
| 2838 | |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2839 | /** |
| 2840 | * i915_gem_request_alloc - allocate a request structure |
| 2841 | * |
| 2842 | * @engine: engine that we wish to issue the request on. |
| 2843 | * @ctx: context that the request will be associated with. |
| 2844 | * This can be NULL if the request is not directly related to |
| 2845 | * any specific user context, in which case this function will |
| 2846 | * choose an appropriate context to use. |
| 2847 | * |
| 2848 | * Returns a pointer to the allocated request if successful, |
| 2849 | * or an error code if not. |
| 2850 | */ |
| 2851 | struct drm_i915_gem_request * |
| 2852 | i915_gem_request_alloc(struct intel_engine_cs *engine, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 2853 | struct i915_gem_context *ctx) |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2854 | { |
| 2855 | struct drm_i915_gem_request *req; |
| 2856 | int err; |
| 2857 | |
| 2858 | if (ctx == NULL) |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 2859 | ctx = engine->i915->kernel_context; |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2860 | err = __i915_gem_request_alloc(engine, ctx, &req); |
| 2861 | return err ? ERR_PTR(err) : req; |
| 2862 | } |
| 2863 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2864 | struct drm_i915_gem_request * |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2865 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2866 | { |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2867 | struct drm_i915_gem_request *request; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2868 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2869 | list_for_each_entry(request, &engine->request_list, list) { |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 2870 | if (i915_gem_request_completed(request, false)) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2871 | continue; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2872 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2873 | return request; |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2874 | } |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2875 | |
| 2876 | return NULL; |
| 2877 | } |
| 2878 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2879 | static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2880 | struct intel_engine_cs *engine) |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2881 | { |
| 2882 | struct drm_i915_gem_request *request; |
| 2883 | bool ring_hung; |
| 2884 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2885 | request = i915_gem_find_active_request(engine); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2886 | |
| 2887 | if (request == NULL) |
| 2888 | return; |
| 2889 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2890 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2891 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2892 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2893 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2894 | list_for_each_entry_continue(request, &engine->request_list, list) |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2895 | i915_set_reset_status(dev_priv, request->ctx, false); |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2896 | } |
| 2897 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2898 | static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2899 | struct intel_engine_cs *engine) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2900 | { |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2901 | struct intel_ringbuffer *buffer; |
| 2902 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2903 | while (!list_empty(&engine->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2904 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2905 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2906 | obj = list_first_entry(&engine->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2907 | struct drm_i915_gem_object, |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2908 | engine_list[engine->id]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2909 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2910 | i915_gem_object_retire__read(obj, engine->id); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2911 | } |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2912 | |
| 2913 | /* |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2914 | * Clear the execlists queue up before freeing the requests, as those |
| 2915 | * are the ones that keep the context and ringbuffer backing objects |
| 2916 | * pinned in place. |
| 2917 | */ |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2918 | |
Tomas Elf | 7de1691 | 2015-10-19 16:32:32 +0100 | [diff] [blame] | 2919 | if (i915.enable_execlists) { |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 2920 | /* Ensure irq handler finishes or is cancelled. */ |
| 2921 | tasklet_kill(&engine->irq_tasklet); |
Mika Kuoppala | 1197b4f | 2015-01-13 11:32:24 +0200 | [diff] [blame] | 2922 | |
Tvrtko Ursulin | e39d42f | 2016-04-28 09:56:58 +0100 | [diff] [blame] | 2923 | intel_execlists_cancel_requests(engine); |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2924 | } |
| 2925 | |
| 2926 | /* |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2927 | * We must free the requests after all the corresponding objects have |
| 2928 | * been moved off active lists. Which is the same order as the normal |
| 2929 | * retire_requests function does. This is important if object hold |
| 2930 | * implicit references on things like e.g. ppgtt address spaces through |
| 2931 | * the request. |
| 2932 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2933 | while (!list_empty(&engine->request_list)) { |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2934 | struct drm_i915_gem_request *request; |
| 2935 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2936 | request = list_first_entry(&engine->request_list, |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2937 | struct drm_i915_gem_request, |
| 2938 | list); |
| 2939 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2940 | i915_gem_request_retire(request); |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2941 | } |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2942 | |
| 2943 | /* Having flushed all requests from all queues, we know that all |
| 2944 | * ringbuffers must now be empty. However, since we do not reclaim |
| 2945 | * all space when retiring the request (to prevent HEADs colliding |
| 2946 | * with rapid ringbuffer wraparound) the amount of available space |
| 2947 | * upon reset is less than when we start. Do one more pass over |
| 2948 | * all the ringbuffers to reset last_retired_head. |
| 2949 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2950 | list_for_each_entry(buffer, &engine->buffers, link) { |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2951 | buffer->last_retired_head = buffer->tail; |
| 2952 | intel_ring_update_space(buffer); |
| 2953 | } |
Chris Wilson | 2ed53a9 | 2016-04-07 07:29:11 +0100 | [diff] [blame] | 2954 | |
| 2955 | intel_ring_init_seqno(engine, engine->last_submitted_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2956 | } |
| 2957 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2958 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2959 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2961 | struct intel_engine_cs *engine; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2962 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2963 | /* |
| 2964 | * Before we free the objects from the requests, we need to inspect |
| 2965 | * them for finding the guilty party. As the requests only borrow |
| 2966 | * their reference to the objects, the inspection must be done first. |
| 2967 | */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2968 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2969 | i915_gem_reset_engine_status(dev_priv, engine); |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2970 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2971 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2972 | i915_gem_reset_engine_cleanup(dev_priv, engine); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2973 | |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2974 | i915_gem_context_reset(dev); |
| 2975 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2976 | i915_gem_restore_fences(dev); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2977 | |
| 2978 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2979 | } |
| 2980 | |
| 2981 | /** |
| 2982 | * This function clears the request list as sequence numbers are passed. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 2983 | * @engine: engine to retire requests on |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2984 | */ |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 2985 | void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2986 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2987 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2988 | WARN_ON(i915_verify_lists(engine->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2989 | |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2990 | /* Retire requests first as we use it above for the early return. |
| 2991 | * If we retire requests last, we may use a later seqno and so clear |
| 2992 | * the requests lists without clearing the active list, leading to |
| 2993 | * confusion. |
Chris Wilson | e910303 | 2014-01-07 11:45:14 +0000 | [diff] [blame] | 2994 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2995 | while (!list_empty(&engine->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2996 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2997 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2998 | request = list_first_entry(&engine->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2999 | struct drm_i915_gem_request, |
| 3000 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3001 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 3002 | if (!i915_gem_request_completed(request, true)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3003 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 3004 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3005 | i915_gem_request_retire(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 3006 | } |
| 3007 | |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 3008 | /* Move any buffers on the active list that are no longer referenced |
| 3009 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 3010 | * before we free the context associated with the requests. |
| 3011 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3012 | while (!list_empty(&engine->active_list)) { |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 3013 | struct drm_i915_gem_object *obj; |
| 3014 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3015 | obj = list_first_entry(&engine->active_list, |
| 3016 | struct drm_i915_gem_object, |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 3017 | engine_list[engine->id]); |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 3018 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3019 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 3020 | break; |
| 3021 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3022 | i915_gem_object_retire__read(obj, engine->id); |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 3023 | } |
| 3024 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3025 | if (unlikely(engine->trace_irq_req && |
| 3026 | i915_gem_request_completed(engine->trace_irq_req, true))) { |
| 3027 | engine->irq_put(engine); |
| 3028 | i915_gem_request_assign(&engine->trace_irq_req, NULL); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 3029 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3030 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3031 | WARN_ON(i915_verify_lists(engine->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3032 | } |
| 3033 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3034 | bool |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3035 | i915_gem_retire_requests(struct drm_i915_private *dev_priv) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 3036 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3037 | struct intel_engine_cs *engine; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3038 | bool idle = true; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 3039 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3040 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3041 | i915_gem_retire_requests_ring(engine); |
| 3042 | idle &= list_empty(&engine->request_list); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 3043 | if (i915.enable_execlists) { |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 3044 | spin_lock_bh(&engine->execlist_lock); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3045 | idle &= list_empty(&engine->execlist_queue); |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 3046 | spin_unlock_bh(&engine->execlist_lock); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 3047 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3048 | } |
| 3049 | |
| 3050 | if (idle) |
| 3051 | mod_delayed_work(dev_priv->wq, |
| 3052 | &dev_priv->mm.idle_work, |
| 3053 | msecs_to_jiffies(100)); |
| 3054 | |
| 3055 | return idle; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 3056 | } |
| 3057 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 3058 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3059 | i915_gem_retire_work_handler(struct work_struct *work) |
| 3060 | { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3061 | struct drm_i915_private *dev_priv = |
| 3062 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 3063 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 3064 | bool idle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3065 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 3066 | /* Come back later if the device is busy... */ |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3067 | idle = false; |
| 3068 | if (mutex_trylock(&dev->struct_mutex)) { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3069 | idle = i915_gem_retire_requests(dev_priv); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3070 | mutex_unlock(&dev->struct_mutex); |
| 3071 | } |
| 3072 | if (!idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 3073 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 3074 | round_jiffies_up_relative(HZ)); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3075 | } |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 3076 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3077 | static void |
| 3078 | i915_gem_idle_work_handler(struct work_struct *work) |
| 3079 | { |
| 3080 | struct drm_i915_private *dev_priv = |
| 3081 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
Chris Wilson | 35c9418 | 2015-04-07 16:20:37 +0100 | [diff] [blame] | 3082 | struct drm_device *dev = dev_priv->dev; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3083 | struct intel_engine_cs *engine; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3084 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3085 | for_each_engine(engine, dev_priv) |
| 3086 | if (!list_empty(&engine->request_list)) |
Chris Wilson | 423795c | 2015-04-07 16:21:08 +0100 | [diff] [blame] | 3087 | return; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3088 | |
Daniel Vetter | 30ecad7 | 2015-12-09 09:29:36 +0100 | [diff] [blame] | 3089 | /* we probably should sync with hangcheck here, using cancel_work_sync. |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3090 | * Also locking seems to be fubar here, engine->request_list is protected |
Daniel Vetter | 30ecad7 | 2015-12-09 09:29:36 +0100 | [diff] [blame] | 3091 | * by dev->struct_mutex. */ |
| 3092 | |
Tvrtko Ursulin | 7d99373 | 2016-04-28 12:57:00 +0100 | [diff] [blame] | 3093 | intel_mark_idle(dev_priv); |
Chris Wilson | 35c9418 | 2015-04-07 16:20:37 +0100 | [diff] [blame] | 3094 | |
| 3095 | if (mutex_trylock(&dev->struct_mutex)) { |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3096 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3097 | i915_gem_batch_pool_fini(&engine->batch_pool); |
Chris Wilson | 35c9418 | 2015-04-07 16:20:37 +0100 | [diff] [blame] | 3098 | |
| 3099 | mutex_unlock(&dev->struct_mutex); |
| 3100 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3101 | } |
| 3102 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3103 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3104 | * Ensures that an object will eventually get non-busy by flushing any required |
| 3105 | * write domains, emitting any outstanding lazy request and retiring and |
| 3106 | * completed requests. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 3107 | * @obj: object to flush |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3108 | */ |
| 3109 | static int |
| 3110 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 3111 | { |
John Harrison | a5ac0f9 | 2015-05-29 17:44:15 +0100 | [diff] [blame] | 3112 | int i; |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3113 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3114 | if (!obj->active) |
| 3115 | return 0; |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 3116 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3117 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3118 | struct drm_i915_gem_request *req; |
| 3119 | |
| 3120 | req = obj->last_read_req[i]; |
| 3121 | if (req == NULL) |
| 3122 | continue; |
| 3123 | |
Chris Wilson | e6db746 | 2016-05-13 11:57:21 +0100 | [diff] [blame] | 3124 | if (i915_gem_request_completed(req, true)) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3125 | i915_gem_object_retire__read(obj, i); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3126 | } |
| 3127 | |
| 3128 | return 0; |
| 3129 | } |
| 3130 | |
| 3131 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3132 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 3133 | * @dev: drm device pointer |
| 3134 | * @data: ioctl data blob |
| 3135 | * @file: drm file pointer |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3136 | * |
| 3137 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 3138 | * the timeout parameter. |
| 3139 | * -ETIME: object is still busy after timeout |
| 3140 | * -ERESTARTSYS: signal interrupted the wait |
| 3141 | * -ENONENT: object doesn't exist |
| 3142 | * Also possible, but rare: |
| 3143 | * -EAGAIN: GPU wedged |
| 3144 | * -ENOMEM: damn |
| 3145 | * -ENODEV: Internal IRQ fail |
| 3146 | * -E?: The add request failed |
| 3147 | * |
| 3148 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 3149 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 3150 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 3151 | * without holding struct_mutex the object may become re-busied before this |
| 3152 | * function completes. A similar but shorter * race condition exists in the busy |
| 3153 | * ioctl |
| 3154 | */ |
| 3155 | int |
| 3156 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 3157 | { |
| 3158 | struct drm_i915_gem_wait *args = data; |
| 3159 | struct drm_i915_gem_object *obj; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3160 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3161 | int i, n = 0; |
| 3162 | int ret; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3163 | |
Daniel Vetter | 11b5d51 | 2014-09-29 15:31:26 +0200 | [diff] [blame] | 3164 | if (args->flags != 0) |
| 3165 | return -EINVAL; |
| 3166 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3167 | ret = i915_mutex_lock_interruptible(dev); |
| 3168 | if (ret) |
| 3169 | return ret; |
| 3170 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 3171 | obj = to_intel_bo(drm_gem_object_lookup(file, args->bo_handle)); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3172 | if (&obj->base == NULL) { |
| 3173 | mutex_unlock(&dev->struct_mutex); |
| 3174 | return -ENOENT; |
| 3175 | } |
| 3176 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3177 | /* Need to make sure the object gets inactive eventually. */ |
| 3178 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3179 | if (ret) |
| 3180 | goto out; |
| 3181 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3182 | if (!obj->active) |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 3183 | goto out; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3184 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3185 | /* Do this after OLR check to make sure we make forward progress polling |
Chris Wilson | 762e458 | 2015-03-04 18:09:26 +0000 | [diff] [blame] | 3186 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3187 | */ |
Chris Wilson | 762e458 | 2015-03-04 18:09:26 +0000 | [diff] [blame] | 3188 | if (args->timeout_ns == 0) { |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3189 | ret = -ETIME; |
| 3190 | goto out; |
| 3191 | } |
| 3192 | |
| 3193 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3194 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3195 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3196 | if (obj->last_read_req[i] == NULL) |
| 3197 | continue; |
| 3198 | |
| 3199 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); |
| 3200 | } |
| 3201 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3202 | mutex_unlock(&dev->struct_mutex); |
| 3203 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3204 | for (i = 0; i < n; i++) { |
| 3205 | if (ret == 0) |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 3206 | ret = __i915_wait_request(req[i], true, |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3207 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
Chris Wilson | b6aa087 | 2015-12-02 09:13:46 +0000 | [diff] [blame] | 3208 | to_rps_client(file)); |
Chris Wilson | 73db04c | 2016-04-28 09:56:55 +0100 | [diff] [blame] | 3209 | i915_gem_request_unreference(req[i]); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3210 | } |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 3211 | return ret; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3212 | |
| 3213 | out: |
| 3214 | drm_gem_object_unreference(&obj->base); |
| 3215 | mutex_unlock(&dev->struct_mutex); |
| 3216 | return ret; |
| 3217 | } |
| 3218 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3219 | static int |
| 3220 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 3221 | struct intel_engine_cs *to, |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3222 | struct drm_i915_gem_request *from_req, |
| 3223 | struct drm_i915_gem_request **to_req) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3224 | { |
| 3225 | struct intel_engine_cs *from; |
| 3226 | int ret; |
| 3227 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3228 | from = i915_gem_request_get_engine(from_req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3229 | if (to == from) |
| 3230 | return 0; |
| 3231 | |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3232 | if (i915_gem_request_completed(from_req, true)) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3233 | return 0; |
| 3234 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3235 | if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) { |
Chris Wilson | a6f766f | 2015-04-27 13:41:20 +0100 | [diff] [blame] | 3236 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3237 | ret = __i915_wait_request(from_req, |
Chris Wilson | a6f766f | 2015-04-27 13:41:20 +0100 | [diff] [blame] | 3238 | i915->mm.interruptible, |
| 3239 | NULL, |
| 3240 | &i915->rps.semaphores); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3241 | if (ret) |
| 3242 | return ret; |
| 3243 | |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3244 | i915_gem_object_retire_request(obj, from_req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3245 | } else { |
| 3246 | int idx = intel_ring_sync_index(from, to); |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3247 | u32 seqno = i915_gem_request_get_seqno(from_req); |
| 3248 | |
| 3249 | WARN_ON(!to_req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3250 | |
| 3251 | if (seqno <= from->semaphore.sync_seqno[idx]) |
| 3252 | return 0; |
| 3253 | |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3254 | if (*to_req == NULL) { |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 3255 | struct drm_i915_gem_request *req; |
| 3256 | |
| 3257 | req = i915_gem_request_alloc(to, NULL); |
| 3258 | if (IS_ERR(req)) |
| 3259 | return PTR_ERR(req); |
| 3260 | |
| 3261 | *to_req = req; |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3262 | } |
| 3263 | |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 3264 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
| 3265 | ret = to->semaphore.sync_to(*to_req, from, seqno); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3266 | if (ret) |
| 3267 | return ret; |
| 3268 | |
| 3269 | /* We use last_read_req because sync_to() |
| 3270 | * might have just caused seqno wrap under |
| 3271 | * the radar. |
| 3272 | */ |
| 3273 | from->semaphore.sync_seqno[idx] = |
| 3274 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); |
| 3275 | } |
| 3276 | |
| 3277 | return 0; |
| 3278 | } |
| 3279 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3280 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3281 | * i915_gem_object_sync - sync an object to a ring. |
| 3282 | * |
| 3283 | * @obj: object which may be in use on another ring. |
| 3284 | * @to: ring we wish to use the object on. May be NULL. |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3285 | * @to_req: request we wish to use the object for. See below. |
| 3286 | * This will be allocated and returned if a request is |
| 3287 | * required but not passed in. |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3288 | * |
| 3289 | * This code is meant to abstract object synchronization with the GPU. |
| 3290 | * Calling with NULL implies synchronizing the object with the CPU |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3291 | * rather than a particular GPU ring. Conceptually we serialise writes |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3292 | * between engines inside the GPU. We only allow one engine to write |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3293 | * into a buffer at any time, but multiple readers. To ensure each has |
| 3294 | * a coherent view of memory, we must: |
| 3295 | * |
| 3296 | * - If there is an outstanding write request to the object, the new |
| 3297 | * request must wait for it to complete (either CPU or in hw, requests |
| 3298 | * on the same ring will be naturally ordered). |
| 3299 | * |
| 3300 | * - If we are a write request (pending_write_domain is set), the new |
| 3301 | * request must wait for outstanding read requests to complete. |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3302 | * |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3303 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
| 3304 | * rings to_req must be non-NULL. However, a request does not have to be |
| 3305 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a |
| 3306 | * request will be allocated automatically and returned through *to_req. Note |
| 3307 | * that it is not guaranteed that commands will be emitted (because the system |
| 3308 | * might already be idle). Hence there is no need to create a request that |
| 3309 | * might never have any work submitted. Note further that if a request is |
| 3310 | * returned in *to_req, it is the responsibility of the caller to submit |
| 3311 | * that request (after potentially adding more work to it). |
| 3312 | * |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3313 | * Returns 0 if successful, else propagates up the lower layer error. |
| 3314 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3315 | int |
| 3316 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3317 | struct intel_engine_cs *to, |
| 3318 | struct drm_i915_gem_request **to_req) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3319 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3320 | const bool readonly = obj->base.pending_write_domain == 0; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3321 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3322 | int ret, i, n; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3323 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3324 | if (!obj->active) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3325 | return 0; |
| 3326 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3327 | if (to == NULL) |
| 3328 | return i915_gem_object_wait_rendering(obj, readonly); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3329 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3330 | n = 0; |
| 3331 | if (readonly) { |
| 3332 | if (obj->last_write_req) |
| 3333 | req[n++] = obj->last_write_req; |
| 3334 | } else { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3335 | for (i = 0; i < I915_NUM_ENGINES; i++) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3336 | if (obj->last_read_req[i]) |
| 3337 | req[n++] = obj->last_read_req[i]; |
| 3338 | } |
| 3339 | for (i = 0; i < n; i++) { |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3340 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3341 | if (ret) |
| 3342 | return ret; |
| 3343 | } |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3344 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3345 | return 0; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3346 | } |
| 3347 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3348 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 3349 | { |
| 3350 | u32 old_write_domain, old_read_domains; |
| 3351 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3352 | /* Force a pagefault for domain tracking on next user access */ |
| 3353 | i915_gem_release_mmap(obj); |
| 3354 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 3355 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3356 | return; |
| 3357 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3358 | old_read_domains = obj->base.read_domains; |
| 3359 | old_write_domain = obj->base.write_domain; |
| 3360 | |
| 3361 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 3362 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 3363 | |
| 3364 | trace_i915_gem_object_change_domain(obj, |
| 3365 | old_read_domains, |
| 3366 | old_write_domain); |
| 3367 | } |
| 3368 | |
Chris Wilson | 8ef8561 | 2016-04-28 09:56:39 +0100 | [diff] [blame] | 3369 | static void __i915_vma_iounmap(struct i915_vma *vma) |
| 3370 | { |
| 3371 | GEM_BUG_ON(vma->pin_count); |
| 3372 | |
| 3373 | if (vma->iomap == NULL) |
| 3374 | return; |
| 3375 | |
| 3376 | io_mapping_unmap(vma->iomap); |
| 3377 | vma->iomap = NULL; |
| 3378 | } |
| 3379 | |
Tvrtko Ursulin | e9f24d5 | 2015-10-05 13:26:36 +0100 | [diff] [blame] | 3380 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3381 | { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3382 | struct drm_i915_gem_object *obj = vma->obj; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3383 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 3384 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3385 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3386 | if (list_empty(&vma->obj_link)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3387 | return 0; |
| 3388 | |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 3389 | if (!drm_mm_node_allocated(&vma->node)) { |
| 3390 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 3391 | return 0; |
| 3392 | } |
Ben Widawsky | 433544b | 2013-08-13 18:09:06 -0700 | [diff] [blame] | 3393 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3394 | if (vma->pin_count) |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 3395 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3396 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 3397 | BUG_ON(obj->pages == NULL); |
| 3398 | |
Tvrtko Ursulin | e9f24d5 | 2015-10-05 13:26:36 +0100 | [diff] [blame] | 3399 | if (wait) { |
| 3400 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3401 | if (ret) |
| 3402 | return ret; |
| 3403 | } |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3404 | |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 3405 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3406 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3407 | |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3408 | /* release the fence reg _after_ flushing */ |
| 3409 | ret = i915_gem_object_put_fence(obj); |
| 3410 | if (ret) |
| 3411 | return ret; |
Chris Wilson | 8ef8561 | 2016-04-28 09:56:39 +0100 | [diff] [blame] | 3412 | |
| 3413 | __i915_vma_iounmap(vma); |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3414 | } |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 3415 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3416 | trace_i915_vma_unbind(vma); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3417 | |
Daniel Vetter | 777dc5b | 2015-04-14 17:35:12 +0200 | [diff] [blame] | 3418 | vma->vm->unbind_vma(vma); |
Mika Kuoppala | 5e562f1 | 2015-04-30 11:02:31 +0300 | [diff] [blame] | 3419 | vma->bound = 0; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3420 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3421 | list_del_init(&vma->vm_link); |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 3422 | if (vma->is_ggtt) { |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3423 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
| 3424 | obj->map_and_fenceable = false; |
| 3425 | } else if (vma->ggtt_view.pages) { |
| 3426 | sg_free_table(vma->ggtt_view.pages); |
| 3427 | kfree(vma->ggtt_view.pages); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3428 | } |
Chris Wilson | 016a65a | 2015-06-11 08:06:08 +0100 | [diff] [blame] | 3429 | vma->ggtt_view.pages = NULL; |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3430 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3431 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3432 | drm_mm_remove_node(&vma->node); |
| 3433 | i915_gem_vma_destroy(vma); |
| 3434 | |
| 3435 | /* Since the unbound list is global, only move to that list if |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 3436 | * no more VMAs exist. */ |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 3437 | if (list_empty(&obj->vma_list)) |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3438 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3439 | |
Chris Wilson | 70903c3 | 2013-12-04 09:59:09 +0000 | [diff] [blame] | 3440 | /* And finally now the object is completely decoupled from this vma, |
| 3441 | * we can drop its hold on the backing storage and allow it to be |
| 3442 | * reaped by the shrinker. |
| 3443 | */ |
| 3444 | i915_gem_object_unpin_pages(obj); |
| 3445 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3446 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 3447 | } |
| 3448 | |
Tvrtko Ursulin | e9f24d5 | 2015-10-05 13:26:36 +0100 | [diff] [blame] | 3449 | int i915_vma_unbind(struct i915_vma *vma) |
| 3450 | { |
| 3451 | return __i915_vma_unbind(vma, true); |
| 3452 | } |
| 3453 | |
| 3454 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) |
| 3455 | { |
| 3456 | return __i915_vma_unbind(vma, false); |
| 3457 | } |
| 3458 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3459 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3460 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3461 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3462 | struct intel_engine_cs *engine; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3463 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3464 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3465 | /* Flush everything onto the inactive list. */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3466 | for_each_engine(engine, dev_priv) { |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame] | 3467 | if (!i915.enable_execlists) { |
John Harrison | 73cfa86 | 2015-05-29 17:43:35 +0100 | [diff] [blame] | 3468 | struct drm_i915_gem_request *req; |
| 3469 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3470 | req = i915_gem_request_alloc(engine, NULL); |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 3471 | if (IS_ERR(req)) |
| 3472 | return PTR_ERR(req); |
John Harrison | 73cfa86 | 2015-05-29 17:43:35 +0100 | [diff] [blame] | 3473 | |
John Harrison | ba01cc9 | 2015-05-29 17:43:41 +0100 | [diff] [blame] | 3474 | ret = i915_switch_context(req); |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 3475 | i915_add_request_no_flush(req); |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 3476 | if (ret) |
| 3477 | return ret; |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame] | 3478 | } |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 3479 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3480 | ret = intel_engine_idle(engine); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3481 | if (ret) |
| 3482 | return ret; |
| 3483 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3484 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3485 | WARN_ON(i915_verify_lists(dev)); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3486 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3487 | } |
| 3488 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3489 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3490 | unsigned long cache_level) |
| 3491 | { |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3492 | struct drm_mm_node *gtt_space = &vma->node; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3493 | struct drm_mm_node *other; |
| 3494 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3495 | /* |
| 3496 | * On some machines we have to be careful when putting differing types |
| 3497 | * of snoopable memory together to avoid the prefetcher crossing memory |
| 3498 | * domains and dying. During vm initialisation, we decide whether or not |
| 3499 | * these constraints apply and set the drm_mm.color_adjust |
| 3500 | * appropriately. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3501 | */ |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3502 | if (vma->vm->mm.color_adjust == NULL) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3503 | return true; |
| 3504 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3505 | if (!drm_mm_node_allocated(gtt_space)) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3506 | return true; |
| 3507 | |
| 3508 | if (list_empty(>t_space->node_list)) |
| 3509 | return true; |
| 3510 | |
| 3511 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3512 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3513 | return false; |
| 3514 | |
| 3515 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3516 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3517 | return false; |
| 3518 | |
| 3519 | return true; |
| 3520 | } |
| 3521 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3522 | /** |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3523 | * Finds free space in the GTT aperture and binds the object or a view of it |
| 3524 | * there. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 3525 | * @obj: object to bind |
| 3526 | * @vm: address space to bind into |
| 3527 | * @ggtt_view: global gtt view if applicable |
| 3528 | * @alignment: requested alignment |
| 3529 | * @flags: mask of PIN_* flags to use |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3530 | */ |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3531 | static struct i915_vma * |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3532 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3533 | struct i915_address_space *vm, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3534 | const struct i915_ggtt_view *ggtt_view, |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3535 | unsigned alignment, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3536 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3537 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3538 | struct drm_device *dev = obj->base.dev; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 3539 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3540 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Michel Thierry | 65bd342 | 2015-07-29 17:23:58 +0100 | [diff] [blame] | 3541 | u32 fence_alignment, unfenced_alignment; |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3542 | u32 search_flag, alloc_flag; |
| 3543 | u64 start, end; |
Michel Thierry | 65bd342 | 2015-07-29 17:23:58 +0100 | [diff] [blame] | 3544 | u64 size, fence_size; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3545 | struct i915_vma *vma; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3546 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3547 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3548 | if (i915_is_ggtt(vm)) { |
| 3549 | u32 view_size; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3550 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3551 | if (WARN_ON(!ggtt_view)) |
| 3552 | return ERR_PTR(-EINVAL); |
| 3553 | |
| 3554 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
| 3555 | |
| 3556 | fence_size = i915_gem_get_gtt_size(dev, |
| 3557 | view_size, |
| 3558 | obj->tiling_mode); |
| 3559 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3560 | view_size, |
| 3561 | obj->tiling_mode, |
| 3562 | true); |
| 3563 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, |
| 3564 | view_size, |
| 3565 | obj->tiling_mode, |
| 3566 | false); |
| 3567 | size = flags & PIN_MAPPABLE ? fence_size : view_size; |
| 3568 | } else { |
| 3569 | fence_size = i915_gem_get_gtt_size(dev, |
| 3570 | obj->base.size, |
| 3571 | obj->tiling_mode); |
| 3572 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3573 | obj->base.size, |
| 3574 | obj->tiling_mode, |
| 3575 | true); |
| 3576 | unfenced_alignment = |
| 3577 | i915_gem_get_gtt_alignment(dev, |
| 3578 | obj->base.size, |
| 3579 | obj->tiling_mode, |
| 3580 | false); |
| 3581 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
| 3582 | } |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3583 | |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3584 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
| 3585 | end = vm->total; |
| 3586 | if (flags & PIN_MAPPABLE) |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 3587 | end = min_t(u64, end, ggtt->mappable_end); |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3588 | if (flags & PIN_ZONE_4G) |
Michel Thierry | 48ea1e3 | 2016-01-11 11:39:27 +0000 | [diff] [blame] | 3589 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3590 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3591 | if (alignment == 0) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3592 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3593 | unfenced_alignment; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3594 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3595 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
| 3596 | ggtt_view ? ggtt_view->type : 0, |
| 3597 | alignment); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3598 | return ERR_PTR(-EINVAL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3599 | } |
| 3600 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3601 | /* If binding the object/GGTT view requires more space than the entire |
| 3602 | * aperture has, reject it early before evicting everything in a vain |
| 3603 | * attempt to find space. |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3604 | */ |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3605 | if (size > end) { |
Michel Thierry | 65bd342 | 2015-07-29 17:23:58 +0100 | [diff] [blame] | 3606 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3607 | ggtt_view ? ggtt_view->type : 0, |
| 3608 | size, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3609 | flags & PIN_MAPPABLE ? "mappable" : "total", |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3610 | end); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3611 | return ERR_PTR(-E2BIG); |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3612 | } |
| 3613 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3614 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3615 | if (ret) |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3616 | return ERR_PTR(ret); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3617 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3618 | i915_gem_object_pin_pages(obj); |
| 3619 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3620 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
| 3621 | i915_gem_obj_lookup_or_create_vma(obj, vm); |
| 3622 | |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3623 | if (IS_ERR(vma)) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3624 | goto err_unpin; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3625 | |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 3626 | if (flags & PIN_OFFSET_FIXED) { |
| 3627 | uint64_t offset = flags & PIN_OFFSET_MASK; |
| 3628 | |
| 3629 | if (offset & (alignment - 1) || offset + size > end) { |
| 3630 | ret = -EINVAL; |
| 3631 | goto err_free_vma; |
| 3632 | } |
| 3633 | vma->node.start = offset; |
| 3634 | vma->node.size = size; |
| 3635 | vma->node.color = obj->cache_level; |
| 3636 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); |
| 3637 | if (ret) { |
| 3638 | ret = i915_gem_evict_for_vma(vma); |
| 3639 | if (ret == 0) |
| 3640 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); |
| 3641 | } |
| 3642 | if (ret) |
| 3643 | goto err_free_vma; |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3644 | } else { |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 3645 | if (flags & PIN_HIGH) { |
| 3646 | search_flag = DRM_MM_SEARCH_BELOW; |
| 3647 | alloc_flag = DRM_MM_CREATE_TOP; |
| 3648 | } else { |
| 3649 | search_flag = DRM_MM_SEARCH_DEFAULT; |
| 3650 | alloc_flag = DRM_MM_CREATE_DEFAULT; |
| 3651 | } |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3652 | |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3653 | search_free: |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 3654 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
| 3655 | size, alignment, |
| 3656 | obj->cache_level, |
| 3657 | start, end, |
| 3658 | search_flag, |
| 3659 | alloc_flag); |
| 3660 | if (ret) { |
| 3661 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
| 3662 | obj->cache_level, |
| 3663 | start, end, |
| 3664 | flags); |
| 3665 | if (ret == 0) |
| 3666 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3667 | |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 3668 | goto err_free_vma; |
| 3669 | } |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3670 | } |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3671 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3672 | ret = -EINVAL; |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3673 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3674 | } |
| 3675 | |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3676 | trace_i915_vma_bind(vma, flags); |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 3677 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3678 | if (ret) |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 3679 | goto err_remove_node; |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3680 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3681 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3682 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3683 | |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3684 | return vma; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3685 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3686 | err_remove_node: |
Dan Carpenter | 6286ef9 | 2013-07-19 08:46:27 +0300 | [diff] [blame] | 3687 | drm_mm_remove_node(&vma->node); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3688 | err_free_vma: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3689 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3690 | vma = ERR_PTR(ret); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3691 | err_unpin: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3692 | i915_gem_object_unpin_pages(obj); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3693 | return vma; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3694 | } |
| 3695 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3696 | bool |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3697 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3698 | bool force) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3699 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3700 | /* If we don't have a page list set up, then we're not pinned |
| 3701 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3702 | * again at bind time. |
| 3703 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3704 | if (obj->pages == NULL) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3705 | return false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3706 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3707 | /* |
| 3708 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3709 | * marked as wc by the system, or the system is cache-coherent. |
| 3710 | */ |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 3711 | if (obj->stolen || obj->phys_handle) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3712 | return false; |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3713 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3714 | /* If the GPU is snooping the contents of the CPU cache, |
| 3715 | * we do not need to manually clear the CPU cache lines. However, |
| 3716 | * the caches are only snooped when the render cache is |
| 3717 | * flushed/invalidated. As we always have to emit invalidations |
| 3718 | * and flushes when moving into and out of the RENDER domain, correct |
| 3719 | * snooping behaviour occurs naturally as the result of our domain |
| 3720 | * tracking. |
| 3721 | */ |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3722 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
| 3723 | obj->cache_dirty = true; |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3724 | return false; |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3725 | } |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3726 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3727 | trace_i915_gem_object_clflush(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3728 | drm_clflush_sg(obj->pages); |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3729 | obj->cache_dirty = false; |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3730 | |
| 3731 | return true; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3732 | } |
| 3733 | |
| 3734 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3735 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3736 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3737 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3738 | uint32_t old_write_domain; |
| 3739 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3740 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3741 | return; |
| 3742 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3743 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3744 | * to it immediately go to main memory as far as we know, so there's |
| 3745 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3746 | * |
| 3747 | * However, we do have to enforce the order so that all writes through |
| 3748 | * the GTT land before any writes to the device, such as updates to |
| 3749 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3750 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3751 | wmb(); |
| 3752 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3753 | old_write_domain = obj->base.write_domain; |
| 3754 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3755 | |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 3756 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3757 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3758 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3759 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3760 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3761 | } |
| 3762 | |
| 3763 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3764 | static void |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3765 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3766 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3767 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3768 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3769 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3770 | return; |
| 3771 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3772 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3773 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3774 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3775 | old_write_domain = obj->base.write_domain; |
| 3776 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3777 | |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 3778 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3779 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3780 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3781 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3782 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3783 | } |
| 3784 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3785 | /** |
| 3786 | * Moves a single object to the GTT read, and possibly write domain. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 3787 | * @obj: object to act on |
| 3788 | * @write: ask for write access or read only |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3789 | * |
| 3790 | * This function returns when the move is complete, including waiting on |
| 3791 | * flushes to occur. |
| 3792 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3793 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3794 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3795 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 3796 | struct drm_device *dev = obj->base.dev; |
| 3797 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3798 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3799 | uint32_t old_write_domain, old_read_domains; |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3800 | struct i915_vma *vma; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3801 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3802 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3803 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3804 | return 0; |
| 3805 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3806 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3807 | if (ret) |
| 3808 | return ret; |
| 3809 | |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3810 | /* Flush and acquire obj->pages so that we are coherent through |
| 3811 | * direct access in memory with previous cached writes through |
| 3812 | * shmemfs and that our cache domain tracking remains valid. |
| 3813 | * For example, if the obj->filp was moved to swap without us |
| 3814 | * being notified and releasing the pages, we would mistakenly |
| 3815 | * continue to assume that the obj remained out of the CPU cached |
| 3816 | * domain. |
| 3817 | */ |
| 3818 | ret = i915_gem_object_get_pages(obj); |
| 3819 | if (ret) |
| 3820 | return ret; |
| 3821 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3822 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3823 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3824 | /* Serialise direct access to this object with the barriers for |
| 3825 | * coherent writes from the GPU, by effectively invalidating the |
| 3826 | * GTT domain upon first access. |
| 3827 | */ |
| 3828 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3829 | mb(); |
| 3830 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3831 | old_write_domain = obj->base.write_domain; |
| 3832 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3833 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3834 | /* It should now be out of any other write domains, and we can update |
| 3835 | * the domain values for our changes. |
| 3836 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3837 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3838 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3839 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3840 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3841 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3842 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3843 | } |
| 3844 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3845 | trace_i915_gem_object_change_domain(obj, |
| 3846 | old_read_domains, |
| 3847 | old_write_domain); |
| 3848 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3849 | /* And bump the LRU for this access */ |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3850 | vma = i915_gem_obj_to_ggtt(obj); |
| 3851 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3852 | list_move_tail(&vma->vm_link, |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 3853 | &ggtt->base.inactive_list); |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3854 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3855 | return 0; |
| 3856 | } |
| 3857 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3858 | /** |
| 3859 | * Changes the cache-level of an object across all VMA. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 3860 | * @obj: object to act on |
| 3861 | * @cache_level: new cache level to set for the object |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3862 | * |
| 3863 | * After this function returns, the object will be in the new cache-level |
| 3864 | * across all GTT and the contents of the backing storage will be coherent, |
| 3865 | * with respect to the new cache-level. In order to keep the backing storage |
| 3866 | * coherent for all users, we only allow a single cache level to be set |
| 3867 | * globally on the object and prevent it from being changed whilst the |
| 3868 | * hardware is reading from the object. That is if the object is currently |
| 3869 | * on the scanout it will be set to uncached (or equivalent display |
| 3870 | * cache coherency) and all non-MOCS GPU access will also be uncached so |
| 3871 | * that all direct access to the scanout remains coherent. |
| 3872 | */ |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3873 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3874 | enum i915_cache_level cache_level) |
| 3875 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3876 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | df6f783 | 2014-03-21 07:40:56 +0000 | [diff] [blame] | 3877 | struct i915_vma *vma, *next; |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3878 | bool bound = false; |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 3879 | int ret = 0; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3880 | |
| 3881 | if (obj->cache_level == cache_level) |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 3882 | goto out; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3883 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3884 | /* Inspect the list of currently bound VMA and unbind any that would |
| 3885 | * be invalid given the new cache-level. This is principally to |
| 3886 | * catch the issue of the CS prefetch crossing page boundaries and |
| 3887 | * reading an invalid PTE on older architectures. |
| 3888 | */ |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3889 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3890 | if (!drm_mm_node_allocated(&vma->node)) |
| 3891 | continue; |
| 3892 | |
| 3893 | if (vma->pin_count) { |
| 3894 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3895 | return -EBUSY; |
| 3896 | } |
| 3897 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3898 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3899 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3900 | if (ret) |
| 3901 | return ret; |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3902 | } else |
| 3903 | bound = true; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3904 | } |
| 3905 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3906 | /* We can reuse the existing drm_mm nodes but need to change the |
| 3907 | * cache-level on the PTE. We could simply unbind them all and |
| 3908 | * rebind with the correct cache-level on next use. However since |
| 3909 | * we already have a valid slot, dma mapping, pages etc, we may as |
| 3910 | * rewrite the PTE in the belief that doing so tramples upon less |
| 3911 | * state and so involves less work. |
| 3912 | */ |
| 3913 | if (bound) { |
| 3914 | /* Before we change the PTE, the GPU must not be accessing it. |
| 3915 | * If we wait upon the object, we know that all the bound |
| 3916 | * VMA are no longer active. |
| 3917 | */ |
Chris Wilson | 2e2f351 | 2015-04-27 13:41:14 +0100 | [diff] [blame] | 3918 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3919 | if (ret) |
| 3920 | return ret; |
| 3921 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3922 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
| 3923 | /* Access to snoopable pages through the GTT is |
| 3924 | * incoherent and on some machines causes a hard |
| 3925 | * lockup. Relinquish the CPU mmaping to force |
| 3926 | * userspace to refault in the pages and we can |
| 3927 | * then double check if the GTT mapping is still |
| 3928 | * valid for that pointer access. |
| 3929 | */ |
| 3930 | i915_gem_release_mmap(obj); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3931 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3932 | /* As we no longer need a fence for GTT access, |
| 3933 | * we can relinquish it now (and so prevent having |
| 3934 | * to steal a fence from someone else on the next |
| 3935 | * fence request). Note GPU activity would have |
| 3936 | * dropped the fence as all snoopable access is |
| 3937 | * supposed to be linear. |
| 3938 | */ |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3939 | ret = i915_gem_object_put_fence(obj); |
| 3940 | if (ret) |
| 3941 | return ret; |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3942 | } else { |
| 3943 | /* We either have incoherent backing store and |
| 3944 | * so no GTT access or the architecture is fully |
| 3945 | * coherent. In such cases, existing GTT mmaps |
| 3946 | * ignore the cache bit in the PTE and we can |
| 3947 | * rewrite it without confusing the GPU or having |
| 3948 | * to force userspace to fault back in its mmaps. |
| 3949 | */ |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3950 | } |
| 3951 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3952 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3953 | if (!drm_mm_node_allocated(&vma->node)) |
| 3954 | continue; |
| 3955 | |
| 3956 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); |
| 3957 | if (ret) |
| 3958 | return ret; |
| 3959 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3960 | } |
| 3961 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3962 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3963 | vma->node.color = cache_level; |
| 3964 | obj->cache_level = cache_level; |
| 3965 | |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 3966 | out: |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3967 | /* Flush the dirty CPU caches to the backing storage so that the |
| 3968 | * object is now coherent at its new cache level (with respect |
| 3969 | * to the access domain). |
| 3970 | */ |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3971 | if (obj->cache_dirty && |
| 3972 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 3973 | cpu_write_needs_clflush(obj)) { |
| 3974 | if (i915_gem_clflush_object(obj, true)) |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 3975 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3976 | } |
| 3977 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3978 | return 0; |
| 3979 | } |
| 3980 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3981 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3982 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3983 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3984 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3985 | struct drm_i915_gem_object *obj; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3986 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 3987 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
Chris Wilson | 432be69 | 2015-05-07 12:14:55 +0100 | [diff] [blame] | 3988 | if (&obj->base == NULL) |
| 3989 | return -ENOENT; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3990 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3991 | switch (obj->cache_level) { |
| 3992 | case I915_CACHE_LLC: |
| 3993 | case I915_CACHE_L3_LLC: |
| 3994 | args->caching = I915_CACHING_CACHED; |
| 3995 | break; |
| 3996 | |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3997 | case I915_CACHE_WT: |
| 3998 | args->caching = I915_CACHING_DISPLAY; |
| 3999 | break; |
| 4000 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 4001 | default: |
| 4002 | args->caching = I915_CACHING_NONE; |
| 4003 | break; |
| 4004 | } |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4005 | |
Chris Wilson | 432be69 | 2015-05-07 12:14:55 +0100 | [diff] [blame] | 4006 | drm_gem_object_unreference_unlocked(&obj->base); |
| 4007 | return 0; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4008 | } |
| 4009 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4010 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 4011 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4012 | { |
Imre Deak | fd0fe6a | 2015-11-04 21:25:32 +0200 | [diff] [blame] | 4013 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4014 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4015 | struct drm_i915_gem_object *obj; |
| 4016 | enum i915_cache_level level; |
| 4017 | int ret; |
| 4018 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4019 | switch (args->caching) { |
| 4020 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4021 | level = I915_CACHE_NONE; |
| 4022 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 4023 | case I915_CACHING_CACHED: |
Imre Deak | e5756c1 | 2015-08-14 18:43:30 +0300 | [diff] [blame] | 4024 | /* |
| 4025 | * Due to a HW issue on BXT A stepping, GPU stores via a |
| 4026 | * snooped mapping may leave stale data in a corresponding CPU |
| 4027 | * cacheline, whereas normally such cachelines would get |
| 4028 | * invalidated. |
| 4029 | */ |
Tvrtko Ursulin | ca37780 | 2016-03-02 12:10:31 +0000 | [diff] [blame] | 4030 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
Imre Deak | e5756c1 | 2015-08-14 18:43:30 +0300 | [diff] [blame] | 4031 | return -ENODEV; |
| 4032 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4033 | level = I915_CACHE_LLC; |
| 4034 | break; |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 4035 | case I915_CACHING_DISPLAY: |
| 4036 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 4037 | break; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4038 | default: |
| 4039 | return -EINVAL; |
| 4040 | } |
| 4041 | |
Imre Deak | fd0fe6a | 2015-11-04 21:25:32 +0200 | [diff] [blame] | 4042 | intel_runtime_pm_get(dev_priv); |
| 4043 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 4044 | ret = i915_mutex_lock_interruptible(dev); |
| 4045 | if (ret) |
Imre Deak | fd0fe6a | 2015-11-04 21:25:32 +0200 | [diff] [blame] | 4046 | goto rpm_put; |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 4047 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 4048 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4049 | if (&obj->base == NULL) { |
| 4050 | ret = -ENOENT; |
| 4051 | goto unlock; |
| 4052 | } |
| 4053 | |
| 4054 | ret = i915_gem_object_set_cache_level(obj, level); |
| 4055 | |
| 4056 | drm_gem_object_unreference(&obj->base); |
| 4057 | unlock: |
| 4058 | mutex_unlock(&dev->struct_mutex); |
Imre Deak | fd0fe6a | 2015-11-04 21:25:32 +0200 | [diff] [blame] | 4059 | rpm_put: |
| 4060 | intel_runtime_pm_put(dev_priv); |
| 4061 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4062 | return ret; |
| 4063 | } |
| 4064 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4065 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4066 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 4067 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 4068 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4069 | */ |
| 4070 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4071 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 4072 | u32 alignment, |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4073 | const struct i915_ggtt_view *view) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4074 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4075 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4076 | int ret; |
| 4077 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4078 | /* Mark the pin_display early so that we account for the |
| 4079 | * display coherency whilst setting up the cache domains. |
| 4080 | */ |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4081 | obj->pin_display++; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4082 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4083 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 4084 | * a result, we make sure that the pinning that is about to occur is |
| 4085 | * done with uncached PTEs. This is lowest common denominator for all |
| 4086 | * chipsets. |
| 4087 | * |
| 4088 | * However for gen6+, we could do better by using the GFDT bit instead |
| 4089 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 4090 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 4091 | */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 4092 | ret = i915_gem_object_set_cache_level(obj, |
| 4093 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4094 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4095 | goto err_unpin_display; |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4096 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4097 | /* As the user may map the buffer once pinned in the display plane |
| 4098 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 4099 | * always use map_and_fenceable for all scanout buffers. |
| 4100 | */ |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 4101 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
| 4102 | view->type == I915_GGTT_VIEW_NORMAL ? |
| 4103 | PIN_MAPPABLE : 0); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4104 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4105 | goto err_unpin_display; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4106 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 4107 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 4108 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4109 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4110 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4111 | |
| 4112 | /* It should now be out of any other write domains, and we can update |
| 4113 | * the domain values for our changes. |
| 4114 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 4115 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4116 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4117 | |
| 4118 | trace_i915_gem_object_change_domain(obj, |
| 4119 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4120 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4121 | |
| 4122 | return 0; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4123 | |
| 4124 | err_unpin_display: |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4125 | obj->pin_display--; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4126 | return ret; |
| 4127 | } |
| 4128 | |
| 4129 | void |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4130 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
| 4131 | const struct i915_ggtt_view *view) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4132 | { |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4133 | if (WARN_ON(obj->pin_display == 0)) |
| 4134 | return; |
| 4135 | |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4136 | i915_gem_object_ggtt_unpin_view(obj, view); |
| 4137 | |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4138 | obj->pin_display--; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4139 | } |
| 4140 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4141 | /** |
| 4142 | * Moves a single object to the CPU read, and possibly write domain. |
Tvrtko Ursulin | 14bb2c1 | 2016-06-03 14:02:17 +0100 | [diff] [blame] | 4143 | * @obj: object to act on |
| 4144 | * @write: requesting write or read-only access |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4145 | * |
| 4146 | * This function returns when the move is complete, including waiting on |
| 4147 | * flushes to occur. |
| 4148 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 4149 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 4150 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4151 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4152 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4153 | int ret; |
| 4154 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 4155 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 4156 | return 0; |
| 4157 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 4158 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 4159 | if (ret) |
| 4160 | return ret; |
| 4161 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4162 | i915_gem_object_flush_gtt_write_domain(obj); |
| 4163 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4164 | old_write_domain = obj->base.write_domain; |
| 4165 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4166 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4167 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4168 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 4169 | i915_gem_clflush_object(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4170 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4171 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4172 | } |
| 4173 | |
| 4174 | /* It should now be out of any other write domains, and we can update |
| 4175 | * the domain values for our changes. |
| 4176 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4177 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4178 | |
| 4179 | /* If we're writing through the CPU, then the GPU read domains will |
| 4180 | * need to be invalidated at next use. |
| 4181 | */ |
| 4182 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4183 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4184 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4185 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4186 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4187 | trace_i915_gem_object_change_domain(obj, |
| 4188 | old_read_domains, |
| 4189 | old_write_domain); |
| 4190 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4191 | return 0; |
| 4192 | } |
| 4193 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4194 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 4195 | * emitted over 20 msec ago. |
| 4196 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4197 | * Note that if we were to use the current jiffies each time around the loop, |
| 4198 | * we wouldn't escape the function with any frames outstanding if the time to |
| 4199 | * render a frame was over 20ms. |
| 4200 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4201 | * This should get us reasonable parallelism between CPU and GPU but also |
| 4202 | * relatively low latency when blocking on a particular request to finish. |
| 4203 | */ |
| 4204 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4205 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4206 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4207 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4208 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Chris Wilson | d0bc54f | 2015-05-21 21:01:48 +0100 | [diff] [blame] | 4209 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4210 | struct drm_i915_gem_request *request, *target = NULL; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4211 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4212 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 4213 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 4214 | if (ret) |
| 4215 | return ret; |
| 4216 | |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 4217 | /* ABI: return -EIO if already wedged */ |
| 4218 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
| 4219 | return -EIO; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 4220 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4221 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4222 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4223 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 4224 | break; |
| 4225 | |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 4226 | /* |
| 4227 | * Note that the request might not have been submitted yet. |
| 4228 | * In which case emitted_jiffies will be zero. |
| 4229 | */ |
| 4230 | if (!request->emitted_jiffies) |
| 4231 | continue; |
| 4232 | |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4233 | target = request; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4234 | } |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 4235 | if (target) |
| 4236 | i915_gem_request_reference(target); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4237 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4238 | |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4239 | if (target == NULL) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4240 | return 0; |
| 4241 | |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 4242 | ret = __i915_wait_request(target, true, NULL, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4243 | if (ret == 0) |
| 4244 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4245 | |
Chris Wilson | 73db04c | 2016-04-28 09:56:55 +0100 | [diff] [blame] | 4246 | i915_gem_request_unreference(target); |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 4247 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4248 | return ret; |
| 4249 | } |
| 4250 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4251 | static bool |
| 4252 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
| 4253 | { |
| 4254 | struct drm_i915_gem_object *obj = vma->obj; |
| 4255 | |
| 4256 | if (alignment && |
| 4257 | vma->node.start & (alignment - 1)) |
| 4258 | return true; |
| 4259 | |
| 4260 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
| 4261 | return true; |
| 4262 | |
| 4263 | if (flags & PIN_OFFSET_BIAS && |
| 4264 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
| 4265 | return true; |
| 4266 | |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 4267 | if (flags & PIN_OFFSET_FIXED && |
| 4268 | vma->node.start != (flags & PIN_OFFSET_MASK)) |
| 4269 | return true; |
| 4270 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4271 | return false; |
| 4272 | } |
| 4273 | |
Chris Wilson | d0710ab | 2015-11-20 14:16:39 +0000 | [diff] [blame] | 4274 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
| 4275 | { |
| 4276 | struct drm_i915_gem_object *obj = vma->obj; |
| 4277 | bool mappable, fenceable; |
| 4278 | u32 fence_size, fence_alignment; |
| 4279 | |
| 4280 | fence_size = i915_gem_get_gtt_size(obj->base.dev, |
| 4281 | obj->base.size, |
| 4282 | obj->tiling_mode); |
| 4283 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, |
| 4284 | obj->base.size, |
| 4285 | obj->tiling_mode, |
| 4286 | true); |
| 4287 | |
| 4288 | fenceable = (vma->node.size == fence_size && |
| 4289 | (vma->node.start & (fence_alignment - 1)) == 0); |
| 4290 | |
| 4291 | mappable = (vma->node.start + fence_size <= |
Joonas Lahtinen | 62106b4 | 2016-03-18 10:42:57 +0200 | [diff] [blame] | 4292 | to_i915(obj->base.dev)->ggtt.mappable_end); |
Chris Wilson | d0710ab | 2015-11-20 14:16:39 +0000 | [diff] [blame] | 4293 | |
| 4294 | obj->map_and_fenceable = mappable && fenceable; |
| 4295 | } |
| 4296 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4297 | static int |
| 4298 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, |
| 4299 | struct i915_address_space *vm, |
| 4300 | const struct i915_ggtt_view *ggtt_view, |
| 4301 | uint32_t alignment, |
| 4302 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4303 | { |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4304 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4305 | struct i915_vma *vma; |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4306 | unsigned bound; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4307 | int ret; |
| 4308 | |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4309 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
| 4310 | return -ENODEV; |
| 4311 | |
Daniel Vetter | bf3d149 | 2014-02-14 14:01:12 +0100 | [diff] [blame] | 4312 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4313 | return -EINVAL; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4314 | |
Chris Wilson | c826c44 | 2014-10-31 13:53:53 +0000 | [diff] [blame] | 4315 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
| 4316 | return -EINVAL; |
| 4317 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4318 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
| 4319 | return -EINVAL; |
| 4320 | |
| 4321 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : |
| 4322 | i915_gem_obj_to_vma(obj, vm); |
| 4323 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4324 | if (vma) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4325 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 4326 | return -EBUSY; |
| 4327 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4328 | if (i915_vma_misplaced(vma, alignment, flags)) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4329 | WARN(vma->pin_count, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4330 | "bo is already pinned in %s with incorrect alignment:" |
Michel Thierry | 088e0df | 2015-08-07 17:40:17 +0100 | [diff] [blame] | 4331 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4332 | " obj->map_and_fenceable=%d\n", |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4333 | ggtt_view ? "ggtt" : "ppgtt", |
Michel Thierry | 088e0df | 2015-08-07 17:40:17 +0100 | [diff] [blame] | 4334 | upper_32_bits(vma->node.start), |
| 4335 | lower_32_bits(vma->node.start), |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 4336 | alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4337 | !!(flags & PIN_MAPPABLE), |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4338 | obj->map_and_fenceable); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4339 | ret = i915_vma_unbind(vma); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4340 | if (ret) |
| 4341 | return ret; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4342 | |
| 4343 | vma = NULL; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4344 | } |
| 4345 | } |
| 4346 | |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4347 | bound = vma ? vma->bound : 0; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4348 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4349 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
| 4350 | flags); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 4351 | if (IS_ERR(vma)) |
| 4352 | return PTR_ERR(vma); |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 4353 | } else { |
| 4354 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 4355 | if (ret) |
| 4356 | return ret; |
| 4357 | } |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 4358 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 4359 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
| 4360 | (bound ^ vma->bound) & GLOBAL_BIND) { |
Chris Wilson | d0710ab | 2015-11-20 14:16:39 +0000 | [diff] [blame] | 4361 | __i915_vma_set_map_and_fenceable(vma); |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 4362 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
| 4363 | } |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4364 | |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4365 | vma->pin_count++; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4366 | return 0; |
| 4367 | } |
| 4368 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4369 | int |
| 4370 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 4371 | struct i915_address_space *vm, |
| 4372 | uint32_t alignment, |
| 4373 | uint64_t flags) |
| 4374 | { |
| 4375 | return i915_gem_object_do_pin(obj, vm, |
| 4376 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, |
| 4377 | alignment, flags); |
| 4378 | } |
| 4379 | |
| 4380 | int |
| 4381 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
| 4382 | const struct i915_ggtt_view *view, |
| 4383 | uint32_t alignment, |
| 4384 | uint64_t flags) |
| 4385 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 4386 | struct drm_device *dev = obj->base.dev; |
| 4387 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 4388 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
| 4389 | |
Matthew Auld | ade7daa | 2016-03-24 15:54:20 +0000 | [diff] [blame] | 4390 | BUG_ON(!view); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4391 | |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 4392 | return i915_gem_object_do_pin(obj, &ggtt->base, view, |
Tvrtko Ursulin | 6fafab7 | 2015-03-17 15:36:51 +0000 | [diff] [blame] | 4393 | alignment, flags | PIN_GLOBAL); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4394 | } |
| 4395 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4396 | void |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4397 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
| 4398 | const struct i915_ggtt_view *view) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4399 | { |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4400 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4401 | |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4402 | WARN_ON(vma->pin_count == 0); |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 4403 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4404 | |
Chris Wilson | 3015465 | 2015-04-07 17:28:24 +0100 | [diff] [blame] | 4405 | --vma->pin_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4406 | } |
| 4407 | |
| 4408 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4409 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4410 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4411 | { |
| 4412 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4413 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4414 | int ret; |
| 4415 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4416 | ret = i915_mutex_lock_interruptible(dev); |
| 4417 | if (ret) |
| 4418 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4419 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 4420 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4421 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4422 | ret = -ENOENT; |
| 4423 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4424 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4425 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4426 | /* Count all active objects as busy, even if they are currently not used |
| 4427 | * by the gpu. Users of this interface expect objects to eventually |
| 4428 | * become non-busy without any further actions, therefore emit any |
| 4429 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4430 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4431 | ret = i915_gem_object_flush_active(obj); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4432 | if (ret) |
| 4433 | goto unref; |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4434 | |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 4435 | args->busy = 0; |
| 4436 | if (obj->active) { |
| 4437 | int i; |
| 4438 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 4439 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 4440 | struct drm_i915_gem_request *req; |
| 4441 | |
| 4442 | req = obj->last_read_req[i]; |
| 4443 | if (req) |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 4444 | args->busy |= 1 << (16 + req->engine->exec_id); |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 4445 | } |
| 4446 | if (obj->last_write_req) |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 4447 | args->busy |= obj->last_write_req->engine->exec_id; |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 4448 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4449 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4450 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4451 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4452 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4453 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4454 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4455 | } |
| 4456 | |
| 4457 | int |
| 4458 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4459 | struct drm_file *file_priv) |
| 4460 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 4461 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4462 | } |
| 4463 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4464 | int |
| 4465 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4466 | struct drm_file *file_priv) |
| 4467 | { |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4468 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4469 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4470 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4471 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4472 | |
| 4473 | switch (args->madv) { |
| 4474 | case I915_MADV_DONTNEED: |
| 4475 | case I915_MADV_WILLNEED: |
| 4476 | break; |
| 4477 | default: |
| 4478 | return -EINVAL; |
| 4479 | } |
| 4480 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4481 | ret = i915_mutex_lock_interruptible(dev); |
| 4482 | if (ret) |
| 4483 | return ret; |
| 4484 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 4485 | obj = to_intel_bo(drm_gem_object_lookup(file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4486 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4487 | ret = -ENOENT; |
| 4488 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4489 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4490 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4491 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4492 | ret = -EINVAL; |
| 4493 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4494 | } |
| 4495 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4496 | if (obj->pages && |
| 4497 | obj->tiling_mode != I915_TILING_NONE && |
| 4498 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
| 4499 | if (obj->madv == I915_MADV_WILLNEED) |
| 4500 | i915_gem_object_unpin_pages(obj); |
| 4501 | if (args->madv == I915_MADV_WILLNEED) |
| 4502 | i915_gem_object_pin_pages(obj); |
| 4503 | } |
| 4504 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4505 | if (obj->madv != __I915_MADV_PURGED) |
| 4506 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4507 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4508 | /* if the object is no longer attached, discard its backing storage */ |
Daniel Vetter | be6a037 | 2015-03-18 10:46:04 +0100 | [diff] [blame] | 4509 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4510 | i915_gem_object_truncate(obj); |
| 4511 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4512 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4513 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4514 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4515 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4516 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4517 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4518 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4519 | } |
| 4520 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4521 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4522 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4523 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4524 | int i; |
| 4525 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4526 | INIT_LIST_HEAD(&obj->global_list); |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 4527 | for (i = 0; i < I915_NUM_ENGINES; i++) |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4528 | INIT_LIST_HEAD(&obj->engine_list[i]); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 4529 | INIT_LIST_HEAD(&obj->obj_exec_link); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4530 | INIT_LIST_HEAD(&obj->vma_list); |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 4531 | INIT_LIST_HEAD(&obj->batch_pool_link); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4532 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4533 | obj->ops = ops; |
| 4534 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4535 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4536 | obj->madv = I915_MADV_WILLNEED; |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4537 | |
| 4538 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4539 | } |
| 4540 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4541 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
Chris Wilson | de47266 | 2016-01-22 18:32:31 +0000 | [diff] [blame] | 4542 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4543 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4544 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4545 | }; |
| 4546 | |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 4547 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4548 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4549 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4550 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4551 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 4552 | gfp_t mask; |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 4553 | int ret; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4554 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4555 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4556 | if (obj == NULL) |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 4557 | return ERR_PTR(-ENOMEM); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4558 | |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 4559 | ret = drm_gem_object_init(dev, &obj->base, size); |
| 4560 | if (ret) |
| 4561 | goto fail; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4562 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4563 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4564 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4565 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4566 | mask &= ~__GFP_HIGHMEM; |
| 4567 | mask |= __GFP_DMA32; |
| 4568 | } |
| 4569 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4570 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4571 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4572 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4573 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4574 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4575 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4576 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4577 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 4578 | if (HAS_LLC(dev)) { |
| 4579 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 4580 | * cache) for about a 10% performance improvement |
| 4581 | * compared to uncached. Graphics requests other than |
| 4582 | * display scanout are coherent with the CPU in |
| 4583 | * accessing this cache. This means in this mode we |
| 4584 | * don't need to clflush on the CPU side, and on the |
| 4585 | * GPU side we only need to flush internal caches to |
| 4586 | * get data visible to the CPU. |
| 4587 | * |
| 4588 | * However, we maintain the display planes as UC, and so |
| 4589 | * need to rebind when first used as such. |
| 4590 | */ |
| 4591 | obj->cache_level = I915_CACHE_LLC; |
| 4592 | } else |
| 4593 | obj->cache_level = I915_CACHE_NONE; |
| 4594 | |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 4595 | trace_i915_gem_object_create(obj); |
| 4596 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4597 | return obj; |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 4598 | |
| 4599 | fail: |
| 4600 | i915_gem_object_free(obj); |
| 4601 | |
| 4602 | return ERR_PTR(ret); |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4603 | } |
| 4604 | |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4605 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
| 4606 | { |
| 4607 | /* If we are the last user of the backing storage (be it shmemfs |
| 4608 | * pages or stolen etc), we know that the pages are going to be |
| 4609 | * immediately released. In this case, we can then skip copying |
| 4610 | * back the contents from the GPU. |
| 4611 | */ |
| 4612 | |
| 4613 | if (obj->madv != I915_MADV_WILLNEED) |
| 4614 | return false; |
| 4615 | |
| 4616 | if (obj->base.filp == NULL) |
| 4617 | return true; |
| 4618 | |
| 4619 | /* At first glance, this looks racy, but then again so would be |
| 4620 | * userspace racing mmap against close. However, the first external |
| 4621 | * reference to the filp can only be obtained through the |
| 4622 | * i915_gem_mmap_ioctl() which safeguards us against the user |
| 4623 | * acquiring such a reference whilst we are in the middle of |
| 4624 | * freeing the object. |
| 4625 | */ |
| 4626 | return atomic_long_read(&obj->base.filp->f_count) == 1; |
| 4627 | } |
| 4628 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4629 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4630 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4631 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4632 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4633 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4634 | struct i915_vma *vma, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4635 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4636 | intel_runtime_pm_get(dev_priv); |
| 4637 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 4638 | trace_i915_gem_object_destroy(obj); |
| 4639 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 4640 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4641 | int ret; |
| 4642 | |
| 4643 | vma->pin_count = 0; |
| 4644 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4645 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4646 | bool was_interruptible; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4647 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4648 | was_interruptible = dev_priv->mm.interruptible; |
| 4649 | dev_priv->mm.interruptible = false; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4650 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4651 | WARN_ON(i915_vma_unbind(vma)); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4652 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4653 | dev_priv->mm.interruptible = was_interruptible; |
| 4654 | } |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4655 | } |
| 4656 | |
Ben Widawsky | 1d64ae7 | 2013-05-31 14:46:20 -0700 | [diff] [blame] | 4657 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4658 | * before progressing. */ |
| 4659 | if (obj->stolen) |
| 4660 | i915_gem_object_unpin_pages(obj); |
| 4661 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 4662 | WARN_ON(obj->frontbuffer_bits); |
| 4663 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4664 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
| 4665 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
| 4666 | obj->tiling_mode != I915_TILING_NONE) |
| 4667 | i915_gem_object_unpin_pages(obj); |
| 4668 | |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 4669 | if (WARN_ON(obj->pages_pin_count)) |
| 4670 | obj->pages_pin_count = 0; |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4671 | if (discard_backing_storage(obj)) |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 4672 | obj->madv = I915_MADV_DONTNEED; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4673 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 4674 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4675 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 4676 | BUG_ON(obj->pages); |
| 4677 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 4678 | if (obj->base.import_attach) |
| 4679 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4680 | |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 4681 | if (obj->ops->release) |
| 4682 | obj->ops->release(obj); |
| 4683 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4684 | drm_gem_object_release(&obj->base); |
| 4685 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4686 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4687 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4688 | i915_gem_object_free(obj); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4689 | |
| 4690 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4691 | } |
| 4692 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4693 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 4694 | struct i915_address_space *vm) |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4695 | { |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4696 | struct i915_vma *vma; |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 4697 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
Tvrtko Ursulin | 1b68372 | 2015-11-12 11:59:55 +0000 | [diff] [blame] | 4698 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
| 4699 | vma->vm == vm) |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4700 | return vma; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4701 | } |
| 4702 | return NULL; |
| 4703 | } |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4704 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4705 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, |
| 4706 | const struct i915_ggtt_view *view) |
| 4707 | { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4708 | struct i915_vma *vma; |
| 4709 | |
Tvrtko Ursulin | 598b9ec | 2016-04-21 13:04:44 +0100 | [diff] [blame] | 4710 | GEM_BUG_ON(!view); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4711 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 4712 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
Tvrtko Ursulin | 598b9ec | 2016-04-21 13:04:44 +0100 | [diff] [blame] | 4713 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4714 | return vma; |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4715 | return NULL; |
| 4716 | } |
| 4717 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4718 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4719 | { |
| 4720 | WARN_ON(vma->node.allocated); |
Chris Wilson | aaa0566 | 2013-08-20 12:56:40 +0100 | [diff] [blame] | 4721 | |
| 4722 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4723 | if (!list_empty(&vma->exec_list)) |
| 4724 | return; |
| 4725 | |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 4726 | if (!vma->is_ggtt) |
| 4727 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4728 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 4729 | list_del(&vma->obj_link); |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 4730 | |
Chris Wilson | e20d2ab | 2015-04-07 16:20:58 +0100 | [diff] [blame] | 4731 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4732 | } |
| 4733 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4734 | static void |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4735 | i915_gem_stop_engines(struct drm_device *dev) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4736 | { |
| 4737 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4738 | struct intel_engine_cs *engine; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4739 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 4740 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4741 | dev_priv->gt.stop_engine(engine); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4742 | } |
| 4743 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4744 | int |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4745 | i915_gem_suspend(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4746 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4747 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4748 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4749 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4750 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4751 | ret = i915_gpu_idle(dev); |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4752 | if (ret) |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4753 | goto err; |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4754 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 4755 | i915_gem_retire_requests(dev_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4756 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4757 | i915_gem_stop_engines(dev); |
Chris Wilson | b2e862d | 2016-04-28 09:56:41 +0100 | [diff] [blame] | 4758 | i915_gem_context_lost(dev_priv); |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4759 | mutex_unlock(&dev->struct_mutex); |
| 4760 | |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 4761 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4762 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
Deepak S | 274fa1c | 2014-08-05 07:51:20 -0700 | [diff] [blame] | 4763 | flush_delayed_work(&dev_priv->mm.idle_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4764 | |
Chris Wilson | bdcf120 | 2014-11-25 11:56:33 +0000 | [diff] [blame] | 4765 | /* Assert that we sucessfully flushed all the work and |
| 4766 | * reset the GPU back to its idle, low power state. |
| 4767 | */ |
| 4768 | WARN_ON(dev_priv->mm.busy); |
| 4769 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4770 | return 0; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4771 | |
| 4772 | err: |
| 4773 | mutex_unlock(&dev->struct_mutex); |
| 4774 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4775 | } |
| 4776 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4777 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4778 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4779 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4780 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4781 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4782 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4783 | return; |
| 4784 | |
| 4785 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4786 | DISP_TILE_SURFACE_SWIZZLING); |
| 4787 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4788 | if (IS_GEN5(dev)) |
| 4789 | return; |
| 4790 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4791 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4792 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4793 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4794 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4795 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 31a5336 | 2013-11-02 21:07:04 -0700 | [diff] [blame] | 4796 | else if (IS_GEN8(dev)) |
| 4797 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4798 | else |
| 4799 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4800 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4801 | |
Ville Syrjälä | 81e7f20 | 2014-08-15 01:21:55 +0300 | [diff] [blame] | 4802 | static void init_unused_ring(struct drm_device *dev, u32 base) |
| 4803 | { |
| 4804 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4805 | |
| 4806 | I915_WRITE(RING_CTL(base), 0); |
| 4807 | I915_WRITE(RING_HEAD(base), 0); |
| 4808 | I915_WRITE(RING_TAIL(base), 0); |
| 4809 | I915_WRITE(RING_START(base), 0); |
| 4810 | } |
| 4811 | |
| 4812 | static void init_unused_rings(struct drm_device *dev) |
| 4813 | { |
| 4814 | if (IS_I830(dev)) { |
| 4815 | init_unused_ring(dev, PRB1_BASE); |
| 4816 | init_unused_ring(dev, SRB0_BASE); |
| 4817 | init_unused_ring(dev, SRB1_BASE); |
| 4818 | init_unused_ring(dev, SRB2_BASE); |
| 4819 | init_unused_ring(dev, SRB3_BASE); |
| 4820 | } else if (IS_GEN2(dev)) { |
| 4821 | init_unused_ring(dev, SRB0_BASE); |
| 4822 | init_unused_ring(dev, SRB1_BASE); |
| 4823 | } else if (IS_GEN3(dev)) { |
| 4824 | init_unused_ring(dev, PRB1_BASE); |
| 4825 | init_unused_ring(dev, PRB2_BASE); |
| 4826 | } |
| 4827 | } |
| 4828 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4829 | int i915_gem_init_engines(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4830 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4831 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4832 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4833 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4834 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4835 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4836 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4837 | |
| 4838 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4839 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4840 | if (ret) |
| 4841 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4842 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4843 | |
Jani Nikula | d39398f | 2015-10-07 11:17:44 +0300 | [diff] [blame] | 4844 | if (HAS_BLT(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4845 | ret = intel_init_blt_ring_buffer(dev); |
| 4846 | if (ret) |
| 4847 | goto cleanup_bsd_ring; |
| 4848 | } |
| 4849 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4850 | if (HAS_VEBOX(dev)) { |
| 4851 | ret = intel_init_vebox_ring_buffer(dev); |
| 4852 | if (ret) |
| 4853 | goto cleanup_blt_ring; |
| 4854 | } |
| 4855 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4856 | if (HAS_BSD2(dev)) { |
| 4857 | ret = intel_init_bsd2_ring_buffer(dev); |
| 4858 | if (ret) |
| 4859 | goto cleanup_vebox_ring; |
| 4860 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4861 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4862 | return 0; |
| 4863 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4864 | cleanup_vebox_ring: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4865 | intel_cleanup_engine(&dev_priv->engine[VECS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4866 | cleanup_blt_ring: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4867 | intel_cleanup_engine(&dev_priv->engine[BCS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4868 | cleanup_bsd_ring: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4869 | intel_cleanup_engine(&dev_priv->engine[VCS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4870 | cleanup_render_ring: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4871 | intel_cleanup_engine(&dev_priv->engine[RCS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4872 | |
| 4873 | return ret; |
| 4874 | } |
| 4875 | |
| 4876 | int |
| 4877 | i915_gem_init_hw(struct drm_device *dev) |
| 4878 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4879 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4880 | struct intel_engine_cs *engine; |
Chris Wilson | d200cda | 2016-04-28 09:56:44 +0100 | [diff] [blame] | 4881 | int ret; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4882 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4883 | /* Double layer security blanket, see i915_gem_init() */ |
| 4884 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 4885 | |
Mika Kuoppala | 3accaf7 | 2016-04-13 17:26:43 +0300 | [diff] [blame] | 4886 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 4887 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4888 | |
Ville Syrjälä | 0bf2134 | 2013-11-29 14:56:12 +0200 | [diff] [blame] | 4889 | if (IS_HASWELL(dev)) |
| 4890 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 4891 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 4892 | |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4893 | if (HAS_PCH_NOP(dev)) { |
Daniel Vetter | 6ba844b | 2014-01-22 23:39:30 +0100 | [diff] [blame] | 4894 | if (IS_IVYBRIDGE(dev)) { |
| 4895 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4896 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4897 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4898 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 4899 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 4900 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 4901 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 4902 | } |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4903 | } |
| 4904 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4905 | i915_gem_init_swizzling(dev); |
| 4906 | |
Daniel Vetter | d5abdfd | 2014-11-20 09:45:19 +0100 | [diff] [blame] | 4907 | /* |
| 4908 | * At least 830 can leave some of the unused rings |
| 4909 | * "active" (ie. head != tail) after resume which |
| 4910 | * will prevent c3 entry. Makes sure all unused rings |
| 4911 | * are totally idle. |
| 4912 | */ |
| 4913 | init_unused_rings(dev); |
| 4914 | |
Dave Gordon | ed54c1a | 2016-01-19 19:02:54 +0000 | [diff] [blame] | 4915 | BUG_ON(!dev_priv->kernel_context); |
John Harrison | 90638cc | 2015-05-29 17:43:37 +0100 | [diff] [blame] | 4916 | |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 4917 | ret = i915_ppgtt_init_hw(dev); |
| 4918 | if (ret) { |
| 4919 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); |
| 4920 | goto out; |
| 4921 | } |
| 4922 | |
| 4923 | /* Need to do basic initialisation of all rings first: */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 4924 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4925 | ret = engine->init_hw(engine); |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 4926 | if (ret) |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4927 | goto out; |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 4928 | } |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4929 | |
Peter Antoine | 0ccdacf | 2016-04-13 15:03:25 +0100 | [diff] [blame] | 4930 | intel_mocs_init_l3cc_table(dev); |
| 4931 | |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 4932 | /* We can't enable contexts until all firmware is loaded */ |
Dave Gordon | e556f7c | 2016-06-07 09:14:49 +0100 | [diff] [blame^] | 4933 | ret = intel_guc_setup(dev); |
| 4934 | if (ret) |
| 4935 | goto out; |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 4936 | |
Nick Hoath | e84fe80 | 2015-09-11 12:53:46 +0100 | [diff] [blame] | 4937 | /* |
| 4938 | * Increment the next seqno by 0x100 so we have a visible break |
| 4939 | * on re-initialisation |
| 4940 | */ |
| 4941 | ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100); |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 4942 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4943 | out: |
| 4944 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4945 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4946 | } |
| 4947 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4948 | int i915_gem_init(struct drm_device *dev) |
| 4949 | { |
| 4950 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4951 | int ret; |
| 4952 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4953 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4954 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4955 | if (!i915.enable_execlists) { |
John Harrison | f3dc74c | 2015-03-19 12:30:06 +0000 | [diff] [blame] | 4956 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4957 | dev_priv->gt.init_engines = i915_gem_init_engines; |
| 4958 | dev_priv->gt.cleanup_engine = intel_cleanup_engine; |
| 4959 | dev_priv->gt.stop_engine = intel_stop_engine; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 4960 | } else { |
John Harrison | f3dc74c | 2015-03-19 12:30:06 +0000 | [diff] [blame] | 4961 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4962 | dev_priv->gt.init_engines = intel_logical_rings_init; |
| 4963 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
| 4964 | dev_priv->gt.stop_engine = intel_logical_ring_stop; |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4965 | } |
| 4966 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4967 | /* This is just a security blanket to placate dragons. |
| 4968 | * On some systems, we very sporadically observe that the first TLBs |
| 4969 | * used by the CS may be stale, despite us poking the TLB reset. If |
| 4970 | * we hold the forcewake during initialisation these problems |
| 4971 | * just magically go away. |
| 4972 | */ |
| 4973 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 4974 | |
Chris Wilson | 72778cb | 2016-05-19 16:17:16 +0100 | [diff] [blame] | 4975 | i915_gem_init_userptr(dev_priv); |
Joonas Lahtinen | d85489d | 2016-03-24 16:47:46 +0200 | [diff] [blame] | 4976 | i915_gem_init_ggtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4977 | |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4978 | ret = i915_gem_context_init(dev); |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 4979 | if (ret) |
| 4980 | goto out_unlock; |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4981 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4982 | ret = dev_priv->gt.init_engines(dev); |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 4983 | if (ret) |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 4984 | goto out_unlock; |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 4985 | |
| 4986 | ret = i915_gem_init_hw(dev); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4987 | if (ret == -EIO) { |
| 4988 | /* Allow ring initialisation to fail by marking the GPU as |
| 4989 | * wedged. But we only want to do this where the GPU is angry, |
| 4990 | * for all other failure, such as an allocation failure, bail. |
| 4991 | */ |
| 4992 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
Peter Zijlstra | 805de8f4 | 2015-04-24 01:12:32 +0200 | [diff] [blame] | 4993 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4994 | ret = 0; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4995 | } |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 4996 | |
| 4997 | out_unlock: |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4998 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 4999 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5000 | |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 5001 | return ret; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5002 | } |
| 5003 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5004 | void |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 5005 | i915_gem_cleanup_engines(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5006 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 5007 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 5008 | struct intel_engine_cs *engine; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5009 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 5010 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 5011 | dev_priv->gt.cleanup_engine(engine); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5012 | } |
| 5013 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5014 | static void |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 5015 | init_engine_lists(struct intel_engine_cs *engine) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5016 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 5017 | INIT_LIST_HEAD(&engine->active_list); |
| 5018 | INIT_LIST_HEAD(&engine->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5019 | } |
| 5020 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5021 | void |
Imre Deak | 40ae4e1 | 2016-03-16 14:54:03 +0200 | [diff] [blame] | 5022 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) |
| 5023 | { |
| 5024 | struct drm_device *dev = dev_priv->dev; |
| 5025 | |
| 5026 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && |
| 5027 | !IS_CHERRYVIEW(dev_priv)) |
| 5028 | dev_priv->num_fence_regs = 32; |
| 5029 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || |
| 5030 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) |
| 5031 | dev_priv->num_fence_regs = 16; |
| 5032 | else |
| 5033 | dev_priv->num_fence_regs = 8; |
| 5034 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 5035 | if (intel_vgpu_active(dev_priv)) |
Imre Deak | 40ae4e1 | 2016-03-16 14:54:03 +0200 | [diff] [blame] | 5036 | dev_priv->num_fence_regs = |
| 5037 | I915_READ(vgtif_reg(avail_rs.fence_num)); |
| 5038 | |
| 5039 | /* Initialize fence registers to zero */ |
| 5040 | i915_gem_restore_fences(dev); |
| 5041 | |
| 5042 | i915_gem_detect_bit_6_swizzle(dev); |
| 5043 | } |
| 5044 | |
| 5045 | void |
Imre Deak | d64aa09 | 2016-01-19 15:26:29 +0200 | [diff] [blame] | 5046 | i915_gem_load_init(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5047 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 5048 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 5049 | int i; |
| 5050 | |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 5051 | dev_priv->objects = |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 5052 | kmem_cache_create("i915_gem_object", |
| 5053 | sizeof(struct drm_i915_gem_object), 0, |
| 5054 | SLAB_HWCACHE_ALIGN, |
| 5055 | NULL); |
Chris Wilson | e20d2ab | 2015-04-07 16:20:58 +0100 | [diff] [blame] | 5056 | dev_priv->vmas = |
| 5057 | kmem_cache_create("i915_gem_vma", |
| 5058 | sizeof(struct i915_vma), 0, |
| 5059 | SLAB_HWCACHE_ALIGN, |
| 5060 | NULL); |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 5061 | dev_priv->requests = |
| 5062 | kmem_cache_create("i915_gem_request", |
| 5063 | sizeof(struct drm_i915_gem_request), 0, |
| 5064 | SLAB_HWCACHE_ALIGN, |
| 5065 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5066 | |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 5067 | INIT_LIST_HEAD(&dev_priv->vm_list); |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 5068 | INIT_LIST_HEAD(&dev_priv->context_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 5069 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 5070 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 5071 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 5072 | for (i = 0; i < I915_NUM_ENGINES; i++) |
| 5073 | init_engine_lists(&dev_priv->engine[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 5074 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 5075 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5076 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 5077 | i915_gem_retire_work_handler); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5078 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 5079 | i915_gem_idle_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 5080 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5081 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 5082 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 5083 | |
Nick Hoath | e84fe80 | 2015-09-11 12:53:46 +0100 | [diff] [blame] | 5084 | /* |
| 5085 | * Set initial sequence number for requests. |
| 5086 | * Using this number allows the wraparound to happen early, |
| 5087 | * catching any obvious problems. |
| 5088 | */ |
| 5089 | dev_priv->next_seqno = ((u32)~0 - 0x1100); |
| 5090 | dev_priv->last_seqno = ((u32)~0 - 0x1101); |
| 5091 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 5092 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 5093 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5094 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5095 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 5096 | dev_priv->mm.interruptible = true; |
| 5097 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 5098 | mutex_init(&dev_priv->fb_tracking.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5099 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5100 | |
Imre Deak | d64aa09 | 2016-01-19 15:26:29 +0200 | [diff] [blame] | 5101 | void i915_gem_load_cleanup(struct drm_device *dev) |
| 5102 | { |
| 5103 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 5104 | |
| 5105 | kmem_cache_destroy(dev_priv->requests); |
| 5106 | kmem_cache_destroy(dev_priv->vmas); |
| 5107 | kmem_cache_destroy(dev_priv->objects); |
| 5108 | } |
| 5109 | |
Chris Wilson | 461fb99 | 2016-05-14 07:26:33 +0100 | [diff] [blame] | 5110 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
| 5111 | { |
| 5112 | struct drm_i915_gem_object *obj; |
| 5113 | |
| 5114 | /* Called just before we write the hibernation image. |
| 5115 | * |
| 5116 | * We need to update the domain tracking to reflect that the CPU |
| 5117 | * will be accessing all the pages to create and restore from the |
| 5118 | * hibernation, and so upon restoration those pages will be in the |
| 5119 | * CPU domain. |
| 5120 | * |
| 5121 | * To make sure the hibernation image contains the latest state, |
| 5122 | * we update that state just before writing out the image. |
| 5123 | */ |
| 5124 | |
| 5125 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 5126 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 5127 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 5128 | } |
| 5129 | |
| 5130 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 5131 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 5132 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 5133 | } |
| 5134 | |
| 5135 | return 0; |
| 5136 | } |
| 5137 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5138 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5139 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5140 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5141 | |
| 5142 | /* Clean up our request list when the client is going away, so that |
| 5143 | * later retire_requests won't dereference our soon-to-be-gone |
| 5144 | * file_priv. |
| 5145 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5146 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5147 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5148 | struct drm_i915_gem_request *request; |
| 5149 | |
| 5150 | request = list_first_entry(&file_priv->mm.request_list, |
| 5151 | struct drm_i915_gem_request, |
| 5152 | client_list); |
| 5153 | list_del(&request->client_list); |
| 5154 | request->file_priv = NULL; |
| 5155 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5156 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5157 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5158 | if (!list_empty(&file_priv->rps.link)) { |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 5159 | spin_lock(&to_i915(dev)->rps.client_lock); |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5160 | list_del(&file_priv->rps.link); |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 5161 | spin_unlock(&to_i915(dev)->rps.client_lock); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 5162 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5163 | } |
| 5164 | |
| 5165 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 5166 | { |
| 5167 | struct drm_i915_file_private *file_priv; |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5168 | int ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5169 | |
| 5170 | DRM_DEBUG_DRIVER("\n"); |
| 5171 | |
| 5172 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 5173 | if (!file_priv) |
| 5174 | return -ENOMEM; |
| 5175 | |
| 5176 | file->driver_priv = file_priv; |
| 5177 | file_priv->dev_priv = dev->dev_private; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 5178 | file_priv->file = file; |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5179 | INIT_LIST_HEAD(&file_priv->rps.link); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5180 | |
| 5181 | spin_lock_init(&file_priv->mm.lock); |
| 5182 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5183 | |
Tvrtko Ursulin | de1add3 | 2016-01-15 15:12:50 +0000 | [diff] [blame] | 5184 | file_priv->bsd_ring = -1; |
| 5185 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5186 | ret = i915_gem_context_open(dev, file); |
| 5187 | if (ret) |
| 5188 | kfree(file_priv); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5189 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5190 | return ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5191 | } |
| 5192 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 5193 | /** |
| 5194 | * i915_gem_track_fb - update frontbuffer tracking |
Geliang Tang | d9072a3 | 2015-09-15 05:58:44 -0700 | [diff] [blame] | 5195 | * @old: current GEM buffer for the frontbuffer slots |
| 5196 | * @new: new GEM buffer for the frontbuffer slots |
| 5197 | * @frontbuffer_bits: bitmask of frontbuffer slots |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 5198 | * |
| 5199 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them |
| 5200 | * from @old and setting them in @new. Both @old and @new can be NULL. |
| 5201 | */ |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 5202 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 5203 | struct drm_i915_gem_object *new, |
| 5204 | unsigned frontbuffer_bits) |
| 5205 | { |
| 5206 | if (old) { |
| 5207 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
| 5208 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
| 5209 | old->frontbuffer_bits &= ~frontbuffer_bits; |
| 5210 | } |
| 5211 | |
| 5212 | if (new) { |
| 5213 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
| 5214 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
| 5215 | new->frontbuffer_bits |= frontbuffer_bits; |
| 5216 | } |
| 5217 | } |
| 5218 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5219 | /* All the new VM stuff */ |
Michel Thierry | 088e0df | 2015-08-07 17:40:17 +0100 | [diff] [blame] | 5220 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 5221 | struct i915_address_space *vm) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5222 | { |
| 5223 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5224 | struct i915_vma *vma; |
| 5225 | |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 5226 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5227 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5228 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 5229 | if (vma->is_ggtt && |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5230 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5231 | continue; |
| 5232 | if (vma->vm == vm) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5233 | return vma->node.start; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5234 | } |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5235 | |
Daniel Vetter | f25748ea | 2014-06-17 22:34:38 +0200 | [diff] [blame] | 5236 | WARN(1, "%s vma for this object not found.\n", |
| 5237 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5238 | return -1; |
| 5239 | } |
| 5240 | |
Michel Thierry | 088e0df | 2015-08-07 17:40:17 +0100 | [diff] [blame] | 5241 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
| 5242 | const struct i915_ggtt_view *view) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5243 | { |
| 5244 | struct i915_vma *vma; |
| 5245 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5246 | list_for_each_entry(vma, &o->vma_list, obj_link) |
Tvrtko Ursulin | 8aac222 | 2016-04-21 13:04:45 +0100 | [diff] [blame] | 5247 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5248 | return vma->node.start; |
| 5249 | |
Tvrtko Ursulin | 5678ad7 | 2015-03-17 14:45:29 +0000 | [diff] [blame] | 5250 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5251 | return -1; |
| 5252 | } |
| 5253 | |
| 5254 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 5255 | struct i915_address_space *vm) |
| 5256 | { |
| 5257 | struct i915_vma *vma; |
| 5258 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5259 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 5260 | if (vma->is_ggtt && |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5261 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5262 | continue; |
| 5263 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
| 5264 | return true; |
| 5265 | } |
| 5266 | |
| 5267 | return false; |
| 5268 | } |
| 5269 | |
| 5270 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 5271 | const struct i915_ggtt_view *view) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5272 | { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5273 | struct i915_vma *vma; |
| 5274 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5275 | list_for_each_entry(vma, &o->vma_list, obj_link) |
Tvrtko Ursulin | ff5ec22 | 2016-04-21 13:04:46 +0100 | [diff] [blame] | 5276 | if (vma->is_ggtt && |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 5277 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 5278 | drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5279 | return true; |
| 5280 | |
| 5281 | return false; |
| 5282 | } |
| 5283 | |
| 5284 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 5285 | { |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5286 | struct i915_vma *vma; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5287 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5288 | list_for_each_entry(vma, &o->vma_list, obj_link) |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5289 | if (drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5290 | return true; |
| 5291 | |
| 5292 | return false; |
| 5293 | } |
| 5294 | |
Tvrtko Ursulin | 8da3272 | 2016-04-21 13:04:43 +0100 | [diff] [blame] | 5295 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5296 | { |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5297 | struct i915_vma *vma; |
| 5298 | |
Tvrtko Ursulin | 8da3272 | 2016-04-21 13:04:43 +0100 | [diff] [blame] | 5299 | GEM_BUG_ON(list_empty(&o->vma_list)); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5300 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5301 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 5302 | if (vma->is_ggtt && |
Tvrtko Ursulin | 8da3272 | 2016-04-21 13:04:43 +0100 | [diff] [blame] | 5303 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5304 | return vma->node.size; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5305 | } |
Tvrtko Ursulin | 8da3272 | 2016-04-21 13:04:43 +0100 | [diff] [blame] | 5306 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5307 | return 0; |
| 5308 | } |
| 5309 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5310 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5311 | { |
| 5312 | struct i915_vma *vma; |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5313 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5314 | if (vma->pin_count > 0) |
| 5315 | return true; |
Joonas Lahtinen | a6631ae | 2015-05-06 14:34:58 +0300 | [diff] [blame] | 5316 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5317 | return false; |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5318 | } |
Dave Gordon | ea70299 | 2015-07-09 19:29:02 +0100 | [diff] [blame] | 5319 | |
Dave Gordon | 033908a | 2015-12-10 18:51:23 +0000 | [diff] [blame] | 5320 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
| 5321 | struct page * |
| 5322 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) |
| 5323 | { |
| 5324 | struct page *page; |
| 5325 | |
| 5326 | /* Only default objects have per-page dirty tracking */ |
Chris Wilson | de47266 | 2016-01-22 18:32:31 +0000 | [diff] [blame] | 5327 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
Dave Gordon | 033908a | 2015-12-10 18:51:23 +0000 | [diff] [blame] | 5328 | return NULL; |
| 5329 | |
| 5330 | page = i915_gem_object_get_page(obj, n); |
| 5331 | set_page_dirty(page); |
| 5332 | return page; |
| 5333 | } |
| 5334 | |
Dave Gordon | ea70299 | 2015-07-09 19:29:02 +0100 | [diff] [blame] | 5335 | /* Allocate a new GEM object and fill it with the supplied data */ |
| 5336 | struct drm_i915_gem_object * |
| 5337 | i915_gem_object_create_from_data(struct drm_device *dev, |
| 5338 | const void *data, size_t size) |
| 5339 | { |
| 5340 | struct drm_i915_gem_object *obj; |
| 5341 | struct sg_table *sg; |
| 5342 | size_t bytes; |
| 5343 | int ret; |
| 5344 | |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 5345 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
Chris Wilson | fe3db79 | 2016-04-25 13:32:13 +0100 | [diff] [blame] | 5346 | if (IS_ERR(obj)) |
Dave Gordon | ea70299 | 2015-07-09 19:29:02 +0100 | [diff] [blame] | 5347 | return obj; |
| 5348 | |
| 5349 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 5350 | if (ret) |
| 5351 | goto fail; |
| 5352 | |
| 5353 | ret = i915_gem_object_get_pages(obj); |
| 5354 | if (ret) |
| 5355 | goto fail; |
| 5356 | |
| 5357 | i915_gem_object_pin_pages(obj); |
| 5358 | sg = obj->pages; |
| 5359 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
Dave Gordon | 9e7d18c | 2015-12-10 18:51:24 +0000 | [diff] [blame] | 5360 | obj->dirty = 1; /* Backing store is now out of date */ |
Dave Gordon | ea70299 | 2015-07-09 19:29:02 +0100 | [diff] [blame] | 5361 | i915_gem_object_unpin_pages(obj); |
| 5362 | |
| 5363 | if (WARN_ON(bytes != size)) { |
| 5364 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); |
| 5365 | ret = -EFAULT; |
| 5366 | goto fail; |
| 5367 | } |
| 5368 | |
| 5369 | return obj; |
| 5370 | |
| 5371 | fail: |
| 5372 | drm_gem_object_unreference(&obj->base); |
| 5373 | return ERR_PTR(ret); |
| 5374 | } |