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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070042#include <drm/drm_plane_helper.h>
43#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080044#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080045
Matt Roper465c1202014-05-29 08:06:54 -070046/* Primary plane formats supported by all gen */
47#define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53/* Primary plane formats for gen <= 3 */
54static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58};
59
60/* Primary plane formats for gen >= 4 */
61static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69};
70
Matt Roper3d7d6512014-06-10 08:28:13 -070071/* Cursor formats */
72static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74};
75
Chris Wilson6b383a72010-09-13 13:54:26 +010076static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080077
Jesse Barnesf1f644d2013-06-27 00:39:25 +030078static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030080static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030082
Damien Lespiaue7457a92013-08-08 22:28:59 +010083static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080085static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020089static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020091static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -070092 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +020094static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +020095static void haswell_set_pipeconf(struct drm_crtc *crtc);
96static void intel_set_pipe_csc(struct drm_crtc *crtc);
Ville Syrjäläd288f652014-10-28 13:20:22 +020097static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100101
Dave Airlie0e32b392014-05-02 14:02:48 +1000102static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103{
104 if (!connector->mst_port)
105 return connector->encoder;
106 else
107 return &connector->mst_port->mst_encoders[pipe]->base;
108}
109
Jesse Barnes79e53942008-11-07 14:24:08 -0800110typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400111 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800112} intel_range_t;
113
114typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400115 int dot_limit;
116 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800117} intel_p2_t;
118
Ma Lingd4906092009-03-18 20:13:27 +0800119typedef struct intel_limit intel_limit_t;
120struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
122 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800123};
Jesse Barnes79e53942008-11-07 14:24:08 -0800124
Daniel Vetterd2acd212012-10-20 20:57:43 +0200125int
126intel_pch_rawclk(struct drm_device *dev)
127{
128 struct drm_i915_private *dev_priv = dev->dev_private;
129
130 WARN_ON(!HAS_PCH_SPLIT(dev));
131
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133}
134
Chris Wilson021357a2010-09-07 20:54:59 +0100135static inline u32 /* units of 100MHz */
136intel_fdi_link_freq(struct drm_device *dev)
137{
Chris Wilson8b99e682010-10-13 09:59:17 +0100138 if (IS_GEN5(dev)) {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141 } else
142 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100143}
144
Daniel Vetter5d536e22013-07-06 12:52:06 +0200145static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400146 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200147 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200148 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
Daniel Vetter5d536e22013-07-06 12:52:06 +0200158static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200160 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200161 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
169};
170
Keith Packarde4b36692009-06-05 19:22:17 -0700171static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400172 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200173 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200174 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700182};
Eric Anholt273e27c2011-03-30 13:01:10 -0700183
Keith Packarde4b36692009-06-05 19:22:17 -0700184static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700195};
196
197static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700208};
209
Eric Anholt273e27c2011-03-30 13:01:10 -0700210
Keith Packarde4b36692009-06-05 19:22:17 -0700211static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
221 .p2_slow = 10,
222 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800223 },
Keith Packarde4b36692009-06-05 19:22:17 -0700224};
225
226static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700237};
238
239static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800250 },
Keith Packarde4b36692009-06-05 19:22:17 -0700251};
252
253static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800264 },
Keith Packarde4b36692009-06-05 19:22:17 -0700265};
266
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500267static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700270 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700280};
281
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500282static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700293};
294
Eric Anholt273e27c2011-03-30 13:01:10 -0700295/* Ironlake / Sandybridge
296 *
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
299 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800300static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700311};
312
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800313static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800324};
325
326static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800337};
338
Eric Anholt273e27c2011-03-30 13:01:10 -0700339/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800340static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400348 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800351};
352
353static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400361 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800364};
365
Ville Syrjälädc730512013-09-24 21:26:30 +0300366static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300367 /*
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
372 */
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200374 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700375 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300378 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700380};
381
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300382static const intel_limit_t intel_limits_chv = {
383 /*
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
388 */
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396};
397
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300398static void vlv_clock(int refclk, intel_clock_t *clock)
399{
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200402 if (WARN_ON(clock->n == 0 || clock->p == 0))
403 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300406}
407
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300408/**
409 * Returns whether any output on the specified pipe is of the specified type
410 */
Damien Lespiau40935612014-10-29 11:16:59 +0000411bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300412{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300413 struct drm_device *dev = crtc->base.dev;
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300414 struct intel_encoder *encoder;
415
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300417 if (encoder->type == type)
418 return true;
419
420 return false;
421}
422
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200423/**
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427 * encoder->crtc.
428 */
429static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
430{
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
433
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
436 return true;
437
438 return false;
439}
440
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300441static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
Chris Wilson1b894b52010-12-14 20:04:54 +0000442 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800443{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300444 struct drm_device *dev = crtc->base.dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800445 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800446
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100448 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000449 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800450 limit = &intel_limits_ironlake_dual_lvds_100m;
451 else
452 limit = &intel_limits_ironlake_dual_lvds;
453 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000454 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800455 limit = &intel_limits_ironlake_single_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_single_lvds;
458 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200459 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800460 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800461
462 return limit;
463}
464
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300465static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
Ma Ling044c7c42009-03-18 20:13:23 +0800466{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300467 struct drm_device *dev = crtc->base.dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800468 const intel_limit_t *limit;
469
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100471 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700472 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800473 else
Keith Packarde4b36692009-06-05 19:22:17 -0700474 limit = &intel_limits_g4x_single_channel_lvds;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700477 limit = &intel_limits_g4x_hdmi;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700479 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800480 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700481 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800482
483 return limit;
484}
485
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300486static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800487{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300488 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800489 const intel_limit_t *limit;
490
Eric Anholtbad720f2009-10-22 16:11:14 -0700491 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000492 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800493 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800494 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500495 } else if (IS_PINEVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500497 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800498 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500499 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700502 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300503 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100504 } else if (!IS_GEN2(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100506 limit = &intel_limits_i9xx_lvds;
507 else
508 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800509 } else {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700511 limit = &intel_limits_i8xx_lvds;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700513 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200514 else
515 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800516 }
517 return limit;
518}
519
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500520/* m1 is reserved as 0 in Pineview, n is a ring counter */
521static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800522{
Shaohua Li21778322009-02-23 15:19:16 +0800523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800529}
530
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200531static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532{
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534}
535
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200536static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800537{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200538 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800539 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
541 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800544}
545
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300546static void chv_clock(int refclk, intel_clock_t *clock)
547{
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
553 clock->n << 22);
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555}
556
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800557#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800558/**
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
561 */
562
Chris Wilson1b894b52010-12-14 20:04:54 +0000563static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800566{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400570 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400572 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400574 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300575
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
579
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
585 }
586
Jesse Barnes79e53942008-11-07 14:24:08 -0800587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400588 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
591 */
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400593 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800594
595 return true;
596}
597
Ma Lingd4906092009-03-18 20:13:27 +0800598static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300599i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800602{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300603 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800604 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800605 int err = target;
606
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800608 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800612 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100613 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800614 clock.p2 = limit->p2.p2_fast;
615 else
616 clock.p2 = limit->p2.p2_slow;
617 } else {
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
620 else
621 clock.p2 = limit->p2.p2_fast;
622 }
623
Akshay Joshi0206e352011-08-16 15:34:10 -0400624 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800625
Zhao Yakui42158662009-11-20 11:24:18 +0800626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
627 clock.m1++) {
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200630 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800631 break;
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800636 int this_err;
637
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200638 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000639 if (!intel_PLL_is_valid(dev, limit,
640 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800641 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657}
658
Ma Lingd4906092009-03-18 20:13:27 +0800659static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300660pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200663{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300664 struct drm_device *dev = crtc->base.dev;
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200665 intel_clock_t clock;
666 int err = target;
667
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200669 /*
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
673 */
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
676 else
677 clock.p2 = limit->p2.p2_slow;
678 } else {
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
681 else
682 clock.p2 = limit->p2.p2_fast;
683 }
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800698 if (!intel_PLL_is_valid(dev, limit,
699 &clock))
700 continue;
701 if (match_clock &&
702 clock.p != match_clock->p)
703 continue;
704
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
707 *best_clock = clock;
708 err = this_err;
709 }
710 }
711 }
712 }
713 }
714
715 return (err != target);
716}
717
Ma Lingd4906092009-03-18 20:13:27 +0800718static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300719g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800722{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300723 struct drm_device *dev = crtc->base.dev;
Ma Lingd4906092009-03-18 20:13:27 +0800724 intel_clock_t clock;
725 int max_n;
726 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800729 found = false;
730
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100732 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800733 clock.p2 = limit->p2.p2_fast;
734 else
735 clock.p2 = limit->p2.p2_slow;
736 } else {
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
739 else
740 clock.p2 = limit->p2.p2_fast;
741 }
742
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200745 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200747 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
754 int this_err;
755
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200756 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800759 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000760
761 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800762 if (this_err < err_most) {
763 *best_clock = clock;
764 err_most = this_err;
765 max_n = clock.n;
766 found = true;
767 }
768 }
769 }
770 }
771 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800772 return found;
773}
Ma Lingd4906092009-03-18 20:13:27 +0800774
Zhenyu Wang2c072452009-06-05 15:38:42 +0800775static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300776vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700779{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300780 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300781 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300782 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300785 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700786
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300787 target *= 5; /* fast clock */
788
789 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700790
791 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300796 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700797 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300799 unsigned int ppm, diff;
800
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
802 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300803
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300804 vlv_clock(refclk, &clock);
805
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300808 continue;
809
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
812
813 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300814 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300815 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300816 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300817 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300818
Ville Syrjäläc6861222013-09-24 21:26:21 +0300819 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300820 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300821 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300822 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700823 }
824 }
825 }
826 }
827 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700828
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300829 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700830}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700831
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300832static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300833chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
836{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300837 struct drm_device *dev = crtc->base.dev;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300838 intel_clock_t clock;
839 uint64_t m2;
840 int found = false;
841
842 memset(best_clock, 0, sizeof(*best_clock));
843
844 /*
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
848 */
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
851
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856
857 clock.p = clock.p1 * clock.p2;
858
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
861
862 if (m2 > INT_MAX/clock.m1)
863 continue;
864
865 clock.m2 = m2;
866
867 chv_clock(refclk, &clock);
868
869 if (!intel_PLL_is_valid(dev, limit, &clock))
870 continue;
871
872 /* based on hardware requirement, prefer bigger p
873 */
874 if (clock.p > best_clock->p) {
875 *best_clock = clock;
876 found = true;
877 }
878 }
879 }
880
881 return found;
882}
883
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300884bool intel_crtc_active(struct drm_crtc *crtc)
885{
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
890 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100891 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300892 * as Haswell has gained clock readout/fastboot support.
893 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000894 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300895 * properly reconstruct framebuffers.
896 */
Matt Roperf4510a22014-04-01 15:22:40 -0700897 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100898 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300899}
900
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200901enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902 enum pipe pipe)
903{
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906
Daniel Vetter3b117c82013-04-17 20:15:07 +0200907 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200908}
909
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300910static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
911{
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
914 u32 line1, line2;
915 u32 line_mask;
916
917 if (IS_GEN2(dev))
918 line_mask = DSL_LINEMASK_GEN2;
919 else
920 line_mask = DSL_LINEMASK_GEN3;
921
922 line1 = I915_READ(reg) & line_mask;
923 mdelay(5);
924 line2 = I915_READ(reg) & line_mask;
925
926 return line1 == line2;
927}
928
Keith Packardab7ad7f2010-10-03 00:33:06 -0700929/*
930 * intel_wait_for_pipe_off - wait for pipe to turn off
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300931 * @crtc: crtc whose pipe to wait for
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700932 *
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
936 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700937 * On Gen4 and above:
938 * wait for the pipe register state bit to turn off
939 *
940 * Otherwise:
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100943 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700944 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300945static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700946{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300947 struct drm_device *dev = crtc->base.dev;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700948 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700951
Keith Packardab7ad7f2010-10-03 00:33:06 -0700952 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200953 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700954
Keith Packardab7ad7f2010-10-03 00:33:06 -0700955 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
957 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200958 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700959 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700960 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200962 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700963 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800964}
965
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000966/*
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
970 *
971 * Returns true if @port is connected, false otherwise.
972 */
973bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
975{
976 u32 bit;
977
Damien Lespiauc36346e2012-12-13 16:09:03 +0000978 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +0200979 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000980 case PORT_B:
981 bit = SDE_PORTB_HOTPLUG;
982 break;
983 case PORT_C:
984 bit = SDE_PORTC_HOTPLUG;
985 break;
986 case PORT_D:
987 bit = SDE_PORTD_HOTPLUG;
988 break;
989 default:
990 return true;
991 }
992 } else {
Robin Schroereba905b2014-05-18 02:24:50 +0200993 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000994 case PORT_B:
995 bit = SDE_PORTB_HOTPLUG_CPT;
996 break;
997 case PORT_C:
998 bit = SDE_PORTC_HOTPLUG_CPT;
999 break;
1000 case PORT_D:
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1002 break;
1003 default:
1004 return true;
1005 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001006 }
1007
1008 return I915_READ(SDEISR) & bit;
1009}
1010
Jesse Barnesb24e7172011-01-04 15:09:30 -08001011static const char *state_string(bool enabled)
1012{
1013 return enabled ? "on" : "off";
1014}
1015
1016/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001017void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001019{
1020 int reg;
1021 u32 val;
1022 bool cur_state;
1023
1024 reg = DPLL(pipe);
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1030}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001031
Jani Nikula23538ef2013-08-27 15:12:22 +03001032/* XXX: the dsi pll is shared between MIPI DSI ports */
1033static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034{
1035 u32 val;
1036 bool cur_state;
1037
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1041
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1046}
1047#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
Daniel Vetter55607e82013-06-16 21:42:39 +02001050struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001051intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001052{
Daniel Vettere2b78262013-06-07 23:10:03 +02001053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
Daniel Vettera43f6e02013-06-07 23:10:32 +02001055 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001056 return NULL;
1057
Daniel Vettera43f6e02013-06-07 23:10:32 +02001058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001059}
1060
Jesse Barnesb24e7172011-01-04 15:09:30 -08001061/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001062void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1064 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001065{
Jesse Barnes040484a2011-01-03 12:14:26 -08001066 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001067 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001068
Chris Wilson92b27b02012-05-20 18:10:50 +01001069 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001070 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001072
Daniel Vetter53589012013-06-05 13:34:16 +02001073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001074 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001077}
Jesse Barnes040484a2011-01-03 12:14:26 -08001078
1079static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081{
1082 int reg;
1083 u32 val;
1084 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001087
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001091 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101}
1102#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107{
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118}
1119#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001130 return;
1131
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001133 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001134 return;
1135
Jesse Barnes040484a2011-01-03 12:14:26 -08001136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139}
1140
Daniel Vetter55607e82013-06-16 21:42:39 +02001141void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001143{
1144 int reg;
1145 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001146 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001154}
1155
Daniel Vetterb680c372014-09-19 18:27:27 +02001156void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
Jesse Barnesea0760c2011-01-04 15:09:32 -08001158{
Jani Nikulabedd4db2014-08-22 15:04:13 +03001159 struct drm_device *dev = dev_priv->dev;
1160 int pp_reg;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001161 u32 val;
1162 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001163 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001164
Jani Nikulabedd4db2014-08-22 15:04:13 +03001165 if (WARN_ON(HAS_DDI(dev)))
1166 return;
1167
1168 if (HAS_PCH_SPLIT(dev)) {
1169 u32 port_sel;
1170
Jesse Barnesea0760c2011-01-04 15:09:32 -08001171 pp_reg = PCH_PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181 panel_pipe = pipe;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001182 } else {
1183 pp_reg = PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001186 }
1187
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
Jani Nikulaec49ba22014-08-21 15:06:25 +03001190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
Jesse Barnesea0760c2011-01-04 15:09:32 -08001191 locked = false;
1192
Jesse Barnesea0760c2011-01-04 15:09:32 -08001193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001195 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001196}
1197
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001198static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200{
1201 struct drm_device *dev = dev_priv->dev;
1202 bool cur_state;
1203
Paulo Zanonid9d82082014-02-27 16:30:56 -03001204 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001206 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001208
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1212}
1213#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001216void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001218{
1219 int reg;
1220 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001221 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001224
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetter8e636782012-01-22 01:36:48 +01001228 state = true;
1229
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001230 if (!intel_display_power_is_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001241 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001242}
1243
Chris Wilson931872f2012-01-16 23:01:13 +00001244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001246{
1247 int reg;
1248 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001249 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001257}
1258
Chris Wilson931872f2012-01-16 23:01:13 +00001259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
Jesse Barnesb24e7172011-01-04 15:09:30 -08001262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001265 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001266 int reg, i;
1267 u32 val;
1268 int cur_pipe;
1269
Ville Syrjälä653e1022013-06-04 13:49:05 +03001270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001274 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001275 "plane %c assertion failure, should be disabled but not\n",
1276 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001277 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001278 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001279
Jesse Barnesb24e7172011-01-04 15:09:30 -08001280 /* Need to check both planes against the pipe */
Damien Lespiau055e3932014-08-18 13:49:10 +01001281 for_each_pipe(dev_priv, i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001282 reg = DSPCNTR(i);
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001289 }
1290}
1291
Jesse Barnes19332d72013-03-28 09:55:38 -07001292static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe)
1294{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001295 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001296 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001297 u32 val;
1298
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1305 }
1306 } else if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001309 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001310 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001312 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001313 }
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1315 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001316 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001317 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001323 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001326 }
1327}
1328
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001329static void assert_vblank_disabled(struct drm_crtc *crtc)
1330{
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1333}
1334
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001335static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001336{
1337 u32 val;
1338 bool enabled;
1339
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001341
Jesse Barnes92f25842011-01-04 15:09:34 -08001342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346}
1347
Daniel Vetterab9412b2013-05-03 11:49:46 +02001348static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001350{
1351 int reg;
1352 u32 val;
1353 bool enabled;
1354
Daniel Vetterab9412b2013-05-03 11:49:46 +02001355 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001358 WARN(enabled,
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001361}
1362
Keith Packard4e634382011-08-06 10:39:45 -07001363static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001365{
1366 if ((val & DP_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001377 } else {
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379 return false;
1380 }
1381 return true;
1382}
1383
Keith Packard1519b992011-08-06 10:35:34 -07001384static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1386{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001387 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001388 return false;
1389
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001392 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001396 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001398 return false;
1399 }
1400 return true;
1401}
1402
1403static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1405{
1406 if ((val & LVDS_PORT_EN) == 0)
1407 return false;
1408
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411 return false;
1412 } else {
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414 return false;
1415 }
1416 return true;
1417}
1418
1419static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421{
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1423 return false;
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426 return false;
1427 } else {
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429 return false;
1430 }
1431 return true;
1432}
1433
Jesse Barnes291906f2011-02-02 12:28:03 -08001434static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001435 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001436{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001437 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001440 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001441
Daniel Vetter75c5da22012-09-10 21:58:29 +02001442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001444 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001445}
1446
1447static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1449{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001450 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001453 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001454
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001456 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001457 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001458}
1459
1460static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe)
1462{
1463 int reg;
1464 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001465
Keith Packardf0575e92011-07-25 22:12:43 -07001466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001469
1470 reg = PCH_ADPA;
1471 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001473 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001474 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001475
1476 reg = PCH_LVDS;
1477 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001480 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001481
Paulo Zanonie2debe92013-02-18 19:00:27 -03001482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001485}
1486
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001487static void intel_init_dpio(struct drm_device *dev)
1488{
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491 if (!IS_VALLEYVIEW(dev))
1492 return;
1493
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001494 /*
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498 */
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502 } else {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001505}
1506
Ville Syrjäläd288f652014-10-28 13:20:22 +02001507static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001509{
Daniel Vetter426115c2013-07-11 22:13:42 +02001510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
Ville Syrjäläd288f652014-10-28 13:20:22 +02001513 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001514
Daniel Vetter426115c2013-07-11 22:13:42 +02001515 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001516
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001517 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520 /* PLL is protected by panel, make sure we can write it */
Jani Nikula6a9e7362014-08-22 15:06:35 +03001521 if (IS_MOBILE(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001522 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001523
Daniel Vetter426115c2013-07-11 22:13:42 +02001524 I915_WRITE(reg, dpll);
1525 POSTING_READ(reg);
1526 udelay(150);
1527
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
Ville Syrjäläd288f652014-10-28 13:20:22 +02001531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
Daniel Vetter426115c2013-07-11 22:13:42 +02001532 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001533
1534 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001535 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001536 POSTING_READ(reg);
1537 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001538 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001541 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544}
1545
Ville Syrjäläd288f652014-10-28 13:20:22 +02001546static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001548{
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001553 u32 tmp;
1554
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559 mutex_lock(&dev_priv->dpio_lock);
1560
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566 /*
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568 */
1569 udelay(1);
1570
1571 /* Enable PLL */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001573
1574 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001578 /* not sure when this should be written */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001580 POSTING_READ(DPLL_MD(pipe));
1581
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001582 mutex_unlock(&dev_priv->dpio_lock);
1583}
1584
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001585static int intel_num_dvo_pipes(struct drm_device *dev)
1586{
1587 struct intel_crtc *crtc;
1588 int count = 0;
1589
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001593
1594 return count;
1595}
1596
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001597static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001598{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001603
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001604 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001605
1606 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001608
1609 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001612
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615 /*
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1620 */
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001641
1642 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001643 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001646 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001649 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652}
1653
1654/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001655 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001663static void i9xx_disable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001664{
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1668
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677 }
1678
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001682 return;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
Daniel Vetter50b44a42013-06-05 13:34:33 +02001687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001689}
1690
Jesse Barnesf6071162013-10-01 10:41:38 -07001691static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692{
1693 u32 val = 0;
1694
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1697
Imre Deake5cbfbf2014-01-09 17:08:16 +02001698 /*
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1701 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001702 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001706
1707}
1708
1709static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001712 u32 val;
1713
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001716
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001717 /* Set PLL en = 0 */
Ville Syrjäläd17ec4c2014-06-28 02:03:59 +03001718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001719 if (pipe != PIPE_A)
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001723
1724 mutex_lock(&dev_priv->dpio_lock);
1725
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
Ville Syrjälä61407f62014-05-27 16:32:55 +03001731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736 } else {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740 }
1741
Ville Syrjäläd7520482014-04-09 13:28:59 +03001742 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001743}
1744
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001745void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001747{
1748 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001749 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001750
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001751 switch (dport->port) {
1752 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001753 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001754 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001755 break;
1756 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001757 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_D:
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001763 break;
1764 default:
1765 BUG();
1766 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001767
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001770 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001771}
1772
Daniel Vetterb14b1052014-04-24 23:55:13 +02001773static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774{
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001779 if (WARN_ON(pll == NULL))
1780 return;
1781
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001782 WARN_ON(!pll->config.crtc_mask);
Daniel Vetterb14b1052014-04-24 23:55:13 +02001783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785 WARN_ON(pll->on);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788 pll->mode_set(dev_priv, pll);
1789 }
1790}
1791
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001792/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001793 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1796 *
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1799 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001800static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001801{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001805
Daniel Vetter87a875b2013-06-05 13:34:19 +02001806 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001807 return;
1808
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001809 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001810 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001811
Damien Lespiau74dd6922014-07-29 18:06:17 +01001812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
Daniel Vetter46edb022013-06-05 13:34:12 +02001813 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001814 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001815
Daniel Vettercdbd2312013-06-05 13:34:03 +02001816 if (pll->active++) {
1817 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001818 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001819 return;
1820 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001821 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001822
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
Daniel Vetter46edb022013-06-05 13:34:12 +02001825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001826 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001827 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001828}
1829
Damien Lespiauf6daaec2014-08-09 23:00:56 +01001830static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001831{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001835
Jesse Barnes92f25842011-01-04 15:09:34 -08001836 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001837 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001838 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001839 return;
1840
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001841 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001842 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001843
Daniel Vetter46edb022013-06-05 13:34:12 +02001844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001846 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001847
Chris Wilson48da64a2012-05-13 20:16:12 +01001848 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001849 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001850 return;
1851 }
1852
Daniel Vettere9d69442013-06-05 13:34:15 +02001853 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001854 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001855 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001856 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001857
Daniel Vetter46edb022013-06-05 13:34:12 +02001858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001859 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001860 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001861
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001863}
1864
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001865static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001867{
Daniel Vetter23670b322012-11-01 09:15:30 +01001868 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001871 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001872
1873 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03001874 BUG_ON(!HAS_PCH_SPLIT(dev));
Jesse Barnes040484a2011-01-03 12:14:26 -08001875
1876 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001877 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001878 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1883
Daniel Vetter23670b322012-11-01 09:15:30 +01001884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001891 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001892
Daniel Vetterab9412b2013-05-03 11:49:46 +02001893 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001894 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001895 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001896
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1898 /*
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1901 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001904 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001905
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001908 if (HAS_PCH_IBX(dev_priv->dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001910 val |= TRANS_LEGACY_INTERLACED_ILK;
1911 else
1912 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001913 else
1914 val |= TRANS_PROGRESSIVE;
1915
Jesse Barnes040484a2011-01-03 12:14:26 -08001916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001919}
1920
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001921static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001922 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001923{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001924 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001925
1926 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03001927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001928
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001929 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001932
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001936 I915_WRITE(_TRANSA_CHICKEN2, val);
1937
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001938 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001940
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001943 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001944 else
1945 val |= TRANS_PROGRESSIVE;
1946
Daniel Vetterab9412b2013-05-03 11:49:46 +02001947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001949 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001950}
1951
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001952static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001954{
Daniel Vetter23670b322012-11-01 09:15:30 +01001955 struct drm_device *dev = dev_priv->dev;
1956 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001957
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1961
Jesse Barnes291906f2011-02-02 12:28:03 -08001962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1964
Daniel Vetterab9412b2013-05-03 11:49:46 +02001965 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001972
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1979 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001980}
1981
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001982static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001983{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001984 u32 val;
1985
Daniel Vetterab9412b2013-05-03 11:49:46 +02001986 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001987 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001988 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001989 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001991 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001992
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001996 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001997}
1998
1999/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002000 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02002001 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002002 *
Paulo Zanoni03722642014-01-17 13:51:09 -02002003 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002005 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02002006static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002007{
Paulo Zanoni03722642014-01-17 13:51:09 -02002008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002013 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002014 int reg;
2015 u32 val;
2016
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002017 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002018 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002019 assert_sprites_disabled(dev_priv, pipe);
2020
Paulo Zanoni681e5812012-12-06 11:12:38 -02002021 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002022 pch_transcoder = TRANSCODER_A;
2023 else
2024 pch_transcoder = pipe;
2025
Jesse Barnesb24e7172011-01-04 15:09:30 -08002026 /*
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2029 * need the check.
2030 */
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002033 assert_dsi_pll_enabled(dev_priv);
2034 else
2035 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002036 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002037 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002038 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002042 }
2043 /* FIXME: assert CPU port conditions for SNB+ */
2044 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002045
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002046 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002047 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002048 if (val & PIPECONF_ENABLE) {
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
Chris Wilson00d70b12011-03-17 07:18:29 +00002051 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002052 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002053
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002055 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002056}
2057
2058/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002059 * intel_disable_pipe - disable a pipe, asserting requirements
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002060 * @crtc: crtc whose pipes is to be disabled
Jesse Barnesb24e7172011-01-04 15:09:30 -08002061 *
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002065 *
2066 * Will wait until the pipe has shut down before returning.
2067 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002068static void intel_disable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002069{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002073 int reg;
2074 u32 val;
2075
2076 /*
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2079 */
2080 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002081 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002082 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002083
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002084 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002085 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
Ville Syrjälä67adc642014-08-15 01:21:57 +03002089 /*
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2092 */
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096 /* Don't disable pipe or pipe PLLs if needed */
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Ville Syrjälä67adc642014-08-15 01:21:57 +03002099 val &= ~PIPECONF_ENABLE;
2100
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002104}
2105
Keith Packardd74362c2011-07-28 14:47:14 -07002106/*
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2109 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002110void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002112{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002115
2116 I915_WRITE(reg, I915_READ(reg));
2117 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002118}
2119
Jesse Barnesb24e7172011-01-04 15:09:30 -08002120/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002124 *
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002125 * Enable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002126 */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002127static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002129{
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002133
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002136
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002137 if (intel_crtc->primary_enabled)
2138 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002139
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002140 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002141
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2143 crtc->x, crtc->y);
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002144
2145 /*
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2149 */
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002152}
2153
Jesse Barnesb24e7172011-01-04 15:09:30 -08002154/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002155 * intel_disable_primary_hw_plane - disable the primary hardware plane
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002158 *
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002159 * Disable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002160 */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002161static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002163{
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002169
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002170 if (!intel_crtc->primary_enabled)
2171 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002172
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002173 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002174
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002177}
2178
Chris Wilson693db182013-03-05 14:52:39 +00002179static bool need_vtd_wa(struct drm_device *dev)
2180{
2181#ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184#endif
2185 return false;
2186}
2187
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002188static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189{
2190 int tile_height;
2191
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2194}
2195
Chris Wilson127bd2a2010-07-23 23:32:05 +01002196int
Chris Wilson48b956c2010-09-14 12:50:34 +01002197intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002198 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002199 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002200{
Chris Wilsonce453d82011-02-21 14:43:56 +00002201 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002202 u32 alignment;
2203 int ret;
2204
Matt Roperebcdd392014-07-09 16:22:11 -07002205 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2206
Chris Wilson05394f32010-11-08 19:18:58 +00002207 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002208 case I915_TILING_NONE:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002209 if (INTEL_INFO(dev)->gen >= 9)
2210 alignment = 256 * 1024;
2211 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
Chris Wilson534843d2010-07-05 18:01:46 +01002212 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002213 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002214 alignment = 4 * 1024;
2215 else
2216 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002217 break;
2218 case I915_TILING_X:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002219 if (INTEL_INFO(dev)->gen >= 9)
2220 alignment = 256 * 1024;
2221 else {
2222 /* pin() will align the object as required by fence */
2223 alignment = 0;
2224 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002225 break;
2226 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002227 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002228 return -EINVAL;
2229 default:
2230 BUG();
2231 }
2232
Chris Wilson693db182013-03-05 14:52:39 +00002233 /* Note that the w/a also requires 64 PTE of padding following the
2234 * bo. We currently fill all unused PTE with the shadow page and so
2235 * we should always have valid PTE following the scanout preventing
2236 * the VT-d warning.
2237 */
2238 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239 alignment = 256 * 1024;
2240
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002241 /*
2242 * Global gtt pte registers are special registers which actually forward
2243 * writes to a chunk of system memory. Which means that there is no risk
2244 * that the register values disappear as soon as we call
2245 * intel_runtime_pm_put(), so it is correct to wrap only the
2246 * pin/unpin/fence and not more.
2247 */
2248 intel_runtime_pm_get(dev_priv);
2249
Chris Wilsonce453d82011-02-21 14:43:56 +00002250 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002251 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002252 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002253 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002254
2255 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256 * fence, whereas 965+ only requires a fence if using
2257 * framebuffer compression. For simplicity, we always install
2258 * a fence as the cost is not that onerous.
2259 */
Chris Wilson06d98132012-04-17 15:31:24 +01002260 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002261 if (ret)
2262 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002263
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002264 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002265
Chris Wilsonce453d82011-02-21 14:43:56 +00002266 dev_priv->mm.interruptible = true;
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002267 intel_runtime_pm_put(dev_priv);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002268 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002269
2270err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002271 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002272err_interruptible:
2273 dev_priv->mm.interruptible = true;
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002274 intel_runtime_pm_put(dev_priv);
Chris Wilson48b956c2010-09-14 12:50:34 +01002275 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002276}
2277
Chris Wilson1690e1e2011-12-14 13:57:08 +01002278void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2279{
Matt Roperebcdd392014-07-09 16:22:11 -07002280 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2281
Chris Wilson1690e1e2011-12-14 13:57:08 +01002282 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002283 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002284}
2285
Daniel Vetterc2c75132012-07-05 12:17:30 +02002286/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2287 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002288unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2289 unsigned int tiling_mode,
2290 unsigned int cpp,
2291 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002292{
Chris Wilsonbc752862013-02-21 20:04:31 +00002293 if (tiling_mode != I915_TILING_NONE) {
2294 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002295
Chris Wilsonbc752862013-02-21 20:04:31 +00002296 tile_rows = *y / 8;
2297 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002298
Chris Wilsonbc752862013-02-21 20:04:31 +00002299 tiles = *x / (512/cpp);
2300 *x %= 512/cpp;
2301
2302 return tile_rows * pitch * 8 + tiles * 4096;
2303 } else {
2304 unsigned int offset;
2305
2306 offset = *y * pitch + *x * cpp;
2307 *y = 0;
2308 *x = (offset & 4095) / cpp;
2309 return offset & -4096;
2310 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002311}
2312
Jesse Barnes46f297f2014-03-07 08:57:48 -08002313int intel_format_to_fourcc(int format)
2314{
2315 switch (format) {
2316 case DISPPLANE_8BPP:
2317 return DRM_FORMAT_C8;
2318 case DISPPLANE_BGRX555:
2319 return DRM_FORMAT_XRGB1555;
2320 case DISPPLANE_BGRX565:
2321 return DRM_FORMAT_RGB565;
2322 default:
2323 case DISPPLANE_BGRX888:
2324 return DRM_FORMAT_XRGB8888;
2325 case DISPPLANE_RGBX888:
2326 return DRM_FORMAT_XBGR8888;
2327 case DISPPLANE_BGRX101010:
2328 return DRM_FORMAT_XRGB2101010;
2329 case DISPPLANE_RGBX101010:
2330 return DRM_FORMAT_XBGR2101010;
2331 }
2332}
2333
Jesse Barnes484b41d2014-03-07 08:57:55 -08002334static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002335 struct intel_plane_config *plane_config)
2336{
2337 struct drm_device *dev = crtc->base.dev;
2338 struct drm_i915_gem_object *obj = NULL;
2339 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2340 u32 base = plane_config->base;
2341
Chris Wilsonff2652e2014-03-10 08:07:02 +00002342 if (plane_config->size == 0)
2343 return false;
2344
Jesse Barnes46f297f2014-03-07 08:57:48 -08002345 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2346 plane_config->size);
2347 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002348 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002349
2350 if (plane_config->tiled) {
2351 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002352 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002353 }
2354
Dave Airlie66e514c2014-04-03 07:51:54 +10002355 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2356 mode_cmd.width = crtc->base.primary->fb->width;
2357 mode_cmd.height = crtc->base.primary->fb->height;
2358 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002359
2360 mutex_lock(&dev->struct_mutex);
2361
Dave Airlie66e514c2014-04-03 07:51:54 +10002362 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002363 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002364 DRM_DEBUG_KMS("intel fb init failed\n");
2365 goto out_unref_obj;
2366 }
2367
Daniel Vettera071fa02014-06-18 23:28:09 +02002368 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002369 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002370
2371 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2372 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002373
2374out_unref_obj:
2375 drm_gem_object_unreference(&obj->base);
2376 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002377 return false;
2378}
2379
2380static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2381 struct intel_plane_config *plane_config)
2382{
2383 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002384 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002385 struct drm_crtc *c;
2386 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002387 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002388
Dave Airlie66e514c2014-04-03 07:51:54 +10002389 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002390 return;
2391
2392 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2393 return;
2394
Dave Airlie66e514c2014-04-03 07:51:54 +10002395 kfree(intel_crtc->base.primary->fb);
2396 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002397
2398 /*
2399 * Failed to alloc the obj, check to see if we should share
2400 * an fb with another CRTC instead
2401 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002402 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002403 i = to_intel_crtc(c);
2404
2405 if (c == &intel_crtc->base)
2406 continue;
2407
Matt Roper2ff8fde2014-07-08 07:50:07 -07002408 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002409 continue;
2410
Matt Roper2ff8fde2014-07-08 07:50:07 -07002411 obj = intel_fb_obj(c->primary->fb);
2412 if (obj == NULL)
2413 continue;
2414
2415 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002416 if (obj->tiling_mode != I915_TILING_NONE)
2417 dev_priv->preserve_bios_swizzle = true;
2418
Dave Airlie66e514c2014-04-03 07:51:54 +10002419 drm_framebuffer_reference(c->primary->fb);
2420 intel_crtc->base.primary->fb = c->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002421 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002422 break;
2423 }
2424 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002425}
2426
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002427static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2428 struct drm_framebuffer *fb,
2429 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002430{
2431 struct drm_device *dev = crtc->dev;
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002434 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002435 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002436 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002437 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002438 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302439 int pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002440
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002441 if (!intel_crtc->primary_enabled) {
2442 I915_WRITE(reg, 0);
2443 if (INTEL_INFO(dev)->gen >= 4)
2444 I915_WRITE(DSPSURF(plane), 0);
2445 else
2446 I915_WRITE(DSPADDR(plane), 0);
2447 POSTING_READ(reg);
2448 return;
2449 }
2450
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002451 obj = intel_fb_obj(fb);
2452 if (WARN_ON(obj == NULL))
2453 return;
2454
2455 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2456
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002457 dspcntr = DISPPLANE_GAMMA_ENABLE;
2458
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002459 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002460
2461 if (INTEL_INFO(dev)->gen < 4) {
2462 if (intel_crtc->pipe == PIPE_B)
2463 dspcntr |= DISPPLANE_SEL_PIPE_B;
2464
2465 /* pipesrc and dspsize control the size that is scaled from,
2466 * which should always be the user's requested size.
2467 */
2468 I915_WRITE(DSPSIZE(plane),
2469 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2470 (intel_crtc->config.pipe_src_w - 1));
2471 I915_WRITE(DSPPOS(plane), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +03002472 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2473 I915_WRITE(PRIMSIZE(plane),
2474 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2475 (intel_crtc->config.pipe_src_w - 1));
2476 I915_WRITE(PRIMPOS(plane), 0);
2477 I915_WRITE(PRIMCNSTALPHA(plane), 0);
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002478 }
2479
Ville Syrjälä57779d02012-10-31 17:50:14 +02002480 switch (fb->pixel_format) {
2481 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002482 dspcntr |= DISPPLANE_8BPP;
2483 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002484 case DRM_FORMAT_XRGB1555:
2485 case DRM_FORMAT_ARGB1555:
2486 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002487 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002488 case DRM_FORMAT_RGB565:
2489 dspcntr |= DISPPLANE_BGRX565;
2490 break;
2491 case DRM_FORMAT_XRGB8888:
2492 case DRM_FORMAT_ARGB8888:
2493 dspcntr |= DISPPLANE_BGRX888;
2494 break;
2495 case DRM_FORMAT_XBGR8888:
2496 case DRM_FORMAT_ABGR8888:
2497 dspcntr |= DISPPLANE_RGBX888;
2498 break;
2499 case DRM_FORMAT_XRGB2101010:
2500 case DRM_FORMAT_ARGB2101010:
2501 dspcntr |= DISPPLANE_BGRX101010;
2502 break;
2503 case DRM_FORMAT_XBGR2101010:
2504 case DRM_FORMAT_ABGR2101010:
2505 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002506 break;
2507 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002508 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002509 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002510
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002511 if (INTEL_INFO(dev)->gen >= 4 &&
2512 obj->tiling_mode != I915_TILING_NONE)
2513 dspcntr |= DISPPLANE_TILED;
Jesse Barnes81255562010-08-02 12:07:50 -07002514
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002515 if (IS_G4X(dev))
2516 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2517
Ville Syrjäläb98971272014-08-27 16:51:22 +03002518 linear_offset = y * fb->pitches[0] + x * pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002519
Daniel Vetterc2c75132012-07-05 12:17:30 +02002520 if (INTEL_INFO(dev)->gen >= 4) {
2521 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002522 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002523 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002524 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002525 linear_offset -= intel_crtc->dspaddr_offset;
2526 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002527 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002528 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002529
Sonika Jindal48404c12014-08-22 14:06:04 +05302530 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2531 dspcntr |= DISPPLANE_ROTATE_180;
2532
2533 x += (intel_crtc->config.pipe_src_w - 1);
2534 y += (intel_crtc->config.pipe_src_h - 1);
2535
2536 /* Finding the last pixel of the last line of the display
2537 data and adding to linear_offset*/
2538 linear_offset +=
2539 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2540 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2541 }
2542
2543 I915_WRITE(reg, dspcntr);
2544
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002545 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2546 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2547 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002548 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002549 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002550 I915_WRITE(DSPSURF(plane),
2551 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002552 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002553 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002554 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002555 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002556 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002557}
2558
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002559static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2560 struct drm_framebuffer *fb,
2561 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002562{
2563 struct drm_device *dev = crtc->dev;
2564 struct drm_i915_private *dev_priv = dev->dev_private;
2565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002566 struct drm_i915_gem_object *obj;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002567 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002568 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002569 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002570 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302571 int pixel_size;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002572
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002573 if (!intel_crtc->primary_enabled) {
2574 I915_WRITE(reg, 0);
2575 I915_WRITE(DSPSURF(plane), 0);
2576 POSTING_READ(reg);
2577 return;
2578 }
2579
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002580 obj = intel_fb_obj(fb);
2581 if (WARN_ON(obj == NULL))
2582 return;
2583
2584 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2585
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002586 dspcntr = DISPPLANE_GAMMA_ENABLE;
2587
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002588 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002589
2590 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2591 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2592
Ville Syrjälä57779d02012-10-31 17:50:14 +02002593 switch (fb->pixel_format) {
2594 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002595 dspcntr |= DISPPLANE_8BPP;
2596 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002597 case DRM_FORMAT_RGB565:
2598 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002599 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002600 case DRM_FORMAT_XRGB8888:
2601 case DRM_FORMAT_ARGB8888:
2602 dspcntr |= DISPPLANE_BGRX888;
2603 break;
2604 case DRM_FORMAT_XBGR8888:
2605 case DRM_FORMAT_ABGR8888:
2606 dspcntr |= DISPPLANE_RGBX888;
2607 break;
2608 case DRM_FORMAT_XRGB2101010:
2609 case DRM_FORMAT_ARGB2101010:
2610 dspcntr |= DISPPLANE_BGRX101010;
2611 break;
2612 case DRM_FORMAT_XBGR2101010:
2613 case DRM_FORMAT_ABGR2101010:
2614 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002615 break;
2616 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002617 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002618 }
2619
2620 if (obj->tiling_mode != I915_TILING_NONE)
2621 dspcntr |= DISPPLANE_TILED;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002622
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002623 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002624 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002625
Ville Syrjäläb98971272014-08-27 16:51:22 +03002626 linear_offset = y * fb->pitches[0] + x * pixel_size;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002627 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002628 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002629 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002630 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002631 linear_offset -= intel_crtc->dspaddr_offset;
Sonika Jindal48404c12014-08-22 14:06:04 +05302632 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2633 dspcntr |= DISPPLANE_ROTATE_180;
2634
2635 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2636 x += (intel_crtc->config.pipe_src_w - 1);
2637 y += (intel_crtc->config.pipe_src_h - 1);
2638
2639 /* Finding the last pixel of the last line of the display
2640 data and adding to linear_offset*/
2641 linear_offset +=
2642 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2643 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2644 }
2645 }
2646
2647 I915_WRITE(reg, dspcntr);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002648
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002649 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2650 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2651 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002652 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002653 I915_WRITE(DSPSURF(plane),
2654 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002655 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002656 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2657 } else {
2658 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2659 I915_WRITE(DSPLINOFF(plane), linear_offset);
2660 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002661 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002662}
2663
Damien Lespiau70d21f02013-07-03 21:06:04 +01002664static void skylake_update_primary_plane(struct drm_crtc *crtc,
2665 struct drm_framebuffer *fb,
2666 int x, int y)
2667{
2668 struct drm_device *dev = crtc->dev;
2669 struct drm_i915_private *dev_priv = dev->dev_private;
2670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671 struct intel_framebuffer *intel_fb;
2672 struct drm_i915_gem_object *obj;
2673 int pipe = intel_crtc->pipe;
2674 u32 plane_ctl, stride;
2675
2676 if (!intel_crtc->primary_enabled) {
2677 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2678 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2679 POSTING_READ(PLANE_CTL(pipe, 0));
2680 return;
2681 }
2682
2683 plane_ctl = PLANE_CTL_ENABLE |
2684 PLANE_CTL_PIPE_GAMMA_ENABLE |
2685 PLANE_CTL_PIPE_CSC_ENABLE;
2686
2687 switch (fb->pixel_format) {
2688 case DRM_FORMAT_RGB565:
2689 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2690 break;
2691 case DRM_FORMAT_XRGB8888:
2692 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2693 break;
2694 case DRM_FORMAT_XBGR8888:
2695 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2696 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2697 break;
2698 case DRM_FORMAT_XRGB2101010:
2699 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2700 break;
2701 case DRM_FORMAT_XBGR2101010:
2702 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2703 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2704 break;
2705 default:
2706 BUG();
2707 }
2708
2709 intel_fb = to_intel_framebuffer(fb);
2710 obj = intel_fb->obj;
2711
2712 /*
2713 * The stride is either expressed as a multiple of 64 bytes chunks for
2714 * linear buffers or in number of tiles for tiled buffers.
2715 */
2716 switch (obj->tiling_mode) {
2717 case I915_TILING_NONE:
2718 stride = fb->pitches[0] >> 6;
2719 break;
2720 case I915_TILING_X:
2721 plane_ctl |= PLANE_CTL_TILED_X;
2722 stride = fb->pitches[0] >> 9;
2723 break;
2724 default:
2725 BUG();
2726 }
2727
2728 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
Sonika Jindal1447dde2014-10-04 10:53:31 +01002729 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2730 plane_ctl |= PLANE_CTL_ROTATE_180;
Damien Lespiau70d21f02013-07-03 21:06:04 +01002731
2732 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2733
2734 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2735 i915_gem_obj_ggtt_offset(obj),
2736 x, y, fb->width, fb->height,
2737 fb->pitches[0]);
2738
2739 I915_WRITE(PLANE_POS(pipe, 0), 0);
2740 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2741 I915_WRITE(PLANE_SIZE(pipe, 0),
2742 (intel_crtc->config.pipe_src_h - 1) << 16 |
2743 (intel_crtc->config.pipe_src_w - 1));
2744 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2745 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2746
2747 POSTING_READ(PLANE_SURF(pipe, 0));
2748}
2749
Jesse Barnes17638cd2011-06-24 12:19:23 -07002750/* Assume fb object is pinned & idle & fenced and just update base pointers */
2751static int
2752intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2753 int x, int y, enum mode_set_atomic state)
2754{
2755 struct drm_device *dev = crtc->dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002757
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002758 if (dev_priv->display.disable_fbc)
2759 dev_priv->display.disable_fbc(dev);
Jesse Barnes81255562010-08-02 12:07:50 -07002760
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002761 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2762
2763 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002764}
2765
Ville Syrjälä96a02912013-02-18 19:08:49 +02002766void intel_display_handle_reset(struct drm_device *dev)
2767{
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct drm_crtc *crtc;
2770
2771 /*
2772 * Flips in the rings have been nuked by the reset,
2773 * so complete all pending flips so that user space
2774 * will get its events and not get stuck.
2775 *
2776 * Also update the base address of all primary
2777 * planes to the the last fb to make sure we're
2778 * showing the correct fb after a reset.
2779 *
2780 * Need to make two loops over the crtcs so that we
2781 * don't try to grab a crtc mutex before the
2782 * pending_flip_queue really got woken up.
2783 */
2784
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002785 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2787 enum plane plane = intel_crtc->plane;
2788
2789 intel_prepare_page_flip(dev, plane);
2790 intel_finish_page_flip_plane(dev, plane);
2791 }
2792
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002793 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795
Rob Clark51fd3712013-11-19 12:10:12 -05002796 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002797 /*
2798 * FIXME: Once we have proper support for primary planes (and
2799 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002800 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002801 */
Matt Roperf4510a22014-04-01 15:22:40 -07002802 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002803 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002804 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002805 crtc->x,
2806 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05002807 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002808 }
2809}
2810
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002811static int
Chris Wilson14667a42012-04-03 17:58:35 +01002812intel_finish_fb(struct drm_framebuffer *old_fb)
2813{
Matt Roper2ff8fde2014-07-08 07:50:07 -07002814 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
Chris Wilson14667a42012-04-03 17:58:35 +01002815 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2816 bool was_interruptible = dev_priv->mm.interruptible;
2817 int ret;
2818
Chris Wilson14667a42012-04-03 17:58:35 +01002819 /* Big Hammer, we also need to ensure that any pending
2820 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2821 * current scanout is retired before unpinning the old
2822 * framebuffer.
2823 *
2824 * This should only fail upon a hung GPU, in which case we
2825 * can safely continue.
2826 */
2827 dev_priv->mm.interruptible = false;
2828 ret = i915_gem_object_finish_gpu(obj);
2829 dev_priv->mm.interruptible = was_interruptible;
2830
2831 return ret;
2832}
2833
Chris Wilson7d5e3792014-03-04 13:15:08 +00002834static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2835{
2836 struct drm_device *dev = crtc->dev;
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002839 bool pending;
2840
2841 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843 return false;
2844
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02002845 spin_lock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002846 pending = to_intel_crtc(crtc)->unpin_work != NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02002847 spin_unlock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002848
2849 return pending;
2850}
2851
Gustavo Padovane30e8f72014-09-10 12:04:17 -03002852static void intel_update_pipe_size(struct intel_crtc *crtc)
2853{
2854 struct drm_device *dev = crtc->base.dev;
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856 const struct drm_display_mode *adjusted_mode;
2857
2858 if (!i915.fastboot)
2859 return;
2860
2861 /*
2862 * Update pipe size and adjust fitter if needed: the reason for this is
2863 * that in compute_mode_changes we check the native mode (not the pfit
2864 * mode) to see if we can flip rather than do a full mode set. In the
2865 * fastboot case, we'll flip, but if we don't update the pipesrc and
2866 * pfit state, we'll end up with a big fb scanned out into the wrong
2867 * sized surface.
2868 *
2869 * To fix this properly, we need to hoist the checks up into
2870 * compute_mode_changes (or above), check the actual pfit state and
2871 * whether the platform allows pfit disable with pipe active, and only
2872 * then update the pipesrc and pfit state, even on the flip path.
2873 */
2874
2875 adjusted_mode = &crtc->config.adjusted_mode;
2876
2877 I915_WRITE(PIPESRC(crtc->pipe),
2878 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2879 (adjusted_mode->crtc_vdisplay - 1));
2880 if (!crtc->config.pch_pfit.enabled &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002881 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2882 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Gustavo Padovane30e8f72014-09-10 12:04:17 -03002883 I915_WRITE(PF_CTL(crtc->pipe), 0);
2884 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2885 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2886 }
2887 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2888 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2889}
2890
Chris Wilson14667a42012-04-03 17:58:35 +01002891static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002892intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002893 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002894{
2895 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002896 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02002898 enum pipe pipe = intel_crtc->pipe;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002899 struct drm_framebuffer *old_fb = crtc->primary->fb;
2900 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2901 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002902 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002903
Chris Wilson7d5e3792014-03-04 13:15:08 +00002904 if (intel_crtc_has_pending_flip(crtc)) {
2905 DRM_ERROR("pipe is still busy with an old pageflip\n");
2906 return -EBUSY;
2907 }
2908
Jesse Barnes79e53942008-11-07 14:24:08 -08002909 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002910 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002911 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002912 return 0;
2913 }
2914
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002915 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002916 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2917 plane_name(intel_crtc->plane),
2918 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002919 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002920 }
2921
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002922 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02002923 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2924 if (ret == 0)
Matt Roper91565c82014-06-24 17:05:02 -07002925 i915_gem_track_fb(old_obj, obj,
Daniel Vettera071fa02014-06-18 23:28:09 +02002926 INTEL_FRONTBUFFER_PRIMARY(pipe));
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002927 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002928 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002929 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002930 return ret;
2931 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002932
Gustavo Padovane30e8f72014-09-10 12:04:17 -03002933 intel_update_pipe_size(intel_crtc);
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002934
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002935 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002936
Daniel Vetterf99d7062014-06-19 16:01:59 +02002937 if (intel_crtc->active)
2938 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2939
Matt Roperf4510a22014-04-01 15:22:40 -07002940 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002941 crtc->x = x;
2942 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002943
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002944 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002945 if (intel_crtc->active && old_fb != fb)
2946 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002947 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002948 intel_unpin_fb_obj(old_obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002949 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002950 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002951
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002952 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002953 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002954 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002955
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002956 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002957}
2958
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002959static void intel_fdi_normal_train(struct drm_crtc *crtc)
2960{
2961 struct drm_device *dev = crtc->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964 int pipe = intel_crtc->pipe;
2965 u32 reg, temp;
2966
2967 /* enable normal train */
2968 reg = FDI_TX_CTL(pipe);
2969 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002970 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002971 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2972 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002973 } else {
2974 temp &= ~FDI_LINK_TRAIN_NONE;
2975 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002976 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002977 I915_WRITE(reg, temp);
2978
2979 reg = FDI_RX_CTL(pipe);
2980 temp = I915_READ(reg);
2981 if (HAS_PCH_CPT(dev)) {
2982 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2983 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2984 } else {
2985 temp &= ~FDI_LINK_TRAIN_NONE;
2986 temp |= FDI_LINK_TRAIN_NONE;
2987 }
2988 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2989
2990 /* wait one idle pattern time */
2991 POSTING_READ(reg);
2992 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002993
2994 /* IVB wants error correction enabled */
2995 if (IS_IVYBRIDGE(dev))
2996 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2997 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002998}
2999
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003000static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01003001{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003002 return crtc->base.enabled && crtc->active &&
3003 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01003004}
3005
Daniel Vetter01a415f2012-10-27 15:58:40 +02003006static void ivb_modeset_global_resources(struct drm_device *dev)
3007{
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009 struct intel_crtc *pipe_B_crtc =
3010 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3011 struct intel_crtc *pipe_C_crtc =
3012 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3013 uint32_t temp;
3014
Daniel Vetter1e833f42013-02-19 22:31:57 +01003015 /*
3016 * When everything is off disable fdi C so that we could enable fdi B
3017 * with all lanes. Note that we don't care about enabled pipes without
3018 * an enabled pch encoder.
3019 */
3020 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3021 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02003022 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3024
3025 temp = I915_READ(SOUTH_CHICKEN1);
3026 temp &= ~FDI_BC_BIFURCATION_SELECT;
3027 DRM_DEBUG_KMS("disabling fdi C rx\n");
3028 I915_WRITE(SOUTH_CHICKEN1, temp);
3029 }
3030}
3031
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003032/* The FDI link training functions for ILK/Ibexpeak. */
3033static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003039 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003040
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03003041 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003042 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003043
Adam Jacksone1a44742010-06-25 15:32:14 -04003044 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3045 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003046 reg = FDI_RX_IMR(pipe);
3047 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003048 temp &= ~FDI_RX_SYMBOL_LOCK;
3049 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003050 I915_WRITE(reg, temp);
3051 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003052 udelay(150);
3053
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003054 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003055 reg = FDI_TX_CTL(pipe);
3056 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003057 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003059 temp &= ~FDI_LINK_TRAIN_NONE;
3060 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003061 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003062
Chris Wilson5eddb702010-09-11 13:48:45 +01003063 reg = FDI_RX_CTL(pipe);
3064 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003065 temp &= ~FDI_LINK_TRAIN_NONE;
3066 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003067 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3068
3069 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003070 udelay(150);
3071
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003072 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01003073 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3075 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003076
Chris Wilson5eddb702010-09-11 13:48:45 +01003077 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003078 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003079 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003080 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082 if ((temp & FDI_RX_BIT_LOCK)) {
3083 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003084 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003085 break;
3086 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003087 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003088 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003089 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003090
3091 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003092 reg = FDI_TX_CTL(pipe);
3093 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003094 temp &= ~FDI_LINK_TRAIN_NONE;
3095 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003096 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003097
Chris Wilson5eddb702010-09-11 13:48:45 +01003098 reg = FDI_RX_CTL(pipe);
3099 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003100 temp &= ~FDI_LINK_TRAIN_NONE;
3101 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003102 I915_WRITE(reg, temp);
3103
3104 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003105 udelay(150);
3106
Chris Wilson5eddb702010-09-11 13:48:45 +01003107 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003108 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003109 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003110 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3111
3112 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003113 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003114 DRM_DEBUG_KMS("FDI train 2 done.\n");
3115 break;
3116 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003117 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003118 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003119 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003120
3121 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07003122
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003123}
3124
Akshay Joshi0206e352011-08-16 15:34:10 -04003125static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003126 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3127 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3128 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3129 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3130};
3131
3132/* The FDI link training functions for SNB/Cougarpoint. */
3133static void gen6_fdi_link_train(struct drm_crtc *crtc)
3134{
3135 struct drm_device *dev = crtc->dev;
3136 struct drm_i915_private *dev_priv = dev->dev_private;
3137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3138 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05003139 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003140
Adam Jacksone1a44742010-06-25 15:32:14 -04003141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3142 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003143 reg = FDI_RX_IMR(pipe);
3144 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003145 temp &= ~FDI_RX_SYMBOL_LOCK;
3146 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003147 I915_WRITE(reg, temp);
3148
3149 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003150 udelay(150);
3151
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003152 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003153 reg = FDI_TX_CTL(pipe);
3154 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003155 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3156 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003157 temp &= ~FDI_LINK_TRAIN_NONE;
3158 temp |= FDI_LINK_TRAIN_PATTERN_1;
3159 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3160 /* SNB-B */
3161 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01003162 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003163
Daniel Vetterd74cf322012-10-26 10:58:13 +02003164 I915_WRITE(FDI_RX_MISC(pipe),
3165 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3166
Chris Wilson5eddb702010-09-11 13:48:45 +01003167 reg = FDI_RX_CTL(pipe);
3168 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003169 if (HAS_PCH_CPT(dev)) {
3170 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3171 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3172 } else {
3173 temp &= ~FDI_LINK_TRAIN_NONE;
3174 temp |= FDI_LINK_TRAIN_PATTERN_1;
3175 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003176 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3177
3178 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003179 udelay(150);
3180
Akshay Joshi0206e352011-08-16 15:34:10 -04003181 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003182 reg = FDI_TX_CTL(pipe);
3183 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003184 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3185 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003186 I915_WRITE(reg, temp);
3187
3188 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003189 udelay(500);
3190
Sean Paulfa37d392012-03-02 12:53:39 -05003191 for (retry = 0; retry < 5; retry++) {
3192 reg = FDI_RX_IIR(pipe);
3193 temp = I915_READ(reg);
3194 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3195 if (temp & FDI_RX_BIT_LOCK) {
3196 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3197 DRM_DEBUG_KMS("FDI train 1 done.\n");
3198 break;
3199 }
3200 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003201 }
Sean Paulfa37d392012-03-02 12:53:39 -05003202 if (retry < 5)
3203 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003204 }
3205 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003206 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003207
3208 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003209 reg = FDI_TX_CTL(pipe);
3210 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003211 temp &= ~FDI_LINK_TRAIN_NONE;
3212 temp |= FDI_LINK_TRAIN_PATTERN_2;
3213 if (IS_GEN6(dev)) {
3214 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3215 /* SNB-B */
3216 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3217 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003218 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003219
Chris Wilson5eddb702010-09-11 13:48:45 +01003220 reg = FDI_RX_CTL(pipe);
3221 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003222 if (HAS_PCH_CPT(dev)) {
3223 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3224 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3225 } else {
3226 temp &= ~FDI_LINK_TRAIN_NONE;
3227 temp |= FDI_LINK_TRAIN_PATTERN_2;
3228 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003229 I915_WRITE(reg, temp);
3230
3231 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003232 udelay(150);
3233
Akshay Joshi0206e352011-08-16 15:34:10 -04003234 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003235 reg = FDI_TX_CTL(pipe);
3236 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003237 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3238 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003239 I915_WRITE(reg, temp);
3240
3241 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003242 udelay(500);
3243
Sean Paulfa37d392012-03-02 12:53:39 -05003244 for (retry = 0; retry < 5; retry++) {
3245 reg = FDI_RX_IIR(pipe);
3246 temp = I915_READ(reg);
3247 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248 if (temp & FDI_RX_SYMBOL_LOCK) {
3249 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3250 DRM_DEBUG_KMS("FDI train 2 done.\n");
3251 break;
3252 }
3253 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003254 }
Sean Paulfa37d392012-03-02 12:53:39 -05003255 if (retry < 5)
3256 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003257 }
3258 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003259 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003260
3261 DRM_DEBUG_KMS("FDI train done.\n");
3262}
3263
Jesse Barnes357555c2011-04-28 15:09:55 -07003264/* Manual link training for Ivy Bridge A0 parts */
3265static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3266{
3267 struct drm_device *dev = crtc->dev;
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003271 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003272
3273 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3274 for train result */
3275 reg = FDI_RX_IMR(pipe);
3276 temp = I915_READ(reg);
3277 temp &= ~FDI_RX_SYMBOL_LOCK;
3278 temp &= ~FDI_RX_BIT_LOCK;
3279 I915_WRITE(reg, temp);
3280
3281 POSTING_READ(reg);
3282 udelay(150);
3283
Daniel Vetter01a415f2012-10-27 15:58:40 +02003284 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3285 I915_READ(FDI_RX_IIR(pipe)));
3286
Jesse Barnes139ccd32013-08-19 11:04:55 -07003287 /* Try each vswing and preemphasis setting twice before moving on */
3288 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3289 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003292 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3293 temp &= ~FDI_TX_ENABLE;
3294 I915_WRITE(reg, temp);
3295
3296 reg = FDI_RX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 temp &= ~FDI_LINK_TRAIN_AUTO;
3299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300 temp &= ~FDI_RX_ENABLE;
3301 I915_WRITE(reg, temp);
3302
3303 /* enable CPU FDI TX and PCH FDI RX */
3304 reg = FDI_TX_CTL(pipe);
3305 temp = I915_READ(reg);
3306 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3308 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003309 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003310 temp |= snb_b_fdi_train_param[j/2];
3311 temp |= FDI_COMPOSITE_SYNC;
3312 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3313
3314 I915_WRITE(FDI_RX_MISC(pipe),
3315 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3316
3317 reg = FDI_RX_CTL(pipe);
3318 temp = I915_READ(reg);
3319 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3320 temp |= FDI_COMPOSITE_SYNC;
3321 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3322
3323 POSTING_READ(reg);
3324 udelay(1); /* should be 0.5us */
3325
3326 for (i = 0; i < 4; i++) {
3327 reg = FDI_RX_IIR(pipe);
3328 temp = I915_READ(reg);
3329 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3330
3331 if (temp & FDI_RX_BIT_LOCK ||
3332 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3333 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3335 i);
3336 break;
3337 }
3338 udelay(1); /* should be 0.5us */
3339 }
3340 if (i == 4) {
3341 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3342 continue;
3343 }
3344
3345 /* Train 2 */
3346 reg = FDI_TX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3350 I915_WRITE(reg, temp);
3351
3352 reg = FDI_RX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3355 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003356 I915_WRITE(reg, temp);
3357
3358 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003359 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003360
Jesse Barnes139ccd32013-08-19 11:04:55 -07003361 for (i = 0; i < 4; i++) {
3362 reg = FDI_RX_IIR(pipe);
3363 temp = I915_READ(reg);
3364 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003365
Jesse Barnes139ccd32013-08-19 11:04:55 -07003366 if (temp & FDI_RX_SYMBOL_LOCK ||
3367 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3369 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3370 i);
3371 goto train_done;
3372 }
3373 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003374 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003375 if (i == 4)
3376 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003377 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003378
Jesse Barnes139ccd32013-08-19 11:04:55 -07003379train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003380 DRM_DEBUG_KMS("FDI train done.\n");
3381}
3382
Daniel Vetter88cefb62012-08-12 19:27:14 +02003383static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003384{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003385 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003386 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003387 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003388 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003389
Jesse Barnesc64e3112010-09-10 11:27:03 -07003390
Jesse Barnes0e23b992010-09-10 11:10:00 -07003391 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003392 reg = FDI_RX_CTL(pipe);
3393 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003394 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3395 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003396 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003397 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3398
3399 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003400 udelay(200);
3401
3402 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003403 temp = I915_READ(reg);
3404 I915_WRITE(reg, temp | FDI_PCDCLK);
3405
3406 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003407 udelay(200);
3408
Paulo Zanoni20749732012-11-23 15:30:38 -02003409 /* Enable CPU FDI TX PLL, always on for Ironlake */
3410 reg = FDI_TX_CTL(pipe);
3411 temp = I915_READ(reg);
3412 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3413 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003414
Paulo Zanoni20749732012-11-23 15:30:38 -02003415 POSTING_READ(reg);
3416 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003417 }
3418}
3419
Daniel Vetter88cefb62012-08-12 19:27:14 +02003420static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3421{
3422 struct drm_device *dev = intel_crtc->base.dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 int pipe = intel_crtc->pipe;
3425 u32 reg, temp;
3426
3427 /* Switch from PCDclk to Rawclk */
3428 reg = FDI_RX_CTL(pipe);
3429 temp = I915_READ(reg);
3430 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3431
3432 /* Disable CPU FDI TX PLL */
3433 reg = FDI_TX_CTL(pipe);
3434 temp = I915_READ(reg);
3435 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3436
3437 POSTING_READ(reg);
3438 udelay(100);
3439
3440 reg = FDI_RX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3443
3444 /* Wait for the clocks to turn off. */
3445 POSTING_READ(reg);
3446 udelay(100);
3447}
3448
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003449static void ironlake_fdi_disable(struct drm_crtc *crtc)
3450{
3451 struct drm_device *dev = crtc->dev;
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454 int pipe = intel_crtc->pipe;
3455 u32 reg, temp;
3456
3457 /* disable CPU FDI tx and PCH FDI rx */
3458 reg = FDI_TX_CTL(pipe);
3459 temp = I915_READ(reg);
3460 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3461 POSTING_READ(reg);
3462
3463 reg = FDI_RX_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003466 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003467 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3468
3469 POSTING_READ(reg);
3470 udelay(100);
3471
3472 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003473 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003474 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003475
3476 /* still set train pattern 1 */
3477 reg = FDI_TX_CTL(pipe);
3478 temp = I915_READ(reg);
3479 temp &= ~FDI_LINK_TRAIN_NONE;
3480 temp |= FDI_LINK_TRAIN_PATTERN_1;
3481 I915_WRITE(reg, temp);
3482
3483 reg = FDI_RX_CTL(pipe);
3484 temp = I915_READ(reg);
3485 if (HAS_PCH_CPT(dev)) {
3486 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3487 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3488 } else {
3489 temp &= ~FDI_LINK_TRAIN_NONE;
3490 temp |= FDI_LINK_TRAIN_PATTERN_1;
3491 }
3492 /* BPC in FDI rx is consistent with that in PIPECONF */
3493 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003494 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003495 I915_WRITE(reg, temp);
3496
3497 POSTING_READ(reg);
3498 udelay(100);
3499}
3500
Chris Wilson5dce5b932014-01-20 10:17:36 +00003501bool intel_has_pending_fb_unpin(struct drm_device *dev)
3502{
3503 struct intel_crtc *crtc;
3504
3505 /* Note that we don't need to be called with mode_config.lock here
3506 * as our list of CRTC objects is static for the lifetime of the
3507 * device and so cannot disappear as we iterate. Similarly, we can
3508 * happily treat the predicates as racy, atomic checks as userspace
3509 * cannot claim and pin a new fb without at least acquring the
3510 * struct_mutex and so serialising with us.
3511 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003512 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003513 if (atomic_read(&crtc->unpin_work_count) == 0)
3514 continue;
3515
3516 if (crtc->unpin_work)
3517 intel_wait_for_vblank(dev, crtc->pipe);
3518
3519 return true;
3520 }
3521
3522 return false;
3523}
3524
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003525static void page_flip_completed(struct intel_crtc *intel_crtc)
3526{
3527 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3528 struct intel_unpin_work *work = intel_crtc->unpin_work;
3529
3530 /* ensure that the unpin work is consistent wrt ->pending. */
3531 smp_rmb();
3532 intel_crtc->unpin_work = NULL;
3533
3534 if (work->event)
3535 drm_send_vblank_event(intel_crtc->base.dev,
3536 intel_crtc->pipe,
3537 work->event);
3538
3539 drm_crtc_vblank_put(&intel_crtc->base);
3540
3541 wake_up_all(&dev_priv->pending_flip_queue);
3542 queue_work(dev_priv->wq, &work->work);
3543
3544 trace_i915_flip_complete(intel_crtc->plane,
3545 work->pending_flip_obj);
3546}
3547
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003548void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003549{
Chris Wilson0f911282012-04-17 10:05:38 +01003550 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003551 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003552
Daniel Vetter2c10d572012-12-20 21:24:07 +01003553 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
Chris Wilson9c787942014-09-05 07:13:25 +01003554 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3555 !intel_crtc_has_pending_flip(crtc),
3556 60*HZ) == 0)) {
3557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter2c10d572012-12-20 21:24:07 +01003558
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003559 spin_lock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003560 if (intel_crtc->unpin_work) {
3561 WARN_ONCE(1, "Removing stuck page flip\n");
3562 page_flip_completed(intel_crtc);
3563 }
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003564 spin_unlock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003565 }
Chris Wilson5bb61642012-09-27 21:25:58 +01003566
Chris Wilson975d5682014-08-20 13:13:34 +01003567 if (crtc->primary->fb) {
3568 mutex_lock(&dev->struct_mutex);
3569 intel_finish_fb(crtc->primary->fb);
3570 mutex_unlock(&dev->struct_mutex);
3571 }
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003572}
3573
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003574/* Program iCLKIP clock to the desired frequency */
3575static void lpt_program_iclkip(struct drm_crtc *crtc)
3576{
3577 struct drm_device *dev = crtc->dev;
3578 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003579 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003580 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3581 u32 temp;
3582
Daniel Vetter09153002012-12-12 14:06:44 +01003583 mutex_lock(&dev_priv->dpio_lock);
3584
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003585 /* It is necessary to ungate the pixclk gate prior to programming
3586 * the divisors, and gate it back when it is done.
3587 */
3588 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3589
3590 /* Disable SSCCTL */
3591 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003592 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3593 SBI_SSCCTL_DISABLE,
3594 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003595
3596 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003597 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003598 auxdiv = 1;
3599 divsel = 0x41;
3600 phaseinc = 0x20;
3601 } else {
3602 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003603 * but the adjusted_mode->crtc_clock in in KHz. To get the
3604 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003605 * convert the virtual clock precision to KHz here for higher
3606 * precision.
3607 */
3608 u32 iclk_virtual_root_freq = 172800 * 1000;
3609 u32 iclk_pi_range = 64;
3610 u32 desired_divisor, msb_divisor_value, pi_value;
3611
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003612 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003613 msb_divisor_value = desired_divisor / iclk_pi_range;
3614 pi_value = desired_divisor % iclk_pi_range;
3615
3616 auxdiv = 0;
3617 divsel = msb_divisor_value - 2;
3618 phaseinc = pi_value;
3619 }
3620
3621 /* This should not happen with any sane values */
3622 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3623 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3624 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3625 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3626
3627 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003628 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003629 auxdiv,
3630 divsel,
3631 phasedir,
3632 phaseinc);
3633
3634 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003635 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003636 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3637 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3638 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3639 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3640 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3641 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003642 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003643
3644 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003645 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003646 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3647 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003648 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003649
3650 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003651 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003652 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003653 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003654
3655 /* Wait for initialization time */
3656 udelay(24);
3657
3658 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003659
3660 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003661}
3662
Daniel Vetter275f01b22013-05-03 11:49:47 +02003663static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3664 enum pipe pch_transcoder)
3665{
3666 struct drm_device *dev = crtc->base.dev;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3669
3670 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3671 I915_READ(HTOTAL(cpu_transcoder)));
3672 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3673 I915_READ(HBLANK(cpu_transcoder)));
3674 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3675 I915_READ(HSYNC(cpu_transcoder)));
3676
3677 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3678 I915_READ(VTOTAL(cpu_transcoder)));
3679 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3680 I915_READ(VBLANK(cpu_transcoder)));
3681 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3682 I915_READ(VSYNC(cpu_transcoder)));
3683 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3684 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3685}
3686
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003687static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3688{
3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690 uint32_t temp;
3691
3692 temp = I915_READ(SOUTH_CHICKEN1);
3693 if (temp & FDI_BC_BIFURCATION_SELECT)
3694 return;
3695
3696 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3698
3699 temp |= FDI_BC_BIFURCATION_SELECT;
3700 DRM_DEBUG_KMS("enabling fdi C rx\n");
3701 I915_WRITE(SOUTH_CHICKEN1, temp);
3702 POSTING_READ(SOUTH_CHICKEN1);
3703}
3704
3705static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3706{
3707 struct drm_device *dev = intel_crtc->base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710 switch (intel_crtc->pipe) {
3711 case PIPE_A:
3712 break;
3713 case PIPE_B:
3714 if (intel_crtc->config.fdi_lanes > 2)
3715 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3716 else
3717 cpt_enable_fdi_bc_bifurcation(dev);
3718
3719 break;
3720 case PIPE_C:
3721 cpt_enable_fdi_bc_bifurcation(dev);
3722
3723 break;
3724 default:
3725 BUG();
3726 }
3727}
3728
Jesse Barnesf67a5592011-01-05 10:31:48 -08003729/*
3730 * Enable PCH resources required for PCH ports:
3731 * - PCH PLLs
3732 * - FDI training & RX/TX
3733 * - update transcoder timings
3734 * - DP transcoding bits
3735 * - transcoder
3736 */
3737static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003738{
3739 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003743 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003744
Daniel Vetterab9412b2013-05-03 11:49:46 +02003745 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003746
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003747 if (IS_IVYBRIDGE(dev))
3748 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3749
Daniel Vettercd986ab2012-10-26 10:58:12 +02003750 /* Write the TU size bits before fdi link training, so that error
3751 * detection works. */
3752 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3753 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3754
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003755 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003756 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003757
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003758 /* We need to program the right clock selection before writing the pixel
3759 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003760 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003761 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003762
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003763 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003764 temp |= TRANS_DPLL_ENABLE(pipe);
3765 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003766 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003767 temp |= sel;
3768 else
3769 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003770 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003771 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003772
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003773 /* XXX: pch pll's can be enabled any time before we enable the PCH
3774 * transcoder, and we actually should do this to not upset any PCH
3775 * transcoder that already use the clock when we share it.
3776 *
3777 * Note that enable_shared_dpll tries to do the right thing, but
3778 * get_shared_dpll unconditionally resets the pll - we need that to have
3779 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003780 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003781
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003782 /* set transcoder timing, panel must allow it */
3783 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003784 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003785
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003786 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003787
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003788 /* For PCH DP, enable TRANS_DP_CTL */
Daniel Vetter0a888182014-11-03 14:37:38 +01003789 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003790 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003791 reg = TRANS_DP_CTL(pipe);
3792 temp = I915_READ(reg);
3793 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003794 TRANS_DP_SYNC_MASK |
3795 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003796 temp |= (TRANS_DP_OUTPUT_ENABLE |
3797 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003798 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003799
3800 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003801 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003802 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003803 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003804
3805 switch (intel_trans_dp_port_sel(crtc)) {
3806 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003807 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003808 break;
3809 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003810 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003811 break;
3812 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003813 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003814 break;
3815 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003816 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003817 }
3818
Chris Wilson5eddb702010-09-11 13:48:45 +01003819 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003820 }
3821
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003822 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003823}
3824
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003825static void lpt_pch_enable(struct drm_crtc *crtc)
3826{
3827 struct drm_device *dev = crtc->dev;
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003830 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003831
Daniel Vetterab9412b2013-05-03 11:49:46 +02003832 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003833
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003834 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003835
Paulo Zanoni0540e482012-10-31 18:12:40 -02003836 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003837 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003838
Paulo Zanoni937bb612012-10-31 18:12:47 -02003839 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003840}
3841
Daniel Vetter716c2e52014-06-25 22:02:02 +03003842void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003843{
Daniel Vettere2b78262013-06-07 23:10:03 +02003844 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003845
3846 if (pll == NULL)
3847 return;
3848
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02003849 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02003850 WARN(1, "bad %s crtc mask\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003851 return;
3852 }
3853
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02003854 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3855 if (pll->config.crtc_mask == 0) {
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003856 WARN_ON(pll->on);
3857 WARN_ON(pll->active);
3858 }
3859
Daniel Vettera43f6e02013-06-07 23:10:32 +02003860 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003861}
3862
Daniel Vetter716c2e52014-06-25 22:02:02 +03003863struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003864{
Daniel Vettere2b78262013-06-07 23:10:03 +02003865 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003866 struct intel_shared_dpll *pll;
Daniel Vettere2b78262013-06-07 23:10:03 +02003867 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003868
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003869 if (HAS_PCH_IBX(dev_priv->dev)) {
3870 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003871 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003872 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003873
Daniel Vetter46edb022013-06-05 13:34:12 +02003874 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3875 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003876
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003877 WARN_ON(pll->new_config->crtc_mask);
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003878
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003879 goto found;
3880 }
3881
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003882 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3883 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003884
3885 /* Only want to check enabled timings first */
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003886 if (pll->new_config->crtc_mask == 0)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003887 continue;
3888
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003889 if (memcmp(&crtc->new_config->dpll_hw_state,
3890 &pll->new_config->hw_state,
3891 sizeof(pll->new_config->hw_state)) == 0) {
3892 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02003893 crtc->base.base.id, pll->name,
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003894 pll->new_config->crtc_mask,
3895 pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003896 goto found;
3897 }
3898 }
3899
3900 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003901 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3902 pll = &dev_priv->shared_dplls[i];
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003903 if (pll->new_config->crtc_mask == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003904 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3905 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003906 goto found;
3907 }
3908 }
3909
3910 return NULL;
3911
3912found:
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003913 if (pll->new_config->crtc_mask == 0)
3914 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003915
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003916 crtc->new_config->shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003917 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3918 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003919
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003920 pll->new_config->crtc_mask |= 1 << crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003921
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003922 return pll;
3923}
3924
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003925/**
3926 * intel_shared_dpll_start_config - start a new PLL staged config
3927 * @dev_priv: DRM device
3928 * @clear_pipes: mask of pipes that will have their PLLs freed
3929 *
3930 * Starts a new PLL staged config, copying the current config but
3931 * releasing the references of pipes specified in clear_pipes.
3932 */
3933static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3934 unsigned clear_pipes)
3935{
3936 struct intel_shared_dpll *pll;
3937 enum intel_dpll_id i;
3938
3939 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3940 pll = &dev_priv->shared_dplls[i];
3941
3942 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3943 GFP_KERNEL);
3944 if (!pll->new_config)
3945 goto cleanup;
3946
3947 pll->new_config->crtc_mask &= ~clear_pipes;
3948 }
3949
3950 return 0;
3951
3952cleanup:
3953 while (--i >= 0) {
3954 pll = &dev_priv->shared_dplls[i];
3955 pll->new_config = NULL;
3956 }
3957
3958 return -ENOMEM;
3959}
3960
3961static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3962{
3963 struct intel_shared_dpll *pll;
3964 enum intel_dpll_id i;
3965
3966 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3967 pll = &dev_priv->shared_dplls[i];
3968
3969 WARN_ON(pll->new_config == &pll->config);
3970
3971 pll->config = *pll->new_config;
3972 kfree(pll->new_config);
3973 pll->new_config = NULL;
3974 }
3975}
3976
3977static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3978{
3979 struct intel_shared_dpll *pll;
3980 enum intel_dpll_id i;
3981
3982 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3983 pll = &dev_priv->shared_dplls[i];
3984
3985 WARN_ON(pll->new_config == &pll->config);
3986
3987 kfree(pll->new_config);
3988 pll->new_config = NULL;
3989 }
3990}
3991
Daniel Vettera1520312013-05-03 11:49:50 +02003992static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003993{
3994 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003995 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003996 u32 temp;
3997
3998 temp = I915_READ(dslreg);
3999 udelay(500);
4000 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07004001 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03004002 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07004003 }
4004}
4005
Jesse Barnesb074cec2013-04-25 12:55:02 -07004006static void ironlake_pfit_enable(struct intel_crtc *crtc)
4007{
4008 struct drm_device *dev = crtc->base.dev;
4009 struct drm_i915_private *dev_priv = dev->dev_private;
4010 int pipe = crtc->pipe;
4011
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004012 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07004013 /* Force use of hard-coded filter coefficients
4014 * as some pre-programmed values are broken,
4015 * e.g. x201.
4016 */
4017 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4018 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4019 PF_PIPE_SEL_IVB(pipe));
4020 else
4021 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4022 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4023 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08004024 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004025}
4026
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004027static void intel_enable_planes(struct drm_crtc *crtc)
4028{
4029 struct drm_device *dev = crtc->dev;
4030 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07004031 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004032 struct intel_plane *intel_plane;
4033
Matt Roperaf2b6532014-04-01 15:22:32 -07004034 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4035 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004036 if (intel_plane->pipe == pipe)
4037 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07004038 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004039}
4040
4041static void intel_disable_planes(struct drm_crtc *crtc)
4042{
4043 struct drm_device *dev = crtc->dev;
4044 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07004045 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004046 struct intel_plane *intel_plane;
4047
Matt Roperaf2b6532014-04-01 15:22:32 -07004048 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4049 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004050 if (intel_plane->pipe == pipe)
4051 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07004052 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004053}
4054
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004055void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004056{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004057 struct drm_device *dev = crtc->base.dev;
4058 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03004059
4060 if (!crtc->config.ips_enabled)
4061 return;
4062
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004063 /* We can only enable IPS after we enable a plane and wait for a vblank */
4064 intel_wait_for_vblank(dev, crtc->pipe);
4065
Paulo Zanonid77e4532013-09-24 13:52:55 -03004066 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004067 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004068 mutex_lock(&dev_priv->rps.hw_lock);
4069 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4070 mutex_unlock(&dev_priv->rps.hw_lock);
4071 /* Quoting Art Runyan: "its not safe to expect any particular
4072 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08004073 * mailbox." Moreover, the mailbox may return a bogus state,
4074 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004075 */
4076 } else {
4077 I915_WRITE(IPS_CTL, IPS_ENABLE);
4078 /* The bit only becomes 1 in the next vblank, so this wait here
4079 * is essentially intel_wait_for_vblank. If we don't have this
4080 * and don't wait for vblanks until the end of crtc_enable, then
4081 * the HW state readout code will complain that the expected
4082 * IPS_CTL value is not the one we read. */
4083 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4084 DRM_ERROR("Timed out waiting for IPS enable\n");
4085 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004086}
4087
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004088void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004089{
4090 struct drm_device *dev = crtc->base.dev;
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092
4093 if (!crtc->config.ips_enabled)
4094 return;
4095
4096 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004097 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004098 mutex_lock(&dev_priv->rps.hw_lock);
4099 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4100 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004101 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4102 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4103 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08004104 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004105 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08004106 POSTING_READ(IPS_CTL);
4107 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004108
4109 /* We need to wait for a vblank before we can disable the plane. */
4110 intel_wait_for_vblank(dev, crtc->pipe);
4111}
4112
4113/** Loads the palette/gamma unit for the CRTC with the prepared values */
4114static void intel_crtc_load_lut(struct drm_crtc *crtc)
4115{
4116 struct drm_device *dev = crtc->dev;
4117 struct drm_i915_private *dev_priv = dev->dev_private;
4118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119 enum pipe pipe = intel_crtc->pipe;
4120 int palreg = PALETTE(pipe);
4121 int i;
4122 bool reenable_ips = false;
4123
4124 /* The clocks have to be on to load the palette. */
4125 if (!crtc->enabled || !intel_crtc->active)
4126 return;
4127
4128 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03004129 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
Paulo Zanonid77e4532013-09-24 13:52:55 -03004130 assert_dsi_pll_enabled(dev_priv);
4131 else
4132 assert_pll_enabled(dev_priv, pipe);
4133 }
4134
4135 /* use legacy palette for Ironlake */
Sonika Jindal7a1db492014-07-22 11:18:27 +05304136 if (!HAS_GMCH_DISPLAY(dev))
Paulo Zanonid77e4532013-09-24 13:52:55 -03004137 palreg = LGC_PALETTE(pipe);
4138
4139 /* Workaround : Do not read or write the pipe palette/gamma data while
4140 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4141 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02004142 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03004143 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4144 GAMMA_MODE_MODE_SPLIT)) {
4145 hsw_disable_ips(intel_crtc);
4146 reenable_ips = true;
4147 }
4148
4149 for (i = 0; i < 256; i++) {
4150 I915_WRITE(palreg + 4 * i,
4151 (intel_crtc->lut_r[i] << 16) |
4152 (intel_crtc->lut_g[i] << 8) |
4153 intel_crtc->lut_b[i]);
4154 }
4155
4156 if (reenable_ips)
4157 hsw_enable_ips(intel_crtc);
4158}
4159
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004160static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4161{
4162 if (!enable && intel_crtc->overlay) {
4163 struct drm_device *dev = intel_crtc->base.dev;
4164 struct drm_i915_private *dev_priv = dev->dev_private;
4165
4166 mutex_lock(&dev->struct_mutex);
4167 dev_priv->mm.interruptible = false;
4168 (void) intel_overlay_switch_off(intel_crtc->overlay);
4169 dev_priv->mm.interruptible = true;
4170 mutex_unlock(&dev->struct_mutex);
4171 }
4172
4173 /* Let userspace switch the overlay on again. In most cases userspace
4174 * has to recompute where to put it anyway.
4175 */
4176}
4177
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004178static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004179{
4180 struct drm_device *dev = crtc->dev;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004183
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03004184 intel_enable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004185 intel_enable_planes(crtc);
4186 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004187 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004188
4189 hsw_enable_ips(intel_crtc);
4190
4191 mutex_lock(&dev->struct_mutex);
4192 intel_update_fbc(dev);
4193 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf99d7062014-06-19 16:01:59 +02004194
4195 /*
4196 * FIXME: Once we grow proper nuclear flip support out of this we need
4197 * to compute the mask of flip planes precisely. For the time being
4198 * consider this a flip from a NULL plane.
4199 */
4200 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004201}
4202
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004203static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004204{
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208 int pipe = intel_crtc->pipe;
4209 int plane = intel_crtc->plane;
4210
4211 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004212
4213 if (dev_priv->fbc.plane == plane)
4214 intel_disable_fbc(dev);
4215
4216 hsw_disable_ips(intel_crtc);
4217
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004218 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004219 intel_crtc_update_cursor(crtc, false);
4220 intel_disable_planes(crtc);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03004221 intel_disable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03004222
Daniel Vetterf99d7062014-06-19 16:01:59 +02004223 /*
4224 * FIXME: Once we grow proper nuclear flip support out of this we need
4225 * to compute the mask of flip planes precisely. For the time being
4226 * consider this a flip to a NULL plane.
4227 */
4228 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004229}
4230
Jesse Barnesf67a5592011-01-05 10:31:48 -08004231static void ironlake_crtc_enable(struct drm_crtc *crtc)
4232{
4233 struct drm_device *dev = crtc->dev;
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004236 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004237 int pipe = intel_crtc->pipe;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004238
Daniel Vetter08a48462012-07-02 11:43:47 +02004239 WARN_ON(!crtc->enabled);
4240
Jesse Barnesf67a5592011-01-05 10:31:48 -08004241 if (intel_crtc->active)
4242 return;
4243
Daniel Vetterb14b1052014-04-24 23:55:13 +02004244 if (intel_crtc->config.has_pch_encoder)
4245 intel_prepare_shared_dpll(intel_crtc);
4246
Daniel Vetter29407aa2014-04-24 23:55:08 +02004247 if (intel_crtc->config.has_dp_encoder)
4248 intel_dp_set_m_n(intel_crtc);
4249
4250 intel_set_pipe_timings(intel_crtc);
4251
4252 if (intel_crtc->config.has_pch_encoder) {
4253 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004254 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004255 }
4256
4257 ironlake_set_pipeconf(crtc);
4258
Jesse Barnesf67a5592011-01-05 10:31:48 -08004259 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004260
Daniel Vettera72e4c92014-09-30 10:56:47 +02004261 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4262 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni86642812013-04-12 17:57:57 -03004263
Daniel Vetterf6736a12013-06-05 13:34:30 +02004264 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02004265 if (encoder->pre_enable)
4266 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004267
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004268 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02004269 /* Note: FDI PLL enabling _must_ be done before we enable the
4270 * cpu pipes, hence this is separate from all the other fdi/pch
4271 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02004272 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02004273 } else {
4274 assert_fdi_tx_disabled(dev_priv, pipe);
4275 assert_fdi_rx_disabled(dev_priv, pipe);
4276 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004277
Jesse Barnesb074cec2013-04-25 12:55:02 -07004278 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004279
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02004280 /*
4281 * On ILK+ LUT must be loaded before the pipe is running but with
4282 * clocks enabled
4283 */
4284 intel_crtc_load_lut(crtc);
4285
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004286 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004287 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004288
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004289 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004290 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004291
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004292 for_each_encoder_on_crtc(dev, crtc, encoder)
4293 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004294
4295 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004296 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004297
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004298 assert_vblank_disabled(crtc);
4299 drm_crtc_vblank_on(crtc);
4300
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004301 intel_crtc_enable_planes(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004302}
4303
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004304/* IPS only exists on ULT machines and is tied to pipe A. */
4305static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4306{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004307 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004308}
4309
Paulo Zanonie4916942013-09-20 16:21:19 -03004310/*
4311 * This implements the workaround described in the "notes" section of the mode
4312 * set sequence documentation. When going from no pipes or single pipe to
4313 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4314 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4315 */
4316static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4317{
4318 struct drm_device *dev = crtc->base.dev;
4319 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4320
4321 /* We want to get the other_active_crtc only if there's only 1 other
4322 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004323 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004324 if (!crtc_it->active || crtc_it == crtc)
4325 continue;
4326
4327 if (other_active_crtc)
4328 return;
4329
4330 other_active_crtc = crtc_it;
4331 }
4332 if (!other_active_crtc)
4333 return;
4334
4335 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4336 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4337}
4338
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004339static void haswell_crtc_enable(struct drm_crtc *crtc)
4340{
4341 struct drm_device *dev = crtc->dev;
4342 struct drm_i915_private *dev_priv = dev->dev_private;
4343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344 struct intel_encoder *encoder;
4345 int pipe = intel_crtc->pipe;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004346
4347 WARN_ON(!crtc->enabled);
4348
4349 if (intel_crtc->active)
4350 return;
4351
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004352 if (intel_crtc_to_shared_dpll(intel_crtc))
4353 intel_enable_shared_dpll(intel_crtc);
4354
Daniel Vetter229fca92014-04-24 23:55:09 +02004355 if (intel_crtc->config.has_dp_encoder)
4356 intel_dp_set_m_n(intel_crtc);
4357
4358 intel_set_pipe_timings(intel_crtc);
4359
Clint Taylorebb69c92014-09-30 10:30:22 -07004360 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4361 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4362 intel_crtc->config.pixel_multiplier - 1);
4363 }
4364
Daniel Vetter229fca92014-04-24 23:55:09 +02004365 if (intel_crtc->config.has_pch_encoder) {
4366 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004367 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02004368 }
4369
4370 haswell_set_pipeconf(crtc);
4371
4372 intel_set_pipe_csc(crtc);
4373
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004374 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004375
Daniel Vettera72e4c92014-09-30 10:56:47 +02004376 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004377 for_each_encoder_on_crtc(dev, crtc, encoder)
4378 if (encoder->pre_enable)
4379 encoder->pre_enable(encoder);
4380
Imre Deak4fe94672014-06-25 22:01:49 +03004381 if (intel_crtc->config.has_pch_encoder) {
Daniel Vettera72e4c92014-09-30 10:56:47 +02004382 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4383 true);
Imre Deak4fe94672014-06-25 22:01:49 +03004384 dev_priv->display.fdi_link_train(crtc);
4385 }
4386
Paulo Zanoni1f544382012-10-24 11:32:00 -02004387 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004388
Jesse Barnesb074cec2013-04-25 12:55:02 -07004389 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004390
4391 /*
4392 * On ILK+ LUT must be loaded before the pipe is running but with
4393 * clocks enabled
4394 */
4395 intel_crtc_load_lut(crtc);
4396
Paulo Zanoni1f544382012-10-24 11:32:00 -02004397 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004398 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004399
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004400 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004401 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004402
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004403 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004404 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004405
Dave Airlie0e32b392014-05-02 14:02:48 +10004406 if (intel_crtc->config.dp_encoder_is_mst)
4407 intel_ddi_set_vc_payload_alloc(crtc, true);
4408
Jani Nikula8807e552013-08-30 19:40:32 +03004409 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004410 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004411 intel_opregion_notify_encoder(encoder, true);
4412 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004413
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004414 assert_vblank_disabled(crtc);
4415 drm_crtc_vblank_on(crtc);
4416
Paulo Zanonie4916942013-09-20 16:21:19 -03004417 /* If we change the relative order between pipe/planes enabling, we need
4418 * to change the workaround. */
4419 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004420 intel_crtc_enable_planes(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004421}
4422
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004423static void ironlake_pfit_disable(struct intel_crtc *crtc)
4424{
4425 struct drm_device *dev = crtc->base.dev;
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427 int pipe = crtc->pipe;
4428
4429 /* To avoid upsetting the power well on haswell only disable the pfit if
4430 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004431 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004432 I915_WRITE(PF_CTL(pipe), 0);
4433 I915_WRITE(PF_WIN_POS(pipe), 0);
4434 I915_WRITE(PF_WIN_SZ(pipe), 0);
4435 }
4436}
4437
Jesse Barnes6be4a602010-09-10 10:26:01 -07004438static void ironlake_crtc_disable(struct drm_crtc *crtc)
4439{
4440 struct drm_device *dev = crtc->dev;
4441 struct drm_i915_private *dev_priv = dev->dev_private;
4442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004443 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004444 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004445 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004446
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004447 if (!intel_crtc->active)
4448 return;
4449
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004450 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004451
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004452 drm_crtc_vblank_off(crtc);
4453 assert_vblank_disabled(crtc);
4454
Daniel Vetterea9d7582012-07-10 10:42:52 +02004455 for_each_encoder_on_crtc(dev, crtc, encoder)
4456 encoder->disable(encoder);
4457
Daniel Vetterd925c592013-06-05 13:34:04 +02004458 if (intel_crtc->config.has_pch_encoder)
Daniel Vettera72e4c92014-09-30 10:56:47 +02004459 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
Daniel Vetterd925c592013-06-05 13:34:04 +02004460
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03004461 intel_disable_pipe(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004462
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004463 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004464
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004465 for_each_encoder_on_crtc(dev, crtc, encoder)
4466 if (encoder->post_disable)
4467 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004468
Daniel Vetterd925c592013-06-05 13:34:04 +02004469 if (intel_crtc->config.has_pch_encoder) {
4470 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004471
Daniel Vetterd925c592013-06-05 13:34:04 +02004472 ironlake_disable_pch_transcoder(dev_priv, pipe);
Daniel Vettera72e4c92014-09-30 10:56:47 +02004473 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004474
Daniel Vetterd925c592013-06-05 13:34:04 +02004475 if (HAS_PCH_CPT(dev)) {
4476 /* disable TRANS_DP_CTL */
4477 reg = TRANS_DP_CTL(pipe);
4478 temp = I915_READ(reg);
4479 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4480 TRANS_DP_PORT_SEL_MASK);
4481 temp |= TRANS_DP_PORT_SEL_NONE;
4482 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004483
Daniel Vetterd925c592013-06-05 13:34:04 +02004484 /* disable DPLL_SEL */
4485 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004486 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004487 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004488 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004489
4490 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004491 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004492
4493 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004494 }
4495
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004496 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004497 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004498
4499 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004500 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004501 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004502}
4503
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004504static void haswell_crtc_disable(struct drm_crtc *crtc)
4505{
4506 struct drm_device *dev = crtc->dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509 struct intel_encoder *encoder;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004510 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004511
4512 if (!intel_crtc->active)
4513 return;
4514
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004515 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004516
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004517 drm_crtc_vblank_off(crtc);
4518 assert_vblank_disabled(crtc);
4519
Jani Nikula8807e552013-08-30 19:40:32 +03004520 for_each_encoder_on_crtc(dev, crtc, encoder) {
4521 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004522 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004523 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004524
Paulo Zanoni86642812013-04-12 17:57:57 -03004525 if (intel_crtc->config.has_pch_encoder)
Daniel Vettera72e4c92014-09-30 10:56:47 +02004526 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4527 false);
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03004528 intel_disable_pipe(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004529
Ville Syrjäläa4bf2142014-08-18 21:27:34 +03004530 if (intel_crtc->config.dp_encoder_is_mst)
4531 intel_ddi_set_vc_payload_alloc(crtc, false);
4532
Paulo Zanoniad80a812012-10-24 16:06:19 -02004533 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004534
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004535 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004536
Paulo Zanoni1f544382012-10-24 11:32:00 -02004537 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004538
Daniel Vetter88adfff2013-03-28 10:42:01 +01004539 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004540 lpt_disable_pch_transcoder(dev_priv);
Daniel Vettera72e4c92014-09-30 10:56:47 +02004541 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4542 true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004543 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004544 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004545
Imre Deak97b040a2014-06-25 22:01:50 +03004546 for_each_encoder_on_crtc(dev, crtc, encoder)
4547 if (encoder->post_disable)
4548 encoder->post_disable(encoder);
4549
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004550 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004551 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004552
4553 mutex_lock(&dev->struct_mutex);
4554 intel_update_fbc(dev);
4555 mutex_unlock(&dev->struct_mutex);
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004556
4557 if (intel_crtc_to_shared_dpll(intel_crtc))
4558 intel_disable_shared_dpll(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004559}
4560
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004561static void ironlake_crtc_off(struct drm_crtc *crtc)
4562{
4563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004564 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004565}
4566
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004567
Jesse Barnes2dd24552013-04-25 12:55:01 -07004568static void i9xx_pfit_enable(struct intel_crtc *crtc)
4569{
4570 struct drm_device *dev = crtc->base.dev;
4571 struct drm_i915_private *dev_priv = dev->dev_private;
4572 struct intel_crtc_config *pipe_config = &crtc->config;
4573
Daniel Vetter328d8e82013-05-08 10:36:31 +02004574 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004575 return;
4576
Daniel Vetterc0b03412013-05-28 12:05:54 +02004577 /*
4578 * The panel fitter should only be adjusted whilst the pipe is disabled,
4579 * according to register description and PRM.
4580 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004581 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4582 assert_pipe_disabled(dev_priv, crtc->pipe);
4583
Jesse Barnesb074cec2013-04-25 12:55:02 -07004584 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4585 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004586
4587 /* Border color in case we don't scale up to the full screen. Black by
4588 * default, change to something else for debugging. */
4589 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004590}
4591
Dave Airlied05410f2014-06-05 13:22:59 +10004592static enum intel_display_power_domain port_to_power_domain(enum port port)
4593{
4594 switch (port) {
4595 case PORT_A:
4596 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4597 case PORT_B:
4598 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4599 case PORT_C:
4600 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4601 case PORT_D:
4602 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4603 default:
4604 WARN_ON_ONCE(1);
4605 return POWER_DOMAIN_PORT_OTHER;
4606 }
4607}
4608
Imre Deak77d22dc2014-03-05 16:20:52 +02004609#define for_each_power_domain(domain, mask) \
4610 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4611 if ((1 << (domain)) & (mask))
4612
Imre Deak319be8a2014-03-04 19:22:57 +02004613enum intel_display_power_domain
4614intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004615{
Imre Deak319be8a2014-03-04 19:22:57 +02004616 struct drm_device *dev = intel_encoder->base.dev;
4617 struct intel_digital_port *intel_dig_port;
4618
4619 switch (intel_encoder->type) {
4620 case INTEL_OUTPUT_UNKNOWN:
4621 /* Only DDI platforms should ever use this output type */
4622 WARN_ON_ONCE(!HAS_DDI(dev));
4623 case INTEL_OUTPUT_DISPLAYPORT:
4624 case INTEL_OUTPUT_HDMI:
4625 case INTEL_OUTPUT_EDP:
4626 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10004627 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10004628 case INTEL_OUTPUT_DP_MST:
4629 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4630 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02004631 case INTEL_OUTPUT_ANALOG:
4632 return POWER_DOMAIN_PORT_CRT;
4633 case INTEL_OUTPUT_DSI:
4634 return POWER_DOMAIN_PORT_DSI;
4635 default:
4636 return POWER_DOMAIN_PORT_OTHER;
4637 }
4638}
4639
4640static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4641{
4642 struct drm_device *dev = crtc->dev;
4643 struct intel_encoder *intel_encoder;
4644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02004646 unsigned long mask;
4647 enum transcoder transcoder;
4648
4649 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4650
4651 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4652 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Daniel Vetterfabf6e52014-05-29 14:10:22 +02004653 if (intel_crtc->config.pch_pfit.enabled ||
4654 intel_crtc->config.pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02004655 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4656
Imre Deak319be8a2014-03-04 19:22:57 +02004657 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4658 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4659
Imre Deak77d22dc2014-03-05 16:20:52 +02004660 return mask;
4661}
4662
Imre Deak77d22dc2014-03-05 16:20:52 +02004663static void modeset_update_crtc_power_domains(struct drm_device *dev)
4664{
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4667 struct intel_crtc *crtc;
4668
4669 /*
4670 * First get all needed power domains, then put all unneeded, to avoid
4671 * any unnecessary toggling of the power wells.
4672 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004673 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004674 enum intel_display_power_domain domain;
4675
4676 if (!crtc->base.enabled)
4677 continue;
4678
Imre Deak319be8a2014-03-04 19:22:57 +02004679 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004680
4681 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4682 intel_display_power_get(dev_priv, domain);
4683 }
4684
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004685 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004686 enum intel_display_power_domain domain;
4687
4688 for_each_power_domain(domain, crtc->enabled_power_domains)
4689 intel_display_power_put(dev_priv, domain);
4690
4691 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4692 }
4693
4694 intel_display_set_init_power(dev_priv, false);
4695}
4696
Ville Syrjälädfcab172014-06-13 13:37:47 +03004697/* returns HPLL frequency in kHz */
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004698static int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004699{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004700 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004701
Jesse Barnes586f49d2013-11-04 16:06:59 -08004702 /* Obtain SKU information */
4703 mutex_lock(&dev_priv->dpio_lock);
4704 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4705 CCK_FUSE_HPLL_FREQ_MASK;
4706 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004707
Ville Syrjälädfcab172014-06-13 13:37:47 +03004708 return vco_freq[hpll_freq] * 1000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004709}
4710
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004711static void vlv_update_cdclk(struct drm_device *dev)
4712{
4713 struct drm_i915_private *dev_priv = dev->dev_private;
4714
4715 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
Ville Syrjälä43dc52c2014-10-07 17:41:20 +03004716 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004717 dev_priv->vlv_cdclk_freq);
4718
4719 /*
4720 * Program the gmbus_freq based on the cdclk frequency.
4721 * BSpec erroneously claims we should aim for 4MHz, but
4722 * in fact 1MHz is the correct frequency.
4723 */
4724 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4725}
4726
Jesse Barnes30a970c2013-11-04 13:48:12 -08004727/* Adjust CDclk dividers to allow high res or save power if possible */
4728static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4729{
4730 struct drm_i915_private *dev_priv = dev->dev_private;
4731 u32 val, cmd;
4732
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03004733 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02004734
Ville Syrjälädfcab172014-06-13 13:37:47 +03004735 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08004736 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03004737 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004738 cmd = 1;
4739 else
4740 cmd = 0;
4741
4742 mutex_lock(&dev_priv->rps.hw_lock);
4743 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4744 val &= ~DSPFREQGUAR_MASK;
4745 val |= (cmd << DSPFREQGUAR_SHIFT);
4746 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4747 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4748 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4749 50)) {
4750 DRM_ERROR("timed out waiting for CDclk change\n");
4751 }
4752 mutex_unlock(&dev_priv->rps.hw_lock);
4753
Ville Syrjälädfcab172014-06-13 13:37:47 +03004754 if (cdclk == 400000) {
Jesse Barnes30a970c2013-11-04 13:48:12 -08004755 u32 divider, vco;
4756
4757 vco = valleyview_get_vco(dev_priv);
Ville Syrjälädfcab172014-06-13 13:37:47 +03004758 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004759
4760 mutex_lock(&dev_priv->dpio_lock);
4761 /* adjust cdclk divider */
4762 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Ville Syrjälä9cf33db2014-06-13 13:37:48 +03004763 val &= ~DISPLAY_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004764 val |= divider;
4765 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03004766
4767 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4768 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4769 50))
4770 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08004771 mutex_unlock(&dev_priv->dpio_lock);
4772 }
4773
4774 mutex_lock(&dev_priv->dpio_lock);
4775 /* adjust self-refresh exit latency value */
4776 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4777 val &= ~0x7f;
4778
4779 /*
4780 * For high bandwidth configs, we set a higher latency in the bunit
4781 * so that the core display fetch happens in time to avoid underruns.
4782 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03004783 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004784 val |= 4500 / 250; /* 4.5 usec */
4785 else
4786 val |= 3000 / 250; /* 3.0 usec */
4787 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4788 mutex_unlock(&dev_priv->dpio_lock);
4789
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004790 vlv_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004791}
4792
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004793static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4794{
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 u32 val, cmd;
4797
4798 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4799
4800 switch (cdclk) {
4801 case 400000:
4802 cmd = 3;
4803 break;
4804 case 333333:
4805 case 320000:
4806 cmd = 2;
4807 break;
4808 case 266667:
4809 cmd = 1;
4810 break;
4811 case 200000:
4812 cmd = 0;
4813 break;
4814 default:
4815 WARN_ON(1);
4816 return;
4817 }
4818
4819 mutex_lock(&dev_priv->rps.hw_lock);
4820 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4821 val &= ~DSPFREQGUAR_MASK_CHV;
4822 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4823 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4824 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4825 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4826 50)) {
4827 DRM_ERROR("timed out waiting for CDclk change\n");
4828 }
4829 mutex_unlock(&dev_priv->rps.hw_lock);
4830
4831 vlv_update_cdclk(dev);
4832}
4833
Jesse Barnes30a970c2013-11-04 13:48:12 -08004834static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4835 int max_pixclk)
4836{
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004837 int vco = valleyview_get_vco(dev_priv);
4838 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4839
Ville Syrjäläd49a3402014-06-28 02:03:58 +03004840 /* FIXME: Punit isn't quite ready yet */
4841 if (IS_CHERRYVIEW(dev_priv->dev))
4842 return 400000;
4843
Jesse Barnes30a970c2013-11-04 13:48:12 -08004844 /*
4845 * Really only a few cases to deal with, as only 4 CDclks are supported:
4846 * 200MHz
4847 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004848 * 320/333MHz (depends on HPLL freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004849 * 400MHz
4850 * So we check to see whether we're above 90% of the lower bin and
4851 * adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004852 *
4853 * We seem to get an unstable or solid color picture at 200MHz.
4854 * Not sure what's wrong. For now use 200MHz only when all pipes
4855 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08004856 */
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004857 if (max_pixclk > freq_320*9/10)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004858 return 400000;
4859 else if (max_pixclk > 266667*9/10)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004860 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004861 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004862 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004863 else
4864 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004865}
4866
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004867/* compute the max pixel clock for new configuration */
4868static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004869{
4870 struct drm_device *dev = dev_priv->dev;
4871 struct intel_crtc *intel_crtc;
4872 int max_pixclk = 0;
4873
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004874 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004875 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004876 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004877 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004878 }
4879
4880 return max_pixclk;
4881}
4882
4883static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004884 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004885{
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004888 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004889
Imre Deakd60c4472014-03-27 17:45:10 +02004890 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4891 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004892 return;
4893
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004894 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004895 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004896 if (intel_crtc->base.enabled)
4897 *prepare_pipes |= (1 << intel_crtc->pipe);
4898}
4899
4900static void valleyview_modeset_global_resources(struct drm_device *dev)
4901{
4902 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004903 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004904 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4905
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004906 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4907 if (IS_CHERRYVIEW(dev))
4908 cherryview_set_cdclk(dev, req_cdclk);
4909 else
4910 valleyview_set_cdclk(dev, req_cdclk);
4911 }
4912
Imre Deak77961eb2014-03-05 16:20:56 +02004913 modeset_update_crtc_power_domains(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004914}
4915
Jesse Barnes89b667f2013-04-18 14:51:36 -07004916static void valleyview_crtc_enable(struct drm_crtc *crtc)
4917{
4918 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02004919 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921 struct intel_encoder *encoder;
4922 int pipe = intel_crtc->pipe;
Jani Nikula23538ef2013-08-27 15:12:22 +03004923 bool is_dsi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004924
4925 WARN_ON(!crtc->enabled);
4926
4927 if (intel_crtc->active)
4928 return;
4929
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03004930 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
Shobhit Kumar8525a232014-06-25 12:20:39 +05304931
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004932 if (!is_dsi) {
4933 if (IS_CHERRYVIEW(dev))
Ville Syrjäläd288f652014-10-28 13:20:22 +02004934 chv_prepare_pll(intel_crtc, &intel_crtc->config);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004935 else
Ville Syrjäläd288f652014-10-28 13:20:22 +02004936 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004937 }
Daniel Vetter5b18e572014-04-24 23:55:06 +02004938
4939 if (intel_crtc->config.has_dp_encoder)
4940 intel_dp_set_m_n(intel_crtc);
4941
4942 intel_set_pipe_timings(intel_crtc);
4943
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004944 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946
4947 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4948 I915_WRITE(CHV_CANVAS(pipe), 0);
4949 }
4950
Daniel Vetter5b18e572014-04-24 23:55:06 +02004951 i9xx_set_pipeconf(intel_crtc);
4952
Jesse Barnes89b667f2013-04-18 14:51:36 -07004953 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004954
Daniel Vettera72e4c92014-09-30 10:56:47 +02004955 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004956
Jesse Barnes89b667f2013-04-18 14:51:36 -07004957 for_each_encoder_on_crtc(dev, crtc, encoder)
4958 if (encoder->pre_pll_enable)
4959 encoder->pre_pll_enable(encoder);
4960
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004961 if (!is_dsi) {
4962 if (IS_CHERRYVIEW(dev))
Ville Syrjäläd288f652014-10-28 13:20:22 +02004963 chv_enable_pll(intel_crtc, &intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004964 else
Ville Syrjäläd288f652014-10-28 13:20:22 +02004965 vlv_enable_pll(intel_crtc, &intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004966 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004967
4968 for_each_encoder_on_crtc(dev, crtc, encoder)
4969 if (encoder->pre_enable)
4970 encoder->pre_enable(encoder);
4971
Jesse Barnes2dd24552013-04-25 12:55:01 -07004972 i9xx_pfit_enable(intel_crtc);
4973
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004974 intel_crtc_load_lut(crtc);
4975
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004976 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004977 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004978
Jani Nikula50049452013-07-30 12:20:32 +03004979 for_each_encoder_on_crtc(dev, crtc, encoder)
4980 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004981
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004982 assert_vblank_disabled(crtc);
4983 drm_crtc_vblank_on(crtc);
4984
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004985 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004986
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004987 /* Underruns don't raise interrupts, so check manually. */
Daniel Vettera72e4c92014-09-30 10:56:47 +02004988 i9xx_check_fifo_underruns(dev_priv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004989}
4990
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004991static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4992{
4993 struct drm_device *dev = crtc->base.dev;
4994 struct drm_i915_private *dev_priv = dev->dev_private;
4995
4996 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4997 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4998}
4999
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005000static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005001{
5002 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02005003 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08005004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005005 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005006 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08005007
Daniel Vetter08a48462012-07-02 11:43:47 +02005008 WARN_ON(!crtc->enabled);
5009
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005010 if (intel_crtc->active)
5011 return;
5012
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02005013 i9xx_set_pll_dividers(intel_crtc);
5014
Daniel Vetter5b18e572014-04-24 23:55:06 +02005015 if (intel_crtc->config.has_dp_encoder)
5016 intel_dp_set_m_n(intel_crtc);
5017
5018 intel_set_pipe_timings(intel_crtc);
5019
Daniel Vetter5b18e572014-04-24 23:55:06 +02005020 i9xx_set_pipeconf(intel_crtc);
5021
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005022 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01005023
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005024 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005025 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005026
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02005027 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02005028 if (encoder->pre_enable)
5029 encoder->pre_enable(encoder);
5030
Daniel Vetterf6736a12013-06-05 13:34:30 +02005031 i9xx_enable_pll(intel_crtc);
5032
Jesse Barnes2dd24552013-04-25 12:55:01 -07005033 i9xx_pfit_enable(intel_crtc);
5034
Ville Syrjälä63cbb072013-06-04 13:48:59 +03005035 intel_crtc_load_lut(crtc);
5036
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005037 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005038 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02005039
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02005040 for_each_encoder_on_crtc(dev, crtc, encoder)
5041 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005042
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005043 assert_vblank_disabled(crtc);
5044 drm_crtc_vblank_on(crtc);
5045
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005046 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02005047
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005048 /*
5049 * Gen2 reports pipe underruns whenever all planes are disabled.
5050 * So don't enable underrun reporting before at least some planes
5051 * are enabled.
5052 * FIXME: Need to fix the logic to work when we turn off all planes
5053 * but leave the pipe running.
5054 */
5055 if (IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005056 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005057
Ville Syrjälä56b80e12014-05-16 19:40:22 +03005058 /* Underruns don't raise interrupts, so check manually. */
Daniel Vettera72e4c92014-09-30 10:56:47 +02005059 i9xx_check_fifo_underruns(dev_priv);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005060}
5061
Daniel Vetter87476d62013-04-11 16:29:06 +02005062static void i9xx_pfit_disable(struct intel_crtc *crtc)
5063{
5064 struct drm_device *dev = crtc->base.dev;
5065 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02005066
5067 if (!crtc->config.gmch_pfit.control)
5068 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02005069
5070 assert_pipe_disabled(dev_priv, crtc->pipe);
5071
Daniel Vetter328d8e82013-05-08 10:36:31 +02005072 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5073 I915_READ(PFIT_CONTROL));
5074 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02005075}
5076
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005077static void i9xx_crtc_disable(struct drm_crtc *crtc)
5078{
5079 struct drm_device *dev = crtc->dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005082 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005083 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005084
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005085 if (!intel_crtc->active)
5086 return;
5087
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005088 /*
5089 * Gen2 reports pipe underruns whenever all planes are disabled.
5090 * So diasble underrun reporting before all the planes get disabled.
5091 * FIXME: Need to fix the logic to work when we turn off all planes
5092 * but leave the pipe running.
5093 */
5094 if (IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005095 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005096
Imre Deak564ed192014-06-13 14:54:21 +03005097 /*
5098 * Vblank time updates from the shadow to live plane control register
5099 * are blocked if the memory self-refresh mode is active at that
5100 * moment. So to make sure the plane gets truly disabled, disable
5101 * first the self-refresh mode. The self-refresh enable bit in turn
5102 * will be checked/applied by the HW only at the next frame start
5103 * event which is after the vblank start event, so we need to have a
5104 * wait-for-vblank between disabling the plane and the pipe.
5105 */
5106 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005107 intel_crtc_disable_planes(crtc);
5108
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005109 /*
5110 * On gen2 planes are double buffered but the pipe isn't, so we must
5111 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03005112 * We also need to wait on all gmch platforms because of the
5113 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005114 */
Imre Deak564ed192014-06-13 14:54:21 +03005115 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005116
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005117 drm_crtc_vblank_off(crtc);
5118 assert_vblank_disabled(crtc);
5119
5120 for_each_encoder_on_crtc(dev, crtc, encoder)
5121 encoder->disable(encoder);
5122
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03005123 intel_disable_pipe(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02005124
Daniel Vetter87476d62013-04-11 16:29:06 +02005125 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02005126
Jesse Barnes89b667f2013-04-18 14:51:36 -07005127 for_each_encoder_on_crtc(dev, crtc, encoder)
5128 if (encoder->post_disable)
5129 encoder->post_disable(encoder);
5130
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005131 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03005132 if (IS_CHERRYVIEW(dev))
5133 chv_disable_pll(dev_priv, pipe);
5134 else if (IS_VALLEYVIEW(dev))
5135 vlv_disable_pll(dev_priv, pipe);
5136 else
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03005137 i9xx_disable_pll(intel_crtc);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03005138 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005139
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005140 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005141 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005142
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005143 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03005144 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005145
Daniel Vetterefa96242014-04-24 23:55:02 +02005146 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01005147 intel_update_fbc(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02005148 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005149}
5150
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005151static void i9xx_crtc_off(struct drm_crtc *crtc)
5152{
5153}
5154
Daniel Vetter976f8a22012-07-08 22:34:21 +02005155static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5156 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005157{
5158 struct drm_device *dev = crtc->dev;
5159 struct drm_i915_master_private *master_priv;
5160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08005162
5163 if (!dev->primary->master)
5164 return;
5165
5166 master_priv = dev->primary->master->driver_priv;
5167 if (!master_priv->sarea_priv)
5168 return;
5169
Jesse Barnes79e53942008-11-07 14:24:08 -08005170 switch (pipe) {
5171 case 0:
5172 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5173 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5174 break;
5175 case 1:
5176 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5177 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5178 break;
5179 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005180 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005181 break;
5182 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005183}
5184
Borun Fub04c5bd2014-07-12 10:02:27 +05305185/* Master function to enable/disable CRTC and corresponding power wells */
5186void intel_crtc_control(struct drm_crtc *crtc, bool enable)
Chris Wilsoncdd59982010-09-08 16:30:16 +01005187{
Chris Wilsoncdd59982010-09-08 16:30:16 +01005188 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005189 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005191 enum intel_display_power_domain domain;
5192 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005193
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005194 if (enable) {
5195 if (!intel_crtc->active) {
Daniel Vettere1e9fb82014-06-25 22:02:04 +03005196 domains = get_crtc_power_domains(crtc);
5197 for_each_power_domain(domain, domains)
5198 intel_display_power_get(dev_priv, domain);
5199 intel_crtc->enabled_power_domains = domains;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005200
5201 dev_priv->display.crtc_enable(crtc);
5202 }
5203 } else {
5204 if (intel_crtc->active) {
5205 dev_priv->display.crtc_disable(crtc);
5206
Daniel Vettere1e9fb82014-06-25 22:02:04 +03005207 domains = intel_crtc->enabled_power_domains;
5208 for_each_power_domain(domain, domains)
5209 intel_display_power_put(dev_priv, domain);
5210 intel_crtc->enabled_power_domains = 0;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005211 }
5212 }
Borun Fub04c5bd2014-07-12 10:02:27 +05305213}
5214
5215/**
5216 * Sets the power management mode of the pipe and plane.
5217 */
5218void intel_crtc_update_dpms(struct drm_crtc *crtc)
5219{
5220 struct drm_device *dev = crtc->dev;
5221 struct intel_encoder *intel_encoder;
5222 bool enable = false;
5223
5224 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5225 enable |= intel_encoder->connectors_active;
5226
5227 intel_crtc_control(crtc, enable);
Daniel Vetter976f8a22012-07-08 22:34:21 +02005228
5229 intel_crtc_update_sarea(crtc, enable);
5230}
5231
Daniel Vetter976f8a22012-07-08 22:34:21 +02005232static void intel_crtc_disable(struct drm_crtc *crtc)
5233{
5234 struct drm_device *dev = crtc->dev;
5235 struct drm_connector *connector;
5236 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper2ff8fde2014-07-08 07:50:07 -07005237 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
Daniel Vettera071fa02014-06-18 23:28:09 +02005238 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005239
5240 /* crtc should still be enabled when we disable it. */
5241 WARN_ON(!crtc->enabled);
5242
5243 dev_priv->display.crtc_disable(crtc);
5244 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005245 dev_priv->display.off(crtc);
5246
Matt Roperf4510a22014-04-01 15:22:40 -07005247 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01005248 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02005249 intel_unpin_fb_obj(old_obj);
5250 i915_gem_track_fb(old_obj, NULL,
5251 INTEL_FRONTBUFFER_PRIMARY(pipe));
Chris Wilsoncdd59982010-09-08 16:30:16 +01005252 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07005253 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005254 }
5255
5256 /* Update computed state. */
5257 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5258 if (!connector->encoder || !connector->encoder->crtc)
5259 continue;
5260
5261 if (connector->encoder->crtc != crtc)
5262 continue;
5263
5264 connector->dpms = DRM_MODE_DPMS_OFF;
5265 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01005266 }
5267}
5268
Chris Wilsonea5b2132010-08-04 13:50:23 +01005269void intel_encoder_destroy(struct drm_encoder *encoder)
5270{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005271 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01005272
Chris Wilsonea5b2132010-08-04 13:50:23 +01005273 drm_encoder_cleanup(encoder);
5274 kfree(intel_encoder);
5275}
5276
Damien Lespiau92373292013-08-08 22:28:57 +01005277/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005278 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5279 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01005280static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005281{
5282 if (mode == DRM_MODE_DPMS_ON) {
5283 encoder->connectors_active = true;
5284
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005285 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005286 } else {
5287 encoder->connectors_active = false;
5288
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005289 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005290 }
5291}
5292
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005293/* Cross check the actual hw state with our own modeset state tracking (and it's
5294 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02005295static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005296{
5297 if (connector->get_hw_state(connector)) {
5298 struct intel_encoder *encoder = connector->encoder;
5299 struct drm_crtc *crtc;
5300 bool encoder_enabled;
5301 enum pipe pipe;
5302
5303 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5304 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03005305 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005306
Dave Airlie0e32b392014-05-02 14:02:48 +10005307 /* there is no real hw state for MST connectors */
5308 if (connector->mst_port)
5309 return;
5310
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005311 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5312 "wrong connector dpms state\n");
5313 WARN(connector->base.encoder != &encoder->base,
5314 "active connector not linked to encoder\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005315
Dave Airlie36cd7442014-05-02 13:44:18 +10005316 if (encoder) {
5317 WARN(!encoder->connectors_active,
5318 "encoder->connectors_active not set\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005319
Dave Airlie36cd7442014-05-02 13:44:18 +10005320 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5321 WARN(!encoder_enabled, "encoder not enabled\n");
5322 if (WARN_ON(!encoder->base.crtc))
5323 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005324
Dave Airlie36cd7442014-05-02 13:44:18 +10005325 crtc = encoder->base.crtc;
5326
5327 WARN(!crtc->enabled, "crtc not enabled\n");
5328 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5329 WARN(pipe != to_intel_crtc(crtc)->pipe,
5330 "encoder active on the wrong pipe\n");
5331 }
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005332 }
5333}
5334
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005335/* Even simpler default implementation, if there's really no special case to
5336 * consider. */
5337void intel_connector_dpms(struct drm_connector *connector, int mode)
5338{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005339 /* All the simple cases only support two dpms states. */
5340 if (mode != DRM_MODE_DPMS_ON)
5341 mode = DRM_MODE_DPMS_OFF;
5342
5343 if (mode == connector->dpms)
5344 return;
5345
5346 connector->dpms = mode;
5347
5348 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01005349 if (connector->encoder)
5350 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005351
Daniel Vetterb9805142012-08-31 17:37:33 +02005352 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005353}
5354
Daniel Vetterf0947c32012-07-02 13:10:34 +02005355/* Simple connector->get_hw_state implementation for encoders that support only
5356 * one connector and no cloning and hence the encoder state determines the state
5357 * of the connector. */
5358bool intel_connector_get_hw_state(struct intel_connector *connector)
5359{
Daniel Vetter24929352012-07-02 20:28:59 +02005360 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02005361 struct intel_encoder *encoder = connector->encoder;
5362
5363 return encoder->get_hw_state(encoder, &pipe);
5364}
5365
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005366static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5367 struct intel_crtc_config *pipe_config)
5368{
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 struct intel_crtc *pipe_B_crtc =
5371 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5372
5373 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5374 pipe_name(pipe), pipe_config->fdi_lanes);
5375 if (pipe_config->fdi_lanes > 4) {
5376 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5377 pipe_name(pipe), pipe_config->fdi_lanes);
5378 return false;
5379 }
5380
Paulo Zanonibafb6552013-11-02 21:07:44 -07005381 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005382 if (pipe_config->fdi_lanes > 2) {
5383 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5384 pipe_config->fdi_lanes);
5385 return false;
5386 } else {
5387 return true;
5388 }
5389 }
5390
5391 if (INTEL_INFO(dev)->num_pipes == 2)
5392 return true;
5393
5394 /* Ivybridge 3 pipe is really complicated */
5395 switch (pipe) {
5396 case PIPE_A:
5397 return true;
5398 case PIPE_B:
5399 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5400 pipe_config->fdi_lanes > 2) {
5401 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5402 pipe_name(pipe), pipe_config->fdi_lanes);
5403 return false;
5404 }
5405 return true;
5406 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005407 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005408 pipe_B_crtc->config.fdi_lanes <= 2) {
5409 if (pipe_config->fdi_lanes > 2) {
5410 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5411 pipe_name(pipe), pipe_config->fdi_lanes);
5412 return false;
5413 }
5414 } else {
5415 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5416 return false;
5417 }
5418 return true;
5419 default:
5420 BUG();
5421 }
5422}
5423
Daniel Vettere29c22c2013-02-21 00:00:16 +01005424#define RETRY 1
5425static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5426 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005427{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005428 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005429 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005430 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005431 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005432
Daniel Vettere29c22c2013-02-21 00:00:16 +01005433retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005434 /* FDI is a binary signal running at ~2.7GHz, encoding
5435 * each output octet as 10 bits. The actual frequency
5436 * is stored as a divider into a 100MHz clock, and the
5437 * mode pixel clock is stored in units of 1KHz.
5438 * Hence the bw of each lane in terms of the mode signal
5439 * is:
5440 */
5441 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5442
Damien Lespiau241bfc32013-09-25 16:45:37 +01005443 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005444
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005445 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005446 pipe_config->pipe_bpp);
5447
5448 pipe_config->fdi_lanes = lane;
5449
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005450 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005451 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005452
Daniel Vettere29c22c2013-02-21 00:00:16 +01005453 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5454 intel_crtc->pipe, pipe_config);
5455 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5456 pipe_config->pipe_bpp -= 2*3;
5457 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5458 pipe_config->pipe_bpp);
5459 needs_recompute = true;
5460 pipe_config->bw_constrained = true;
5461
5462 goto retry;
5463 }
5464
5465 if (needs_recompute)
5466 return RETRY;
5467
5468 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005469}
5470
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005471static void hsw_compute_ips_config(struct intel_crtc *crtc,
5472 struct intel_crtc_config *pipe_config)
5473{
Jani Nikulad330a952014-01-21 11:24:25 +02005474 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005475 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005476 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005477}
5478
Daniel Vettera43f6e02013-06-07 23:10:32 +02005479static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005480 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005481{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005482 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02005483 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005484 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005485
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005486 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005487 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005488 int clock_limit =
5489 dev_priv->display.get_display_clock_speed(dev);
5490
5491 /*
5492 * Enable pixel doubling when the dot clock
5493 * is > 90% of the (display) core speed.
5494 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005495 * GDG double wide on either pipe,
5496 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005497 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005498 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005499 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005500 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005501 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005502 }
5503
Damien Lespiau241bfc32013-09-25 16:45:37 +01005504 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005505 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005506 }
Chris Wilson89749352010-09-12 18:25:19 +01005507
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005508 /*
5509 * Pipe horizontal size must be even in:
5510 * - DVO ganged mode
5511 * - LVDS dual channel mode
5512 * - Double wide pipe
5513 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005514 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005515 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5516 pipe_config->pipe_src_w &= ~1;
5517
Damien Lespiau8693a822013-05-03 18:48:11 +01005518 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5519 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005520 */
5521 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5522 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005523 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005524
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005525 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005526 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005527 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005528 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5529 * for lvds. */
5530 pipe_config->pipe_bpp = 8*3;
5531 }
5532
Damien Lespiauf5adf942013-06-24 18:29:34 +01005533 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005534 hsw_compute_ips_config(crtc, pipe_config);
5535
Daniel Vetter877d48d2013-04-19 11:24:43 +02005536 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005537 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005538
Daniel Vettere29c22c2013-02-21 00:00:16 +01005539 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005540}
5541
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005542static int valleyview_get_display_clock_speed(struct drm_device *dev)
5543{
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005544 struct drm_i915_private *dev_priv = dev->dev_private;
5545 int vco = valleyview_get_vco(dev_priv);
5546 u32 val;
5547 int divider;
5548
Ville Syrjäläd49a3402014-06-28 02:03:58 +03005549 /* FIXME: Punit isn't quite ready yet */
5550 if (IS_CHERRYVIEW(dev))
5551 return 400000;
5552
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005553 mutex_lock(&dev_priv->dpio_lock);
5554 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5555 mutex_unlock(&dev_priv->dpio_lock);
5556
5557 divider = val & DISPLAY_FREQUENCY_VALUES;
5558
Ville Syrjälä7d007f42014-06-13 13:37:53 +03005559 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5560 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5561 "cdclk change in progress\n");
5562
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005563 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005564}
5565
Jesse Barnese70236a2009-09-21 10:42:27 -07005566static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005567{
Jesse Barnese70236a2009-09-21 10:42:27 -07005568 return 400000;
5569}
Jesse Barnes79e53942008-11-07 14:24:08 -08005570
Jesse Barnese70236a2009-09-21 10:42:27 -07005571static int i915_get_display_clock_speed(struct drm_device *dev)
5572{
5573 return 333000;
5574}
Jesse Barnes79e53942008-11-07 14:24:08 -08005575
Jesse Barnese70236a2009-09-21 10:42:27 -07005576static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5577{
5578 return 200000;
5579}
Jesse Barnes79e53942008-11-07 14:24:08 -08005580
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005581static int pnv_get_display_clock_speed(struct drm_device *dev)
5582{
5583 u16 gcfgc = 0;
5584
5585 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5586
5587 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5588 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5589 return 267000;
5590 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5591 return 333000;
5592 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5593 return 444000;
5594 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5595 return 200000;
5596 default:
5597 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5598 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5599 return 133000;
5600 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5601 return 167000;
5602 }
5603}
5604
Jesse Barnese70236a2009-09-21 10:42:27 -07005605static int i915gm_get_display_clock_speed(struct drm_device *dev)
5606{
5607 u16 gcfgc = 0;
5608
5609 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5610
5611 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005612 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005613 else {
5614 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5615 case GC_DISPLAY_CLOCK_333_MHZ:
5616 return 333000;
5617 default:
5618 case GC_DISPLAY_CLOCK_190_200_MHZ:
5619 return 190000;
5620 }
5621 }
5622}
Jesse Barnes79e53942008-11-07 14:24:08 -08005623
Jesse Barnese70236a2009-09-21 10:42:27 -07005624static int i865_get_display_clock_speed(struct drm_device *dev)
5625{
5626 return 266000;
5627}
5628
5629static int i855_get_display_clock_speed(struct drm_device *dev)
5630{
5631 u16 hpllcc = 0;
5632 /* Assume that the hardware is in the high speed state. This
5633 * should be the default.
5634 */
5635 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5636 case GC_CLOCK_133_200:
5637 case GC_CLOCK_100_200:
5638 return 200000;
5639 case GC_CLOCK_166_250:
5640 return 250000;
5641 case GC_CLOCK_100_133:
5642 return 133000;
5643 }
5644
5645 /* Shouldn't happen */
5646 return 0;
5647}
5648
5649static int i830_get_display_clock_speed(struct drm_device *dev)
5650{
5651 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005652}
5653
Zhenyu Wang2c072452009-06-05 15:38:42 +08005654static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005655intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005656{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005657 while (*num > DATA_LINK_M_N_MASK ||
5658 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005659 *num >>= 1;
5660 *den >>= 1;
5661 }
5662}
5663
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005664static void compute_m_n(unsigned int m, unsigned int n,
5665 uint32_t *ret_m, uint32_t *ret_n)
5666{
5667 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5668 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5669 intel_reduce_m_n_ratio(ret_m, ret_n);
5670}
5671
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005672void
5673intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5674 int pixel_clock, int link_clock,
5675 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005676{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005677 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005678
5679 compute_m_n(bits_per_pixel * pixel_clock,
5680 link_clock * nlanes * 8,
5681 &m_n->gmch_m, &m_n->gmch_n);
5682
5683 compute_m_n(pixel_clock, link_clock,
5684 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005685}
5686
Chris Wilsona7615032011-01-12 17:04:08 +00005687static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5688{
Jani Nikulad330a952014-01-21 11:24:25 +02005689 if (i915.panel_use_ssc >= 0)
5690 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005691 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005692 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005693}
5694
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005695static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005696{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005697 struct drm_device *dev = crtc->base.dev;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005698 struct drm_i915_private *dev_priv = dev->dev_private;
5699 int refclk;
5700
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005701 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005702 refclk = 100000;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02005703 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005704 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005705 refclk = dev_priv->vbt.lvds_ssc_freq;
5706 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005707 } else if (!IS_GEN2(dev)) {
5708 refclk = 96000;
5709 } else {
5710 refclk = 48000;
5711 }
5712
5713 return refclk;
5714}
5715
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005716static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005717{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005718 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005719}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005720
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005721static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5722{
5723 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005724}
5725
Daniel Vetterf47709a2013-03-28 10:42:02 +01005726static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005727 intel_clock_t *reduced_clock)
5728{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005729 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005730 u32 fp, fp2 = 0;
5731
5732 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005733 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005734 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005735 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005736 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005737 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005738 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005739 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005740 }
5741
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005742 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005743
Daniel Vetterf47709a2013-03-28 10:42:02 +01005744 crtc->lowfreq_avail = false;
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005745 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005746 reduced_clock && i915.powersave) {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005747 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005748 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005749 } else {
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005750 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005751 }
5752}
5753
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005754static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5755 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005756{
5757 u32 reg_val;
5758
5759 /*
5760 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5761 * and set it to a reasonable value instead.
5762 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005763 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005764 reg_val &= 0xffffff00;
5765 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005766 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005767
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005768 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005769 reg_val &= 0x8cffffff;
5770 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005771 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005772
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005773 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005774 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005775 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005776
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005777 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005778 reg_val &= 0x00ffffff;
5779 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005780 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005781}
5782
Daniel Vetterb5518422013-05-03 11:49:48 +02005783static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5784 struct intel_link_m_n *m_n)
5785{
5786 struct drm_device *dev = crtc->base.dev;
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788 int pipe = crtc->pipe;
5789
Daniel Vettere3b95f12013-05-03 11:49:49 +02005790 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5791 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5792 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5793 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005794}
5795
5796static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07005797 struct intel_link_m_n *m_n,
5798 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02005799{
5800 struct drm_device *dev = crtc->base.dev;
5801 struct drm_i915_private *dev_priv = dev->dev_private;
5802 int pipe = crtc->pipe;
5803 enum transcoder transcoder = crtc->config.cpu_transcoder;
5804
5805 if (INTEL_INFO(dev)->gen >= 5) {
5806 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5807 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5808 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5809 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07005810 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5811 * for gen < 8) and if DRRS is supported (to make sure the
5812 * registers are not unnecessarily accessed).
5813 */
5814 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5815 crtc->config.has_drrs) {
5816 I915_WRITE(PIPE_DATA_M2(transcoder),
5817 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5818 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5819 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5820 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5821 }
Daniel Vetterb5518422013-05-03 11:49:48 +02005822 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005823 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5824 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5825 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5826 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005827 }
5828}
5829
Vandana Kannanf769cd22014-08-05 07:51:22 -07005830void intel_dp_set_m_n(struct intel_crtc *crtc)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005831{
5832 if (crtc->config.has_pch_encoder)
5833 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5834 else
Vandana Kannanf769cd22014-08-05 07:51:22 -07005835 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5836 &crtc->config.dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005837}
5838
Ville Syrjäläd288f652014-10-28 13:20:22 +02005839static void vlv_update_pll(struct intel_crtc *crtc,
5840 struct intel_crtc_config *pipe_config)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005841{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005842 u32 dpll, dpll_md;
5843
5844 /*
5845 * Enable DPIO clock input. We should never disable the reference
5846 * clock for pipe B, since VGA hotplug / manual detection depends
5847 * on it.
5848 */
5849 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5850 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5851 /* We should never disable this, set it here for state tracking */
5852 if (crtc->pipe == PIPE_B)
5853 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5854 dpll |= DPLL_VCO_ENABLE;
Ville Syrjäläd288f652014-10-28 13:20:22 +02005855 pipe_config->dpll_hw_state.dpll = dpll;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005856
Ville Syrjäläd288f652014-10-28 13:20:22 +02005857 dpll_md = (pipe_config->pixel_multiplier - 1)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005858 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjäläd288f652014-10-28 13:20:22 +02005859 pipe_config->dpll_hw_state.dpll_md = dpll_md;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005860}
5861
Ville Syrjäläd288f652014-10-28 13:20:22 +02005862static void vlv_prepare_pll(struct intel_crtc *crtc,
5863 const struct intel_crtc_config *pipe_config)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005864{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005865 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005866 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005867 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005868 u32 mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005869 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005870 u32 coreclk, reg_val;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005871
Daniel Vetter09153002012-12-12 14:06:44 +01005872 mutex_lock(&dev_priv->dpio_lock);
5873
Ville Syrjäläd288f652014-10-28 13:20:22 +02005874 bestn = pipe_config->dpll.n;
5875 bestm1 = pipe_config->dpll.m1;
5876 bestm2 = pipe_config->dpll.m2;
5877 bestp1 = pipe_config->dpll.p1;
5878 bestp2 = pipe_config->dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005879
Jesse Barnes89b667f2013-04-18 14:51:36 -07005880 /* See eDP HDMI DPIO driver vbios notes doc */
5881
5882 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005883 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005884 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005885
5886 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005887 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005888
5889 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005890 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005891 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005892 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005893
5894 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005895 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005896
5897 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005898 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5899 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5900 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005901 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005902
5903 /*
5904 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5905 * but we don't support that).
5906 * Note: don't use the DAC post divider as it seems unstable.
5907 */
5908 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005909 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005910
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005911 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005912 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005913
Jesse Barnes89b667f2013-04-18 14:51:36 -07005914 /* Set HBR and RBR LPF coefficients */
Ville Syrjäläd288f652014-10-28 13:20:22 +02005915 if (pipe_config->port_clock == 162000 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005916 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5917 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005918 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03005919 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005920 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005921 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005922 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005923
Daniel Vetter0a888182014-11-03 14:37:38 +01005924 if (crtc->config.has_dp_encoder) {
Jesse Barnes89b667f2013-04-18 14:51:36 -07005925 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005926 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005928 0x0df40000);
5929 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005930 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005931 0x0df70000);
5932 } else { /* HDMI or VGA */
5933 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005934 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005936 0x0df70000);
5937 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005939 0x0df40000);
5940 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005941
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005942 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005943 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005944 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5945 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
Jesse Barnes89b667f2013-04-18 14:51:36 -07005946 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005948
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005950 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005951}
5952
Ville Syrjäläd288f652014-10-28 13:20:22 +02005953static void chv_update_pll(struct intel_crtc *crtc,
5954 struct intel_crtc_config *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005955{
Ville Syrjäläd288f652014-10-28 13:20:22 +02005956 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005957 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5958 DPLL_VCO_ENABLE;
5959 if (crtc->pipe != PIPE_A)
Ville Syrjäläd288f652014-10-28 13:20:22 +02005960 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005961
Ville Syrjäläd288f652014-10-28 13:20:22 +02005962 pipe_config->dpll_hw_state.dpll_md =
5963 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005964}
5965
Ville Syrjäläd288f652014-10-28 13:20:22 +02005966static void chv_prepare_pll(struct intel_crtc *crtc,
5967 const struct intel_crtc_config *pipe_config)
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005968{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005969 struct drm_device *dev = crtc->base.dev;
5970 struct drm_i915_private *dev_priv = dev->dev_private;
5971 int pipe = crtc->pipe;
5972 int dpll_reg = DPLL(crtc->pipe);
5973 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005974 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005975 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5976 int refclk;
5977
Ville Syrjäläd288f652014-10-28 13:20:22 +02005978 bestn = pipe_config->dpll.n;
5979 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5980 bestm1 = pipe_config->dpll.m1;
5981 bestm2 = pipe_config->dpll.m2 >> 22;
5982 bestp1 = pipe_config->dpll.p1;
5983 bestp2 = pipe_config->dpll.p2;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005984
5985 /*
5986 * Enable Refclk and SSC
5987 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005988 I915_WRITE(dpll_reg,
Ville Syrjäläd288f652014-10-28 13:20:22 +02005989 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005990
5991 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005992
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005993 /* p1 and p2 divider */
5994 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5995 5 << DPIO_CHV_S1_DIV_SHIFT |
5996 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5997 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5998 1 << DPIO_CHV_K_DIV_SHIFT);
5999
6000 /* Feedback post-divider - m2 */
6001 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6002
6003 /* Feedback refclk divider - n and m1 */
6004 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6005 DPIO_CHV_M1_DIV_BY_2 |
6006 1 << DPIO_CHV_N_DIV_SHIFT);
6007
6008 /* M2 fraction division */
6009 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6010
6011 /* M2 fraction division enable */
6012 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6013 DPIO_CHV_FRAC_DIV_EN |
6014 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6015
6016 /* Loop filter */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006017 refclk = i9xx_get_refclk(crtc, 0);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006018 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6019 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6020 if (refclk == 100000)
6021 intcoeff = 11;
6022 else if (refclk == 38400)
6023 intcoeff = 10;
6024 else
6025 intcoeff = 9;
6026 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6027 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6028
6029 /* AFC Recal */
6030 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6031 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6032 DPIO_AFC_RECAL);
6033
6034 mutex_unlock(&dev_priv->dpio_lock);
6035}
6036
Ville Syrjäläd288f652014-10-28 13:20:22 +02006037/**
6038 * vlv_force_pll_on - forcibly enable just the PLL
6039 * @dev_priv: i915 private structure
6040 * @pipe: pipe PLL to enable
6041 * @dpll: PLL configuration
6042 *
6043 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6044 * in cases where we need the PLL enabled even when @pipe is not going to
6045 * be enabled.
6046 */
6047void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6048 const struct dpll *dpll)
6049{
6050 struct intel_crtc *crtc =
6051 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6052 struct intel_crtc_config pipe_config = {
6053 .pixel_multiplier = 1,
6054 .dpll = *dpll,
6055 };
6056
6057 if (IS_CHERRYVIEW(dev)) {
6058 chv_update_pll(crtc, &pipe_config);
6059 chv_prepare_pll(crtc, &pipe_config);
6060 chv_enable_pll(crtc, &pipe_config);
6061 } else {
6062 vlv_update_pll(crtc, &pipe_config);
6063 vlv_prepare_pll(crtc, &pipe_config);
6064 vlv_enable_pll(crtc, &pipe_config);
6065 }
6066}
6067
6068/**
6069 * vlv_force_pll_off - forcibly disable just the PLL
6070 * @dev_priv: i915 private structure
6071 * @pipe: pipe PLL to disable
6072 *
6073 * Disable the PLL for @pipe. To be used in cases where we need
6074 * the PLL enabled even when @pipe is not going to be enabled.
6075 */
6076void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6077{
6078 if (IS_CHERRYVIEW(dev))
6079 chv_disable_pll(to_i915(dev), pipe);
6080 else
6081 vlv_disable_pll(to_i915(dev), pipe);
6082}
6083
Daniel Vetterf47709a2013-03-28 10:42:02 +01006084static void i9xx_update_pll(struct intel_crtc *crtc,
6085 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006086 int num_connectors)
6087{
Daniel Vetterf47709a2013-03-28 10:42:02 +01006088 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006089 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006090 u32 dpll;
6091 bool is_sdvo;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006092 struct dpll *clock = &crtc->new_config->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006093
Daniel Vetterf47709a2013-03-28 10:42:02 +01006094 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306095
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006096 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6097 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006098
6099 dpll = DPLL_VGA_MODE_DIS;
6100
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006101 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006102 dpll |= DPLLB_MODE_LVDS;
6103 else
6104 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006105
Daniel Vetteref1b4602013-06-01 17:17:04 +02006106 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006107 dpll |= (crtc->new_config->pixel_multiplier - 1)
Daniel Vetter198a037f2013-04-19 11:14:37 +02006108 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006109 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02006110
6111 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006112 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006113
Daniel Vetter0a888182014-11-03 14:37:38 +01006114 if (crtc->new_config->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006115 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006116
6117 /* compute bitmask from p1 value */
6118 if (IS_PINEVIEW(dev))
6119 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6120 else {
6121 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6122 if (IS_G4X(dev) && reduced_clock)
6123 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6124 }
6125 switch (clock->p2) {
6126 case 5:
6127 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6128 break;
6129 case 7:
6130 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6131 break;
6132 case 10:
6133 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6134 break;
6135 case 14:
6136 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6137 break;
6138 }
6139 if (INTEL_INFO(dev)->gen >= 4)
6140 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6141
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006142 if (crtc->new_config->sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006143 dpll |= PLL_REF_INPUT_TVCLKINBC;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006144 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006145 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6146 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6147 else
6148 dpll |= PLL_REF_INPUT_DREFCLK;
6149
6150 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006151 crtc->new_config->dpll_hw_state.dpll = dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006152
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006153 if (INTEL_INFO(dev)->gen >= 4) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006154 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02006155 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006156 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006157 }
6158}
6159
Daniel Vetterf47709a2013-03-28 10:42:02 +01006160static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01006161 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006162 int num_connectors)
6163{
Daniel Vetterf47709a2013-03-28 10:42:02 +01006164 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006165 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006166 u32 dpll;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006167 struct dpll *clock = &crtc->new_config->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006168
Daniel Vetterf47709a2013-03-28 10:42:02 +01006169 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306170
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006171 dpll = DPLL_VGA_MODE_DIS;
6172
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006173 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006174 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6175 } else {
6176 if (clock->p1 == 2)
6177 dpll |= PLL_P1_DIVIDE_BY_TWO;
6178 else
6179 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6180 if (clock->p2 == 4)
6181 dpll |= PLL_P2_DIVIDE_BY_4;
6182 }
6183
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006184 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
Daniel Vetter4a33e482013-07-06 12:52:05 +02006185 dpll |= DPLL_DVO_2X_MODE;
6186
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006187 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006188 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6189 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6190 else
6191 dpll |= PLL_REF_INPUT_DREFCLK;
6192
6193 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006194 crtc->new_config->dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006195}
6196
Daniel Vetter8a654f32013-06-01 17:16:22 +02006197static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006198{
6199 struct drm_device *dev = intel_crtc->base.dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006202 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02006203 struct drm_display_mode *adjusted_mode =
6204 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02006205 uint32_t crtc_vtotal, crtc_vblank_end;
6206 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006207
6208 /* We need to be careful not to changed the adjusted mode, for otherwise
6209 * the hw state checker will get angry at the mismatch. */
6210 crtc_vtotal = adjusted_mode->crtc_vtotal;
6211 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006212
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006213 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006214 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006215 crtc_vtotal -= 1;
6216 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006217
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006218 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006219 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6220 else
6221 vsyncshift = adjusted_mode->crtc_hsync_start -
6222 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02006223 if (vsyncshift < 0)
6224 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006225 }
6226
6227 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006228 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006229
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006230 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006231 (adjusted_mode->crtc_hdisplay - 1) |
6232 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006233 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006234 (adjusted_mode->crtc_hblank_start - 1) |
6235 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006236 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006237 (adjusted_mode->crtc_hsync_start - 1) |
6238 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6239
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006240 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006241 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006242 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006243 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006244 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006245 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006246 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006247 (adjusted_mode->crtc_vsync_start - 1) |
6248 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6249
Paulo Zanonib5e508d2012-10-24 11:34:43 -02006250 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6251 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6252 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6253 * bits. */
6254 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6255 (pipe == PIPE_B || pipe == PIPE_C))
6256 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6257
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006258 /* pipesrc controls the size that is scaled from, which should
6259 * always be the user's requested size.
6260 */
6261 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03006262 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6263 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006264}
6265
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006266static void intel_get_pipe_timings(struct intel_crtc *crtc,
6267 struct intel_crtc_config *pipe_config)
6268{
6269 struct drm_device *dev = crtc->base.dev;
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6272 uint32_t tmp;
6273
6274 tmp = I915_READ(HTOTAL(cpu_transcoder));
6275 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6276 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6277 tmp = I915_READ(HBLANK(cpu_transcoder));
6278 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6279 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6280 tmp = I915_READ(HSYNC(cpu_transcoder));
6281 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6282 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6283
6284 tmp = I915_READ(VTOTAL(cpu_transcoder));
6285 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6286 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6287 tmp = I915_READ(VBLANK(cpu_transcoder));
6288 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6289 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6290 tmp = I915_READ(VSYNC(cpu_transcoder));
6291 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6292 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6293
6294 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6295 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6296 pipe_config->adjusted_mode.crtc_vtotal += 1;
6297 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6298 }
6299
6300 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03006301 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6302 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6303
6304 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6305 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006306}
6307
Daniel Vetterf6a83282014-02-11 15:28:57 -08006308void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6309 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03006310{
Daniel Vetterf6a83282014-02-11 15:28:57 -08006311 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6312 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6313 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6314 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006315
Daniel Vetterf6a83282014-02-11 15:28:57 -08006316 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6317 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6318 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6319 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006320
Daniel Vetterf6a83282014-02-11 15:28:57 -08006321 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006322
Daniel Vetterf6a83282014-02-11 15:28:57 -08006323 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6324 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006325}
6326
Daniel Vetter84b046f2013-02-19 18:48:54 +01006327static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6328{
6329 struct drm_device *dev = intel_crtc->base.dev;
6330 struct drm_i915_private *dev_priv = dev->dev_private;
6331 uint32_t pipeconf;
6332
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006333 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006334
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03006335 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6336 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6337 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
Daniel Vetter67c72a12013-09-24 11:46:14 +02006338
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006339 if (intel_crtc->config.double_wide)
6340 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006341
Daniel Vetterff9ce462013-04-24 14:57:17 +02006342 /* only g4x and later have fancy bpc/dither controls */
6343 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02006344 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6345 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6346 pipeconf |= PIPECONF_DITHER_EN |
6347 PIPECONF_DITHER_TYPE_SP;
6348
6349 switch (intel_crtc->config.pipe_bpp) {
6350 case 18:
6351 pipeconf |= PIPECONF_6BPC;
6352 break;
6353 case 24:
6354 pipeconf |= PIPECONF_8BPC;
6355 break;
6356 case 30:
6357 pipeconf |= PIPECONF_10BPC;
6358 break;
6359 default:
6360 /* Case prevented by intel_choose_pipe_bpp_dither. */
6361 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01006362 }
6363 }
6364
6365 if (HAS_PIPE_CXSR(dev)) {
6366 if (intel_crtc->lowfreq_avail) {
6367 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6368 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6369 } else {
6370 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01006371 }
6372 }
6373
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006374 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6375 if (INTEL_INFO(dev)->gen < 4 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006376 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006377 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6378 else
6379 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6380 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01006381 pipeconf |= PIPECONF_PROGRESSIVE;
6382
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006383 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6384 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03006385
Daniel Vetter84b046f2013-02-19 18:48:54 +01006386 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6387 POSTING_READ(PIPECONF(intel_crtc->pipe));
6388}
6389
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +02006390static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08006391{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006392 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08006393 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholtc751ce42010-03-25 11:48:48 -07006394 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07006395 intel_clock_t clock, reduced_clock;
Daniel Vettera16af7212013-04-30 14:01:44 +02006396 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006397 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01006398 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08006399 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08006400
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006401 for_each_intel_encoder(dev, encoder) {
6402 if (encoder->new_crtc != crtc)
6403 continue;
6404
Chris Wilson5eddb702010-09-11 13:48:45 +01006405 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006406 case INTEL_OUTPUT_LVDS:
6407 is_lvds = true;
6408 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006409 case INTEL_OUTPUT_DSI:
6410 is_dsi = true;
6411 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02006412 default:
6413 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006414 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006415
Eric Anholtc751ce42010-03-25 11:48:48 -07006416 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08006417 }
6418
Jani Nikulaf2335332013-09-13 11:03:09 +03006419 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02006420 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006421
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006422 if (!crtc->new_config->clock_set) {
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006423 refclk = i9xx_get_refclk(crtc, num_connectors);
Jani Nikulaf2335332013-09-13 11:03:09 +03006424
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006425 /*
6426 * Returns a set of divisors for the desired target clock with
6427 * the given refclk, or FALSE. The returned values represent
6428 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6429 * 2) / p1 / p2.
6430 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006431 limit = intel_limit(crtc, refclk);
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006432 ok = dev_priv->display.find_dpll(limit, crtc,
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006433 crtc->new_config->port_clock,
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006434 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03006435 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006436 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6437 return -EINVAL;
6438 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006439
Jani Nikulaf2335332013-09-13 11:03:09 +03006440 if (is_lvds && dev_priv->lvds_downclock_avail) {
6441 /*
6442 * Ensure we match the reduced clock's P to the target
6443 * clock. If the clocks don't match, we can't switch
6444 * the display clock by using the FP0/FP1. In such case
6445 * we will disable the LVDS downclock feature.
6446 */
6447 has_reduced_clock =
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006448 dev_priv->display.find_dpll(limit, crtc,
Jani Nikulaf2335332013-09-13 11:03:09 +03006449 dev_priv->lvds_downclock,
6450 refclk, &clock,
6451 &reduced_clock);
6452 }
6453 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006454 crtc->new_config->dpll.n = clock.n;
6455 crtc->new_config->dpll.m1 = clock.m1;
6456 crtc->new_config->dpll.m2 = clock.m2;
6457 crtc->new_config->dpll.p1 = clock.p1;
6458 crtc->new_config->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01006459 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006460
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006461 if (IS_GEN2(dev)) {
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006462 i8xx_update_pll(crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306463 has_reduced_clock ? &reduced_clock : NULL,
6464 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006465 } else if (IS_CHERRYVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006466 chv_update_pll(crtc, crtc->new_config);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006467 } else if (IS_VALLEYVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006468 vlv_update_pll(crtc, crtc->new_config);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006469 } else {
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006470 i9xx_update_pll(crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006471 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006472 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006473 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006474
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006475 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006476}
6477
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006478static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6479 struct intel_crtc_config *pipe_config)
6480{
6481 struct drm_device *dev = crtc->base.dev;
6482 struct drm_i915_private *dev_priv = dev->dev_private;
6483 uint32_t tmp;
6484
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006485 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6486 return;
6487
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006488 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006489 if (!(tmp & PFIT_ENABLE))
6490 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006491
Daniel Vetter06922822013-07-11 13:35:40 +02006492 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006493 if (INTEL_INFO(dev)->gen < 4) {
6494 if (crtc->pipe != PIPE_B)
6495 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006496 } else {
6497 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6498 return;
6499 }
6500
Daniel Vetter06922822013-07-11 13:35:40 +02006501 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006502 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6503 if (INTEL_INFO(dev)->gen < 5)
6504 pipe_config->gmch_pfit.lvds_border_bits =
6505 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6506}
6507
Jesse Barnesacbec812013-09-20 11:29:32 -07006508static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6509 struct intel_crtc_config *pipe_config)
6510{
6511 struct drm_device *dev = crtc->base.dev;
6512 struct drm_i915_private *dev_priv = dev->dev_private;
6513 int pipe = pipe_config->cpu_transcoder;
6514 intel_clock_t clock;
6515 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006516 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006517
Shobhit Kumarf573de52014-07-30 20:32:37 +05306518 /* In case of MIPI DPLL will not even be used */
6519 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6520 return;
6521
Jesse Barnesacbec812013-09-20 11:29:32 -07006522 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006523 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006524 mutex_unlock(&dev_priv->dpio_lock);
6525
6526 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6527 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6528 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6529 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6530 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6531
Ville Syrjäläf6466282013-10-14 14:50:31 +03006532 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006533
Ville Syrjäläf6466282013-10-14 14:50:31 +03006534 /* clock.dot is the fast clock */
6535 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006536}
6537
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006538static void i9xx_get_plane_config(struct intel_crtc *crtc,
6539 struct intel_plane_config *plane_config)
6540{
6541 struct drm_device *dev = crtc->base.dev;
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543 u32 val, base, offset;
6544 int pipe = crtc->pipe, plane = crtc->plane;
6545 int fourcc, pixel_format;
6546 int aligned_height;
6547
Dave Airlie66e514c2014-04-03 07:51:54 +10006548 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6549 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006550 DRM_DEBUG_KMS("failed to alloc fb\n");
6551 return;
6552 }
6553
6554 val = I915_READ(DSPCNTR(plane));
6555
6556 if (INTEL_INFO(dev)->gen >= 4)
6557 if (val & DISPPLANE_TILED)
6558 plane_config->tiled = true;
6559
6560 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6561 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006562 crtc->base.primary->fb->pixel_format = fourcc;
6563 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006564 drm_format_plane_cpp(fourcc, 0) * 8;
6565
6566 if (INTEL_INFO(dev)->gen >= 4) {
6567 if (plane_config->tiled)
6568 offset = I915_READ(DSPTILEOFF(plane));
6569 else
6570 offset = I915_READ(DSPLINOFF(plane));
6571 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6572 } else {
6573 base = I915_READ(DSPADDR(plane));
6574 }
6575 plane_config->base = base;
6576
6577 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006578 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6579 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006580
6581 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01006582 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006583
Dave Airlie66e514c2014-04-03 07:51:54 +10006584 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006585 plane_config->tiled);
6586
Fabian Frederick1267a262014-07-01 20:39:41 +02006587 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6588 aligned_height);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006589
6590 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006591 pipe, plane, crtc->base.primary->fb->width,
6592 crtc->base.primary->fb->height,
6593 crtc->base.primary->fb->bits_per_pixel, base,
6594 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006595 plane_config->size);
6596
6597}
6598
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006599static void chv_crtc_clock_get(struct intel_crtc *crtc,
6600 struct intel_crtc_config *pipe_config)
6601{
6602 struct drm_device *dev = crtc->base.dev;
6603 struct drm_i915_private *dev_priv = dev->dev_private;
6604 int pipe = pipe_config->cpu_transcoder;
6605 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6606 intel_clock_t clock;
6607 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6608 int refclk = 100000;
6609
6610 mutex_lock(&dev_priv->dpio_lock);
6611 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6612 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6613 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6614 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6615 mutex_unlock(&dev_priv->dpio_lock);
6616
6617 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6618 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6619 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6620 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6621 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6622
6623 chv_clock(refclk, &clock);
6624
6625 /* clock.dot is the fast clock */
6626 pipe_config->port_clock = clock.dot / 5;
6627}
6628
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006629static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6630 struct intel_crtc_config *pipe_config)
6631{
6632 struct drm_device *dev = crtc->base.dev;
6633 struct drm_i915_private *dev_priv = dev->dev_private;
6634 uint32_t tmp;
6635
Daniel Vetterf458ebb2014-09-30 10:56:39 +02006636 if (!intel_display_power_is_enabled(dev_priv,
6637 POWER_DOMAIN_PIPE(crtc->pipe)))
Imre Deakb5482bd2014-03-05 16:20:55 +02006638 return false;
6639
Daniel Vettere143a212013-07-04 12:01:15 +02006640 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006641 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006642
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006643 tmp = I915_READ(PIPECONF(crtc->pipe));
6644 if (!(tmp & PIPECONF_ENABLE))
6645 return false;
6646
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006647 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6648 switch (tmp & PIPECONF_BPC_MASK) {
6649 case PIPECONF_6BPC:
6650 pipe_config->pipe_bpp = 18;
6651 break;
6652 case PIPECONF_8BPC:
6653 pipe_config->pipe_bpp = 24;
6654 break;
6655 case PIPECONF_10BPC:
6656 pipe_config->pipe_bpp = 30;
6657 break;
6658 default:
6659 break;
6660 }
6661 }
6662
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006663 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6664 pipe_config->limited_color_range = true;
6665
Ville Syrjälä282740f2013-09-04 18:30:03 +03006666 if (INTEL_INFO(dev)->gen < 4)
6667 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6668
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006669 intel_get_pipe_timings(crtc, pipe_config);
6670
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006671 i9xx_get_pfit_config(crtc, pipe_config);
6672
Daniel Vetter6c49f242013-06-06 12:45:25 +02006673 if (INTEL_INFO(dev)->gen >= 4) {
6674 tmp = I915_READ(DPLL_MD(crtc->pipe));
6675 pipe_config->pixel_multiplier =
6676 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6677 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006678 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006679 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6680 tmp = I915_READ(DPLL(crtc->pipe));
6681 pipe_config->pixel_multiplier =
6682 ((tmp & SDVO_MULTIPLIER_MASK)
6683 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6684 } else {
6685 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6686 * port and will be fixed up in the encoder->get_config
6687 * function. */
6688 pipe_config->pixel_multiplier = 1;
6689 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006690 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6691 if (!IS_VALLEYVIEW(dev)) {
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03006692 /*
6693 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6694 * on 830. Filter it out here so that we don't
6695 * report errors due to that.
6696 */
6697 if (IS_I830(dev))
6698 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6699
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006700 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6701 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006702 } else {
6703 /* Mask out read-only status bits. */
6704 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6705 DPLL_PORTC_READY_MASK |
6706 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006707 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006708
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006709 if (IS_CHERRYVIEW(dev))
6710 chv_crtc_clock_get(crtc, pipe_config);
6711 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006712 vlv_crtc_clock_get(crtc, pipe_config);
6713 else
6714 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006715
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006716 return true;
6717}
6718
Paulo Zanonidde86e22012-12-01 12:04:25 -02006719static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006720{
6721 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006722 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006723 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006724 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006725 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006726 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006727 bool has_ck505 = false;
6728 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006729
6730 /* We need to take the global config into account */
Damien Lespiaub2784e12014-08-05 11:29:37 +01006731 for_each_intel_encoder(dev, encoder) {
Keith Packard199e5d72011-09-22 12:01:57 -07006732 switch (encoder->type) {
6733 case INTEL_OUTPUT_LVDS:
6734 has_panel = true;
6735 has_lvds = true;
6736 break;
6737 case INTEL_OUTPUT_EDP:
6738 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006739 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006740 has_cpu_edp = true;
6741 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02006742 default:
6743 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006744 }
6745 }
6746
Keith Packard99eb6a02011-09-26 14:29:12 -07006747 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006748 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006749 can_ssc = has_ck505;
6750 } else {
6751 has_ck505 = false;
6752 can_ssc = true;
6753 }
6754
Imre Deak2de69052013-05-08 13:14:04 +03006755 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6756 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006757
6758 /* Ironlake: try to setup display ref clock before DPLL
6759 * enabling. This is only under driver's control after
6760 * PCH B stepping, previous chipset stepping should be
6761 * ignoring this setting.
6762 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006763 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006764
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006765 /* As we must carefully and slowly disable/enable each source in turn,
6766 * compute the final state we want first and check if we need to
6767 * make any changes at all.
6768 */
6769 final = val;
6770 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006771 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006772 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006773 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006774 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6775
6776 final &= ~DREF_SSC_SOURCE_MASK;
6777 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6778 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006779
Keith Packard199e5d72011-09-22 12:01:57 -07006780 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006781 final |= DREF_SSC_SOURCE_ENABLE;
6782
6783 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6784 final |= DREF_SSC1_ENABLE;
6785
6786 if (has_cpu_edp) {
6787 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6788 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6789 else
6790 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6791 } else
6792 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6793 } else {
6794 final |= DREF_SSC_SOURCE_DISABLE;
6795 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6796 }
6797
6798 if (final == val)
6799 return;
6800
6801 /* Always enable nonspread source */
6802 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6803
6804 if (has_ck505)
6805 val |= DREF_NONSPREAD_CK505_ENABLE;
6806 else
6807 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6808
6809 if (has_panel) {
6810 val &= ~DREF_SSC_SOURCE_MASK;
6811 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006812
Keith Packard199e5d72011-09-22 12:01:57 -07006813 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006814 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006815 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006816 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006817 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006818 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006819
6820 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006821 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006822 POSTING_READ(PCH_DREF_CONTROL);
6823 udelay(200);
6824
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006825 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006826
6827 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006828 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006829 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006830 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006831 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006832 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006833 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006834 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006835 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006836
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006837 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006838 POSTING_READ(PCH_DREF_CONTROL);
6839 udelay(200);
6840 } else {
6841 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6842
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006843 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006844
6845 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006846 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006847
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006848 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006849 POSTING_READ(PCH_DREF_CONTROL);
6850 udelay(200);
6851
6852 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006853 val &= ~DREF_SSC_SOURCE_MASK;
6854 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006855
6856 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006857 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006858
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006859 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006860 POSTING_READ(PCH_DREF_CONTROL);
6861 udelay(200);
6862 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006863
6864 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006865}
6866
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006867static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006868{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006869 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006870
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006871 tmp = I915_READ(SOUTH_CHICKEN2);
6872 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6873 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006874
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006875 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6876 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6877 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006878
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006879 tmp = I915_READ(SOUTH_CHICKEN2);
6880 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6881 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006882
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006883 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6884 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6885 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006886}
6887
6888/* WaMPhyProgramming:hsw */
6889static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6890{
6891 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006892
6893 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6894 tmp &= ~(0xFF << 24);
6895 tmp |= (0x12 << 24);
6896 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6897
Paulo Zanonidde86e22012-12-01 12:04:25 -02006898 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6899 tmp |= (1 << 11);
6900 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6901
6902 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6903 tmp |= (1 << 11);
6904 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6905
Paulo Zanonidde86e22012-12-01 12:04:25 -02006906 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6907 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6908 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6909
6910 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6911 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6912 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6913
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006914 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6915 tmp &= ~(7 << 13);
6916 tmp |= (5 << 13);
6917 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006918
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006919 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6920 tmp &= ~(7 << 13);
6921 tmp |= (5 << 13);
6922 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006923
6924 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6925 tmp &= ~0xFF;
6926 tmp |= 0x1C;
6927 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6928
6929 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6930 tmp &= ~0xFF;
6931 tmp |= 0x1C;
6932 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6933
6934 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6935 tmp &= ~(0xFF << 16);
6936 tmp |= (0x1C << 16);
6937 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6938
6939 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6940 tmp &= ~(0xFF << 16);
6941 tmp |= (0x1C << 16);
6942 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6943
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006944 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6945 tmp |= (1 << 27);
6946 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006947
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006948 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6949 tmp |= (1 << 27);
6950 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006951
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006952 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6953 tmp &= ~(0xF << 28);
6954 tmp |= (4 << 28);
6955 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006956
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006957 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6958 tmp &= ~(0xF << 28);
6959 tmp |= (4 << 28);
6960 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006961}
6962
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006963/* Implements 3 different sequences from BSpec chapter "Display iCLK
6964 * Programming" based on the parameters passed:
6965 * - Sequence to enable CLKOUT_DP
6966 * - Sequence to enable CLKOUT_DP without spread
6967 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6968 */
6969static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6970 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006971{
6972 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006973 uint32_t reg, tmp;
6974
6975 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6976 with_spread = true;
6977 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6978 with_fdi, "LP PCH doesn't have FDI\n"))
6979 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006980
6981 mutex_lock(&dev_priv->dpio_lock);
6982
6983 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6984 tmp &= ~SBI_SSCCTL_DISABLE;
6985 tmp |= SBI_SSCCTL_PATHALT;
6986 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6987
6988 udelay(24);
6989
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006990 if (with_spread) {
6991 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6992 tmp &= ~SBI_SSCCTL_PATHALT;
6993 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006994
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006995 if (with_fdi) {
6996 lpt_reset_fdi_mphy(dev_priv);
6997 lpt_program_fdi_mphy(dev_priv);
6998 }
6999 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02007000
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03007001 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7002 SBI_GEN0 : SBI_DBUFF0;
7003 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7004 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7005 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01007006
7007 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02007008}
7009
Paulo Zanoni47701c32013-07-23 11:19:25 -03007010/* Sequence to disable CLKOUT_DP */
7011static void lpt_disable_clkout_dp(struct drm_device *dev)
7012{
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 uint32_t reg, tmp;
7015
7016 mutex_lock(&dev_priv->dpio_lock);
7017
7018 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7019 SBI_GEN0 : SBI_DBUFF0;
7020 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7021 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7022 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7023
7024 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7025 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7026 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7027 tmp |= SBI_SSCCTL_PATHALT;
7028 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7029 udelay(32);
7030 }
7031 tmp |= SBI_SSCCTL_DISABLE;
7032 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7033 }
7034
7035 mutex_unlock(&dev_priv->dpio_lock);
7036}
7037
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007038static void lpt_init_pch_refclk(struct drm_device *dev)
7039{
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007040 struct intel_encoder *encoder;
7041 bool has_vga = false;
7042
Damien Lespiaub2784e12014-08-05 11:29:37 +01007043 for_each_intel_encoder(dev, encoder) {
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007044 switch (encoder->type) {
7045 case INTEL_OUTPUT_ANALOG:
7046 has_vga = true;
7047 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007048 default:
7049 break;
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007050 }
7051 }
7052
Paulo Zanoni47701c32013-07-23 11:19:25 -03007053 if (has_vga)
7054 lpt_enable_clkout_dp(dev, true, true);
7055 else
7056 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007057}
7058
Paulo Zanonidde86e22012-12-01 12:04:25 -02007059/*
7060 * Initialize reference clocks when the driver loads
7061 */
7062void intel_init_pch_refclk(struct drm_device *dev)
7063{
7064 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7065 ironlake_init_pch_refclk(dev);
7066 else if (HAS_PCH_LPT(dev))
7067 lpt_init_pch_refclk(dev);
7068}
7069
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007070static int ironlake_get_refclk(struct drm_crtc *crtc)
7071{
7072 struct drm_device *dev = crtc->dev;
7073 struct drm_i915_private *dev_priv = dev->dev_private;
7074 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007075 int num_connectors = 0;
7076 bool is_lvds = false;
7077
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007078 for_each_intel_encoder(dev, encoder) {
7079 if (encoder->new_crtc != to_intel_crtc(crtc))
7080 continue;
7081
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007082 switch (encoder->type) {
7083 case INTEL_OUTPUT_LVDS:
7084 is_lvds = true;
7085 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007086 default:
7087 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007088 }
7089 num_connectors++;
7090 }
7091
7092 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007093 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03007094 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007095 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007096 }
7097
7098 return 120000;
7099}
7100
Daniel Vetter6ff93602013-04-19 11:24:36 +02007101static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03007102{
7103 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7105 int pipe = intel_crtc->pipe;
7106 uint32_t val;
7107
Daniel Vetter78114072013-06-13 00:54:57 +02007108 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03007109
Daniel Vetter965e0c42013-03-27 00:44:57 +01007110 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03007111 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007112 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007113 break;
7114 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007115 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007116 break;
7117 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007118 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007119 break;
7120 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007121 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007122 break;
7123 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03007124 /* Case prevented by intel_choose_pipe_bpp_dither. */
7125 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03007126 }
7127
Daniel Vetterd8b32242013-04-25 17:54:44 +02007128 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03007129 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7130
Daniel Vetter6ff93602013-04-19 11:24:36 +02007131 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03007132 val |= PIPECONF_INTERLACED_ILK;
7133 else
7134 val |= PIPECONF_PROGRESSIVE;
7135
Daniel Vetter50f3b012013-03-27 00:44:56 +01007136 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02007137 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02007138
Paulo Zanonic8203562012-09-12 10:06:29 -03007139 I915_WRITE(PIPECONF(pipe), val);
7140 POSTING_READ(PIPECONF(pipe));
7141}
7142
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007143/*
7144 * Set up the pipe CSC unit.
7145 *
7146 * Currently only full range RGB to limited range RGB conversion
7147 * is supported, but eventually this should handle various
7148 * RGB<->YCbCr scenarios as well.
7149 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01007150static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007151{
7152 struct drm_device *dev = crtc->dev;
7153 struct drm_i915_private *dev_priv = dev->dev_private;
7154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7155 int pipe = intel_crtc->pipe;
7156 uint16_t coeff = 0x7800; /* 1.0 */
7157
7158 /*
7159 * TODO: Check what kind of values actually come out of the pipe
7160 * with these coeff/postoff values and adjust to get the best
7161 * accuracy. Perhaps we even need to take the bpc value into
7162 * consideration.
7163 */
7164
Daniel Vetter50f3b012013-03-27 00:44:56 +01007165 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007166 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7167
7168 /*
7169 * GY/GU and RY/RU should be the other way around according
7170 * to BSpec, but reality doesn't agree. Just set them up in
7171 * a way that results in the correct picture.
7172 */
7173 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7174 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7175
7176 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7177 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7178
7179 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7180 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7181
7182 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7183 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7184 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7185
7186 if (INTEL_INFO(dev)->gen > 6) {
7187 uint16_t postoff = 0;
7188
Daniel Vetter50f3b012013-03-27 00:44:56 +01007189 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02007190 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007191
7192 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7193 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7194 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7195
7196 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7197 } else {
7198 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7199
Daniel Vetter50f3b012013-03-27 00:44:56 +01007200 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007201 mode |= CSC_BLACK_SCREEN_OFFSET;
7202
7203 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7204 }
7205}
7206
Daniel Vetter6ff93602013-04-19 11:24:36 +02007207static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007208{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007209 struct drm_device *dev = crtc->dev;
7210 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007212 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02007213 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007214 uint32_t val;
7215
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02007216 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007217
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007218 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007219 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7220
Daniel Vetter6ff93602013-04-19 11:24:36 +02007221 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007222 val |= PIPECONF_INTERLACED_ILK;
7223 else
7224 val |= PIPECONF_PROGRESSIVE;
7225
Paulo Zanoni702e7a52012-10-23 18:29:59 -02007226 I915_WRITE(PIPECONF(cpu_transcoder), val);
7227 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02007228
7229 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7230 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007231
Satheeshakrishna M3cdf1222014-04-08 15:46:53 +05307232 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007233 val = 0;
7234
7235 switch (intel_crtc->config.pipe_bpp) {
7236 case 18:
7237 val |= PIPEMISC_DITHER_6_BPC;
7238 break;
7239 case 24:
7240 val |= PIPEMISC_DITHER_8_BPC;
7241 break;
7242 case 30:
7243 val |= PIPEMISC_DITHER_10_BPC;
7244 break;
7245 case 36:
7246 val |= PIPEMISC_DITHER_12_BPC;
7247 break;
7248 default:
7249 /* Case prevented by pipe_config_set_bpp. */
7250 BUG();
7251 }
7252
7253 if (intel_crtc->config.dither)
7254 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7255
7256 I915_WRITE(PIPEMISC(pipe), val);
7257 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007258}
7259
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007260static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007261 intel_clock_t *clock,
7262 bool *has_reduced_clock,
7263 intel_clock_t *reduced_clock)
7264{
7265 struct drm_device *dev = crtc->dev;
7266 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007268 int refclk;
7269 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02007270 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007271
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007272 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007273
7274 refclk = ironlake_get_refclk(crtc);
7275
7276 /*
7277 * Returns a set of divisors for the desired target clock with the given
7278 * refclk, or FALSE. The returned values represent the clock equation:
7279 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7280 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007281 limit = intel_limit(intel_crtc, refclk);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007282 ret = dev_priv->display.find_dpll(limit, intel_crtc,
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007283 intel_crtc->new_config->port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02007284 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007285 if (!ret)
7286 return false;
7287
7288 if (is_lvds && dev_priv->lvds_downclock_avail) {
7289 /*
7290 * Ensure we match the reduced clock's P to the target clock.
7291 * If the clocks don't match, we can't switch the display clock
7292 * by using the FP0/FP1. In such case we will disable the LVDS
7293 * downclock feature.
7294 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02007295 *has_reduced_clock =
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007296 dev_priv->display.find_dpll(limit, intel_crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +02007297 dev_priv->lvds_downclock,
7298 refclk, clock,
7299 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007300 }
7301
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007302 return true;
7303}
7304
Paulo Zanonid4b19312012-11-29 11:29:32 -02007305int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7306{
7307 /*
7308 * Account for spread spectrum to avoid
7309 * oversubscribing the link. Max center spread
7310 * is 2.5%; use 5% for safety's sake.
7311 */
7312 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02007313 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02007314}
7315
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007316static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02007317{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007318 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007319}
7320
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007321static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007322 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007323 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007324{
7325 struct drm_crtc *crtc = &intel_crtc->base;
7326 struct drm_device *dev = crtc->dev;
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7328 struct intel_encoder *intel_encoder;
7329 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01007330 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02007331 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007332
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007333 for_each_intel_encoder(dev, intel_encoder) {
7334 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7335 continue;
7336
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007337 switch (intel_encoder->type) {
7338 case INTEL_OUTPUT_LVDS:
7339 is_lvds = true;
7340 break;
7341 case INTEL_OUTPUT_SDVO:
7342 case INTEL_OUTPUT_HDMI:
7343 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007344 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007345 default:
7346 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007347 }
7348
7349 num_connectors++;
7350 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007351
Chris Wilsonc1858122010-12-03 21:35:48 +00007352 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07007353 factor = 21;
7354 if (is_lvds) {
7355 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007356 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02007357 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07007358 factor = 25;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007359 } else if (intel_crtc->new_config->sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07007360 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00007361
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007362 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02007363 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00007364
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007365 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7366 *fp2 |= FP_CB_TUNE;
7367
Chris Wilson5eddb702010-09-11 13:48:45 +01007368 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08007369
Eric Anholta07d6782011-03-30 13:01:08 -07007370 if (is_lvds)
7371 dpll |= DPLLB_MODE_LVDS;
7372 else
7373 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007374
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007375 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02007376 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007377
7378 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007379 dpll |= DPLL_SDVO_HIGH_SPEED;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007380 if (intel_crtc->new_config->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007381 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08007382
Eric Anholta07d6782011-03-30 13:01:08 -07007383 /* compute bitmask from p1 value */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007384 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007385 /* also FPA1 */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007386 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007387
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007388 switch (intel_crtc->new_config->dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07007389 case 5:
7390 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7391 break;
7392 case 7:
7393 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7394 break;
7395 case 10:
7396 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7397 break;
7398 case 14:
7399 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7400 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007401 }
7402
Daniel Vetterb4c09f32013-04-30 14:01:42 +02007403 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05007404 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08007405 else
7406 dpll |= PLL_REF_INPUT_DREFCLK;
7407
Daniel Vetter959e16d2013-06-05 13:34:21 +02007408 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007409}
7410
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02007411static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08007412{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007413 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007414 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007415 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03007416 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01007417 bool is_lvds = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007418 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007419
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007420 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
Jesse Barnes79e53942008-11-07 14:24:08 -08007421
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007422 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7423 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7424
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007425 ok = ironlake_compute_clocks(&crtc->base, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007426 &has_reduced_clock, &reduced_clock);
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007427 if (!ok && !crtc->new_config->clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007428 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7429 return -EINVAL;
7430 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01007431 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007432 if (!crtc->new_config->clock_set) {
7433 crtc->new_config->dpll.n = clock.n;
7434 crtc->new_config->dpll.m1 = clock.m1;
7435 crtc->new_config->dpll.m2 = clock.m2;
7436 crtc->new_config->dpll.p1 = clock.p1;
7437 crtc->new_config->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01007438 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007439
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007440 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007441 if (crtc->new_config->has_pch_encoder) {
7442 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007443 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007444 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007445
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007446 dpll = ironlake_compute_dpll(crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007447 &fp, &reduced_clock,
7448 has_reduced_clock ? &fp2 : NULL);
7449
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007450 crtc->new_config->dpll_hw_state.dpll = dpll;
7451 crtc->new_config->dpll_hw_state.fp0 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007452 if (has_reduced_clock)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007453 crtc->new_config->dpll_hw_state.fp1 = fp2;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007454 else
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007455 crtc->new_config->dpll_hw_state.fp1 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007456
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007457 pll = intel_get_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007458 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03007459 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007460 pipe_name(crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07007461 return -EINVAL;
7462 }
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02007463 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007464
Jani Nikulad330a952014-01-21 11:24:25 +02007465 if (is_lvds && has_reduced_clock && i915.powersave)
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007466 crtc->lowfreq_avail = true;
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007467 else
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007468 crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007469
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007470 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007471}
7472
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007473static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7474 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007475{
7476 struct drm_device *dev = crtc->base.dev;
7477 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007478 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007479
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007480 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7481 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7482 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7483 & ~TU_SIZE_MASK;
7484 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7485 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7486 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7487}
7488
7489static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7490 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007491 struct intel_link_m_n *m_n,
7492 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007493{
7494 struct drm_device *dev = crtc->base.dev;
7495 struct drm_i915_private *dev_priv = dev->dev_private;
7496 enum pipe pipe = crtc->pipe;
7497
7498 if (INTEL_INFO(dev)->gen >= 5) {
7499 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7500 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7501 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7502 & ~TU_SIZE_MASK;
7503 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7504 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7505 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007506 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7507 * gen < 8) and if DRRS is supported (to make sure the
7508 * registers are not unnecessarily read).
7509 */
7510 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7511 crtc->config.has_drrs) {
7512 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7513 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7514 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7515 & ~TU_SIZE_MASK;
7516 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7517 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7518 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7519 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007520 } else {
7521 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7522 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7523 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7524 & ~TU_SIZE_MASK;
7525 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7526 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7527 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7528 }
7529}
7530
7531void intel_dp_get_m_n(struct intel_crtc *crtc,
7532 struct intel_crtc_config *pipe_config)
7533{
7534 if (crtc->config.has_pch_encoder)
7535 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7536 else
7537 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007538 &pipe_config->dp_m_n,
7539 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007540}
7541
Daniel Vetter72419202013-04-04 13:28:53 +02007542static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7543 struct intel_crtc_config *pipe_config)
7544{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007545 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007546 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02007547}
7548
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007549static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7550 struct intel_crtc_config *pipe_config)
7551{
7552 struct drm_device *dev = crtc->base.dev;
7553 struct drm_i915_private *dev_priv = dev->dev_private;
7554 uint32_t tmp;
7555
7556 tmp = I915_READ(PF_CTL(crtc->pipe));
7557
7558 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007559 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007560 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7561 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007562
7563 /* We currently do not free assignements of panel fitters on
7564 * ivb/hsw (since we don't use the higher upscaling modes which
7565 * differentiates them) so just WARN about this case for now. */
7566 if (IS_GEN7(dev)) {
7567 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7568 PF_PIPE_SEL_IVB(crtc->pipe));
7569 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007570 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007571}
7572
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007573static void ironlake_get_plane_config(struct intel_crtc *crtc,
7574 struct intel_plane_config *plane_config)
7575{
7576 struct drm_device *dev = crtc->base.dev;
7577 struct drm_i915_private *dev_priv = dev->dev_private;
7578 u32 val, base, offset;
7579 int pipe = crtc->pipe, plane = crtc->plane;
7580 int fourcc, pixel_format;
7581 int aligned_height;
7582
Dave Airlie66e514c2014-04-03 07:51:54 +10007583 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7584 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007585 DRM_DEBUG_KMS("failed to alloc fb\n");
7586 return;
7587 }
7588
7589 val = I915_READ(DSPCNTR(plane));
7590
7591 if (INTEL_INFO(dev)->gen >= 4)
7592 if (val & DISPPLANE_TILED)
7593 plane_config->tiled = true;
7594
7595 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7596 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007597 crtc->base.primary->fb->pixel_format = fourcc;
7598 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007599 drm_format_plane_cpp(fourcc, 0) * 8;
7600
7601 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7602 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7603 offset = I915_READ(DSPOFFSET(plane));
7604 } else {
7605 if (plane_config->tiled)
7606 offset = I915_READ(DSPTILEOFF(plane));
7607 else
7608 offset = I915_READ(DSPLINOFF(plane));
7609 }
7610 plane_config->base = base;
7611
7612 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007613 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7614 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007615
7616 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01007617 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007618
Dave Airlie66e514c2014-04-03 07:51:54 +10007619 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007620 plane_config->tiled);
7621
Fabian Frederick1267a262014-07-01 20:39:41 +02007622 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7623 aligned_height);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007624
7625 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007626 pipe, plane, crtc->base.primary->fb->width,
7627 crtc->base.primary->fb->height,
7628 crtc->base.primary->fb->bits_per_pixel, base,
7629 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007630 plane_config->size);
7631}
7632
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007633static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7634 struct intel_crtc_config *pipe_config)
7635{
7636 struct drm_device *dev = crtc->base.dev;
7637 struct drm_i915_private *dev_priv = dev->dev_private;
7638 uint32_t tmp;
7639
Daniel Vetterf458ebb2014-09-30 10:56:39 +02007640 if (!intel_display_power_is_enabled(dev_priv,
7641 POWER_DOMAIN_PIPE(crtc->pipe)))
Paulo Zanoni930e8c92014-07-04 13:38:34 -03007642 return false;
7643
Daniel Vettere143a212013-07-04 12:01:15 +02007644 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007645 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007646
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007647 tmp = I915_READ(PIPECONF(crtc->pipe));
7648 if (!(tmp & PIPECONF_ENABLE))
7649 return false;
7650
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007651 switch (tmp & PIPECONF_BPC_MASK) {
7652 case PIPECONF_6BPC:
7653 pipe_config->pipe_bpp = 18;
7654 break;
7655 case PIPECONF_8BPC:
7656 pipe_config->pipe_bpp = 24;
7657 break;
7658 case PIPECONF_10BPC:
7659 pipe_config->pipe_bpp = 30;
7660 break;
7661 case PIPECONF_12BPC:
7662 pipe_config->pipe_bpp = 36;
7663 break;
7664 default:
7665 break;
7666 }
7667
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007668 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7669 pipe_config->limited_color_range = true;
7670
Daniel Vetterab9412b2013-05-03 11:49:46 +02007671 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007672 struct intel_shared_dpll *pll;
7673
Daniel Vetter88adfff2013-03-28 10:42:01 +01007674 pipe_config->has_pch_encoder = true;
7675
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007676 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7677 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7678 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007679
7680 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007681
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007682 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007683 pipe_config->shared_dpll =
7684 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007685 } else {
7686 tmp = I915_READ(PCH_DPLL_SEL);
7687 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7688 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7689 else
7690 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7691 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007692
7693 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7694
7695 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7696 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007697
7698 tmp = pipe_config->dpll_hw_state.dpll;
7699 pipe_config->pixel_multiplier =
7700 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7701 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007702
7703 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007704 } else {
7705 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007706 }
7707
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007708 intel_get_pipe_timings(crtc, pipe_config);
7709
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007710 ironlake_get_pfit_config(crtc, pipe_config);
7711
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007712 return true;
7713}
7714
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007715static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7716{
7717 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007718 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007719
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007720 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007721 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007722 pipe_name(crtc->pipe));
7723
7724 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
Daniel Vetter8cc3e162014-06-25 22:01:46 +03007725 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7726 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7727 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007728 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7729 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7730 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -03007731 if (IS_HASWELL(dev))
7732 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7733 "CPU PWM2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007734 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7735 "PCH PWM1 enabled\n");
7736 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7737 "Utility pin enabled\n");
7738 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7739
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007740 /*
7741 * In theory we can still leave IRQs enabled, as long as only the HPD
7742 * interrupts remain enabled. We used to check for that, but since it's
7743 * gen-specific and since we only disable LCPLL after we fully disable
7744 * the interrupts, the check below should be enough.
7745 */
Jesse Barnes9df7575f2014-06-20 09:29:20 -07007746 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007747}
7748
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007749static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7750{
7751 struct drm_device *dev = dev_priv->dev;
7752
7753 if (IS_HASWELL(dev))
7754 return I915_READ(D_COMP_HSW);
7755 else
7756 return I915_READ(D_COMP_BDW);
7757}
7758
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007759static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7760{
7761 struct drm_device *dev = dev_priv->dev;
7762
7763 if (IS_HASWELL(dev)) {
7764 mutex_lock(&dev_priv->rps.hw_lock);
7765 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7766 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03007767 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007768 mutex_unlock(&dev_priv->rps.hw_lock);
7769 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007770 I915_WRITE(D_COMP_BDW, val);
7771 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007772 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007773}
7774
7775/*
7776 * This function implements pieces of two sequences from BSpec:
7777 * - Sequence for display software to disable LCPLL
7778 * - Sequence for display software to allow package C8+
7779 * The steps implemented here are just the steps that actually touch the LCPLL
7780 * register. Callers should take care of disabling all the display engine
7781 * functions, doing the mode unset, fixing interrupts, etc.
7782 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007783static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7784 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007785{
7786 uint32_t val;
7787
7788 assert_can_disable_lcpll(dev_priv);
7789
7790 val = I915_READ(LCPLL_CTL);
7791
7792 if (switch_to_fclk) {
7793 val |= LCPLL_CD_SOURCE_FCLK;
7794 I915_WRITE(LCPLL_CTL, val);
7795
7796 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7797 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7798 DRM_ERROR("Switching to FCLK failed\n");
7799
7800 val = I915_READ(LCPLL_CTL);
7801 }
7802
7803 val |= LCPLL_PLL_DISABLE;
7804 I915_WRITE(LCPLL_CTL, val);
7805 POSTING_READ(LCPLL_CTL);
7806
7807 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7808 DRM_ERROR("LCPLL still locked\n");
7809
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007810 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007811 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007812 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007813 ndelay(100);
7814
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007815 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7816 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007817 DRM_ERROR("D_COMP RCOMP still in progress\n");
7818
7819 if (allow_power_down) {
7820 val = I915_READ(LCPLL_CTL);
7821 val |= LCPLL_POWER_DOWN_ALLOW;
7822 I915_WRITE(LCPLL_CTL, val);
7823 POSTING_READ(LCPLL_CTL);
7824 }
7825}
7826
7827/*
7828 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7829 * source.
7830 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007831static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007832{
7833 uint32_t val;
7834
7835 val = I915_READ(LCPLL_CTL);
7836
7837 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7838 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7839 return;
7840
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007841 /*
7842 * Make sure we're not on PC8 state before disabling PC8, otherwise
7843 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7844 *
7845 * The other problem is that hsw_restore_lcpll() is called as part of
7846 * the runtime PM resume sequence, so we can't just call
7847 * gen6_gt_force_wake_get() because that function calls
7848 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7849 * while we are on the resume sequence. So to solve this problem we have
7850 * to call special forcewake code that doesn't touch runtime PM and
7851 * doesn't enable the forcewake delayed work.
7852 */
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007853 spin_lock_irq(&dev_priv->uncore.lock);
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007854 if (dev_priv->uncore.forcewake_count++ == 0)
7855 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007856 spin_unlock_irq(&dev_priv->uncore.lock);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007857
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007858 if (val & LCPLL_POWER_DOWN_ALLOW) {
7859 val &= ~LCPLL_POWER_DOWN_ALLOW;
7860 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007861 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007862 }
7863
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007864 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007865 val |= D_COMP_COMP_FORCE;
7866 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007867 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007868
7869 val = I915_READ(LCPLL_CTL);
7870 val &= ~LCPLL_PLL_DISABLE;
7871 I915_WRITE(LCPLL_CTL, val);
7872
7873 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7874 DRM_ERROR("LCPLL not locked yet\n");
7875
7876 if (val & LCPLL_CD_SOURCE_FCLK) {
7877 val = I915_READ(LCPLL_CTL);
7878 val &= ~LCPLL_CD_SOURCE_FCLK;
7879 I915_WRITE(LCPLL_CTL, val);
7880
7881 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7882 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7883 DRM_ERROR("Switching back to LCPLL failed\n");
7884 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007885
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007886 /* See the big comment above. */
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007887 spin_lock_irq(&dev_priv->uncore.lock);
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007888 if (--dev_priv->uncore.forcewake_count == 0)
7889 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007890 spin_unlock_irq(&dev_priv->uncore.lock);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007891}
7892
Paulo Zanoni765dab62014-03-07 20:08:18 -03007893/*
7894 * Package states C8 and deeper are really deep PC states that can only be
7895 * reached when all the devices on the system allow it, so even if the graphics
7896 * device allows PC8+, it doesn't mean the system will actually get to these
7897 * states. Our driver only allows PC8+ when going into runtime PM.
7898 *
7899 * The requirements for PC8+ are that all the outputs are disabled, the power
7900 * well is disabled and most interrupts are disabled, and these are also
7901 * requirements for runtime PM. When these conditions are met, we manually do
7902 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7903 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7904 * hang the machine.
7905 *
7906 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7907 * the state of some registers, so when we come back from PC8+ we need to
7908 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7909 * need to take care of the registers kept by RC6. Notice that this happens even
7910 * if we don't put the device in PCI D3 state (which is what currently happens
7911 * because of the runtime PM support).
7912 *
7913 * For more, read "Display Sequences for Package C8" on the hardware
7914 * documentation.
7915 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007916void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007917{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007918 struct drm_device *dev = dev_priv->dev;
7919 uint32_t val;
7920
Paulo Zanonic67a4702013-08-19 13:18:09 -03007921 DRM_DEBUG_KMS("Enabling package C8+\n");
7922
Paulo Zanonic67a4702013-08-19 13:18:09 -03007923 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7924 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7925 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7926 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7927 }
7928
7929 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007930 hsw_disable_lcpll(dev_priv, true, true);
7931}
7932
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007933void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007934{
7935 struct drm_device *dev = dev_priv->dev;
7936 uint32_t val;
7937
Paulo Zanonic67a4702013-08-19 13:18:09 -03007938 DRM_DEBUG_KMS("Disabling package C8+\n");
7939
7940 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007941 lpt_init_pch_refclk(dev);
7942
7943 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7944 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7945 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7946 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7947 }
7948
7949 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007950}
7951
Paulo Zanoni9a952a02014-03-07 20:12:34 -03007952static void snb_modeset_global_resources(struct drm_device *dev)
7953{
7954 modeset_update_crtc_power_domains(dev);
7955}
7956
Imre Deak4f074122013-10-16 17:25:51 +03007957static void haswell_modeset_global_resources(struct drm_device *dev)
7958{
Paulo Zanonida723562013-12-19 11:54:51 -02007959 modeset_update_crtc_power_domains(dev);
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02007960}
7961
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +02007962static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007963{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007964 if (!intel_ddi_pll_select(crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007965 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03007966
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007967 crtc->lowfreq_avail = false;
Daniel Vetter644cef32014-04-24 23:55:07 +02007968
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007969 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007970}
7971
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007972static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7973 enum port port,
7974 struct intel_crtc_config *pipe_config)
7975{
7976 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7977
7978 switch (pipe_config->ddi_pll_sel) {
7979 case PORT_CLK_SEL_WRPLL1:
7980 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7981 break;
7982 case PORT_CLK_SEL_WRPLL2:
7983 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7984 break;
7985 }
7986}
7987
Daniel Vetter26804af2014-06-25 22:01:55 +03007988static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7989 struct intel_crtc_config *pipe_config)
7990{
7991 struct drm_device *dev = crtc->base.dev;
7992 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007993 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03007994 enum port port;
7995 uint32_t tmp;
7996
7997 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7998
7999 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8000
Damien Lespiau7d2c8172014-07-29 18:06:18 +01008001 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +03008002
Daniel Vetterd452c5b2014-07-04 11:27:39 -03008003 if (pipe_config->shared_dpll >= 0) {
8004 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8005
8006 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8007 &pipe_config->dpll_hw_state));
8008 }
8009
Daniel Vetter26804af2014-06-25 22:01:55 +03008010 /*
8011 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8012 * DDI E. So just check whether this pipe is wired to DDI E and whether
8013 * the PCH transcoder is on.
8014 */
Damien Lespiauca370452013-12-03 13:56:24 +00008015 if (INTEL_INFO(dev)->gen < 9 &&
8016 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter26804af2014-06-25 22:01:55 +03008017 pipe_config->has_pch_encoder = true;
8018
8019 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8020 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8021 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8022
8023 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8024 }
8025}
8026
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008027static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8028 struct intel_crtc_config *pipe_config)
8029{
8030 struct drm_device *dev = crtc->base.dev;
8031 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008032 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008033 uint32_t tmp;
8034
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008035 if (!intel_display_power_is_enabled(dev_priv,
Imre Deakb5482bd2014-03-05 16:20:55 +02008036 POWER_DOMAIN_PIPE(crtc->pipe)))
8037 return false;
8038
Daniel Vettere143a212013-07-04 12:01:15 +02008039 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008040 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8041
Daniel Vettereccb1402013-05-22 00:50:22 +02008042 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8043 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8044 enum pipe trans_edp_pipe;
8045 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8046 default:
8047 WARN(1, "unknown pipe linked to edp transcoder\n");
8048 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8049 case TRANS_DDI_EDP_INPUT_A_ON:
8050 trans_edp_pipe = PIPE_A;
8051 break;
8052 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8053 trans_edp_pipe = PIPE_B;
8054 break;
8055 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8056 trans_edp_pipe = PIPE_C;
8057 break;
8058 }
8059
8060 if (trans_edp_pipe == crtc->pipe)
8061 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8062 }
8063
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008064 if (!intel_display_power_is_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02008065 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03008066 return false;
8067
Daniel Vettereccb1402013-05-22 00:50:22 +02008068 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008069 if (!(tmp & PIPECONF_ENABLE))
8070 return false;
8071
Daniel Vetter26804af2014-06-25 22:01:55 +03008072 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02008073
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008074 intel_get_pipe_timings(crtc, pipe_config);
8075
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008076 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008077 if (intel_display_power_is_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008078 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01008079
Jesse Barnese59150d2014-01-07 13:30:45 -08008080 if (IS_HASWELL(dev))
8081 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8082 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03008083
Clint Taylorebb69c92014-09-30 10:30:22 -07008084 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8085 pipe_config->pixel_multiplier =
8086 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8087 } else {
8088 pipe_config->pixel_multiplier = 1;
8089 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02008090
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008091 return true;
8092}
8093
Chris Wilson560b85b2010-08-07 11:01:38 +01008094static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8095{
8096 struct drm_device *dev = crtc->dev;
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälädc41c152014-08-13 11:57:05 +03008099 uint32_t cntl = 0, size = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01008100
Ville Syrjälädc41c152014-08-13 11:57:05 +03008101 if (base) {
8102 unsigned int width = intel_crtc->cursor_width;
8103 unsigned int height = intel_crtc->cursor_height;
8104 unsigned int stride = roundup_pow_of_two(width) * 4;
8105
8106 switch (stride) {
8107 default:
8108 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8109 width, stride);
8110 stride = 256;
8111 /* fallthrough */
8112 case 256:
8113 case 512:
8114 case 1024:
8115 case 2048:
8116 break;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008117 }
8118
Ville Syrjälädc41c152014-08-13 11:57:05 +03008119 cntl |= CURSOR_ENABLE |
8120 CURSOR_GAMMA_ENABLE |
8121 CURSOR_FORMAT_ARGB |
8122 CURSOR_STRIDE(stride);
8123
8124 size = (height << 12) | width;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008125 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008126
Ville Syrjälädc41c152014-08-13 11:57:05 +03008127 if (intel_crtc->cursor_cntl != 0 &&
8128 (intel_crtc->cursor_base != base ||
8129 intel_crtc->cursor_size != size ||
8130 intel_crtc->cursor_cntl != cntl)) {
8131 /* On these chipsets we can only modify the base/size/stride
8132 * whilst the cursor is disabled.
8133 */
8134 I915_WRITE(_CURACNTR, 0);
8135 POSTING_READ(_CURACNTR);
8136 intel_crtc->cursor_cntl = 0;
8137 }
8138
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008139 if (intel_crtc->cursor_base != base) {
Ville Syrjälädc41c152014-08-13 11:57:05 +03008140 I915_WRITE(_CURABASE, base);
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008141 intel_crtc->cursor_base = base;
8142 }
Ville Syrjälädc41c152014-08-13 11:57:05 +03008143
8144 if (intel_crtc->cursor_size != size) {
8145 I915_WRITE(CURSIZE, size);
8146 intel_crtc->cursor_size = size;
8147 }
8148
Chris Wilson4b0e3332014-05-30 16:35:26 +03008149 if (intel_crtc->cursor_cntl != cntl) {
8150 I915_WRITE(_CURACNTR, cntl);
8151 POSTING_READ(_CURACNTR);
8152 intel_crtc->cursor_cntl = cntl;
8153 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008154}
8155
8156static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8157{
8158 struct drm_device *dev = crtc->dev;
8159 struct drm_i915_private *dev_priv = dev->dev_private;
8160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8161 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008162 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01008163
Chris Wilson4b0e3332014-05-30 16:35:26 +03008164 cntl = 0;
8165 if (base) {
8166 cntl = MCURSOR_GAMMA_ENABLE;
8167 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308168 case 64:
8169 cntl |= CURSOR_MODE_64_ARGB_AX;
8170 break;
8171 case 128:
8172 cntl |= CURSOR_MODE_128_ARGB_AX;
8173 break;
8174 case 256:
8175 cntl |= CURSOR_MODE_256_ARGB_AX;
8176 break;
8177 default:
8178 WARN_ON(1);
8179 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01008180 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008181 cntl |= pipe << 28; /* Connect to correct pipe */
Ville Syrjälä47bf17a2014-09-12 20:53:33 +03008182
8183 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8184 cntl |= CURSOR_PIPE_CSC_ENABLE;
Chris Wilson560b85b2010-08-07 11:01:38 +01008185 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008186
Ville Syrjälä4398ad42014-10-23 07:41:34 -07008187 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8188 cntl |= CURSOR_ROTATE_180;
8189
Chris Wilson4b0e3332014-05-30 16:35:26 +03008190 if (intel_crtc->cursor_cntl != cntl) {
8191 I915_WRITE(CURCNTR(pipe), cntl);
8192 POSTING_READ(CURCNTR(pipe));
8193 intel_crtc->cursor_cntl = cntl;
8194 }
8195
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008196 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008197 I915_WRITE(CURBASE(pipe), base);
8198 POSTING_READ(CURBASE(pipe));
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008199
8200 intel_crtc->cursor_base = base;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008201}
8202
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008203/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01008204static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8205 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008206{
8207 struct drm_device *dev = crtc->dev;
8208 struct drm_i915_private *dev_priv = dev->dev_private;
8209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8210 int pipe = intel_crtc->pipe;
Matt Roper3d7d6512014-06-10 08:28:13 -07008211 int x = crtc->cursor_x;
8212 int y = crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008213 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008214
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008215 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008216 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008217
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008218 if (x >= intel_crtc->config.pipe_src_w)
8219 base = 0;
8220
8221 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008222 base = 0;
8223
8224 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008225 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008226 base = 0;
8227
8228 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8229 x = -x;
8230 }
8231 pos |= x << CURSOR_X_SHIFT;
8232
8233 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008234 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008235 base = 0;
8236
8237 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8238 y = -y;
8239 }
8240 pos |= y << CURSOR_Y_SHIFT;
8241
Chris Wilson4b0e3332014-05-30 16:35:26 +03008242 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008243 return;
8244
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008245 I915_WRITE(CURPOS(pipe), pos);
8246
Ville Syrjälä4398ad42014-10-23 07:41:34 -07008247 /* ILK+ do this automagically */
8248 if (HAS_GMCH_DISPLAY(dev) &&
8249 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8250 base += (intel_crtc->cursor_height *
8251 intel_crtc->cursor_width - 1) * 4;
8252 }
8253
Ville Syrjälä8ac54662014-08-12 19:39:54 +03008254 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008255 i845_update_cursor(crtc, base);
8256 else
8257 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008258}
8259
Ville Syrjälädc41c152014-08-13 11:57:05 +03008260static bool cursor_size_ok(struct drm_device *dev,
8261 uint32_t width, uint32_t height)
8262{
8263 if (width == 0 || height == 0)
8264 return false;
8265
8266 /*
8267 * 845g/865g are special in that they are only limited by
8268 * the width of their cursors, the height is arbitrary up to
8269 * the precision of the register. Everything else requires
8270 * square cursors, limited to a few power-of-two sizes.
8271 */
8272 if (IS_845G(dev) || IS_I865G(dev)) {
8273 if ((width & 63) != 0)
8274 return false;
8275
8276 if (width > (IS_845G(dev) ? 64 : 512))
8277 return false;
8278
8279 if (height > 1023)
8280 return false;
8281 } else {
8282 switch (width | height) {
8283 case 256:
8284 case 128:
8285 if (IS_GEN2(dev))
8286 return false;
8287 case 64:
8288 break;
8289 default:
8290 return false;
8291 }
8292 }
8293
8294 return true;
8295}
8296
Matt Ropere3287952014-06-10 08:28:12 -07008297static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8298 struct drm_i915_gem_object *obj,
8299 uint32_t width, uint32_t height)
Jesse Barnes79e53942008-11-07 14:24:08 -08008300{
8301 struct drm_device *dev = crtc->dev;
8302 struct drm_i915_private *dev_priv = dev->dev_private;
8303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02008304 enum pipe pipe = intel_crtc->pipe;
Gustavo Padovan757f9a32014-09-24 14:20:24 -03008305 unsigned old_width;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008306 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008307 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008308
Jesse Barnes79e53942008-11-07 14:24:08 -08008309 /* if we want to turn off the cursor ignore width and height */
Matt Ropere3287952014-06-10 08:28:12 -07008310 if (!obj) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008311 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008312 addr = 0;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008313 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008314 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008315 }
8316
Dave Airlie71acb5e2008-12-30 20:31:46 +10008317 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008318 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008319 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008320 unsigned alignment;
8321
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008322 /*
8323 * Global gtt pte registers are special registers which actually
8324 * forward writes to a chunk of system memory. Which means that
8325 * there is no risk that the register values disappear as soon
8326 * as we call intel_runtime_pm_put(), so it is correct to wrap
8327 * only the pin/unpin/fence and not more.
8328 */
8329 intel_runtime_pm_get(dev_priv);
8330
Chris Wilson693db182013-03-05 14:52:39 +00008331 /* Note that the w/a also requires 2 PTE of padding following
8332 * the bo. We currently fill all unused PTE with the shadow
8333 * page and so we should always have valid PTE following the
8334 * cursor preventing the VT-d warning.
8335 */
8336 alignment = 0;
8337 if (need_vtd_wa(dev))
8338 alignment = 64*1024;
8339
8340 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008341 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008342 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008343 intel_runtime_pm_put(dev_priv);
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008344 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008345 }
8346
Chris Wilsond9e86c02010-11-10 16:40:20 +00008347 ret = i915_gem_object_put_fence(obj);
8348 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008349 DRM_DEBUG_KMS("failed to release fence for cursor");
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008350 intel_runtime_pm_put(dev_priv);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008351 goto fail_unpin;
8352 }
8353
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008354 addr = i915_gem_obj_ggtt_offset(obj);
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008355
8356 intel_runtime_pm_put(dev_priv);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008357 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008358 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson00731152014-05-21 12:42:56 +01008359 ret = i915_gem_object_attach_phys(obj, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008360 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008361 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008362 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008363 }
Chris Wilson00731152014-05-21 12:42:56 +01008364 addr = obj->phys_handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008365 }
8366
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008367 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008368 if (intel_crtc->cursor_bo) {
Chris Wilson00731152014-05-21 12:42:56 +01008369 if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilsoncc98b412013-08-09 12:25:09 +01008370 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008371 }
Jesse Barnes80824002009-09-10 15:28:06 -07008372
Daniel Vettera071fa02014-06-18 23:28:09 +02008373 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8374 INTEL_FRONTBUFFER_CURSOR(pipe));
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008375 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008376
Chris Wilson64f962e2014-03-26 12:38:15 +00008377 old_width = intel_crtc->cursor_width;
8378
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008379 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008380 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008381 intel_crtc->cursor_width = width;
8382 intel_crtc->cursor_height = height;
8383
Chris Wilson64f962e2014-03-26 12:38:15 +00008384 if (intel_crtc->active) {
8385 if (old_width != width)
8386 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008387 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008388
Gustavo Padovan3f20df92014-10-24 14:51:34 +01008389 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8390 }
Daniel Vetterf99d7062014-06-19 16:01:59 +02008391
Jesse Barnes79e53942008-11-07 14:24:08 -08008392 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008393fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008394 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008395fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008396 mutex_unlock(&dev->struct_mutex);
8397 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008398}
8399
Jesse Barnes79e53942008-11-07 14:24:08 -08008400static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008401 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008402{
James Simmons72034252010-08-03 01:33:19 +01008403 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008405
James Simmons72034252010-08-03 01:33:19 +01008406 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008407 intel_crtc->lut_r[i] = red[i] >> 8;
8408 intel_crtc->lut_g[i] = green[i] >> 8;
8409 intel_crtc->lut_b[i] = blue[i] >> 8;
8410 }
8411
8412 intel_crtc_load_lut(crtc);
8413}
8414
Jesse Barnes79e53942008-11-07 14:24:08 -08008415/* VESA 640x480x72Hz mode to set on the pipe */
8416static struct drm_display_mode load_detect_mode = {
8417 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8418 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8419};
8420
Daniel Vettera8bb6812014-02-10 18:00:39 +01008421struct drm_framebuffer *
8422__intel_framebuffer_create(struct drm_device *dev,
8423 struct drm_mode_fb_cmd2 *mode_cmd,
8424 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008425{
8426 struct intel_framebuffer *intel_fb;
8427 int ret;
8428
8429 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8430 if (!intel_fb) {
8431 drm_gem_object_unreference_unlocked(&obj->base);
8432 return ERR_PTR(-ENOMEM);
8433 }
8434
8435 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008436 if (ret)
8437 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008438
8439 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008440err:
8441 drm_gem_object_unreference_unlocked(&obj->base);
8442 kfree(intel_fb);
8443
8444 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008445}
8446
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008447static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008448intel_framebuffer_create(struct drm_device *dev,
8449 struct drm_mode_fb_cmd2 *mode_cmd,
8450 struct drm_i915_gem_object *obj)
8451{
8452 struct drm_framebuffer *fb;
8453 int ret;
8454
8455 ret = i915_mutex_lock_interruptible(dev);
8456 if (ret)
8457 return ERR_PTR(ret);
8458 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8459 mutex_unlock(&dev->struct_mutex);
8460
8461 return fb;
8462}
8463
Chris Wilsond2dff872011-04-19 08:36:26 +01008464static u32
8465intel_framebuffer_pitch_for_width(int width, int bpp)
8466{
8467 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8468 return ALIGN(pitch, 64);
8469}
8470
8471static u32
8472intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8473{
8474 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +02008475 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +01008476}
8477
8478static struct drm_framebuffer *
8479intel_framebuffer_create_for_mode(struct drm_device *dev,
8480 struct drm_display_mode *mode,
8481 int depth, int bpp)
8482{
8483 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008484 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008485
8486 obj = i915_gem_alloc_object(dev,
8487 intel_framebuffer_size_for_mode(mode, bpp));
8488 if (obj == NULL)
8489 return ERR_PTR(-ENOMEM);
8490
8491 mode_cmd.width = mode->hdisplay;
8492 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008493 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8494 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008495 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008496
8497 return intel_framebuffer_create(dev, &mode_cmd, obj);
8498}
8499
8500static struct drm_framebuffer *
8501mode_fits_in_fbdev(struct drm_device *dev,
8502 struct drm_display_mode *mode)
8503{
Daniel Vetter4520f532013-10-09 09:18:51 +02008504#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008505 struct drm_i915_private *dev_priv = dev->dev_private;
8506 struct drm_i915_gem_object *obj;
8507 struct drm_framebuffer *fb;
8508
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008509 if (!dev_priv->fbdev)
8510 return NULL;
8511
8512 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008513 return NULL;
8514
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008515 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008516 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008517
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008518 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008519 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8520 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008521 return NULL;
8522
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008523 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008524 return NULL;
8525
8526 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008527#else
8528 return NULL;
8529#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008530}
8531
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008532bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008533 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05008534 struct intel_load_detect_pipe *old,
8535 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008536{
8537 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008538 struct intel_encoder *intel_encoder =
8539 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008540 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008541 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008542 struct drm_crtc *crtc = NULL;
8543 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008544 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05008545 struct drm_mode_config *config = &dev->mode_config;
8546 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008547
Chris Wilsond2dff872011-04-19 08:36:26 +01008548 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008549 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008550 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008551
Rob Clark51fd3712013-11-19 12:10:12 -05008552retry:
8553 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8554 if (ret)
8555 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008556
Jesse Barnes79e53942008-11-07 14:24:08 -08008557 /*
8558 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008559 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008560 * - if the connector already has an assigned crtc, use it (but make
8561 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008562 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008563 * - try to find the first unused crtc that can drive this connector,
8564 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008565 */
8566
8567 /* See if we already have a CRTC for this connector */
8568 if (encoder->crtc) {
8569 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008570
Rob Clark51fd3712013-11-19 12:10:12 -05008571 ret = drm_modeset_lock(&crtc->mutex, ctx);
8572 if (ret)
8573 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01008574
Daniel Vetter24218aa2012-08-12 19:27:11 +02008575 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008576 old->load_detect_temp = false;
8577
8578 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008579 if (connector->dpms != DRM_MODE_DPMS_ON)
8580 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008581
Chris Wilson71731882011-04-19 23:10:58 +01008582 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008583 }
8584
8585 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008586 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008587 i++;
8588 if (!(encoder->possible_crtcs & (1 << i)))
8589 continue;
Ville Syrjäläa4592492014-08-11 13:15:36 +03008590 if (possible_crtc->enabled)
8591 continue;
8592 /* This can occur when applying the pipe A quirk on resume. */
8593 if (to_intel_crtc(possible_crtc)->new_enabled)
8594 continue;
8595
8596 crtc = possible_crtc;
8597 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08008598 }
8599
8600 /*
8601 * If we didn't find an unused CRTC, don't use any.
8602 */
8603 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008604 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05008605 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08008606 }
8607
Rob Clark51fd3712013-11-19 12:10:12 -05008608 ret = drm_modeset_lock(&crtc->mutex, ctx);
8609 if (ret)
8610 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02008611 intel_encoder->new_crtc = to_intel_crtc(crtc);
8612 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008613
8614 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008615 intel_crtc->new_enabled = true;
8616 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008617 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008618 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008619 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008620
Chris Wilson64927112011-04-20 07:25:26 +01008621 if (!mode)
8622 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008623
Chris Wilsond2dff872011-04-19 08:36:26 +01008624 /* We need a framebuffer large enough to accommodate all accesses
8625 * that the plane may generate whilst we perform load detection.
8626 * We can not rely on the fbcon either being present (we get called
8627 * during its initialisation to detect all boot displays, or it may
8628 * not even exist) or that it is large enough to satisfy the
8629 * requested mode.
8630 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008631 fb = mode_fits_in_fbdev(dev, mode);
8632 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008633 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008634 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8635 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008636 } else
8637 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008638 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008639 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008640 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008641 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008642
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008643 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008644 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008645 if (old->release_fb)
8646 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008647 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008648 }
Chris Wilson71731882011-04-19 23:10:58 +01008649
Jesse Barnes79e53942008-11-07 14:24:08 -08008650 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008651 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008652 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008653
8654 fail:
8655 intel_crtc->new_enabled = crtc->enabled;
8656 if (intel_crtc->new_enabled)
8657 intel_crtc->new_config = &intel_crtc->config;
8658 else
8659 intel_crtc->new_config = NULL;
Rob Clark51fd3712013-11-19 12:10:12 -05008660fail_unlock:
8661 if (ret == -EDEADLK) {
8662 drm_modeset_backoff(ctx);
8663 goto retry;
8664 }
8665
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008666 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008667}
8668
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008669void intel_release_load_detect_pipe(struct drm_connector *connector,
Ville Syrjälä208bf9f2014-08-11 13:15:35 +03008670 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008671{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008672 struct intel_encoder *intel_encoder =
8673 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008674 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008675 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008677
Chris Wilsond2dff872011-04-19 08:36:26 +01008678 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008679 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008680 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008681
Chris Wilson8261b192011-04-19 23:18:09 +01008682 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008683 to_intel_connector(connector)->new_encoder = NULL;
8684 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008685 intel_crtc->new_enabled = false;
8686 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008687 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008688
Daniel Vetter36206362012-12-10 20:42:17 +01008689 if (old->release_fb) {
8690 drm_framebuffer_unregister_private(old->release_fb);
8691 drm_framebuffer_unreference(old->release_fb);
8692 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008693
Chris Wilson0622a532011-04-21 09:32:11 +01008694 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008695 }
8696
Eric Anholtc751ce42010-03-25 11:48:48 -07008697 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008698 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8699 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008700}
8701
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008702static int i9xx_pll_refclk(struct drm_device *dev,
8703 const struct intel_crtc_config *pipe_config)
8704{
8705 struct drm_i915_private *dev_priv = dev->dev_private;
8706 u32 dpll = pipe_config->dpll_hw_state.dpll;
8707
8708 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008709 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008710 else if (HAS_PCH_SPLIT(dev))
8711 return 120000;
8712 else if (!IS_GEN2(dev))
8713 return 96000;
8714 else
8715 return 48000;
8716}
8717
Jesse Barnes79e53942008-11-07 14:24:08 -08008718/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008719static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8720 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008721{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008722 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008723 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008724 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008725 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008726 u32 fp;
8727 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008728 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008729
8730 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008731 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008732 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008733 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008734
8735 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008736 if (IS_PINEVIEW(dev)) {
8737 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8738 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008739 } else {
8740 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8741 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8742 }
8743
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008744 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008745 if (IS_PINEVIEW(dev))
8746 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8747 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008748 else
8749 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008750 DPLL_FPA01_P1_POST_DIV_SHIFT);
8751
8752 switch (dpll & DPLL_MODE_MASK) {
8753 case DPLLB_MODE_DAC_SERIAL:
8754 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8755 5 : 10;
8756 break;
8757 case DPLLB_MODE_LVDS:
8758 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8759 7 : 14;
8760 break;
8761 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008762 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008763 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008764 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008765 }
8766
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008767 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008768 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008769 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008770 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008771 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008772 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008773 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008774
8775 if (is_lvds) {
8776 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8777 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008778
8779 if (lvds & LVDS_CLKB_POWER_UP)
8780 clock.p2 = 7;
8781 else
8782 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008783 } else {
8784 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8785 clock.p1 = 2;
8786 else {
8787 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8788 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8789 }
8790 if (dpll & PLL_P2_DIVIDE_BY_4)
8791 clock.p2 = 4;
8792 else
8793 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008794 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008795
8796 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008797 }
8798
Ville Syrjälä18442d02013-09-13 16:00:08 +03008799 /*
8800 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008801 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008802 * encoder's get_config() function.
8803 */
8804 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008805}
8806
Ville Syrjälä6878da02013-09-13 15:59:11 +03008807int intel_dotclock_calculate(int link_freq,
8808 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008809{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008810 /*
8811 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008812 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008813 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008814 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008815 *
8816 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008817 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008818 */
8819
Ville Syrjälä6878da02013-09-13 15:59:11 +03008820 if (!m_n->link_n)
8821 return 0;
8822
8823 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8824}
8825
Ville Syrjälä18442d02013-09-13 16:00:08 +03008826static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8827 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008828{
8829 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008830
8831 /* read out port_clock from the DPLL */
8832 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008833
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008834 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008835 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008836 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008837 * agree once we know their relationship in the encoder's
8838 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008839 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008840 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008841 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8842 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008843}
8844
8845/** Returns the currently programmed mode of the given pipe. */
8846struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8847 struct drm_crtc *crtc)
8848{
Jesse Barnes548f2452011-02-17 10:40:53 -08008849 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008851 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008852 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008853 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008854 int htot = I915_READ(HTOTAL(cpu_transcoder));
8855 int hsync = I915_READ(HSYNC(cpu_transcoder));
8856 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8857 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008858 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008859
8860 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8861 if (!mode)
8862 return NULL;
8863
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008864 /*
8865 * Construct a pipe_config sufficient for getting the clock info
8866 * back out of crtc_clock_get.
8867 *
8868 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8869 * to use a real value here instead.
8870 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008871 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008872 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008873 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8874 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8875 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008876 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8877
Ville Syrjälä773ae032013-09-23 17:48:20 +03008878 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008879 mode->hdisplay = (htot & 0xffff) + 1;
8880 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8881 mode->hsync_start = (hsync & 0xffff) + 1;
8882 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8883 mode->vdisplay = (vtot & 0xffff) + 1;
8884 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8885 mode->vsync_start = (vsync & 0xffff) + 1;
8886 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8887
8888 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008889
8890 return mode;
8891}
8892
Jesse Barnes652c3932009-08-17 13:31:43 -07008893static void intel_decrease_pllclock(struct drm_crtc *crtc)
8894{
8895 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008896 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008898
Sonika Jindalbaff2962014-07-22 11:16:35 +05308899 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008900 return;
8901
8902 if (!dev_priv->lvds_downclock_avail)
8903 return;
8904
8905 /*
8906 * Since this is called by a timer, we should never get here in
8907 * the manual case.
8908 */
8909 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008910 int pipe = intel_crtc->pipe;
8911 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008912 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008913
Zhao Yakui44d98a62009-10-09 11:39:40 +08008914 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008915
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008916 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008917
Chris Wilson074b5e12012-05-02 12:07:06 +01008918 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008919 dpll |= DISPLAY_RATE_SELECT_FPA1;
8920 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008921 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008922 dpll = I915_READ(dpll_reg);
8923 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008924 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008925 }
8926
8927}
8928
Chris Wilsonf047e392012-07-21 12:31:41 +01008929void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008930{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008931 struct drm_i915_private *dev_priv = dev->dev_private;
8932
Chris Wilsonf62a0072014-02-21 17:55:39 +00008933 if (dev_priv->mm.busy)
8934 return;
8935
Paulo Zanoni43694d62014-03-07 20:08:08 -03008936 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008937 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008938 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008939}
8940
8941void intel_mark_idle(struct drm_device *dev)
8942{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008943 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008944 struct drm_crtc *crtc;
8945
Chris Wilsonf62a0072014-02-21 17:55:39 +00008946 if (!dev_priv->mm.busy)
8947 return;
8948
8949 dev_priv->mm.busy = false;
8950
Jani Nikulad330a952014-01-21 11:24:25 +02008951 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008952 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008953
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008954 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008955 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008956 continue;
8957
8958 intel_decrease_pllclock(crtc);
8959 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008960
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008961 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008962 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008963
8964out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03008965 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008966}
8967
Jesse Barnes79e53942008-11-07 14:24:08 -08008968static void intel_crtc_destroy(struct drm_crtc *crtc)
8969{
8970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008971 struct drm_device *dev = crtc->dev;
8972 struct intel_unpin_work *work;
Daniel Vetter67e77c52010-08-20 22:26:30 +02008973
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02008974 spin_lock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008975 work = intel_crtc->unpin_work;
8976 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02008977 spin_unlock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008978
8979 if (work) {
8980 cancel_work_sync(&work->work);
8981 kfree(work);
8982 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008983
8984 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008985
Jesse Barnes79e53942008-11-07 14:24:08 -08008986 kfree(intel_crtc);
8987}
8988
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008989static void intel_unpin_work_fn(struct work_struct *__work)
8990{
8991 struct intel_unpin_work *work =
8992 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008993 struct drm_device *dev = work->crtc->dev;
Daniel Vetterf99d7062014-06-19 16:01:59 +02008994 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008995
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008996 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01008997 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00008998 drm_gem_object_unreference(&work->pending_flip_obj->base);
8999 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00009000
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009001 intel_update_fbc(dev);
9002 mutex_unlock(&dev->struct_mutex);
9003
Daniel Vetterf99d7062014-06-19 16:01:59 +02009004 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9005
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009006 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9007 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9008
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009009 kfree(work);
9010}
9011
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009012static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01009013 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009014{
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9016 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009017 unsigned long flags;
9018
9019 /* Ignore early vblank irqs */
9020 if (intel_crtc == NULL)
9021 return;
9022
Daniel Vetterf3260382014-09-15 14:55:23 +02009023 /*
9024 * This is called both by irq handlers and the reset code (to complete
9025 * lost pageflips) so needs the full irqsave spinlocks.
9026 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009027 spin_lock_irqsave(&dev->event_lock, flags);
9028 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00009029
9030 /* Ensure we don't miss a work->pending update ... */
9031 smp_rmb();
9032
9033 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009034 spin_unlock_irqrestore(&dev->event_lock, flags);
9035 return;
9036 }
9037
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009038 page_flip_completed(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01009039
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009040 spin_unlock_irqrestore(&dev->event_lock, flags);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009041}
9042
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009043void intel_finish_page_flip(struct drm_device *dev, int pipe)
9044{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009045 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009046 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9047
Mario Kleiner49b14a52010-12-09 07:00:07 +01009048 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009049}
9050
9051void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9052{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009053 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009054 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9055
Mario Kleiner49b14a52010-12-09 07:00:07 +01009056 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009057}
9058
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009059/* Is 'a' after or equal to 'b'? */
9060static bool g4x_flip_count_after_eq(u32 a, u32 b)
9061{
9062 return !((a - b) & 0x80000000);
9063}
9064
9065static bool page_flip_finished(struct intel_crtc *crtc)
9066{
9067 struct drm_device *dev = crtc->base.dev;
9068 struct drm_i915_private *dev_priv = dev->dev_private;
9069
9070 /*
9071 * The relevant registers doen't exist on pre-ctg.
9072 * As the flip done interrupt doesn't trigger for mmio
9073 * flips on gmch platforms, a flip count check isn't
9074 * really needed there. But since ctg has the registers,
9075 * include it in the check anyway.
9076 */
9077 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9078 return true;
9079
9080 /*
9081 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9082 * used the same base address. In that case the mmio flip might
9083 * have completed, but the CS hasn't even executed the flip yet.
9084 *
9085 * A flip count check isn't enough as the CS might have updated
9086 * the base address just after start of vblank, but before we
9087 * managed to process the interrupt. This means we'd complete the
9088 * CS flip too soon.
9089 *
9090 * Combining both checks should get us a good enough result. It may
9091 * still happen that the CS flip has been executed, but has not
9092 * yet actually completed. But in case the base address is the same
9093 * anyway, we don't really care.
9094 */
9095 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9096 crtc->unpin_work->gtt_offset &&
9097 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9098 crtc->unpin_work->flip_count);
9099}
9100
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009101void intel_prepare_page_flip(struct drm_device *dev, int plane)
9102{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009103 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009104 struct intel_crtc *intel_crtc =
9105 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9106 unsigned long flags;
9107
Daniel Vetterf3260382014-09-15 14:55:23 +02009108
9109 /*
9110 * This is called both by irq handlers and the reset code (to complete
9111 * lost pageflips) so needs the full irqsave spinlocks.
9112 *
9113 * NB: An MMIO update of the plane base pointer will also
Chris Wilsone7d841c2012-12-03 11:36:30 +00009114 * generate a page-flip completion irq, i.e. every modeset
9115 * is also accompanied by a spurious intel_prepare_page_flip().
9116 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009117 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009118 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00009119 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009120 spin_unlock_irqrestore(&dev->event_lock, flags);
9121}
9122
Robin Schroereba905b2014-05-18 02:24:50 +02009123static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00009124{
9125 /* Ensure that the work item is consistent when activating it ... */
9126 smp_wmb();
9127 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9128 /* and that it is marked active as soon as the irq could fire. */
9129 smp_wmb();
9130}
9131
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009132static int intel_gen2_queue_flip(struct drm_device *dev,
9133 struct drm_crtc *crtc,
9134 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009135 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009136 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009137 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009138{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009140 u32 flip_mask;
9141 int ret;
9142
Daniel Vetter6d90c952012-04-26 23:28:05 +02009143 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009144 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009145 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009146
9147 /* Can't queue multiple flips, so wait for the previous
9148 * one to finish before executing the next.
9149 */
9150 if (intel_crtc->plane)
9151 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9152 else
9153 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009154 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9155 intel_ring_emit(ring, MI_NOOP);
9156 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9157 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9158 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009159 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009160 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00009161
9162 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009163 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009164 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009165}
9166
9167static int intel_gen3_queue_flip(struct drm_device *dev,
9168 struct drm_crtc *crtc,
9169 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009170 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009171 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009172 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009173{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009175 u32 flip_mask;
9176 int ret;
9177
Daniel Vetter6d90c952012-04-26 23:28:05 +02009178 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009179 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009180 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009181
9182 if (intel_crtc->plane)
9183 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9184 else
9185 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009186 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9187 intel_ring_emit(ring, MI_NOOP);
9188 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9189 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9190 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009191 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009192 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009193
Chris Wilsone7d841c2012-12-03 11:36:30 +00009194 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009195 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009196 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009197}
9198
9199static int intel_gen4_queue_flip(struct drm_device *dev,
9200 struct drm_crtc *crtc,
9201 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009202 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009203 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009204 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009205{
9206 struct drm_i915_private *dev_priv = dev->dev_private;
9207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9208 uint32_t pf, pipesrc;
9209 int ret;
9210
Daniel Vetter6d90c952012-04-26 23:28:05 +02009211 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009212 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009213 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009214
9215 /* i965+ uses the linear or tiled offsets from the
9216 * Display Registers (which do not change across a page-flip)
9217 * so we need only reprogram the base address.
9218 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009219 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9220 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9221 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009222 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009223 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009224
9225 /* XXX Enabling the panel-fitter across page-flip is so far
9226 * untested on non-native modes, so ignore it for now.
9227 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9228 */
9229 pf = 0;
9230 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009231 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009232
9233 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009234 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009235 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009236}
9237
9238static int intel_gen6_queue_flip(struct drm_device *dev,
9239 struct drm_crtc *crtc,
9240 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009241 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009242 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009243 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009244{
9245 struct drm_i915_private *dev_priv = dev->dev_private;
9246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9247 uint32_t pf, pipesrc;
9248 int ret;
9249
Daniel Vetter6d90c952012-04-26 23:28:05 +02009250 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009251 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009252 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009253
Daniel Vetter6d90c952012-04-26 23:28:05 +02009254 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9255 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9256 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009257 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009258
Chris Wilson99d9acd2012-04-17 20:37:00 +01009259 /* Contrary to the suggestions in the documentation,
9260 * "Enable Panel Fitter" does not seem to be required when page
9261 * flipping with a non-native mode, and worse causes a normal
9262 * modeset to fail.
9263 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9264 */
9265 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009266 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009267 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009268
9269 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009270 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009271 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009272}
9273
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009274static int intel_gen7_queue_flip(struct drm_device *dev,
9275 struct drm_crtc *crtc,
9276 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009277 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009278 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009279 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009280{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009282 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009283 int len, ret;
9284
Robin Schroereba905b2014-05-18 02:24:50 +02009285 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009286 case PLANE_A:
9287 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9288 break;
9289 case PLANE_B:
9290 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9291 break;
9292 case PLANE_C:
9293 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9294 break;
9295 default:
9296 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009297 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009298 }
9299
Chris Wilsonffe74d72013-08-26 20:58:12 +01009300 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009301 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009302 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009303 /*
9304 * On Gen 8, SRM is now taking an extra dword to accommodate
9305 * 48bits addresses, and we need a NOOP for the batch size to
9306 * stay even.
9307 */
9308 if (IS_GEN8(dev))
9309 len += 2;
9310 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009311
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009312 /*
9313 * BSpec MI_DISPLAY_FLIP for IVB:
9314 * "The full packet must be contained within the same cache line."
9315 *
9316 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9317 * cacheline, if we ever start emitting more commands before
9318 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9319 * then do the cacheline alignment, and finally emit the
9320 * MI_DISPLAY_FLIP.
9321 */
9322 ret = intel_ring_cacheline_align(ring);
9323 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009324 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009325
Chris Wilsonffe74d72013-08-26 20:58:12 +01009326 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009327 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009328 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009329
Chris Wilsonffe74d72013-08-26 20:58:12 +01009330 /* Unmask the flip-done completion message. Note that the bspec says that
9331 * we should do this for both the BCS and RCS, and that we must not unmask
9332 * more than one flip event at any time (or ensure that one flip message
9333 * can be sent by waiting for flip-done prior to queueing new flips).
9334 * Experimentation says that BCS works despite DERRMR masking all
9335 * flip-done completion events and that unmasking all planes at once
9336 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9337 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9338 */
9339 if (ring->id == RCS) {
9340 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9341 intel_ring_emit(ring, DERRMR);
9342 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9343 DERRMR_PIPEB_PRI_FLIP_DONE |
9344 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009345 if (IS_GEN8(dev))
9346 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9347 MI_SRM_LRM_GLOBAL_GTT);
9348 else
9349 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9350 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009351 intel_ring_emit(ring, DERRMR);
9352 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009353 if (IS_GEN8(dev)) {
9354 intel_ring_emit(ring, 0);
9355 intel_ring_emit(ring, MI_NOOP);
9356 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009357 }
9358
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009359 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009360 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009361 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009362 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009363
9364 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009365 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009366 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009367}
9368
Sourab Gupta84c33a62014-06-02 16:47:17 +05309369static bool use_mmio_flip(struct intel_engine_cs *ring,
9370 struct drm_i915_gem_object *obj)
9371{
9372 /*
9373 * This is not being used for older platforms, because
9374 * non-availability of flip done interrupt forces us to use
9375 * CS flips. Older platforms derive flip done using some clever
9376 * tricks involving the flip_pending status bits and vblank irqs.
9377 * So using MMIO flips there would disrupt this mechanism.
9378 */
9379
Chris Wilson8e09bf82014-07-08 10:40:30 +01009380 if (ring == NULL)
9381 return true;
9382
Sourab Gupta84c33a62014-06-02 16:47:17 +05309383 if (INTEL_INFO(ring->dev)->gen < 5)
9384 return false;
9385
9386 if (i915.use_mmio_flip < 0)
9387 return false;
9388 else if (i915.use_mmio_flip > 0)
9389 return true;
Oscar Mateo14bf9932014-07-24 17:04:34 +01009390 else if (i915.enable_execlists)
9391 return true;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309392 else
9393 return ring != obj->ring;
9394}
9395
9396static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9397{
9398 struct drm_device *dev = intel_crtc->base.dev;
9399 struct drm_i915_private *dev_priv = dev->dev_private;
9400 struct intel_framebuffer *intel_fb =
9401 to_intel_framebuffer(intel_crtc->base.primary->fb);
9402 struct drm_i915_gem_object *obj = intel_fb->obj;
9403 u32 dspcntr;
9404 u32 reg;
9405
9406 intel_mark_page_flip_active(intel_crtc);
9407
9408 reg = DSPCNTR(intel_crtc->plane);
9409 dspcntr = I915_READ(reg);
9410
Damien Lespiauc5d97472014-10-25 00:11:11 +01009411 if (obj->tiling_mode != I915_TILING_NONE)
9412 dspcntr |= DISPPLANE_TILED;
9413 else
9414 dspcntr &= ~DISPPLANE_TILED;
9415
Sourab Gupta84c33a62014-06-02 16:47:17 +05309416 I915_WRITE(reg, dspcntr);
9417
9418 I915_WRITE(DSPSURF(intel_crtc->plane),
9419 intel_crtc->unpin_work->gtt_offset);
9420 POSTING_READ(DSPSURF(intel_crtc->plane));
9421}
9422
9423static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9424{
9425 struct intel_engine_cs *ring;
9426 int ret;
9427
9428 lockdep_assert_held(&obj->base.dev->struct_mutex);
9429
9430 if (!obj->last_write_seqno)
9431 return 0;
9432
9433 ring = obj->ring;
9434
9435 if (i915_seqno_passed(ring->get_seqno(ring, true),
9436 obj->last_write_seqno))
9437 return 0;
9438
9439 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9440 if (ret)
9441 return ret;
9442
9443 if (WARN_ON(!ring->irq_get(ring)))
9444 return 0;
9445
9446 return 1;
9447}
9448
9449void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9450{
9451 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9452 struct intel_crtc *intel_crtc;
9453 unsigned long irq_flags;
9454 u32 seqno;
9455
9456 seqno = ring->get_seqno(ring, false);
9457
9458 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9459 for_each_intel_crtc(ring->dev, intel_crtc) {
9460 struct intel_mmio_flip *mmio_flip;
9461
9462 mmio_flip = &intel_crtc->mmio_flip;
9463 if (mmio_flip->seqno == 0)
9464 continue;
9465
9466 if (ring->id != mmio_flip->ring_id)
9467 continue;
9468
9469 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9470 intel_do_mmio_flip(intel_crtc);
9471 mmio_flip->seqno = 0;
9472 ring->irq_put(ring);
9473 }
9474 }
9475 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9476}
9477
9478static int intel_queue_mmio_flip(struct drm_device *dev,
9479 struct drm_crtc *crtc,
9480 struct drm_framebuffer *fb,
9481 struct drm_i915_gem_object *obj,
9482 struct intel_engine_cs *ring,
9483 uint32_t flags)
9484{
9485 struct drm_i915_private *dev_priv = dev->dev_private;
9486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Sourab Gupta84c33a62014-06-02 16:47:17 +05309487 int ret;
9488
9489 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9490 return -EBUSY;
9491
9492 ret = intel_postpone_flip(obj);
9493 if (ret < 0)
9494 return ret;
9495 if (ret == 0) {
9496 intel_do_mmio_flip(intel_crtc);
9497 return 0;
9498 }
9499
Daniel Vetter24955f22014-09-15 14:55:32 +02009500 spin_lock_irq(&dev_priv->mmio_flip_lock);
Sourab Gupta84c33a62014-06-02 16:47:17 +05309501 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9502 intel_crtc->mmio_flip.ring_id = obj->ring->id;
Daniel Vetter24955f22014-09-15 14:55:32 +02009503 spin_unlock_irq(&dev_priv->mmio_flip_lock);
Sourab Gupta84c33a62014-06-02 16:47:17 +05309504
9505 /*
9506 * Double check to catch cases where irq fired before
9507 * mmio flip data was ready
9508 */
9509 intel_notify_mmio_flip(obj->ring);
9510 return 0;
9511}
9512
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009513static int intel_default_queue_flip(struct drm_device *dev,
9514 struct drm_crtc *crtc,
9515 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009516 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009517 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009518 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009519{
9520 return -ENODEV;
9521}
9522
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009523static bool __intel_pageflip_stall_check(struct drm_device *dev,
9524 struct drm_crtc *crtc)
9525{
9526 struct drm_i915_private *dev_priv = dev->dev_private;
9527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9528 struct intel_unpin_work *work = intel_crtc->unpin_work;
9529 u32 addr;
9530
9531 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9532 return true;
9533
9534 if (!work->enable_stall_check)
9535 return false;
9536
9537 if (work->flip_ready_vblank == 0) {
9538 if (work->flip_queued_ring &&
9539 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9540 work->flip_queued_seqno))
9541 return false;
9542
9543 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9544 }
9545
9546 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9547 return false;
9548
9549 /* Potential stall - if we see that the flip has happened,
9550 * assume a missed interrupt. */
9551 if (INTEL_INFO(dev)->gen >= 4)
9552 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9553 else
9554 addr = I915_READ(DSPADDR(intel_crtc->plane));
9555
9556 /* There is a potential issue here with a false positive after a flip
9557 * to the same address. We could address this by checking for a
9558 * non-incrementing frame counter.
9559 */
9560 return addr == work->gtt_offset;
9561}
9562
9563void intel_check_page_flip(struct drm_device *dev, int pipe)
9564{
9565 struct drm_i915_private *dev_priv = dev->dev_private;
9566 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterf3260382014-09-15 14:55:23 +02009568
9569 WARN_ON(!in_irq());
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009570
9571 if (crtc == NULL)
9572 return;
9573
Daniel Vetterf3260382014-09-15 14:55:23 +02009574 spin_lock(&dev->event_lock);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009575 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9576 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9577 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9578 page_flip_completed(intel_crtc);
9579 }
Daniel Vetterf3260382014-09-15 14:55:23 +02009580 spin_unlock(&dev->event_lock);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009581}
9582
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009583static int intel_crtc_page_flip(struct drm_crtc *crtc,
9584 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009585 struct drm_pending_vblank_event *event,
9586 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009587{
9588 struct drm_device *dev = crtc->dev;
9589 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009590 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009591 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02009593 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009594 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009595 struct intel_engine_cs *ring;
Chris Wilson52e68632010-08-08 10:15:59 +01009596 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009597
Matt Roper2ff8fde2014-07-08 07:50:07 -07009598 /*
9599 * drm_mode_page_flip_ioctl() should already catch this, but double
9600 * check to be safe. In the future we may enable pageflipping from
9601 * a disabled primary plane.
9602 */
9603 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9604 return -EBUSY;
9605
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009606 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009607 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009608 return -EINVAL;
9609
9610 /*
9611 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9612 * Note that pitch changes could also affect these register.
9613 */
9614 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009615 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9616 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009617 return -EINVAL;
9618
Chris Wilsonf900db42014-02-20 09:26:13 +00009619 if (i915_terminally_wedged(&dev_priv->gpu_error))
9620 goto out_hang;
9621
Daniel Vetterb14c5672013-09-19 12:18:32 +02009622 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009623 if (work == NULL)
9624 return -ENOMEM;
9625
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009626 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009627 work->crtc = crtc;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009628 work->old_fb_obj = intel_fb_obj(old_fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009629 INIT_WORK(&work->work, intel_unpin_work_fn);
9630
Daniel Vetter87b6b102014-05-15 15:33:46 +02009631 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009632 if (ret)
9633 goto free_work;
9634
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009635 /* We borrow the event spin lock for protecting unpin_work */
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009636 spin_lock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009637 if (intel_crtc->unpin_work) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009638 /* Before declaring the flip queue wedged, check if
9639 * the hardware completed the operation behind our backs.
9640 */
9641 if (__intel_pageflip_stall_check(dev, crtc)) {
9642 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9643 page_flip_completed(intel_crtc);
9644 } else {
9645 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009646 spin_unlock_irq(&dev->event_lock);
Chris Wilson468f0b42010-05-27 13:18:13 +01009647
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009648 drm_crtc_vblank_put(crtc);
9649 kfree(work);
9650 return -EBUSY;
9651 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009652 }
9653 intel_crtc->unpin_work = work;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009654 spin_unlock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009655
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009656 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9657 flush_workqueue(dev_priv->wq);
9658
Chris Wilson79158102012-05-23 11:13:58 +01009659 ret = i915_mutex_lock_interruptible(dev);
9660 if (ret)
9661 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009662
Jesse Barnes75dfca82010-02-10 15:09:44 -08009663 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009664 drm_gem_object_reference(&work->old_fb_obj->base);
9665 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009666
Matt Roperf4510a22014-04-01 15:22:40 -07009667 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009668
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009669 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009670
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009671 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009672 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009673
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009674 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Daniel Vettera071fa02014-06-18 23:28:09 +02009675 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009676
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009677 if (IS_VALLEYVIEW(dev)) {
9678 ring = &dev_priv->ring[BCS];
Chris Wilson8e09bf82014-07-08 10:40:30 +01009679 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9680 /* vlv: DISPLAY_FLIP fails to change tiling */
9681 ring = NULL;
Chris Wilson2a92d5b2014-07-08 10:40:29 +01009682 } else if (IS_IVYBRIDGE(dev)) {
9683 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009684 } else if (INTEL_INFO(dev)->gen >= 7) {
9685 ring = obj->ring;
9686 if (ring == NULL || ring->id != RCS)
9687 ring = &dev_priv->ring[BCS];
9688 } else {
9689 ring = &dev_priv->ring[RCS];
9690 }
9691
9692 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009693 if (ret)
9694 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009695
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009696 work->gtt_offset =
9697 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9698
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009699 if (use_mmio_flip(ring, obj)) {
Sourab Gupta84c33a62014-06-02 16:47:17 +05309700 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9701 page_flip_flags);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009702 if (ret)
9703 goto cleanup_unpin;
9704
9705 work->flip_queued_seqno = obj->last_write_seqno;
9706 work->flip_queued_ring = obj->ring;
9707 } else {
Sourab Gupta84c33a62014-06-02 16:47:17 +05309708 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009709 page_flip_flags);
9710 if (ret)
9711 goto cleanup_unpin;
9712
9713 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9714 work->flip_queued_ring = ring;
9715 }
9716
9717 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9718 work->enable_stall_check = true;
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009719
Daniel Vettera071fa02014-06-18 23:28:09 +02009720 i915_gem_track_fb(work->old_fb_obj, obj,
9721 INTEL_FRONTBUFFER_PRIMARY(pipe));
9722
Chris Wilson7782de32011-07-08 12:22:41 +01009723 intel_disable_fbc(dev);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009724 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009725 mutex_unlock(&dev->struct_mutex);
9726
Jesse Barnese5510fa2010-07-01 16:48:37 -07009727 trace_i915_flip_request(intel_crtc->plane, obj);
9728
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009729 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009730
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009731cleanup_unpin:
9732 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009733cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009734 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009735 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009736 drm_gem_object_unreference(&work->old_fb_obj->base);
9737 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009738 mutex_unlock(&dev->struct_mutex);
9739
Chris Wilson79158102012-05-23 11:13:58 +01009740cleanup:
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009741 spin_lock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +01009742 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009743 spin_unlock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +01009744
Daniel Vetter87b6b102014-05-15 15:33:46 +02009745 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009746free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009747 kfree(work);
9748
Chris Wilsonf900db42014-02-20 09:26:13 +00009749 if (ret == -EIO) {
9750out_hang:
9751 intel_crtc_wait_for_pending_flips(crtc);
9752 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +01009753 if (ret == 0 && event) {
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009754 spin_lock_irq(&dev->event_lock);
Daniel Vettera071fa02014-06-18 23:28:09 +02009755 drm_send_vblank_event(dev, pipe, event);
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009756 spin_unlock_irq(&dev->event_lock);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +01009757 }
Chris Wilsonf900db42014-02-20 09:26:13 +00009758 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009759 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009760}
9761
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009762static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009763 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9764 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009765};
9766
Daniel Vetter9a935852012-07-05 22:34:27 +02009767/**
9768 * intel_modeset_update_staged_output_state
9769 *
9770 * Updates the staged output configuration state, e.g. after we've read out the
9771 * current hw state.
9772 */
9773static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9774{
Ville Syrjälä76688512014-01-10 11:28:06 +02009775 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009776 struct intel_encoder *encoder;
9777 struct intel_connector *connector;
9778
9779 list_for_each_entry(connector, &dev->mode_config.connector_list,
9780 base.head) {
9781 connector->new_encoder =
9782 to_intel_encoder(connector->base.encoder);
9783 }
9784
Damien Lespiaub2784e12014-08-05 11:29:37 +01009785 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009786 encoder->new_crtc =
9787 to_intel_crtc(encoder->base.crtc);
9788 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009789
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009790 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009791 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009792
9793 if (crtc->new_enabled)
9794 crtc->new_config = &crtc->config;
9795 else
9796 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009797 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009798}
9799
9800/**
9801 * intel_modeset_commit_output_state
9802 *
9803 * This function copies the stage display pipe configuration to the real one.
9804 */
9805static void intel_modeset_commit_output_state(struct drm_device *dev)
9806{
Ville Syrjälä76688512014-01-10 11:28:06 +02009807 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009808 struct intel_encoder *encoder;
9809 struct intel_connector *connector;
9810
9811 list_for_each_entry(connector, &dev->mode_config.connector_list,
9812 base.head) {
9813 connector->base.encoder = &connector->new_encoder->base;
9814 }
9815
Damien Lespiaub2784e12014-08-05 11:29:37 +01009816 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009817 encoder->base.crtc = &encoder->new_crtc->base;
9818 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009819
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009820 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009821 crtc->base.enabled = crtc->new_enabled;
9822 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009823}
9824
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009825static void
Robin Schroereba905b2014-05-18 02:24:50 +02009826connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009827 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009828{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009829 int bpp = pipe_config->pipe_bpp;
9830
9831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9832 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009833 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009834
9835 /* Don't use an invalid EDID bpc value */
9836 if (connector->base.display_info.bpc &&
9837 connector->base.display_info.bpc * 3 < bpp) {
9838 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9839 bpp, connector->base.display_info.bpc*3);
9840 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9841 }
9842
9843 /* Clamp bpp to 8 on screens without EDID 1.4 */
9844 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9845 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9846 bpp);
9847 pipe_config->pipe_bpp = 24;
9848 }
9849}
9850
9851static int
9852compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9853 struct drm_framebuffer *fb,
9854 struct intel_crtc_config *pipe_config)
9855{
9856 struct drm_device *dev = crtc->base.dev;
9857 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009858 int bpp;
9859
Daniel Vetterd42264b2013-03-28 16:38:08 +01009860 switch (fb->pixel_format) {
9861 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009862 bpp = 8*3; /* since we go through a colormap */
9863 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009864 case DRM_FORMAT_XRGB1555:
9865 case DRM_FORMAT_ARGB1555:
9866 /* checked in intel_framebuffer_init already */
9867 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9868 return -EINVAL;
9869 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009870 bpp = 6*3; /* min is 18bpp */
9871 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009872 case DRM_FORMAT_XBGR8888:
9873 case DRM_FORMAT_ABGR8888:
9874 /* checked in intel_framebuffer_init already */
9875 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9876 return -EINVAL;
9877 case DRM_FORMAT_XRGB8888:
9878 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009879 bpp = 8*3;
9880 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009881 case DRM_FORMAT_XRGB2101010:
9882 case DRM_FORMAT_ARGB2101010:
9883 case DRM_FORMAT_XBGR2101010:
9884 case DRM_FORMAT_ABGR2101010:
9885 /* checked in intel_framebuffer_init already */
9886 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01009887 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009888 bpp = 10*3;
9889 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01009890 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009891 default:
9892 DRM_DEBUG_KMS("unsupported depth\n");
9893 return -EINVAL;
9894 }
9895
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009896 pipe_config->pipe_bpp = bpp;
9897
9898 /* Clamp display bpp to EDID value */
9899 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009900 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02009901 if (!connector->new_encoder ||
9902 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009903 continue;
9904
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009905 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009906 }
9907
9908 return bpp;
9909}
9910
Daniel Vetter644db712013-09-19 14:53:58 +02009911static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9912{
9913 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9914 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +01009915 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +02009916 mode->crtc_hdisplay, mode->crtc_hsync_start,
9917 mode->crtc_hsync_end, mode->crtc_htotal,
9918 mode->crtc_vdisplay, mode->crtc_vsync_start,
9919 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9920}
9921
Daniel Vetterc0b03412013-05-28 12:05:54 +02009922static void intel_dump_pipe_config(struct intel_crtc *crtc,
9923 struct intel_crtc_config *pipe_config,
9924 const char *context)
9925{
9926 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9927 context, pipe_name(crtc->pipe));
9928
9929 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9930 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9931 pipe_config->pipe_bpp, pipe_config->dither);
9932 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9933 pipe_config->has_pch_encoder,
9934 pipe_config->fdi_lanes,
9935 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9936 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9937 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009938 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9939 pipe_config->has_dp_encoder,
9940 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9941 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9942 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009943
9944 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9945 pipe_config->has_dp_encoder,
9946 pipe_config->dp_m2_n2.gmch_m,
9947 pipe_config->dp_m2_n2.gmch_n,
9948 pipe_config->dp_m2_n2.link_m,
9949 pipe_config->dp_m2_n2.link_n,
9950 pipe_config->dp_m2_n2.tu);
9951
Daniel Vetterc0b03412013-05-28 12:05:54 +02009952 DRM_DEBUG_KMS("requested mode:\n");
9953 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9954 DRM_DEBUG_KMS("adjusted mode:\n");
9955 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +02009956 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009957 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009958 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9959 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009960 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9961 pipe_config->gmch_pfit.control,
9962 pipe_config->gmch_pfit.pgm_ratios,
9963 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009964 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +02009965 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009966 pipe_config->pch_pfit.size,
9967 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009968 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03009969 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009970}
9971
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009972static bool encoders_cloneable(const struct intel_encoder *a,
9973 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009974{
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009975 /* masks could be asymmetric, so check both ways */
9976 return a == b || (a->cloneable & (1 << b->type) &&
9977 b->cloneable & (1 << a->type));
9978}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009979
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009980static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9981 struct intel_encoder *encoder)
9982{
9983 struct drm_device *dev = crtc->base.dev;
9984 struct intel_encoder *source_encoder;
9985
Damien Lespiaub2784e12014-08-05 11:29:37 +01009986 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009987 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009988 continue;
9989
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009990 if (!encoders_cloneable(encoder, source_encoder))
9991 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009992 }
9993
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009994 return true;
9995}
9996
9997static bool check_encoder_cloning(struct intel_crtc *crtc)
9998{
9999 struct drm_device *dev = crtc->base.dev;
10000 struct intel_encoder *encoder;
10001
Damien Lespiaub2784e12014-08-05 11:29:37 +010010002 for_each_intel_encoder(dev, encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010003 if (encoder->new_crtc != crtc)
10004 continue;
10005
10006 if (!check_single_encoder_cloning(crtc, encoder))
10007 return false;
10008 }
10009
10010 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010011}
10012
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010013static struct intel_crtc_config *
10014intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010015 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010016 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +020010017{
10018 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +020010019 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010020 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +010010021 int plane_bpp, ret = -EINVAL;
10022 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020010023
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010024 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010025 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10026 return ERR_PTR(-EINVAL);
10027 }
10028
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010029 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10030 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020010031 return ERR_PTR(-ENOMEM);
10032
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010033 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10034 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010035
Daniel Vettere143a212013-07-04 12:01:15 +020010036 pipe_config->cpu_transcoder =
10037 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010038 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010039
Imre Deak2960bc92013-07-30 13:36:32 +030010040 /*
10041 * Sanitize sync polarity flags based on requested ones. If neither
10042 * positive or negative polarity is requested, treat this as meaning
10043 * negative polarity.
10044 */
10045 if (!(pipe_config->adjusted_mode.flags &
10046 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10047 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10048
10049 if (!(pipe_config->adjusted_mode.flags &
10050 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10051 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10052
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010053 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10054 * plane pixel format and any sink constraints into account. Returns the
10055 * source plane bpp so that dithering can be selected on mismatches
10056 * after encoders and crtc also have had their say. */
10057 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10058 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010059 if (plane_bpp < 0)
10060 goto fail;
10061
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030010062 /*
10063 * Determine the real pipe dimensions. Note that stereo modes can
10064 * increase the actual pipe size due to the frame doubling and
10065 * insertion of additional space for blanks between the frame. This
10066 * is stored in the crtc timings. We use the requested mode to do this
10067 * computation to clearly distinguish it from the adjusted mode, which
10068 * can be changed by the connectors in the below retry loop.
10069 */
10070 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10071 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10072 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10073
Daniel Vettere29c22c2013-02-21 00:00:16 +010010074encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020010075 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020010076 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020010077 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010078
Daniel Vetter135c81b2013-07-21 21:37:09 +020010079 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +010010080 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020010081
Daniel Vetter7758a112012-07-08 19:40:39 +020010082 /* Pass our mode to the connectors and the CRTC to give them a chance to
10083 * adjust it according to limitations or connector properties, and also
10084 * a chance to reject the mode entirely.
10085 */
Damien Lespiaub2784e12014-08-05 11:29:37 +010010086 for_each_intel_encoder(dev, encoder) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010087
10088 if (&encoder->new_crtc->base != crtc)
10089 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +010010090
Daniel Vetterefea6e82013-07-21 21:36:59 +020010091 if (!(encoder->compute_config(encoder, pipe_config))) {
10092 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020010093 goto fail;
10094 }
10095 }
10096
Daniel Vetterff9a6752013-06-01 17:16:21 +020010097 /* Set default port clock if not overwritten by the encoder. Needs to be
10098 * done afterwards in case the encoder adjusts the mode. */
10099 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +010010100 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10101 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010102
Daniel Vettera43f6e02013-06-07 23:10:32 +020010103 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010104 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010105 DRM_DEBUG_KMS("CRTC fixup failed\n");
10106 goto fail;
10107 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010010108
10109 if (ret == RETRY) {
10110 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10111 ret = -EINVAL;
10112 goto fail;
10113 }
10114
10115 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10116 retry = false;
10117 goto encoder_retry;
10118 }
10119
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010120 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10121 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10122 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10123
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010124 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +020010125fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010126 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010127 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +020010128}
10129
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010130/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10131 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10132static void
10133intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10134 unsigned *prepare_pipes, unsigned *disable_pipes)
10135{
10136 struct intel_crtc *intel_crtc;
10137 struct drm_device *dev = crtc->dev;
10138 struct intel_encoder *encoder;
10139 struct intel_connector *connector;
10140 struct drm_crtc *tmp_crtc;
10141
10142 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10143
10144 /* Check which crtcs have changed outputs connected to them, these need
10145 * to be part of the prepare_pipes mask. We don't (yet) support global
10146 * modeset across multiple crtcs, so modeset_pipes will only have one
10147 * bit set at most. */
10148 list_for_each_entry(connector, &dev->mode_config.connector_list,
10149 base.head) {
10150 if (connector->base.encoder == &connector->new_encoder->base)
10151 continue;
10152
10153 if (connector->base.encoder) {
10154 tmp_crtc = connector->base.encoder->crtc;
10155
10156 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10157 }
10158
10159 if (connector->new_encoder)
10160 *prepare_pipes |=
10161 1 << connector->new_encoder->new_crtc->pipe;
10162 }
10163
Damien Lespiaub2784e12014-08-05 11:29:37 +010010164 for_each_intel_encoder(dev, encoder) {
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010165 if (encoder->base.crtc == &encoder->new_crtc->base)
10166 continue;
10167
10168 if (encoder->base.crtc) {
10169 tmp_crtc = encoder->base.crtc;
10170
10171 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10172 }
10173
10174 if (encoder->new_crtc)
10175 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10176 }
10177
Ville Syrjälä76688512014-01-10 11:28:06 +020010178 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010179 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010180 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010181 continue;
10182
Ville Syrjälä76688512014-01-10 11:28:06 +020010183 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010184 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +020010185 else
10186 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010187 }
10188
10189
10190 /* set_mode is also used to update properties on life display pipes. */
10191 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +020010192 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010193 *prepare_pipes |= 1 << intel_crtc->pipe;
10194
Daniel Vetterb6c51642013-04-12 18:48:43 +020010195 /*
10196 * For simplicity do a full modeset on any pipe where the output routing
10197 * changed. We could be more clever, but that would require us to be
10198 * more careful with calling the relevant encoder->mode_set functions.
10199 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010200 if (*prepare_pipes)
10201 *modeset_pipes = *prepare_pipes;
10202
10203 /* ... and mask these out. */
10204 *modeset_pipes &= ~(*disable_pipes);
10205 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +020010206
10207 /*
10208 * HACK: We don't (yet) fully support global modesets. intel_set_config
10209 * obies this rule, but the modeset restore mode of
10210 * intel_modeset_setup_hw_state does not.
10211 */
10212 *modeset_pipes &= 1 << intel_crtc->pipe;
10213 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +020010214
10215 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10216 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010217}
10218
Daniel Vetterea9d7582012-07-10 10:42:52 +020010219static bool intel_crtc_in_use(struct drm_crtc *crtc)
10220{
10221 struct drm_encoder *encoder;
10222 struct drm_device *dev = crtc->dev;
10223
10224 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10225 if (encoder->crtc == crtc)
10226 return true;
10227
10228 return false;
10229}
10230
10231static void
10232intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10233{
Daniel Vetterba41c0de2014-11-03 15:04:55 +010010234 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterea9d7582012-07-10 10:42:52 +020010235 struct intel_encoder *intel_encoder;
10236 struct intel_crtc *intel_crtc;
10237 struct drm_connector *connector;
10238
Daniel Vetterba41c0de2014-11-03 15:04:55 +010010239 intel_shared_dpll_commit(dev_priv);
10240
Damien Lespiaub2784e12014-08-05 11:29:37 +010010241 for_each_intel_encoder(dev, intel_encoder) {
Daniel Vetterea9d7582012-07-10 10:42:52 +020010242 if (!intel_encoder->base.crtc)
10243 continue;
10244
10245 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10246
10247 if (prepare_pipes & (1 << intel_crtc->pipe))
10248 intel_encoder->connectors_active = false;
10249 }
10250
10251 intel_modeset_commit_output_state(dev);
10252
Ville Syrjälä76688512014-01-10 11:28:06 +020010253 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010254 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010255 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010256 WARN_ON(intel_crtc->new_config &&
10257 intel_crtc->new_config != &intel_crtc->config);
10258 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010259 }
10260
10261 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10262 if (!connector->encoder || !connector->encoder->crtc)
10263 continue;
10264
10265 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10266
10267 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +020010268 struct drm_property *dpms_property =
10269 dev->mode_config.dpms_property;
10270
Daniel Vetterea9d7582012-07-10 10:42:52 +020010271 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -050010272 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +020010273 dpms_property,
10274 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010275
10276 intel_encoder = to_intel_encoder(connector->encoder);
10277 intel_encoder->connectors_active = true;
10278 }
10279 }
10280
10281}
10282
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010283static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010284{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010285 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010286
10287 if (clock1 == clock2)
10288 return true;
10289
10290 if (!clock1 || !clock2)
10291 return false;
10292
10293 diff = abs(clock1 - clock2);
10294
10295 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10296 return true;
10297
10298 return false;
10299}
10300
Daniel Vetter25c5b262012-07-08 22:08:04 +020010301#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10302 list_for_each_entry((intel_crtc), \
10303 &(dev)->mode_config.crtc_list, \
10304 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +020010305 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020010306
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010307static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010308intel_pipe_config_compare(struct drm_device *dev,
10309 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010310 struct intel_crtc_config *pipe_config)
10311{
Daniel Vetter66e985c2013-06-05 13:34:20 +020010312#define PIPE_CONF_CHECK_X(name) \
10313 if (current_config->name != pipe_config->name) { \
10314 DRM_ERROR("mismatch in " #name " " \
10315 "(expected 0x%08x, found 0x%08x)\n", \
10316 current_config->name, \
10317 pipe_config->name); \
10318 return false; \
10319 }
10320
Daniel Vetter08a24032013-04-19 11:25:34 +020010321#define PIPE_CONF_CHECK_I(name) \
10322 if (current_config->name != pipe_config->name) { \
10323 DRM_ERROR("mismatch in " #name " " \
10324 "(expected %i, found %i)\n", \
10325 current_config->name, \
10326 pipe_config->name); \
10327 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010010328 }
10329
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010330/* This is required for BDW+ where there is only one set of registers for
10331 * switching between high and low RR.
10332 * This macro can be used whenever a comparison has to be made between one
10333 * hw state and multiple sw state variables.
10334 */
10335#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10336 if ((current_config->name != pipe_config->name) && \
10337 (current_config->alt_name != pipe_config->name)) { \
10338 DRM_ERROR("mismatch in " #name " " \
10339 "(expected %i or %i, found %i)\n", \
10340 current_config->name, \
10341 current_config->alt_name, \
10342 pipe_config->name); \
10343 return false; \
10344 }
10345
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010346#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10347 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -070010348 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010349 "(expected %i, found %i)\n", \
10350 current_config->name & (mask), \
10351 pipe_config->name & (mask)); \
10352 return false; \
10353 }
10354
Ville Syrjälä5e550652013-09-06 23:29:07 +030010355#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10356 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10357 DRM_ERROR("mismatch in " #name " " \
10358 "(expected %i, found %i)\n", \
10359 current_config->name, \
10360 pipe_config->name); \
10361 return false; \
10362 }
10363
Daniel Vetterbb760062013-06-06 14:55:52 +020010364#define PIPE_CONF_QUIRK(quirk) \
10365 ((current_config->quirks | pipe_config->quirks) & (quirk))
10366
Daniel Vettereccb1402013-05-22 00:50:22 +020010367 PIPE_CONF_CHECK_I(cpu_transcoder);
10368
Daniel Vetter08a24032013-04-19 11:25:34 +020010369 PIPE_CONF_CHECK_I(has_pch_encoder);
10370 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +020010371 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10372 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10373 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10374 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10375 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +020010376
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010377 PIPE_CONF_CHECK_I(has_dp_encoder);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010378
10379 if (INTEL_INFO(dev)->gen < 8) {
10380 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10381 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10382 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10383 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10384 PIPE_CONF_CHECK_I(dp_m_n.tu);
10385
10386 if (current_config->has_drrs) {
10387 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10388 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10389 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10390 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10391 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10392 }
10393 } else {
10394 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10395 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10396 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10397 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10398 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10399 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010400
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010401 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10402 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10403 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10404 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10405 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10406 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10407
10408 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10409 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10410 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10411 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10412 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10413 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10414
Daniel Vetterc93f54c2013-06-27 19:47:19 +020010415 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +020010416 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020010417 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10418 IS_VALLEYVIEW(dev))
10419 PIPE_CONF_CHECK_I(limited_color_range);
Daniel Vetter6c49f242013-06-06 12:45:25 +020010420
Daniel Vetter9ed109a2014-04-24 23:54:52 +020010421 PIPE_CONF_CHECK_I(has_audio);
10422
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010423 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10424 DRM_MODE_FLAG_INTERLACE);
10425
Daniel Vetterbb760062013-06-06 14:55:52 +020010426 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10427 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10428 DRM_MODE_FLAG_PHSYNC);
10429 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10430 DRM_MODE_FLAG_NHSYNC);
10431 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10432 DRM_MODE_FLAG_PVSYNC);
10433 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10434 DRM_MODE_FLAG_NVSYNC);
10435 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010436
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010437 PIPE_CONF_CHECK_I(pipe_src_w);
10438 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010439
Daniel Vetter99535992014-04-13 12:00:33 +020010440 /*
10441 * FIXME: BIOS likes to set up a cloned config with lvds+external
10442 * screen. Since we don't yet re-compute the pipe config when moving
10443 * just the lvds port away to another pipe the sw tracking won't match.
10444 *
10445 * Proper atomic modesets with recomputed global state will fix this.
10446 * Until then just don't check gmch state for inherited modes.
10447 */
10448 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10449 PIPE_CONF_CHECK_I(gmch_pfit.control);
10450 /* pfit ratios are autocomputed by the hw on gen4+ */
10451 if (INTEL_INFO(dev)->gen < 4)
10452 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10453 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10454 }
10455
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010456 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10457 if (current_config->pch_pfit.enabled) {
10458 PIPE_CONF_CHECK_I(pch_pfit.pos);
10459 PIPE_CONF_CHECK_I(pch_pfit.size);
10460 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010461
Jesse Barnese59150d2014-01-07 13:30:45 -080010462 /* BDW+ don't expose a synchronous way to read the state */
10463 if (IS_HASWELL(dev))
10464 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010465
Ville Syrjälä282740f2013-09-04 18:30:03 +030010466 PIPE_CONF_CHECK_I(double_wide);
10467
Daniel Vetter26804af2014-06-25 22:01:55 +030010468 PIPE_CONF_CHECK_X(ddi_pll_sel);
10469
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010470 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010471 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010472 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010473 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10474 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010475 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010476
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010477 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10478 PIPE_CONF_CHECK_I(pipe_bpp);
10479
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010480 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10481 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010482
Daniel Vetter66e985c2013-06-05 13:34:20 +020010483#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010484#undef PIPE_CONF_CHECK_I
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010485#undef PIPE_CONF_CHECK_I_ALT
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010486#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010487#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010488#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010489
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010490 return true;
10491}
10492
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010493static void
10494check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010495{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010496 struct intel_connector *connector;
10497
10498 list_for_each_entry(connector, &dev->mode_config.connector_list,
10499 base.head) {
10500 /* This also checks the encoder/connector hw state with the
10501 * ->get_hw_state callbacks. */
10502 intel_connector_check_state(connector);
10503
10504 WARN(&connector->new_encoder->base != connector->base.encoder,
10505 "connector's staged encoder doesn't match current encoder\n");
10506 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010507}
10508
10509static void
10510check_encoder_state(struct drm_device *dev)
10511{
10512 struct intel_encoder *encoder;
10513 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010514
Damien Lespiaub2784e12014-08-05 11:29:37 +010010515 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010516 bool enabled = false;
10517 bool active = false;
10518 enum pipe pipe, tracked_pipe;
10519
10520 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10521 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030010522 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010523
10524 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10525 "encoder's stage crtc doesn't match current crtc\n");
10526 WARN(encoder->connectors_active && !encoder->base.crtc,
10527 "encoder's active_connectors set, but no crtc\n");
10528
10529 list_for_each_entry(connector, &dev->mode_config.connector_list,
10530 base.head) {
10531 if (connector->base.encoder != &encoder->base)
10532 continue;
10533 enabled = true;
10534 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10535 active = true;
10536 }
Dave Airlie0e32b392014-05-02 14:02:48 +100010537 /*
10538 * for MST connectors if we unplug the connector is gone
10539 * away but the encoder is still connected to a crtc
10540 * until a modeset happens in response to the hotplug.
10541 */
10542 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10543 continue;
10544
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010545 WARN(!!encoder->base.crtc != enabled,
10546 "encoder's enabled state mismatch "
10547 "(expected %i, found %i)\n",
10548 !!encoder->base.crtc, enabled);
10549 WARN(active && !encoder->base.crtc,
10550 "active encoder with no crtc\n");
10551
10552 WARN(encoder->connectors_active != active,
10553 "encoder's computed active state doesn't match tracked active state "
10554 "(expected %i, found %i)\n", active, encoder->connectors_active);
10555
10556 active = encoder->get_hw_state(encoder, &pipe);
10557 WARN(active != encoder->connectors_active,
10558 "encoder's hw state doesn't match sw tracking "
10559 "(expected %i, found %i)\n",
10560 encoder->connectors_active, active);
10561
10562 if (!encoder->base.crtc)
10563 continue;
10564
10565 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10566 WARN(active && pipe != tracked_pipe,
10567 "active encoder's pipe doesn't match"
10568 "(expected %i, found %i)\n",
10569 tracked_pipe, pipe);
10570
10571 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010572}
10573
10574static void
10575check_crtc_state(struct drm_device *dev)
10576{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010577 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010578 struct intel_crtc *crtc;
10579 struct intel_encoder *encoder;
10580 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010581
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010582 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010583 bool enabled = false;
10584 bool active = false;
10585
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010586 memset(&pipe_config, 0, sizeof(pipe_config));
10587
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010588 DRM_DEBUG_KMS("[CRTC:%d]\n",
10589 crtc->base.base.id);
10590
10591 WARN(crtc->active && !crtc->base.enabled,
10592 "active crtc, but not enabled in sw tracking\n");
10593
Damien Lespiaub2784e12014-08-05 11:29:37 +010010594 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010595 if (encoder->base.crtc != &crtc->base)
10596 continue;
10597 enabled = true;
10598 if (encoder->connectors_active)
10599 active = true;
10600 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010601
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010602 WARN(active != crtc->active,
10603 "crtc's computed active state doesn't match tracked active state "
10604 "(expected %i, found %i)\n", active, crtc->active);
10605 WARN(enabled != crtc->base.enabled,
10606 "crtc's computed enabled state doesn't match tracked enabled state "
10607 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10608
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010609 active = dev_priv->display.get_pipe_config(crtc,
10610 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010611
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030010612 /* hw state is inconsistent with the pipe quirk */
10613 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10614 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetterd62cf622013-05-29 10:41:29 +020010615 active = crtc->active;
10616
Damien Lespiaub2784e12014-08-05 11:29:37 +010010617 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010618 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010619 if (encoder->base.crtc != &crtc->base)
10620 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010621 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010622 encoder->get_config(encoder, &pipe_config);
10623 }
10624
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010625 WARN(crtc->active != active,
10626 "crtc active state doesn't match with hw state "
10627 "(expected %i, found %i)\n", crtc->active, active);
10628
Daniel Vetterc0b03412013-05-28 12:05:54 +020010629 if (active &&
10630 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10631 WARN(1, "pipe state doesn't match!\n");
10632 intel_dump_pipe_config(crtc, &pipe_config,
10633 "[hw state]");
10634 intel_dump_pipe_config(crtc, &crtc->config,
10635 "[sw state]");
10636 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010637 }
10638}
10639
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010640static void
10641check_shared_dpll_state(struct drm_device *dev)
10642{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010643 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010644 struct intel_crtc *crtc;
10645 struct intel_dpll_hw_state dpll_hw_state;
10646 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010647
10648 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10649 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10650 int enabled_crtcs = 0, active_crtcs = 0;
10651 bool active;
10652
10653 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10654
10655 DRM_DEBUG_KMS("%s\n", pll->name);
10656
10657 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10658
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010659 WARN(pll->active > hweight32(pll->config.crtc_mask),
Daniel Vetter53589012013-06-05 13:34:16 +020010660 "more active pll users than references: %i vs %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010661 pll->active, hweight32(pll->config.crtc_mask));
Daniel Vetter53589012013-06-05 13:34:16 +020010662 WARN(pll->active && !pll->on,
10663 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010664 WARN(pll->on && !pll->active,
10665 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010666 WARN(pll->on != active,
10667 "pll on state mismatch (expected %i, found %i)\n",
10668 pll->on, active);
10669
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010670 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010671 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10672 enabled_crtcs++;
10673 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10674 active_crtcs++;
10675 }
10676 WARN(pll->active != active_crtcs,
10677 "pll active crtcs mismatch (expected %i, found %i)\n",
10678 pll->active, active_crtcs);
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010679 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
Daniel Vetter53589012013-06-05 13:34:16 +020010680 "pll enabled crtcs mismatch (expected %i, found %i)\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010681 hweight32(pll->config.crtc_mask), enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010682
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010683 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
Daniel Vetter66e985c2013-06-05 13:34:20 +020010684 sizeof(dpll_hw_state)),
10685 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010686 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010687}
10688
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010689void
10690intel_modeset_check_state(struct drm_device *dev)
10691{
10692 check_connector_state(dev);
10693 check_encoder_state(dev);
10694 check_crtc_state(dev);
10695 check_shared_dpll_state(dev);
10696}
10697
Ville Syrjälä18442d02013-09-13 16:00:08 +030010698void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10699 int dotclock)
10700{
10701 /*
10702 * FDI already provided one idea for the dotclock.
10703 * Yell if the encoder disagrees.
10704 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010705 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010706 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010707 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010708}
10709
Ville Syrjälä80715b22014-05-15 20:23:23 +030010710static void update_scanline_offset(struct intel_crtc *crtc)
10711{
10712 struct drm_device *dev = crtc->base.dev;
10713
10714 /*
10715 * The scanline counter increments at the leading edge of hsync.
10716 *
10717 * On most platforms it starts counting from vtotal-1 on the
10718 * first active line. That means the scanline counter value is
10719 * always one less than what we would expect. Ie. just after
10720 * start of vblank, which also occurs at start of hsync (on the
10721 * last active line), the scanline counter will read vblank_start-1.
10722 *
10723 * On gen2 the scanline counter starts counting from 1 instead
10724 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10725 * to keep the value positive), instead of adding one.
10726 *
10727 * On HSW+ the behaviour of the scanline counter depends on the output
10728 * type. For DP ports it behaves like most other platforms, but on HDMI
10729 * there's an extra 1 line difference. So we need to add two instead of
10730 * one to the value.
10731 */
10732 if (IS_GEN2(dev)) {
10733 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10734 int vtotal;
10735
10736 vtotal = mode->crtc_vtotal;
10737 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10738 vtotal /= 2;
10739
10740 crtc->scanline_offset = vtotal - 1;
10741 } else if (HAS_DDI(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +030010742 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
Ville Syrjälä80715b22014-05-15 20:23:23 +030010743 crtc->scanline_offset = 2;
10744 } else
10745 crtc->scanline_offset = 1;
10746}
10747
Daniel Vetterf30da182013-04-11 20:22:50 +020010748static int __intel_set_mode(struct drm_crtc *crtc,
10749 struct drm_display_mode *mode,
10750 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +020010751{
10752 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010753 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010754 struct drm_display_mode *saved_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010755 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010756 struct intel_crtc *intel_crtc;
10757 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010758 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010759
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010760 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010761 if (!saved_mode)
10762 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010763
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010764 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +020010765 &prepare_pipes, &disable_pipes);
10766
Tim Gardner3ac18232012-12-07 07:54:26 -070010767 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010768
Daniel Vetter25c5b262012-07-08 22:08:04 +020010769 /* Hack: Because we don't (yet) support global modeset on multiple
10770 * crtcs, we don't keep track of the new mode for more than one crtc.
10771 * Hence simply check whether any bit is set in modeset_pipes in all the
10772 * pieces of code that are not yet converted to deal with mutliple crtcs
10773 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010774 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010775 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010776 if (IS_ERR(pipe_config)) {
10777 ret = PTR_ERR(pipe_config);
10778 pipe_config = NULL;
10779
Tim Gardner3ac18232012-12-07 07:54:26 -070010780 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010781 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020010782 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10783 "[modeset]");
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010784 to_intel_crtc(crtc)->new_config = pipe_config;
Daniel Vettera6778b32012-07-02 09:56:42 +020010785 }
10786
Jesse Barnes30a970c2013-11-04 13:48:12 -080010787 /*
10788 * See if the config requires any additional preparation, e.g.
10789 * to adjust global state with pipes off. We need to do this
10790 * here so we can get the modeset_pipe updated config for the new
10791 * mode set on this crtc. For other crtcs we need to use the
10792 * adjusted_mode bits in the crtc directly.
10793 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010794 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010795 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010796
Ville Syrjäläc164f832013-11-05 22:34:12 +020010797 /* may have added more to prepare_pipes than we should */
10798 prepare_pipes &= ~disable_pipes;
10799 }
10800
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +020010801 if (dev_priv->display.crtc_compute_clock) {
10802 unsigned clear_pipes = modeset_pipes | disable_pipes;
10803
10804 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10805 if (ret)
10806 goto done;
10807
10808 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10809 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10810 if (ret) {
10811 intel_shared_dpll_abort_config(dev_priv);
10812 goto done;
10813 }
10814 }
10815 }
10816
Daniel Vetter460da9162013-03-27 00:44:51 +010010817 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10818 intel_crtc_disable(&intel_crtc->base);
10819
Daniel Vetterea9d7582012-07-10 10:42:52 +020010820 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10821 if (intel_crtc->base.enabled)
10822 dev_priv->display.crtc_disable(&intel_crtc->base);
10823 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010824
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010825 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10826 * to set it here already despite that we pass it down the callchain.
10827 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010828 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010829 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010830 /* mode_set/enable/disable functions rely on a correct pipe
10831 * config. */
10832 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010833 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010834
10835 /*
10836 * Calculate and store various constants which
10837 * are later needed by vblank and swap-completion
10838 * timestamping. They are derived from true hwmode.
10839 */
10840 drm_calc_timestamping_constants(crtc,
10841 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010842 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010843
Daniel Vetterea9d7582012-07-10 10:42:52 +020010844 /* Only after disabling all output pipelines that will be changed can we
10845 * update the the output configuration. */
10846 intel_modeset_update_state(dev, prepare_pipes);
10847
Daniel Vetter47fab732012-10-26 10:58:18 +020010848 if (dev_priv->display.modeset_global_resources)
10849 dev_priv->display.modeset_global_resources(dev);
10850
Daniel Vettera6778b32012-07-02 09:56:42 +020010851 /* Set up the DPLL and any encoders state that needs to adjust or depend
10852 * on the DPLL.
10853 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010854 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070010855 struct drm_framebuffer *old_fb = crtc->primary->fb;
10856 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10857 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Daniel Vetter4c107942014-04-24 23:55:05 +020010858
10859 mutex_lock(&dev->struct_mutex);
10860 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vettera071fa02014-06-18 23:28:09 +020010861 obj,
Daniel Vetter4c107942014-04-24 23:55:05 +020010862 NULL);
10863 if (ret != 0) {
10864 DRM_ERROR("pin & fence failed\n");
10865 mutex_unlock(&dev->struct_mutex);
10866 goto done;
10867 }
Matt Roper2ff8fde2014-07-08 07:50:07 -070010868 if (old_fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020010869 intel_unpin_fb_obj(old_obj);
Daniel Vettera071fa02014-06-18 23:28:09 +020010870 i915_gem_track_fb(old_obj, obj,
10871 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Daniel Vetter4c107942014-04-24 23:55:05 +020010872 mutex_unlock(&dev->struct_mutex);
10873
10874 crtc->primary->fb = fb;
10875 crtc->x = x;
10876 crtc->y = y;
Daniel Vettera6778b32012-07-02 09:56:42 +020010877 }
10878
10879 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030010880 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10881 update_scanline_offset(intel_crtc);
10882
Daniel Vetter25c5b262012-07-08 22:08:04 +020010883 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030010884 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010885
Daniel Vettera6778b32012-07-02 09:56:42 +020010886 /* FIXME: add subpixel order */
10887done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010888 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070010889 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010890
Tim Gardner3ac18232012-12-07 07:54:26 -070010891out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010892 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070010893 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020010894 return ret;
10895}
10896
Damien Lespiaue7457a92013-08-08 22:28:59 +010010897static int intel_set_mode(struct drm_crtc *crtc,
10898 struct drm_display_mode *mode,
10899 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020010900{
10901 int ret;
10902
10903 ret = __intel_set_mode(crtc, mode, x, y, fb);
10904
10905 if (ret == 0)
10906 intel_modeset_check_state(crtc->dev);
10907
10908 return ret;
10909}
10910
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010911void intel_crtc_restore_mode(struct drm_crtc *crtc)
10912{
Matt Roperf4510a22014-04-01 15:22:40 -070010913 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010914}
10915
Daniel Vetter25c5b262012-07-08 22:08:04 +020010916#undef for_each_intel_crtc_masked
10917
Daniel Vetterd9e55602012-07-04 22:16:09 +020010918static void intel_set_config_free(struct intel_set_config *config)
10919{
10920 if (!config)
10921 return;
10922
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010923 kfree(config->save_connector_encoders);
10924 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020010925 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020010926 kfree(config);
10927}
10928
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010929static int intel_set_config_save_state(struct drm_device *dev,
10930 struct intel_set_config *config)
10931{
Ville Syrjälä76688512014-01-10 11:28:06 +020010932 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010933 struct drm_encoder *encoder;
10934 struct drm_connector *connector;
10935 int count;
10936
Ville Syrjälä76688512014-01-10 11:28:06 +020010937 config->save_crtc_enabled =
10938 kcalloc(dev->mode_config.num_crtc,
10939 sizeof(bool), GFP_KERNEL);
10940 if (!config->save_crtc_enabled)
10941 return -ENOMEM;
10942
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010943 config->save_encoder_crtcs =
10944 kcalloc(dev->mode_config.num_encoder,
10945 sizeof(struct drm_crtc *), GFP_KERNEL);
10946 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010947 return -ENOMEM;
10948
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010949 config->save_connector_encoders =
10950 kcalloc(dev->mode_config.num_connector,
10951 sizeof(struct drm_encoder *), GFP_KERNEL);
10952 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010953 return -ENOMEM;
10954
10955 /* Copy data. Note that driver private data is not affected.
10956 * Should anything bad happen only the expected state is
10957 * restored, not the drivers personal bookkeeping.
10958 */
10959 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010010960 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010961 config->save_crtc_enabled[count++] = crtc->enabled;
10962 }
10963
10964 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010965 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010966 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010967 }
10968
10969 count = 0;
10970 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010971 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010972 }
10973
10974 return 0;
10975}
10976
10977static void intel_set_config_restore_state(struct drm_device *dev,
10978 struct intel_set_config *config)
10979{
Ville Syrjälä76688512014-01-10 11:28:06 +020010980 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020010981 struct intel_encoder *encoder;
10982 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010983 int count;
10984
10985 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010986 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010987 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010988
10989 if (crtc->new_enabled)
10990 crtc->new_config = &crtc->config;
10991 else
10992 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020010993 }
10994
10995 count = 0;
Damien Lespiaub2784e12014-08-05 11:29:37 +010010996 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +020010997 encoder->new_crtc =
10998 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010999 }
11000
11001 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011002 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11003 connector->new_encoder =
11004 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011005 }
11006}
11007
Imre Deake3de42b2013-05-03 19:44:07 +020011008static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010011009is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020011010{
11011 int i;
11012
Chris Wilson2e57f472013-07-17 12:14:40 +010011013 if (set->num_connectors == 0)
11014 return false;
11015
11016 if (WARN_ON(set->connectors == NULL))
11017 return false;
11018
11019 for (i = 0; i < set->num_connectors; i++)
11020 if (set->connectors[i]->encoder &&
11021 set->connectors[i]->encoder->crtc == set->crtc &&
11022 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020011023 return true;
11024
11025 return false;
11026}
11027
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011028static void
11029intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11030 struct intel_set_config *config)
11031{
11032
11033 /* We should be able to check here if the fb has the same properties
11034 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010011035 if (is_crtc_connector_off(set)) {
11036 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070011037 } else if (set->crtc->primary->fb != set->fb) {
Matt Roper3b150f02014-05-29 08:06:53 -070011038 /*
11039 * If we have no fb, we can only flip as long as the crtc is
11040 * active, otherwise we need a full mode set. The crtc may
11041 * be active if we've only disabled the primary plane, or
11042 * in fastboot situations.
11043 */
Matt Roperf4510a22014-04-01 15:22:40 -070011044 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011045 struct intel_crtc *intel_crtc =
11046 to_intel_crtc(set->crtc);
11047
Matt Roper3b150f02014-05-29 08:06:53 -070011048 if (intel_crtc->active) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011049 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11050 config->fb_changed = true;
11051 } else {
11052 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11053 config->mode_changed = true;
11054 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011055 } else if (set->fb == NULL) {
11056 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010011057 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070011058 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011059 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011060 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011061 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011062 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011063 }
11064
Daniel Vetter835c5872012-07-10 18:11:08 +020011065 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011066 config->fb_changed = true;
11067
11068 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11069 DRM_DEBUG_KMS("modes are different, full mode set\n");
11070 drm_mode_debug_printmodeline(&set->crtc->mode);
11071 drm_mode_debug_printmodeline(set->mode);
11072 config->mode_changed = true;
11073 }
Chris Wilsona1d95702013-08-13 18:48:47 +010011074
11075 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11076 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011077}
11078
Daniel Vetter2e431052012-07-04 22:42:15 +020011079static int
Daniel Vetter9a935852012-07-05 22:34:27 +020011080intel_modeset_stage_output_state(struct drm_device *dev,
11081 struct drm_mode_set *set,
11082 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020011083{
Daniel Vetter9a935852012-07-05 22:34:27 +020011084 struct intel_connector *connector;
11085 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020011086 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030011087 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020011088
Damien Lespiau9abdda72013-02-13 13:29:23 +000011089 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020011090 * of connectors. For paranoia, double-check this. */
11091 WARN_ON(!set->fb && (set->num_connectors != 0));
11092 WARN_ON(set->fb && (set->num_connectors == 0));
11093
Daniel Vetter9a935852012-07-05 22:34:27 +020011094 list_for_each_entry(connector, &dev->mode_config.connector_list,
11095 base.head) {
11096 /* Otherwise traverse passed in connector list and get encoders
11097 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020011098 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011099 if (set->connectors[ro] == &connector->base) {
Dave Airlie0e32b392014-05-02 14:02:48 +100011100 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
Daniel Vetter50f56112012-07-02 09:35:43 +020011101 break;
11102 }
11103 }
11104
Daniel Vetter9a935852012-07-05 22:34:27 +020011105 /* If we disable the crtc, disable all its connectors. Also, if
11106 * the connector is on the changing crtc but not on the new
11107 * connector list, disable it. */
11108 if ((!set->fb || ro == set->num_connectors) &&
11109 connector->base.encoder &&
11110 connector->base.encoder->crtc == set->crtc) {
11111 connector->new_encoder = NULL;
11112
11113 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11114 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011115 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020011116 }
11117
11118
11119 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011120 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011121 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011122 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011123 }
11124 /* connector->new_encoder is now updated for all connectors. */
11125
11126 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020011127 list_for_each_entry(connector, &dev->mode_config.connector_list,
11128 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011129 struct drm_crtc *new_crtc;
11130
Daniel Vetter9a935852012-07-05 22:34:27 +020011131 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020011132 continue;
11133
Daniel Vetter9a935852012-07-05 22:34:27 +020011134 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020011135
11136 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011137 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020011138 new_crtc = set->crtc;
11139 }
11140
11141 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010011142 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11143 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011144 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020011145 }
Dave Airlie0e32b392014-05-02 14:02:48 +100011146 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
Daniel Vetter9a935852012-07-05 22:34:27 +020011147
11148 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11149 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011150 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020011151 new_crtc->base.id);
11152 }
11153
11154 /* Check for any encoders that needs to be disabled. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010011155 for_each_intel_encoder(dev, encoder) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011156 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011157 list_for_each_entry(connector,
11158 &dev->mode_config.connector_list,
11159 base.head) {
11160 if (connector->new_encoder == encoder) {
11161 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011162 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020011163 }
11164 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011165
11166 if (num_connectors == 0)
11167 encoder->new_crtc = NULL;
11168 else if (num_connectors > 1)
11169 return -EINVAL;
11170
Daniel Vetter9a935852012-07-05 22:34:27 +020011171 /* Only now check for crtc changes so we don't miss encoders
11172 * that will be disabled. */
11173 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011174 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011175 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011176 }
11177 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011178 /* Now we've also updated encoder->new_crtc for all encoders. */
Dave Airlie0e32b392014-05-02 14:02:48 +100011179 list_for_each_entry(connector, &dev->mode_config.connector_list,
11180 base.head) {
11181 if (connector->new_encoder)
11182 if (connector->new_encoder != connector->encoder)
11183 connector->encoder = connector->new_encoder;
11184 }
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011185 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011186 crtc->new_enabled = false;
11187
Damien Lespiaub2784e12014-08-05 11:29:37 +010011188 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011189 if (encoder->new_crtc == crtc) {
11190 crtc->new_enabled = true;
11191 break;
11192 }
11193 }
11194
11195 if (crtc->new_enabled != crtc->base.enabled) {
11196 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11197 crtc->new_enabled ? "en" : "dis");
11198 config->mode_changed = true;
11199 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011200
11201 if (crtc->new_enabled)
11202 crtc->new_config = &crtc->config;
11203 else
11204 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011205 }
11206
Daniel Vetter2e431052012-07-04 22:42:15 +020011207 return 0;
11208}
11209
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011210static void disable_crtc_nofb(struct intel_crtc *crtc)
11211{
11212 struct drm_device *dev = crtc->base.dev;
11213 struct intel_encoder *encoder;
11214 struct intel_connector *connector;
11215
11216 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11217 pipe_name(crtc->pipe));
11218
11219 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11220 if (connector->new_encoder &&
11221 connector->new_encoder->new_crtc == crtc)
11222 connector->new_encoder = NULL;
11223 }
11224
Damien Lespiaub2784e12014-08-05 11:29:37 +010011225 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011226 if (encoder->new_crtc == crtc)
11227 encoder->new_crtc = NULL;
11228 }
11229
11230 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011231 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011232}
11233
Daniel Vetter2e431052012-07-04 22:42:15 +020011234static int intel_crtc_set_config(struct drm_mode_set *set)
11235{
11236 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020011237 struct drm_mode_set save_set;
11238 struct intel_set_config *config;
11239 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020011240
Daniel Vetter8d3e3752012-07-05 16:09:09 +020011241 BUG_ON(!set);
11242 BUG_ON(!set->crtc);
11243 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020011244
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010011245 /* Enforce sane interface api - has been abused by the fb helper. */
11246 BUG_ON(!set->mode && set->fb);
11247 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020011248
Daniel Vetter2e431052012-07-04 22:42:15 +020011249 if (set->fb) {
11250 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11251 set->crtc->base.id, set->fb->base.id,
11252 (int)set->num_connectors, set->x, set->y);
11253 } else {
11254 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020011255 }
11256
11257 dev = set->crtc->dev;
11258
11259 ret = -ENOMEM;
11260 config = kzalloc(sizeof(*config), GFP_KERNEL);
11261 if (!config)
11262 goto out_config;
11263
11264 ret = intel_set_config_save_state(dev, config);
11265 if (ret)
11266 goto out_config;
11267
11268 save_set.crtc = set->crtc;
11269 save_set.mode = &set->crtc->mode;
11270 save_set.x = set->crtc->x;
11271 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070011272 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020011273
11274 /* Compute whether we need a full modeset, only an fb base update or no
11275 * change at all. In the future we might also check whether only the
11276 * mode changed, e.g. for LVDS where we only change the panel fitter in
11277 * such cases. */
11278 intel_set_config_compute_mode_changes(set, config);
11279
Daniel Vetter9a935852012-07-05 22:34:27 +020011280 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020011281 if (ret)
11282 goto fail;
11283
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011284 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011285 ret = intel_set_mode(set->crtc, set->mode,
11286 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011287 } else if (config->fb_changed) {
Matt Roper3b150f02014-05-29 08:06:53 -070011288 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11289
Ville Syrjälä4878cae2013-02-18 19:08:48 +020011290 intel_crtc_wait_for_pending_flips(set->crtc);
11291
Daniel Vetter4f660f42012-07-02 09:47:37 +020011292 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020011293 set->x, set->y, set->fb);
Matt Roper3b150f02014-05-29 08:06:53 -070011294
11295 /*
11296 * We need to make sure the primary plane is re-enabled if it
11297 * has previously been turned off.
11298 */
11299 if (!intel_crtc->primary_enabled && ret == 0) {
11300 WARN_ON(!intel_crtc->active);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011301 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
Matt Roper3b150f02014-05-29 08:06:53 -070011302 }
11303
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011304 /*
11305 * In the fastboot case this may be our only check of the
11306 * state after boot. It would be better to only do it on
11307 * the first update, but we don't have a nice way of doing that
11308 * (and really, set_config isn't used much for high freq page
11309 * flipping, so increasing its cost here shouldn't be a big
11310 * deal).
11311 */
Jani Nikulad330a952014-01-21 11:24:25 +020011312 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011313 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020011314 }
11315
Chris Wilson2d05eae2013-05-03 17:36:25 +010011316 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020011317 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11318 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020011319fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010011320 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011321
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011322 /*
11323 * HACK: if the pipe was on, but we didn't have a framebuffer,
11324 * force the pipe off to avoid oopsing in the modeset code
11325 * due to fb==NULL. This should only happen during boot since
11326 * we don't yet reconstruct the FB from the hardware state.
11327 */
11328 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11329 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11330
Chris Wilson2d05eae2013-05-03 17:36:25 +010011331 /* Try to restore the config */
11332 if (config->mode_changed &&
11333 intel_set_mode(save_set.crtc, save_set.mode,
11334 save_set.x, save_set.y, save_set.fb))
11335 DRM_ERROR("failed to restore config after modeset failure\n");
11336 }
Daniel Vetter50f56112012-07-02 09:35:43 +020011337
Daniel Vetterd9e55602012-07-04 22:16:09 +020011338out_config:
11339 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011340 return ret;
11341}
11342
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011343static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011344 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020011345 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011346 .destroy = intel_crtc_destroy,
11347 .page_flip = intel_crtc_page_flip,
11348};
11349
Daniel Vetter53589012013-06-05 13:34:16 +020011350static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11351 struct intel_shared_dpll *pll,
11352 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011353{
Daniel Vetter53589012013-06-05 13:34:16 +020011354 uint32_t val;
11355
Daniel Vetterf458ebb2014-09-30 10:56:39 +020011356 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030011357 return false;
11358
Daniel Vetter53589012013-06-05 13:34:16 +020011359 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020011360 hw_state->dpll = val;
11361 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11362 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020011363
11364 return val & DPLL_VCO_ENABLE;
11365}
11366
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011367static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11368 struct intel_shared_dpll *pll)
11369{
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011370 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11371 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011372}
11373
Daniel Vettere7b903d2013-06-05 13:34:14 +020011374static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11375 struct intel_shared_dpll *pll)
11376{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011377 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020011378 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020011379
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011380 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011381
11382 /* Wait for the clocks to stabilize. */
11383 POSTING_READ(PCH_DPLL(pll->id));
11384 udelay(150);
11385
11386 /* The pixel multiplier can only be updated once the
11387 * DPLL is enabled and the clocks are stable.
11388 *
11389 * So write it again.
11390 */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011391 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011392 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011393 udelay(200);
11394}
11395
11396static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11397 struct intel_shared_dpll *pll)
11398{
11399 struct drm_device *dev = dev_priv->dev;
11400 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011401
11402 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011403 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020011404 if (intel_crtc_to_shared_dpll(crtc) == pll)
11405 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11406 }
11407
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011408 I915_WRITE(PCH_DPLL(pll->id), 0);
11409 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011410 udelay(200);
11411}
11412
Daniel Vetter46edb022013-06-05 13:34:12 +020011413static char *ibx_pch_dpll_names[] = {
11414 "PCH DPLL A",
11415 "PCH DPLL B",
11416};
11417
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011418static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011419{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011420 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011421 int i;
11422
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011423 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011424
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011425 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020011426 dev_priv->shared_dplls[i].id = i;
11427 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011428 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011429 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11430 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020011431 dev_priv->shared_dplls[i].get_hw_state =
11432 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011433 }
11434}
11435
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011436static void intel_shared_dpll_init(struct drm_device *dev)
11437{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011438 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011439
Daniel Vetter9cd86932014-06-25 22:01:57 +030011440 if (HAS_DDI(dev))
11441 intel_ddi_pll_init(dev);
11442 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011443 ibx_pch_dpll_init(dev);
11444 else
11445 dev_priv->num_shared_dpll = 0;
11446
11447 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011448}
11449
Matt Roper465c1202014-05-29 08:06:54 -070011450static int
11451intel_primary_plane_disable(struct drm_plane *plane)
11452{
11453 struct drm_device *dev = plane->dev;
Matt Roper465c1202014-05-29 08:06:54 -070011454 struct intel_crtc *intel_crtc;
11455
11456 if (!plane->fb)
11457 return 0;
11458
11459 BUG_ON(!plane->crtc);
11460
11461 intel_crtc = to_intel_crtc(plane->crtc);
11462
11463 /*
11464 * Even though we checked plane->fb above, it's still possible that
11465 * the primary plane has been implicitly disabled because the crtc
11466 * coordinates given weren't visible, or because we detected
11467 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11468 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11469 * In either case, we need to unpin the FB and let the fb pointer get
11470 * updated, but otherwise we don't need to touch the hardware.
11471 */
11472 if (!intel_crtc->primary_enabled)
11473 goto disable_unpin;
11474
11475 intel_crtc_wait_for_pending_flips(plane->crtc);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011476 intel_disable_primary_hw_plane(plane, plane->crtc);
11477
Matt Roper465c1202014-05-29 08:06:54 -070011478disable_unpin:
Matt Roper4c345742014-07-09 16:22:10 -070011479 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011480 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
Daniel Vettera071fa02014-06-18 23:28:09 +020011481 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper2ff8fde2014-07-08 07:50:07 -070011482 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
Matt Roper4c345742014-07-09 16:22:10 -070011483 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011484 plane->fb = NULL;
11485
11486 return 0;
11487}
11488
11489static int
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011490intel_check_primary_plane(struct drm_plane *plane,
11491 struct intel_plane_state *state)
Matt Roper465c1202014-05-29 08:06:54 -070011492{
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011493 struct drm_crtc *crtc = state->crtc;
11494 struct drm_framebuffer *fb = state->fb;
11495 struct drm_rect *dest = &state->dst;
11496 struct drm_rect *src = &state->src;
11497 const struct drm_rect *clip = &state->clip;
11498
Gustavo Padovan3ead8bb2014-10-24 19:00:18 +010011499 return drm_plane_helper_check_update(plane, crtc, fb,
11500 src, dest, clip,
11501 DRM_PLANE_HELPER_NO_SCALING,
11502 DRM_PLANE_HELPER_NO_SCALING,
11503 false, true, &state->visible);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011504}
11505
11506static int
Gustavo Padovan14af2932014-10-24 14:51:31 +010011507intel_prepare_primary_plane(struct drm_plane *plane,
11508 struct intel_plane_state *state)
11509{
11510 struct drm_crtc *crtc = state->crtc;
11511 struct drm_framebuffer *fb = state->fb;
11512 struct drm_device *dev = crtc->dev;
11513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11514 enum pipe pipe = intel_crtc->pipe;
11515 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11516 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11517 int ret;
11518
11519 intel_crtc_wait_for_pending_flips(crtc);
11520
11521 if (intel_crtc_has_pending_flip(crtc)) {
11522 DRM_ERROR("pipe is still busy with an old pageflip\n");
11523 return -EBUSY;
11524 }
11525
11526 if (old_obj != obj) {
11527 mutex_lock(&dev->struct_mutex);
11528 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11529 if (ret == 0)
11530 i915_gem_track_fb(old_obj, obj,
11531 INTEL_FRONTBUFFER_PRIMARY(pipe));
11532 mutex_unlock(&dev->struct_mutex);
11533 if (ret != 0) {
11534 DRM_DEBUG_KMS("pin & fence failed\n");
11535 return ret;
11536 }
11537 }
11538
11539 return 0;
11540}
11541
11542static void
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011543intel_commit_primary_plane(struct drm_plane *plane,
11544 struct intel_plane_state *state)
11545{
11546 struct drm_crtc *crtc = state->crtc;
11547 struct drm_framebuffer *fb = state->fb;
Matt Roper465c1202014-05-29 08:06:54 -070011548 struct drm_device *dev = crtc->dev;
Sonika Jindal48404c12014-08-22 14:06:04 +053011549 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper465c1202014-05-29 08:06:54 -070011550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011551 enum pipe pipe = intel_crtc->pipe;
11552 struct drm_framebuffer *old_fb = plane->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -070011553 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11554 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
Sonika Jindalce54d852014-08-21 11:44:39 +053011555 struct intel_plane *intel_plane = to_intel_plane(plane);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011556 struct drm_rect *src = &state->src;
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011557
11558 crtc->primary->fb = fb;
11559 crtc->x = src->x1;
11560 crtc->y = src->y1;
11561
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011562 intel_plane->crtc_x = state->orig_dst.x1;
11563 intel_plane->crtc_y = state->orig_dst.y1;
11564 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11565 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11566 intel_plane->src_x = state->orig_src.x1;
11567 intel_plane->src_y = state->orig_src.y1;
11568 intel_plane->src_w = drm_rect_width(&state->orig_src);
11569 intel_plane->src_h = drm_rect_height(&state->orig_src);
Sonika Jindalce54d852014-08-21 11:44:39 +053011570 intel_plane->obj = obj;
Matt Roper465c1202014-05-29 08:06:54 -070011571
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011572 if (intel_crtc->active) {
11573 /*
11574 * FBC does not work on some platforms for rotated
11575 * planes, so disable it when rotation is not 0 and
11576 * update it when rotation is set back to 0.
11577 *
11578 * FIXME: This is redundant with the fbc update done in
11579 * the primary plane enable function except that that
11580 * one is done too late. We eventually need to unify
11581 * this.
11582 */
11583 if (intel_crtc->primary_enabled &&
11584 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11585 dev_priv->fbc.plane == intel_crtc->plane &&
11586 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11587 intel_disable_fbc(dev);
11588 }
11589
11590 if (state->visible) {
11591 bool was_enabled = intel_crtc->primary_enabled;
11592
11593 /* FIXME: kill this fastboot hack */
11594 intel_update_pipe_size(intel_crtc);
11595
11596 intel_crtc->primary_enabled = true;
11597
11598 dev_priv->display.update_primary_plane(crtc, plane->fb,
11599 crtc->x, crtc->y);
11600
11601 /*
11602 * BDW signals flip done immediately if the plane
11603 * is disabled, even if the plane enable is already
11604 * armed to occur at the next vblank :(
11605 */
11606 if (IS_BROADWELL(dev) && !was_enabled)
11607 intel_wait_for_vblank(dev, intel_crtc->pipe);
11608 } else {
11609 /*
11610 * If clipping results in a non-visible primary plane,
11611 * we'll disable the primary plane. Note that this is
11612 * a bit different than what happens if userspace
11613 * explicitly disables the plane by passing fb=0
11614 * because plane->fb still gets set and pinned.
11615 */
11616 intel_disable_primary_hw_plane(plane, crtc);
11617 }
11618
11619 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11620
11621 mutex_lock(&dev->struct_mutex);
11622 intel_update_fbc(dev);
11623 mutex_unlock(&dev->struct_mutex);
11624 }
11625
11626 if (old_fb && old_fb != fb) {
11627 if (intel_crtc->active)
11628 intel_wait_for_vblank(dev, intel_crtc->pipe);
11629
11630 mutex_lock(&dev->struct_mutex);
11631 intel_unpin_fb_obj(old_obj);
11632 mutex_unlock(&dev->struct_mutex);
11633 }
Matt Roper465c1202014-05-29 08:06:54 -070011634}
11635
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011636static int
11637intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11638 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11639 unsigned int crtc_w, unsigned int crtc_h,
11640 uint32_t src_x, uint32_t src_y,
11641 uint32_t src_w, uint32_t src_h)
11642{
11643 struct intel_plane_state state;
11644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11645 int ret;
11646
11647 state.crtc = crtc;
11648 state.fb = fb;
11649
11650 /* sample coordinates in 16.16 fixed point */
11651 state.src.x1 = src_x;
11652 state.src.x2 = src_x + src_w;
11653 state.src.y1 = src_y;
11654 state.src.y2 = src_y + src_h;
11655
11656 /* integer pixels */
11657 state.dst.x1 = crtc_x;
11658 state.dst.x2 = crtc_x + crtc_w;
11659 state.dst.y1 = crtc_y;
11660 state.dst.y2 = crtc_y + crtc_h;
11661
11662 state.clip.x1 = 0;
11663 state.clip.y1 = 0;
11664 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11665 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11666
11667 state.orig_src = state.src;
11668 state.orig_dst = state.dst;
11669
11670 ret = intel_check_primary_plane(plane, &state);
11671 if (ret)
11672 return ret;
11673
Gustavo Padovan14af2932014-10-24 14:51:31 +010011674 ret = intel_prepare_primary_plane(plane, &state);
11675 if (ret)
11676 return ret;
11677
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011678 intel_commit_primary_plane(plane, &state);
11679
11680 return 0;
11681}
11682
Matt Roper3d7d6512014-06-10 08:28:13 -070011683/* Common destruction function for both primary and cursor planes */
11684static void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070011685{
11686 struct intel_plane *intel_plane = to_intel_plane(plane);
11687 drm_plane_cleanup(plane);
11688 kfree(intel_plane);
11689}
11690
11691static const struct drm_plane_funcs intel_primary_plane_funcs = {
11692 .update_plane = intel_primary_plane_setplane,
11693 .disable_plane = intel_primary_plane_disable,
Matt Roper3d7d6512014-06-10 08:28:13 -070011694 .destroy = intel_plane_destroy,
Sonika Jindal48404c12014-08-22 14:06:04 +053011695 .set_property = intel_plane_set_property
Matt Roper465c1202014-05-29 08:06:54 -070011696};
11697
11698static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11699 int pipe)
11700{
11701 struct intel_plane *primary;
11702 const uint32_t *intel_primary_formats;
11703 int num_formats;
11704
11705 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11706 if (primary == NULL)
11707 return NULL;
11708
11709 primary->can_scale = false;
11710 primary->max_downscale = 1;
11711 primary->pipe = pipe;
11712 primary->plane = pipe;
Sonika Jindal48404c12014-08-22 14:06:04 +053011713 primary->rotation = BIT(DRM_ROTATE_0);
Matt Roper465c1202014-05-29 08:06:54 -070011714 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11715 primary->plane = !pipe;
11716
11717 if (INTEL_INFO(dev)->gen <= 3) {
11718 intel_primary_formats = intel_primary_formats_gen2;
11719 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11720 } else {
11721 intel_primary_formats = intel_primary_formats_gen4;
11722 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11723 }
11724
11725 drm_universal_plane_init(dev, &primary->base, 0,
11726 &intel_primary_plane_funcs,
11727 intel_primary_formats, num_formats,
11728 DRM_PLANE_TYPE_PRIMARY);
Sonika Jindal48404c12014-08-22 14:06:04 +053011729
11730 if (INTEL_INFO(dev)->gen >= 4) {
11731 if (!dev->mode_config.rotation_property)
11732 dev->mode_config.rotation_property =
11733 drm_mode_create_rotation_property(dev,
11734 BIT(DRM_ROTATE_0) |
11735 BIT(DRM_ROTATE_180));
11736 if (dev->mode_config.rotation_property)
11737 drm_object_attach_property(&primary->base.base,
11738 dev->mode_config.rotation_property,
11739 primary->rotation);
11740 }
11741
Matt Roper465c1202014-05-29 08:06:54 -070011742 return &primary->base;
11743}
11744
Matt Roper3d7d6512014-06-10 08:28:13 -070011745static int
11746intel_cursor_plane_disable(struct drm_plane *plane)
11747{
11748 if (!plane->fb)
11749 return 0;
11750
11751 BUG_ON(!plane->crtc);
11752
11753 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11754}
11755
11756static int
Gustavo Padovan852e7872014-09-05 17:22:31 -030011757intel_check_cursor_plane(struct drm_plane *plane,
11758 struct intel_plane_state *state)
Matt Roper3d7d6512014-06-10 08:28:13 -070011759{
Gustavo Padovan852e7872014-09-05 17:22:31 -030011760 struct drm_crtc *crtc = state->crtc;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011761 struct drm_device *dev = crtc->dev;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011762 struct drm_framebuffer *fb = state->fb;
11763 struct drm_rect *dest = &state->dst;
11764 struct drm_rect *src = &state->src;
11765 const struct drm_rect *clip = &state->clip;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011766 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11767 int crtc_w, crtc_h;
11768 unsigned stride;
11769 int ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011770
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011771 ret = drm_plane_helper_check_update(plane, crtc, fb,
Gustavo Padovan852e7872014-09-05 17:22:31 -030011772 src, dest, clip,
11773 DRM_PLANE_HELPER_NO_SCALING,
11774 DRM_PLANE_HELPER_NO_SCALING,
11775 true, true, &state->visible);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011776 if (ret)
11777 return ret;
11778
11779
11780 /* if we want to turn off the cursor ignore width and height */
11781 if (!obj)
11782 return 0;
11783
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011784 /* Check for which cursor types we support */
11785 crtc_w = drm_rect_width(&state->orig_dst);
11786 crtc_h = drm_rect_height(&state->orig_dst);
11787 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11788 DRM_DEBUG("Cursor dimension not supported\n");
11789 return -EINVAL;
11790 }
11791
11792 stride = roundup_pow_of_two(crtc_w) * 4;
11793 if (obj->base.size < stride * crtc_h) {
11794 DRM_DEBUG_KMS("buffer is too small\n");
11795 return -ENOMEM;
11796 }
11797
Gustavo Padovane391ea82014-09-24 14:20:25 -030011798 if (fb == crtc->cursor->fb)
11799 return 0;
11800
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011801 /* we only need to pin inside GTT if cursor is non-phy */
11802 mutex_lock(&dev->struct_mutex);
11803 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11804 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11805 ret = -EINVAL;
11806 }
11807 mutex_unlock(&dev->struct_mutex);
11808
11809 return ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011810}
11811
11812static int
11813intel_commit_cursor_plane(struct drm_plane *plane,
11814 struct intel_plane_state *state)
11815{
11816 struct drm_crtc *crtc = state->crtc;
11817 struct drm_framebuffer *fb = state->fb;
Matt Roper3d7d6512014-06-10 08:28:13 -070011818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Sonika Jindala919db92014-10-23 07:41:33 -070011819 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper3d7d6512014-06-10 08:28:13 -070011820 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11821 struct drm_i915_gem_object *obj = intel_fb->obj;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011822 int crtc_w, crtc_h;
Matt Roper3d7d6512014-06-10 08:28:13 -070011823
Gustavo Padovan852e7872014-09-05 17:22:31 -030011824 crtc->cursor_x = state->orig_dst.x1;
11825 crtc->cursor_y = state->orig_dst.y1;
Sonika Jindala919db92014-10-23 07:41:33 -070011826
11827 intel_plane->crtc_x = state->orig_dst.x1;
11828 intel_plane->crtc_y = state->orig_dst.y1;
11829 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11830 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11831 intel_plane->src_x = state->orig_src.x1;
11832 intel_plane->src_y = state->orig_src.y1;
11833 intel_plane->src_w = drm_rect_width(&state->orig_src);
11834 intel_plane->src_h = drm_rect_height(&state->orig_src);
11835 intel_plane->obj = obj;
11836
Matt Roper3d7d6512014-06-10 08:28:13 -070011837 if (fb != crtc->cursor->fb) {
Gustavo Padovan852e7872014-09-05 17:22:31 -030011838 crtc_w = drm_rect_width(&state->orig_dst);
11839 crtc_h = drm_rect_height(&state->orig_dst);
Matt Roper3d7d6512014-06-10 08:28:13 -070011840 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11841 } else {
Gustavo Padovan852e7872014-09-05 17:22:31 -030011842 intel_crtc_update_cursor(crtc, state->visible);
Daniel Vetter4ed91092014-08-08 20:27:01 +020011843
11844 intel_frontbuffer_flip(crtc->dev,
11845 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11846
Matt Roper3d7d6512014-06-10 08:28:13 -070011847 return 0;
11848 }
11849}
Gustavo Padovan852e7872014-09-05 17:22:31 -030011850
11851static int
11852intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11853 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11854 unsigned int crtc_w, unsigned int crtc_h,
11855 uint32_t src_x, uint32_t src_y,
11856 uint32_t src_w, uint32_t src_h)
11857{
11858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11859 struct intel_plane_state state;
11860 int ret;
11861
11862 state.crtc = crtc;
11863 state.fb = fb;
11864
11865 /* sample coordinates in 16.16 fixed point */
11866 state.src.x1 = src_x;
11867 state.src.x2 = src_x + src_w;
11868 state.src.y1 = src_y;
11869 state.src.y2 = src_y + src_h;
11870
11871 /* integer pixels */
11872 state.dst.x1 = crtc_x;
11873 state.dst.x2 = crtc_x + crtc_w;
11874 state.dst.y1 = crtc_y;
11875 state.dst.y2 = crtc_y + crtc_h;
11876
11877 state.clip.x1 = 0;
11878 state.clip.y1 = 0;
11879 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11880 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11881
11882 state.orig_src = state.src;
11883 state.orig_dst = state.dst;
11884
11885 ret = intel_check_cursor_plane(plane, &state);
11886 if (ret)
11887 return ret;
11888
11889 return intel_commit_cursor_plane(plane, &state);
11890}
11891
Matt Roper3d7d6512014-06-10 08:28:13 -070011892static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11893 .update_plane = intel_cursor_plane_update,
11894 .disable_plane = intel_cursor_plane_disable,
11895 .destroy = intel_plane_destroy,
Ville Syrjälä4398ad42014-10-23 07:41:34 -070011896 .set_property = intel_plane_set_property,
Matt Roper3d7d6512014-06-10 08:28:13 -070011897};
11898
11899static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11900 int pipe)
11901{
11902 struct intel_plane *cursor;
11903
11904 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11905 if (cursor == NULL)
11906 return NULL;
11907
11908 cursor->can_scale = false;
11909 cursor->max_downscale = 1;
11910 cursor->pipe = pipe;
11911 cursor->plane = pipe;
Ville Syrjälä4398ad42014-10-23 07:41:34 -070011912 cursor->rotation = BIT(DRM_ROTATE_0);
Matt Roper3d7d6512014-06-10 08:28:13 -070011913
11914 drm_universal_plane_init(dev, &cursor->base, 0,
11915 &intel_cursor_plane_funcs,
11916 intel_cursor_formats,
11917 ARRAY_SIZE(intel_cursor_formats),
11918 DRM_PLANE_TYPE_CURSOR);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070011919
11920 if (INTEL_INFO(dev)->gen >= 4) {
11921 if (!dev->mode_config.rotation_property)
11922 dev->mode_config.rotation_property =
11923 drm_mode_create_rotation_property(dev,
11924 BIT(DRM_ROTATE_0) |
11925 BIT(DRM_ROTATE_180));
11926 if (dev->mode_config.rotation_property)
11927 drm_object_attach_property(&cursor->base.base,
11928 dev->mode_config.rotation_property,
11929 cursor->rotation);
11930 }
11931
Matt Roper3d7d6512014-06-10 08:28:13 -070011932 return &cursor->base;
11933}
11934
Hannes Ederb358d0a2008-12-18 21:18:47 +010011935static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080011936{
Jani Nikulafbee40d2014-03-31 14:27:18 +030011937 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080011938 struct intel_crtc *intel_crtc;
Matt Roper3d7d6512014-06-10 08:28:13 -070011939 struct drm_plane *primary = NULL;
11940 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070011941 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080011942
Daniel Vetter955382f2013-09-19 14:05:45 +020011943 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080011944 if (intel_crtc == NULL)
11945 return;
11946
Matt Roper465c1202014-05-29 08:06:54 -070011947 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011948 if (!primary)
11949 goto fail;
11950
11951 cursor = intel_cursor_plane_create(dev, pipe);
11952 if (!cursor)
11953 goto fail;
11954
Matt Roper465c1202014-05-29 08:06:54 -070011955 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070011956 cursor, &intel_crtc_funcs);
11957 if (ret)
11958 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080011959
11960 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080011961 for (i = 0; i < 256; i++) {
11962 intel_crtc->lut_r[i] = i;
11963 intel_crtc->lut_g[i] = i;
11964 intel_crtc->lut_b[i] = i;
11965 }
11966
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011967 /*
11968 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020011969 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020011970 */
Jesse Barnes80824002009-09-10 15:28:06 -070011971 intel_crtc->pipe = pipe;
11972 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010011973 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080011974 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010011975 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070011976 }
11977
Chris Wilson4b0e3332014-05-30 16:35:26 +030011978 intel_crtc->cursor_base = ~0;
11979 intel_crtc->cursor_cntl = ~0;
Ville Syrjälädc41c152014-08-13 11:57:05 +030011980 intel_crtc->cursor_size = ~0;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030011981
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080011982 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11983 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11984 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11985 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11986
Jesse Barnes79e53942008-11-07 14:24:08 -080011987 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020011988
11989 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070011990 return;
11991
11992fail:
11993 if (primary)
11994 drm_plane_cleanup(primary);
11995 if (cursor)
11996 drm_plane_cleanup(cursor);
11997 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080011998}
11999
Jesse Barnes752aa882013-10-31 18:55:49 +020012000enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12001{
12002 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012003 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020012004
Rob Clark51fd3712013-11-19 12:10:12 -050012005 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020012006
12007 if (!encoder)
12008 return INVALID_PIPE;
12009
12010 return to_intel_crtc(encoder->crtc)->pipe;
12011}
12012
Carl Worth08d7b3d2009-04-29 14:43:54 -070012013int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000012014 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070012015{
Carl Worth08d7b3d2009-04-29 14:43:54 -070012016 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040012017 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020012018 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012019
Daniel Vetter1cff8f62012-04-24 09:55:08 +020012020 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12021 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012022
Rob Clark7707e652014-07-17 23:30:04 -040012023 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Carl Worth08d7b3d2009-04-29 14:43:54 -070012024
Rob Clark7707e652014-07-17 23:30:04 -040012025 if (!drmmode_crtc) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070012026 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030012027 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012028 }
12029
Rob Clark7707e652014-07-17 23:30:04 -040012030 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020012031 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012032
Daniel Vetterc05422d2009-08-11 16:05:30 +020012033 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012034}
12035
Daniel Vetter66a92782012-07-12 20:08:18 +020012036static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080012037{
Daniel Vetter66a92782012-07-12 20:08:18 +020012038 struct drm_device *dev = encoder->base.dev;
12039 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080012040 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080012041 int entry = 0;
12042
Damien Lespiaub2784e12014-08-05 11:29:37 +010012043 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020012044 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020012045 index_mask |= (1 << entry);
12046
Jesse Barnes79e53942008-11-07 14:24:08 -080012047 entry++;
12048 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010012049
Jesse Barnes79e53942008-11-07 14:24:08 -080012050 return index_mask;
12051}
12052
Chris Wilson4d302442010-12-14 19:21:29 +000012053static bool has_edp_a(struct drm_device *dev)
12054{
12055 struct drm_i915_private *dev_priv = dev->dev_private;
12056
12057 if (!IS_MOBILE(dev))
12058 return false;
12059
12060 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12061 return false;
12062
Damien Lespiaue3589902014-02-07 19:12:50 +000012063 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000012064 return false;
12065
12066 return true;
12067}
12068
Damien Lespiauba0fbca2014-01-08 14:18:23 +000012069const char *intel_output_name(int output)
12070{
12071 static const char *names[] = {
12072 [INTEL_OUTPUT_UNUSED] = "Unused",
12073 [INTEL_OUTPUT_ANALOG] = "Analog",
12074 [INTEL_OUTPUT_DVO] = "DVO",
12075 [INTEL_OUTPUT_SDVO] = "SDVO",
12076 [INTEL_OUTPUT_LVDS] = "LVDS",
12077 [INTEL_OUTPUT_TVOUT] = "TV",
12078 [INTEL_OUTPUT_HDMI] = "HDMI",
12079 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12080 [INTEL_OUTPUT_EDP] = "eDP",
12081 [INTEL_OUTPUT_DSI] = "DSI",
12082 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12083 };
12084
12085 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12086 return "Invalid";
12087
12088 return names[output];
12089}
12090
Jesse Barnes84b4e042014-06-25 08:24:29 -070012091static bool intel_crt_present(struct drm_device *dev)
12092{
12093 struct drm_i915_private *dev_priv = dev->dev_private;
12094
Damien Lespiau884497e2013-12-03 13:56:23 +000012095 if (INTEL_INFO(dev)->gen >= 9)
12096 return false;
12097
Damien Lespiaucf404ce2014-10-01 20:04:15 +010012098 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
Jesse Barnes84b4e042014-06-25 08:24:29 -070012099 return false;
12100
12101 if (IS_CHERRYVIEW(dev))
12102 return false;
12103
12104 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12105 return false;
12106
12107 return true;
12108}
12109
Jesse Barnes79e53942008-11-07 14:24:08 -080012110static void intel_setup_outputs(struct drm_device *dev)
12111{
Eric Anholt725e30a2009-01-22 13:01:02 -080012112 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010012113 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012114 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080012115
Daniel Vetterc9093352013-06-06 22:22:47 +020012116 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012117
Jesse Barnes84b4e042014-06-25 08:24:29 -070012118 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020012119 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012120
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012121 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030012122 int found;
12123
12124 /* Haswell uses DDI functions to detect digital outputs */
12125 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12126 /* DDI A only supports eDP */
12127 if (found)
12128 intel_ddi_init(dev, PORT_A);
12129
12130 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12131 * register */
12132 found = I915_READ(SFUSE_STRAP);
12133
12134 if (found & SFUSE_STRAP_DDIB_DETECTED)
12135 intel_ddi_init(dev, PORT_B);
12136 if (found & SFUSE_STRAP_DDIC_DETECTED)
12137 intel_ddi_init(dev, PORT_C);
12138 if (found & SFUSE_STRAP_DDID_DETECTED)
12139 intel_ddi_init(dev, PORT_D);
12140 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012141 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012142 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020012143
12144 if (has_edp_a(dev))
12145 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012146
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012147 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080012148 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010012149 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012150 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012151 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012152 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012153 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012154 }
12155
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012156 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012157 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012158
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012159 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012160 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012161
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012162 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012163 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012164
Daniel Vetter270b3042012-10-27 15:52:05 +020012165 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012166 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070012167 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012168 /*
12169 * The DP_DETECTED bit is the latched state of the DDC
12170 * SDA pin at boot. However since eDP doesn't require DDC
12171 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12172 * eDP ports may have been muxed to an alternate function.
12173 * Thus we can't rely on the DP_DETECTED bit alone to detect
12174 * eDP ports. Consult the VBT as well as DP_DETECTED to
12175 * detect eDP ports.
12176 */
12177 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012178 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12179 PORT_B);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012180 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12181 intel_dp_is_edp(dev, PORT_B))
12182 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012183
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012184 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012185 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12186 PORT_C);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012187 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12188 intel_dp_is_edp(dev, PORT_C))
12189 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +053012190
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012191 if (IS_CHERRYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012192 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012193 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12194 PORT_D);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012195 /* eDP not supported on port D, so don't check VBT */
12196 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12197 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012198 }
12199
Jani Nikula3cfca972013-08-27 15:12:26 +030012200 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080012201 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012202 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080012203
Paulo Zanonie2debe92013-02-18 19:00:27 -030012204 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012205 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012206 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012207 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12208 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012209 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012210 }
Ma Ling27185ae2009-08-24 13:50:23 +080012211
Imre Deake7281ea2013-05-08 13:14:08 +030012212 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012213 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080012214 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012215
12216 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012217
Paulo Zanonie2debe92013-02-18 19:00:27 -030012218 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012219 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012220 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012221 }
Ma Ling27185ae2009-08-24 13:50:23 +080012222
Paulo Zanonie2debe92013-02-18 19:00:27 -030012223 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012224
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012225 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12226 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012227 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012228 }
Imre Deake7281ea2013-05-08 13:14:08 +030012229 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012230 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080012231 }
Ma Ling27185ae2009-08-24 13:50:23 +080012232
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012233 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030012234 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012235 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070012236 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012237 intel_dvo_init(dev);
12238
Zhenyu Wang103a1962009-11-27 11:44:36 +080012239 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012240 intel_tv_init(dev);
12241
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070012242 intel_edp_psr_init(dev);
12243
Damien Lespiaub2784e12014-08-05 11:29:37 +010012244 for_each_intel_encoder(dev, encoder) {
Chris Wilson4ef69c72010-09-09 15:14:28 +010012245 encoder->base.possible_crtcs = encoder->crtc_mask;
12246 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020012247 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080012248 }
Chris Wilson47356eb2011-01-11 17:06:04 +000012249
Paulo Zanonidde86e22012-12-01 12:04:25 -020012250 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020012251
12252 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012253}
12254
12255static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12256{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012257 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080012258 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080012259
Daniel Vetteref2d6332014-02-10 18:00:38 +010012260 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012261 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010012262 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012263 drm_gem_object_unreference(&intel_fb->obj->base);
12264 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012265 kfree(intel_fb);
12266}
12267
12268static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000012269 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080012270 unsigned int *handle)
12271{
12272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000012273 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012274
Chris Wilson05394f32010-11-08 19:18:58 +000012275 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080012276}
12277
12278static const struct drm_framebuffer_funcs intel_fb_funcs = {
12279 .destroy = intel_user_framebuffer_destroy,
12280 .create_handle = intel_user_framebuffer_create_handle,
12281};
12282
Daniel Vetterb5ea6422014-03-02 21:18:00 +010012283static int intel_framebuffer_init(struct drm_device *dev,
12284 struct intel_framebuffer *intel_fb,
12285 struct drm_mode_fb_cmd2 *mode_cmd,
12286 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080012287{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012288 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012289 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080012290 int ret;
12291
Daniel Vetterdd4916c2013-10-09 21:23:51 +020012292 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12293
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012294 if (obj->tiling_mode == I915_TILING_Y) {
12295 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010012296 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012297 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012298
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012299 if (mode_cmd->pitches[0] & 63) {
12300 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12301 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010012302 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012303 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012304
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012305 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12306 pitch_limit = 32*1024;
12307 } else if (INTEL_INFO(dev)->gen >= 4) {
12308 if (obj->tiling_mode)
12309 pitch_limit = 16*1024;
12310 else
12311 pitch_limit = 32*1024;
12312 } else if (INTEL_INFO(dev)->gen >= 3) {
12313 if (obj->tiling_mode)
12314 pitch_limit = 8*1024;
12315 else
12316 pitch_limit = 16*1024;
12317 } else
12318 /* XXX DSPC is limited to 4k tiled */
12319 pitch_limit = 8*1024;
12320
12321 if (mode_cmd->pitches[0] > pitch_limit) {
12322 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12323 obj->tiling_mode ? "tiled" : "linear",
12324 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012325 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012326 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012327
12328 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012329 mode_cmd->pitches[0] != obj->stride) {
12330 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12331 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012332 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012333 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012334
Ville Syrjälä57779d02012-10-31 17:50:14 +020012335 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012336 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020012337 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012338 case DRM_FORMAT_RGB565:
12339 case DRM_FORMAT_XRGB8888:
12340 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012341 break;
12342 case DRM_FORMAT_XRGB1555:
12343 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012344 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012345 DRM_DEBUG("unsupported pixel format: %s\n",
12346 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012347 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012348 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020012349 break;
12350 case DRM_FORMAT_XBGR8888:
12351 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012352 case DRM_FORMAT_XRGB2101010:
12353 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012354 case DRM_FORMAT_XBGR2101010:
12355 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012356 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012357 DRM_DEBUG("unsupported pixel format: %s\n",
12358 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012359 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012360 }
Jesse Barnesb5626742011-06-24 12:19:27 -070012361 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020012362 case DRM_FORMAT_YUYV:
12363 case DRM_FORMAT_UYVY:
12364 case DRM_FORMAT_YVYU:
12365 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012366 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012367 DRM_DEBUG("unsupported pixel format: %s\n",
12368 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012369 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012370 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012371 break;
12372 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012373 DRM_DEBUG("unsupported pixel format: %s\n",
12374 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010012375 return -EINVAL;
12376 }
12377
Ville Syrjälä90f9a332012-10-31 17:50:19 +020012378 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12379 if (mode_cmd->offsets[0] != 0)
12380 return -EINVAL;
12381
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012382 aligned_height = intel_align_height(dev, mode_cmd->height,
12383 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020012384 /* FIXME drm helper for size checks (especially planar formats)? */
12385 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12386 return -EINVAL;
12387
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012388 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12389 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020012390 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012391
Jesse Barnes79e53942008-11-07 14:24:08 -080012392 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12393 if (ret) {
12394 DRM_ERROR("framebuffer init failed %d\n", ret);
12395 return ret;
12396 }
12397
Jesse Barnes79e53942008-11-07 14:24:08 -080012398 return 0;
12399}
12400
Jesse Barnes79e53942008-11-07 14:24:08 -080012401static struct drm_framebuffer *
12402intel_user_framebuffer_create(struct drm_device *dev,
12403 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012404 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080012405{
Chris Wilson05394f32010-11-08 19:18:58 +000012406 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012407
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012408 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12409 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000012410 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010012411 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080012412
Chris Wilsond2dff872011-04-19 08:36:26 +010012413 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080012414}
12415
Daniel Vetter4520f532013-10-09 09:18:51 +020012416#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020012417static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020012418{
12419}
12420#endif
12421
Jesse Barnes79e53942008-11-07 14:24:08 -080012422static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080012423 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020012424 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080012425};
12426
Jesse Barnese70236a2009-09-21 10:42:27 -070012427/* Set up chip specific display functions */
12428static void intel_init_display(struct drm_device *dev)
12429{
12430 struct drm_i915_private *dev_priv = dev->dev_private;
12431
Daniel Vetteree9300b2013-06-03 22:40:22 +020012432 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12433 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030012434 else if (IS_CHERRYVIEW(dev))
12435 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020012436 else if (IS_VALLEYVIEW(dev))
12437 dev_priv->display.find_dpll = vlv_find_best_dpll;
12438 else if (IS_PINEVIEW(dev))
12439 dev_priv->display.find_dpll = pnv_find_best_dpll;
12440 else
12441 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12442
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012443 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012444 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012445 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +020012446 dev_priv->display.crtc_compute_clock =
12447 haswell_crtc_compute_clock;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020012448 dev_priv->display.crtc_enable = haswell_crtc_enable;
12449 dev_priv->display.crtc_disable = haswell_crtc_disable;
Daniel Vetterdf8ad702014-06-25 22:02:03 +030012450 dev_priv->display.off = ironlake_crtc_off;
Damien Lespiau70d21f02013-07-03 21:06:04 +010012451 if (INTEL_INFO(dev)->gen >= 9)
12452 dev_priv->display.update_primary_plane =
12453 skylake_update_primary_plane;
12454 else
12455 dev_priv->display.update_primary_plane =
12456 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012457 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012458 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012459 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +020012460 dev_priv->display.crtc_compute_clock =
12461 ironlake_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012462 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12463 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012464 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012465 dev_priv->display.update_primary_plane =
12466 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012467 } else if (IS_VALLEYVIEW(dev)) {
12468 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012469 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020012470 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012471 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12472 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12473 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012474 dev_priv->display.update_primary_plane =
12475 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012476 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012477 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012478 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020012479 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012480 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12481 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012482 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012483 dev_priv->display.update_primary_plane =
12484 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012485 }
Jesse Barnese70236a2009-09-21 10:42:27 -070012486
Jesse Barnese70236a2009-09-21 10:42:27 -070012487 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070012488 if (IS_VALLEYVIEW(dev))
12489 dev_priv->display.get_display_clock_speed =
12490 valleyview_get_display_clock_speed;
12491 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070012492 dev_priv->display.get_display_clock_speed =
12493 i945_get_display_clock_speed;
12494 else if (IS_I915G(dev))
12495 dev_priv->display.get_display_clock_speed =
12496 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012497 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012498 dev_priv->display.get_display_clock_speed =
12499 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012500 else if (IS_PINEVIEW(dev))
12501 dev_priv->display.get_display_clock_speed =
12502 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070012503 else if (IS_I915GM(dev))
12504 dev_priv->display.get_display_clock_speed =
12505 i915gm_get_display_clock_speed;
12506 else if (IS_I865G(dev))
12507 dev_priv->display.get_display_clock_speed =
12508 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020012509 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012510 dev_priv->display.get_display_clock_speed =
12511 i855_get_display_clock_speed;
12512 else /* 852, 830 */
12513 dev_priv->display.get_display_clock_speed =
12514 i830_get_display_clock_speed;
12515
Jani Nikula7c10a2b2014-10-27 16:26:43 +020012516 if (IS_GEN5(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012517 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012518 } else if (IS_GEN6(dev)) {
12519 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012520 dev_priv->display.modeset_global_resources =
12521 snb_modeset_global_resources;
12522 } else if (IS_IVYBRIDGE(dev)) {
12523 /* FIXME: detect B0+ stepping and use auto training */
12524 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012525 dev_priv->display.modeset_global_resources =
12526 ivb_modeset_global_resources;
Paulo Zanoni059b2fe2014-09-02 16:53:57 -030012527 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012528 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012529 dev_priv->display.modeset_global_resources =
12530 haswell_modeset_global_resources;
Jesse Barnes30a970c2013-11-04 13:48:12 -080012531 } else if (IS_VALLEYVIEW(dev)) {
12532 dev_priv->display.modeset_global_resources =
12533 valleyview_modeset_global_resources;
Satheeshakrishna M02c29252014-04-08 15:46:54 +053012534 } else if (INTEL_INFO(dev)->gen >= 9) {
Satheeshakrishna M02c29252014-04-08 15:46:54 +053012535 dev_priv->display.modeset_global_resources =
12536 haswell_modeset_global_resources;
Jesse Barnese70236a2009-09-21 10:42:27 -070012537 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012538
12539 /* Default just returns -ENODEV to indicate unsupported */
12540 dev_priv->display.queue_flip = intel_default_queue_flip;
12541
12542 switch (INTEL_INFO(dev)->gen) {
12543 case 2:
12544 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12545 break;
12546
12547 case 3:
12548 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12549 break;
12550
12551 case 4:
12552 case 5:
12553 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12554 break;
12555
12556 case 6:
12557 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12558 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012559 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012560 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012561 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12562 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012563 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020012564
12565 intel_panel_init_backlight_funcs(dev);
Ville Syrjäläe39b9992014-09-04 14:53:14 +030012566
12567 mutex_init(&dev_priv->pps_mutex);
Jesse Barnese70236a2009-09-21 10:42:27 -070012568}
12569
Jesse Barnesb690e962010-07-19 13:53:12 -070012570/*
12571 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12572 * resume, or other times. This quirk makes sure that's the case for
12573 * affected systems.
12574 */
Akshay Joshi0206e352011-08-16 15:34:10 -040012575static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070012576{
12577 struct drm_i915_private *dev_priv = dev->dev_private;
12578
12579 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012580 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012581}
12582
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030012583static void quirk_pipeb_force(struct drm_device *dev)
12584{
12585 struct drm_i915_private *dev_priv = dev->dev_private;
12586
12587 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12588 DRM_INFO("applying pipe b force quirk\n");
12589}
12590
Keith Packard435793d2011-07-12 14:56:22 -070012591/*
12592 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12593 */
12594static void quirk_ssc_force_disable(struct drm_device *dev)
12595{
12596 struct drm_i915_private *dev_priv = dev->dev_private;
12597 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012598 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070012599}
12600
Carsten Emde4dca20e2012-03-15 15:56:26 +010012601/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010012602 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12603 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010012604 */
12605static void quirk_invert_brightness(struct drm_device *dev)
12606{
12607 struct drm_i915_private *dev_priv = dev->dev_private;
12608 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012609 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012610}
12611
Scot Doyle9c72cc62014-07-03 23:27:50 +000012612/* Some VBT's incorrectly indicate no backlight is present */
12613static void quirk_backlight_present(struct drm_device *dev)
12614{
12615 struct drm_i915_private *dev_priv = dev->dev_private;
12616 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12617 DRM_INFO("applying backlight present quirk\n");
12618}
12619
Jesse Barnesb690e962010-07-19 13:53:12 -070012620struct intel_quirk {
12621 int device;
12622 int subsystem_vendor;
12623 int subsystem_device;
12624 void (*hook)(struct drm_device *dev);
12625};
12626
Egbert Eich5f85f1762012-10-14 15:46:38 +020012627/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12628struct intel_dmi_quirk {
12629 void (*hook)(struct drm_device *dev);
12630 const struct dmi_system_id (*dmi_id_list)[];
12631};
12632
12633static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12634{
12635 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12636 return 1;
12637}
12638
12639static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12640 {
12641 .dmi_id_list = &(const struct dmi_system_id[]) {
12642 {
12643 .callback = intel_dmi_reverse_brightness,
12644 .ident = "NCR Corporation",
12645 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12646 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12647 },
12648 },
12649 { } /* terminating entry */
12650 },
12651 .hook = quirk_invert_brightness,
12652 },
12653};
12654
Ben Widawskyc43b5632012-04-16 14:07:40 -070012655static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070012656 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040012657 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070012658
Jesse Barnesb690e962010-07-19 13:53:12 -070012659 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12660 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12661
Jesse Barnesb690e962010-07-19 13:53:12 -070012662 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12663 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12664
Ville Syrjälä5f080c02014-08-15 01:22:06 +030012665 /* 830 needs to leave pipe A & dpll A up */
12666 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12667
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030012668 /* 830 needs to leave pipe B & dpll B up */
12669 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12670
Keith Packard435793d2011-07-12 14:56:22 -070012671 /* Lenovo U160 cannot use SSC on LVDS */
12672 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020012673
12674 /* Sony Vaio Y cannot use SSC on LVDS */
12675 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010012676
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010012677 /* Acer Aspire 5734Z must invert backlight brightness */
12678 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12679
12680 /* Acer/eMachines G725 */
12681 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12682
12683 /* Acer/eMachines e725 */
12684 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12685
12686 /* Acer/Packard Bell NCL20 */
12687 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12688
12689 /* Acer Aspire 4736Z */
12690 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020012691
12692 /* Acer Aspire 5336 */
12693 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000012694
12695 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12696 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000012697
Scot Doyledfb3d47b2014-08-21 16:08:02 +000012698 /* Acer C720 Chromebook (Core i3 4005U) */
12699 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12700
Scot Doyled4967d82014-07-03 23:27:52 +000012701 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12702 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000012703
12704 /* HP Chromebook 14 (Celeron 2955U) */
12705 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070012706};
12707
12708static void intel_init_quirks(struct drm_device *dev)
12709{
12710 struct pci_dev *d = dev->pdev;
12711 int i;
12712
12713 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12714 struct intel_quirk *q = &intel_quirks[i];
12715
12716 if (d->device == q->device &&
12717 (d->subsystem_vendor == q->subsystem_vendor ||
12718 q->subsystem_vendor == PCI_ANY_ID) &&
12719 (d->subsystem_device == q->subsystem_device ||
12720 q->subsystem_device == PCI_ANY_ID))
12721 q->hook(dev);
12722 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020012723 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12724 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12725 intel_dmi_quirks[i].hook(dev);
12726 }
Jesse Barnesb690e962010-07-19 13:53:12 -070012727}
12728
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012729/* Disable the VGA plane that we never use */
12730static void i915_disable_vga(struct drm_device *dev)
12731{
12732 struct drm_i915_private *dev_priv = dev->dev_private;
12733 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012734 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012735
Ville Syrjälä2b37c612014-01-22 21:32:38 +020012736 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012737 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070012738 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012739 sr1 = inb(VGA_SR_DATA);
12740 outb(sr1 | 1<<5, VGA_SR_DATA);
12741 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12742 udelay(300);
12743
Ville Syrjälä69769f92014-08-15 01:22:08 +030012744 /*
12745 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12746 * from S3 without preserving (some of?) the other bits.
12747 */
12748 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012749 POSTING_READ(vga_reg);
12750}
12751
Daniel Vetterf8175862012-04-10 15:50:11 +020012752void intel_modeset_init_hw(struct drm_device *dev)
12753{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030012754 intel_prepare_ddi(dev);
12755
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +030012756 if (IS_VALLEYVIEW(dev))
12757 vlv_update_cdclk(dev);
12758
Daniel Vetterf8175862012-04-10 15:50:11 +020012759 intel_init_clock_gating(dev);
12760
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012761 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020012762}
12763
Jesse Barnes79e53942008-11-07 14:24:08 -080012764void intel_modeset_init(struct drm_device *dev)
12765{
Jesse Barnes652c3932009-08-17 13:31:43 -070012766 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000012767 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012768 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080012769 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080012770
12771 drm_mode_config_init(dev);
12772
12773 dev->mode_config.min_width = 0;
12774 dev->mode_config.min_height = 0;
12775
Dave Airlie019d96c2011-09-29 16:20:42 +010012776 dev->mode_config.preferred_depth = 24;
12777 dev->mode_config.prefer_shadow = 1;
12778
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020012779 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080012780
Jesse Barnesb690e962010-07-19 13:53:12 -070012781 intel_init_quirks(dev);
12782
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030012783 intel_init_pm(dev);
12784
Ben Widawskye3c74752013-04-05 13:12:39 -070012785 if (INTEL_INFO(dev)->num_pipes == 0)
12786 return;
12787
Jesse Barnese70236a2009-09-21 10:42:27 -070012788 intel_init_display(dev);
Jani Nikula7c10a2b2014-10-27 16:26:43 +020012789 intel_init_audio(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012790
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012791 if (IS_GEN2(dev)) {
12792 dev->mode_config.max_width = 2048;
12793 dev->mode_config.max_height = 2048;
12794 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070012795 dev->mode_config.max_width = 4096;
12796 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080012797 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012798 dev->mode_config.max_width = 8192;
12799 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080012800 }
Damien Lespiau068be562014-03-28 14:17:49 +000012801
Ville Syrjälädc41c152014-08-13 11:57:05 +030012802 if (IS_845G(dev) || IS_I865G(dev)) {
12803 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12804 dev->mode_config.cursor_height = 1023;
12805 } else if (IS_GEN2(dev)) {
Damien Lespiau068be562014-03-28 14:17:49 +000012806 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12807 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12808 } else {
12809 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12810 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12811 }
12812
Ben Widawsky5d4545a2013-01-17 12:45:15 -080012813 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080012814
Zhao Yakui28c97732009-10-09 11:39:41 +080012815 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012816 INTEL_INFO(dev)->num_pipes,
12817 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080012818
Damien Lespiau055e3932014-08-18 13:49:10 +010012819 for_each_pipe(dev_priv, pipe) {
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012820 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000012821 for_each_sprite(pipe, sprite) {
12822 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012823 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030012824 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000012825 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012826 }
Jesse Barnes79e53942008-11-07 14:24:08 -080012827 }
12828
Jesse Barnesf42bb702013-12-16 16:34:23 -080012829 intel_init_dpio(dev);
12830
Daniel Vettere72f9fb2013-06-05 13:34:06 +020012831 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012832
Ville Syrjälä69769f92014-08-15 01:22:08 +030012833 /* save the BIOS value before clobbering it */
12834 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012835 /* Just disable it once at startup */
12836 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012837 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000012838
12839 /* Just in case the BIOS is doing something questionable. */
12840 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012841
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012842 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012843 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012844 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012845
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012846 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080012847 if (!crtc->active)
12848 continue;
12849
Jesse Barnes46f297f2014-03-07 08:57:48 -080012850 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080012851 * Note that reserving the BIOS fb up front prevents us
12852 * from stuffing other stolen allocations like the ring
12853 * on top. This prevents some ugliness at boot time, and
12854 * can even allow for smooth boot transitions if the BIOS
12855 * fb is large enough for the active pipe configuration.
12856 */
12857 if (dev_priv->display.get_plane_config) {
12858 dev_priv->display.get_plane_config(crtc,
12859 &crtc->plane_config);
12860 /*
12861 * If the fb is shared between multiple heads, we'll
12862 * just get the first one.
12863 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080012864 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012865 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080012866 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010012867}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080012868
Daniel Vetter7fad7982012-07-04 17:51:47 +020012869static void intel_enable_pipe_a(struct drm_device *dev)
12870{
12871 struct intel_connector *connector;
12872 struct drm_connector *crt = NULL;
12873 struct intel_load_detect_pipe load_detect_temp;
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030012874 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020012875
12876 /* We can't just switch on the pipe A, we need to set things up with a
12877 * proper mode and output configuration. As a gross hack, enable pipe A
12878 * by enabling the load detect pipe once. */
12879 list_for_each_entry(connector,
12880 &dev->mode_config.connector_list,
12881 base.head) {
12882 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12883 crt = &connector->base;
12884 break;
12885 }
12886 }
12887
12888 if (!crt)
12889 return;
12890
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030012891 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12892 intel_release_load_detect_pipe(crt, &load_detect_temp);
Daniel Vetter7fad7982012-07-04 17:51:47 +020012893}
12894
Daniel Vetterfa555832012-10-10 23:14:00 +020012895static bool
12896intel_check_plane_mapping(struct intel_crtc *crtc)
12897{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012898 struct drm_device *dev = crtc->base.dev;
12899 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012900 u32 reg, val;
12901
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012902 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020012903 return true;
12904
12905 reg = DSPCNTR(!crtc->plane);
12906 val = I915_READ(reg);
12907
12908 if ((val & DISPLAY_PLANE_ENABLE) &&
12909 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12910 return false;
12911
12912 return true;
12913}
12914
Daniel Vetter24929352012-07-02 20:28:59 +020012915static void intel_sanitize_crtc(struct intel_crtc *crtc)
12916{
12917 struct drm_device *dev = crtc->base.dev;
12918 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012919 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020012920
Daniel Vetter24929352012-07-02 20:28:59 +020012921 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020012922 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020012923 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12924
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012925 /* restore vblank interrupts to correct state */
Ville Syrjäläd297e102014-08-06 14:50:01 +030012926 if (crtc->active) {
12927 update_scanline_offset(crtc);
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012928 drm_vblank_on(dev, crtc->pipe);
Ville Syrjäläd297e102014-08-06 14:50:01 +030012929 } else
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012930 drm_vblank_off(dev, crtc->pipe);
12931
Daniel Vetter24929352012-07-02 20:28:59 +020012932 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020012933 * disable the crtc (and hence change the state) if it is wrong. Note
12934 * that gen4+ has a fixed plane -> pipe mapping. */
12935 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020012936 struct intel_connector *connector;
12937 bool plane;
12938
Daniel Vetter24929352012-07-02 20:28:59 +020012939 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12940 crtc->base.base.id);
12941
12942 /* Pipe has the wrong plane attached and the plane is active.
12943 * Temporarily change the plane mapping and disable everything
12944 * ... */
12945 plane = crtc->plane;
12946 crtc->plane = !plane;
Daniel Vetter9c8958b2014-07-14 19:35:31 +020012947 crtc->primary_enabled = true;
Daniel Vetter24929352012-07-02 20:28:59 +020012948 dev_priv->display.crtc_disable(&crtc->base);
12949 crtc->plane = plane;
12950
12951 /* ... and break all links. */
12952 list_for_each_entry(connector, &dev->mode_config.connector_list,
12953 base.head) {
12954 if (connector->encoder->base.crtc != &crtc->base)
12955 continue;
12956
Egbert Eich7f1950f2014-04-25 10:56:22 +020012957 connector->base.dpms = DRM_MODE_DPMS_OFF;
12958 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020012959 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020012960 /* multiple connectors may have the same encoder:
12961 * handle them and break crtc link separately */
12962 list_for_each_entry(connector, &dev->mode_config.connector_list,
12963 base.head)
12964 if (connector->encoder->base.crtc == &crtc->base) {
12965 connector->encoder->base.crtc = NULL;
12966 connector->encoder->connectors_active = false;
12967 }
Daniel Vetter24929352012-07-02 20:28:59 +020012968
12969 WARN_ON(crtc->active);
12970 crtc->base.enabled = false;
12971 }
Daniel Vetter24929352012-07-02 20:28:59 +020012972
Daniel Vetter7fad7982012-07-04 17:51:47 +020012973 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12974 crtc->pipe == PIPE_A && !crtc->active) {
12975 /* BIOS forgot to enable pipe A, this mostly happens after
12976 * resume. Force-enable the pipe to fix this, the update_dpms
12977 * call below we restore the pipe to the right state, but leave
12978 * the required bits on. */
12979 intel_enable_pipe_a(dev);
12980 }
12981
Daniel Vetter24929352012-07-02 20:28:59 +020012982 /* Adjust the state of the output pipe according to whether we
12983 * have active connectors/encoders. */
12984 intel_crtc_update_dpms(&crtc->base);
12985
12986 if (crtc->active != crtc->base.enabled) {
12987 struct intel_encoder *encoder;
12988
12989 /* This can happen either due to bugs in the get_hw_state
12990 * functions or because the pipe is force-enabled due to the
12991 * pipe A quirk. */
12992 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12993 crtc->base.base.id,
12994 crtc->base.enabled ? "enabled" : "disabled",
12995 crtc->active ? "enabled" : "disabled");
12996
12997 crtc->base.enabled = crtc->active;
12998
12999 /* Because we only establish the connector -> encoder ->
13000 * crtc links if something is active, this means the
13001 * crtc is now deactivated. Break the links. connector
13002 * -> encoder links are only establish when things are
13003 * actually up, hence no need to break them. */
13004 WARN_ON(crtc->active);
13005
13006 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13007 WARN_ON(encoder->connectors_active);
13008 encoder->base.crtc = NULL;
13009 }
13010 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020013011
Ville Syrjäläa3ed6aa2014-09-03 14:09:52 +030013012 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010013013 /*
13014 * We start out with underrun reporting disabled to avoid races.
13015 * For correct bookkeeping mark this on active crtcs.
13016 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020013017 * Also on gmch platforms we dont have any hardware bits to
13018 * disable the underrun reporting. Which means we need to start
13019 * out with underrun reporting disabled also on inactive pipes,
13020 * since otherwise we'll complain about the garbage we read when
13021 * e.g. coming up after runtime pm.
13022 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010013023 * No protection against concurrent access is required - at
13024 * worst a fifo underrun happens which also sets this to false.
13025 */
13026 crtc->cpu_fifo_underrun_disabled = true;
13027 crtc->pch_fifo_underrun_disabled = true;
13028 }
Daniel Vetter24929352012-07-02 20:28:59 +020013029}
13030
13031static void intel_sanitize_encoder(struct intel_encoder *encoder)
13032{
13033 struct intel_connector *connector;
13034 struct drm_device *dev = encoder->base.dev;
13035
13036 /* We need to check both for a crtc link (meaning that the
13037 * encoder is active and trying to read from a pipe) and the
13038 * pipe itself being active. */
13039 bool has_active_crtc = encoder->base.crtc &&
13040 to_intel_crtc(encoder->base.crtc)->active;
13041
13042 if (encoder->connectors_active && !has_active_crtc) {
13043 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13044 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013045 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020013046
13047 /* Connector is active, but has no active pipe. This is
13048 * fallout from our resume register restoring. Disable
13049 * the encoder manually again. */
13050 if (encoder->base.crtc) {
13051 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13052 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013053 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020013054 encoder->disable(encoder);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030013055 if (encoder->post_disable)
13056 encoder->post_disable(encoder);
Daniel Vetter24929352012-07-02 20:28:59 +020013057 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020013058 encoder->base.crtc = NULL;
13059 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020013060
13061 /* Inconsistent output/port/pipe state happens presumably due to
13062 * a bug in one of the get_hw_state functions. Or someplace else
13063 * in our code, like the register restore mess on resume. Clamp
13064 * things to off as a safer default. */
13065 list_for_each_entry(connector,
13066 &dev->mode_config.connector_list,
13067 base.head) {
13068 if (connector->encoder != encoder)
13069 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020013070 connector->base.dpms = DRM_MODE_DPMS_OFF;
13071 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020013072 }
13073 }
13074 /* Enabled encoders without active connectors will be fixed in
13075 * the crtc fixup. */
13076}
13077
Imre Deak04098752014-02-18 00:02:16 +020013078void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013079{
13080 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020013081 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013082
Imre Deak04098752014-02-18 00:02:16 +020013083 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13084 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13085 i915_disable_vga(dev);
13086 }
13087}
13088
13089void i915_redisable_vga(struct drm_device *dev)
13090{
13091 struct drm_i915_private *dev_priv = dev->dev_private;
13092
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013093 /* This function can be called both from intel_modeset_setup_hw_state or
13094 * at a very early point in our resume sequence, where the power well
13095 * structures are not yet restored. Since this function is at a very
13096 * paranoid "someone might have enabled VGA while we were not looking"
13097 * level, just check if the power well is enabled instead of trying to
13098 * follow the "don't touch the power well if we don't need it" policy
13099 * the rest of the driver uses. */
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013100 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013101 return;
13102
Imre Deak04098752014-02-18 00:02:16 +020013103 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013104}
13105
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013106static bool primary_get_hw_state(struct intel_crtc *crtc)
13107{
13108 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13109
13110 if (!crtc->active)
13111 return false;
13112
13113 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13114}
13115
Daniel Vetter30e984d2013-06-05 13:34:17 +020013116static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020013117{
13118 struct drm_i915_private *dev_priv = dev->dev_private;
13119 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020013120 struct intel_crtc *crtc;
13121 struct intel_encoder *encoder;
13122 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020013123 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020013124
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013125 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010013126 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020013127
Daniel Vetter99535992014-04-13 12:00:33 +020013128 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13129
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013130 crtc->active = dev_priv->display.get_pipe_config(crtc,
13131 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013132
13133 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013134 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020013135
13136 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13137 crtc->base.base.id,
13138 crtc->active ? "enabled" : "disabled");
13139 }
13140
Daniel Vetter53589012013-06-05 13:34:16 +020013141 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13142 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13143
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013144 pll->on = pll->get_hw_state(dev_priv, pll,
13145 &pll->config.hw_state);
Daniel Vetter53589012013-06-05 13:34:16 +020013146 pll->active = 0;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013147 pll->config.crtc_mask = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013148 for_each_intel_crtc(dev, crtc) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013149 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
Daniel Vetter53589012013-06-05 13:34:16 +020013150 pll->active++;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013151 pll->config.crtc_mask |= 1 << crtc->pipe;
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013152 }
Daniel Vetter53589012013-06-05 13:34:16 +020013153 }
Daniel Vetter53589012013-06-05 13:34:16 +020013154
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013155 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013156 pll->name, pll->config.crtc_mask, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013157
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013158 if (pll->config.crtc_mask)
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013159 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020013160 }
13161
Damien Lespiaub2784e12014-08-05 11:29:37 +010013162 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013163 pipe = 0;
13164
13165 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070013166 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13167 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010013168 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013169 } else {
13170 encoder->base.crtc = NULL;
13171 }
13172
13173 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013174 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020013175 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013176 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013177 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013178 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020013179 }
13180
13181 list_for_each_entry(connector, &dev->mode_config.connector_list,
13182 base.head) {
13183 if (connector->get_hw_state(connector)) {
13184 connector->base.dpms = DRM_MODE_DPMS_ON;
13185 connector->encoder->connectors_active = true;
13186 connector->base.encoder = &connector->encoder->base;
13187 } else {
13188 connector->base.dpms = DRM_MODE_DPMS_OFF;
13189 connector->base.encoder = NULL;
13190 }
13191 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13192 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030013193 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013194 connector->base.encoder ? "enabled" : "disabled");
13195 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020013196}
13197
13198/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13199 * and i915 state tracking structures. */
13200void intel_modeset_setup_hw_state(struct drm_device *dev,
13201 bool force_restore)
13202{
13203 struct drm_i915_private *dev_priv = dev->dev_private;
13204 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013205 struct intel_crtc *crtc;
13206 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020013207 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013208
13209 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020013210
Jesse Barnesbabea612013-06-26 18:57:38 +030013211 /*
13212 * Now that we have the config, copy it to each CRTC struct
13213 * Note that this could go away if we move to using crtc_config
13214 * checking everywhere.
13215 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013216 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020013217 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080013218 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030013219 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13220 crtc->base.base.id);
13221 drm_mode_debug_printmodeline(&crtc->base.mode);
13222 }
13223 }
13224
Daniel Vetter24929352012-07-02 20:28:59 +020013225 /* HW state is read out, now we need to sanitize this mess. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010013226 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013227 intel_sanitize_encoder(encoder);
13228 }
13229
Damien Lespiau055e3932014-08-18 13:49:10 +010013230 for_each_pipe(dev_priv, pipe) {
Daniel Vetter24929352012-07-02 20:28:59 +020013231 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13232 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020013233 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020013234 }
Daniel Vetter9a935852012-07-05 22:34:27 +020013235
Daniel Vetter35c95372013-07-17 06:55:04 +020013236 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13237 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13238
13239 if (!pll->on || pll->active)
13240 continue;
13241
13242 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13243
13244 pll->disable(dev_priv, pll);
13245 pll->on = false;
13246 }
13247
Ville Syrjälä96f90c52013-12-05 15:51:38 +020013248 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030013249 ilk_wm_get_hw_state(dev);
13250
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013251 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030013252 i915_redisable_vga(dev);
13253
Daniel Vetterf30da182013-04-11 20:22:50 +020013254 /*
13255 * We need to use raw interfaces for restoring state to avoid
13256 * checking (bogus) intermediate states.
13257 */
Damien Lespiau055e3932014-08-18 13:49:10 +010013258 for_each_pipe(dev_priv, pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070013259 struct drm_crtc *crtc =
13260 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020013261
13262 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
Matt Roperf4510a22014-04-01 15:22:40 -070013263 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013264 }
13265 } else {
13266 intel_modeset_update_staged_output_state(dev);
13267 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013268
13269 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010013270}
13271
13272void intel_modeset_gem_init(struct drm_device *dev)
13273{
Jesse Barnes484b41d2014-03-07 08:57:55 -080013274 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070013275 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013276
Imre Deakae484342014-03-31 15:10:44 +030013277 mutex_lock(&dev->struct_mutex);
13278 intel_init_gt_powersave(dev);
13279 mutex_unlock(&dev->struct_mutex);
13280
Chris Wilson1833b132012-05-09 11:56:28 +010013281 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020013282
13283 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080013284
13285 /*
13286 * Make sure any fbs we allocated at startup are properly
13287 * pinned & fenced. When we do the allocation it's too early
13288 * for this.
13289 */
13290 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010013291 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070013292 obj = intel_fb_obj(c->primary->fb);
13293 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080013294 continue;
13295
Matt Roper2ff8fde2014-07-08 07:50:07 -070013296 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080013297 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13298 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100013299 drm_framebuffer_unreference(c->primary->fb);
13300 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013301 }
13302 }
13303 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013304}
13305
Imre Deak4932e2c2014-02-11 17:12:48 +020013306void intel_connector_unregister(struct intel_connector *intel_connector)
13307{
13308 struct drm_connector *connector = &intel_connector->base;
13309
13310 intel_panel_destroy_backlight(connector);
Thomas Wood34ea3d32014-05-29 16:57:41 +010013311 drm_connector_unregister(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020013312}
13313
Jesse Barnes79e53942008-11-07 14:24:08 -080013314void intel_modeset_cleanup(struct drm_device *dev)
13315{
Jesse Barnes652c3932009-08-17 13:31:43 -070013316 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid9255d52013-09-26 20:05:59 -030013317 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070013318
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013319 /*
13320 * Interrupts and polling as the first thing to avoid creating havoc.
13321 * Too much stuff here (turning of rps, connectors, ...) would
13322 * experience fancy races otherwise.
13323 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +020013324 intel_irq_uninstall(dev_priv);
Jesse Barneseb21b922014-06-20 11:57:33 -070013325
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013326 /*
13327 * Due to the hpd irq storm handling the hotplug work can re-arm the
13328 * poll handlers. Hence disable polling after hpd handling is shut down.
13329 */
Keith Packardf87ea762010-10-03 19:36:26 -070013330 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013331
Jesse Barnes652c3932009-08-17 13:31:43 -070013332 mutex_lock(&dev->struct_mutex);
13333
Jesse Barnes723bfd72010-10-07 16:01:13 -070013334 intel_unregister_dsm_handler();
13335
Chris Wilson973d04f2011-07-08 12:22:37 +010013336 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070013337
Daniel Vetter8090c6b2012-06-24 16:42:32 +020013338 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000013339
Daniel Vetter930ebb42012-06-29 23:32:16 +020013340 ironlake_teardown_rc6(dev);
13341
Kristian Høgsberg69341a52009-11-11 12:19:17 -050013342 mutex_unlock(&dev->struct_mutex);
13343
Chris Wilson1630fe72011-07-08 12:22:42 +010013344 /* flush any delayed tasks or pending work */
13345 flush_scheduled_work();
13346
Jani Nikuladb31af12013-11-08 16:48:53 +020013347 /* destroy the backlight and sysfs files before encoders/connectors */
13348 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020013349 struct intel_connector *intel_connector;
13350
13351 intel_connector = to_intel_connector(connector);
13352 intel_connector->unregister(intel_connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020013353 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030013354
Jesse Barnes79e53942008-11-07 14:24:08 -080013355 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010013356
13357 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030013358
13359 mutex_lock(&dev->struct_mutex);
13360 intel_cleanup_gt_powersave(dev);
13361 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013362}
13363
Dave Airlie28d52042009-09-21 14:33:58 +100013364/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080013365 * Return which encoder is currently attached for connector.
13366 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010013367struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080013368{
Chris Wilsondf0e9242010-09-09 16:20:55 +010013369 return &intel_attached_encoder(connector)->base;
13370}
Jesse Barnes79e53942008-11-07 14:24:08 -080013371
Chris Wilsondf0e9242010-09-09 16:20:55 +010013372void intel_connector_attach_encoder(struct intel_connector *connector,
13373 struct intel_encoder *encoder)
13374{
13375 connector->encoder = encoder;
13376 drm_mode_connector_attach_encoder(&connector->base,
13377 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080013378}
Dave Airlie28d52042009-09-21 14:33:58 +100013379
13380/*
13381 * set vga decode state - true == enable VGA decode
13382 */
13383int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13384{
13385 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000013386 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100013387 u16 gmch_ctrl;
13388
Chris Wilson75fa0412014-02-07 18:37:02 -020013389 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13390 DRM_ERROR("failed to read control word\n");
13391 return -EIO;
13392 }
13393
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020013394 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13395 return 0;
13396
Dave Airlie28d52042009-09-21 14:33:58 +100013397 if (state)
13398 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13399 else
13400 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020013401
13402 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13403 DRM_ERROR("failed to write control word\n");
13404 return -EIO;
13405 }
13406
Dave Airlie28d52042009-09-21 14:33:58 +100013407 return 0;
13408}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013409
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013410struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013411
13412 u32 power_well_driver;
13413
Chris Wilson63b66e52013-08-08 15:12:06 +020013414 int num_transcoders;
13415
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013416 struct intel_cursor_error_state {
13417 u32 control;
13418 u32 position;
13419 u32 base;
13420 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010013421 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013422
13423 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013424 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013425 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030013426 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010013427 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013428
13429 struct intel_plane_error_state {
13430 u32 control;
13431 u32 stride;
13432 u32 size;
13433 u32 pos;
13434 u32 addr;
13435 u32 surface;
13436 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010013437 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020013438
13439 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013440 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020013441 enum transcoder cpu_transcoder;
13442
13443 u32 conf;
13444
13445 u32 htotal;
13446 u32 hblank;
13447 u32 hsync;
13448 u32 vtotal;
13449 u32 vblank;
13450 u32 vsync;
13451 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013452};
13453
13454struct intel_display_error_state *
13455intel_display_capture_error_state(struct drm_device *dev)
13456{
Jani Nikulafbee40d2014-03-31 14:27:18 +030013457 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013458 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020013459 int transcoders[] = {
13460 TRANSCODER_A,
13461 TRANSCODER_B,
13462 TRANSCODER_C,
13463 TRANSCODER_EDP,
13464 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013465 int i;
13466
Chris Wilson63b66e52013-08-08 15:12:06 +020013467 if (INTEL_INFO(dev)->num_pipes == 0)
13468 return NULL;
13469
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013470 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013471 if (error == NULL)
13472 return NULL;
13473
Imre Deak190be112013-11-25 17:15:31 +020013474 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013475 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13476
Damien Lespiau055e3932014-08-18 13:49:10 +010013477 for_each_pipe(dev_priv, i) {
Imre Deakddf9c532013-11-27 22:02:02 +020013478 error->pipe[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013479 __intel_display_power_is_enabled(dev_priv,
13480 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020013481 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013482 continue;
13483
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030013484 error->cursor[i].control = I915_READ(CURCNTR(i));
13485 error->cursor[i].position = I915_READ(CURPOS(i));
13486 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013487
13488 error->plane[i].control = I915_READ(DSPCNTR(i));
13489 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013490 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030013491 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013492 error->plane[i].pos = I915_READ(DSPPOS(i));
13493 }
Paulo Zanonica291362013-03-06 20:03:14 -030013494 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13495 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013496 if (INTEL_INFO(dev)->gen >= 4) {
13497 error->plane[i].surface = I915_READ(DSPSURF(i));
13498 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13499 }
13500
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013501 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030013502
Sonika Jindal3abfce72014-07-21 15:23:43 +053013503 if (HAS_GMCH_DISPLAY(dev))
Imre Deakf301b1e2014-04-18 15:55:04 +030013504 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020013505 }
13506
13507 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13508 if (HAS_DDI(dev_priv->dev))
13509 error->num_transcoders++; /* Account for eDP. */
13510
13511 for (i = 0; i < error->num_transcoders; i++) {
13512 enum transcoder cpu_transcoder = transcoders[i];
13513
Imre Deakddf9c532013-11-27 22:02:02 +020013514 error->transcoder[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013515 __intel_display_power_is_enabled(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020013516 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013517 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013518 continue;
13519
Chris Wilson63b66e52013-08-08 15:12:06 +020013520 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13521
13522 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13523 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13524 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13525 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13526 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13527 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13528 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013529 }
13530
13531 return error;
13532}
13533
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013534#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13535
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013536void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013537intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013538 struct drm_device *dev,
13539 struct intel_display_error_state *error)
13540{
Damien Lespiau055e3932014-08-18 13:49:10 +010013541 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013542 int i;
13543
Chris Wilson63b66e52013-08-08 15:12:06 +020013544 if (!error)
13545 return;
13546
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013547 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020013548 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013549 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013550 error->power_well_driver);
Damien Lespiau055e3932014-08-18 13:49:10 +010013551 for_each_pipe(dev_priv, i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013552 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020013553 err_printf(m, " Power: %s\n",
13554 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013555 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030013556 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013557
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013558 err_printf(m, "Plane [%d]:\n", i);
13559 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13560 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013561 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013562 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13563 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013564 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030013565 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013566 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013567 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013568 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13569 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013570 }
13571
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013572 err_printf(m, "Cursor [%d]:\n", i);
13573 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13574 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13575 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013576 }
Chris Wilson63b66e52013-08-08 15:12:06 +020013577
13578 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010013579 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020013580 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013581 err_printf(m, " Power: %s\n",
13582 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020013583 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13584 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13585 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13586 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13587 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13588 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13589 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13590 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013591}
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013592
13593void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13594{
13595 struct intel_crtc *crtc;
13596
13597 for_each_intel_crtc(dev, crtc) {
13598 struct intel_unpin_work *work;
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013599
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020013600 spin_lock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013601
13602 work = crtc->unpin_work;
13603
13604 if (work && work->event &&
13605 work->event->base.file_priv == file) {
13606 kfree(work->event);
13607 work->event = NULL;
13608 }
13609
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020013610 spin_unlock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013611 }
13612}