Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 31 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 33 | #include <linux/circ_buf.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 34 | #include <drm/drmP.h> |
| 35 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 37 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 40 | static const u32 hpd_ibx[] = { |
| 41 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
| 42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, |
| 43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, |
| 44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, |
| 45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG |
| 46 | }; |
| 47 | |
| 48 | static const u32 hpd_cpt[] = { |
| 49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
Daniel Vetter | 73c352a | 2013-03-26 22:38:43 +0100 | [diff] [blame] | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
| 52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, |
| 53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT |
| 54 | }; |
| 55 | |
| 56 | static const u32 hpd_mask_i915[] = { |
| 57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
| 58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, |
| 59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, |
| 60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, |
| 61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, |
| 62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN |
| 63 | }; |
| 64 | |
Daniel Vetter | 704cfb8 | 2013-12-18 09:08:43 +0100 | [diff] [blame] | 65 | static const u32 hpd_status_g4x[] = { |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, |
| 68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, |
| 69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 72 | }; |
| 73 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
| 75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, |
| 77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, |
| 78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 81 | }; |
| 82 | |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 83 | /* IIR can theoretically queue up two events. Be paranoid. */ |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 84 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 85 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
| 86 | POSTING_READ(GEN8_##type##_IMR(which)); \ |
| 87 | I915_WRITE(GEN8_##type##_IER(which), 0); \ |
| 88 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 89 | POSTING_READ(GEN8_##type##_IIR(which)); \ |
| 90 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 91 | POSTING_READ(GEN8_##type##_IIR(which)); \ |
| 92 | } while (0) |
| 93 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 94 | #define GEN5_IRQ_RESET(type) do { \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 95 | I915_WRITE(type##IMR, 0xffffffff); \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 96 | POSTING_READ(type##IMR); \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 97 | I915_WRITE(type##IER, 0); \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 98 | I915_WRITE(type##IIR, 0xffffffff); \ |
| 99 | POSTING_READ(type##IIR); \ |
| 100 | I915_WRITE(type##IIR, 0xffffffff); \ |
| 101 | POSTING_READ(type##IIR); \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 102 | } while (0) |
| 103 | |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 104 | /* |
| 105 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. |
| 106 | */ |
| 107 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ |
| 108 | u32 val = I915_READ(reg); \ |
| 109 | if (val) { \ |
| 110 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ |
| 111 | (reg), val); \ |
| 112 | I915_WRITE((reg), 0xffffffff); \ |
| 113 | POSTING_READ(reg); \ |
| 114 | I915_WRITE((reg), 0xffffffff); \ |
| 115 | POSTING_READ(reg); \ |
| 116 | } \ |
| 117 | } while (0) |
| 118 | |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 119 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 120 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 121 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
| 122 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
| 123 | POSTING_READ(GEN8_##type##_IER(which)); \ |
| 124 | } while (0) |
| 125 | |
| 126 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 127 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 128 | I915_WRITE(type##IMR, (imr_val)); \ |
| 129 | I915_WRITE(type##IER, (ier_val)); \ |
| 130 | POSTING_READ(type##IER); \ |
| 131 | } while (0) |
| 132 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 133 | /* For display hotplug interrupt */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 134 | static void |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 135 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 136 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 137 | assert_spin_locked(&dev_priv->irq_lock); |
| 138 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 139 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 140 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 141 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 142 | if ((dev_priv->irq_mask & mask) != 0) { |
| 143 | dev_priv->irq_mask &= ~mask; |
| 144 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 145 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 146 | } |
| 147 | } |
| 148 | |
Paulo Zanoni | 0ff9800 | 2013-02-22 17:05:31 -0300 | [diff] [blame] | 149 | static void |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 150 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 151 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 152 | assert_spin_locked(&dev_priv->irq_lock); |
| 153 | |
Paulo Zanoni | 06ffc77 | 2014-07-17 17:43:46 -0300 | [diff] [blame] | 154 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 155 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 156 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 157 | if ((dev_priv->irq_mask & mask) != mask) { |
| 158 | dev_priv->irq_mask |= mask; |
| 159 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 160 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 161 | } |
| 162 | } |
| 163 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 164 | /** |
| 165 | * ilk_update_gt_irq - update GTIMR |
| 166 | * @dev_priv: driver private |
| 167 | * @interrupt_mask: mask of interrupt bits to update |
| 168 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 169 | */ |
| 170 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, |
| 171 | uint32_t interrupt_mask, |
| 172 | uint32_t enabled_irq_mask) |
| 173 | { |
| 174 | assert_spin_locked(&dev_priv->irq_lock); |
| 175 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 176 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 177 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 178 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 179 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
| 180 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); |
| 181 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 182 | POSTING_READ(GTIMR); |
| 183 | } |
| 184 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 185 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 186 | { |
| 187 | ilk_update_gt_irq(dev_priv, mask, mask); |
| 188 | } |
| 189 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 190 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 191 | { |
| 192 | ilk_update_gt_irq(dev_priv, mask, 0); |
| 193 | } |
| 194 | |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 195 | /** |
| 196 | * snb_update_pm_irq - update GEN6_PMIMR |
| 197 | * @dev_priv: driver private |
| 198 | * @interrupt_mask: mask of interrupt bits to update |
| 199 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 200 | */ |
| 201 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
| 202 | uint32_t interrupt_mask, |
| 203 | uint32_t enabled_irq_mask) |
| 204 | { |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 205 | uint32_t new_val; |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 206 | |
| 207 | assert_spin_locked(&dev_priv->irq_lock); |
| 208 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 209 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 210 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 211 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 212 | new_val = dev_priv->pm_irq_mask; |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 213 | new_val &= ~interrupt_mask; |
| 214 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 215 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 216 | if (new_val != dev_priv->pm_irq_mask) { |
| 217 | dev_priv->pm_irq_mask = new_val; |
| 218 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 219 | POSTING_READ(GEN6_PMIMR); |
| 220 | } |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 221 | } |
| 222 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 223 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 224 | { |
| 225 | snb_update_pm_irq(dev_priv, mask, mask); |
| 226 | } |
| 227 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 228 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 229 | { |
| 230 | snb_update_pm_irq(dev_priv, mask, 0); |
| 231 | } |
| 232 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 233 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
| 234 | { |
| 235 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 236 | struct intel_crtc *crtc; |
| 237 | enum pipe pipe; |
| 238 | |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 239 | assert_spin_locked(&dev_priv->irq_lock); |
| 240 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 241 | for_each_pipe(dev_priv, pipe) { |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 242 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 243 | |
| 244 | if (crtc->cpu_fifo_underrun_disabled) |
| 245 | return false; |
| 246 | } |
| 247 | |
| 248 | return true; |
| 249 | } |
| 250 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 251 | /** |
| 252 | * bdw_update_pm_irq - update GT interrupt 2 |
| 253 | * @dev_priv: driver private |
| 254 | * @interrupt_mask: mask of interrupt bits to update |
| 255 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 256 | * |
| 257 | * Copied from the snb function, updated with relevant register offsets |
| 258 | */ |
| 259 | static void bdw_update_pm_irq(struct drm_i915_private *dev_priv, |
| 260 | uint32_t interrupt_mask, |
| 261 | uint32_t enabled_irq_mask) |
| 262 | { |
| 263 | uint32_t new_val; |
| 264 | |
| 265 | assert_spin_locked(&dev_priv->irq_lock); |
| 266 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 267 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 268 | return; |
| 269 | |
| 270 | new_val = dev_priv->pm_irq_mask; |
| 271 | new_val &= ~interrupt_mask; |
| 272 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 273 | |
| 274 | if (new_val != dev_priv->pm_irq_mask) { |
| 275 | dev_priv->pm_irq_mask = new_val; |
| 276 | I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask); |
| 277 | POSTING_READ(GEN8_GT_IMR(2)); |
| 278 | } |
| 279 | } |
| 280 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 281 | void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 282 | { |
| 283 | bdw_update_pm_irq(dev_priv, mask, mask); |
| 284 | } |
| 285 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 286 | void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 287 | { |
| 288 | bdw_update_pm_irq(dev_priv, mask, 0); |
| 289 | } |
| 290 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 291 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
| 292 | { |
| 293 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 294 | enum pipe pipe; |
| 295 | struct intel_crtc *crtc; |
| 296 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 297 | assert_spin_locked(&dev_priv->irq_lock); |
| 298 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 299 | for_each_pipe(dev_priv, pipe) { |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 300 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 301 | |
| 302 | if (crtc->pch_fifo_underrun_disabled) |
| 303 | return false; |
| 304 | } |
| 305 | |
| 306 | return true; |
| 307 | } |
| 308 | |
Ville Syrjälä | 56b80e1 | 2014-05-16 19:40:22 +0300 | [diff] [blame] | 309 | void i9xx_check_fifo_underruns(struct drm_device *dev) |
| 310 | { |
| 311 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 312 | struct intel_crtc *crtc; |
| 313 | unsigned long flags; |
| 314 | |
| 315 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 316 | |
| 317 | for_each_intel_crtc(dev, crtc) { |
| 318 | u32 reg = PIPESTAT(crtc->pipe); |
| 319 | u32 pipestat; |
| 320 | |
| 321 | if (crtc->cpu_fifo_underrun_disabled) |
| 322 | continue; |
| 323 | |
| 324 | pipestat = I915_READ(reg) & 0xffff0000; |
| 325 | if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) |
| 326 | continue; |
| 327 | |
| 328 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
| 329 | POSTING_READ(reg); |
| 330 | |
| 331 | DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); |
| 332 | } |
| 333 | |
| 334 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 335 | } |
| 336 | |
Ville Syrjälä | e69abff | 2014-05-16 19:40:21 +0300 | [diff] [blame] | 337 | static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 338 | enum pipe pipe, |
| 339 | bool enable, bool old) |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 340 | { |
| 341 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 342 | u32 reg = PIPESTAT(pipe); |
Ville Syrjälä | e69abff | 2014-05-16 19:40:21 +0300 | [diff] [blame] | 343 | u32 pipestat = I915_READ(reg) & 0xffff0000; |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 344 | |
| 345 | assert_spin_locked(&dev_priv->irq_lock); |
| 346 | |
Ville Syrjälä | e69abff | 2014-05-16 19:40:21 +0300 | [diff] [blame] | 347 | if (enable) { |
| 348 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); |
| 349 | POSTING_READ(reg); |
| 350 | } else { |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 351 | if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) |
Ville Syrjälä | e69abff | 2014-05-16 19:40:21 +0300 | [diff] [blame] | 352 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
| 353 | } |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 354 | } |
| 355 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 356 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
| 357 | enum pipe pipe, bool enable) |
| 358 | { |
| 359 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 360 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : |
| 361 | DE_PIPEB_FIFO_UNDERRUN; |
| 362 | |
| 363 | if (enable) |
| 364 | ironlake_enable_display_irq(dev_priv, bit); |
| 365 | else |
| 366 | ironlake_disable_display_irq(dev_priv, bit); |
| 367 | } |
| 368 | |
| 369 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 370 | enum pipe pipe, |
| 371 | bool enable, bool old) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 372 | { |
| 373 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 374 | if (enable) { |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 375 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
| 376 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 377 | if (!ivb_can_enable_err_int(dev)) |
| 378 | return; |
| 379 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 380 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| 381 | } else { |
| 382 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 383 | |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 384 | if (old && |
| 385 | I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { |
Ville Syrjälä | 823c690 | 2014-05-16 19:40:23 +0300 | [diff] [blame] | 386 | DRM_ERROR("uncleared fifo underrun on pipe %c\n", |
| 387 | pipe_name(pipe)); |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 388 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 389 | } |
| 390 | } |
| 391 | |
Daniel Vetter | 38d83c96 | 2013-11-07 11:05:46 +0100 | [diff] [blame] | 392 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
| 393 | enum pipe pipe, bool enable) |
| 394 | { |
| 395 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 396 | |
| 397 | assert_spin_locked(&dev_priv->irq_lock); |
| 398 | |
| 399 | if (enable) |
| 400 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; |
| 401 | else |
| 402 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; |
| 403 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 404 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
| 405 | } |
| 406 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 407 | /** |
| 408 | * ibx_display_interrupt_update - update SDEIMR |
| 409 | * @dev_priv: driver private |
| 410 | * @interrupt_mask: mask of interrupt bits to update |
| 411 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 412 | */ |
| 413 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
| 414 | uint32_t interrupt_mask, |
| 415 | uint32_t enabled_irq_mask) |
| 416 | { |
| 417 | uint32_t sdeimr = I915_READ(SDEIMR); |
| 418 | sdeimr &= ~interrupt_mask; |
| 419 | sdeimr |= (~enabled_irq_mask & interrupt_mask); |
| 420 | |
| 421 | assert_spin_locked(&dev_priv->irq_lock); |
| 422 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 423 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 424 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 425 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 426 | I915_WRITE(SDEIMR, sdeimr); |
| 427 | POSTING_READ(SDEIMR); |
| 428 | } |
| 429 | #define ibx_enable_display_interrupt(dev_priv, bits) \ |
| 430 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) |
| 431 | #define ibx_disable_display_interrupt(dev_priv, bits) \ |
| 432 | ibx_display_interrupt_update((dev_priv), (bits), 0) |
| 433 | |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 434 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
| 435 | enum transcoder pch_transcoder, |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 436 | bool enable) |
| 437 | { |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 438 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 439 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
| 440 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 441 | |
| 442 | if (enable) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 443 | ibx_enable_display_interrupt(dev_priv, bit); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 444 | else |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 445 | ibx_disable_display_interrupt(dev_priv, bit); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, |
| 449 | enum transcoder pch_transcoder, |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 450 | bool enable, bool old) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 451 | { |
| 452 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 453 | |
| 454 | if (enable) { |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 455 | I915_WRITE(SERR_INT, |
| 456 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); |
| 457 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 458 | if (!cpt_can_enable_serr_int(dev)) |
| 459 | return; |
| 460 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 461 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 462 | } else { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 463 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 464 | |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 465 | if (old && I915_READ(SERR_INT) & |
| 466 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { |
Ville Syrjälä | 823c690 | 2014-05-16 19:40:23 +0300 | [diff] [blame] | 467 | DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", |
| 468 | transcoder_name(pch_transcoder)); |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 469 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 470 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | /** |
| 474 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages |
| 475 | * @dev: drm device |
| 476 | * @pipe: pipe |
| 477 | * @enable: true if we want to report FIFO underrun errors, false otherwise |
| 478 | * |
| 479 | * This function makes us disable or enable CPU fifo underruns for a specific |
| 480 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun |
| 481 | * reporting for one pipe may also disable all the other CPU error interruts for |
| 482 | * the other pipes, due to the fact that there's just one interrupt mask/enable |
| 483 | * bit for all the pipes. |
| 484 | * |
| 485 | * Returns the previous state of underrun reporting. |
| 486 | */ |
Daniel Vetter | c5ab3bc | 2014-05-14 15:40:34 +0200 | [diff] [blame] | 487 | static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| 488 | enum pipe pipe, bool enable) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 489 | { |
| 490 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 491 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 492 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 493 | bool old; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 494 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 495 | assert_spin_locked(&dev_priv->irq_lock); |
| 496 | |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 497 | old = !intel_crtc->cpu_fifo_underrun_disabled; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 498 | intel_crtc->cpu_fifo_underrun_disabled = !enable; |
| 499 | |
Ville Syrjälä | a3ed6aa | 2014-09-03 14:09:52 +0300 | [diff] [blame] | 500 | if (HAS_GMCH_DISPLAY(dev)) |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 501 | i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 502 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 503 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
| 504 | else if (IS_GEN7(dev)) |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 505 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); |
Daniel Vetter | 38d83c96 | 2013-11-07 11:05:46 +0100 | [diff] [blame] | 506 | else if (IS_GEN8(dev)) |
| 507 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 508 | |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 509 | return old; |
Imre Deak | f88d42f | 2014-03-04 19:23:09 +0200 | [diff] [blame] | 510 | } |
| 511 | |
| 512 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| 513 | enum pipe pipe, bool enable) |
| 514 | { |
| 515 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 516 | unsigned long flags; |
| 517 | bool ret; |
| 518 | |
| 519 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 520 | ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 521 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Imre Deak | f88d42f | 2014-03-04 19:23:09 +0200 | [diff] [blame] | 522 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 523 | return ret; |
| 524 | } |
| 525 | |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 526 | static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, |
| 527 | enum pipe pipe) |
| 528 | { |
| 529 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 530 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 531 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 532 | |
| 533 | return !intel_crtc->cpu_fifo_underrun_disabled; |
| 534 | } |
| 535 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 536 | /** |
| 537 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages |
| 538 | * @dev: drm device |
| 539 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
| 540 | * @enable: true if we want to report FIFO underrun errors, false otherwise |
| 541 | * |
| 542 | * This function makes us disable or enable PCH fifo underruns for a specific |
| 543 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO |
| 544 | * underrun reporting for one transcoder may also disable all the other PCH |
| 545 | * error interruts for the other transcoders, due to the fact that there's just |
| 546 | * one interrupt mask/enable bit for all the transcoders. |
| 547 | * |
| 548 | * Returns the previous state of underrun reporting. |
| 549 | */ |
| 550 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
| 551 | enum transcoder pch_transcoder, |
| 552 | bool enable) |
| 553 | { |
| 554 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 555 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
| 556 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 557 | unsigned long flags; |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 558 | bool old; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 559 | |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 560 | /* |
| 561 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT |
| 562 | * has only one pch transcoder A that all pipes can use. To avoid racy |
| 563 | * pch transcoder -> pipe lookups from interrupt code simply store the |
| 564 | * underrun statistics in crtc A. Since we never expose this anywhere |
| 565 | * nor use it outside of the fifo underrun code here using the "wrong" |
| 566 | * crtc on LPT won't cause issues. |
| 567 | */ |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 568 | |
| 569 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 570 | |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 571 | old = !intel_crtc->pch_fifo_underrun_disabled; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 572 | intel_crtc->pch_fifo_underrun_disabled = !enable; |
| 573 | |
| 574 | if (HAS_PCH_IBX(dev)) |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 575 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 576 | else |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 577 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 578 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 579 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | 2ae2a50 | 2014-05-22 17:56:32 +0200 | [diff] [blame] | 580 | return old; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 581 | } |
| 582 | |
| 583 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 584 | static void |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 585 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 586 | u32 enable_mask, u32 status_mask) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 587 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 588 | u32 reg = PIPESTAT(pipe); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 589 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 590 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 591 | assert_spin_locked(&dev_priv->irq_lock); |
Daniel Vetter | d518ce5 | 2014-08-27 10:43:37 +0200 | [diff] [blame^] | 592 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 593 | |
Ville Syrjälä | 04feced | 2014-04-03 13:28:33 +0300 | [diff] [blame] | 594 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
| 595 | status_mask & ~PIPESTAT_INT_STATUS_MASK, |
| 596 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", |
| 597 | pipe_name(pipe), enable_mask, status_mask)) |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 598 | return; |
| 599 | |
| 600 | if ((pipestat & enable_mask) == enable_mask) |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 601 | return; |
| 602 | |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 603 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
| 604 | |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 605 | /* Enable the interrupt, clear any pending status */ |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 606 | pipestat |= enable_mask | status_mask; |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 607 | I915_WRITE(reg, pipestat); |
| 608 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 609 | } |
| 610 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 611 | static void |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 612 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 613 | u32 enable_mask, u32 status_mask) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 614 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 615 | u32 reg = PIPESTAT(pipe); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 616 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 617 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 618 | assert_spin_locked(&dev_priv->irq_lock); |
Daniel Vetter | d518ce5 | 2014-08-27 10:43:37 +0200 | [diff] [blame^] | 619 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 620 | |
Ville Syrjälä | 04feced | 2014-04-03 13:28:33 +0300 | [diff] [blame] | 621 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
| 622 | status_mask & ~PIPESTAT_INT_STATUS_MASK, |
| 623 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", |
| 624 | pipe_name(pipe), enable_mask, status_mask)) |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 625 | return; |
| 626 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 627 | if ((pipestat & enable_mask) == 0) |
| 628 | return; |
| 629 | |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 630 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
| 631 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 632 | pipestat &= ~enable_mask; |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 633 | I915_WRITE(reg, pipestat); |
| 634 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 635 | } |
| 636 | |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 637 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
| 638 | { |
| 639 | u32 enable_mask = status_mask << 16; |
| 640 | |
| 641 | /* |
Ville Syrjälä | 724a690 | 2014-04-09 13:28:48 +0300 | [diff] [blame] | 642 | * On pipe A we don't support the PSR interrupt yet, |
| 643 | * on pipe B and C the same bit MBZ. |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 644 | */ |
| 645 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) |
| 646 | return 0; |
Ville Syrjälä | 724a690 | 2014-04-09 13:28:48 +0300 | [diff] [blame] | 647 | /* |
| 648 | * On pipe B and C we don't support the PSR interrupt yet, on pipe |
| 649 | * A the same bit is for perf counters which we don't use either. |
| 650 | */ |
| 651 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) |
| 652 | return 0; |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 653 | |
| 654 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | |
| 655 | SPRITE0_FLIP_DONE_INT_EN_VLV | |
| 656 | SPRITE1_FLIP_DONE_INT_EN_VLV); |
| 657 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) |
| 658 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; |
| 659 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) |
| 660 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; |
| 661 | |
| 662 | return enable_mask; |
| 663 | } |
| 664 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 665 | void |
| 666 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 667 | u32 status_mask) |
| 668 | { |
| 669 | u32 enable_mask; |
| 670 | |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 671 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 672 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
| 673 | status_mask); |
| 674 | else |
| 675 | enable_mask = status_mask << 16; |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 676 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
| 677 | } |
| 678 | |
| 679 | void |
| 680 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 681 | u32 status_mask) |
| 682 | { |
| 683 | u32 enable_mask; |
| 684 | |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 685 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 686 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
| 687 | status_mask); |
| 688 | else |
| 689 | enable_mask = status_mask << 16; |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 690 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
| 691 | } |
| 692 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 693 | /** |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 694 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 695 | */ |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 696 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 697 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 698 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 699 | unsigned long irqflags; |
| 700 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 701 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
| 702 | return; |
| 703 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 704 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 705 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 706 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
Jani Nikula | f898780 | 2013-04-29 13:02:53 +0300 | [diff] [blame] | 707 | if (INTEL_INFO(dev)->gen >= 4) |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 708 | i915_enable_pipestat(dev_priv, PIPE_A, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 709 | PIPE_LEGACY_BLC_EVENT_STATUS); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 710 | |
| 711 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 712 | } |
| 713 | |
| 714 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 715 | * i915_pipe_enabled - check if a pipe is enabled |
| 716 | * @dev: DRM device |
| 717 | * @pipe: pipe to check |
| 718 | * |
| 719 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 720 | * Use this routine to make sure the PLL is running and the pipe is active |
| 721 | * before reading such registers if unsure. |
| 722 | */ |
| 723 | static int |
| 724 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 725 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 726 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 727 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 728 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 729 | /* Locking is horribly broken here, but whatever. */ |
| 730 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 731 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 71f8ba6 | 2013-05-03 12:15:39 -0300 | [diff] [blame] | 732 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 733 | return intel_crtc->active; |
| 734 | } else { |
| 735 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
| 736 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 737 | } |
| 738 | |
Ville Syrjälä | f75f374 | 2014-05-15 20:20:36 +0300 | [diff] [blame] | 739 | /* |
| 740 | * This timing diagram depicts the video signal in and |
| 741 | * around the vertical blanking period. |
| 742 | * |
| 743 | * Assumptions about the fictitious mode used in this example: |
| 744 | * vblank_start >= 3 |
| 745 | * vsync_start = vblank_start + 1 |
| 746 | * vsync_end = vblank_start + 2 |
| 747 | * vtotal = vblank_start + 3 |
| 748 | * |
| 749 | * start of vblank: |
| 750 | * latch double buffered registers |
| 751 | * increment frame counter (ctg+) |
| 752 | * generate start of vblank interrupt (gen4+) |
| 753 | * | |
| 754 | * | frame start: |
| 755 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) |
| 756 | * | may be shifted forward 1-3 extra lines via PIPECONF |
| 757 | * | | |
| 758 | * | | start of vsync: |
| 759 | * | | generate vsync interrupt |
| 760 | * | | | |
| 761 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx |
| 762 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ |
| 763 | * ----va---> <-----------------vb--------------------> <--------va------------- |
| 764 | * | | <----vs-----> | |
| 765 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) |
| 766 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) |
| 767 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) |
| 768 | * | | | |
| 769 | * last visible pixel first visible pixel |
| 770 | * | increment frame counter (gen3/4) |
| 771 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) |
| 772 | * |
| 773 | * x = horizontal active |
| 774 | * _ = horizontal blanking |
| 775 | * hs = horizontal sync |
| 776 | * va = vertical active |
| 777 | * vb = vertical blanking |
| 778 | * vs = vertical sync |
| 779 | * vbs = vblank_start (number) |
| 780 | * |
| 781 | * Summary: |
| 782 | * - most events happen at the start of horizontal sync |
| 783 | * - frame start happens at the start of horizontal blank, 1-4 lines |
| 784 | * (depending on PIPECONF settings) after the start of vblank |
| 785 | * - gen3/4 pixel and frame counter are synchronized with the start |
| 786 | * of horizontal active on the first line of vertical active |
| 787 | */ |
| 788 | |
Ville Syrjälä | 4cdb83e | 2013-10-11 21:52:44 +0300 | [diff] [blame] | 789 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
| 790 | { |
| 791 | /* Gen2 doesn't have a hardware frame counter */ |
| 792 | return 0; |
| 793 | } |
| 794 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 795 | /* Called from drm generic code, passed a 'crtc', which |
| 796 | * we use as a pipe index |
| 797 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 798 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 799 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 800 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 801 | unsigned long high_frame; |
| 802 | unsigned long low_frame; |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 803 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 804 | |
| 805 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 806 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 807 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 808 | return 0; |
| 809 | } |
| 810 | |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 811 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 812 | struct intel_crtc *intel_crtc = |
| 813 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 814 | const struct drm_display_mode *mode = |
| 815 | &intel_crtc->config.adjusted_mode; |
| 816 | |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 817 | htotal = mode->crtc_htotal; |
| 818 | hsync_start = mode->crtc_hsync_start; |
| 819 | vbl_start = mode->crtc_vblank_start; |
| 820 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 821 | vbl_start = DIV_ROUND_UP(vbl_start, 2); |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 822 | } else { |
Daniel Vetter | a2d213d | 2014-02-07 16:34:05 +0100 | [diff] [blame] | 823 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 824 | |
| 825 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 826 | hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 827 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 828 | if ((I915_READ(PIPECONF(cpu_transcoder)) & |
| 829 | PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE) |
| 830 | vbl_start = DIV_ROUND_UP(vbl_start, 2); |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 831 | } |
| 832 | |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 833 | /* Convert to pixel count */ |
| 834 | vbl_start *= htotal; |
| 835 | |
| 836 | /* Start of vblank event occurs at start of hsync */ |
| 837 | vbl_start -= htotal - hsync_start; |
| 838 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 839 | high_frame = PIPEFRAME(pipe); |
| 840 | low_frame = PIPEFRAMEPIXEL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 841 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 842 | /* |
| 843 | * High & low register fields aren't synchronized, so make sure |
| 844 | * we get a low value that's stable across two reads of the high |
| 845 | * register. |
| 846 | */ |
| 847 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 848 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 849 | low = I915_READ(low_frame); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 850 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 851 | } while (high1 != high2); |
| 852 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 853 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 854 | pixel = low & PIPE_PIXEL_MASK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 855 | low >>= PIPE_FRAME_LOW_SHIFT; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 856 | |
| 857 | /* |
| 858 | * The frame counter increments at beginning of active. |
| 859 | * Cook up a vblank counter by also checking the pixel |
| 860 | * counter against vblank start. |
| 861 | */ |
Ville Syrjälä | edc08d0 | 2013-11-06 13:56:27 -0200 | [diff] [blame] | 862 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 863 | } |
| 864 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 865 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 866 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 867 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 868 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 869 | |
| 870 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 871 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 872 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 873 | return 0; |
| 874 | } |
| 875 | |
| 876 | return I915_READ(reg); |
| 877 | } |
| 878 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 879 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
| 880 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 881 | |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 882 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
| 883 | { |
| 884 | struct drm_device *dev = crtc->base.dev; |
| 885 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 886 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
| 887 | enum pipe pipe = crtc->pipe; |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 888 | int position, vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 889 | |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 890 | vtotal = mode->crtc_vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 891 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 892 | vtotal /= 2; |
| 893 | |
| 894 | if (IS_GEN2(dev)) |
| 895 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
| 896 | else |
| 897 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
| 898 | |
| 899 | /* |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 900 | * See update_scanline_offset() for the details on the |
| 901 | * scanline_offset adjustment. |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 902 | */ |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 903 | return (position + crtc->scanline_offset) % vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 904 | } |
| 905 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 906 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
Ville Syrjälä | abca9e4 | 2013-10-28 20:50:48 +0200 | [diff] [blame] | 907 | unsigned int flags, int *vpos, int *hpos, |
| 908 | ktime_t *stime, ktime_t *etime) |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 909 | { |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 910 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 911 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 912 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 913 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 914 | int position; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 915 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 916 | bool in_vbl = true; |
| 917 | int ret = 0; |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 918 | unsigned long irqflags; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 919 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 920 | if (!intel_crtc->active) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 921 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 922 | "pipe %c\n", pipe_name(pipe)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 923 | return 0; |
| 924 | } |
| 925 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 926 | htotal = mode->crtc_htotal; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 927 | hsync_start = mode->crtc_hsync_start; |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 928 | vtotal = mode->crtc_vtotal; |
| 929 | vbl_start = mode->crtc_vblank_start; |
| 930 | vbl_end = mode->crtc_vblank_end; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 931 | |
Ville Syrjälä | d31faf6 | 2013-10-28 16:31:41 +0200 | [diff] [blame] | 932 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 933 | vbl_start = DIV_ROUND_UP(vbl_start, 2); |
| 934 | vbl_end /= 2; |
| 935 | vtotal /= 2; |
| 936 | } |
| 937 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 938 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
| 939 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 940 | /* |
| 941 | * Lock uncore.lock, as we will do multiple timing critical raw |
| 942 | * register reads, potentially with preemption disabled, so the |
| 943 | * following code must not block on uncore.lock. |
| 944 | */ |
| 945 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 946 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 947 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
| 948 | |
| 949 | /* Get optional system timestamp before query. */ |
| 950 | if (stime) |
| 951 | *stime = ktime_get(); |
| 952 | |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 953 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 954 | /* No obvious pixelcount register. Only query vertical |
| 955 | * scanout position from Display scan line register. |
| 956 | */ |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 957 | position = __intel_get_crtc_scanline(intel_crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 958 | } else { |
| 959 | /* Have access to pixelcount since start of frame. |
| 960 | * We can split this into vertical and horizontal |
| 961 | * scanout position. |
| 962 | */ |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 963 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 964 | |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 965 | /* convert to pixel counts */ |
| 966 | vbl_start *= htotal; |
| 967 | vbl_end *= htotal; |
| 968 | vtotal *= htotal; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 969 | |
| 970 | /* |
Ville Syrjälä | 7e78f1cb | 2014-04-29 13:35:49 +0300 | [diff] [blame] | 971 | * In interlaced modes, the pixel counter counts all pixels, |
| 972 | * so one field will have htotal more pixels. In order to avoid |
| 973 | * the reported position from jumping backwards when the pixel |
| 974 | * counter is beyond the length of the shorter field, just |
| 975 | * clamp the position the length of the shorter field. This |
| 976 | * matches how the scanline counter based position works since |
| 977 | * the scanline counter doesn't count the two half lines. |
| 978 | */ |
| 979 | if (position >= vtotal) |
| 980 | position = vtotal - 1; |
| 981 | |
| 982 | /* |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 983 | * Start of vblank interrupt is triggered at start of hsync, |
| 984 | * just prior to the first active line of vblank. However we |
| 985 | * consider lines to start at the leading edge of horizontal |
| 986 | * active. So, should we get here before we've crossed into |
| 987 | * the horizontal active of the first line in vblank, we would |
| 988 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, |
| 989 | * always add htotal-hsync_start to the current pixel position. |
| 990 | */ |
| 991 | position = (position + htotal - hsync_start) % vtotal; |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 992 | } |
| 993 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 994 | /* Get optional system timestamp after query. */ |
| 995 | if (etime) |
| 996 | *etime = ktime_get(); |
| 997 | |
| 998 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ |
| 999 | |
| 1000 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 1001 | |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 1002 | in_vbl = position >= vbl_start && position < vbl_end; |
| 1003 | |
| 1004 | /* |
| 1005 | * While in vblank, position will be negative |
| 1006 | * counting up towards 0 at vbl_end. And outside |
| 1007 | * vblank, position will be positive counting |
| 1008 | * up since vbl_end. |
| 1009 | */ |
| 1010 | if (position >= vbl_start) |
| 1011 | position -= vbl_end; |
| 1012 | else |
| 1013 | position += vtotal - vbl_end; |
| 1014 | |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 1015 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 1016 | *vpos = position; |
| 1017 | *hpos = 0; |
| 1018 | } else { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1019 | *vpos = position / htotal; |
| 1020 | *hpos = position - (*vpos * htotal); |
| 1021 | } |
| 1022 | |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1023 | /* In vblank? */ |
| 1024 | if (in_vbl) |
Daniel Vetter | 3d3cbd8 | 2014-09-10 17:36:11 +0200 | [diff] [blame] | 1025 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1026 | |
| 1027 | return ret; |
| 1028 | } |
| 1029 | |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 1030 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
| 1031 | { |
| 1032 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 1033 | unsigned long irqflags; |
| 1034 | int position; |
| 1035 | |
| 1036 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 1037 | position = __intel_get_crtc_scanline(crtc); |
| 1038 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 1039 | |
| 1040 | return position; |
| 1041 | } |
| 1042 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1043 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1044 | int *max_error, |
| 1045 | struct timeval *vblank_time, |
| 1046 | unsigned flags) |
| 1047 | { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 1048 | struct drm_crtc *crtc; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1049 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 1050 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 1051 | DRM_ERROR("Invalid crtc %d\n", pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1052 | return -EINVAL; |
| 1053 | } |
| 1054 | |
| 1055 | /* Get drm_crtc to timestamp: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 1056 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
| 1057 | if (crtc == NULL) { |
| 1058 | DRM_ERROR("Invalid crtc %d\n", pipe); |
| 1059 | return -EINVAL; |
| 1060 | } |
| 1061 | |
| 1062 | if (!crtc->enabled) { |
| 1063 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
| 1064 | return -EBUSY; |
| 1065 | } |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1066 | |
| 1067 | /* Helper routine in DRM core does all the work: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 1068 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
| 1069 | vblank_time, flags, |
Ville Syrjälä | 7da903e | 2013-10-26 17:57:31 +0300 | [diff] [blame] | 1070 | crtc, |
| 1071 | &to_intel_crtc(crtc)->config.adjusted_mode); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 1072 | } |
| 1073 | |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 1074 | static bool intel_hpd_irq_event(struct drm_device *dev, |
| 1075 | struct drm_connector *connector) |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 1076 | { |
| 1077 | enum drm_connector_status old_status; |
| 1078 | |
| 1079 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
| 1080 | old_status = connector->status; |
| 1081 | |
| 1082 | connector->status = connector->funcs->detect(connector, false); |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 1083 | if (old_status == connector->status) |
| 1084 | return false; |
| 1085 | |
| 1086 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 1087 | connector->base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 1088 | connector->name, |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 1089 | drm_get_connector_status_name(old_status), |
| 1090 | drm_get_connector_status_name(connector->status)); |
| 1091 | |
| 1092 | return true; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 1093 | } |
| 1094 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1095 | static void i915_digport_work_func(struct work_struct *work) |
| 1096 | { |
| 1097 | struct drm_i915_private *dev_priv = |
| 1098 | container_of(work, struct drm_i915_private, dig_port_work); |
| 1099 | unsigned long irqflags; |
| 1100 | u32 long_port_mask, short_port_mask; |
| 1101 | struct intel_digital_port *intel_dig_port; |
| 1102 | int i, ret; |
| 1103 | u32 old_bits = 0; |
| 1104 | |
| 1105 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1106 | long_port_mask = dev_priv->long_hpd_port_mask; |
| 1107 | dev_priv->long_hpd_port_mask = 0; |
| 1108 | short_port_mask = dev_priv->short_hpd_port_mask; |
| 1109 | dev_priv->short_hpd_port_mask = 0; |
| 1110 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1111 | |
| 1112 | for (i = 0; i < I915_MAX_PORTS; i++) { |
| 1113 | bool valid = false; |
| 1114 | bool long_hpd = false; |
| 1115 | intel_dig_port = dev_priv->hpd_irq_port[i]; |
| 1116 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) |
| 1117 | continue; |
| 1118 | |
| 1119 | if (long_port_mask & (1 << i)) { |
| 1120 | valid = true; |
| 1121 | long_hpd = true; |
| 1122 | } else if (short_port_mask & (1 << i)) |
| 1123 | valid = true; |
| 1124 | |
| 1125 | if (valid) { |
| 1126 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); |
| 1127 | if (ret == true) { |
| 1128 | /* if we get true fallback to old school hpd */ |
| 1129 | old_bits |= (1 << intel_dig_port->base.hpd_pin); |
| 1130 | } |
| 1131 | } |
| 1132 | } |
| 1133 | |
| 1134 | if (old_bits) { |
| 1135 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1136 | dev_priv->hpd_event_bits |= old_bits; |
| 1137 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1138 | schedule_work(&dev_priv->hotplug_work); |
| 1139 | } |
| 1140 | } |
| 1141 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1142 | /* |
| 1143 | * Handle hotplug events outside the interrupt handler proper. |
| 1144 | */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 1145 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
| 1146 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1147 | static void i915_hotplug_work_func(struct work_struct *work) |
| 1148 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1149 | struct drm_i915_private *dev_priv = |
| 1150 | container_of(work, struct drm_i915_private, hotplug_work); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1151 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 1152 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 1153 | struct intel_connector *intel_connector; |
| 1154 | struct intel_encoder *intel_encoder; |
| 1155 | struct drm_connector *connector; |
| 1156 | unsigned long irqflags; |
| 1157 | bool hpd_disabled = false; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 1158 | bool changed = false; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1159 | u32 hpd_event_bits; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1160 | |
Keith Packard | a65e34c | 2011-07-25 10:04:56 -0700 | [diff] [blame] | 1161 | mutex_lock(&mode_config->mutex); |
Jesse Barnes | e67189ab | 2011-02-11 14:44:51 -0800 | [diff] [blame] | 1162 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
| 1163 | |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 1164 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1165 | |
| 1166 | hpd_event_bits = dev_priv->hpd_event_bits; |
| 1167 | dev_priv->hpd_event_bits = 0; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 1168 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 1169 | intel_connector = to_intel_connector(connector); |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 1170 | if (!intel_connector->encoder) |
| 1171 | continue; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 1172 | intel_encoder = intel_connector->encoder; |
| 1173 | if (intel_encoder->hpd_pin > HPD_NONE && |
| 1174 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && |
| 1175 | connector->polled == DRM_CONNECTOR_POLL_HPD) { |
| 1176 | DRM_INFO("HPD interrupt storm detected on connector %s: " |
| 1177 | "switching from hotplug detection to polling\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 1178 | connector->name); |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 1179 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
| 1180 | connector->polled = DRM_CONNECTOR_POLL_CONNECT |
| 1181 | | DRM_CONNECTOR_POLL_DISCONNECT; |
| 1182 | hpd_disabled = true; |
| 1183 | } |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1184 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 1185 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 1186 | connector->name, intel_encoder->hpd_pin); |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1187 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 1188 | } |
| 1189 | /* if there were no outputs to poll, poll was disabled, |
| 1190 | * therefore make sure it's enabled when disabling HPD on |
| 1191 | * some connectors */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 1192 | if (hpd_disabled) { |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 1193 | drm_kms_helper_poll_enable(dev); |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 1194 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
| 1195 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 1196 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 1197 | |
| 1198 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1199 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 1200 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 1201 | intel_connector = to_intel_connector(connector); |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 1202 | if (!intel_connector->encoder) |
| 1203 | continue; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 1204 | intel_encoder = intel_connector->encoder; |
| 1205 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 1206 | if (intel_encoder->hot_plug) |
| 1207 | intel_encoder->hot_plug(intel_encoder); |
| 1208 | if (intel_hpd_irq_event(dev, connector)) |
| 1209 | changed = true; |
| 1210 | } |
| 1211 | } |
Keith Packard | 40ee338 | 2011-07-28 15:31:19 -0700 | [diff] [blame] | 1212 | mutex_unlock(&mode_config->mutex); |
| 1213 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 1214 | if (changed) |
| 1215 | drm_kms_helper_hotplug_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 1216 | } |
| 1217 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1218 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1219 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1220 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 1221 | u32 busy_up, busy_down, max_avg, min_avg; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 1222 | u8 new_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 1223 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1224 | spin_lock(&mchdev_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1225 | |
Daniel Vetter | 73edd18f | 2012-08-08 23:35:37 +0200 | [diff] [blame] | 1226 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
| 1227 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1228 | new_delay = dev_priv->ips.cur_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 1229 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1230 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 1231 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 1232 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1233 | max_avg = I915_READ(RCBMAXAVG); |
| 1234 | min_avg = I915_READ(RCBMINAVG); |
| 1235 | |
| 1236 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 1237 | if (busy_up > max_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1238 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
| 1239 | new_delay = dev_priv->ips.cur_delay - 1; |
| 1240 | if (new_delay < dev_priv->ips.max_delay) |
| 1241 | new_delay = dev_priv->ips.max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 1242 | } else if (busy_down < min_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1243 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
| 1244 | new_delay = dev_priv->ips.cur_delay + 1; |
| 1245 | if (new_delay > dev_priv->ips.min_delay) |
| 1246 | new_delay = dev_priv->ips.min_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1247 | } |
| 1248 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1249 | if (ironlake_set_drps(dev, new_delay)) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1250 | dev_priv->ips.cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1251 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1252 | spin_unlock(&mchdev_lock); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 1253 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1254 | return; |
| 1255 | } |
| 1256 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1257 | static void notify_ring(struct drm_device *dev, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1258 | struct intel_engine_cs *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1259 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1260 | if (!intel_ring_initialized(ring)) |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 1261 | return; |
| 1262 | |
Chris Wilson | 814e9b5 | 2013-09-23 17:33:19 -0300 | [diff] [blame] | 1263 | trace_i915_gem_request_complete(ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 1264 | |
Sourab Gupta | 84c33a6 | 2014-06-02 16:47:17 +0530 | [diff] [blame] | 1265 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 1266 | intel_notify_mmio_flip(ring); |
| 1267 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1268 | wake_up_all(&ring->irq_queue); |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 1269 | i915_queue_hangcheck(dev); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1270 | } |
| 1271 | |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1272 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1273 | struct intel_rps_ei *rps_ei) |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1274 | { |
| 1275 | u32 cz_ts, cz_freq_khz; |
| 1276 | u32 render_count, media_count; |
| 1277 | u32 elapsed_render, elapsed_media, elapsed_time; |
| 1278 | u32 residency = 0; |
| 1279 | |
| 1280 | cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
| 1281 | cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4); |
| 1282 | |
| 1283 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); |
| 1284 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); |
| 1285 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1286 | if (rps_ei->cz_clock == 0) { |
| 1287 | rps_ei->cz_clock = cz_ts; |
| 1288 | rps_ei->render_c0 = render_count; |
| 1289 | rps_ei->media_c0 = media_count; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1290 | |
| 1291 | return dev_priv->rps.cur_freq; |
| 1292 | } |
| 1293 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1294 | elapsed_time = cz_ts - rps_ei->cz_clock; |
| 1295 | rps_ei->cz_clock = cz_ts; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1296 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1297 | elapsed_render = render_count - rps_ei->render_c0; |
| 1298 | rps_ei->render_c0 = render_count; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1299 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1300 | elapsed_media = media_count - rps_ei->media_c0; |
| 1301 | rps_ei->media_c0 = media_count; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1302 | |
| 1303 | /* Convert all the counters into common unit of milli sec */ |
| 1304 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; |
| 1305 | elapsed_render /= cz_freq_khz; |
| 1306 | elapsed_media /= cz_freq_khz; |
| 1307 | |
| 1308 | /* |
| 1309 | * Calculate overall C0 residency percentage |
| 1310 | * only if elapsed time is non zero |
| 1311 | */ |
| 1312 | if (elapsed_time) { |
| 1313 | residency = |
| 1314 | ((max(elapsed_render, elapsed_media) * 100) |
| 1315 | / elapsed_time); |
| 1316 | } |
| 1317 | |
| 1318 | return residency; |
| 1319 | } |
| 1320 | |
| 1321 | /** |
| 1322 | * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU |
| 1323 | * busy-ness calculated from C0 counters of render & media power wells |
| 1324 | * @dev_priv: DRM device private |
| 1325 | * |
| 1326 | */ |
Damien Lespiau | 4fa7904 | 2014-08-08 19:25:57 +0100 | [diff] [blame] | 1327 | static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1328 | { |
| 1329 | u32 residency_C0_up = 0, residency_C0_down = 0; |
Damien Lespiau | 4fa7904 | 2014-08-08 19:25:57 +0100 | [diff] [blame] | 1330 | int new_delay, adj; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1331 | |
| 1332 | dev_priv->rps.ei_interrupt_count++; |
| 1333 | |
| 1334 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 1335 | |
| 1336 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1337 | if (dev_priv->rps.up_ei.cz_clock == 0) { |
| 1338 | vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei); |
| 1339 | vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1340 | return dev_priv->rps.cur_freq; |
| 1341 | } |
| 1342 | |
| 1343 | |
| 1344 | /* |
| 1345 | * To down throttle, C0 residency should be less than down threshold |
| 1346 | * for continous EI intervals. So calculate down EI counters |
| 1347 | * once in VLV_INT_COUNT_FOR_DOWN_EI |
| 1348 | */ |
| 1349 | if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) { |
| 1350 | |
| 1351 | dev_priv->rps.ei_interrupt_count = 0; |
| 1352 | |
| 1353 | residency_C0_down = vlv_c0_residency(dev_priv, |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1354 | &dev_priv->rps.down_ei); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1355 | } else { |
| 1356 | residency_C0_up = vlv_c0_residency(dev_priv, |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1357 | &dev_priv->rps.up_ei); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1358 | } |
| 1359 | |
| 1360 | new_delay = dev_priv->rps.cur_freq; |
| 1361 | |
| 1362 | adj = dev_priv->rps.last_adj; |
| 1363 | /* C0 residency is greater than UP threshold. Increase Frequency */ |
| 1364 | if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) { |
| 1365 | if (adj > 0) |
| 1366 | adj *= 2; |
| 1367 | else |
| 1368 | adj = 1; |
| 1369 | |
| 1370 | if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit) |
| 1371 | new_delay = dev_priv->rps.cur_freq + adj; |
| 1372 | |
| 1373 | /* |
| 1374 | * For better performance, jump directly |
| 1375 | * to RPe if we're below it. |
| 1376 | */ |
| 1377 | if (new_delay < dev_priv->rps.efficient_freq) |
| 1378 | new_delay = dev_priv->rps.efficient_freq; |
| 1379 | |
| 1380 | } else if (!dev_priv->rps.ei_interrupt_count && |
| 1381 | (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) { |
| 1382 | if (adj < 0) |
| 1383 | adj *= 2; |
| 1384 | else |
| 1385 | adj = -1; |
| 1386 | /* |
| 1387 | * This means, C0 residency is less than down threshold over |
| 1388 | * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq |
| 1389 | */ |
| 1390 | if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) |
| 1391 | new_delay = dev_priv->rps.cur_freq + adj; |
| 1392 | } |
| 1393 | |
| 1394 | return new_delay; |
| 1395 | } |
| 1396 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 1397 | static void gen6_pm_rps_work(struct work_struct *work) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1398 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1399 | struct drm_i915_private *dev_priv = |
| 1400 | container_of(work, struct drm_i915_private, rps.work); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 1401 | u32 pm_iir; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1402 | int new_delay, adj; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1403 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1404 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1405 | pm_iir = dev_priv->rps.pm_iir; |
| 1406 | dev_priv->rps.pm_iir = 0; |
Damien Lespiau | 6af257c | 2014-07-15 09:17:41 +0200 | [diff] [blame] | 1407 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1408 | gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1409 | else { |
| 1410 | /* Make sure not to corrupt PMIMR state used by ringbuffer */ |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1411 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1412 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1413 | spin_unlock_irq(&dev_priv->irq_lock); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 1414 | |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 1415 | /* Make sure we didn't queue anything we're not going to process. */ |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1416 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 1417 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1418 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1419 | return; |
| 1420 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1421 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 1422 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1423 | adj = dev_priv->rps.last_adj; |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 1424 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1425 | if (adj > 0) |
| 1426 | adj *= 2; |
Deepak S | 13a5660 | 2014-05-23 21:00:21 +0530 | [diff] [blame] | 1427 | else { |
| 1428 | /* CHV needs even encode values */ |
| 1429 | adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; |
| 1430 | } |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1431 | new_delay = dev_priv->rps.cur_freq + adj; |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 1432 | |
| 1433 | /* |
| 1434 | * For better performance, jump directly |
| 1435 | * to RPe if we're below it. |
| 1436 | */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1437 | if (new_delay < dev_priv->rps.efficient_freq) |
| 1438 | new_delay = dev_priv->rps.efficient_freq; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1439 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1440 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
| 1441 | new_delay = dev_priv->rps.efficient_freq; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1442 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1443 | new_delay = dev_priv->rps.min_freq_softlimit; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1444 | adj = 0; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1445 | } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
| 1446 | new_delay = vlv_calc_delay_from_C0_counters(dev_priv); |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1447 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
| 1448 | if (adj < 0) |
| 1449 | adj *= 2; |
Deepak S | 13a5660 | 2014-05-23 21:00:21 +0530 | [diff] [blame] | 1450 | else { |
| 1451 | /* CHV needs even encode values */ |
| 1452 | adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; |
| 1453 | } |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1454 | new_delay = dev_priv->rps.cur_freq + adj; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1455 | } else { /* unknown event */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1456 | new_delay = dev_priv->rps.cur_freq; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1457 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1458 | |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 1459 | /* sysfs frequency interfaces may have snuck in while servicing the |
| 1460 | * interrupt |
| 1461 | */ |
Ville Syrjälä | 1272e7b | 2013-11-07 19:57:49 +0200 | [diff] [blame] | 1462 | new_delay = clamp_t(int, new_delay, |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1463 | dev_priv->rps.min_freq_softlimit, |
| 1464 | dev_priv->rps.max_freq_softlimit); |
Deepak S | 2754436 | 2014-01-27 21:35:05 +0530 | [diff] [blame] | 1465 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1466 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1467 | |
| 1468 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 1469 | valleyview_set_rps(dev_priv->dev, new_delay); |
| 1470 | else |
| 1471 | gen6_set_rps(dev_priv->dev, new_delay); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1472 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1473 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1474 | } |
| 1475 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1476 | |
| 1477 | /** |
| 1478 | * ivybridge_parity_work - Workqueue called when a parity error interrupt |
| 1479 | * occurred. |
| 1480 | * @work: workqueue struct |
| 1481 | * |
| 1482 | * Doesn't actually do anything except notify userspace. As a consequence of |
| 1483 | * this event, userspace should try to remap the bad rows since statistically |
| 1484 | * it is likely the same row is more likely to go bad again. |
| 1485 | */ |
| 1486 | static void ivybridge_parity_work(struct work_struct *work) |
| 1487 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1488 | struct drm_i915_private *dev_priv = |
| 1489 | container_of(work, struct drm_i915_private, l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1490 | u32 error_status, row, bank, subbank; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1491 | char *parity_event[6]; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1492 | uint32_t misccpctl; |
| 1493 | unsigned long flags; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1494 | uint8_t slice = 0; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1495 | |
| 1496 | /* We must turn off DOP level clock gating to access the L3 registers. |
| 1497 | * In order to prevent a get/put style interface, acquire struct mutex |
| 1498 | * any time we access those registers. |
| 1499 | */ |
| 1500 | mutex_lock(&dev_priv->dev->struct_mutex); |
| 1501 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1502 | /* If we've screwed up tracking, just let the interrupt fire again */ |
| 1503 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) |
| 1504 | goto out; |
| 1505 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1506 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 1507 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 1508 | POSTING_READ(GEN7_MISCCPCTL); |
| 1509 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1510 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
| 1511 | u32 reg; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1512 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1513 | slice--; |
| 1514 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) |
| 1515 | break; |
| 1516 | |
| 1517 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
| 1518 | |
| 1519 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
| 1520 | |
| 1521 | error_status = I915_READ(reg); |
| 1522 | row = GEN7_PARITY_ERROR_ROW(error_status); |
| 1523 | bank = GEN7_PARITY_ERROR_BANK(error_status); |
| 1524 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); |
| 1525 | |
| 1526 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); |
| 1527 | POSTING_READ(reg); |
| 1528 | |
| 1529 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; |
| 1530 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); |
| 1531 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); |
| 1532 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); |
| 1533 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); |
| 1534 | parity_event[5] = NULL; |
| 1535 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 1536 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1537 | KOBJ_CHANGE, parity_event); |
| 1538 | |
| 1539 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
| 1540 | slice, row, bank, subbank); |
| 1541 | |
| 1542 | kfree(parity_event[4]); |
| 1543 | kfree(parity_event[3]); |
| 1544 | kfree(parity_event[2]); |
| 1545 | kfree(parity_event[1]); |
| 1546 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1547 | |
| 1548 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 1549 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1550 | out: |
| 1551 | WARN_ON(dev_priv->l3_parity.which_slice); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1552 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1553 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1554 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1555 | |
| 1556 | mutex_unlock(&dev_priv->dev->struct_mutex); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1557 | } |
| 1558 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1559 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1560 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1561 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1562 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1563 | if (!HAS_L3_DPF(dev)) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1564 | return; |
| 1565 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1566 | spin_lock(&dev_priv->irq_lock); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1567 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1568 | spin_unlock(&dev_priv->irq_lock); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1569 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1570 | iir &= GT_PARITY_ERROR(dev); |
| 1571 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
| 1572 | dev_priv->l3_parity.which_slice |= 1 << 1; |
| 1573 | |
| 1574 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) |
| 1575 | dev_priv->l3_parity.which_slice |= 1 << 0; |
| 1576 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1577 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1578 | } |
| 1579 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1580 | static void ilk_gt_irq_handler(struct drm_device *dev, |
| 1581 | struct drm_i915_private *dev_priv, |
| 1582 | u32 gt_iir) |
| 1583 | { |
| 1584 | if (gt_iir & |
| 1585 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
| 1586 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 1587 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
| 1588 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 1589 | } |
| 1590 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1591 | static void snb_gt_irq_handler(struct drm_device *dev, |
| 1592 | struct drm_i915_private *dev_priv, |
| 1593 | u32 gt_iir) |
| 1594 | { |
| 1595 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1596 | if (gt_iir & |
| 1597 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1598 | notify_ring(dev, &dev_priv->ring[RCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1599 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1600 | notify_ring(dev, &dev_priv->ring[VCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1601 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1602 | notify_ring(dev, &dev_priv->ring[BCS]); |
| 1603 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1604 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
| 1605 | GT_BSD_CS_ERROR_INTERRUPT | |
| 1606 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 1607 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
| 1608 | gt_iir); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1609 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1610 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1611 | if (gt_iir & GT_PARITY_ERROR(dev)) |
| 1612 | ivybridge_parity_error_irq_handler(dev, gt_iir); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1613 | } |
| 1614 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1615 | static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
| 1616 | { |
| 1617 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
| 1618 | return; |
| 1619 | |
| 1620 | spin_lock(&dev_priv->irq_lock); |
| 1621 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1622 | gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1623 | spin_unlock(&dev_priv->irq_lock); |
| 1624 | |
| 1625 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
| 1626 | } |
| 1627 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1628 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
| 1629 | struct drm_i915_private *dev_priv, |
| 1630 | u32 master_ctl) |
| 1631 | { |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1632 | struct intel_engine_cs *ring; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1633 | u32 rcs, bcs, vcs; |
| 1634 | uint32_t tmp = 0; |
| 1635 | irqreturn_t ret = IRQ_NONE; |
| 1636 | |
| 1637 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { |
| 1638 | tmp = I915_READ(GEN8_GT_IIR(0)); |
| 1639 | if (tmp) { |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 1640 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1641 | ret = IRQ_HANDLED; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1642 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1643 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1644 | ring = &dev_priv->ring[RCS]; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1645 | if (rcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1646 | notify_ring(dev, ring); |
| 1647 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) |
| 1648 | intel_execlists_handle_ctx_events(ring); |
| 1649 | |
| 1650 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; |
| 1651 | ring = &dev_priv->ring[BCS]; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1652 | if (bcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1653 | notify_ring(dev, ring); |
| 1654 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) |
| 1655 | intel_execlists_handle_ctx_events(ring); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1656 | } else |
| 1657 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); |
| 1658 | } |
| 1659 | |
Zhao Yakui | 85f9b5f | 2014-04-17 10:37:38 +0800 | [diff] [blame] | 1660 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1661 | tmp = I915_READ(GEN8_GT_IIR(1)); |
| 1662 | if (tmp) { |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 1663 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1664 | ret = IRQ_HANDLED; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1665 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1666 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1667 | ring = &dev_priv->ring[VCS]; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1668 | if (vcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1669 | notify_ring(dev, ring); |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1670 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1671 | intel_execlists_handle_ctx_events(ring); |
| 1672 | |
Zhao Yakui | 85f9b5f | 2014-04-17 10:37:38 +0800 | [diff] [blame] | 1673 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1674 | ring = &dev_priv->ring[VCS2]; |
Zhao Yakui | 85f9b5f | 2014-04-17 10:37:38 +0800 | [diff] [blame] | 1675 | if (vcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1676 | notify_ring(dev, ring); |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1677 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1678 | intel_execlists_handle_ctx_events(ring); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1679 | } else |
| 1680 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
| 1681 | } |
| 1682 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1683 | if (master_ctl & GEN8_GT_PM_IRQ) { |
| 1684 | tmp = I915_READ(GEN8_GT_IIR(2)); |
| 1685 | if (tmp & dev_priv->pm_rps_events) { |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1686 | I915_WRITE(GEN8_GT_IIR(2), |
| 1687 | tmp & dev_priv->pm_rps_events); |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 1688 | ret = IRQ_HANDLED; |
| 1689 | gen8_rps_irq_handler(dev_priv, tmp); |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1690 | } else |
| 1691 | DRM_ERROR("The master control interrupt lied (PM)!\n"); |
| 1692 | } |
| 1693 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1694 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
| 1695 | tmp = I915_READ(GEN8_GT_IIR(3)); |
| 1696 | if (tmp) { |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 1697 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1698 | ret = IRQ_HANDLED; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1699 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1700 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1701 | ring = &dev_priv->ring[VECS]; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1702 | if (vcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1703 | notify_ring(dev, ring); |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1704 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1705 | intel_execlists_handle_ctx_events(ring); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1706 | } else |
| 1707 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); |
| 1708 | } |
| 1709 | |
| 1710 | return ret; |
| 1711 | } |
| 1712 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1713 | #define HPD_STORM_DETECT_PERIOD 1000 |
| 1714 | #define HPD_STORM_THRESHOLD 5 |
| 1715 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1716 | static int ilk_port_to_hotplug_shift(enum port port) |
| 1717 | { |
| 1718 | switch (port) { |
| 1719 | case PORT_A: |
| 1720 | case PORT_E: |
| 1721 | default: |
| 1722 | return -1; |
| 1723 | case PORT_B: |
| 1724 | return 0; |
| 1725 | case PORT_C: |
| 1726 | return 8; |
| 1727 | case PORT_D: |
| 1728 | return 16; |
| 1729 | } |
| 1730 | } |
| 1731 | |
| 1732 | static int g4x_port_to_hotplug_shift(enum port port) |
| 1733 | { |
| 1734 | switch (port) { |
| 1735 | case PORT_A: |
| 1736 | case PORT_E: |
| 1737 | default: |
| 1738 | return -1; |
| 1739 | case PORT_B: |
| 1740 | return 17; |
| 1741 | case PORT_C: |
| 1742 | return 19; |
| 1743 | case PORT_D: |
| 1744 | return 21; |
| 1745 | } |
| 1746 | } |
| 1747 | |
| 1748 | static inline enum port get_port_from_pin(enum hpd_pin pin) |
| 1749 | { |
| 1750 | switch (pin) { |
| 1751 | case HPD_PORT_B: |
| 1752 | return PORT_B; |
| 1753 | case HPD_PORT_C: |
| 1754 | return PORT_C; |
| 1755 | case HPD_PORT_D: |
| 1756 | return PORT_D; |
| 1757 | default: |
| 1758 | return PORT_A; /* no hpd */ |
| 1759 | } |
| 1760 | } |
| 1761 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1762 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
Daniel Vetter | 22062db | 2013-06-27 17:52:11 +0200 | [diff] [blame] | 1763 | u32 hotplug_trigger, |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1764 | u32 dig_hotplug_reg, |
Daniel Vetter | 22062db | 2013-06-27 17:52:11 +0200 | [diff] [blame] | 1765 | const u32 *hpd) |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1766 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1767 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1768 | int i; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1769 | enum port port; |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1770 | bool storm_detected = false; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1771 | bool queue_dig = false, queue_hp = false; |
| 1772 | u32 dig_shift; |
| 1773 | u32 dig_port_mask = 0; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1774 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1775 | if (!hotplug_trigger) |
| 1776 | return; |
| 1777 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1778 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
| 1779 | hotplug_trigger, dig_hotplug_reg); |
Imre Deak | cc9bd49 | 2014-01-16 19:56:54 +0200 | [diff] [blame] | 1780 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1781 | spin_lock(&dev_priv->irq_lock); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1782 | for (i = 1; i < HPD_NUM_PINS; i++) { |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1783 | if (!(hpd[i] & hotplug_trigger)) |
| 1784 | continue; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 1785 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1786 | port = get_port_from_pin(i); |
| 1787 | if (port && dev_priv->hpd_irq_port[port]) { |
| 1788 | bool long_hpd; |
| 1789 | |
| 1790 | if (IS_G4X(dev)) { |
| 1791 | dig_shift = g4x_port_to_hotplug_shift(port); |
| 1792 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
| 1793 | } else { |
| 1794 | dig_shift = ilk_port_to_hotplug_shift(port); |
| 1795 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
| 1796 | } |
| 1797 | |
Ville Syrjälä | 26fbb77 | 2014-08-11 18:37:37 +0300 | [diff] [blame] | 1798 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
| 1799 | port_name(port), |
| 1800 | long_hpd ? "long" : "short"); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1801 | /* for long HPD pulses we want to have the digital queue happen, |
| 1802 | but we still want HPD storm detection to function. */ |
| 1803 | if (long_hpd) { |
| 1804 | dev_priv->long_hpd_port_mask |= (1 << port); |
| 1805 | dig_port_mask |= hpd[i]; |
| 1806 | } else { |
| 1807 | /* for short HPD just trigger the digital queue */ |
| 1808 | dev_priv->short_hpd_port_mask |= (1 << port); |
| 1809 | hotplug_trigger &= ~hpd[i]; |
| 1810 | } |
| 1811 | queue_dig = true; |
| 1812 | } |
| 1813 | } |
| 1814 | |
| 1815 | for (i = 1; i < HPD_NUM_PINS; i++) { |
Daniel Vetter | 3ff04a16 | 2014-04-24 12:03:17 +0200 | [diff] [blame] | 1816 | if (hpd[i] & hotplug_trigger && |
| 1817 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { |
| 1818 | /* |
| 1819 | * On GMCH platforms the interrupt mask bits only |
| 1820 | * prevent irq generation, not the setting of the |
| 1821 | * hotplug bits itself. So only WARN about unexpected |
| 1822 | * interrupts on saner platforms. |
| 1823 | */ |
| 1824 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), |
| 1825 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", |
| 1826 | hotplug_trigger, i, hpd[i]); |
| 1827 | |
| 1828 | continue; |
| 1829 | } |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1830 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1831 | if (!(hpd[i] & hotplug_trigger) || |
| 1832 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) |
| 1833 | continue; |
| 1834 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1835 | if (!(dig_port_mask & hpd[i])) { |
| 1836 | dev_priv->hpd_event_bits |= (1 << i); |
| 1837 | queue_hp = true; |
| 1838 | } |
| 1839 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1840 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
| 1841 | dev_priv->hpd_stats[i].hpd_last_jiffies |
| 1842 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { |
| 1843 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; |
| 1844 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1845 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1846 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
| 1847 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1848 | dev_priv->hpd_event_bits &= ~(1 << i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1849 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1850 | storm_detected = true; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1851 | } else { |
| 1852 | dev_priv->hpd_stats[i].hpd_cnt++; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1853 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
| 1854 | dev_priv->hpd_stats[i].hpd_cnt); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1855 | } |
| 1856 | } |
| 1857 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1858 | if (storm_detected) |
| 1859 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1860 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 5876fa0 | 2013-06-27 17:52:13 +0200 | [diff] [blame] | 1861 | |
Daniel Vetter | 645416f | 2013-09-02 16:22:25 +0200 | [diff] [blame] | 1862 | /* |
| 1863 | * Our hotplug handler can grab modeset locks (by calling down into the |
| 1864 | * fb helpers). Hence it must not be run on our own dev-priv->wq work |
| 1865 | * queue for otherwise the flush_work in the pageflip code will |
| 1866 | * deadlock. |
| 1867 | */ |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1868 | if (queue_dig) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1869 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1870 | if (queue_hp) |
| 1871 | schedule_work(&dev_priv->hotplug_work); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1872 | } |
| 1873 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1874 | static void gmbus_irq_handler(struct drm_device *dev) |
| 1875 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1877 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1878 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1879 | } |
| 1880 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1881 | static void dp_aux_irq_handler(struct drm_device *dev) |
| 1882 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1883 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1884 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1885 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1886 | } |
| 1887 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1888 | #if defined(CONFIG_DEBUG_FS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1889 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
| 1890 | uint32_t crc0, uint32_t crc1, |
| 1891 | uint32_t crc2, uint32_t crc3, |
| 1892 | uint32_t crc4) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1893 | { |
| 1894 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1895 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
| 1896 | struct intel_pipe_crc_entry *entry; |
Damien Lespiau | ac2300d | 2013-10-15 18:55:30 +0100 | [diff] [blame] | 1897 | int head, tail; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1898 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1899 | spin_lock(&pipe_crc->lock); |
| 1900 | |
Damien Lespiau | 0c912c7 | 2013-10-15 18:55:37 +0100 | [diff] [blame] | 1901 | if (!pipe_crc->entries) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1902 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | 0c912c7 | 2013-10-15 18:55:37 +0100 | [diff] [blame] | 1903 | DRM_ERROR("spurious interrupt\n"); |
| 1904 | return; |
| 1905 | } |
| 1906 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1907 | head = pipe_crc->head; |
| 1908 | tail = pipe_crc->tail; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1909 | |
| 1910 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1911 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1912 | DRM_ERROR("CRC buffer overflowing\n"); |
| 1913 | return; |
| 1914 | } |
| 1915 | |
| 1916 | entry = &pipe_crc->entries[head]; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1917 | |
Daniel Vetter | 8bc5e95 | 2013-10-16 22:55:49 +0200 | [diff] [blame] | 1918 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1919 | entry->crc[0] = crc0; |
| 1920 | entry->crc[1] = crc1; |
| 1921 | entry->crc[2] = crc2; |
| 1922 | entry->crc[3] = crc3; |
| 1923 | entry->crc[4] = crc4; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1924 | |
| 1925 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1926 | pipe_crc->head = head; |
| 1927 | |
| 1928 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1929 | |
| 1930 | wake_up_interruptible(&pipe_crc->wq); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1931 | } |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1932 | #else |
| 1933 | static inline void |
| 1934 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
| 1935 | uint32_t crc0, uint32_t crc1, |
| 1936 | uint32_t crc2, uint32_t crc3, |
| 1937 | uint32_t crc4) {} |
| 1938 | #endif |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1939 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1940 | |
| 1941 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1942 | { |
| 1943 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1944 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1945 | display_pipe_crc_irq_handler(dev, pipe, |
| 1946 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
| 1947 | 0, 0, 0, 0); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1948 | } |
| 1949 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1950 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1951 | { |
| 1952 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1953 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1954 | display_pipe_crc_irq_handler(dev, pipe, |
| 1955 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
| 1956 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), |
| 1957 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), |
| 1958 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), |
| 1959 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1960 | } |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1961 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1962 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1963 | { |
| 1964 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 0b5c5ed | 2013-10-16 22:55:53 +0200 | [diff] [blame] | 1965 | uint32_t res1, res2; |
| 1966 | |
| 1967 | if (INTEL_INFO(dev)->gen >= 3) |
| 1968 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
| 1969 | else |
| 1970 | res1 = 0; |
| 1971 | |
| 1972 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
| 1973 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
| 1974 | else |
| 1975 | res2 = 0; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1976 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1977 | display_pipe_crc_irq_handler(dev, pipe, |
| 1978 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
| 1979 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), |
| 1980 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), |
| 1981 | res1, res2); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1982 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1983 | |
Daisy Sun | c76bb61 | 2014-08-11 11:08:38 -0700 | [diff] [blame] | 1984 | void gen8_flip_interrupt(struct drm_device *dev) |
| 1985 | { |
| 1986 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1987 | |
| 1988 | if (!dev_priv->rps.is_bdw_sw_turbo) |
| 1989 | return; |
| 1990 | |
| 1991 | if(atomic_read(&dev_priv->rps.sw_turbo.flip_received)) { |
| 1992 | mod_timer(&dev_priv->rps.sw_turbo.flip_timer, |
| 1993 | usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies); |
| 1994 | } |
| 1995 | else { |
| 1996 | dev_priv->rps.sw_turbo.flip_timer.expires = |
| 1997 | usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies; |
| 1998 | add_timer(&dev_priv->rps.sw_turbo.flip_timer); |
| 1999 | atomic_set(&dev_priv->rps.sw_turbo.flip_received, true); |
| 2000 | } |
| 2001 | |
| 2002 | bdw_software_turbo(dev); |
| 2003 | } |
| 2004 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 2005 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
| 2006 | * IMR bits until the work is done. Other interrupts can be processed without |
| 2007 | * the work queue. */ |
| 2008 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 2009 | { |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 2010 | if (pm_iir & dev_priv->pm_rps_events) { |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 2011 | spin_lock(&dev_priv->irq_lock); |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 2012 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 2013 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 2014 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 2adbee6 | 2013-07-04 23:35:27 +0200 | [diff] [blame] | 2015 | |
| 2016 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 2017 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 2018 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 2019 | if (HAS_VEBOX(dev_priv->dev)) { |
| 2020 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
| 2021 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 2022 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 2023 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2024 | i915_handle_error(dev_priv->dev, false, |
| 2025 | "VEBOX CS error interrupt 0x%08x", |
| 2026 | pm_iir); |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 2027 | } |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 2028 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 2029 | } |
| 2030 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 2031 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
| 2032 | { |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 2033 | if (!drm_handle_vblank(dev, pipe)) |
| 2034 | return false; |
| 2035 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 2036 | return true; |
| 2037 | } |
| 2038 | |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2039 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
| 2040 | { |
| 2041 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 2042 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2043 | int pipe; |
| 2044 | |
Imre Deak | 58ead0d | 2014-02-04 21:35:47 +0200 | [diff] [blame] | 2045 | spin_lock(&dev_priv->irq_lock); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2046 | for_each_pipe(dev_priv, pipe) { |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 2047 | int reg; |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 2048 | u32 mask, iir_bit = 0; |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 2049 | |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 2050 | /* |
| 2051 | * PIPESTAT bits get signalled even when the interrupt is |
| 2052 | * disabled with the mask bits, and some of the status bits do |
| 2053 | * not generate interrupts at all (like the underrun bit). Hence |
| 2054 | * we need to be careful that we only handle what we want to |
| 2055 | * handle. |
| 2056 | */ |
| 2057 | mask = 0; |
| 2058 | if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) |
| 2059 | mask |= PIPE_FIFO_UNDERRUN_STATUS; |
| 2060 | |
| 2061 | switch (pipe) { |
| 2062 | case PIPE_A: |
| 2063 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; |
| 2064 | break; |
| 2065 | case PIPE_B: |
| 2066 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
| 2067 | break; |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 2068 | case PIPE_C: |
| 2069 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
| 2070 | break; |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 2071 | } |
| 2072 | if (iir & iir_bit) |
| 2073 | mask |= dev_priv->pipestat_irq_mask[pipe]; |
| 2074 | |
| 2075 | if (!mask) |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 2076 | continue; |
| 2077 | |
| 2078 | reg = PIPESTAT(pipe); |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 2079 | mask |= PIPESTAT_INT_ENABLE_MASK; |
| 2080 | pipe_stats[pipe] = I915_READ(reg) & mask; |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2081 | |
| 2082 | /* |
| 2083 | * Clear the PIPE*STAT regs before the IIR |
| 2084 | */ |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 2085 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
| 2086 | PIPESTAT_INT_STATUS_MASK)) |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2087 | I915_WRITE(reg, pipe_stats[pipe]); |
| 2088 | } |
Imre Deak | 58ead0d | 2014-02-04 21:35:47 +0200 | [diff] [blame] | 2089 | spin_unlock(&dev_priv->irq_lock); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2090 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2091 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 2092 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
| 2093 | intel_pipe_handle_vblank(dev, pipe)) |
| 2094 | intel_check_page_flip(dev, pipe); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2095 | |
Imre Deak | 579a9b0 | 2014-02-04 21:35:48 +0200 | [diff] [blame] | 2096 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 2097 | intel_prepare_page_flip(dev, pipe); |
| 2098 | intel_finish_page_flip(dev, pipe); |
| 2099 | } |
| 2100 | |
| 2101 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
| 2102 | i9xx_pipe_crc_irq_handler(dev, pipe); |
| 2103 | |
| 2104 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
| 2105 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) |
| 2106 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
| 2107 | } |
| 2108 | |
| 2109 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 2110 | gmbus_irq_handler(dev); |
| 2111 | } |
| 2112 | |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2113 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
| 2114 | { |
| 2115 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2116 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 2117 | |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2118 | if (hotplug_status) { |
| 2119 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 2120 | /* |
| 2121 | * Make sure hotplug status is cleared before we clear IIR, or else we |
| 2122 | * may miss hotplug events. |
| 2123 | */ |
| 2124 | POSTING_READ(PORT_HOTPLUG_STAT); |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2125 | |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2126 | if (IS_G4X(dev)) { |
| 2127 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2128 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2129 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2130 | } else { |
| 2131 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
| 2132 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2133 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2134 | } |
| 2135 | |
| 2136 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
| 2137 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) |
| 2138 | dp_aux_irq_handler(dev); |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2139 | } |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 2140 | } |
| 2141 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 2142 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2143 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 2144 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2145 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2146 | u32 iir, gt_iir, pm_iir; |
| 2147 | irqreturn_t ret = IRQ_NONE; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2148 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2149 | while (true) { |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2150 | /* Find, clear, then process each source of interrupt */ |
| 2151 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2152 | gt_iir = I915_READ(GTIIR); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2153 | if (gt_iir) |
| 2154 | I915_WRITE(GTIIR, gt_iir); |
| 2155 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2156 | pm_iir = I915_READ(GEN6_PMIIR); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2157 | if (pm_iir) |
| 2158 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 2159 | |
| 2160 | iir = I915_READ(VLV_IIR); |
| 2161 | if (iir) { |
| 2162 | /* Consume port before clearing IIR or we'll miss events */ |
| 2163 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
| 2164 | i9xx_hpd_irq_handler(dev); |
| 2165 | I915_WRITE(VLV_IIR, iir); |
| 2166 | } |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2167 | |
| 2168 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) |
| 2169 | goto out; |
| 2170 | |
| 2171 | ret = IRQ_HANDLED; |
| 2172 | |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2173 | if (gt_iir) |
| 2174 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 2175 | if (pm_iir) |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 2176 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 2177 | /* Call regardless, as some status bits might not be |
| 2178 | * signalled in iir */ |
| 2179 | valleyview_pipestat_irq_handler(dev, iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2180 | } |
| 2181 | |
| 2182 | out: |
| 2183 | return ret; |
| 2184 | } |
| 2185 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2186 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
| 2187 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 2188 | struct drm_device *dev = arg; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2189 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2190 | u32 master_ctl, iir; |
| 2191 | irqreturn_t ret = IRQ_NONE; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2192 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2193 | for (;;) { |
| 2194 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
| 2195 | iir = I915_READ(VLV_IIR); |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 2196 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2197 | if (master_ctl == 0 && iir == 0) |
| 2198 | break; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2199 | |
Oscar Mateo | 27b6c12 | 2014-06-16 16:11:00 +0100 | [diff] [blame] | 2200 | ret = IRQ_HANDLED; |
| 2201 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2202 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2203 | |
Oscar Mateo | 27b6c12 | 2014-06-16 16:11:00 +0100 | [diff] [blame] | 2204 | /* Find, clear, then process each source of interrupt */ |
| 2205 | |
| 2206 | if (iir) { |
| 2207 | /* Consume port before clearing IIR or we'll miss events */ |
| 2208 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
| 2209 | i9xx_hpd_irq_handler(dev); |
| 2210 | I915_WRITE(VLV_IIR, iir); |
| 2211 | } |
| 2212 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2213 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2214 | |
Oscar Mateo | 27b6c12 | 2014-06-16 16:11:00 +0100 | [diff] [blame] | 2215 | /* Call regardless, as some status bits might not be |
| 2216 | * signalled in iir */ |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2217 | valleyview_pipestat_irq_handler(dev, iir); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2218 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 2219 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
| 2220 | POSTING_READ(GEN8_MASTER_IRQ); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2221 | } |
| 2222 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 2223 | return ret; |
| 2224 | } |
| 2225 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2226 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2227 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2228 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2229 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 2230 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2231 | u32 dig_hotplug_reg; |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2232 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2233 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
| 2234 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
| 2235 | |
| 2236 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2237 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 2238 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
| 2239 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> |
| 2240 | SDE_AUDIO_POWER_SHIFT); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2241 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 2242 | port_name(port)); |
| 2243 | } |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2244 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 2245 | if (pch_iir & SDE_AUX_MASK) |
| 2246 | dp_aux_irq_handler(dev); |
| 2247 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2248 | if (pch_iir & SDE_GMBUS) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 2249 | gmbus_irq_handler(dev); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2250 | |
| 2251 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
| 2252 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
| 2253 | |
| 2254 | if (pch_iir & SDE_AUDIO_TRANS_MASK) |
| 2255 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); |
| 2256 | |
| 2257 | if (pch_iir & SDE_POISON) |
| 2258 | DRM_ERROR("PCH poison interrupt\n"); |
| 2259 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2260 | if (pch_iir & SDE_FDI_MASK) |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2261 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2262 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 2263 | pipe_name(pipe), |
| 2264 | I915_READ(FDI_RX_IIR(pipe))); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2265 | |
| 2266 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) |
| 2267 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); |
| 2268 | |
| 2269 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) |
| 2270 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); |
| 2271 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2272 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2273 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| 2274 | false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 2275 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2276 | |
| 2277 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) |
| 2278 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, |
| 2279 | false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 2280 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2281 | } |
| 2282 | |
| 2283 | static void ivb_err_int_handler(struct drm_device *dev) |
| 2284 | { |
| 2285 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2286 | u32 err_int = I915_READ(GEN7_ERR_INT); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2287 | enum pipe pipe; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2288 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 2289 | if (err_int & ERR_INT_POISON) |
| 2290 | DRM_ERROR("Poison interrupt\n"); |
| 2291 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2292 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2293 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { |
| 2294 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, |
| 2295 | false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 2296 | DRM_ERROR("Pipe %c FIFO underrun\n", |
| 2297 | pipe_name(pipe)); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2298 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2299 | |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2300 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
| 2301 | if (IS_IVYBRIDGE(dev)) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 2302 | ivb_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2303 | else |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 2304 | hsw_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 2305 | } |
| 2306 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2307 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2308 | I915_WRITE(GEN7_ERR_INT, err_int); |
| 2309 | } |
| 2310 | |
| 2311 | static void cpt_serr_int_handler(struct drm_device *dev) |
| 2312 | { |
| 2313 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2314 | u32 serr_int = I915_READ(SERR_INT); |
| 2315 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 2316 | if (serr_int & SERR_INT_POISON) |
| 2317 | DRM_ERROR("PCH poison interrupt\n"); |
| 2318 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2319 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
| 2320 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| 2321 | false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 2322 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2323 | |
| 2324 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) |
| 2325 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, |
| 2326 | false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 2327 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2328 | |
| 2329 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) |
| 2330 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, |
| 2331 | false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 2332 | DRM_ERROR("PCH transcoder C FIFO underrun\n"); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2333 | |
| 2334 | I915_WRITE(SERR_INT, serr_int); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2335 | } |
| 2336 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2337 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
| 2338 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2339 | struct drm_i915_private *dev_priv = dev->dev_private; |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2340 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 2341 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2342 | u32 dig_hotplug_reg; |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2343 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2344 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
| 2345 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
| 2346 | |
| 2347 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2348 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 2349 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
| 2350 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> |
| 2351 | SDE_AUDIO_POWER_SHIFT_CPT); |
| 2352 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", |
| 2353 | port_name(port)); |
| 2354 | } |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2355 | |
| 2356 | if (pch_iir & SDE_AUX_MASK_CPT) |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 2357 | dp_aux_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2358 | |
| 2359 | if (pch_iir & SDE_GMBUS_CPT) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 2360 | gmbus_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2361 | |
| 2362 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) |
| 2363 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); |
| 2364 | |
| 2365 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) |
| 2366 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); |
| 2367 | |
| 2368 | if (pch_iir & SDE_FDI_MASK_CPT) |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2369 | for_each_pipe(dev_priv, pipe) |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2370 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 2371 | pipe_name(pipe), |
| 2372 | I915_READ(FDI_RX_IIR(pipe))); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2373 | |
| 2374 | if (pch_iir & SDE_ERROR_CPT) |
| 2375 | cpt_serr_int_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2376 | } |
| 2377 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2378 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 2379 | { |
| 2380 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2381 | enum pipe pipe; |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2382 | |
| 2383 | if (de_iir & DE_AUX_CHANNEL_A) |
| 2384 | dp_aux_irq_handler(dev); |
| 2385 | |
| 2386 | if (de_iir & DE_GSE) |
| 2387 | intel_opregion_asle_intr(dev); |
| 2388 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2389 | if (de_iir & DE_POISON) |
| 2390 | DRM_ERROR("Poison interrupt\n"); |
| 2391 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2392 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 2393 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
| 2394 | intel_pipe_handle_vblank(dev, pipe)) |
| 2395 | intel_check_page_flip(dev, pipe); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2396 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2397 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
| 2398 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 2399 | DRM_ERROR("Pipe %c FIFO underrun\n", |
| 2400 | pipe_name(pipe)); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2401 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2402 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
| 2403 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2404 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2405 | /* plane/pipes map 1:1 on ilk+ */ |
| 2406 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { |
| 2407 | intel_prepare_page_flip(dev, pipe); |
| 2408 | intel_finish_page_flip_plane(dev, pipe); |
| 2409 | } |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2410 | } |
| 2411 | |
| 2412 | /* check event from PCH */ |
| 2413 | if (de_iir & DE_PCH_EVENT) { |
| 2414 | u32 pch_iir = I915_READ(SDEIIR); |
| 2415 | |
| 2416 | if (HAS_PCH_CPT(dev)) |
| 2417 | cpt_irq_handler(dev, pch_iir); |
| 2418 | else |
| 2419 | ibx_irq_handler(dev, pch_iir); |
| 2420 | |
| 2421 | /* should clear PCH hotplug event before clear CPU irq */ |
| 2422 | I915_WRITE(SDEIIR, pch_iir); |
| 2423 | } |
| 2424 | |
| 2425 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
| 2426 | ironlake_rps_change_irq_handler(dev); |
| 2427 | } |
| 2428 | |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2429 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 2430 | { |
| 2431 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 2432 | enum pipe pipe; |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2433 | |
| 2434 | if (de_iir & DE_ERR_INT_IVB) |
| 2435 | ivb_err_int_handler(dev); |
| 2436 | |
| 2437 | if (de_iir & DE_AUX_CHANNEL_A_IVB) |
| 2438 | dp_aux_irq_handler(dev); |
| 2439 | |
| 2440 | if (de_iir & DE_GSE_IVB) |
| 2441 | intel_opregion_asle_intr(dev); |
| 2442 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2443 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 2444 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
| 2445 | intel_pipe_handle_vblank(dev, pipe)) |
| 2446 | intel_check_page_flip(dev, pipe); |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2447 | |
| 2448 | /* plane/pipes map 1:1 on ilk+ */ |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 2449 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
| 2450 | intel_prepare_page_flip(dev, pipe); |
| 2451 | intel_finish_page_flip_plane(dev, pipe); |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2452 | } |
| 2453 | } |
| 2454 | |
| 2455 | /* check event from PCH */ |
| 2456 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { |
| 2457 | u32 pch_iir = I915_READ(SDEIIR); |
| 2458 | |
| 2459 | cpt_irq_handler(dev, pch_iir); |
| 2460 | |
| 2461 | /* clear PCH hotplug event before clear CPU irq */ |
| 2462 | I915_WRITE(SDEIIR, pch_iir); |
| 2463 | } |
| 2464 | } |
| 2465 | |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2466 | /* |
| 2467 | * To handle irqs with the minimum potential races with fresh interrupts, we: |
| 2468 | * 1 - Disable Master Interrupt Control. |
| 2469 | * 2 - Find the source(s) of the interrupt. |
| 2470 | * 3 - Clear the Interrupt Identity bits (IIR). |
| 2471 | * 4 - Process the interrupt(s) that had bits set in the IIRs. |
| 2472 | * 5 - Re-enable Master Interrupt Control. |
| 2473 | */ |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2474 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2475 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 2476 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2477 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2478 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2479 | irqreturn_t ret = IRQ_NONE; |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2480 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2481 | /* We get interrupts on unclaimed registers, so check for this before we |
| 2482 | * do any I915_{READ,WRITE}. */ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 2483 | intel_uncore_check_errors(dev); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2484 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2485 | /* disable master interrupt before clearing iir */ |
| 2486 | de_ier = I915_READ(DEIER); |
| 2487 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Paulo Zanoni | 23a7851 | 2013-07-12 16:35:14 -0300 | [diff] [blame] | 2488 | POSTING_READ(DEIER); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2489 | |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 2490 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
| 2491 | * interrupts will will be stored on its back queue, and then we'll be |
| 2492 | * able to process them after we restore SDEIER (as soon as we restore |
| 2493 | * it, we'll get an interrupt if SDEIIR still has something to process |
| 2494 | * due to its back queue). */ |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2495 | if (!HAS_PCH_NOP(dev)) { |
| 2496 | sde_ier = I915_READ(SDEIER); |
| 2497 | I915_WRITE(SDEIER, 0); |
| 2498 | POSTING_READ(SDEIER); |
| 2499 | } |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 2500 | |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2501 | /* Find, clear, then process each source of interrupt */ |
| 2502 | |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2503 | gt_iir = I915_READ(GTIIR); |
| 2504 | if (gt_iir) { |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2505 | I915_WRITE(GTIIR, gt_iir); |
| 2506 | ret = IRQ_HANDLED; |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 2507 | if (INTEL_INFO(dev)->gen >= 6) |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2508 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 2509 | else |
| 2510 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2511 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2512 | |
| 2513 | de_iir = I915_READ(DEIIR); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2514 | if (de_iir) { |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2515 | I915_WRITE(DEIIR, de_iir); |
| 2516 | ret = IRQ_HANDLED; |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2517 | if (INTEL_INFO(dev)->gen >= 7) |
| 2518 | ivb_display_irq_handler(dev, de_iir); |
| 2519 | else |
| 2520 | ilk_display_irq_handler(dev, de_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2521 | } |
| 2522 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2523 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2524 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
| 2525 | if (pm_iir) { |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2526 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 2527 | ret = IRQ_HANDLED; |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2528 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2529 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2530 | } |
| 2531 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2532 | I915_WRITE(DEIER, de_ier); |
| 2533 | POSTING_READ(DEIER); |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2534 | if (!HAS_PCH_NOP(dev)) { |
| 2535 | I915_WRITE(SDEIER, sde_ier); |
| 2536 | POSTING_READ(SDEIER); |
| 2537 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2538 | |
| 2539 | return ret; |
| 2540 | } |
| 2541 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2542 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
| 2543 | { |
| 2544 | struct drm_device *dev = arg; |
| 2545 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2546 | u32 master_ctl; |
| 2547 | irqreturn_t ret = IRQ_NONE; |
| 2548 | uint32_t tmp = 0; |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2549 | enum pipe pipe; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2550 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2551 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
| 2552 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
| 2553 | if (!master_ctl) |
| 2554 | return IRQ_NONE; |
| 2555 | |
| 2556 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 2557 | POSTING_READ(GEN8_MASTER_IRQ); |
| 2558 | |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2559 | /* Find, clear, then process each source of interrupt */ |
| 2560 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2561 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
| 2562 | |
| 2563 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
| 2564 | tmp = I915_READ(GEN8_DE_MISC_IIR); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2565 | if (tmp) { |
| 2566 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); |
| 2567 | ret = IRQ_HANDLED; |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2568 | if (tmp & GEN8_DE_MISC_GSE) |
| 2569 | intel_opregion_asle_intr(dev); |
| 2570 | else |
| 2571 | DRM_ERROR("Unexpected DE Misc interrupt\n"); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2572 | } |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2573 | else |
| 2574 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2575 | } |
| 2576 | |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2577 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
| 2578 | tmp = I915_READ(GEN8_DE_PORT_IIR); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2579 | if (tmp) { |
| 2580 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); |
| 2581 | ret = IRQ_HANDLED; |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2582 | if (tmp & GEN8_AUX_CHANNEL_A) |
| 2583 | dp_aux_irq_handler(dev); |
| 2584 | else |
| 2585 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2586 | } |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2587 | else |
| 2588 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2589 | } |
| 2590 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2591 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2592 | uint32_t pipe_iir; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2593 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2594 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
| 2595 | continue; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2596 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2597 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2598 | if (pipe_iir) { |
| 2599 | ret = IRQ_HANDLED; |
| 2600 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 2601 | if (pipe_iir & GEN8_PIPE_VBLANK && |
| 2602 | intel_pipe_handle_vblank(dev, pipe)) |
| 2603 | intel_check_page_flip(dev, pipe); |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2604 | |
| 2605 | if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) { |
| 2606 | intel_prepare_page_flip(dev, pipe); |
| 2607 | intel_finish_page_flip_plane(dev, pipe); |
| 2608 | } |
| 2609 | |
| 2610 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
| 2611 | hsw_pipe_crc_irq_handler(dev, pipe); |
| 2612 | |
| 2613 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
| 2614 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, |
| 2615 | false)) |
| 2616 | DRM_ERROR("Pipe %c FIFO underrun\n", |
| 2617 | pipe_name(pipe)); |
| 2618 | } |
| 2619 | |
| 2620 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
| 2621 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
| 2622 | pipe_name(pipe), |
| 2623 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); |
| 2624 | } |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2625 | } else |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2626 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
| 2627 | } |
| 2628 | |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2629 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
| 2630 | /* |
| 2631 | * FIXME(BDW): Assume for now that the new interrupt handling |
| 2632 | * scheme also closed the SDE interrupt handling race we've seen |
| 2633 | * on older pch-split platforms. But this needs testing. |
| 2634 | */ |
| 2635 | u32 pch_iir = I915_READ(SDEIIR); |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2636 | if (pch_iir) { |
| 2637 | I915_WRITE(SDEIIR, pch_iir); |
| 2638 | ret = IRQ_HANDLED; |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2639 | cpt_irq_handler(dev, pch_iir); |
| 2640 | } else |
| 2641 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); |
| 2642 | |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2643 | } |
| 2644 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2645 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
| 2646 | POSTING_READ(GEN8_MASTER_IRQ); |
| 2647 | |
| 2648 | return ret; |
| 2649 | } |
| 2650 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2651 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
| 2652 | bool reset_completed) |
| 2653 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2654 | struct intel_engine_cs *ring; |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2655 | int i; |
| 2656 | |
| 2657 | /* |
| 2658 | * Notify all waiters for GPU completion events that reset state has |
| 2659 | * been changed, and that they need to restart their wait after |
| 2660 | * checking for potential errors (and bail out to drop locks if there is |
| 2661 | * a gpu reset pending so that i915_error_work_func can acquire them). |
| 2662 | */ |
| 2663 | |
| 2664 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ |
| 2665 | for_each_ring(ring, dev_priv, i) |
| 2666 | wake_up_all(&ring->irq_queue); |
| 2667 | |
| 2668 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ |
| 2669 | wake_up_all(&dev_priv->pending_flip_queue); |
| 2670 | |
| 2671 | /* |
| 2672 | * Signal tasks blocked in i915_gem_wait_for_error that the pending |
| 2673 | * reset state is cleared. |
| 2674 | */ |
| 2675 | if (reset_completed) |
| 2676 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
| 2677 | } |
| 2678 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2679 | /** |
| 2680 | * i915_error_work_func - do process context error handling work |
| 2681 | * @work: work struct |
| 2682 | * |
| 2683 | * Fire an error uevent so userspace can see that a hang or error |
| 2684 | * was detected. |
| 2685 | */ |
| 2686 | static void i915_error_work_func(struct work_struct *work) |
| 2687 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2688 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
| 2689 | work); |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2690 | struct drm_i915_private *dev_priv = |
| 2691 | container_of(error, struct drm_i915_private, gpu_error); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2692 | struct drm_device *dev = dev_priv->dev; |
Ben Widawsky | cce723e | 2013-07-19 09:16:42 -0700 | [diff] [blame] | 2693 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
| 2694 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; |
| 2695 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2696 | int ret; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2697 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 2698 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2699 | |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 2700 | /* |
| 2701 | * Note that there's only one work item which does gpu resets, so we |
| 2702 | * need not worry about concurrent gpu resets potentially incrementing |
| 2703 | * error->reset_counter twice. We only need to take care of another |
| 2704 | * racing irq/hangcheck declaring the gpu dead for a second time. A |
| 2705 | * quick check for that is good enough: schedule_work ensures the |
| 2706 | * correct ordering between hang detection and this work item, and since |
| 2707 | * the reset in-progress bit is only ever set by code outside of this |
| 2708 | * work we don't need to worry about any other races. |
| 2709 | */ |
| 2710 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 2711 | DRM_DEBUG_DRIVER("resetting chip\n"); |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 2712 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 2713 | reset_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2714 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2715 | /* |
Imre Deak | f454c69 | 2014-04-23 01:09:04 +0300 | [diff] [blame] | 2716 | * In most cases it's guaranteed that we get here with an RPM |
| 2717 | * reference held, for example because there is a pending GPU |
| 2718 | * request that won't finish until the reset is done. This |
| 2719 | * isn't the case at least when we get here by doing a |
| 2720 | * simulated reset via debugs, so get an RPM reference. |
| 2721 | */ |
| 2722 | intel_runtime_pm_get(dev_priv); |
| 2723 | /* |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2724 | * All state reset _must_ be completed before we update the |
| 2725 | * reset counter, for otherwise waiters might miss the reset |
| 2726 | * pending state and not properly drop locks, resulting in |
| 2727 | * deadlocks with the reset work. |
| 2728 | */ |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2729 | ret = i915_reset(dev); |
| 2730 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2731 | intel_display_handle_reset(dev); |
| 2732 | |
Imre Deak | f454c69 | 2014-04-23 01:09:04 +0300 | [diff] [blame] | 2733 | intel_runtime_pm_put(dev_priv); |
| 2734 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2735 | if (ret == 0) { |
| 2736 | /* |
| 2737 | * After all the gem state is reset, increment the reset |
| 2738 | * counter and wake up everyone waiting for the reset to |
| 2739 | * complete. |
| 2740 | * |
| 2741 | * Since unlock operations are a one-sided barrier only, |
| 2742 | * we need to insert a barrier here to order any seqno |
| 2743 | * updates before |
| 2744 | * the counter increment. |
| 2745 | */ |
Peter Zijlstra | 4e857c5 | 2014-03-17 18:06:10 +0100 | [diff] [blame] | 2746 | smp_mb__before_atomic(); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2747 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
| 2748 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 2749 | kobject_uevent_env(&dev->primary->kdev->kobj, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2750 | KOBJ_CHANGE, reset_done_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2751 | } else { |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 2752 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 2753 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2754 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2755 | /* |
| 2756 | * Note: The wake_up also serves as a memory barrier so that |
| 2757 | * waiters see the update value of the reset counter atomic_t. |
| 2758 | */ |
| 2759 | i915_error_wake_up(dev_priv, true); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 2760 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2761 | } |
| 2762 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2763 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2764 | { |
| 2765 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 2766 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2767 | u32 eir = I915_READ(EIR); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2768 | int pipe, i; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2769 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2770 | if (!eir) |
| 2771 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2772 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2773 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2774 | |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 2775 | i915_get_extra_instdone(dev, instdone); |
| 2776 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2777 | if (IS_G4X(dev)) { |
| 2778 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 2779 | u32 ipeir = I915_READ(IPEIR_I965); |
| 2780 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2781 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 2782 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2783 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 2784 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2785 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2786 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2787 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2788 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2789 | } |
| 2790 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 2791 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2792 | pr_err("page table error\n"); |
| 2793 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2794 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2795 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2796 | } |
| 2797 | } |
| 2798 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2799 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2800 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 2801 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2802 | pr_err("page table error\n"); |
| 2803 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2804 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2805 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2806 | } |
| 2807 | } |
| 2808 | |
| 2809 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2810 | pr_err("memory refresh error:\n"); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2811 | for_each_pipe(dev_priv, pipe) |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2812 | pr_err("pipe %c stat: 0x%08x\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2813 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2814 | /* pipestat has already been acked */ |
| 2815 | } |
| 2816 | if (eir & I915_ERROR_INSTRUCTION) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2817 | pr_err("instruction error\n"); |
| 2818 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2819 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 2820 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2821 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2822 | u32 ipeir = I915_READ(IPEIR); |
| 2823 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2824 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
| 2825 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2826 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2827 | I915_WRITE(IPEIR, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2828 | POSTING_READ(IPEIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2829 | } else { |
| 2830 | u32 ipeir = I915_READ(IPEIR_I965); |
| 2831 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2832 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 2833 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2834 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2835 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2836 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2837 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2838 | } |
| 2839 | } |
| 2840 | |
| 2841 | I915_WRITE(EIR, eir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2842 | POSTING_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2843 | eir = I915_READ(EIR); |
| 2844 | if (eir) { |
| 2845 | /* |
| 2846 | * some errors might have become stuck, |
| 2847 | * mask them. |
| 2848 | */ |
| 2849 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 2850 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 2851 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2852 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2853 | } |
| 2854 | |
| 2855 | /** |
| 2856 | * i915_handle_error - handle an error interrupt |
| 2857 | * @dev: drm device |
| 2858 | * |
| 2859 | * Do some basic checking of regsiter state at error interrupt time and |
| 2860 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 2861 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 2862 | * so userspace knows something bad happened (should trigger collection |
| 2863 | * of a ring dump etc.). |
| 2864 | */ |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2865 | void i915_handle_error(struct drm_device *dev, bool wedged, |
| 2866 | const char *fmt, ...) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2867 | { |
| 2868 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2869 | va_list args; |
| 2870 | char error_msg[80]; |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2871 | |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2872 | va_start(args, fmt); |
| 2873 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); |
| 2874 | va_end(args); |
| 2875 | |
| 2876 | i915_capture_error_state(dev, wedged, error_msg); |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2877 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2878 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2879 | if (wedged) { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2880 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
| 2881 | &dev_priv->gpu_error.reset_counter); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2882 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2883 | /* |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2884 | * Wakeup waiting processes so that the reset work function |
| 2885 | * i915_error_work_func doesn't deadlock trying to grab various |
| 2886 | * locks. By bumping the reset counter first, the woken |
| 2887 | * processes will see a reset in progress and back off, |
| 2888 | * releasing their locks and then wait for the reset completion. |
| 2889 | * We must do this for _all_ gpu waiters that might hold locks |
| 2890 | * that the reset work needs to acquire. |
| 2891 | * |
| 2892 | * Note: The wake_up serves as the required memory barrier to |
| 2893 | * ensure that the waiters see the updated value of the reset |
| 2894 | * counter atomic_t. |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2895 | */ |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2896 | i915_error_wake_up(dev_priv, false); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2897 | } |
| 2898 | |
Daniel Vetter | 122f46b | 2013-09-04 17:36:14 +0200 | [diff] [blame] | 2899 | /* |
| 2900 | * Our reset work can grab modeset locks (since it needs to reset the |
| 2901 | * state of outstanding pagelips). Hence it must not be run on our own |
| 2902 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip |
| 2903 | * code will deadlock. |
| 2904 | */ |
| 2905 | schedule_work(&dev_priv->gpu_error.work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2906 | } |
| 2907 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 2908 | /* Called from drm generic code, passed 'crtc' which |
| 2909 | * we use as a pipe index |
| 2910 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2911 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2912 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2913 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2914 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 2915 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2916 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 2917 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2918 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2919 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2920 | if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2921 | i915_enable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2922 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2923 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2924 | i915_enable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2925 | PIPE_VBLANK_INTERRUPT_STATUS); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2926 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 2927 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2928 | return 0; |
| 2929 | } |
| 2930 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2931 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2932 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2933 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2934 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2935 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2936 | DE_PIPE_VBLANK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2937 | |
| 2938 | if (!i915_pipe_enabled(dev, pipe)) |
| 2939 | return -EINVAL; |
| 2940 | |
| 2941 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2942 | ironlake_enable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2943 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2944 | |
| 2945 | return 0; |
| 2946 | } |
| 2947 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2948 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
| 2949 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2950 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2951 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2952 | |
| 2953 | if (!i915_pipe_enabled(dev, pipe)) |
| 2954 | return -EINVAL; |
| 2955 | |
| 2956 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2957 | i915_enable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2958 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2959 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2960 | |
| 2961 | return 0; |
| 2962 | } |
| 2963 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2964 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
| 2965 | { |
| 2966 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2967 | unsigned long irqflags; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2968 | |
| 2969 | if (!i915_pipe_enabled(dev, pipe)) |
| 2970 | return -EINVAL; |
| 2971 | |
| 2972 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 7167d7c | 2013-11-07 11:05:45 +0100 | [diff] [blame] | 2973 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
| 2974 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 2975 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2976 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2977 | return 0; |
| 2978 | } |
| 2979 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 2980 | /* Called from drm generic code, passed 'crtc' which |
| 2981 | * we use as a pipe index |
| 2982 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2983 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2984 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2985 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2986 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2987 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2988 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2989 | i915_disable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2990 | PIPE_VBLANK_INTERRUPT_STATUS | |
| 2991 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2992 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2993 | } |
| 2994 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2995 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2996 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2997 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2998 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2999 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 3000 | DE_PIPE_VBLANK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 3001 | |
| 3002 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 3003 | ironlake_disable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 3004 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3005 | } |
| 3006 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3007 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
| 3008 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3009 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3010 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3011 | |
| 3012 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 3013 | i915_disable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 3014 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3015 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3016 | } |
| 3017 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3018 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
| 3019 | { |
| 3020 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3021 | unsigned long irqflags; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3022 | |
| 3023 | if (!i915_pipe_enabled(dev, pipe)) |
| 3024 | return; |
| 3025 | |
| 3026 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 7167d7c | 2013-11-07 11:05:45 +0100 | [diff] [blame] | 3027 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
| 3028 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 3029 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3030 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3031 | } |
| 3032 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 3033 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3034 | ring_last_seqno(struct intel_engine_cs *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3035 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 3036 | return list_entry(ring->request_list.prev, |
| 3037 | struct drm_i915_gem_request, list)->seqno; |
| 3038 | } |
| 3039 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3040 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3041 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 3042 | { |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3043 | return (list_empty(&ring->request_list) || |
| 3044 | i915_seqno_passed(seqno, ring_last_seqno(ring))); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 3045 | } |
| 3046 | |
Daniel Vetter | a028c4b | 2014-03-15 00:08:56 +0100 | [diff] [blame] | 3047 | static bool |
| 3048 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) |
| 3049 | { |
| 3050 | if (INTEL_INFO(dev)->gen >= 8) { |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3051 | return (ipehr >> 23) == 0x1c; |
Daniel Vetter | a028c4b | 2014-03-15 00:08:56 +0100 | [diff] [blame] | 3052 | } else { |
| 3053 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; |
| 3054 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | |
| 3055 | MI_SEMAPHORE_REGISTER); |
| 3056 | } |
| 3057 | } |
| 3058 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3059 | static struct intel_engine_cs * |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3060 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 3061 | { |
| 3062 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3063 | struct intel_engine_cs *signaller; |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 3064 | int i; |
| 3065 | |
| 3066 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3067 | for_each_ring(signaller, dev_priv, i) { |
| 3068 | if (ring == signaller) |
| 3069 | continue; |
| 3070 | |
| 3071 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) |
| 3072 | return signaller; |
| 3073 | } |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 3074 | } else { |
| 3075 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; |
| 3076 | |
| 3077 | for_each_ring(signaller, dev_priv, i) { |
| 3078 | if(ring == signaller) |
| 3079 | continue; |
| 3080 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 3081 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 3082 | return signaller; |
| 3083 | } |
| 3084 | } |
| 3085 | |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3086 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
| 3087 | ring->id, ipehr, offset); |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 3088 | |
| 3089 | return NULL; |
| 3090 | } |
| 3091 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3092 | static struct intel_engine_cs * |
| 3093 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 3094 | { |
| 3095 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3096 | u32 cmd, ipehr, head; |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3097 | u64 offset = 0; |
| 3098 | int i, backwards; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 3099 | |
| 3100 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); |
Daniel Vetter | a028c4b | 2014-03-15 00:08:56 +0100 | [diff] [blame] | 3101 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3102 | return NULL; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 3103 | |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3104 | /* |
| 3105 | * HEAD is likely pointing to the dword after the actual command, |
| 3106 | * so scan backwards until we find the MBOX. But limit it to just 3 |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3107 | * or 4 dwords depending on the semaphore wait command size. |
| 3108 | * Note that we don't care about ACTHD here since that might |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3109 | * point at at batch, and semaphores are always emitted into the |
| 3110 | * ringbuffer itself. |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 3111 | */ |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3112 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3113 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3114 | |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3115 | for (i = backwards; i; --i) { |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3116 | /* |
| 3117 | * Be paranoid and presume the hw has gone off into the wild - |
| 3118 | * our ring is smaller than what the hardware (and hence |
| 3119 | * HEAD_ADDR) allows. Also handles wrap-around. |
| 3120 | */ |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 3121 | head &= ring->buffer->size - 1; |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3122 | |
| 3123 | /* This here seems to blow up */ |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 3124 | cmd = ioread32(ring->buffer->virtual_start + head); |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 3125 | if (cmd == ipehr) |
| 3126 | break; |
| 3127 | |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3128 | head -= 4; |
| 3129 | } |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 3130 | |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 3131 | if (!i) |
| 3132 | return NULL; |
| 3133 | |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 3134 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 3135 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 3136 | offset = ioread32(ring->buffer->virtual_start + head + 12); |
| 3137 | offset <<= 32; |
| 3138 | offset = ioread32(ring->buffer->virtual_start + head + 8); |
| 3139 | } |
| 3140 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 3141 | } |
| 3142 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3143 | static int semaphore_passed(struct intel_engine_cs *ring) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3144 | { |
| 3145 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3146 | struct intel_engine_cs *signaller; |
Chris Wilson | a0d036b | 2014-07-19 12:40:42 +0100 | [diff] [blame] | 3147 | u32 seqno; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3148 | |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 3149 | ring->hangcheck.deadlock++; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3150 | |
| 3151 | signaller = semaphore_waits_for(ring, &seqno); |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 3152 | if (signaller == NULL) |
| 3153 | return -1; |
| 3154 | |
| 3155 | /* Prevent pathological recursion due to driver bugs */ |
| 3156 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3157 | return -1; |
| 3158 | |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 3159 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
| 3160 | return 1; |
| 3161 | |
Chris Wilson | a0d036b | 2014-07-19 12:40:42 +0100 | [diff] [blame] | 3162 | /* cursory check for an unkickable deadlock */ |
| 3163 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && |
| 3164 | semaphore_passed(signaller) < 0) |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 3165 | return -1; |
| 3166 | |
| 3167 | return 0; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3168 | } |
| 3169 | |
| 3170 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) |
| 3171 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3172 | struct intel_engine_cs *ring; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3173 | int i; |
| 3174 | |
| 3175 | for_each_ring(ring, dev_priv, i) |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 3176 | ring->hangcheck.deadlock = 0; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3177 | } |
| 3178 | |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 3179 | static enum intel_ring_hangcheck_action |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3180 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3181 | { |
| 3182 | struct drm_device *dev = ring->dev; |
| 3183 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3184 | u32 tmp; |
| 3185 | |
Mika Kuoppala | f260fe7 | 2014-08-05 17:16:26 +0300 | [diff] [blame] | 3186 | if (acthd != ring->hangcheck.acthd) { |
| 3187 | if (acthd > ring->hangcheck.max_acthd) { |
| 3188 | ring->hangcheck.max_acthd = acthd; |
| 3189 | return HANGCHECK_ACTIVE; |
| 3190 | } |
| 3191 | |
| 3192 | return HANGCHECK_ACTIVE_LOOP; |
| 3193 | } |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3194 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3195 | if (IS_GEN2(dev)) |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3196 | return HANGCHECK_HUNG; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3197 | |
| 3198 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 3199 | * If so we can simply poke the RB_WAIT bit |
| 3200 | * and break the hang. This should work on |
| 3201 | * all but the second generation chipsets. |
| 3202 | */ |
| 3203 | tmp = I915_READ_CTL(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3204 | if (tmp & RING_WAIT) { |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3205 | i915_handle_error(dev, false, |
| 3206 | "Kicking stuck wait on %s", |
| 3207 | ring->name); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3208 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3209 | return HANGCHECK_KICK; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3210 | } |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 3211 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3212 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { |
| 3213 | switch (semaphore_passed(ring)) { |
| 3214 | default: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3215 | return HANGCHECK_HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3216 | case 1: |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3217 | i915_handle_error(dev, false, |
| 3218 | "Kicking stuck semaphore on %s", |
| 3219 | ring->name); |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3220 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3221 | return HANGCHECK_KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3222 | case 0: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3223 | return HANGCHECK_WAIT; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3224 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3225 | } |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 3226 | |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3227 | return HANGCHECK_HUNG; |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 3228 | } |
| 3229 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 3230 | /** |
| 3231 | * This is called when the chip hasn't reported back with completed |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3232 | * batchbuffers in a long time. We keep track per ring seqno progress and |
| 3233 | * if there are no progress, hangcheck score for that ring is increased. |
| 3234 | * Further, acthd is inspected to see if the ring is stuck. On stuck case |
| 3235 | * we kick the ring. If we see no progress on three subsequent calls |
| 3236 | * we assume chip is wedged and try to fix it by resetting the chip. |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 3237 | */ |
Damien Lespiau | a658b5d | 2013-08-08 22:28:56 +0100 | [diff] [blame] | 3238 | static void i915_hangcheck_elapsed(unsigned long data) |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 3239 | { |
| 3240 | struct drm_device *dev = (struct drm_device *)data; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3241 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3242 | struct intel_engine_cs *ring; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3243 | int i; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3244 | int busy_count = 0, rings_hung = 0; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3245 | bool stuck[I915_NUM_RINGS] = { 0 }; |
| 3246 | #define BUSY 1 |
| 3247 | #define KICK 5 |
| 3248 | #define HUNG 20 |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 3249 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 3250 | if (!i915.enable_hangcheck) |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 3251 | return; |
| 3252 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3253 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 3254 | u64 acthd; |
| 3255 | u32 seqno; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3256 | bool busy = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3257 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3258 | semaphore_clear_deadlocks(dev_priv); |
| 3259 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3260 | seqno = ring->get_seqno(ring, false); |
| 3261 | acthd = intel_ring_get_active_head(ring); |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 3262 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3263 | if (ring->hangcheck.seqno == seqno) { |
| 3264 | if (ring_idle(ring, seqno)) { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 3265 | ring->hangcheck.action = HANGCHECK_IDLE; |
| 3266 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3267 | if (waitqueue_active(&ring->irq_queue)) { |
| 3268 | /* Issue a wake-up to catch stuck h/w. */ |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 3269 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
Daniel Vetter | f4adcd2 | 2013-10-28 09:24:13 +0100 | [diff] [blame] | 3270 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
| 3271 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", |
| 3272 | ring->name); |
| 3273 | else |
| 3274 | DRM_INFO("Fake missed irq on %s\n", |
| 3275 | ring->name); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 3276 | wake_up_all(&ring->irq_queue); |
| 3277 | } |
| 3278 | /* Safeguard against driver failure */ |
| 3279 | ring->hangcheck.score += BUSY; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3280 | } else |
| 3281 | busy = false; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3282 | } else { |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3283 | /* We always increment the hangcheck score |
| 3284 | * if the ring is busy and still processing |
| 3285 | * the same request, so that no single request |
| 3286 | * can run indefinitely (such as a chain of |
| 3287 | * batches). The only time we do not increment |
| 3288 | * the hangcheck score on this ring, if this |
| 3289 | * ring is in a legitimate wait for another |
| 3290 | * ring. In that case the waiting ring is a |
| 3291 | * victim and we want to be sure we catch the |
| 3292 | * right culprit. Then every time we do kick |
| 3293 | * the ring, add a small increment to the |
| 3294 | * score so that we can catch a batch that is |
| 3295 | * being repeatedly kicked and so responsible |
| 3296 | * for stalling the machine. |
| 3297 | */ |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 3298 | ring->hangcheck.action = ring_stuck(ring, |
| 3299 | acthd); |
| 3300 | |
| 3301 | switch (ring->hangcheck.action) { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 3302 | case HANGCHECK_IDLE: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3303 | case HANGCHECK_WAIT: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3304 | case HANGCHECK_ACTIVE: |
Mika Kuoppala | f260fe7 | 2014-08-05 17:16:26 +0300 | [diff] [blame] | 3305 | break; |
| 3306 | case HANGCHECK_ACTIVE_LOOP: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 3307 | ring->hangcheck.score += BUSY; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3308 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3309 | case HANGCHECK_KICK: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 3310 | ring->hangcheck.score += KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3311 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3312 | case HANGCHECK_HUNG: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 3313 | ring->hangcheck.score += HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3314 | stuck[i] = true; |
| 3315 | break; |
| 3316 | } |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3317 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3318 | } else { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 3319 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
| 3320 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3321 | /* Gradually reduce the count so that we catch DoS |
| 3322 | * attempts across multiple batches. |
| 3323 | */ |
| 3324 | if (ring->hangcheck.score > 0) |
| 3325 | ring->hangcheck.score--; |
Mika Kuoppala | f260fe7 | 2014-08-05 17:16:26 +0300 | [diff] [blame] | 3326 | |
| 3327 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 3328 | } |
| 3329 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3330 | ring->hangcheck.seqno = seqno; |
| 3331 | ring->hangcheck.acthd = acthd; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3332 | busy_count += busy; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 3333 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 3334 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 3335 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 3336 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
Daniel Vetter | b8d88d1 | 2013-08-28 10:57:59 +0200 | [diff] [blame] | 3337 | DRM_INFO("%s on %s\n", |
| 3338 | stuck[i] ? "stuck" : "no progress", |
| 3339 | ring->name); |
Chris Wilson | a43adf0 | 2013-06-10 11:20:22 +0100 | [diff] [blame] | 3340 | rings_hung++; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 3341 | } |
| 3342 | } |
| 3343 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3344 | if (rings_hung) |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3345 | return i915_handle_error(dev, true, "Ring hung"); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 3346 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3347 | if (busy_count) |
| 3348 | /* Reset timer case chip hangs without another request |
| 3349 | * being added */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 3350 | i915_queue_hangcheck(dev); |
| 3351 | } |
| 3352 | |
| 3353 | void i915_queue_hangcheck(struct drm_device *dev) |
| 3354 | { |
| 3355 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 3356 | if (!i915.enable_hangcheck) |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 3357 | return; |
| 3358 | |
| 3359 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 3360 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 3361 | } |
| 3362 | |
Paulo Zanoni | 1c69eb4 | 2014-04-01 15:37:23 -0300 | [diff] [blame] | 3363 | static void ibx_irq_reset(struct drm_device *dev) |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 3364 | { |
| 3365 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3366 | |
| 3367 | if (HAS_PCH_NOP(dev)) |
| 3368 | return; |
| 3369 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3370 | GEN5_IRQ_RESET(SDE); |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3371 | |
| 3372 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
| 3373 | I915_WRITE(SERR_INT, 0xffffffff); |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3374 | } |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3375 | |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3376 | /* |
| 3377 | * SDEIER is also touched by the interrupt handler to work around missed PCH |
| 3378 | * interrupts. Hence we can't update it after the interrupt handler is enabled - |
| 3379 | * instead we unconditionally enable all PCH interrupt sources here, but then |
| 3380 | * only unmask them as needed with SDEIMR. |
| 3381 | * |
| 3382 | * This function needs to be called before interrupts are enabled. |
| 3383 | */ |
| 3384 | static void ibx_irq_pre_postinstall(struct drm_device *dev) |
| 3385 | { |
| 3386 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3387 | |
| 3388 | if (HAS_PCH_NOP(dev)) |
| 3389 | return; |
| 3390 | |
| 3391 | WARN_ON(I915_READ(SDEIER) != 0); |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 3392 | I915_WRITE(SDEIER, 0xffffffff); |
| 3393 | POSTING_READ(SDEIER); |
| 3394 | } |
| 3395 | |
Paulo Zanoni | 7c4d664 | 2014-04-01 15:37:19 -0300 | [diff] [blame] | 3396 | static void gen5_gt_irq_reset(struct drm_device *dev) |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 3397 | { |
| 3398 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3399 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3400 | GEN5_IRQ_RESET(GT); |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 3401 | if (INTEL_INFO(dev)->gen >= 6) |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3402 | GEN5_IRQ_RESET(GEN6_PM); |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 3403 | } |
| 3404 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3405 | /* drm_dma.h hooks |
| 3406 | */ |
Paulo Zanoni | be30b29 | 2014-04-01 15:37:25 -0300 | [diff] [blame] | 3407 | static void ironlake_irq_reset(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3408 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3409 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3410 | |
Paulo Zanoni | 0c84121 | 2014-04-01 15:37:27 -0300 | [diff] [blame] | 3411 | I915_WRITE(HWSTAM, 0xffffffff); |
Daniel Vetter | bdfcdb6 | 2012-01-05 01:05:26 +0100 | [diff] [blame] | 3412 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3413 | GEN5_IRQ_RESET(DE); |
Paulo Zanoni | c6d954c | 2014-04-01 15:37:18 -0300 | [diff] [blame] | 3414 | if (IS_GEN7(dev)) |
| 3415 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3416 | |
Paulo Zanoni | 7c4d664 | 2014-04-01 15:37:19 -0300 | [diff] [blame] | 3417 | gen5_gt_irq_reset(dev); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 3418 | |
Paulo Zanoni | 1c69eb4 | 2014-04-01 15:37:23 -0300 | [diff] [blame] | 3419 | ibx_irq_reset(dev); |
Ben Widawsky | 7d99163 | 2013-05-28 19:22:25 -0700 | [diff] [blame] | 3420 | } |
| 3421 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3422 | static void valleyview_irq_preinstall(struct drm_device *dev) |
| 3423 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3424 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3425 | int pipe; |
| 3426 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3427 | /* VLV magic */ |
| 3428 | I915_WRITE(VLV_IMR, 0); |
| 3429 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); |
| 3430 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); |
| 3431 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); |
| 3432 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3433 | /* and GT */ |
| 3434 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 3435 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 3436 | |
Paulo Zanoni | 7c4d664 | 2014-04-01 15:37:19 -0300 | [diff] [blame] | 3437 | gen5_gt_irq_reset(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3438 | |
| 3439 | I915_WRITE(DPINVGTT, 0xff); |
| 3440 | |
| 3441 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3442 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3443 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3444 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3445 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3446 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 3447 | I915_WRITE(VLV_IER, 0x0); |
| 3448 | POSTING_READ(VLV_IER); |
| 3449 | } |
| 3450 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3451 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
| 3452 | { |
| 3453 | GEN8_IRQ_RESET_NDX(GT, 0); |
| 3454 | GEN8_IRQ_RESET_NDX(GT, 1); |
| 3455 | GEN8_IRQ_RESET_NDX(GT, 2); |
| 3456 | GEN8_IRQ_RESET_NDX(GT, 3); |
| 3457 | } |
| 3458 | |
Paulo Zanoni | 823f6b3 | 2014-04-01 15:37:26 -0300 | [diff] [blame] | 3459 | static void gen8_irq_reset(struct drm_device *dev) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3460 | { |
| 3461 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3462 | int pipe; |
| 3463 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3464 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3465 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3466 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3467 | gen8_gt_irq_reset(dev_priv); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3468 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3469 | for_each_pipe(dev_priv, pipe) |
Paulo Zanoni | 813bde4 | 2014-07-04 11:50:29 -0300 | [diff] [blame] | 3470 | if (intel_display_power_enabled(dev_priv, |
| 3471 | POWER_DOMAIN_PIPE(pipe))) |
| 3472 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3473 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3474 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
| 3475 | GEN5_IRQ_RESET(GEN8_DE_MISC_); |
| 3476 | GEN5_IRQ_RESET(GEN8_PCU_); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3477 | |
Paulo Zanoni | 1c69eb4 | 2014-04-01 15:37:23 -0300 | [diff] [blame] | 3478 | ibx_irq_reset(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3479 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3480 | |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3481 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) |
| 3482 | { |
| 3483 | unsigned long irqflags; |
| 3484 | |
| 3485 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3486 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], |
| 3487 | ~dev_priv->de_irq_mask[PIPE_B]); |
| 3488 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], |
| 3489 | ~dev_priv->de_irq_mask[PIPE_C]); |
| 3490 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3491 | } |
| 3492 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3493 | static void cherryview_irq_preinstall(struct drm_device *dev) |
| 3494 | { |
| 3495 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3496 | int pipe; |
| 3497 | |
| 3498 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3499 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3500 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3501 | gen8_gt_irq_reset(dev_priv); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3502 | |
| 3503 | GEN5_IRQ_RESET(GEN8_PCU_); |
| 3504 | |
| 3505 | POSTING_READ(GEN8_PCU_IIR); |
| 3506 | |
| 3507 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
| 3508 | |
| 3509 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3510 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 3511 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3512 | for_each_pipe(dev_priv, pipe) |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3513 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3514 | |
| 3515 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 3516 | I915_WRITE(VLV_IER, 0x0); |
| 3517 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3518 | POSTING_READ(VLV_IIR); |
| 3519 | } |
| 3520 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3521 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3522 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3523 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3524 | struct intel_encoder *intel_encoder; |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3525 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3526 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3527 | if (HAS_PCH_IBX(dev)) { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3528 | hotplug_irqs = SDE_HOTPLUG_MASK; |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 3529 | for_each_intel_encoder(dev, intel_encoder) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 3530 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3531 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3532 | } else { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3533 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 3534 | for_each_intel_encoder(dev, intel_encoder) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 3535 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3536 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3537 | } |
| 3538 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3539 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3540 | |
| 3541 | /* |
| 3542 | * Enable digital hotplug on the PCH, and configure the DP short pulse |
| 3543 | * duration to 2ms (which is the minimum in the Display Port spec) |
| 3544 | * |
| 3545 | * This register is the same on all known PCH chips. |
| 3546 | */ |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3547 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 3548 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); |
| 3549 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
| 3550 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
| 3551 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
| 3552 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 3553 | } |
| 3554 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3555 | static void ibx_irq_postinstall(struct drm_device *dev) |
| 3556 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3557 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3558 | u32 mask; |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3559 | |
Daniel Vetter | 692a04c | 2013-05-29 21:43:05 +0200 | [diff] [blame] | 3560 | if (HAS_PCH_NOP(dev)) |
| 3561 | return; |
| 3562 | |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3563 | if (HAS_PCH_IBX(dev)) |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3564 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3565 | else |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3566 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3567 | |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 3568 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3569 | I915_WRITE(SDEIMR, ~mask); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3570 | } |
| 3571 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3572 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
| 3573 | { |
| 3574 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3575 | u32 pm_irqs, gt_irqs; |
| 3576 | |
| 3577 | pm_irqs = gt_irqs = 0; |
| 3578 | |
| 3579 | dev_priv->gt_irq_mask = ~0; |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 3580 | if (HAS_L3_DPF(dev)) { |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3581 | /* L3 parity interrupt is always unmasked. */ |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 3582 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
| 3583 | gt_irqs |= GT_PARITY_ERROR(dev); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3584 | } |
| 3585 | |
| 3586 | gt_irqs |= GT_RENDER_USER_INTERRUPT; |
| 3587 | if (IS_GEN5(dev)) { |
| 3588 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | |
| 3589 | ILK_BSD_USER_INTERRUPT; |
| 3590 | } else { |
| 3591 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; |
| 3592 | } |
| 3593 | |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 3594 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3595 | |
| 3596 | if (INTEL_INFO(dev)->gen >= 6) { |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 3597 | pm_irqs |= dev_priv->pm_rps_events; |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3598 | |
| 3599 | if (HAS_VEBOX(dev)) |
| 3600 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
| 3601 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 3602 | dev_priv->pm_irq_mask = 0xffffffff; |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 3603 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3604 | } |
| 3605 | } |
| 3606 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3607 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3608 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 3609 | unsigned long irqflags; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3610 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 3611 | u32 display_mask, extra_mask; |
| 3612 | |
| 3613 | if (INTEL_INFO(dev)->gen >= 7) { |
| 3614 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
| 3615 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | |
| 3616 | DE_PLANEB_FLIP_DONE_IVB | |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3617 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 3618 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3619 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 3620 | } else { |
| 3621 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 3622 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3623 | DE_AUX_CHANNEL_A | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3624 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
| 3625 | DE_POISON); |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3626 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
| 3627 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 3628 | } |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3629 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3630 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3631 | |
Paulo Zanoni | 0c84121 | 2014-04-01 15:37:27 -0300 | [diff] [blame] | 3632 | I915_WRITE(HWSTAM, 0xeffe); |
| 3633 | |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3634 | ibx_irq_pre_postinstall(dev); |
| 3635 | |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 3636 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3637 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3638 | gen5_gt_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3639 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3640 | ibx_irq_postinstall(dev); |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3641 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 3642 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 6005ce4 | 2013-06-27 13:44:59 +0200 | [diff] [blame] | 3643 | /* Enable PCU event interrupts |
| 3644 | * |
| 3645 | * spinlocking not required here for correctness since interrupt |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 3646 | * setup is guaranteed to run in single-threaded context. But we |
| 3647 | * need it to make the assert_spin_locked happy. */ |
| 3648 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 3649 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 3650 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 3651 | } |
| 3652 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3653 | return 0; |
| 3654 | } |
| 3655 | |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3656 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
| 3657 | { |
| 3658 | u32 pipestat_mask; |
| 3659 | u32 iir_mask; |
| 3660 | |
| 3661 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | |
| 3662 | PIPE_FIFO_UNDERRUN_STATUS; |
| 3663 | |
| 3664 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); |
| 3665 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); |
| 3666 | POSTING_READ(PIPESTAT(PIPE_A)); |
| 3667 | |
| 3668 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
| 3669 | PIPE_CRC_DONE_INTERRUPT_STATUS; |
| 3670 | |
| 3671 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | |
| 3672 | PIPE_GMBUS_INTERRUPT_STATUS); |
| 3673 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); |
| 3674 | |
| 3675 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | |
| 3676 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3677 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
| 3678 | dev_priv->irq_mask &= ~iir_mask; |
| 3679 | |
| 3680 | I915_WRITE(VLV_IIR, iir_mask); |
| 3681 | I915_WRITE(VLV_IIR, iir_mask); |
| 3682 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 3683 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
| 3684 | POSTING_READ(VLV_IER); |
| 3685 | } |
| 3686 | |
| 3687 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) |
| 3688 | { |
| 3689 | u32 pipestat_mask; |
| 3690 | u32 iir_mask; |
| 3691 | |
| 3692 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | |
| 3693 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
Imre Deak | 6c7fba0 | 2014-03-10 19:44:48 +0200 | [diff] [blame] | 3694 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3695 | |
| 3696 | dev_priv->irq_mask |= iir_mask; |
| 3697 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
| 3698 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 3699 | I915_WRITE(VLV_IIR, iir_mask); |
| 3700 | I915_WRITE(VLV_IIR, iir_mask); |
| 3701 | POSTING_READ(VLV_IIR); |
| 3702 | |
| 3703 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
| 3704 | PIPE_CRC_DONE_INTERRUPT_STATUS; |
| 3705 | |
| 3706 | i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | |
| 3707 | PIPE_GMBUS_INTERRUPT_STATUS); |
| 3708 | i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); |
| 3709 | |
| 3710 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | |
| 3711 | PIPE_FIFO_UNDERRUN_STATUS; |
| 3712 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); |
| 3713 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); |
| 3714 | POSTING_READ(PIPESTAT(PIPE_A)); |
| 3715 | } |
| 3716 | |
| 3717 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
| 3718 | { |
| 3719 | assert_spin_locked(&dev_priv->irq_lock); |
| 3720 | |
| 3721 | if (dev_priv->display_irqs_enabled) |
| 3722 | return; |
| 3723 | |
| 3724 | dev_priv->display_irqs_enabled = true; |
| 3725 | |
| 3726 | if (dev_priv->dev->irq_enabled) |
| 3727 | valleyview_display_irqs_install(dev_priv); |
| 3728 | } |
| 3729 | |
| 3730 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) |
| 3731 | { |
| 3732 | assert_spin_locked(&dev_priv->irq_lock); |
| 3733 | |
| 3734 | if (!dev_priv->display_irqs_enabled) |
| 3735 | return; |
| 3736 | |
| 3737 | dev_priv->display_irqs_enabled = false; |
| 3738 | |
| 3739 | if (dev_priv->dev->irq_enabled) |
| 3740 | valleyview_display_irqs_uninstall(dev_priv); |
| 3741 | } |
| 3742 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3743 | static int valleyview_irq_postinstall(struct drm_device *dev) |
| 3744 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3745 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 3746 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3747 | |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3748 | dev_priv->irq_mask = ~0; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3749 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3750 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3751 | POSTING_READ(PORT_HOTPLUG_EN); |
| 3752 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3753 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3754 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3755 | I915_WRITE(VLV_IIR, 0xffffffff); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3756 | POSTING_READ(VLV_IER); |
| 3757 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 3758 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3759 | * just to make the assert_spin_locked check happy. */ |
| 3760 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3761 | if (dev_priv->display_irqs_enabled) |
| 3762 | valleyview_display_irqs_install(dev_priv); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 3763 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 3764 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3765 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3766 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3767 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3768 | gen5_gt_irq_postinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3769 | |
| 3770 | /* ack & enable invalid PTE error interrupts */ |
| 3771 | #if 0 /* FIXME: add support to irq handler for checking these bits */ |
| 3772 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
| 3773 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); |
| 3774 | #endif |
| 3775 | |
| 3776 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3777 | |
| 3778 | return 0; |
| 3779 | } |
| 3780 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3781 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
| 3782 | { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3783 | /* These are interrupts we'll toggle with the ring mask register */ |
| 3784 | uint32_t gt_interrupts[] = { |
| 3785 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 3786 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3787 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 3788 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
| 3789 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3790 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 3791 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
| 3792 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | |
| 3793 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3794 | 0, |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 3795 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
| 3796 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3797 | }; |
| 3798 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 3799 | dev_priv->pm_irq_mask = 0xffffffff; |
Deepak S | 9a2d2d8 | 2014-08-22 08:32:40 +0530 | [diff] [blame] | 3800 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
| 3801 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); |
| 3802 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events); |
| 3803 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3804 | } |
| 3805 | |
| 3806 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) |
| 3807 | { |
Damien Lespiau | d0e1f1c | 2014-04-08 01:22:44 +0100 | [diff] [blame] | 3808 | uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE | |
Daniel Vetter | 13b3a0a | 2013-11-07 15:31:52 +0100 | [diff] [blame] | 3809 | GEN8_PIPE_CDCLK_CRC_DONE | |
Daniel Vetter | 13b3a0a | 2013-11-07 15:31:52 +0100 | [diff] [blame] | 3810 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3811 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | |
| 3812 | GEN8_PIPE_FIFO_UNDERRUN; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3813 | int pipe; |
Daniel Vetter | 13b3a0a | 2013-11-07 15:31:52 +0100 | [diff] [blame] | 3814 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
| 3815 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; |
| 3816 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3817 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3818 | for_each_pipe(dev_priv, pipe) |
Paulo Zanoni | 813bde4 | 2014-07-04 11:50:29 -0300 | [diff] [blame] | 3819 | if (intel_display_power_enabled(dev_priv, |
| 3820 | POWER_DOMAIN_PIPE(pipe))) |
| 3821 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, |
| 3822 | dev_priv->de_irq_mask[pipe], |
| 3823 | de_pipe_enables); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3824 | |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 3825 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3826 | } |
| 3827 | |
| 3828 | static int gen8_irq_postinstall(struct drm_device *dev) |
| 3829 | { |
| 3830 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3831 | |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3832 | ibx_irq_pre_postinstall(dev); |
| 3833 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3834 | gen8_gt_irq_postinstall(dev_priv); |
| 3835 | gen8_de_irq_postinstall(dev_priv); |
| 3836 | |
| 3837 | ibx_irq_postinstall(dev); |
| 3838 | |
| 3839 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
| 3840 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3841 | |
| 3842 | return 0; |
| 3843 | } |
| 3844 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3845 | static int cherryview_irq_postinstall(struct drm_device *dev) |
| 3846 | { |
| 3847 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3848 | u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
| 3849 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3850 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 3851 | I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
| 3852 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV | |
| 3853 | PIPE_CRC_DONE_INTERRUPT_STATUS; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3854 | unsigned long irqflags; |
| 3855 | int pipe; |
| 3856 | |
| 3857 | /* |
| 3858 | * Leave vblank interrupts masked initially. enable/disable will |
| 3859 | * toggle them based on usage. |
| 3860 | */ |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 3861 | dev_priv->irq_mask = ~enable_mask; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3862 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3863 | for_each_pipe(dev_priv, pipe) |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3864 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3865 | |
| 3866 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 3867 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3868 | for_each_pipe(dev_priv, pipe) |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3869 | i915_enable_pipestat(dev_priv, pipe, pipestat_enable); |
| 3870 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3871 | |
| 3872 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3873 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 3874 | I915_WRITE(VLV_IER, enable_mask); |
| 3875 | |
| 3876 | gen8_gt_irq_postinstall(dev_priv); |
| 3877 | |
| 3878 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); |
| 3879 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3880 | |
| 3881 | return 0; |
| 3882 | } |
| 3883 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3884 | static void gen8_irq_uninstall(struct drm_device *dev) |
| 3885 | { |
| 3886 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3887 | |
| 3888 | if (!dev_priv) |
| 3889 | return; |
| 3890 | |
Paulo Zanoni | 823f6b3 | 2014-04-01 15:37:26 -0300 | [diff] [blame] | 3891 | gen8_irq_reset(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3892 | } |
| 3893 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3894 | static void valleyview_irq_uninstall(struct drm_device *dev) |
| 3895 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3896 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3897 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3898 | int pipe; |
| 3899 | |
| 3900 | if (!dev_priv) |
| 3901 | return; |
| 3902 | |
Imre Deak | 843d0e7 | 2014-04-14 20:24:23 +0300 | [diff] [blame] | 3903 | I915_WRITE(VLV_MASTER_IER, 0); |
| 3904 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3905 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3906 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3907 | |
| 3908 | I915_WRITE(HWSTAM, 0xffffffff); |
| 3909 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3910 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3911 | |
| 3912 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3913 | if (dev_priv->display_irqs_enabled) |
| 3914 | valleyview_display_irqs_uninstall(dev_priv); |
| 3915 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3916 | |
| 3917 | dev_priv->irq_mask = 0; |
| 3918 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3919 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3920 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 3921 | I915_WRITE(VLV_IER, 0x0); |
| 3922 | POSTING_READ(VLV_IER); |
| 3923 | } |
| 3924 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3925 | static void cherryview_irq_uninstall(struct drm_device *dev) |
| 3926 | { |
| 3927 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3928 | int pipe; |
| 3929 | |
| 3930 | if (!dev_priv) |
| 3931 | return; |
| 3932 | |
| 3933 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3934 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3935 | |
| 3936 | #define GEN8_IRQ_FINI_NDX(type, which) \ |
| 3937 | do { \ |
| 3938 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
| 3939 | I915_WRITE(GEN8_##type##_IER(which), 0); \ |
| 3940 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 3941 | POSTING_READ(GEN8_##type##_IIR(which)); \ |
| 3942 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 3943 | } while (0) |
| 3944 | |
| 3945 | #define GEN8_IRQ_FINI(type) \ |
| 3946 | do { \ |
| 3947 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ |
| 3948 | I915_WRITE(GEN8_##type##_IER, 0); \ |
| 3949 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ |
| 3950 | POSTING_READ(GEN8_##type##_IIR); \ |
| 3951 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ |
| 3952 | } while (0) |
| 3953 | |
| 3954 | GEN8_IRQ_FINI_NDX(GT, 0); |
| 3955 | GEN8_IRQ_FINI_NDX(GT, 1); |
| 3956 | GEN8_IRQ_FINI_NDX(GT, 2); |
| 3957 | GEN8_IRQ_FINI_NDX(GT, 3); |
| 3958 | |
| 3959 | GEN8_IRQ_FINI(PCU); |
| 3960 | |
| 3961 | #undef GEN8_IRQ_FINI |
| 3962 | #undef GEN8_IRQ_FINI_NDX |
| 3963 | |
| 3964 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3965 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 3966 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3967 | for_each_pipe(dev_priv, pipe) |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3968 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3969 | |
| 3970 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 3971 | I915_WRITE(VLV_IER, 0x0); |
| 3972 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3973 | POSTING_READ(VLV_IIR); |
| 3974 | } |
| 3975 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3976 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3977 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3978 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 3979 | |
| 3980 | if (!dev_priv) |
| 3981 | return; |
| 3982 | |
Paulo Zanoni | be30b29 | 2014-04-01 15:37:25 -0300 | [diff] [blame] | 3983 | ironlake_irq_reset(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3984 | } |
| 3985 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3986 | static void i8xx_irq_preinstall(struct drm_device * dev) |
| 3987 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3988 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3989 | int pipe; |
| 3990 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3991 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3992 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3993 | I915_WRITE16(IMR, 0xffff); |
| 3994 | I915_WRITE16(IER, 0x0); |
| 3995 | POSTING_READ16(IER); |
| 3996 | } |
| 3997 | |
| 3998 | static int i8xx_irq_postinstall(struct drm_device *dev) |
| 3999 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4000 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4001 | unsigned long irqflags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4002 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4003 | I915_WRITE16(EMR, |
| 4004 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 4005 | |
| 4006 | /* Unmask the interrupts that we always want on. */ |
| 4007 | dev_priv->irq_mask = |
| 4008 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4009 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4010 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4011 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 4012 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 4013 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 4014 | |
| 4015 | I915_WRITE16(IER, |
| 4016 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4017 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4018 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 4019 | I915_USER_INTERRUPT); |
| 4020 | POSTING_READ16(IER); |
| 4021 | |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4022 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4023 | * just to make the assert_spin_locked check happy. */ |
| 4024 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 4025 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 4026 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4027 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 4028 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4029 | return 0; |
| 4030 | } |
| 4031 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4032 | /* |
| 4033 | * Returns true when a page flip has completed. |
| 4034 | */ |
| 4035 | static bool i8xx_handle_vblank(struct drm_device *dev, |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 4036 | int plane, int pipe, u32 iir) |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4037 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4038 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 4039 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4040 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 4041 | if (!intel_pipe_handle_vblank(dev, pipe)) |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4042 | return false; |
| 4043 | |
| 4044 | if ((iir & flip_pending) == 0) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4045 | goto check_page_flip; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4046 | |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 4047 | intel_prepare_page_flip(dev, plane); |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4048 | |
| 4049 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 4050 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 4051 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 4052 | * the flip is completed (no longer pending). Since this doesn't raise |
| 4053 | * an interrupt per se, we watch for the change at vblank. |
| 4054 | */ |
| 4055 | if (I915_READ16(ISR) & flip_pending) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4056 | goto check_page_flip; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4057 | |
| 4058 | intel_finish_page_flip(dev, pipe); |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4059 | return true; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4060 | |
| 4061 | check_page_flip: |
| 4062 | intel_check_page_flip(dev, pipe); |
| 4063 | return false; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4064 | } |
| 4065 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 4066 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4067 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 4068 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4069 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4070 | u16 iir, new_iir; |
| 4071 | u32 pipe_stats[2]; |
| 4072 | unsigned long irqflags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4073 | int pipe; |
| 4074 | u16 flip_mask = |
| 4075 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4076 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 4077 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4078 | iir = I915_READ16(IIR); |
| 4079 | if (iir == 0) |
| 4080 | return IRQ_NONE; |
| 4081 | |
| 4082 | while (iir & ~flip_mask) { |
| 4083 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 4084 | * have been cleared after the pipestat interrupt was received. |
| 4085 | * It doesn't set the bit in iir again, but it still produces |
| 4086 | * interrupts (for non-MSI). |
| 4087 | */ |
| 4088 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 4089 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 4090 | i915_handle_error(dev, false, |
| 4091 | "Command parser error, iir 0x%08x", |
| 4092 | iir); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4093 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4094 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4095 | int reg = PIPESTAT(pipe); |
| 4096 | pipe_stats[pipe] = I915_READ(reg); |
| 4097 | |
| 4098 | /* |
| 4099 | * Clear the PIPE*STAT regs before the IIR |
| 4100 | */ |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4101 | if (pipe_stats[pipe] & 0x8000ffff) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4102 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4103 | } |
| 4104 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 4105 | |
| 4106 | I915_WRITE16(IIR, iir & ~flip_mask); |
| 4107 | new_iir = I915_READ16(IIR); /* Flush posted writes */ |
| 4108 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 4109 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4110 | |
| 4111 | if (iir & I915_USER_INTERRUPT) |
| 4112 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 4113 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4114 | for_each_pipe(dev_priv, pipe) { |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 4115 | int plane = pipe; |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 4116 | if (HAS_FBC(dev)) |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 4117 | plane = !plane; |
| 4118 | |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 4119 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 4120 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
| 4121 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4122 | |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 4123 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 4124 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4125 | |
| 4126 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
| 4127 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 4128 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 4129 | } |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4130 | |
| 4131 | iir = new_iir; |
| 4132 | } |
| 4133 | |
| 4134 | return IRQ_HANDLED; |
| 4135 | } |
| 4136 | |
| 4137 | static void i8xx_irq_uninstall(struct drm_device * dev) |
| 4138 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4139 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4140 | int pipe; |
| 4141 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4142 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4143 | /* Clear enable bits; then clear status bits */ |
| 4144 | I915_WRITE(PIPESTAT(pipe), 0); |
| 4145 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 4146 | } |
| 4147 | I915_WRITE16(IMR, 0xffff); |
| 4148 | I915_WRITE16(IER, 0x0); |
| 4149 | I915_WRITE16(IIR, I915_READ16(IIR)); |
| 4150 | } |
| 4151 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4152 | static void i915_irq_preinstall(struct drm_device * dev) |
| 4153 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4154 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4155 | int pipe; |
| 4156 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4157 | if (I915_HAS_HOTPLUG(dev)) { |
| 4158 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4159 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 4160 | } |
| 4161 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 4162 | I915_WRITE16(HWSTAM, 0xeffe); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4163 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4164 | I915_WRITE(PIPESTAT(pipe), 0); |
| 4165 | I915_WRITE(IMR, 0xffffffff); |
| 4166 | I915_WRITE(IER, 0x0); |
| 4167 | POSTING_READ(IER); |
| 4168 | } |
| 4169 | |
| 4170 | static int i915_irq_postinstall(struct drm_device *dev) |
| 4171 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4172 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4173 | u32 enable_mask; |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4174 | unsigned long irqflags; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4175 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4176 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 4177 | |
| 4178 | /* Unmask the interrupts that we always want on. */ |
| 4179 | dev_priv->irq_mask = |
| 4180 | ~(I915_ASLE_INTERRUPT | |
| 4181 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4182 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4183 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4184 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 4185 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 4186 | |
| 4187 | enable_mask = |
| 4188 | I915_ASLE_INTERRUPT | |
| 4189 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4190 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4191 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 4192 | I915_USER_INTERRUPT; |
| 4193 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4194 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4195 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4196 | POSTING_READ(PORT_HOTPLUG_EN); |
| 4197 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4198 | /* Enable in IER... */ |
| 4199 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 4200 | /* and unmask in IMR */ |
| 4201 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 4202 | } |
| 4203 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4204 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 4205 | I915_WRITE(IER, enable_mask); |
| 4206 | POSTING_READ(IER); |
| 4207 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 4208 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4209 | |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4210 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4211 | * just to make the assert_spin_locked check happy. */ |
| 4212 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 4213 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 4214 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 4215 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 4216 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4217 | return 0; |
| 4218 | } |
| 4219 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4220 | /* |
| 4221 | * Returns true when a page flip has completed. |
| 4222 | */ |
| 4223 | static bool i915_handle_vblank(struct drm_device *dev, |
| 4224 | int plane, int pipe, u32 iir) |
| 4225 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4226 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4227 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
| 4228 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 4229 | if (!intel_pipe_handle_vblank(dev, pipe)) |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4230 | return false; |
| 4231 | |
| 4232 | if ((iir & flip_pending) == 0) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4233 | goto check_page_flip; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4234 | |
| 4235 | intel_prepare_page_flip(dev, plane); |
| 4236 | |
| 4237 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 4238 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 4239 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 4240 | * the flip is completed (no longer pending). Since this doesn't raise |
| 4241 | * an interrupt per se, we watch for the change at vblank. |
| 4242 | */ |
| 4243 | if (I915_READ(ISR) & flip_pending) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4244 | goto check_page_flip; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4245 | |
| 4246 | intel_finish_page_flip(dev, pipe); |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4247 | return true; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 4248 | |
| 4249 | check_page_flip: |
| 4250 | intel_check_page_flip(dev, pipe); |
| 4251 | return false; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4252 | } |
| 4253 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 4254 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4255 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 4256 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4257 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 4258 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4259 | unsigned long irqflags; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4260 | u32 flip_mask = |
| 4261 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4262 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4263 | int pipe, ret = IRQ_NONE; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4264 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4265 | iir = I915_READ(IIR); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4266 | do { |
| 4267 | bool irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 4268 | bool blc_event = false; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4269 | |
| 4270 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 4271 | * have been cleared after the pipestat interrupt was received. |
| 4272 | * It doesn't set the bit in iir again, but it still produces |
| 4273 | * interrupts (for non-MSI). |
| 4274 | */ |
| 4275 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 4276 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 4277 | i915_handle_error(dev, false, |
| 4278 | "Command parser error, iir 0x%08x", |
| 4279 | iir); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4280 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4281 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4282 | int reg = PIPESTAT(pipe); |
| 4283 | pipe_stats[pipe] = I915_READ(reg); |
| 4284 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4285 | /* Clear the PIPE*STAT regs before the IIR */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4286 | if (pipe_stats[pipe] & 0x8000ffff) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4287 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4288 | irq_received = true; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4289 | } |
| 4290 | } |
| 4291 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 4292 | |
| 4293 | if (!irq_received) |
| 4294 | break; |
| 4295 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4296 | /* Consume port. Then clear IIR or we'll miss events */ |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 4297 | if (I915_HAS_HOTPLUG(dev) && |
| 4298 | iir & I915_DISPLAY_PORT_INTERRUPT) |
| 4299 | i9xx_hpd_irq_handler(dev); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4300 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4301 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4302 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 4303 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4304 | if (iir & I915_USER_INTERRUPT) |
| 4305 | notify_ring(dev, &dev_priv->ring[RCS]); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4306 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4307 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4308 | int plane = pipe; |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 4309 | if (HAS_FBC(dev)) |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4310 | plane = !plane; |
Ville Syrjälä | 5e2032d | 2013-02-19 15:16:38 +0200 | [diff] [blame] | 4311 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4312 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
| 4313 | i915_handle_vblank(dev, plane, pipe, iir)) |
| 4314 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4315 | |
| 4316 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 4317 | blc_event = true; |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 4318 | |
| 4319 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 4320 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4321 | |
| 4322 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
| 4323 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 4324 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4325 | } |
| 4326 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4327 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 4328 | intel_opregion_asle_intr(dev); |
| 4329 | |
| 4330 | /* With MSI, interrupts are only generated when iir |
| 4331 | * transitions from zero to nonzero. If another bit got |
| 4332 | * set while we were handling the existing iir bits, then |
| 4333 | * we would never get another interrupt. |
| 4334 | * |
| 4335 | * This is fine on non-MSI as well, as if we hit this path |
| 4336 | * we avoid exiting the interrupt handler only to generate |
| 4337 | * another one. |
| 4338 | * |
| 4339 | * Note that for MSI this could cause a stray interrupt report |
| 4340 | * if an interrupt landed in the time between writing IIR and |
| 4341 | * the posting read. This should be rare enough to never |
| 4342 | * trigger the 99% of 100,000 interrupts test for disabling |
| 4343 | * stray interrupts. |
| 4344 | */ |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4345 | ret = IRQ_HANDLED; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4346 | iir = new_iir; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 4347 | } while (iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4348 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 4349 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 4350 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4351 | return ret; |
| 4352 | } |
| 4353 | |
| 4354 | static void i915_irq_uninstall(struct drm_device * dev) |
| 4355 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4356 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4357 | int pipe; |
| 4358 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4359 | if (I915_HAS_HOTPLUG(dev)) { |
| 4360 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4361 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 4362 | } |
| 4363 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 4364 | I915_WRITE16(HWSTAM, 0xffff); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4365 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 4366 | /* Clear enable bits; then clear status bits */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4367 | I915_WRITE(PIPESTAT(pipe), 0); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 4368 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 4369 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4370 | I915_WRITE(IMR, 0xffffffff); |
| 4371 | I915_WRITE(IER, 0x0); |
| 4372 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4373 | I915_WRITE(IIR, I915_READ(IIR)); |
| 4374 | } |
| 4375 | |
| 4376 | static void i965_irq_preinstall(struct drm_device * dev) |
| 4377 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4378 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4379 | int pipe; |
| 4380 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 4381 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4382 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4383 | |
| 4384 | I915_WRITE(HWSTAM, 0xeffe); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4385 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4386 | I915_WRITE(PIPESTAT(pipe), 0); |
| 4387 | I915_WRITE(IMR, 0xffffffff); |
| 4388 | I915_WRITE(IER, 0x0); |
| 4389 | POSTING_READ(IER); |
| 4390 | } |
| 4391 | |
| 4392 | static int i965_irq_postinstall(struct drm_device *dev) |
| 4393 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4394 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4395 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4396 | u32 error_mask; |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 4397 | unsigned long irqflags; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4398 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4399 | /* Unmask the interrupts that we always want on. */ |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4400 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 4401 | I915_DISPLAY_PORT_INTERRUPT | |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4402 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4403 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4404 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4405 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 4406 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 4407 | |
| 4408 | enable_mask = ~dev_priv->irq_mask; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 4409 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4410 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4411 | enable_mask |= I915_USER_INTERRUPT; |
| 4412 | |
| 4413 | if (IS_G4X(dev)) |
| 4414 | enable_mask |= I915_BSD_USER_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4415 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 4416 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4417 | * just to make the assert_spin_locked check happy. */ |
| 4418 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 4419 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
| 4420 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 4421 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 4422 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4423 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4424 | /* |
| 4425 | * Enable some error detection, note the instruction error mask |
| 4426 | * bit is reserved, so we leave it masked. |
| 4427 | */ |
| 4428 | if (IS_G4X(dev)) { |
| 4429 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 4430 | GM45_ERROR_MEM_PRIV | |
| 4431 | GM45_ERROR_CP_PRIV | |
| 4432 | I915_ERROR_MEMORY_REFRESH); |
| 4433 | } else { |
| 4434 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 4435 | I915_ERROR_MEMORY_REFRESH); |
| 4436 | } |
| 4437 | I915_WRITE(EMR, error_mask); |
| 4438 | |
| 4439 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 4440 | I915_WRITE(IER, enable_mask); |
| 4441 | POSTING_READ(IER); |
| 4442 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4443 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4444 | POSTING_READ(PORT_HOTPLUG_EN); |
| 4445 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 4446 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4447 | |
| 4448 | return 0; |
| 4449 | } |
| 4450 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4451 | static void i915_hpd_irq_setup(struct drm_device *dev) |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4452 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4453 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 4454 | struct intel_encoder *intel_encoder; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4455 | u32 hotplug_en; |
| 4456 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 4457 | assert_spin_locked(&dev_priv->irq_lock); |
| 4458 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4459 | if (I915_HAS_HOTPLUG(dev)) { |
| 4460 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 4461 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; |
| 4462 | /* Note HDMI and DP share hotplug bits */ |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 4463 | /* enable bits are the same for all generations */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 4464 | for_each_intel_encoder(dev, intel_encoder) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 4465 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
| 4466 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4467 | /* Programming the CRT detection parameters tends |
| 4468 | to generate a spurious hotplug event about three |
| 4469 | seconds later. So just do it once. |
| 4470 | */ |
| 4471 | if (IS_G4X(dev)) |
| 4472 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
Daniel Vetter | 85fc95b | 2013-03-27 15:47:11 +0100 | [diff] [blame] | 4473 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4474 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4475 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4476 | /* Ignore TV since it's buggy */ |
| 4477 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 4478 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4479 | } |
| 4480 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 4481 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4482 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 4483 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4484 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4485 | u32 iir, new_iir; |
| 4486 | u32 pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4487 | unsigned long irqflags; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4488 | int ret = IRQ_NONE, pipe; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 4489 | u32 flip_mask = |
| 4490 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4491 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4492 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4493 | iir = I915_READ(IIR); |
| 4494 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4495 | for (;;) { |
Ville Syrjälä | 501e01d | 2014-01-17 11:35:15 +0200 | [diff] [blame] | 4496 | bool irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 4497 | bool blc_event = false; |
| 4498 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4499 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 4500 | * have been cleared after the pipestat interrupt was received. |
| 4501 | * It doesn't set the bit in iir again, but it still produces |
| 4502 | * interrupts (for non-MSI). |
| 4503 | */ |
| 4504 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 4505 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 4506 | i915_handle_error(dev, false, |
| 4507 | "Command parser error, iir 0x%08x", |
| 4508 | iir); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4509 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4510 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4511 | int reg = PIPESTAT(pipe); |
| 4512 | pipe_stats[pipe] = I915_READ(reg); |
| 4513 | |
| 4514 | /* |
| 4515 | * Clear the PIPE*STAT regs before the IIR |
| 4516 | */ |
| 4517 | if (pipe_stats[pipe] & 0x8000ffff) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4518 | I915_WRITE(reg, pipe_stats[pipe]); |
Ville Syrjälä | 501e01d | 2014-01-17 11:35:15 +0200 | [diff] [blame] | 4519 | irq_received = true; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4520 | } |
| 4521 | } |
| 4522 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 4523 | |
| 4524 | if (!irq_received) |
| 4525 | break; |
| 4526 | |
| 4527 | ret = IRQ_HANDLED; |
| 4528 | |
| 4529 | /* Consume port. Then clear IIR or we'll miss events */ |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 4530 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
| 4531 | i9xx_hpd_irq_handler(dev); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4532 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 4533 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4534 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 4535 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4536 | if (iir & I915_USER_INTERRUPT) |
| 4537 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 4538 | if (iir & I915_BSD_USER_INTERRUPT) |
| 4539 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 4540 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4541 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 4542 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4543 | i915_handle_vblank(dev, pipe, pipe, iir)) |
| 4544 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4545 | |
| 4546 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 4547 | blc_event = true; |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 4548 | |
| 4549 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 4550 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4551 | |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4552 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
| 4553 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) |
Ville Syrjälä | fc2c807 | 2014-01-17 11:44:32 +0200 | [diff] [blame] | 4554 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4555 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4556 | |
| 4557 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 4558 | intel_opregion_asle_intr(dev); |
| 4559 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 4560 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 4561 | gmbus_irq_handler(dev); |
| 4562 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4563 | /* With MSI, interrupts are only generated when iir |
| 4564 | * transitions from zero to nonzero. If another bit got |
| 4565 | * set while we were handling the existing iir bits, then |
| 4566 | * we would never get another interrupt. |
| 4567 | * |
| 4568 | * This is fine on non-MSI as well, as if we hit this path |
| 4569 | * we avoid exiting the interrupt handler only to generate |
| 4570 | * another one. |
| 4571 | * |
| 4572 | * Note that for MSI this could cause a stray interrupt report |
| 4573 | * if an interrupt landed in the time between writing IIR and |
| 4574 | * the posting read. This should be rare enough to never |
| 4575 | * trigger the 99% of 100,000 interrupts test for disabling |
| 4576 | * stray interrupts. |
| 4577 | */ |
| 4578 | iir = new_iir; |
| 4579 | } |
| 4580 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 4581 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 4582 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4583 | return ret; |
| 4584 | } |
| 4585 | |
| 4586 | static void i965_irq_uninstall(struct drm_device * dev) |
| 4587 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4588 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4589 | int pipe; |
| 4590 | |
| 4591 | if (!dev_priv) |
| 4592 | return; |
| 4593 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 4594 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4595 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4596 | |
| 4597 | I915_WRITE(HWSTAM, 0xffffffff); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4598 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4599 | I915_WRITE(PIPESTAT(pipe), 0); |
| 4600 | I915_WRITE(IMR, 0xffffffff); |
| 4601 | I915_WRITE(IER, 0x0); |
| 4602 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4603 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4604 | I915_WRITE(PIPESTAT(pipe), |
| 4605 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); |
| 4606 | I915_WRITE(IIR, I915_READ(IIR)); |
| 4607 | } |
| 4608 | |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4609 | static void intel_hpd_irq_reenable(struct work_struct *work) |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4610 | { |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4611 | struct drm_i915_private *dev_priv = |
| 4612 | container_of(work, typeof(*dev_priv), |
| 4613 | hotplug_reenable_work.work); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4614 | struct drm_device *dev = dev_priv->dev; |
| 4615 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 4616 | unsigned long irqflags; |
| 4617 | int i; |
| 4618 | |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4619 | intel_runtime_pm_get(dev_priv); |
| 4620 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4621 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 4622 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
| 4623 | struct drm_connector *connector; |
| 4624 | |
| 4625 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) |
| 4626 | continue; |
| 4627 | |
| 4628 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 4629 | |
| 4630 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 4631 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4632 | |
| 4633 | if (intel_connector->encoder->hpd_pin == i) { |
| 4634 | if (connector->polled != intel_connector->polled) |
| 4635 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 4636 | connector->name); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4637 | connector->polled = intel_connector->polled; |
| 4638 | if (!connector->polled) |
| 4639 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 4640 | } |
| 4641 | } |
| 4642 | } |
| 4643 | if (dev_priv->display.hpd_irq_setup) |
| 4644 | dev_priv->display.hpd_irq_setup(dev); |
| 4645 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4646 | |
| 4647 | intel_runtime_pm_put(dev_priv); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4648 | } |
| 4649 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4650 | void intel_irq_init(struct drm_device *dev) |
| 4651 | { |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 4652 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4653 | |
| 4654 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4655 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 4656 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 4657 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 4658 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 4659 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 4660 | /* Let's track the enabled rps events */ |
Ville Syrjälä | 6c65a58 | 2014-08-29 14:14:07 +0300 | [diff] [blame] | 4661 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) |
| 4662 | /* WaGsvRC0ResidencyMethod:vlv */ |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 4663 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
| 4664 | else |
| 4665 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 4666 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 4667 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 4668 | i915_hangcheck_elapsed, |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 4669 | (unsigned long) dev); |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4670 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
| 4671 | intel_hpd_irq_reenable); |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 4672 | |
Tomas Janousek | 97a19a2 | 2012-12-08 13:48:13 +0100 | [diff] [blame] | 4673 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 4674 | |
Jesse Barnes | 95f25be | 2014-06-20 09:29:22 -0700 | [diff] [blame] | 4675 | /* Haven't installed the IRQ handler yet */ |
| 4676 | dev_priv->pm._irqs_disabled = true; |
| 4677 | |
Ville Syrjälä | 4cdb83e | 2013-10-11 21:52:44 +0300 | [diff] [blame] | 4678 | if (IS_GEN2(dev)) { |
| 4679 | dev->max_vblank_count = 0; |
| 4680 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; |
| 4681 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4682 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
| 4683 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 4684 | } else { |
| 4685 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
| 4686 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4687 | } |
| 4688 | |
Ville Syrjälä | 21da270 | 2014-08-06 14:49:55 +0300 | [diff] [blame] | 4689 | /* |
| 4690 | * Opt out of the vblank disable timer on everything except gen2. |
| 4691 | * Gen2 doesn't have a hardware frame counter and so depends on |
| 4692 | * vblank interrupts to produce sane vblank seuquence numbers. |
| 4693 | */ |
| 4694 | if (!IS_GEN2(dev)) |
| 4695 | dev->vblank_disable_immediate = true; |
| 4696 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 4697 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Keith Packard | c3613de | 2011-08-12 17:05:54 -0700 | [diff] [blame] | 4698 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 4699 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
| 4700 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4701 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4702 | if (IS_CHERRYVIEW(dev)) { |
| 4703 | dev->driver->irq_handler = cherryview_irq_handler; |
| 4704 | dev->driver->irq_preinstall = cherryview_irq_preinstall; |
| 4705 | dev->driver->irq_postinstall = cherryview_irq_postinstall; |
| 4706 | dev->driver->irq_uninstall = cherryview_irq_uninstall; |
| 4707 | dev->driver->enable_vblank = valleyview_enable_vblank; |
| 4708 | dev->driver->disable_vblank = valleyview_disable_vblank; |
| 4709 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
| 4710 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 4711 | dev->driver->irq_handler = valleyview_irq_handler; |
| 4712 | dev->driver->irq_preinstall = valleyview_irq_preinstall; |
| 4713 | dev->driver->irq_postinstall = valleyview_irq_postinstall; |
| 4714 | dev->driver->irq_uninstall = valleyview_irq_uninstall; |
| 4715 | dev->driver->enable_vblank = valleyview_enable_vblank; |
| 4716 | dev->driver->disable_vblank = valleyview_disable_vblank; |
Egbert Eich | fa00abe | 2013-02-25 12:06:48 -0500 | [diff] [blame] | 4717 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4718 | } else if (IS_GEN8(dev)) { |
| 4719 | dev->driver->irq_handler = gen8_irq_handler; |
Daniel Vetter | 723761b | 2014-05-22 17:56:34 +0200 | [diff] [blame] | 4720 | dev->driver->irq_preinstall = gen8_irq_reset; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4721 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
| 4722 | dev->driver->irq_uninstall = gen8_irq_uninstall; |
| 4723 | dev->driver->enable_vblank = gen8_enable_vblank; |
| 4724 | dev->driver->disable_vblank = gen8_disable_vblank; |
| 4725 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4726 | } else if (HAS_PCH_SPLIT(dev)) { |
| 4727 | dev->driver->irq_handler = ironlake_irq_handler; |
Daniel Vetter | 723761b | 2014-05-22 17:56:34 +0200 | [diff] [blame] | 4728 | dev->driver->irq_preinstall = ironlake_irq_reset; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4729 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
| 4730 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 4731 | dev->driver->enable_vblank = ironlake_enable_vblank; |
| 4732 | dev->driver->disable_vblank = ironlake_disable_vblank; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 4733 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4734 | } else { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4735 | if (INTEL_INFO(dev)->gen == 2) { |
| 4736 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
| 4737 | dev->driver->irq_postinstall = i8xx_irq_postinstall; |
| 4738 | dev->driver->irq_handler = i8xx_irq_handler; |
| 4739 | dev->driver->irq_uninstall = i8xx_irq_uninstall; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4740 | } else if (INTEL_INFO(dev)->gen == 3) { |
| 4741 | dev->driver->irq_preinstall = i915_irq_preinstall; |
| 4742 | dev->driver->irq_postinstall = i915_irq_postinstall; |
| 4743 | dev->driver->irq_uninstall = i915_irq_uninstall; |
| 4744 | dev->driver->irq_handler = i915_irq_handler; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4745 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4746 | } else { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4747 | dev->driver->irq_preinstall = i965_irq_preinstall; |
| 4748 | dev->driver->irq_postinstall = i965_irq_postinstall; |
| 4749 | dev->driver->irq_uninstall = i965_irq_uninstall; |
| 4750 | dev->driver->irq_handler = i965_irq_handler; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4751 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4752 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4753 | dev->driver->enable_vblank = i915_enable_vblank; |
| 4754 | dev->driver->disable_vblank = i915_disable_vblank; |
| 4755 | } |
| 4756 | } |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4757 | |
| 4758 | void intel_hpd_init(struct drm_device *dev) |
| 4759 | { |
| 4760 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 4761 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 4762 | struct drm_connector *connector; |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 4763 | unsigned long irqflags; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 4764 | int i; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4765 | |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 4766 | for (i = 1; i < HPD_NUM_PINS; i++) { |
| 4767 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
| 4768 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 4769 | } |
| 4770 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 4771 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4772 | connector->polled = intel_connector->polled; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4773 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
| 4774 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 4775 | if (intel_connector->mst_port) |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 4776 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 4777 | } |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 4778 | |
| 4779 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4780 | * just to make the assert_spin_locked checks happy. */ |
| 4781 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4782 | if (dev_priv->display.hpd_irq_setup) |
| 4783 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 4784 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4785 | } |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4786 | |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 4787 | /* Disable interrupts so we can allow runtime PM. */ |
Paulo Zanoni | 730488b | 2014-03-07 20:12:32 -0300 | [diff] [blame] | 4788 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4789 | { |
| 4790 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4791 | |
Paulo Zanoni | 730488b | 2014-03-07 20:12:32 -0300 | [diff] [blame] | 4792 | dev->driver->irq_uninstall(dev); |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 4793 | dev_priv->pm._irqs_disabled = true; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4794 | } |
| 4795 | |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 4796 | /* Restore interrupts so we can recover from runtime PM. */ |
Paulo Zanoni | 730488b | 2014-03-07 20:12:32 -0300 | [diff] [blame] | 4797 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4798 | { |
| 4799 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4800 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 4801 | dev_priv->pm._irqs_disabled = false; |
Paulo Zanoni | 730488b | 2014-03-07 20:12:32 -0300 | [diff] [blame] | 4802 | dev->driver->irq_preinstall(dev); |
| 4803 | dev->driver->irq_postinstall(dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4804 | } |