blob: e9b579fd9fc4744a44f68140e066eefdcd3387e5 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070042#include <drm/drm_plane_helper.h>
43#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080044#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080045
Matt Roper465c1202014-05-29 08:06:54 -070046/* Primary plane formats supported by all gen */
47#define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53/* Primary plane formats for gen <= 3 */
54static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58};
59
60/* Primary plane formats for gen >= 4 */
61static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69};
70
Matt Roper3d7d6512014-06-10 08:28:13 -070071/* Cursor formats */
72static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74};
75
Chris Wilson6b383a72010-09-13 13:54:26 +010076static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080077
Jesse Barnesf1f644d2013-06-27 00:39:25 +030078static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030080static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030082
Damien Lespiaue7457a92013-08-08 22:28:59 +010083static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080085static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020089static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020091static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -070092 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +020094static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +020095static void haswell_set_pipeconf(struct drm_crtc *crtc);
96static void intel_set_pipe_csc(struct drm_crtc *crtc);
Ville Syrjäläd288f652014-10-28 13:20:22 +020097static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100101
Dave Airlie0e32b392014-05-02 14:02:48 +1000102static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103{
104 if (!connector->mst_port)
105 return connector->encoder;
106 else
107 return &connector->mst_port->mst_encoders[pipe]->base;
108}
109
Jesse Barnes79e53942008-11-07 14:24:08 -0800110typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400111 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800112} intel_range_t;
113
114typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400115 int dot_limit;
116 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800117} intel_p2_t;
118
Ma Lingd4906092009-03-18 20:13:27 +0800119typedef struct intel_limit intel_limit_t;
120struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
122 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800123};
Jesse Barnes79e53942008-11-07 14:24:08 -0800124
Daniel Vetterd2acd212012-10-20 20:57:43 +0200125int
126intel_pch_rawclk(struct drm_device *dev)
127{
128 struct drm_i915_private *dev_priv = dev->dev_private;
129
130 WARN_ON(!HAS_PCH_SPLIT(dev));
131
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133}
134
Chris Wilson021357a2010-09-07 20:54:59 +0100135static inline u32 /* units of 100MHz */
136intel_fdi_link_freq(struct drm_device *dev)
137{
Chris Wilson8b99e682010-10-13 09:59:17 +0100138 if (IS_GEN5(dev)) {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141 } else
142 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100143}
144
Daniel Vetter5d536e22013-07-06 12:52:06 +0200145static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400146 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200147 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200148 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
Daniel Vetter5d536e22013-07-06 12:52:06 +0200158static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200160 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200161 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
169};
170
Keith Packarde4b36692009-06-05 19:22:17 -0700171static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400172 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200173 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200174 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700182};
Eric Anholt273e27c2011-03-30 13:01:10 -0700183
Keith Packarde4b36692009-06-05 19:22:17 -0700184static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700195};
196
197static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700208};
209
Eric Anholt273e27c2011-03-30 13:01:10 -0700210
Keith Packarde4b36692009-06-05 19:22:17 -0700211static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
221 .p2_slow = 10,
222 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800223 },
Keith Packarde4b36692009-06-05 19:22:17 -0700224};
225
226static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700237};
238
239static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800250 },
Keith Packarde4b36692009-06-05 19:22:17 -0700251};
252
253static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800264 },
Keith Packarde4b36692009-06-05 19:22:17 -0700265};
266
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500267static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700270 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700280};
281
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500282static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700293};
294
Eric Anholt273e27c2011-03-30 13:01:10 -0700295/* Ironlake / Sandybridge
296 *
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
299 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800300static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700311};
312
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800313static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800324};
325
326static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800337};
338
Eric Anholt273e27c2011-03-30 13:01:10 -0700339/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800340static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400348 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800351};
352
353static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400361 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800364};
365
Ville Syrjälädc730512013-09-24 21:26:30 +0300366static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300367 /*
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
372 */
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200374 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700375 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300378 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700380};
381
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300382static const intel_limit_t intel_limits_chv = {
383 /*
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
388 */
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396};
397
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300398static void vlv_clock(int refclk, intel_clock_t *clock)
399{
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200402 if (WARN_ON(clock->n == 0 || clock->p == 0))
403 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300406}
407
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300408/**
409 * Returns whether any output on the specified pipe is of the specified type
410 */
Damien Lespiau40935612014-10-29 11:16:59 +0000411bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300412{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300413 struct drm_device *dev = crtc->base.dev;
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300414 struct intel_encoder *encoder;
415
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300417 if (encoder->type == type)
418 return true;
419
420 return false;
421}
422
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200423/**
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427 * encoder->crtc.
428 */
429static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
430{
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
433
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
436 return true;
437
438 return false;
439}
440
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300441static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
Chris Wilson1b894b52010-12-14 20:04:54 +0000442 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800443{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300444 struct drm_device *dev = crtc->base.dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800445 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800446
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100448 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000449 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800450 limit = &intel_limits_ironlake_dual_lvds_100m;
451 else
452 limit = &intel_limits_ironlake_dual_lvds;
453 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000454 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800455 limit = &intel_limits_ironlake_single_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_single_lvds;
458 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200459 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800460 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800461
462 return limit;
463}
464
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300465static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
Ma Ling044c7c42009-03-18 20:13:23 +0800466{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300467 struct drm_device *dev = crtc->base.dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800468 const intel_limit_t *limit;
469
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100471 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700472 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800473 else
Keith Packarde4b36692009-06-05 19:22:17 -0700474 limit = &intel_limits_g4x_single_channel_lvds;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700477 limit = &intel_limits_g4x_hdmi;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700479 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800480 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700481 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800482
483 return limit;
484}
485
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300486static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800487{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300488 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800489 const intel_limit_t *limit;
490
Eric Anholtbad720f2009-10-22 16:11:14 -0700491 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000492 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800493 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800494 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500495 } else if (IS_PINEVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500497 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800498 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500499 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700502 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300503 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100504 } else if (!IS_GEN2(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100506 limit = &intel_limits_i9xx_lvds;
507 else
508 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800509 } else {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700511 limit = &intel_limits_i8xx_lvds;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700513 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200514 else
515 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800516 }
517 return limit;
518}
519
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500520/* m1 is reserved as 0 in Pineview, n is a ring counter */
521static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800522{
Shaohua Li21778322009-02-23 15:19:16 +0800523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800529}
530
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200531static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532{
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534}
535
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200536static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800537{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200538 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800539 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
541 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800544}
545
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300546static void chv_clock(int refclk, intel_clock_t *clock)
547{
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
553 clock->n << 22);
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555}
556
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800557#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800558/**
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
561 */
562
Chris Wilson1b894b52010-12-14 20:04:54 +0000563static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800566{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400570 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400572 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400574 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300575
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
579
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
585 }
586
Jesse Barnes79e53942008-11-07 14:24:08 -0800587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400588 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
591 */
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400593 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800594
595 return true;
596}
597
Ma Lingd4906092009-03-18 20:13:27 +0800598static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300599i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800602{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300603 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800604 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800605 int err = target;
606
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800608 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800612 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100613 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800614 clock.p2 = limit->p2.p2_fast;
615 else
616 clock.p2 = limit->p2.p2_slow;
617 } else {
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
620 else
621 clock.p2 = limit->p2.p2_fast;
622 }
623
Akshay Joshi0206e352011-08-16 15:34:10 -0400624 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800625
Zhao Yakui42158662009-11-20 11:24:18 +0800626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
627 clock.m1++) {
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200630 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800631 break;
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800636 int this_err;
637
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200638 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000639 if (!intel_PLL_is_valid(dev, limit,
640 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800641 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657}
658
Ma Lingd4906092009-03-18 20:13:27 +0800659static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300660pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200663{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300664 struct drm_device *dev = crtc->base.dev;
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200665 intel_clock_t clock;
666 int err = target;
667
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200669 /*
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
673 */
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
676 else
677 clock.p2 = limit->p2.p2_slow;
678 } else {
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
681 else
682 clock.p2 = limit->p2.p2_fast;
683 }
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800698 if (!intel_PLL_is_valid(dev, limit,
699 &clock))
700 continue;
701 if (match_clock &&
702 clock.p != match_clock->p)
703 continue;
704
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
707 *best_clock = clock;
708 err = this_err;
709 }
710 }
711 }
712 }
713 }
714
715 return (err != target);
716}
717
Ma Lingd4906092009-03-18 20:13:27 +0800718static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300719g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800722{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300723 struct drm_device *dev = crtc->base.dev;
Ma Lingd4906092009-03-18 20:13:27 +0800724 intel_clock_t clock;
725 int max_n;
726 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800729 found = false;
730
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100732 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800733 clock.p2 = limit->p2.p2_fast;
734 else
735 clock.p2 = limit->p2.p2_slow;
736 } else {
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
739 else
740 clock.p2 = limit->p2.p2_fast;
741 }
742
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200745 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200747 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
754 int this_err;
755
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200756 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800759 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000760
761 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800762 if (this_err < err_most) {
763 *best_clock = clock;
764 err_most = this_err;
765 max_n = clock.n;
766 found = true;
767 }
768 }
769 }
770 }
771 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800772 return found;
773}
Ma Lingd4906092009-03-18 20:13:27 +0800774
Zhenyu Wang2c072452009-06-05 15:38:42 +0800775static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300776vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700779{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300780 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300781 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300782 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300785 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700786
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300787 target *= 5; /* fast clock */
788
789 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700790
791 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300796 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700797 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300799 unsigned int ppm, diff;
800
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
802 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300803
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300804 vlv_clock(refclk, &clock);
805
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300808 continue;
809
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
812
813 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300814 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300815 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300816 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300817 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300818
Ville Syrjäläc6861222013-09-24 21:26:21 +0300819 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300820 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300821 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300822 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700823 }
824 }
825 }
826 }
827 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700828
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300829 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700830}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700831
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300832static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300833chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
836{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300837 struct drm_device *dev = crtc->base.dev;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300838 intel_clock_t clock;
839 uint64_t m2;
840 int found = false;
841
842 memset(best_clock, 0, sizeof(*best_clock));
843
844 /*
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
848 */
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
851
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856
857 clock.p = clock.p1 * clock.p2;
858
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
861
862 if (m2 > INT_MAX/clock.m1)
863 continue;
864
865 clock.m2 = m2;
866
867 chv_clock(refclk, &clock);
868
869 if (!intel_PLL_is_valid(dev, limit, &clock))
870 continue;
871
872 /* based on hardware requirement, prefer bigger p
873 */
874 if (clock.p > best_clock->p) {
875 *best_clock = clock;
876 found = true;
877 }
878 }
879 }
880
881 return found;
882}
883
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300884bool intel_crtc_active(struct drm_crtc *crtc)
885{
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
890 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100891 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300892 * as Haswell has gained clock readout/fastboot support.
893 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000894 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300895 * properly reconstruct framebuffers.
896 */
Matt Roperf4510a22014-04-01 15:22:40 -0700897 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100898 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300899}
900
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200901enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902 enum pipe pipe)
903{
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906
Daniel Vetter3b117c82013-04-17 20:15:07 +0200907 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200908}
909
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300910static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
911{
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
914 u32 line1, line2;
915 u32 line_mask;
916
917 if (IS_GEN2(dev))
918 line_mask = DSL_LINEMASK_GEN2;
919 else
920 line_mask = DSL_LINEMASK_GEN3;
921
922 line1 = I915_READ(reg) & line_mask;
923 mdelay(5);
924 line2 = I915_READ(reg) & line_mask;
925
926 return line1 == line2;
927}
928
Keith Packardab7ad7f2010-10-03 00:33:06 -0700929/*
930 * intel_wait_for_pipe_off - wait for pipe to turn off
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300931 * @crtc: crtc whose pipe to wait for
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700932 *
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
936 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700937 * On Gen4 and above:
938 * wait for the pipe register state bit to turn off
939 *
940 * Otherwise:
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100943 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700944 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300945static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700946{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300947 struct drm_device *dev = crtc->base.dev;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700948 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700951
Keith Packardab7ad7f2010-10-03 00:33:06 -0700952 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200953 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700954
Keith Packardab7ad7f2010-10-03 00:33:06 -0700955 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
957 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200958 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700959 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700960 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200962 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700963 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800964}
965
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000966/*
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
970 *
971 * Returns true if @port is connected, false otherwise.
972 */
973bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
975{
976 u32 bit;
977
Damien Lespiauc36346e2012-12-13 16:09:03 +0000978 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +0200979 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000980 case PORT_B:
981 bit = SDE_PORTB_HOTPLUG;
982 break;
983 case PORT_C:
984 bit = SDE_PORTC_HOTPLUG;
985 break;
986 case PORT_D:
987 bit = SDE_PORTD_HOTPLUG;
988 break;
989 default:
990 return true;
991 }
992 } else {
Robin Schroereba905b2014-05-18 02:24:50 +0200993 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000994 case PORT_B:
995 bit = SDE_PORTB_HOTPLUG_CPT;
996 break;
997 case PORT_C:
998 bit = SDE_PORTC_HOTPLUG_CPT;
999 break;
1000 case PORT_D:
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1002 break;
1003 default:
1004 return true;
1005 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001006 }
1007
1008 return I915_READ(SDEISR) & bit;
1009}
1010
Jesse Barnesb24e7172011-01-04 15:09:30 -08001011static const char *state_string(bool enabled)
1012{
1013 return enabled ? "on" : "off";
1014}
1015
1016/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001017void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001019{
1020 int reg;
1021 u32 val;
1022 bool cur_state;
1023
1024 reg = DPLL(pipe);
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1030}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001031
Jani Nikula23538ef2013-08-27 15:12:22 +03001032/* XXX: the dsi pll is shared between MIPI DSI ports */
1033static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034{
1035 u32 val;
1036 bool cur_state;
1037
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1041
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1046}
1047#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
Daniel Vetter55607e82013-06-16 21:42:39 +02001050struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001051intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001052{
Daniel Vettere2b78262013-06-07 23:10:03 +02001053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
Daniel Vettera43f6e02013-06-07 23:10:32 +02001055 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001056 return NULL;
1057
Daniel Vettera43f6e02013-06-07 23:10:32 +02001058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001059}
1060
Jesse Barnesb24e7172011-01-04 15:09:30 -08001061/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001062void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1064 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001065{
Jesse Barnes040484a2011-01-03 12:14:26 -08001066 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001067 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001068
Chris Wilson92b27b02012-05-20 18:10:50 +01001069 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001070 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001072
Daniel Vetter53589012013-06-05 13:34:16 +02001073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001074 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001077}
Jesse Barnes040484a2011-01-03 12:14:26 -08001078
1079static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081{
1082 int reg;
1083 u32 val;
1084 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001087
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001091 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101}
1102#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107{
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118}
1119#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001130 return;
1131
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001133 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001134 return;
1135
Jesse Barnes040484a2011-01-03 12:14:26 -08001136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139}
1140
Daniel Vetter55607e82013-06-16 21:42:39 +02001141void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001143{
1144 int reg;
1145 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001146 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001154}
1155
Daniel Vetterb680c372014-09-19 18:27:27 +02001156void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
Jesse Barnesea0760c2011-01-04 15:09:32 -08001158{
Jani Nikulabedd4db2014-08-22 15:04:13 +03001159 struct drm_device *dev = dev_priv->dev;
1160 int pp_reg;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001161 u32 val;
1162 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001163 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001164
Jani Nikulabedd4db2014-08-22 15:04:13 +03001165 if (WARN_ON(HAS_DDI(dev)))
1166 return;
1167
1168 if (HAS_PCH_SPLIT(dev)) {
1169 u32 port_sel;
1170
Jesse Barnesea0760c2011-01-04 15:09:32 -08001171 pp_reg = PCH_PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181 panel_pipe = pipe;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001182 } else {
1183 pp_reg = PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001186 }
1187
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
Jani Nikulaec49ba22014-08-21 15:06:25 +03001190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
Jesse Barnesea0760c2011-01-04 15:09:32 -08001191 locked = false;
1192
Jesse Barnesea0760c2011-01-04 15:09:32 -08001193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001195 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001196}
1197
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001198static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200{
1201 struct drm_device *dev = dev_priv->dev;
1202 bool cur_state;
1203
Paulo Zanonid9d82082014-02-27 16:30:56 -03001204 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001206 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001208
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1212}
1213#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001216void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001218{
1219 int reg;
1220 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001221 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001224
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetter8e636782012-01-22 01:36:48 +01001228 state = true;
1229
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001230 if (!intel_display_power_is_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001241 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001242}
1243
Chris Wilson931872f2012-01-16 23:01:13 +00001244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001246{
1247 int reg;
1248 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001249 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001257}
1258
Chris Wilson931872f2012-01-16 23:01:13 +00001259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
Jesse Barnesb24e7172011-01-04 15:09:30 -08001262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001265 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001266 int reg, i;
1267 u32 val;
1268 int cur_pipe;
1269
Ville Syrjälä653e1022013-06-04 13:49:05 +03001270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001274 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001275 "plane %c assertion failure, should be disabled but not\n",
1276 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001277 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001278 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001279
Jesse Barnesb24e7172011-01-04 15:09:30 -08001280 /* Need to check both planes against the pipe */
Damien Lespiau055e3932014-08-18 13:49:10 +01001281 for_each_pipe(dev_priv, i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001282 reg = DSPCNTR(i);
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001289 }
1290}
1291
Jesse Barnes19332d72013-03-28 09:55:38 -07001292static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe)
1294{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001295 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001296 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001297 u32 val;
1298
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1305 }
1306 } else if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001309 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001310 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001312 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001313 }
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1315 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001316 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001317 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001323 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001326 }
1327}
1328
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001329static void assert_vblank_disabled(struct drm_crtc *crtc)
1330{
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1333}
1334
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001335static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001336{
1337 u32 val;
1338 bool enabled;
1339
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001341
Jesse Barnes92f25842011-01-04 15:09:34 -08001342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346}
1347
Daniel Vetterab9412b2013-05-03 11:49:46 +02001348static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001350{
1351 int reg;
1352 u32 val;
1353 bool enabled;
1354
Daniel Vetterab9412b2013-05-03 11:49:46 +02001355 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001358 WARN(enabled,
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001361}
1362
Keith Packard4e634382011-08-06 10:39:45 -07001363static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001365{
1366 if ((val & DP_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001377 } else {
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379 return false;
1380 }
1381 return true;
1382}
1383
Keith Packard1519b992011-08-06 10:35:34 -07001384static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1386{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001387 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001388 return false;
1389
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001392 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001396 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001398 return false;
1399 }
1400 return true;
1401}
1402
1403static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1405{
1406 if ((val & LVDS_PORT_EN) == 0)
1407 return false;
1408
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411 return false;
1412 } else {
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414 return false;
1415 }
1416 return true;
1417}
1418
1419static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421{
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1423 return false;
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426 return false;
1427 } else {
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429 return false;
1430 }
1431 return true;
1432}
1433
Jesse Barnes291906f2011-02-02 12:28:03 -08001434static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001435 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001436{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001437 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001440 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001441
Daniel Vetter75c5da22012-09-10 21:58:29 +02001442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001444 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001445}
1446
1447static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1449{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001450 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001453 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001454
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001456 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001457 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001458}
1459
1460static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe)
1462{
1463 int reg;
1464 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001465
Keith Packardf0575e92011-07-25 22:12:43 -07001466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001469
1470 reg = PCH_ADPA;
1471 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001473 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001474 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001475
1476 reg = PCH_LVDS;
1477 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001480 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001481
Paulo Zanonie2debe92013-02-18 19:00:27 -03001482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001485}
1486
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001487static void intel_init_dpio(struct drm_device *dev)
1488{
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491 if (!IS_VALLEYVIEW(dev))
1492 return;
1493
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001494 /*
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498 */
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502 } else {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001505}
1506
Ville Syrjäläd288f652014-10-28 13:20:22 +02001507static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001509{
Daniel Vetter426115c2013-07-11 22:13:42 +02001510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
Ville Syrjäläd288f652014-10-28 13:20:22 +02001513 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001514
Daniel Vetter426115c2013-07-11 22:13:42 +02001515 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001516
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001517 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520 /* PLL is protected by panel, make sure we can write it */
Jani Nikula6a9e7362014-08-22 15:06:35 +03001521 if (IS_MOBILE(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001522 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001523
Daniel Vetter426115c2013-07-11 22:13:42 +02001524 I915_WRITE(reg, dpll);
1525 POSTING_READ(reg);
1526 udelay(150);
1527
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
Ville Syrjäläd288f652014-10-28 13:20:22 +02001531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
Daniel Vetter426115c2013-07-11 22:13:42 +02001532 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001533
1534 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001535 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001536 POSTING_READ(reg);
1537 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001538 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001541 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544}
1545
Ville Syrjäläd288f652014-10-28 13:20:22 +02001546static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001548{
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001553 u32 tmp;
1554
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559 mutex_lock(&dev_priv->dpio_lock);
1560
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566 /*
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568 */
1569 udelay(1);
1570
1571 /* Enable PLL */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001573
1574 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001578 /* not sure when this should be written */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001580 POSTING_READ(DPLL_MD(pipe));
1581
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001582 mutex_unlock(&dev_priv->dpio_lock);
1583}
1584
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001585static int intel_num_dvo_pipes(struct drm_device *dev)
1586{
1587 struct intel_crtc *crtc;
1588 int count = 0;
1589
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001593
1594 return count;
1595}
1596
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001597static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001598{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001603
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001604 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001605
1606 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001608
1609 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001612
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615 /*
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1620 */
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001641
1642 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001643 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001646 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001649 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652}
1653
1654/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001655 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001663static void i9xx_disable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001664{
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1668
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677 }
1678
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001682 return;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
Daniel Vetter50b44a42013-06-05 13:34:33 +02001687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001689}
1690
Jesse Barnesf6071162013-10-01 10:41:38 -07001691static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692{
1693 u32 val = 0;
1694
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1697
Imre Deake5cbfbf2014-01-09 17:08:16 +02001698 /*
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1701 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001702 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001706
1707}
1708
1709static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001712 u32 val;
1713
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001716
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001717 /* Set PLL en = 0 */
Ville Syrjäläd17ec4c2014-06-28 02:03:59 +03001718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001719 if (pipe != PIPE_A)
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001723
1724 mutex_lock(&dev_priv->dpio_lock);
1725
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
Ville Syrjälä61407f62014-05-27 16:32:55 +03001731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736 } else {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740 }
1741
Ville Syrjäläd7520482014-04-09 13:28:59 +03001742 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001743}
1744
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001745void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001747{
1748 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001749 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001750
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001751 switch (dport->port) {
1752 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001753 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001754 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001755 break;
1756 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001757 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_D:
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001763 break;
1764 default:
1765 BUG();
1766 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001767
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001770 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001771}
1772
Daniel Vetterb14b1052014-04-24 23:55:13 +02001773static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774{
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001779 if (WARN_ON(pll == NULL))
1780 return;
1781
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001782 WARN_ON(!pll->config.crtc_mask);
Daniel Vetterb14b1052014-04-24 23:55:13 +02001783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785 WARN_ON(pll->on);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788 pll->mode_set(dev_priv, pll);
1789 }
1790}
1791
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001792/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001793 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1796 *
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1799 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001800static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001801{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001805
Daniel Vetter87a875b2013-06-05 13:34:19 +02001806 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001807 return;
1808
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001809 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001810 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001811
Damien Lespiau74dd6922014-07-29 18:06:17 +01001812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
Daniel Vetter46edb022013-06-05 13:34:12 +02001813 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001814 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001815
Daniel Vettercdbd2312013-06-05 13:34:03 +02001816 if (pll->active++) {
1817 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001818 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001819 return;
1820 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001821 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001822
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
Daniel Vetter46edb022013-06-05 13:34:12 +02001825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001826 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001827 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001828}
1829
Damien Lespiauf6daaec2014-08-09 23:00:56 +01001830static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001831{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001835
Jesse Barnes92f25842011-01-04 15:09:34 -08001836 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001837 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001838 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001839 return;
1840
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001841 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001842 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001843
Daniel Vetter46edb022013-06-05 13:34:12 +02001844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001846 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001847
Chris Wilson48da64a2012-05-13 20:16:12 +01001848 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001849 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001850 return;
1851 }
1852
Daniel Vettere9d69442013-06-05 13:34:15 +02001853 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001854 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001855 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001856 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001857
Daniel Vetter46edb022013-06-05 13:34:12 +02001858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001859 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001860 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001861
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001863}
1864
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001865static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001867{
Daniel Vetter23670b322012-11-01 09:15:30 +01001868 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001871 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001872
1873 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03001874 BUG_ON(!HAS_PCH_SPLIT(dev));
Jesse Barnes040484a2011-01-03 12:14:26 -08001875
1876 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001877 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001878 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1883
Daniel Vetter23670b322012-11-01 09:15:30 +01001884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001891 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001892
Daniel Vetterab9412b2013-05-03 11:49:46 +02001893 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001894 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001895 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001896
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1898 /*
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1901 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001904 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001905
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001908 if (HAS_PCH_IBX(dev_priv->dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001910 val |= TRANS_LEGACY_INTERLACED_ILK;
1911 else
1912 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001913 else
1914 val |= TRANS_PROGRESSIVE;
1915
Jesse Barnes040484a2011-01-03 12:14:26 -08001916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001919}
1920
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001921static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001922 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001923{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001924 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001925
1926 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03001927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001928
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001929 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001932
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001936 I915_WRITE(_TRANSA_CHICKEN2, val);
1937
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001938 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001940
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001943 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001944 else
1945 val |= TRANS_PROGRESSIVE;
1946
Daniel Vetterab9412b2013-05-03 11:49:46 +02001947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001949 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001950}
1951
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001952static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001954{
Daniel Vetter23670b322012-11-01 09:15:30 +01001955 struct drm_device *dev = dev_priv->dev;
1956 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001957
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1961
Jesse Barnes291906f2011-02-02 12:28:03 -08001962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1964
Daniel Vetterab9412b2013-05-03 11:49:46 +02001965 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001972
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1979 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001980}
1981
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001982static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001983{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001984 u32 val;
1985
Daniel Vetterab9412b2013-05-03 11:49:46 +02001986 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001987 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001988 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001989 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001991 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001992
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001996 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001997}
1998
1999/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002000 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02002001 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002002 *
Paulo Zanoni03722642014-01-17 13:51:09 -02002003 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002005 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02002006static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002007{
Paulo Zanoni03722642014-01-17 13:51:09 -02002008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002013 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002014 int reg;
2015 u32 val;
2016
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002017 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002018 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002019 assert_sprites_disabled(dev_priv, pipe);
2020
Paulo Zanoni681e5812012-12-06 11:12:38 -02002021 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002022 pch_transcoder = TRANSCODER_A;
2023 else
2024 pch_transcoder = pipe;
2025
Jesse Barnesb24e7172011-01-04 15:09:30 -08002026 /*
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2029 * need the check.
2030 */
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002033 assert_dsi_pll_enabled(dev_priv);
2034 else
2035 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002036 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002037 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002038 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002042 }
2043 /* FIXME: assert CPU port conditions for SNB+ */
2044 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002045
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002046 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002047 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002048 if (val & PIPECONF_ENABLE) {
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
Chris Wilson00d70b12011-03-17 07:18:29 +00002051 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002052 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002053
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002055 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002056}
2057
2058/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002059 * intel_disable_pipe - disable a pipe, asserting requirements
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002060 * @crtc: crtc whose pipes is to be disabled
Jesse Barnesb24e7172011-01-04 15:09:30 -08002061 *
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002065 *
2066 * Will wait until the pipe has shut down before returning.
2067 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002068static void intel_disable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002069{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002073 int reg;
2074 u32 val;
2075
2076 /*
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2079 */
2080 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002081 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002082 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002083
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002084 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002085 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
Ville Syrjälä67adc642014-08-15 01:21:57 +03002089 /*
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2092 */
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096 /* Don't disable pipe or pipe PLLs if needed */
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Ville Syrjälä67adc642014-08-15 01:21:57 +03002099 val &= ~PIPECONF_ENABLE;
2100
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002104}
2105
Keith Packardd74362c2011-07-28 14:47:14 -07002106/*
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2109 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002110void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002112{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002115
2116 I915_WRITE(reg, I915_READ(reg));
2117 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002118}
2119
Jesse Barnesb24e7172011-01-04 15:09:30 -08002120/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002124 *
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002125 * Enable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002126 */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002127static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002129{
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002133
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002136
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002137 if (intel_crtc->primary_enabled)
2138 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002139
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002140 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002141
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2143 crtc->x, crtc->y);
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002144
2145 /*
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2149 */
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002152}
2153
Jesse Barnesb24e7172011-01-04 15:09:30 -08002154/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002155 * intel_disable_primary_hw_plane - disable the primary hardware plane
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002158 *
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002159 * Disable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002160 */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002161static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002163{
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002169
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002170 if (!intel_crtc->primary_enabled)
2171 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002172
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002173 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002174
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002177}
2178
Chris Wilson693db182013-03-05 14:52:39 +00002179static bool need_vtd_wa(struct drm_device *dev)
2180{
2181#ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184#endif
2185 return false;
2186}
2187
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002188static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189{
2190 int tile_height;
2191
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2194}
2195
Chris Wilson127bd2a2010-07-23 23:32:05 +01002196int
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002197intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198 struct drm_framebuffer *fb,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002199 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002200{
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002201 struct drm_device *dev = fb->dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00002202 struct drm_i915_private *dev_priv = dev->dev_private;
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002203 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002204 u32 alignment;
2205 int ret;
2206
Matt Roperebcdd392014-07-09 16:22:11 -07002207 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
Chris Wilson05394f32010-11-08 19:18:58 +00002209 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002210 case I915_TILING_NONE:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002211 if (INTEL_INFO(dev)->gen >= 9)
2212 alignment = 256 * 1024;
2213 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
Chris Wilson534843d2010-07-05 18:01:46 +01002214 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002215 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002216 alignment = 4 * 1024;
2217 else
2218 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002219 break;
2220 case I915_TILING_X:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002221 if (INTEL_INFO(dev)->gen >= 9)
2222 alignment = 256 * 1024;
2223 else {
2224 /* pin() will align the object as required by fence */
2225 alignment = 0;
2226 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002227 break;
2228 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002230 return -EINVAL;
2231 default:
2232 BUG();
2233 }
2234
Chris Wilson693db182013-03-05 14:52:39 +00002235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2238 * the VT-d warning.
2239 */
2240 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241 alignment = 256 * 1024;
2242
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002243 /*
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2249 */
2250 intel_runtime_pm_get(dev_priv);
2251
Chris Wilsonce453d82011-02-21 14:43:56 +00002252 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002253 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002254 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002255 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002256
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2261 */
Chris Wilson06d98132012-04-17 15:31:24 +01002262 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002263 if (ret)
2264 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002265
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002266 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002267
Chris Wilsonce453d82011-02-21 14:43:56 +00002268 dev_priv->mm.interruptible = true;
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002269 intel_runtime_pm_put(dev_priv);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002270 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002271
2272err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002273 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002274err_interruptible:
2275 dev_priv->mm.interruptible = true;
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002276 intel_runtime_pm_put(dev_priv);
Chris Wilson48b956c2010-09-14 12:50:34 +01002277 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002278}
2279
Chris Wilson1690e1e2011-12-14 13:57:08 +01002280void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281{
Matt Roperebcdd392014-07-09 16:22:11 -07002282 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
Chris Wilson1690e1e2011-12-14 13:57:08 +01002284 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002285 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002286}
2287
Daniel Vetterc2c75132012-07-05 12:17:30 +02002288/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002290unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291 unsigned int tiling_mode,
2292 unsigned int cpp,
2293 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002294{
Chris Wilsonbc752862013-02-21 20:04:31 +00002295 if (tiling_mode != I915_TILING_NONE) {
2296 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002297
Chris Wilsonbc752862013-02-21 20:04:31 +00002298 tile_rows = *y / 8;
2299 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002300
Chris Wilsonbc752862013-02-21 20:04:31 +00002301 tiles = *x / (512/cpp);
2302 *x %= 512/cpp;
2303
2304 return tile_rows * pitch * 8 + tiles * 4096;
2305 } else {
2306 unsigned int offset;
2307
2308 offset = *y * pitch + *x * cpp;
2309 *y = 0;
2310 *x = (offset & 4095) / cpp;
2311 return offset & -4096;
2312 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002313}
2314
Jesse Barnes46f297f2014-03-07 08:57:48 -08002315int intel_format_to_fourcc(int format)
2316{
2317 switch (format) {
2318 case DISPPLANE_8BPP:
2319 return DRM_FORMAT_C8;
2320 case DISPPLANE_BGRX555:
2321 return DRM_FORMAT_XRGB1555;
2322 case DISPPLANE_BGRX565:
2323 return DRM_FORMAT_RGB565;
2324 default:
2325 case DISPPLANE_BGRX888:
2326 return DRM_FORMAT_XRGB8888;
2327 case DISPPLANE_RGBX888:
2328 return DRM_FORMAT_XBGR8888;
2329 case DISPPLANE_BGRX101010:
2330 return DRM_FORMAT_XRGB2101010;
2331 case DISPPLANE_RGBX101010:
2332 return DRM_FORMAT_XBGR2101010;
2333 }
2334}
2335
Jesse Barnes484b41d2014-03-07 08:57:55 -08002336static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002337 struct intel_plane_config *plane_config)
2338{
2339 struct drm_device *dev = crtc->base.dev;
2340 struct drm_i915_gem_object *obj = NULL;
2341 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342 u32 base = plane_config->base;
2343
Chris Wilsonff2652e2014-03-10 08:07:02 +00002344 if (plane_config->size == 0)
2345 return false;
2346
Jesse Barnes46f297f2014-03-07 08:57:48 -08002347 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348 plane_config->size);
2349 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002350 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002351
2352 if (plane_config->tiled) {
2353 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002354 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002355 }
2356
Dave Airlie66e514c2014-04-03 07:51:54 +10002357 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358 mode_cmd.width = crtc->base.primary->fb->width;
2359 mode_cmd.height = crtc->base.primary->fb->height;
2360 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002361
2362 mutex_lock(&dev->struct_mutex);
2363
Dave Airlie66e514c2014-04-03 07:51:54 +10002364 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002365 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002366 DRM_DEBUG_KMS("intel fb init failed\n");
2367 goto out_unref_obj;
2368 }
2369
Daniel Vettera071fa02014-06-18 23:28:09 +02002370 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002371 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002372
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002375
2376out_unref_obj:
2377 drm_gem_object_unreference(&obj->base);
2378 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002379 return false;
2380}
2381
2382static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383 struct intel_plane_config *plane_config)
2384{
2385 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002386 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002387 struct drm_crtc *c;
2388 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002389 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002390
Dave Airlie66e514c2014-04-03 07:51:54 +10002391 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002392 return;
2393
2394 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395 return;
2396
Dave Airlie66e514c2014-04-03 07:51:54 +10002397 kfree(intel_crtc->base.primary->fb);
2398 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002399
2400 /*
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2403 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002404 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002405 i = to_intel_crtc(c);
2406
2407 if (c == &intel_crtc->base)
2408 continue;
2409
Matt Roper2ff8fde2014-07-08 07:50:07 -07002410 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002411 continue;
2412
Matt Roper2ff8fde2014-07-08 07:50:07 -07002413 obj = intel_fb_obj(c->primary->fb);
2414 if (obj == NULL)
2415 continue;
2416
2417 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002418 if (obj->tiling_mode != I915_TILING_NONE)
2419 dev_priv->preserve_bios_swizzle = true;
2420
Dave Airlie66e514c2014-04-03 07:51:54 +10002421 drm_framebuffer_reference(c->primary->fb);
2422 intel_crtc->base.primary->fb = c->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002423 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002424 break;
2425 }
2426 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002427}
2428
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002429static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430 struct drm_framebuffer *fb,
2431 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002432{
2433 struct drm_device *dev = crtc->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002436 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002437 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002438 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002439 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002440 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302441 int pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002442
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002443 if (!intel_crtc->primary_enabled) {
2444 I915_WRITE(reg, 0);
2445 if (INTEL_INFO(dev)->gen >= 4)
2446 I915_WRITE(DSPSURF(plane), 0);
2447 else
2448 I915_WRITE(DSPADDR(plane), 0);
2449 POSTING_READ(reg);
2450 return;
2451 }
2452
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002453 obj = intel_fb_obj(fb);
2454 if (WARN_ON(obj == NULL))
2455 return;
2456
2457 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002459 dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002461 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002462
2463 if (INTEL_INFO(dev)->gen < 4) {
2464 if (intel_crtc->pipe == PIPE_B)
2465 dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2469 */
2470 I915_WRITE(DSPSIZE(plane),
2471 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472 (intel_crtc->config.pipe_src_w - 1));
2473 I915_WRITE(DSPPOS(plane), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +03002474 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475 I915_WRITE(PRIMSIZE(plane),
2476 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477 (intel_crtc->config.pipe_src_w - 1));
2478 I915_WRITE(PRIMPOS(plane), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane), 0);
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002480 }
2481
Ville Syrjälä57779d02012-10-31 17:50:14 +02002482 switch (fb->pixel_format) {
2483 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002484 dspcntr |= DISPPLANE_8BPP;
2485 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002486 case DRM_FORMAT_XRGB1555:
2487 case DRM_FORMAT_ARGB1555:
2488 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002489 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002490 case DRM_FORMAT_RGB565:
2491 dspcntr |= DISPPLANE_BGRX565;
2492 break;
2493 case DRM_FORMAT_XRGB8888:
2494 case DRM_FORMAT_ARGB8888:
2495 dspcntr |= DISPPLANE_BGRX888;
2496 break;
2497 case DRM_FORMAT_XBGR8888:
2498 case DRM_FORMAT_ABGR8888:
2499 dspcntr |= DISPPLANE_RGBX888;
2500 break;
2501 case DRM_FORMAT_XRGB2101010:
2502 case DRM_FORMAT_ARGB2101010:
2503 dspcntr |= DISPPLANE_BGRX101010;
2504 break;
2505 case DRM_FORMAT_XBGR2101010:
2506 case DRM_FORMAT_ABGR2101010:
2507 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002508 break;
2509 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002510 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002511 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002512
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002513 if (INTEL_INFO(dev)->gen >= 4 &&
2514 obj->tiling_mode != I915_TILING_NONE)
2515 dspcntr |= DISPPLANE_TILED;
Jesse Barnes81255562010-08-02 12:07:50 -07002516
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002517 if (IS_G4X(dev))
2518 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
Ville Syrjäläb98971272014-08-27 16:51:22 +03002520 linear_offset = y * fb->pitches[0] + x * pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002521
Daniel Vetterc2c75132012-07-05 12:17:30 +02002522 if (INTEL_INFO(dev)->gen >= 4) {
2523 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002524 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002525 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002526 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002527 linear_offset -= intel_crtc->dspaddr_offset;
2528 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002529 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002530 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002531
Sonika Jindal48404c12014-08-22 14:06:04 +05302532 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535 x += (intel_crtc->config.pipe_src_w - 1);
2536 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2540 linear_offset +=
2541 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543 }
2544
2545 I915_WRITE(reg, dspcntr);
2546
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002550 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002551 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002554 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002555 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002556 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002557 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002558 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002559}
2560
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002561static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562 struct drm_framebuffer *fb,
2563 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002564{
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002568 struct drm_i915_gem_object *obj;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002569 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002570 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002571 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002572 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302573 int pixel_size;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002574
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002575 if (!intel_crtc->primary_enabled) {
2576 I915_WRITE(reg, 0);
2577 I915_WRITE(DSPSURF(plane), 0);
2578 POSTING_READ(reg);
2579 return;
2580 }
2581
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002582 obj = intel_fb_obj(fb);
2583 if (WARN_ON(obj == NULL))
2584 return;
2585
2586 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002588 dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002590 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002591
2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
Ville Syrjälä57779d02012-10-31 17:50:14 +02002595 switch (fb->pixel_format) {
2596 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002597 dspcntr |= DISPPLANE_8BPP;
2598 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002599 case DRM_FORMAT_RGB565:
2600 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002601 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002602 case DRM_FORMAT_XRGB8888:
2603 case DRM_FORMAT_ARGB8888:
2604 dspcntr |= DISPPLANE_BGRX888;
2605 break;
2606 case DRM_FORMAT_XBGR8888:
2607 case DRM_FORMAT_ABGR8888:
2608 dspcntr |= DISPPLANE_RGBX888;
2609 break;
2610 case DRM_FORMAT_XRGB2101010:
2611 case DRM_FORMAT_ARGB2101010:
2612 dspcntr |= DISPPLANE_BGRX101010;
2613 break;
2614 case DRM_FORMAT_XBGR2101010:
2615 case DRM_FORMAT_ABGR2101010:
2616 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002617 break;
2618 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002619 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002620 }
2621
2622 if (obj->tiling_mode != I915_TILING_NONE)
2623 dspcntr |= DISPPLANE_TILED;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002624
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002625 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002626 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002627
Ville Syrjäläb98971272014-08-27 16:51:22 +03002628 linear_offset = y * fb->pitches[0] + x * pixel_size;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002629 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002630 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002631 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002632 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002633 linear_offset -= intel_crtc->dspaddr_offset;
Sonika Jindal48404c12014-08-22 14:06:04 +05302634 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638 x += (intel_crtc->config.pipe_src_w - 1);
2639 y += (intel_crtc->config.pipe_src_h - 1);
2640
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2643 linear_offset +=
2644 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646 }
2647 }
2648
2649 I915_WRITE(reg, dspcntr);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002650
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002654 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002655 I915_WRITE(DSPSURF(plane),
2656 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002657 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002658 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659 } else {
2660 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002663 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002664}
2665
Damien Lespiau70d21f02013-07-03 21:06:04 +01002666static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667 struct drm_framebuffer *fb,
2668 int x, int y)
2669{
2670 struct drm_device *dev = crtc->dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673 struct intel_framebuffer *intel_fb;
2674 struct drm_i915_gem_object *obj;
2675 int pipe = intel_crtc->pipe;
2676 u32 plane_ctl, stride;
2677
2678 if (!intel_crtc->primary_enabled) {
2679 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe, 0));
2682 return;
2683 }
2684
2685 plane_ctl = PLANE_CTL_ENABLE |
2686 PLANE_CTL_PIPE_GAMMA_ENABLE |
2687 PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689 switch (fb->pixel_format) {
2690 case DRM_FORMAT_RGB565:
2691 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692 break;
2693 case DRM_FORMAT_XRGB8888:
2694 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695 break;
2696 case DRM_FORMAT_XBGR8888:
2697 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699 break;
2700 case DRM_FORMAT_XRGB2101010:
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702 break;
2703 case DRM_FORMAT_XBGR2101010:
2704 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706 break;
2707 default:
2708 BUG();
2709 }
2710
2711 intel_fb = to_intel_framebuffer(fb);
2712 obj = intel_fb->obj;
2713
2714 /*
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2717 */
2718 switch (obj->tiling_mode) {
2719 case I915_TILING_NONE:
2720 stride = fb->pitches[0] >> 6;
2721 break;
2722 case I915_TILING_X:
2723 plane_ctl |= PLANE_CTL_TILED_X;
2724 stride = fb->pitches[0] >> 9;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
Sonika Jindal1447dde2014-10-04 10:53:31 +01002731 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732 plane_ctl |= PLANE_CTL_ROTATE_180;
Damien Lespiau70d21f02013-07-03 21:06:04 +01002733
2734 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj),
2738 x, y, fb->width, fb->height,
2739 fb->pitches[0]);
2740
2741 I915_WRITE(PLANE_POS(pipe, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743 I915_WRITE(PLANE_SIZE(pipe, 0),
2744 (intel_crtc->config.pipe_src_h - 1) << 16 |
2745 (intel_crtc->config.pipe_src_w - 1));
2746 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749 POSTING_READ(PLANE_SURF(pipe, 0));
2750}
2751
Jesse Barnes17638cd2011-06-24 12:19:23 -07002752/* Assume fb object is pinned & idle & fenced and just update base pointers */
2753static int
2754intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755 int x, int y, enum mode_set_atomic state)
2756{
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002759
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002760 if (dev_priv->display.disable_fbc)
2761 dev_priv->display.disable_fbc(dev);
Jesse Barnes81255562010-08-02 12:07:50 -07002762
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002763 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002766}
2767
Ville Syrjälä96a02912013-02-18 19:08:49 +02002768void intel_display_handle_reset(struct drm_device *dev)
2769{
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct drm_crtc *crtc;
2772
2773 /*
2774 * Flips in the rings have been nuked by the reset,
2775 * so complete all pending flips so that user space
2776 * will get its events and not get stuck.
2777 *
2778 * Also update the base address of all primary
2779 * planes to the the last fb to make sure we're
2780 * showing the correct fb after a reset.
2781 *
2782 * Need to make two loops over the crtcs so that we
2783 * don't try to grab a crtc mutex before the
2784 * pending_flip_queue really got woken up.
2785 */
2786
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002787 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 enum plane plane = intel_crtc->plane;
2790
2791 intel_prepare_page_flip(dev, plane);
2792 intel_finish_page_flip_plane(dev, plane);
2793 }
2794
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002795 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
Rob Clark51fd3712013-11-19 12:10:12 -05002798 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002799 /*
2800 * FIXME: Once we have proper support for primary planes (and
2801 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002802 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002803 */
Matt Roperf4510a22014-04-01 15:22:40 -07002804 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002805 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002806 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002807 crtc->x,
2808 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05002809 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002810 }
2811}
2812
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002813static int
Chris Wilson14667a42012-04-03 17:58:35 +01002814intel_finish_fb(struct drm_framebuffer *old_fb)
2815{
Matt Roper2ff8fde2014-07-08 07:50:07 -07002816 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
Chris Wilson14667a42012-04-03 17:58:35 +01002817 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818 bool was_interruptible = dev_priv->mm.interruptible;
2819 int ret;
2820
Chris Wilson14667a42012-04-03 17:58:35 +01002821 /* Big Hammer, we also need to ensure that any pending
2822 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823 * current scanout is retired before unpinning the old
2824 * framebuffer.
2825 *
2826 * This should only fail upon a hung GPU, in which case we
2827 * can safely continue.
2828 */
2829 dev_priv->mm.interruptible = false;
2830 ret = i915_gem_object_finish_gpu(obj);
2831 dev_priv->mm.interruptible = was_interruptible;
2832
2833 return ret;
2834}
2835
Chris Wilson7d5e3792014-03-04 13:15:08 +00002836static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002841 bool pending;
2842
2843 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845 return false;
2846
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02002847 spin_lock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002848 pending = to_intel_crtc(crtc)->unpin_work != NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02002849 spin_unlock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002850
2851 return pending;
2852}
2853
Gustavo Padovane30e8f72014-09-10 12:04:17 -03002854static void intel_update_pipe_size(struct intel_crtc *crtc)
2855{
2856 struct drm_device *dev = crtc->base.dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858 const struct drm_display_mode *adjusted_mode;
2859
2860 if (!i915.fastboot)
2861 return;
2862
2863 /*
2864 * Update pipe size and adjust fitter if needed: the reason for this is
2865 * that in compute_mode_changes we check the native mode (not the pfit
2866 * mode) to see if we can flip rather than do a full mode set. In the
2867 * fastboot case, we'll flip, but if we don't update the pipesrc and
2868 * pfit state, we'll end up with a big fb scanned out into the wrong
2869 * sized surface.
2870 *
2871 * To fix this properly, we need to hoist the checks up into
2872 * compute_mode_changes (or above), check the actual pfit state and
2873 * whether the platform allows pfit disable with pipe active, and only
2874 * then update the pipesrc and pfit state, even on the flip path.
2875 */
2876
2877 adjusted_mode = &crtc->config.adjusted_mode;
2878
2879 I915_WRITE(PIPESRC(crtc->pipe),
2880 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881 (adjusted_mode->crtc_vdisplay - 1));
2882 if (!crtc->config.pch_pfit.enabled &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002883 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Gustavo Padovane30e8f72014-09-10 12:04:17 -03002885 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888 }
2889 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891}
2892
Chris Wilson14667a42012-04-03 17:58:35 +01002893static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002894intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002895 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002896{
2897 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002898 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02002900 enum pipe pipe = intel_crtc->pipe;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002901 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002902 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002903 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002904
Chris Wilson7d5e3792014-03-04 13:15:08 +00002905 if (intel_crtc_has_pending_flip(crtc)) {
2906 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907 return -EBUSY;
2908 }
2909
Jesse Barnes79e53942008-11-07 14:24:08 -08002910 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002911 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002912 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002913 return 0;
2914 }
2915
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002916 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002917 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918 plane_name(intel_crtc->plane),
2919 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002920 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002921 }
2922
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002923 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002924 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
Daniel Vettera071fa02014-06-18 23:28:09 +02002925 if (ret == 0)
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002926 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
Daniel Vettera071fa02014-06-18 23:28:09 +02002927 INTEL_FRONTBUFFER_PRIMARY(pipe));
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002928 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002929 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002930 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002931 return ret;
2932 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002933
Gustavo Padovane30e8f72014-09-10 12:04:17 -03002934 intel_update_pipe_size(intel_crtc);
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002935
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002936 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002937
Daniel Vetterf99d7062014-06-19 16:01:59 +02002938 if (intel_crtc->active)
2939 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2940
Matt Roperf4510a22014-04-01 15:22:40 -07002941 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002942 crtc->x = x;
2943 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002944
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002945 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002946 if (intel_crtc->active && old_fb != fb)
2947 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002948 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002949 intel_unpin_fb_obj(old_obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002950 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002951 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002952
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002953 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002954 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002955 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002956
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002957 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002958}
2959
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002960static void intel_fdi_normal_train(struct drm_crtc *crtc)
2961{
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 int pipe = intel_crtc->pipe;
2966 u32 reg, temp;
2967
2968 /* enable normal train */
2969 reg = FDI_TX_CTL(pipe);
2970 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002971 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002972 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2973 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002974 } else {
2975 temp &= ~FDI_LINK_TRAIN_NONE;
2976 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002977 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002978 I915_WRITE(reg, temp);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2985 } else {
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_NONE;
2988 }
2989 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2990
2991 /* wait one idle pattern time */
2992 POSTING_READ(reg);
2993 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002994
2995 /* IVB wants error correction enabled */
2996 if (IS_IVYBRIDGE(dev))
2997 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2998 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002999}
3000
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003001static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01003002{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003003 return crtc->base.enabled && crtc->active &&
3004 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01003005}
3006
Daniel Vetter01a415f2012-10-27 15:58:40 +02003007static void ivb_modeset_global_resources(struct drm_device *dev)
3008{
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *pipe_B_crtc =
3011 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3012 struct intel_crtc *pipe_C_crtc =
3013 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3014 uint32_t temp;
3015
Daniel Vetter1e833f42013-02-19 22:31:57 +01003016 /*
3017 * When everything is off disable fdi C so that we could enable fdi B
3018 * with all lanes. Note that we don't care about enabled pipes without
3019 * an enabled pch encoder.
3020 */
3021 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3022 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02003023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3025
3026 temp = I915_READ(SOUTH_CHICKEN1);
3027 temp &= ~FDI_BC_BIFURCATION_SELECT;
3028 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029 I915_WRITE(SOUTH_CHICKEN1, temp);
3030 }
3031}
3032
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003033/* The FDI link training functions for ILK/Ibexpeak. */
3034static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3035{
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003040 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003041
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03003042 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003043 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003044
Adam Jacksone1a44742010-06-25 15:32:14 -04003045 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003047 reg = FDI_RX_IMR(pipe);
3048 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003049 temp &= ~FDI_RX_SYMBOL_LOCK;
3050 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003051 I915_WRITE(reg, temp);
3052 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003053 udelay(150);
3054
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003055 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003056 reg = FDI_TX_CTL(pipe);
3057 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003058 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3059 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003060 temp &= ~FDI_LINK_TRAIN_NONE;
3061 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003062 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003063
Chris Wilson5eddb702010-09-11 13:48:45 +01003064 reg = FDI_RX_CTL(pipe);
3065 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003066 temp &= ~FDI_LINK_TRAIN_NONE;
3067 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003068 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3069
3070 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003071 udelay(150);
3072
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003073 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01003074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3075 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3076 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003077
Chris Wilson5eddb702010-09-11 13:48:45 +01003078 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003079 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003080 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082
3083 if ((temp & FDI_RX_BIT_LOCK)) {
3084 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003085 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003086 break;
3087 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003088 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003089 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003090 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003091
3092 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003093 reg = FDI_TX_CTL(pipe);
3094 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003095 temp &= ~FDI_LINK_TRAIN_NONE;
3096 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003097 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003098
Chris Wilson5eddb702010-09-11 13:48:45 +01003099 reg = FDI_RX_CTL(pipe);
3100 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003101 temp &= ~FDI_LINK_TRAIN_NONE;
3102 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003103 I915_WRITE(reg, temp);
3104
3105 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003106 udelay(150);
3107
Chris Wilson5eddb702010-09-11 13:48:45 +01003108 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003109 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003110 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003111 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112
3113 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003114 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003115 DRM_DEBUG_KMS("FDI train 2 done.\n");
3116 break;
3117 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003118 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003119 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003120 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003121
3122 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07003123
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003124}
3125
Akshay Joshi0206e352011-08-16 15:34:10 -04003126static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003127 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3128 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3129 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3130 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3131};
3132
3133/* The FDI link training functions for SNB/Cougarpoint. */
3134static void gen6_fdi_link_train(struct drm_crtc *crtc)
3135{
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05003140 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003141
Adam Jacksone1a44742010-06-25 15:32:14 -04003142 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003144 reg = FDI_RX_IMR(pipe);
3145 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003146 temp &= ~FDI_RX_SYMBOL_LOCK;
3147 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003148 I915_WRITE(reg, temp);
3149
3150 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003151 udelay(150);
3152
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003153 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003154 reg = FDI_TX_CTL(pipe);
3155 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003156 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3157 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003158 temp &= ~FDI_LINK_TRAIN_NONE;
3159 temp |= FDI_LINK_TRAIN_PATTERN_1;
3160 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161 /* SNB-B */
3162 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01003163 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003164
Daniel Vetterd74cf322012-10-26 10:58:13 +02003165 I915_WRITE(FDI_RX_MISC(pipe),
3166 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3167
Chris Wilson5eddb702010-09-11 13:48:45 +01003168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003170 if (HAS_PCH_CPT(dev)) {
3171 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3172 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3173 } else {
3174 temp &= ~FDI_LINK_TRAIN_NONE;
3175 temp |= FDI_LINK_TRAIN_PATTERN_1;
3176 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003177 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3178
3179 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003180 udelay(150);
3181
Akshay Joshi0206e352011-08-16 15:34:10 -04003182 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003183 reg = FDI_TX_CTL(pipe);
3184 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3186 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003187 I915_WRITE(reg, temp);
3188
3189 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003190 udelay(500);
3191
Sean Paulfa37d392012-03-02 12:53:39 -05003192 for (retry = 0; retry < 5; retry++) {
3193 reg = FDI_RX_IIR(pipe);
3194 temp = I915_READ(reg);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196 if (temp & FDI_RX_BIT_LOCK) {
3197 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3198 DRM_DEBUG_KMS("FDI train 1 done.\n");
3199 break;
3200 }
3201 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003202 }
Sean Paulfa37d392012-03-02 12:53:39 -05003203 if (retry < 5)
3204 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003205 }
3206 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003207 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003208
3209 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003212 temp &= ~FDI_LINK_TRAIN_NONE;
3213 temp |= FDI_LINK_TRAIN_PATTERN_2;
3214 if (IS_GEN6(dev)) {
3215 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216 /* SNB-B */
3217 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003219 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003220
Chris Wilson5eddb702010-09-11 13:48:45 +01003221 reg = FDI_RX_CTL(pipe);
3222 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003223 if (HAS_PCH_CPT(dev)) {
3224 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3225 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3226 } else {
3227 temp &= ~FDI_LINK_TRAIN_NONE;
3228 temp |= FDI_LINK_TRAIN_PATTERN_2;
3229 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003230 I915_WRITE(reg, temp);
3231
3232 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003233 udelay(150);
3234
Akshay Joshi0206e352011-08-16 15:34:10 -04003235 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003236 reg = FDI_TX_CTL(pipe);
3237 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003238 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3239 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003240 I915_WRITE(reg, temp);
3241
3242 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003243 udelay(500);
3244
Sean Paulfa37d392012-03-02 12:53:39 -05003245 for (retry = 0; retry < 5; retry++) {
3246 reg = FDI_RX_IIR(pipe);
3247 temp = I915_READ(reg);
3248 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3249 if (temp & FDI_RX_SYMBOL_LOCK) {
3250 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3251 DRM_DEBUG_KMS("FDI train 2 done.\n");
3252 break;
3253 }
3254 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003255 }
Sean Paulfa37d392012-03-02 12:53:39 -05003256 if (retry < 5)
3257 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003258 }
3259 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003260 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003261
3262 DRM_DEBUG_KMS("FDI train done.\n");
3263}
3264
Jesse Barnes357555c2011-04-28 15:09:55 -07003265/* Manual link training for Ivy Bridge A0 parts */
3266static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3267{
3268 struct drm_device *dev = crtc->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003272 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003273
3274 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275 for train result */
3276 reg = FDI_RX_IMR(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~FDI_RX_SYMBOL_LOCK;
3279 temp &= ~FDI_RX_BIT_LOCK;
3280 I915_WRITE(reg, temp);
3281
3282 POSTING_READ(reg);
3283 udelay(150);
3284
Daniel Vetter01a415f2012-10-27 15:58:40 +02003285 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286 I915_READ(FDI_RX_IIR(pipe)));
3287
Jesse Barnes139ccd32013-08-19 11:04:55 -07003288 /* Try each vswing and preemphasis setting twice before moving on */
3289 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3290 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003291 reg = FDI_TX_CTL(pipe);
3292 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003293 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3294 temp &= ~FDI_TX_ENABLE;
3295 I915_WRITE(reg, temp);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp &= ~FDI_LINK_TRAIN_AUTO;
3300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3301 temp &= ~FDI_RX_ENABLE;
3302 I915_WRITE(reg, temp);
3303
3304 /* enable CPU FDI TX and PCH FDI RX */
3305 reg = FDI_TX_CTL(pipe);
3306 temp = I915_READ(reg);
3307 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3308 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3309 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003311 temp |= snb_b_fdi_train_param[j/2];
3312 temp |= FDI_COMPOSITE_SYNC;
3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3321 temp |= FDI_COMPOSITE_SYNC;
3322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3323
3324 POSTING_READ(reg);
3325 udelay(1); /* should be 0.5us */
3326
3327 for (i = 0; i < 4; i++) {
3328 reg = FDI_RX_IIR(pipe);
3329 temp = I915_READ(reg);
3330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332 if (temp & FDI_RX_BIT_LOCK ||
3333 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3334 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3335 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3336 i);
3337 break;
3338 }
3339 udelay(1); /* should be 0.5us */
3340 }
3341 if (i == 4) {
3342 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3343 continue;
3344 }
3345
3346 /* Train 2 */
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3351 I915_WRITE(reg, temp);
3352
3353 reg = FDI_RX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003357 I915_WRITE(reg, temp);
3358
3359 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003360 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003361
Jesse Barnes139ccd32013-08-19 11:04:55 -07003362 for (i = 0; i < 4; i++) {
3363 reg = FDI_RX_IIR(pipe);
3364 temp = I915_READ(reg);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003366
Jesse Barnes139ccd32013-08-19 11:04:55 -07003367 if (temp & FDI_RX_SYMBOL_LOCK ||
3368 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3369 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3370 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3371 i);
3372 goto train_done;
3373 }
3374 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003375 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003376 if (i == 4)
3377 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003378 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003379
Jesse Barnes139ccd32013-08-19 11:04:55 -07003380train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003381 DRM_DEBUG_KMS("FDI train done.\n");
3382}
3383
Daniel Vetter88cefb62012-08-12 19:27:14 +02003384static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003385{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003386 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003387 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003388 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003389 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003390
Jesse Barnesc64e3112010-09-10 11:27:03 -07003391
Jesse Barnes0e23b992010-09-10 11:10:00 -07003392 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003393 reg = FDI_RX_CTL(pipe);
3394 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003395 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3396 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003397 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003398 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3399
3400 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003401 udelay(200);
3402
3403 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003404 temp = I915_READ(reg);
3405 I915_WRITE(reg, temp | FDI_PCDCLK);
3406
3407 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003408 udelay(200);
3409
Paulo Zanoni20749732012-11-23 15:30:38 -02003410 /* Enable CPU FDI TX PLL, always on for Ironlake */
3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
3413 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3414 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003415
Paulo Zanoni20749732012-11-23 15:30:38 -02003416 POSTING_READ(reg);
3417 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003418 }
3419}
3420
Daniel Vetter88cefb62012-08-12 19:27:14 +02003421static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3422{
3423 struct drm_device *dev = intel_crtc->base.dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 int pipe = intel_crtc->pipe;
3426 u32 reg, temp;
3427
3428 /* Switch from PCDclk to Rawclk */
3429 reg = FDI_RX_CTL(pipe);
3430 temp = I915_READ(reg);
3431 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3432
3433 /* Disable CPU FDI TX PLL */
3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
3436 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3437
3438 POSTING_READ(reg);
3439 udelay(100);
3440
3441 reg = FDI_RX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3444
3445 /* Wait for the clocks to turn off. */
3446 POSTING_READ(reg);
3447 udelay(100);
3448}
3449
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003450static void ironlake_fdi_disable(struct drm_crtc *crtc)
3451{
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455 int pipe = intel_crtc->pipe;
3456 u32 reg, temp;
3457
3458 /* disable CPU FDI tx and PCH FDI rx */
3459 reg = FDI_TX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3462 POSTING_READ(reg);
3463
3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003467 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003468 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3469
3470 POSTING_READ(reg);
3471 udelay(100);
3472
3473 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003474 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003475 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003476
3477 /* still set train pattern 1 */
3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_1;
3482 I915_WRITE(reg, temp);
3483
3484 reg = FDI_RX_CTL(pipe);
3485 temp = I915_READ(reg);
3486 if (HAS_PCH_CPT(dev)) {
3487 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3488 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3489 } else {
3490 temp &= ~FDI_LINK_TRAIN_NONE;
3491 temp |= FDI_LINK_TRAIN_PATTERN_1;
3492 }
3493 /* BPC in FDI rx is consistent with that in PIPECONF */
3494 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003495 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003496 I915_WRITE(reg, temp);
3497
3498 POSTING_READ(reg);
3499 udelay(100);
3500}
3501
Chris Wilson5dce5b932014-01-20 10:17:36 +00003502bool intel_has_pending_fb_unpin(struct drm_device *dev)
3503{
3504 struct intel_crtc *crtc;
3505
3506 /* Note that we don't need to be called with mode_config.lock here
3507 * as our list of CRTC objects is static for the lifetime of the
3508 * device and so cannot disappear as we iterate. Similarly, we can
3509 * happily treat the predicates as racy, atomic checks as userspace
3510 * cannot claim and pin a new fb without at least acquring the
3511 * struct_mutex and so serialising with us.
3512 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003513 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003514 if (atomic_read(&crtc->unpin_work_count) == 0)
3515 continue;
3516
3517 if (crtc->unpin_work)
3518 intel_wait_for_vblank(dev, crtc->pipe);
3519
3520 return true;
3521 }
3522
3523 return false;
3524}
3525
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003526static void page_flip_completed(struct intel_crtc *intel_crtc)
3527{
3528 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3529 struct intel_unpin_work *work = intel_crtc->unpin_work;
3530
3531 /* ensure that the unpin work is consistent wrt ->pending. */
3532 smp_rmb();
3533 intel_crtc->unpin_work = NULL;
3534
3535 if (work->event)
3536 drm_send_vblank_event(intel_crtc->base.dev,
3537 intel_crtc->pipe,
3538 work->event);
3539
3540 drm_crtc_vblank_put(&intel_crtc->base);
3541
3542 wake_up_all(&dev_priv->pending_flip_queue);
3543 queue_work(dev_priv->wq, &work->work);
3544
3545 trace_i915_flip_complete(intel_crtc->plane,
3546 work->pending_flip_obj);
3547}
3548
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003549void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003550{
Chris Wilson0f911282012-04-17 10:05:38 +01003551 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003552 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003553
Daniel Vetter2c10d572012-12-20 21:24:07 +01003554 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
Chris Wilson9c787942014-09-05 07:13:25 +01003555 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3556 !intel_crtc_has_pending_flip(crtc),
3557 60*HZ) == 0)) {
3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter2c10d572012-12-20 21:24:07 +01003559
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003560 spin_lock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003561 if (intel_crtc->unpin_work) {
3562 WARN_ONCE(1, "Removing stuck page flip\n");
3563 page_flip_completed(intel_crtc);
3564 }
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003565 spin_unlock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003566 }
Chris Wilson5bb61642012-09-27 21:25:58 +01003567
Chris Wilson975d5682014-08-20 13:13:34 +01003568 if (crtc->primary->fb) {
3569 mutex_lock(&dev->struct_mutex);
3570 intel_finish_fb(crtc->primary->fb);
3571 mutex_unlock(&dev->struct_mutex);
3572 }
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003573}
3574
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003575/* Program iCLKIP clock to the desired frequency */
3576static void lpt_program_iclkip(struct drm_crtc *crtc)
3577{
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003580 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003581 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3582 u32 temp;
3583
Daniel Vetter09153002012-12-12 14:06:44 +01003584 mutex_lock(&dev_priv->dpio_lock);
3585
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003586 /* It is necessary to ungate the pixclk gate prior to programming
3587 * the divisors, and gate it back when it is done.
3588 */
3589 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3590
3591 /* Disable SSCCTL */
3592 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003593 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3594 SBI_SSCCTL_DISABLE,
3595 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003596
3597 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003598 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003599 auxdiv = 1;
3600 divsel = 0x41;
3601 phaseinc = 0x20;
3602 } else {
3603 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003604 * but the adjusted_mode->crtc_clock in in KHz. To get the
3605 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003606 * convert the virtual clock precision to KHz here for higher
3607 * precision.
3608 */
3609 u32 iclk_virtual_root_freq = 172800 * 1000;
3610 u32 iclk_pi_range = 64;
3611 u32 desired_divisor, msb_divisor_value, pi_value;
3612
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003613 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003614 msb_divisor_value = desired_divisor / iclk_pi_range;
3615 pi_value = desired_divisor % iclk_pi_range;
3616
3617 auxdiv = 0;
3618 divsel = msb_divisor_value - 2;
3619 phaseinc = pi_value;
3620 }
3621
3622 /* This should not happen with any sane values */
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3624 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3625 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3626 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3627
3628 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003629 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003630 auxdiv,
3631 divsel,
3632 phasedir,
3633 phaseinc);
3634
3635 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003636 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003637 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3638 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3639 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3640 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3641 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3642 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003643 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003644
3645 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003646 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003647 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003649 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003650
3651 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003652 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003653 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003654 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003655
3656 /* Wait for initialization time */
3657 udelay(24);
3658
3659 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003660
3661 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003662}
3663
Daniel Vetter275f01b22013-05-03 11:49:47 +02003664static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3665 enum pipe pch_transcoder)
3666{
3667 struct drm_device *dev = crtc->base.dev;
3668 struct drm_i915_private *dev_priv = dev->dev_private;
3669 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3670
3671 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3672 I915_READ(HTOTAL(cpu_transcoder)));
3673 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3674 I915_READ(HBLANK(cpu_transcoder)));
3675 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3676 I915_READ(HSYNC(cpu_transcoder)));
3677
3678 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3679 I915_READ(VTOTAL(cpu_transcoder)));
3680 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3681 I915_READ(VBLANK(cpu_transcoder)));
3682 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3683 I915_READ(VSYNC(cpu_transcoder)));
3684 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3685 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3686}
3687
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003688static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3689{
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 uint32_t temp;
3692
3693 temp = I915_READ(SOUTH_CHICKEN1);
3694 if (temp & FDI_BC_BIFURCATION_SELECT)
3695 return;
3696
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3698 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3699
3700 temp |= FDI_BC_BIFURCATION_SELECT;
3701 DRM_DEBUG_KMS("enabling fdi C rx\n");
3702 I915_WRITE(SOUTH_CHICKEN1, temp);
3703 POSTING_READ(SOUTH_CHICKEN1);
3704}
3705
3706static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3707{
3708 struct drm_device *dev = intel_crtc->base.dev;
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710
3711 switch (intel_crtc->pipe) {
3712 case PIPE_A:
3713 break;
3714 case PIPE_B:
3715 if (intel_crtc->config.fdi_lanes > 2)
3716 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717 else
3718 cpt_enable_fdi_bc_bifurcation(dev);
3719
3720 break;
3721 case PIPE_C:
3722 cpt_enable_fdi_bc_bifurcation(dev);
3723
3724 break;
3725 default:
3726 BUG();
3727 }
3728}
3729
Jesse Barnesf67a5592011-01-05 10:31:48 -08003730/*
3731 * Enable PCH resources required for PCH ports:
3732 * - PCH PLLs
3733 * - FDI training & RX/TX
3734 * - update transcoder timings
3735 * - DP transcoding bits
3736 * - transcoder
3737 */
3738static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003739{
3740 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003744 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003745
Daniel Vetterab9412b2013-05-03 11:49:46 +02003746 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003747
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003748 if (IS_IVYBRIDGE(dev))
3749 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3750
Daniel Vettercd986ab2012-10-26 10:58:12 +02003751 /* Write the TU size bits before fdi link training, so that error
3752 * detection works. */
3753 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3754 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3755
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003756 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003757 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003758
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003759 /* We need to program the right clock selection before writing the pixel
3760 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003761 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003762 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003763
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003764 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003765 temp |= TRANS_DPLL_ENABLE(pipe);
3766 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003767 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003768 temp |= sel;
3769 else
3770 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003771 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003772 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003773
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003774 /* XXX: pch pll's can be enabled any time before we enable the PCH
3775 * transcoder, and we actually should do this to not upset any PCH
3776 * transcoder that already use the clock when we share it.
3777 *
3778 * Note that enable_shared_dpll tries to do the right thing, but
3779 * get_shared_dpll unconditionally resets the pll - we need that to have
3780 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003781 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003782
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003783 /* set transcoder timing, panel must allow it */
3784 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003785 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003786
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003787 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003788
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003789 /* For PCH DP, enable TRANS_DP_CTL */
Daniel Vetter0a888182014-11-03 14:37:38 +01003790 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003791 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003792 reg = TRANS_DP_CTL(pipe);
3793 temp = I915_READ(reg);
3794 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003795 TRANS_DP_SYNC_MASK |
3796 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003797 temp |= (TRANS_DP_OUTPUT_ENABLE |
3798 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003799 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003800
3801 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003802 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003803 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003804 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003805
3806 switch (intel_trans_dp_port_sel(crtc)) {
3807 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003808 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003809 break;
3810 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003811 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003812 break;
3813 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003814 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003815 break;
3816 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003817 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003818 }
3819
Chris Wilson5eddb702010-09-11 13:48:45 +01003820 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003821 }
3822
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003823 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003824}
3825
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003826static void lpt_pch_enable(struct drm_crtc *crtc)
3827{
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003831 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003832
Daniel Vetterab9412b2013-05-03 11:49:46 +02003833 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003834
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003835 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003836
Paulo Zanoni0540e482012-10-31 18:12:40 -02003837 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003838 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003839
Paulo Zanoni937bb612012-10-31 18:12:47 -02003840 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003841}
3842
Daniel Vetter716c2e52014-06-25 22:02:02 +03003843void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003844{
Daniel Vettere2b78262013-06-07 23:10:03 +02003845 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003846
3847 if (pll == NULL)
3848 return;
3849
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02003850 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02003851 WARN(1, "bad %s crtc mask\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003852 return;
3853 }
3854
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02003855 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3856 if (pll->config.crtc_mask == 0) {
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003857 WARN_ON(pll->on);
3858 WARN_ON(pll->active);
3859 }
3860
Daniel Vettera43f6e02013-06-07 23:10:32 +02003861 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003862}
3863
Daniel Vetter716c2e52014-06-25 22:02:02 +03003864struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003865{
Daniel Vettere2b78262013-06-07 23:10:03 +02003866 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003867 struct intel_shared_dpll *pll;
Daniel Vettere2b78262013-06-07 23:10:03 +02003868 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003869
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003870 if (HAS_PCH_IBX(dev_priv->dev)) {
3871 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003872 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003873 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003874
Daniel Vetter46edb022013-06-05 13:34:12 +02003875 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3876 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003877
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003878 WARN_ON(pll->new_config->crtc_mask);
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003879
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003880 goto found;
3881 }
3882
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003883 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3884 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003885
3886 /* Only want to check enabled timings first */
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003887 if (pll->new_config->crtc_mask == 0)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003888 continue;
3889
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003890 if (memcmp(&crtc->new_config->dpll_hw_state,
3891 &pll->new_config->hw_state,
3892 sizeof(pll->new_config->hw_state)) == 0) {
3893 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02003894 crtc->base.base.id, pll->name,
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003895 pll->new_config->crtc_mask,
3896 pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003897 goto found;
3898 }
3899 }
3900
3901 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003902 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3903 pll = &dev_priv->shared_dplls[i];
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003904 if (pll->new_config->crtc_mask == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003905 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3906 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003907 goto found;
3908 }
3909 }
3910
3911 return NULL;
3912
3913found:
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003914 if (pll->new_config->crtc_mask == 0)
3915 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003916
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003917 crtc->new_config->shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003918 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3919 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003920
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003921 pll->new_config->crtc_mask |= 1 << crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003922
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003923 return pll;
3924}
3925
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003926/**
3927 * intel_shared_dpll_start_config - start a new PLL staged config
3928 * @dev_priv: DRM device
3929 * @clear_pipes: mask of pipes that will have their PLLs freed
3930 *
3931 * Starts a new PLL staged config, copying the current config but
3932 * releasing the references of pipes specified in clear_pipes.
3933 */
3934static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3935 unsigned clear_pipes)
3936{
3937 struct intel_shared_dpll *pll;
3938 enum intel_dpll_id i;
3939
3940 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3941 pll = &dev_priv->shared_dplls[i];
3942
3943 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3944 GFP_KERNEL);
3945 if (!pll->new_config)
3946 goto cleanup;
3947
3948 pll->new_config->crtc_mask &= ~clear_pipes;
3949 }
3950
3951 return 0;
3952
3953cleanup:
3954 while (--i >= 0) {
3955 pll = &dev_priv->shared_dplls[i];
Ander Conselvan de Oliveiraf354d732014-11-07 14:07:41 +02003956 kfree(pll->new_config);
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003957 pll->new_config = NULL;
3958 }
3959
3960 return -ENOMEM;
3961}
3962
3963static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3964{
3965 struct intel_shared_dpll *pll;
3966 enum intel_dpll_id i;
3967
3968 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3969 pll = &dev_priv->shared_dplls[i];
3970
3971 WARN_ON(pll->new_config == &pll->config);
3972
3973 pll->config = *pll->new_config;
3974 kfree(pll->new_config);
3975 pll->new_config = NULL;
3976 }
3977}
3978
3979static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3980{
3981 struct intel_shared_dpll *pll;
3982 enum intel_dpll_id i;
3983
3984 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3985 pll = &dev_priv->shared_dplls[i];
3986
3987 WARN_ON(pll->new_config == &pll->config);
3988
3989 kfree(pll->new_config);
3990 pll->new_config = NULL;
3991 }
3992}
3993
Daniel Vettera1520312013-05-03 11:49:50 +02003994static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003995{
3996 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003997 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003998 u32 temp;
3999
4000 temp = I915_READ(dslreg);
4001 udelay(500);
4002 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07004003 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03004004 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07004005 }
4006}
4007
Jesse Barnesb074cec2013-04-25 12:55:02 -07004008static void ironlake_pfit_enable(struct intel_crtc *crtc)
4009{
4010 struct drm_device *dev = crtc->base.dev;
4011 struct drm_i915_private *dev_priv = dev->dev_private;
4012 int pipe = crtc->pipe;
4013
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004014 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07004015 /* Force use of hard-coded filter coefficients
4016 * as some pre-programmed values are broken,
4017 * e.g. x201.
4018 */
4019 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4020 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4021 PF_PIPE_SEL_IVB(pipe));
4022 else
4023 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4024 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4025 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08004026 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004027}
4028
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004029static void intel_enable_planes(struct drm_crtc *crtc)
4030{
4031 struct drm_device *dev = crtc->dev;
4032 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07004033 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004034 struct intel_plane *intel_plane;
4035
Matt Roperaf2b6532014-04-01 15:22:32 -07004036 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4037 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004038 if (intel_plane->pipe == pipe)
4039 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07004040 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004041}
4042
4043static void intel_disable_planes(struct drm_crtc *crtc)
4044{
4045 struct drm_device *dev = crtc->dev;
4046 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07004047 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004048 struct intel_plane *intel_plane;
4049
Matt Roperaf2b6532014-04-01 15:22:32 -07004050 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4051 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004052 if (intel_plane->pipe == pipe)
4053 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07004054 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004055}
4056
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004057void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004058{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004059 struct drm_device *dev = crtc->base.dev;
4060 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03004061
4062 if (!crtc->config.ips_enabled)
4063 return;
4064
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004065 /* We can only enable IPS after we enable a plane and wait for a vblank */
4066 intel_wait_for_vblank(dev, crtc->pipe);
4067
Paulo Zanonid77e4532013-09-24 13:52:55 -03004068 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004069 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004070 mutex_lock(&dev_priv->rps.hw_lock);
4071 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4072 mutex_unlock(&dev_priv->rps.hw_lock);
4073 /* Quoting Art Runyan: "its not safe to expect any particular
4074 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08004075 * mailbox." Moreover, the mailbox may return a bogus state,
4076 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004077 */
4078 } else {
4079 I915_WRITE(IPS_CTL, IPS_ENABLE);
4080 /* The bit only becomes 1 in the next vblank, so this wait here
4081 * is essentially intel_wait_for_vblank. If we don't have this
4082 * and don't wait for vblanks until the end of crtc_enable, then
4083 * the HW state readout code will complain that the expected
4084 * IPS_CTL value is not the one we read. */
4085 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4086 DRM_ERROR("Timed out waiting for IPS enable\n");
4087 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004088}
4089
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004090void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004091{
4092 struct drm_device *dev = crtc->base.dev;
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094
4095 if (!crtc->config.ips_enabled)
4096 return;
4097
4098 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004099 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004100 mutex_lock(&dev_priv->rps.hw_lock);
4101 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4102 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004103 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4104 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4105 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08004106 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004107 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08004108 POSTING_READ(IPS_CTL);
4109 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004110
4111 /* We need to wait for a vblank before we can disable the plane. */
4112 intel_wait_for_vblank(dev, crtc->pipe);
4113}
4114
4115/** Loads the palette/gamma unit for the CRTC with the prepared values */
4116static void intel_crtc_load_lut(struct drm_crtc *crtc)
4117{
4118 struct drm_device *dev = crtc->dev;
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4121 enum pipe pipe = intel_crtc->pipe;
4122 int palreg = PALETTE(pipe);
4123 int i;
4124 bool reenable_ips = false;
4125
4126 /* The clocks have to be on to load the palette. */
4127 if (!crtc->enabled || !intel_crtc->active)
4128 return;
4129
4130 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03004131 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
Paulo Zanonid77e4532013-09-24 13:52:55 -03004132 assert_dsi_pll_enabled(dev_priv);
4133 else
4134 assert_pll_enabled(dev_priv, pipe);
4135 }
4136
4137 /* use legacy palette for Ironlake */
Sonika Jindal7a1db492014-07-22 11:18:27 +05304138 if (!HAS_GMCH_DISPLAY(dev))
Paulo Zanonid77e4532013-09-24 13:52:55 -03004139 palreg = LGC_PALETTE(pipe);
4140
4141 /* Workaround : Do not read or write the pipe palette/gamma data while
4142 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4143 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02004144 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03004145 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4146 GAMMA_MODE_MODE_SPLIT)) {
4147 hsw_disable_ips(intel_crtc);
4148 reenable_ips = true;
4149 }
4150
4151 for (i = 0; i < 256; i++) {
4152 I915_WRITE(palreg + 4 * i,
4153 (intel_crtc->lut_r[i] << 16) |
4154 (intel_crtc->lut_g[i] << 8) |
4155 intel_crtc->lut_b[i]);
4156 }
4157
4158 if (reenable_ips)
4159 hsw_enable_ips(intel_crtc);
4160}
4161
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004162static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4163{
4164 if (!enable && intel_crtc->overlay) {
4165 struct drm_device *dev = intel_crtc->base.dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167
4168 mutex_lock(&dev->struct_mutex);
4169 dev_priv->mm.interruptible = false;
4170 (void) intel_overlay_switch_off(intel_crtc->overlay);
4171 dev_priv->mm.interruptible = true;
4172 mutex_unlock(&dev->struct_mutex);
4173 }
4174
4175 /* Let userspace switch the overlay on again. In most cases userspace
4176 * has to recompute where to put it anyway.
4177 */
4178}
4179
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004180static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004181{
4182 struct drm_device *dev = crtc->dev;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004185
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03004186 intel_enable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004187 intel_enable_planes(crtc);
4188 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004189 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004190
4191 hsw_enable_ips(intel_crtc);
4192
4193 mutex_lock(&dev->struct_mutex);
4194 intel_update_fbc(dev);
4195 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf99d7062014-06-19 16:01:59 +02004196
4197 /*
4198 * FIXME: Once we grow proper nuclear flip support out of this we need
4199 * to compute the mask of flip planes precisely. For the time being
4200 * consider this a flip from a NULL plane.
4201 */
4202 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004203}
4204
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004205static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004206{
4207 struct drm_device *dev = crtc->dev;
4208 struct drm_i915_private *dev_priv = dev->dev_private;
4209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4210 int pipe = intel_crtc->pipe;
4211 int plane = intel_crtc->plane;
4212
4213 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004214
4215 if (dev_priv->fbc.plane == plane)
4216 intel_disable_fbc(dev);
4217
4218 hsw_disable_ips(intel_crtc);
4219
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004220 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004221 intel_crtc_update_cursor(crtc, false);
4222 intel_disable_planes(crtc);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03004223 intel_disable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03004224
Daniel Vetterf99d7062014-06-19 16:01:59 +02004225 /*
4226 * FIXME: Once we grow proper nuclear flip support out of this we need
4227 * to compute the mask of flip planes precisely. For the time being
4228 * consider this a flip to a NULL plane.
4229 */
4230 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004231}
4232
Jesse Barnesf67a5592011-01-05 10:31:48 -08004233static void ironlake_crtc_enable(struct drm_crtc *crtc)
4234{
4235 struct drm_device *dev = crtc->dev;
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004238 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004239 int pipe = intel_crtc->pipe;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004240
Daniel Vetter08a48462012-07-02 11:43:47 +02004241 WARN_ON(!crtc->enabled);
4242
Jesse Barnesf67a5592011-01-05 10:31:48 -08004243 if (intel_crtc->active)
4244 return;
4245
Daniel Vetterb14b1052014-04-24 23:55:13 +02004246 if (intel_crtc->config.has_pch_encoder)
4247 intel_prepare_shared_dpll(intel_crtc);
4248
Daniel Vetter29407aa2014-04-24 23:55:08 +02004249 if (intel_crtc->config.has_dp_encoder)
4250 intel_dp_set_m_n(intel_crtc);
4251
4252 intel_set_pipe_timings(intel_crtc);
4253
4254 if (intel_crtc->config.has_pch_encoder) {
4255 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004256 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004257 }
4258
4259 ironlake_set_pipeconf(crtc);
4260
Jesse Barnesf67a5592011-01-05 10:31:48 -08004261 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004262
Daniel Vettera72e4c92014-09-30 10:56:47 +02004263 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4264 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni86642812013-04-12 17:57:57 -03004265
Daniel Vetterf6736a12013-06-05 13:34:30 +02004266 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02004267 if (encoder->pre_enable)
4268 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004269
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004270 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02004271 /* Note: FDI PLL enabling _must_ be done before we enable the
4272 * cpu pipes, hence this is separate from all the other fdi/pch
4273 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02004274 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02004275 } else {
4276 assert_fdi_tx_disabled(dev_priv, pipe);
4277 assert_fdi_rx_disabled(dev_priv, pipe);
4278 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004279
Jesse Barnesb074cec2013-04-25 12:55:02 -07004280 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004281
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02004282 /*
4283 * On ILK+ LUT must be loaded before the pipe is running but with
4284 * clocks enabled
4285 */
4286 intel_crtc_load_lut(crtc);
4287
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004288 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004289 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004290
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004291 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004292 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004293
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004294 for_each_encoder_on_crtc(dev, crtc, encoder)
4295 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004296
4297 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004298 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004299
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004300 assert_vblank_disabled(crtc);
4301 drm_crtc_vblank_on(crtc);
4302
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004303 intel_crtc_enable_planes(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004304}
4305
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004306/* IPS only exists on ULT machines and is tied to pipe A. */
4307static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4308{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004309 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004310}
4311
Paulo Zanonie4916942013-09-20 16:21:19 -03004312/*
4313 * This implements the workaround described in the "notes" section of the mode
4314 * set sequence documentation. When going from no pipes or single pipe to
4315 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4316 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4317 */
4318static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4319{
4320 struct drm_device *dev = crtc->base.dev;
4321 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4322
4323 /* We want to get the other_active_crtc only if there's only 1 other
4324 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004325 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004326 if (!crtc_it->active || crtc_it == crtc)
4327 continue;
4328
4329 if (other_active_crtc)
4330 return;
4331
4332 other_active_crtc = crtc_it;
4333 }
4334 if (!other_active_crtc)
4335 return;
4336
4337 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4338 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4339}
4340
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004341static void haswell_crtc_enable(struct drm_crtc *crtc)
4342{
4343 struct drm_device *dev = crtc->dev;
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4346 struct intel_encoder *encoder;
4347 int pipe = intel_crtc->pipe;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004348
4349 WARN_ON(!crtc->enabled);
4350
4351 if (intel_crtc->active)
4352 return;
4353
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004354 if (intel_crtc_to_shared_dpll(intel_crtc))
4355 intel_enable_shared_dpll(intel_crtc);
4356
Daniel Vetter229fca92014-04-24 23:55:09 +02004357 if (intel_crtc->config.has_dp_encoder)
4358 intel_dp_set_m_n(intel_crtc);
4359
4360 intel_set_pipe_timings(intel_crtc);
4361
Clint Taylorebb69c92014-09-30 10:30:22 -07004362 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4363 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4364 intel_crtc->config.pixel_multiplier - 1);
4365 }
4366
Daniel Vetter229fca92014-04-24 23:55:09 +02004367 if (intel_crtc->config.has_pch_encoder) {
4368 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004369 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02004370 }
4371
4372 haswell_set_pipeconf(crtc);
4373
4374 intel_set_pipe_csc(crtc);
4375
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004376 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004377
Daniel Vettera72e4c92014-09-30 10:56:47 +02004378 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004379 for_each_encoder_on_crtc(dev, crtc, encoder)
4380 if (encoder->pre_enable)
4381 encoder->pre_enable(encoder);
4382
Imre Deak4fe94672014-06-25 22:01:49 +03004383 if (intel_crtc->config.has_pch_encoder) {
Daniel Vettera72e4c92014-09-30 10:56:47 +02004384 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4385 true);
Imre Deak4fe94672014-06-25 22:01:49 +03004386 dev_priv->display.fdi_link_train(crtc);
4387 }
4388
Paulo Zanoni1f544382012-10-24 11:32:00 -02004389 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004390
Jesse Barnesb074cec2013-04-25 12:55:02 -07004391 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004392
4393 /*
4394 * On ILK+ LUT must be loaded before the pipe is running but with
4395 * clocks enabled
4396 */
4397 intel_crtc_load_lut(crtc);
4398
Paulo Zanoni1f544382012-10-24 11:32:00 -02004399 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004400 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004401
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004402 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004403 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004404
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004405 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004406 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004407
Dave Airlie0e32b392014-05-02 14:02:48 +10004408 if (intel_crtc->config.dp_encoder_is_mst)
4409 intel_ddi_set_vc_payload_alloc(crtc, true);
4410
Jani Nikula8807e552013-08-30 19:40:32 +03004411 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004412 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004413 intel_opregion_notify_encoder(encoder, true);
4414 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004415
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004416 assert_vblank_disabled(crtc);
4417 drm_crtc_vblank_on(crtc);
4418
Paulo Zanonie4916942013-09-20 16:21:19 -03004419 /* If we change the relative order between pipe/planes enabling, we need
4420 * to change the workaround. */
4421 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004422 intel_crtc_enable_planes(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004423}
4424
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004425static void ironlake_pfit_disable(struct intel_crtc *crtc)
4426{
4427 struct drm_device *dev = crtc->base.dev;
4428 struct drm_i915_private *dev_priv = dev->dev_private;
4429 int pipe = crtc->pipe;
4430
4431 /* To avoid upsetting the power well on haswell only disable the pfit if
4432 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004433 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004434 I915_WRITE(PF_CTL(pipe), 0);
4435 I915_WRITE(PF_WIN_POS(pipe), 0);
4436 I915_WRITE(PF_WIN_SZ(pipe), 0);
4437 }
4438}
4439
Jesse Barnes6be4a602010-09-10 10:26:01 -07004440static void ironlake_crtc_disable(struct drm_crtc *crtc)
4441{
4442 struct drm_device *dev = crtc->dev;
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004445 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004446 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004447 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004448
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004449 if (!intel_crtc->active)
4450 return;
4451
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004452 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004453
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004454 drm_crtc_vblank_off(crtc);
4455 assert_vblank_disabled(crtc);
4456
Daniel Vetterea9d7582012-07-10 10:42:52 +02004457 for_each_encoder_on_crtc(dev, crtc, encoder)
4458 encoder->disable(encoder);
4459
Daniel Vetterd925c592013-06-05 13:34:04 +02004460 if (intel_crtc->config.has_pch_encoder)
Daniel Vettera72e4c92014-09-30 10:56:47 +02004461 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
Daniel Vetterd925c592013-06-05 13:34:04 +02004462
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03004463 intel_disable_pipe(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004464
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004465 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004466
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004467 for_each_encoder_on_crtc(dev, crtc, encoder)
4468 if (encoder->post_disable)
4469 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004470
Daniel Vetterd925c592013-06-05 13:34:04 +02004471 if (intel_crtc->config.has_pch_encoder) {
4472 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004473
Daniel Vetterd925c592013-06-05 13:34:04 +02004474 ironlake_disable_pch_transcoder(dev_priv, pipe);
Daniel Vettera72e4c92014-09-30 10:56:47 +02004475 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004476
Daniel Vetterd925c592013-06-05 13:34:04 +02004477 if (HAS_PCH_CPT(dev)) {
4478 /* disable TRANS_DP_CTL */
4479 reg = TRANS_DP_CTL(pipe);
4480 temp = I915_READ(reg);
4481 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4482 TRANS_DP_PORT_SEL_MASK);
4483 temp |= TRANS_DP_PORT_SEL_NONE;
4484 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004485
Daniel Vetterd925c592013-06-05 13:34:04 +02004486 /* disable DPLL_SEL */
4487 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004488 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004489 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004490 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004491
4492 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004493 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004494
4495 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004496 }
4497
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004498 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004499 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004500
4501 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004502 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004503 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004504}
4505
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004506static void haswell_crtc_disable(struct drm_crtc *crtc)
4507{
4508 struct drm_device *dev = crtc->dev;
4509 struct drm_i915_private *dev_priv = dev->dev_private;
4510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4511 struct intel_encoder *encoder;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004512 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004513
4514 if (!intel_crtc->active)
4515 return;
4516
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004517 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004518
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004519 drm_crtc_vblank_off(crtc);
4520 assert_vblank_disabled(crtc);
4521
Jani Nikula8807e552013-08-30 19:40:32 +03004522 for_each_encoder_on_crtc(dev, crtc, encoder) {
4523 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004524 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004525 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004526
Paulo Zanoni86642812013-04-12 17:57:57 -03004527 if (intel_crtc->config.has_pch_encoder)
Daniel Vettera72e4c92014-09-30 10:56:47 +02004528 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4529 false);
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03004530 intel_disable_pipe(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004531
Ville Syrjäläa4bf2142014-08-18 21:27:34 +03004532 if (intel_crtc->config.dp_encoder_is_mst)
4533 intel_ddi_set_vc_payload_alloc(crtc, false);
4534
Paulo Zanoniad80a812012-10-24 16:06:19 -02004535 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004536
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004537 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004538
Paulo Zanoni1f544382012-10-24 11:32:00 -02004539 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004540
Daniel Vetter88adfff2013-03-28 10:42:01 +01004541 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004542 lpt_disable_pch_transcoder(dev_priv);
Daniel Vettera72e4c92014-09-30 10:56:47 +02004543 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4544 true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004545 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004546 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004547
Imre Deak97b040a2014-06-25 22:01:50 +03004548 for_each_encoder_on_crtc(dev, crtc, encoder)
4549 if (encoder->post_disable)
4550 encoder->post_disable(encoder);
4551
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004552 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004553 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004554
4555 mutex_lock(&dev->struct_mutex);
4556 intel_update_fbc(dev);
4557 mutex_unlock(&dev->struct_mutex);
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004558
4559 if (intel_crtc_to_shared_dpll(intel_crtc))
4560 intel_disable_shared_dpll(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004561}
4562
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004563static void ironlake_crtc_off(struct drm_crtc *crtc)
4564{
4565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004566 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004567}
4568
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004569
Jesse Barnes2dd24552013-04-25 12:55:01 -07004570static void i9xx_pfit_enable(struct intel_crtc *crtc)
4571{
4572 struct drm_device *dev = crtc->base.dev;
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574 struct intel_crtc_config *pipe_config = &crtc->config;
4575
Daniel Vetter328d8e82013-05-08 10:36:31 +02004576 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004577 return;
4578
Daniel Vetterc0b03412013-05-28 12:05:54 +02004579 /*
4580 * The panel fitter should only be adjusted whilst the pipe is disabled,
4581 * according to register description and PRM.
4582 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004583 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4584 assert_pipe_disabled(dev_priv, crtc->pipe);
4585
Jesse Barnesb074cec2013-04-25 12:55:02 -07004586 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4587 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004588
4589 /* Border color in case we don't scale up to the full screen. Black by
4590 * default, change to something else for debugging. */
4591 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004592}
4593
Dave Airlied05410f2014-06-05 13:22:59 +10004594static enum intel_display_power_domain port_to_power_domain(enum port port)
4595{
4596 switch (port) {
4597 case PORT_A:
4598 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4599 case PORT_B:
4600 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4601 case PORT_C:
4602 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4603 case PORT_D:
4604 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4605 default:
4606 WARN_ON_ONCE(1);
4607 return POWER_DOMAIN_PORT_OTHER;
4608 }
4609}
4610
Imre Deak77d22dc2014-03-05 16:20:52 +02004611#define for_each_power_domain(domain, mask) \
4612 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4613 if ((1 << (domain)) & (mask))
4614
Imre Deak319be8a2014-03-04 19:22:57 +02004615enum intel_display_power_domain
4616intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004617{
Imre Deak319be8a2014-03-04 19:22:57 +02004618 struct drm_device *dev = intel_encoder->base.dev;
4619 struct intel_digital_port *intel_dig_port;
4620
4621 switch (intel_encoder->type) {
4622 case INTEL_OUTPUT_UNKNOWN:
4623 /* Only DDI platforms should ever use this output type */
4624 WARN_ON_ONCE(!HAS_DDI(dev));
4625 case INTEL_OUTPUT_DISPLAYPORT:
4626 case INTEL_OUTPUT_HDMI:
4627 case INTEL_OUTPUT_EDP:
4628 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10004629 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10004630 case INTEL_OUTPUT_DP_MST:
4631 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4632 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02004633 case INTEL_OUTPUT_ANALOG:
4634 return POWER_DOMAIN_PORT_CRT;
4635 case INTEL_OUTPUT_DSI:
4636 return POWER_DOMAIN_PORT_DSI;
4637 default:
4638 return POWER_DOMAIN_PORT_OTHER;
4639 }
4640}
4641
4642static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4643{
4644 struct drm_device *dev = crtc->dev;
4645 struct intel_encoder *intel_encoder;
4646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02004648 unsigned long mask;
4649 enum transcoder transcoder;
4650
4651 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4652
4653 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4654 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Daniel Vetterfabf6e52014-05-29 14:10:22 +02004655 if (intel_crtc->config.pch_pfit.enabled ||
4656 intel_crtc->config.pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02004657 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4658
Imre Deak319be8a2014-03-04 19:22:57 +02004659 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4660 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4661
Imre Deak77d22dc2014-03-05 16:20:52 +02004662 return mask;
4663}
4664
Imre Deak77d22dc2014-03-05 16:20:52 +02004665static void modeset_update_crtc_power_domains(struct drm_device *dev)
4666{
4667 struct drm_i915_private *dev_priv = dev->dev_private;
4668 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4669 struct intel_crtc *crtc;
4670
4671 /*
4672 * First get all needed power domains, then put all unneeded, to avoid
4673 * any unnecessary toggling of the power wells.
4674 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004675 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004676 enum intel_display_power_domain domain;
4677
4678 if (!crtc->base.enabled)
4679 continue;
4680
Imre Deak319be8a2014-03-04 19:22:57 +02004681 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004682
4683 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4684 intel_display_power_get(dev_priv, domain);
4685 }
4686
Ville Syrjälä50f6e502014-11-06 14:49:12 +02004687 if (dev_priv->display.modeset_global_resources)
4688 dev_priv->display.modeset_global_resources(dev);
4689
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004690 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004691 enum intel_display_power_domain domain;
4692
4693 for_each_power_domain(domain, crtc->enabled_power_domains)
4694 intel_display_power_put(dev_priv, domain);
4695
4696 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4697 }
4698
4699 intel_display_set_init_power(dev_priv, false);
4700}
4701
Ville Syrjälädfcab172014-06-13 13:37:47 +03004702/* returns HPLL frequency in kHz */
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004703static int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004704{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004705 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004706
Jesse Barnes586f49d2013-11-04 16:06:59 -08004707 /* Obtain SKU information */
4708 mutex_lock(&dev_priv->dpio_lock);
4709 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4710 CCK_FUSE_HPLL_FREQ_MASK;
4711 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004712
Ville Syrjälädfcab172014-06-13 13:37:47 +03004713 return vco_freq[hpll_freq] * 1000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004714}
4715
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004716static void vlv_update_cdclk(struct drm_device *dev)
4717{
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719
4720 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
Ville Syrjälä43dc52c2014-10-07 17:41:20 +03004721 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004722 dev_priv->vlv_cdclk_freq);
4723
4724 /*
4725 * Program the gmbus_freq based on the cdclk frequency.
4726 * BSpec erroneously claims we should aim for 4MHz, but
4727 * in fact 1MHz is the correct frequency.
4728 */
4729 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4730}
4731
Jesse Barnes30a970c2013-11-04 13:48:12 -08004732/* Adjust CDclk dividers to allow high res or save power if possible */
4733static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4734{
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 u32 val, cmd;
4737
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03004738 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02004739
Ville Syrjälädfcab172014-06-13 13:37:47 +03004740 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08004741 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03004742 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004743 cmd = 1;
4744 else
4745 cmd = 0;
4746
4747 mutex_lock(&dev_priv->rps.hw_lock);
4748 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4749 val &= ~DSPFREQGUAR_MASK;
4750 val |= (cmd << DSPFREQGUAR_SHIFT);
4751 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4752 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4753 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4754 50)) {
4755 DRM_ERROR("timed out waiting for CDclk change\n");
4756 }
4757 mutex_unlock(&dev_priv->rps.hw_lock);
4758
Ville Syrjälädfcab172014-06-13 13:37:47 +03004759 if (cdclk == 400000) {
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03004760 u32 divider;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004761
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03004762 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004763
4764 mutex_lock(&dev_priv->dpio_lock);
4765 /* adjust cdclk divider */
4766 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Ville Syrjälä9cf33db2014-06-13 13:37:48 +03004767 val &= ~DISPLAY_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004768 val |= divider;
4769 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03004770
4771 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4772 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4773 50))
4774 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08004775 mutex_unlock(&dev_priv->dpio_lock);
4776 }
4777
4778 mutex_lock(&dev_priv->dpio_lock);
4779 /* adjust self-refresh exit latency value */
4780 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4781 val &= ~0x7f;
4782
4783 /*
4784 * For high bandwidth configs, we set a higher latency in the bunit
4785 * so that the core display fetch happens in time to avoid underruns.
4786 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03004787 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004788 val |= 4500 / 250; /* 4.5 usec */
4789 else
4790 val |= 3000 / 250; /* 3.0 usec */
4791 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4792 mutex_unlock(&dev_priv->dpio_lock);
4793
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004794 vlv_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004795}
4796
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004797static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4798{
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 u32 val, cmd;
4801
4802 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4803
4804 switch (cdclk) {
4805 case 400000:
4806 cmd = 3;
4807 break;
4808 case 333333:
4809 case 320000:
4810 cmd = 2;
4811 break;
4812 case 266667:
4813 cmd = 1;
4814 break;
4815 case 200000:
4816 cmd = 0;
4817 break;
4818 default:
4819 WARN_ON(1);
4820 return;
4821 }
4822
4823 mutex_lock(&dev_priv->rps.hw_lock);
4824 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4825 val &= ~DSPFREQGUAR_MASK_CHV;
4826 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4827 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4828 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4829 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4830 50)) {
4831 DRM_ERROR("timed out waiting for CDclk change\n");
4832 }
4833 mutex_unlock(&dev_priv->rps.hw_lock);
4834
4835 vlv_update_cdclk(dev);
4836}
4837
Jesse Barnes30a970c2013-11-04 13:48:12 -08004838static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4839 int max_pixclk)
4840{
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03004841 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004842
Ville Syrjäläd49a3402014-06-28 02:03:58 +03004843 /* FIXME: Punit isn't quite ready yet */
4844 if (IS_CHERRYVIEW(dev_priv->dev))
4845 return 400000;
4846
Jesse Barnes30a970c2013-11-04 13:48:12 -08004847 /*
4848 * Really only a few cases to deal with, as only 4 CDclks are supported:
4849 * 200MHz
4850 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004851 * 320/333MHz (depends on HPLL freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004852 * 400MHz
4853 * So we check to see whether we're above 90% of the lower bin and
4854 * adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004855 *
4856 * We seem to get an unstable or solid color picture at 200MHz.
4857 * Not sure what's wrong. For now use 200MHz only when all pipes
4858 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08004859 */
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004860 if (max_pixclk > freq_320*9/10)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004861 return 400000;
4862 else if (max_pixclk > 266667*9/10)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004863 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004864 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004865 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004866 else
4867 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004868}
4869
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004870/* compute the max pixel clock for new configuration */
4871static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004872{
4873 struct drm_device *dev = dev_priv->dev;
4874 struct intel_crtc *intel_crtc;
4875 int max_pixclk = 0;
4876
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004877 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004878 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004879 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004880 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004881 }
4882
4883 return max_pixclk;
4884}
4885
4886static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004887 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004888{
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004891 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004892
Imre Deakd60c4472014-03-27 17:45:10 +02004893 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4894 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004895 return;
4896
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004897 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004898 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004899 if (intel_crtc->base.enabled)
4900 *prepare_pipes |= (1 << intel_crtc->pipe);
4901}
4902
4903static void valleyview_modeset_global_resources(struct drm_device *dev)
4904{
4905 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004906 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004907 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4908
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004909 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4910 if (IS_CHERRYVIEW(dev))
4911 cherryview_set_cdclk(dev, req_cdclk);
4912 else
4913 valleyview_set_cdclk(dev, req_cdclk);
4914 }
Jesse Barnes30a970c2013-11-04 13:48:12 -08004915}
4916
Jesse Barnes89b667f2013-04-18 14:51:36 -07004917static void valleyview_crtc_enable(struct drm_crtc *crtc)
4918{
4919 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02004920 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4922 struct intel_encoder *encoder;
4923 int pipe = intel_crtc->pipe;
Jani Nikula23538ef2013-08-27 15:12:22 +03004924 bool is_dsi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004925
4926 WARN_ON(!crtc->enabled);
4927
4928 if (intel_crtc->active)
4929 return;
4930
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03004931 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
Shobhit Kumar8525a232014-06-25 12:20:39 +05304932
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004933 if (!is_dsi) {
4934 if (IS_CHERRYVIEW(dev))
Ville Syrjäläd288f652014-10-28 13:20:22 +02004935 chv_prepare_pll(intel_crtc, &intel_crtc->config);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004936 else
Ville Syrjäläd288f652014-10-28 13:20:22 +02004937 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004938 }
Daniel Vetter5b18e572014-04-24 23:55:06 +02004939
4940 if (intel_crtc->config.has_dp_encoder)
4941 intel_dp_set_m_n(intel_crtc);
4942
4943 intel_set_pipe_timings(intel_crtc);
4944
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004945 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947
4948 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4949 I915_WRITE(CHV_CANVAS(pipe), 0);
4950 }
4951
Daniel Vetter5b18e572014-04-24 23:55:06 +02004952 i9xx_set_pipeconf(intel_crtc);
4953
Jesse Barnes89b667f2013-04-18 14:51:36 -07004954 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004955
Daniel Vettera72e4c92014-09-30 10:56:47 +02004956 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004957
Jesse Barnes89b667f2013-04-18 14:51:36 -07004958 for_each_encoder_on_crtc(dev, crtc, encoder)
4959 if (encoder->pre_pll_enable)
4960 encoder->pre_pll_enable(encoder);
4961
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004962 if (!is_dsi) {
4963 if (IS_CHERRYVIEW(dev))
Ville Syrjäläd288f652014-10-28 13:20:22 +02004964 chv_enable_pll(intel_crtc, &intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004965 else
Ville Syrjäläd288f652014-10-28 13:20:22 +02004966 vlv_enable_pll(intel_crtc, &intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004967 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07004968
4969 for_each_encoder_on_crtc(dev, crtc, encoder)
4970 if (encoder->pre_enable)
4971 encoder->pre_enable(encoder);
4972
Jesse Barnes2dd24552013-04-25 12:55:01 -07004973 i9xx_pfit_enable(intel_crtc);
4974
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004975 intel_crtc_load_lut(crtc);
4976
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004977 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004978 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02004979
Jani Nikula50049452013-07-30 12:20:32 +03004980 for_each_encoder_on_crtc(dev, crtc, encoder)
4981 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004982
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004983 assert_vblank_disabled(crtc);
4984 drm_crtc_vblank_on(crtc);
4985
Ville Syrjälä9ab04602014-05-08 19:23:14 +03004986 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02004987
Ville Syrjälä56b80e12014-05-16 19:40:22 +03004988 /* Underruns don't raise interrupts, so check manually. */
Daniel Vettera72e4c92014-09-30 10:56:47 +02004989 i9xx_check_fifo_underruns(dev_priv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004990}
4991
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02004992static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4993{
4994 struct drm_device *dev = crtc->base.dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996
4997 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4998 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4999}
5000
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005001static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005002{
5003 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02005004 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08005005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005006 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005007 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08005008
Daniel Vetter08a48462012-07-02 11:43:47 +02005009 WARN_ON(!crtc->enabled);
5010
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005011 if (intel_crtc->active)
5012 return;
5013
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02005014 i9xx_set_pll_dividers(intel_crtc);
5015
Daniel Vetter5b18e572014-04-24 23:55:06 +02005016 if (intel_crtc->config.has_dp_encoder)
5017 intel_dp_set_m_n(intel_crtc);
5018
5019 intel_set_pipe_timings(intel_crtc);
5020
Daniel Vetter5b18e572014-04-24 23:55:06 +02005021 i9xx_set_pipeconf(intel_crtc);
5022
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005023 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01005024
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005025 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005026 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005027
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02005028 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02005029 if (encoder->pre_enable)
5030 encoder->pre_enable(encoder);
5031
Daniel Vetterf6736a12013-06-05 13:34:30 +02005032 i9xx_enable_pll(intel_crtc);
5033
Jesse Barnes2dd24552013-04-25 12:55:01 -07005034 i9xx_pfit_enable(intel_crtc);
5035
Ville Syrjälä63cbb072013-06-04 13:48:59 +03005036 intel_crtc_load_lut(crtc);
5037
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005038 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005039 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02005040
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02005041 for_each_encoder_on_crtc(dev, crtc, encoder)
5042 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005043
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005044 assert_vblank_disabled(crtc);
5045 drm_crtc_vblank_on(crtc);
5046
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005047 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02005048
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005049 /*
5050 * Gen2 reports pipe underruns whenever all planes are disabled.
5051 * So don't enable underrun reporting before at least some planes
5052 * are enabled.
5053 * FIXME: Need to fix the logic to work when we turn off all planes
5054 * but leave the pipe running.
5055 */
5056 if (IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005057 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005058
Ville Syrjälä56b80e12014-05-16 19:40:22 +03005059 /* Underruns don't raise interrupts, so check manually. */
Daniel Vettera72e4c92014-09-30 10:56:47 +02005060 i9xx_check_fifo_underruns(dev_priv);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005061}
5062
Daniel Vetter87476d62013-04-11 16:29:06 +02005063static void i9xx_pfit_disable(struct intel_crtc *crtc)
5064{
5065 struct drm_device *dev = crtc->base.dev;
5066 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02005067
5068 if (!crtc->config.gmch_pfit.control)
5069 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02005070
5071 assert_pipe_disabled(dev_priv, crtc->pipe);
5072
Daniel Vetter328d8e82013-05-08 10:36:31 +02005073 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5074 I915_READ(PFIT_CONTROL));
5075 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02005076}
5077
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005078static void i9xx_crtc_disable(struct drm_crtc *crtc)
5079{
5080 struct drm_device *dev = crtc->dev;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005083 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005084 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005085
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005086 if (!intel_crtc->active)
5087 return;
5088
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005089 /*
5090 * Gen2 reports pipe underruns whenever all planes are disabled.
5091 * So diasble underrun reporting before all the planes get disabled.
5092 * FIXME: Need to fix the logic to work when we turn off all planes
5093 * but leave the pipe running.
5094 */
5095 if (IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005096 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005097
Imre Deak564ed192014-06-13 14:54:21 +03005098 /*
5099 * Vblank time updates from the shadow to live plane control register
5100 * are blocked if the memory self-refresh mode is active at that
5101 * moment. So to make sure the plane gets truly disabled, disable
5102 * first the self-refresh mode. The self-refresh enable bit in turn
5103 * will be checked/applied by the HW only at the next frame start
5104 * event which is after the vblank start event, so we need to have a
5105 * wait-for-vblank between disabling the plane and the pipe.
5106 */
5107 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005108 intel_crtc_disable_planes(crtc);
5109
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005110 /*
5111 * On gen2 planes are double buffered but the pipe isn't, so we must
5112 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03005113 * We also need to wait on all gmch platforms because of the
5114 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005115 */
Imre Deak564ed192014-06-13 14:54:21 +03005116 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005117
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005118 drm_crtc_vblank_off(crtc);
5119 assert_vblank_disabled(crtc);
5120
5121 for_each_encoder_on_crtc(dev, crtc, encoder)
5122 encoder->disable(encoder);
5123
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03005124 intel_disable_pipe(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02005125
Daniel Vetter87476d62013-04-11 16:29:06 +02005126 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02005127
Jesse Barnes89b667f2013-04-18 14:51:36 -07005128 for_each_encoder_on_crtc(dev, crtc, encoder)
5129 if (encoder->post_disable)
5130 encoder->post_disable(encoder);
5131
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005132 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03005133 if (IS_CHERRYVIEW(dev))
5134 chv_disable_pll(dev_priv, pipe);
5135 else if (IS_VALLEYVIEW(dev))
5136 vlv_disable_pll(dev_priv, pipe);
5137 else
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03005138 i9xx_disable_pll(intel_crtc);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03005139 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005140
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005141 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005142 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005143
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005144 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03005145 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005146
Daniel Vetterefa96242014-04-24 23:55:02 +02005147 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01005148 intel_update_fbc(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02005149 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005150}
5151
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005152static void i9xx_crtc_off(struct drm_crtc *crtc)
5153{
5154}
5155
Daniel Vetter976f8a22012-07-08 22:34:21 +02005156static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5157 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005158{
5159 struct drm_device *dev = crtc->dev;
5160 struct drm_i915_master_private *master_priv;
5161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5162 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08005163
5164 if (!dev->primary->master)
5165 return;
5166
5167 master_priv = dev->primary->master->driver_priv;
5168 if (!master_priv->sarea_priv)
5169 return;
5170
Jesse Barnes79e53942008-11-07 14:24:08 -08005171 switch (pipe) {
5172 case 0:
5173 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5174 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5175 break;
5176 case 1:
5177 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5178 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5179 break;
5180 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005181 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005182 break;
5183 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005184}
5185
Borun Fub04c5bd2014-07-12 10:02:27 +05305186/* Master function to enable/disable CRTC and corresponding power wells */
5187void intel_crtc_control(struct drm_crtc *crtc, bool enable)
Chris Wilsoncdd59982010-09-08 16:30:16 +01005188{
Chris Wilsoncdd59982010-09-08 16:30:16 +01005189 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005190 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005192 enum intel_display_power_domain domain;
5193 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005194
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005195 if (enable) {
5196 if (!intel_crtc->active) {
Daniel Vettere1e9fb82014-06-25 22:02:04 +03005197 domains = get_crtc_power_domains(crtc);
5198 for_each_power_domain(domain, domains)
5199 intel_display_power_get(dev_priv, domain);
5200 intel_crtc->enabled_power_domains = domains;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005201
5202 dev_priv->display.crtc_enable(crtc);
5203 }
5204 } else {
5205 if (intel_crtc->active) {
5206 dev_priv->display.crtc_disable(crtc);
5207
Daniel Vettere1e9fb82014-06-25 22:02:04 +03005208 domains = intel_crtc->enabled_power_domains;
5209 for_each_power_domain(domain, domains)
5210 intel_display_power_put(dev_priv, domain);
5211 intel_crtc->enabled_power_domains = 0;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005212 }
5213 }
Borun Fub04c5bd2014-07-12 10:02:27 +05305214}
5215
5216/**
5217 * Sets the power management mode of the pipe and plane.
5218 */
5219void intel_crtc_update_dpms(struct drm_crtc *crtc)
5220{
5221 struct drm_device *dev = crtc->dev;
5222 struct intel_encoder *intel_encoder;
5223 bool enable = false;
5224
5225 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5226 enable |= intel_encoder->connectors_active;
5227
5228 intel_crtc_control(crtc, enable);
Daniel Vetter976f8a22012-07-08 22:34:21 +02005229
5230 intel_crtc_update_sarea(crtc, enable);
5231}
5232
Daniel Vetter976f8a22012-07-08 22:34:21 +02005233static void intel_crtc_disable(struct drm_crtc *crtc)
5234{
5235 struct drm_device *dev = crtc->dev;
5236 struct drm_connector *connector;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper2ff8fde2014-07-08 07:50:07 -07005238 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
Daniel Vettera071fa02014-06-18 23:28:09 +02005239 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005240
5241 /* crtc should still be enabled when we disable it. */
5242 WARN_ON(!crtc->enabled);
5243
5244 dev_priv->display.crtc_disable(crtc);
5245 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005246 dev_priv->display.off(crtc);
5247
Matt Roperf4510a22014-04-01 15:22:40 -07005248 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01005249 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02005250 intel_unpin_fb_obj(old_obj);
5251 i915_gem_track_fb(old_obj, NULL,
5252 INTEL_FRONTBUFFER_PRIMARY(pipe));
Chris Wilsoncdd59982010-09-08 16:30:16 +01005253 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07005254 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005255 }
5256
5257 /* Update computed state. */
5258 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5259 if (!connector->encoder || !connector->encoder->crtc)
5260 continue;
5261
5262 if (connector->encoder->crtc != crtc)
5263 continue;
5264
5265 connector->dpms = DRM_MODE_DPMS_OFF;
5266 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01005267 }
5268}
5269
Chris Wilsonea5b2132010-08-04 13:50:23 +01005270void intel_encoder_destroy(struct drm_encoder *encoder)
5271{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005272 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01005273
Chris Wilsonea5b2132010-08-04 13:50:23 +01005274 drm_encoder_cleanup(encoder);
5275 kfree(intel_encoder);
5276}
5277
Damien Lespiau92373292013-08-08 22:28:57 +01005278/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005279 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5280 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01005281static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005282{
5283 if (mode == DRM_MODE_DPMS_ON) {
5284 encoder->connectors_active = true;
5285
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005286 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005287 } else {
5288 encoder->connectors_active = false;
5289
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005290 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005291 }
5292}
5293
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005294/* Cross check the actual hw state with our own modeset state tracking (and it's
5295 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02005296static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005297{
5298 if (connector->get_hw_state(connector)) {
5299 struct intel_encoder *encoder = connector->encoder;
5300 struct drm_crtc *crtc;
5301 bool encoder_enabled;
5302 enum pipe pipe;
5303
5304 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5305 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03005306 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005307
Dave Airlie0e32b392014-05-02 14:02:48 +10005308 /* there is no real hw state for MST connectors */
5309 if (connector->mst_port)
5310 return;
5311
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005312 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5313 "wrong connector dpms state\n");
5314 WARN(connector->base.encoder != &encoder->base,
5315 "active connector not linked to encoder\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005316
Dave Airlie36cd7442014-05-02 13:44:18 +10005317 if (encoder) {
5318 WARN(!encoder->connectors_active,
5319 "encoder->connectors_active not set\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005320
Dave Airlie36cd7442014-05-02 13:44:18 +10005321 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5322 WARN(!encoder_enabled, "encoder not enabled\n");
5323 if (WARN_ON(!encoder->base.crtc))
5324 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005325
Dave Airlie36cd7442014-05-02 13:44:18 +10005326 crtc = encoder->base.crtc;
5327
5328 WARN(!crtc->enabled, "crtc not enabled\n");
5329 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5330 WARN(pipe != to_intel_crtc(crtc)->pipe,
5331 "encoder active on the wrong pipe\n");
5332 }
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005333 }
5334}
5335
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005336/* Even simpler default implementation, if there's really no special case to
5337 * consider. */
5338void intel_connector_dpms(struct drm_connector *connector, int mode)
5339{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005340 /* All the simple cases only support two dpms states. */
5341 if (mode != DRM_MODE_DPMS_ON)
5342 mode = DRM_MODE_DPMS_OFF;
5343
5344 if (mode == connector->dpms)
5345 return;
5346
5347 connector->dpms = mode;
5348
5349 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01005350 if (connector->encoder)
5351 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005352
Daniel Vetterb9805142012-08-31 17:37:33 +02005353 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005354}
5355
Daniel Vetterf0947c32012-07-02 13:10:34 +02005356/* Simple connector->get_hw_state implementation for encoders that support only
5357 * one connector and no cloning and hence the encoder state determines the state
5358 * of the connector. */
5359bool intel_connector_get_hw_state(struct intel_connector *connector)
5360{
Daniel Vetter24929352012-07-02 20:28:59 +02005361 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02005362 struct intel_encoder *encoder = connector->encoder;
5363
5364 return encoder->get_hw_state(encoder, &pipe);
5365}
5366
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005367static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5368 struct intel_crtc_config *pipe_config)
5369{
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5371 struct intel_crtc *pipe_B_crtc =
5372 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5373
5374 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5375 pipe_name(pipe), pipe_config->fdi_lanes);
5376 if (pipe_config->fdi_lanes > 4) {
5377 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5378 pipe_name(pipe), pipe_config->fdi_lanes);
5379 return false;
5380 }
5381
Paulo Zanonibafb6552013-11-02 21:07:44 -07005382 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005383 if (pipe_config->fdi_lanes > 2) {
5384 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5385 pipe_config->fdi_lanes);
5386 return false;
5387 } else {
5388 return true;
5389 }
5390 }
5391
5392 if (INTEL_INFO(dev)->num_pipes == 2)
5393 return true;
5394
5395 /* Ivybridge 3 pipe is really complicated */
5396 switch (pipe) {
5397 case PIPE_A:
5398 return true;
5399 case PIPE_B:
5400 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5401 pipe_config->fdi_lanes > 2) {
5402 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5403 pipe_name(pipe), pipe_config->fdi_lanes);
5404 return false;
5405 }
5406 return true;
5407 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005408 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005409 pipe_B_crtc->config.fdi_lanes <= 2) {
5410 if (pipe_config->fdi_lanes > 2) {
5411 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5412 pipe_name(pipe), pipe_config->fdi_lanes);
5413 return false;
5414 }
5415 } else {
5416 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5417 return false;
5418 }
5419 return true;
5420 default:
5421 BUG();
5422 }
5423}
5424
Daniel Vettere29c22c2013-02-21 00:00:16 +01005425#define RETRY 1
5426static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5427 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005428{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005429 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005430 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005431 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005432 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005433
Daniel Vettere29c22c2013-02-21 00:00:16 +01005434retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005435 /* FDI is a binary signal running at ~2.7GHz, encoding
5436 * each output octet as 10 bits. The actual frequency
5437 * is stored as a divider into a 100MHz clock, and the
5438 * mode pixel clock is stored in units of 1KHz.
5439 * Hence the bw of each lane in terms of the mode signal
5440 * is:
5441 */
5442 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5443
Damien Lespiau241bfc32013-09-25 16:45:37 +01005444 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005445
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005446 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005447 pipe_config->pipe_bpp);
5448
5449 pipe_config->fdi_lanes = lane;
5450
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005451 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005452 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005453
Daniel Vettere29c22c2013-02-21 00:00:16 +01005454 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5455 intel_crtc->pipe, pipe_config);
5456 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5457 pipe_config->pipe_bpp -= 2*3;
5458 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5459 pipe_config->pipe_bpp);
5460 needs_recompute = true;
5461 pipe_config->bw_constrained = true;
5462
5463 goto retry;
5464 }
5465
5466 if (needs_recompute)
5467 return RETRY;
5468
5469 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005470}
5471
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005472static void hsw_compute_ips_config(struct intel_crtc *crtc,
5473 struct intel_crtc_config *pipe_config)
5474{
Jani Nikulad330a952014-01-21 11:24:25 +02005475 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005476 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005477 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005478}
5479
Daniel Vettera43f6e02013-06-07 23:10:32 +02005480static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005481 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005482{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005483 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02005484 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005485 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005486
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005487 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005488 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005489 int clock_limit =
5490 dev_priv->display.get_display_clock_speed(dev);
5491
5492 /*
5493 * Enable pixel doubling when the dot clock
5494 * is > 90% of the (display) core speed.
5495 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005496 * GDG double wide on either pipe,
5497 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005498 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005499 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005500 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005501 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005502 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005503 }
5504
Damien Lespiau241bfc32013-09-25 16:45:37 +01005505 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005506 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005507 }
Chris Wilson89749352010-09-12 18:25:19 +01005508
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005509 /*
5510 * Pipe horizontal size must be even in:
5511 * - DVO ganged mode
5512 * - LVDS dual channel mode
5513 * - Double wide pipe
5514 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005515 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005516 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5517 pipe_config->pipe_src_w &= ~1;
5518
Damien Lespiau8693a822013-05-03 18:48:11 +01005519 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5520 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005521 */
5522 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5523 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005524 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005525
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005526 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005527 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005528 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005529 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5530 * for lvds. */
5531 pipe_config->pipe_bpp = 8*3;
5532 }
5533
Damien Lespiauf5adf942013-06-24 18:29:34 +01005534 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005535 hsw_compute_ips_config(crtc, pipe_config);
5536
Daniel Vetter877d48d2013-04-19 11:24:43 +02005537 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005538 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005539
Daniel Vettere29c22c2013-02-21 00:00:16 +01005540 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005541}
5542
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005543static int valleyview_get_display_clock_speed(struct drm_device *dev)
5544{
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005545 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005546 u32 val;
5547 int divider;
5548
Ville Syrjäläd49a3402014-06-28 02:03:58 +03005549 /* FIXME: Punit isn't quite ready yet */
5550 if (IS_CHERRYVIEW(dev))
5551 return 400000;
5552
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005553 if (dev_priv->hpll_freq == 0)
5554 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5555
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005556 mutex_lock(&dev_priv->dpio_lock);
5557 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5558 mutex_unlock(&dev_priv->dpio_lock);
5559
5560 divider = val & DISPLAY_FREQUENCY_VALUES;
5561
Ville Syrjälä7d007f42014-06-13 13:37:53 +03005562 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5563 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5564 "cdclk change in progress\n");
5565
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005566 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005567}
5568
Jesse Barnese70236a2009-09-21 10:42:27 -07005569static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005570{
Jesse Barnese70236a2009-09-21 10:42:27 -07005571 return 400000;
5572}
Jesse Barnes79e53942008-11-07 14:24:08 -08005573
Jesse Barnese70236a2009-09-21 10:42:27 -07005574static int i915_get_display_clock_speed(struct drm_device *dev)
5575{
5576 return 333000;
5577}
Jesse Barnes79e53942008-11-07 14:24:08 -08005578
Jesse Barnese70236a2009-09-21 10:42:27 -07005579static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5580{
5581 return 200000;
5582}
Jesse Barnes79e53942008-11-07 14:24:08 -08005583
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005584static int pnv_get_display_clock_speed(struct drm_device *dev)
5585{
5586 u16 gcfgc = 0;
5587
5588 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5589
5590 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5591 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5592 return 267000;
5593 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5594 return 333000;
5595 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5596 return 444000;
5597 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5598 return 200000;
5599 default:
5600 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5601 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5602 return 133000;
5603 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5604 return 167000;
5605 }
5606}
5607
Jesse Barnese70236a2009-09-21 10:42:27 -07005608static int i915gm_get_display_clock_speed(struct drm_device *dev)
5609{
5610 u16 gcfgc = 0;
5611
5612 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5613
5614 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005615 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005616 else {
5617 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5618 case GC_DISPLAY_CLOCK_333_MHZ:
5619 return 333000;
5620 default:
5621 case GC_DISPLAY_CLOCK_190_200_MHZ:
5622 return 190000;
5623 }
5624 }
5625}
Jesse Barnes79e53942008-11-07 14:24:08 -08005626
Jesse Barnese70236a2009-09-21 10:42:27 -07005627static int i865_get_display_clock_speed(struct drm_device *dev)
5628{
5629 return 266000;
5630}
5631
5632static int i855_get_display_clock_speed(struct drm_device *dev)
5633{
5634 u16 hpllcc = 0;
5635 /* Assume that the hardware is in the high speed state. This
5636 * should be the default.
5637 */
5638 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5639 case GC_CLOCK_133_200:
5640 case GC_CLOCK_100_200:
5641 return 200000;
5642 case GC_CLOCK_166_250:
5643 return 250000;
5644 case GC_CLOCK_100_133:
5645 return 133000;
5646 }
5647
5648 /* Shouldn't happen */
5649 return 0;
5650}
5651
5652static int i830_get_display_clock_speed(struct drm_device *dev)
5653{
5654 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005655}
5656
Zhenyu Wang2c072452009-06-05 15:38:42 +08005657static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005658intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005659{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005660 while (*num > DATA_LINK_M_N_MASK ||
5661 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005662 *num >>= 1;
5663 *den >>= 1;
5664 }
5665}
5666
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005667static void compute_m_n(unsigned int m, unsigned int n,
5668 uint32_t *ret_m, uint32_t *ret_n)
5669{
5670 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5671 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5672 intel_reduce_m_n_ratio(ret_m, ret_n);
5673}
5674
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005675void
5676intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5677 int pixel_clock, int link_clock,
5678 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005679{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005680 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005681
5682 compute_m_n(bits_per_pixel * pixel_clock,
5683 link_clock * nlanes * 8,
5684 &m_n->gmch_m, &m_n->gmch_n);
5685
5686 compute_m_n(pixel_clock, link_clock,
5687 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005688}
5689
Chris Wilsona7615032011-01-12 17:04:08 +00005690static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5691{
Jani Nikulad330a952014-01-21 11:24:25 +02005692 if (i915.panel_use_ssc >= 0)
5693 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005694 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005695 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005696}
5697
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005698static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005699{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005700 struct drm_device *dev = crtc->base.dev;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005701 struct drm_i915_private *dev_priv = dev->dev_private;
5702 int refclk;
5703
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005704 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005705 refclk = 100000;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02005706 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005707 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005708 refclk = dev_priv->vbt.lvds_ssc_freq;
5709 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005710 } else if (!IS_GEN2(dev)) {
5711 refclk = 96000;
5712 } else {
5713 refclk = 48000;
5714 }
5715
5716 return refclk;
5717}
5718
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005719static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005720{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005721 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005722}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005723
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005724static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5725{
5726 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005727}
5728
Daniel Vetterf47709a2013-03-28 10:42:02 +01005729static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005730 intel_clock_t *reduced_clock)
5731{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005732 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005733 u32 fp, fp2 = 0;
5734
5735 if (IS_PINEVIEW(dev)) {
Bob Paauwee1f234b2014-11-11 09:29:18 -08005736 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005737 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005738 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005739 } else {
Bob Paauwee1f234b2014-11-11 09:29:18 -08005740 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005741 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005742 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005743 }
5744
Bob Paauwee1f234b2014-11-11 09:29:18 -08005745 crtc->new_config->dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005746
Daniel Vetterf47709a2013-03-28 10:42:02 +01005747 crtc->lowfreq_avail = false;
Bob Paauwee1f234b2014-11-11 09:29:18 -08005748 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005749 reduced_clock && i915.powersave) {
Bob Paauwee1f234b2014-11-11 09:29:18 -08005750 crtc->new_config->dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005751 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005752 } else {
Bob Paauwee1f234b2014-11-11 09:29:18 -08005753 crtc->new_config->dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005754 }
5755}
5756
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005757static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5758 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005759{
5760 u32 reg_val;
5761
5762 /*
5763 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5764 * and set it to a reasonable value instead.
5765 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005766 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005767 reg_val &= 0xffffff00;
5768 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005769 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005770
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005771 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005772 reg_val &= 0x8cffffff;
5773 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005774 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005775
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005776 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005777 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005778 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005779
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005780 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005781 reg_val &= 0x00ffffff;
5782 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005783 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005784}
5785
Daniel Vetterb5518422013-05-03 11:49:48 +02005786static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5787 struct intel_link_m_n *m_n)
5788{
5789 struct drm_device *dev = crtc->base.dev;
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791 int pipe = crtc->pipe;
5792
Daniel Vettere3b95f12013-05-03 11:49:49 +02005793 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5794 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5795 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5796 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005797}
5798
5799static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07005800 struct intel_link_m_n *m_n,
5801 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02005802{
5803 struct drm_device *dev = crtc->base.dev;
5804 struct drm_i915_private *dev_priv = dev->dev_private;
5805 int pipe = crtc->pipe;
5806 enum transcoder transcoder = crtc->config.cpu_transcoder;
5807
5808 if (INTEL_INFO(dev)->gen >= 5) {
5809 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5810 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5811 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5812 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07005813 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5814 * for gen < 8) and if DRRS is supported (to make sure the
5815 * registers are not unnecessarily accessed).
5816 */
5817 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5818 crtc->config.has_drrs) {
5819 I915_WRITE(PIPE_DATA_M2(transcoder),
5820 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5821 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5822 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5823 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5824 }
Daniel Vetterb5518422013-05-03 11:49:48 +02005825 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005826 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5827 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5828 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5829 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005830 }
5831}
5832
Vandana Kannanf769cd22014-08-05 07:51:22 -07005833void intel_dp_set_m_n(struct intel_crtc *crtc)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005834{
5835 if (crtc->config.has_pch_encoder)
5836 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5837 else
Vandana Kannanf769cd22014-08-05 07:51:22 -07005838 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5839 &crtc->config.dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005840}
5841
Ville Syrjäläd288f652014-10-28 13:20:22 +02005842static void vlv_update_pll(struct intel_crtc *crtc,
5843 struct intel_crtc_config *pipe_config)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005844{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005845 u32 dpll, dpll_md;
5846
5847 /*
5848 * Enable DPIO clock input. We should never disable the reference
5849 * clock for pipe B, since VGA hotplug / manual detection depends
5850 * on it.
5851 */
5852 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5853 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5854 /* We should never disable this, set it here for state tracking */
5855 if (crtc->pipe == PIPE_B)
5856 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5857 dpll |= DPLL_VCO_ENABLE;
Ville Syrjäläd288f652014-10-28 13:20:22 +02005858 pipe_config->dpll_hw_state.dpll = dpll;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005859
Ville Syrjäläd288f652014-10-28 13:20:22 +02005860 dpll_md = (pipe_config->pixel_multiplier - 1)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005861 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjäläd288f652014-10-28 13:20:22 +02005862 pipe_config->dpll_hw_state.dpll_md = dpll_md;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005863}
5864
Ville Syrjäläd288f652014-10-28 13:20:22 +02005865static void vlv_prepare_pll(struct intel_crtc *crtc,
5866 const struct intel_crtc_config *pipe_config)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005867{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005868 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005869 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005870 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005871 u32 mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005872 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005873 u32 coreclk, reg_val;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005874
Daniel Vetter09153002012-12-12 14:06:44 +01005875 mutex_lock(&dev_priv->dpio_lock);
5876
Ville Syrjäläd288f652014-10-28 13:20:22 +02005877 bestn = pipe_config->dpll.n;
5878 bestm1 = pipe_config->dpll.m1;
5879 bestm2 = pipe_config->dpll.m2;
5880 bestp1 = pipe_config->dpll.p1;
5881 bestp2 = pipe_config->dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005882
Jesse Barnes89b667f2013-04-18 14:51:36 -07005883 /* See eDP HDMI DPIO driver vbios notes doc */
5884
5885 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005886 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005887 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005888
5889 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005890 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005891
5892 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005893 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005894 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005895 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005896
5897 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005898 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005899
5900 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005901 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5902 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5903 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005904 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005905
5906 /*
5907 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5908 * but we don't support that).
5909 * Note: don't use the DAC post divider as it seems unstable.
5910 */
5911 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005912 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005913
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005914 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005915 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005916
Jesse Barnes89b667f2013-04-18 14:51:36 -07005917 /* Set HBR and RBR LPF coefficients */
Ville Syrjäläd288f652014-10-28 13:20:22 +02005918 if (pipe_config->port_clock == 162000 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005919 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5920 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005921 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03005922 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005923 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005925 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005926
Daniel Vetter0a888182014-11-03 14:37:38 +01005927 if (crtc->config.has_dp_encoder) {
Jesse Barnes89b667f2013-04-18 14:51:36 -07005928 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005929 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005930 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005931 0x0df40000);
5932 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005934 0x0df70000);
5935 } else { /* HDMI or VGA */
5936 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005937 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005939 0x0df70000);
5940 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005942 0x0df40000);
5943 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005944
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005945 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005946 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005947 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5948 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
Jesse Barnes89b667f2013-04-18 14:51:36 -07005949 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005951
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005953 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005954}
5955
Ville Syrjäläd288f652014-10-28 13:20:22 +02005956static void chv_update_pll(struct intel_crtc *crtc,
5957 struct intel_crtc_config *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005958{
Ville Syrjäläd288f652014-10-28 13:20:22 +02005959 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005960 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5961 DPLL_VCO_ENABLE;
5962 if (crtc->pipe != PIPE_A)
Ville Syrjäläd288f652014-10-28 13:20:22 +02005963 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005964
Ville Syrjäläd288f652014-10-28 13:20:22 +02005965 pipe_config->dpll_hw_state.dpll_md =
5966 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005967}
5968
Ville Syrjäläd288f652014-10-28 13:20:22 +02005969static void chv_prepare_pll(struct intel_crtc *crtc,
5970 const struct intel_crtc_config *pipe_config)
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005971{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005972 struct drm_device *dev = crtc->base.dev;
5973 struct drm_i915_private *dev_priv = dev->dev_private;
5974 int pipe = crtc->pipe;
5975 int dpll_reg = DPLL(crtc->pipe);
5976 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03005977 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005978 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5979 int refclk;
5980
Ville Syrjäläd288f652014-10-28 13:20:22 +02005981 bestn = pipe_config->dpll.n;
5982 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5983 bestm1 = pipe_config->dpll.m1;
5984 bestm2 = pipe_config->dpll.m2 >> 22;
5985 bestp1 = pipe_config->dpll.p1;
5986 bestp2 = pipe_config->dpll.p2;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005987
5988 /*
5989 * Enable Refclk and SSC
5990 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005991 I915_WRITE(dpll_reg,
Ville Syrjäläd288f652014-10-28 13:20:22 +02005992 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03005993
5994 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005995
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005996 /* p1 and p2 divider */
5997 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5998 5 << DPIO_CHV_S1_DIV_SHIFT |
5999 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6000 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6001 1 << DPIO_CHV_K_DIV_SHIFT);
6002
6003 /* Feedback post-divider - m2 */
6004 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6005
6006 /* Feedback refclk divider - n and m1 */
6007 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6008 DPIO_CHV_M1_DIV_BY_2 |
6009 1 << DPIO_CHV_N_DIV_SHIFT);
6010
6011 /* M2 fraction division */
6012 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6013
6014 /* M2 fraction division enable */
6015 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6016 DPIO_CHV_FRAC_DIV_EN |
6017 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6018
6019 /* Loop filter */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006020 refclk = i9xx_get_refclk(crtc, 0);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006021 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6022 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6023 if (refclk == 100000)
6024 intcoeff = 11;
6025 else if (refclk == 38400)
6026 intcoeff = 10;
6027 else
6028 intcoeff = 9;
6029 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6030 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6031
6032 /* AFC Recal */
6033 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6034 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6035 DPIO_AFC_RECAL);
6036
6037 mutex_unlock(&dev_priv->dpio_lock);
6038}
6039
Ville Syrjäläd288f652014-10-28 13:20:22 +02006040/**
6041 * vlv_force_pll_on - forcibly enable just the PLL
6042 * @dev_priv: i915 private structure
6043 * @pipe: pipe PLL to enable
6044 * @dpll: PLL configuration
6045 *
6046 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6047 * in cases where we need the PLL enabled even when @pipe is not going to
6048 * be enabled.
6049 */
6050void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6051 const struct dpll *dpll)
6052{
6053 struct intel_crtc *crtc =
6054 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6055 struct intel_crtc_config pipe_config = {
6056 .pixel_multiplier = 1,
6057 .dpll = *dpll,
6058 };
6059
6060 if (IS_CHERRYVIEW(dev)) {
6061 chv_update_pll(crtc, &pipe_config);
6062 chv_prepare_pll(crtc, &pipe_config);
6063 chv_enable_pll(crtc, &pipe_config);
6064 } else {
6065 vlv_update_pll(crtc, &pipe_config);
6066 vlv_prepare_pll(crtc, &pipe_config);
6067 vlv_enable_pll(crtc, &pipe_config);
6068 }
6069}
6070
6071/**
6072 * vlv_force_pll_off - forcibly disable just the PLL
6073 * @dev_priv: i915 private structure
6074 * @pipe: pipe PLL to disable
6075 *
6076 * Disable the PLL for @pipe. To be used in cases where we need
6077 * the PLL enabled even when @pipe is not going to be enabled.
6078 */
6079void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6080{
6081 if (IS_CHERRYVIEW(dev))
6082 chv_disable_pll(to_i915(dev), pipe);
6083 else
6084 vlv_disable_pll(to_i915(dev), pipe);
6085}
6086
Daniel Vetterf47709a2013-03-28 10:42:02 +01006087static void i9xx_update_pll(struct intel_crtc *crtc,
6088 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006089 int num_connectors)
6090{
Daniel Vetterf47709a2013-03-28 10:42:02 +01006091 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006092 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006093 u32 dpll;
6094 bool is_sdvo;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006095 struct dpll *clock = &crtc->new_config->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006096
Daniel Vetterf47709a2013-03-28 10:42:02 +01006097 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306098
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006099 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6100 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006101
6102 dpll = DPLL_VGA_MODE_DIS;
6103
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006104 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006105 dpll |= DPLLB_MODE_LVDS;
6106 else
6107 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006108
Daniel Vetteref1b4602013-06-01 17:17:04 +02006109 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006110 dpll |= (crtc->new_config->pixel_multiplier - 1)
Daniel Vetter198a037f2013-04-19 11:14:37 +02006111 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006112 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02006113
6114 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006115 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006116
Daniel Vetter0a888182014-11-03 14:37:38 +01006117 if (crtc->new_config->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006118 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006119
6120 /* compute bitmask from p1 value */
6121 if (IS_PINEVIEW(dev))
6122 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6123 else {
6124 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6125 if (IS_G4X(dev) && reduced_clock)
6126 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6127 }
6128 switch (clock->p2) {
6129 case 5:
6130 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6131 break;
6132 case 7:
6133 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6134 break;
6135 case 10:
6136 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6137 break;
6138 case 14:
6139 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6140 break;
6141 }
6142 if (INTEL_INFO(dev)->gen >= 4)
6143 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6144
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006145 if (crtc->new_config->sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006146 dpll |= PLL_REF_INPUT_TVCLKINBC;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006147 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006148 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6149 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6150 else
6151 dpll |= PLL_REF_INPUT_DREFCLK;
6152
6153 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006154 crtc->new_config->dpll_hw_state.dpll = dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006155
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006156 if (INTEL_INFO(dev)->gen >= 4) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006157 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02006158 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006159 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006160 }
6161}
6162
Daniel Vetterf47709a2013-03-28 10:42:02 +01006163static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01006164 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006165 int num_connectors)
6166{
Daniel Vetterf47709a2013-03-28 10:42:02 +01006167 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006168 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006169 u32 dpll;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006170 struct dpll *clock = &crtc->new_config->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006171
Daniel Vetterf47709a2013-03-28 10:42:02 +01006172 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306173
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006174 dpll = DPLL_VGA_MODE_DIS;
6175
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006176 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006177 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6178 } else {
6179 if (clock->p1 == 2)
6180 dpll |= PLL_P1_DIVIDE_BY_TWO;
6181 else
6182 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6183 if (clock->p2 == 4)
6184 dpll |= PLL_P2_DIVIDE_BY_4;
6185 }
6186
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006187 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
Daniel Vetter4a33e482013-07-06 12:52:05 +02006188 dpll |= DPLL_DVO_2X_MODE;
6189
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006190 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006191 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6192 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6193 else
6194 dpll |= PLL_REF_INPUT_DREFCLK;
6195
6196 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006197 crtc->new_config->dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006198}
6199
Daniel Vetter8a654f32013-06-01 17:16:22 +02006200static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006201{
6202 struct drm_device *dev = intel_crtc->base.dev;
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006205 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02006206 struct drm_display_mode *adjusted_mode =
6207 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02006208 uint32_t crtc_vtotal, crtc_vblank_end;
6209 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006210
6211 /* We need to be careful not to changed the adjusted mode, for otherwise
6212 * the hw state checker will get angry at the mismatch. */
6213 crtc_vtotal = adjusted_mode->crtc_vtotal;
6214 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006215
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006216 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006217 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006218 crtc_vtotal -= 1;
6219 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006220
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006221 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006222 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6223 else
6224 vsyncshift = adjusted_mode->crtc_hsync_start -
6225 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02006226 if (vsyncshift < 0)
6227 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006228 }
6229
6230 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006231 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006232
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006233 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006234 (adjusted_mode->crtc_hdisplay - 1) |
6235 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006236 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006237 (adjusted_mode->crtc_hblank_start - 1) |
6238 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006239 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006240 (adjusted_mode->crtc_hsync_start - 1) |
6241 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6242
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006243 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006244 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006245 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006246 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006247 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006248 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006249 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006250 (adjusted_mode->crtc_vsync_start - 1) |
6251 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6252
Paulo Zanonib5e508d2012-10-24 11:34:43 -02006253 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6254 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6255 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6256 * bits. */
6257 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6258 (pipe == PIPE_B || pipe == PIPE_C))
6259 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6260
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006261 /* pipesrc controls the size that is scaled from, which should
6262 * always be the user's requested size.
6263 */
6264 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03006265 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6266 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006267}
6268
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006269static void intel_get_pipe_timings(struct intel_crtc *crtc,
6270 struct intel_crtc_config *pipe_config)
6271{
6272 struct drm_device *dev = crtc->base.dev;
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6275 uint32_t tmp;
6276
6277 tmp = I915_READ(HTOTAL(cpu_transcoder));
6278 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6279 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6280 tmp = I915_READ(HBLANK(cpu_transcoder));
6281 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6282 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6283 tmp = I915_READ(HSYNC(cpu_transcoder));
6284 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6285 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6286
6287 tmp = I915_READ(VTOTAL(cpu_transcoder));
6288 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6289 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6290 tmp = I915_READ(VBLANK(cpu_transcoder));
6291 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6292 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6293 tmp = I915_READ(VSYNC(cpu_transcoder));
6294 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6295 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6296
6297 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6298 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6299 pipe_config->adjusted_mode.crtc_vtotal += 1;
6300 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6301 }
6302
6303 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03006304 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6305 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6306
6307 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6308 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006309}
6310
Daniel Vetterf6a83282014-02-11 15:28:57 -08006311void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6312 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03006313{
Daniel Vetterf6a83282014-02-11 15:28:57 -08006314 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6315 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6316 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6317 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006318
Daniel Vetterf6a83282014-02-11 15:28:57 -08006319 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6320 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6321 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6322 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006323
Daniel Vetterf6a83282014-02-11 15:28:57 -08006324 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006325
Daniel Vetterf6a83282014-02-11 15:28:57 -08006326 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6327 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006328}
6329
Daniel Vetter84b046f2013-02-19 18:48:54 +01006330static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6331{
6332 struct drm_device *dev = intel_crtc->base.dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 uint32_t pipeconf;
6335
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006336 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006337
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03006338 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6339 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6340 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
Daniel Vetter67c72a12013-09-24 11:46:14 +02006341
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006342 if (intel_crtc->config.double_wide)
6343 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006344
Daniel Vetterff9ce462013-04-24 14:57:17 +02006345 /* only g4x and later have fancy bpc/dither controls */
6346 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02006347 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6348 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6349 pipeconf |= PIPECONF_DITHER_EN |
6350 PIPECONF_DITHER_TYPE_SP;
6351
6352 switch (intel_crtc->config.pipe_bpp) {
6353 case 18:
6354 pipeconf |= PIPECONF_6BPC;
6355 break;
6356 case 24:
6357 pipeconf |= PIPECONF_8BPC;
6358 break;
6359 case 30:
6360 pipeconf |= PIPECONF_10BPC;
6361 break;
6362 default:
6363 /* Case prevented by intel_choose_pipe_bpp_dither. */
6364 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01006365 }
6366 }
6367
6368 if (HAS_PIPE_CXSR(dev)) {
6369 if (intel_crtc->lowfreq_avail) {
6370 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6371 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6372 } else {
6373 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01006374 }
6375 }
6376
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006377 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6378 if (INTEL_INFO(dev)->gen < 4 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006379 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006380 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6381 else
6382 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6383 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01006384 pipeconf |= PIPECONF_PROGRESSIVE;
6385
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006386 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6387 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03006388
Daniel Vetter84b046f2013-02-19 18:48:54 +01006389 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6390 POSTING_READ(PIPECONF(intel_crtc->pipe));
6391}
6392
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +02006393static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08006394{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006395 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08006396 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholtc751ce42010-03-25 11:48:48 -07006397 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07006398 intel_clock_t clock, reduced_clock;
Daniel Vettera16af7212013-04-30 14:01:44 +02006399 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006400 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01006401 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08006402 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08006403
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006404 for_each_intel_encoder(dev, encoder) {
6405 if (encoder->new_crtc != crtc)
6406 continue;
6407
Chris Wilson5eddb702010-09-11 13:48:45 +01006408 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006409 case INTEL_OUTPUT_LVDS:
6410 is_lvds = true;
6411 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006412 case INTEL_OUTPUT_DSI:
6413 is_dsi = true;
6414 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02006415 default:
6416 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006417 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006418
Eric Anholtc751ce42010-03-25 11:48:48 -07006419 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08006420 }
6421
Jani Nikulaf2335332013-09-13 11:03:09 +03006422 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02006423 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006424
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006425 if (!crtc->new_config->clock_set) {
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006426 refclk = i9xx_get_refclk(crtc, num_connectors);
Jani Nikulaf2335332013-09-13 11:03:09 +03006427
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006428 /*
6429 * Returns a set of divisors for the desired target clock with
6430 * the given refclk, or FALSE. The returned values represent
6431 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6432 * 2) / p1 / p2.
6433 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006434 limit = intel_limit(crtc, refclk);
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006435 ok = dev_priv->display.find_dpll(limit, crtc,
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006436 crtc->new_config->port_clock,
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006437 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03006438 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006439 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6440 return -EINVAL;
6441 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006442
Jani Nikulaf2335332013-09-13 11:03:09 +03006443 if (is_lvds && dev_priv->lvds_downclock_avail) {
6444 /*
6445 * Ensure we match the reduced clock's P to the target
6446 * clock. If the clocks don't match, we can't switch
6447 * the display clock by using the FP0/FP1. In such case
6448 * we will disable the LVDS downclock feature.
6449 */
6450 has_reduced_clock =
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006451 dev_priv->display.find_dpll(limit, crtc,
Jani Nikulaf2335332013-09-13 11:03:09 +03006452 dev_priv->lvds_downclock,
6453 refclk, &clock,
6454 &reduced_clock);
6455 }
6456 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006457 crtc->new_config->dpll.n = clock.n;
6458 crtc->new_config->dpll.m1 = clock.m1;
6459 crtc->new_config->dpll.m2 = clock.m2;
6460 crtc->new_config->dpll.p1 = clock.p1;
6461 crtc->new_config->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01006462 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006463
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006464 if (IS_GEN2(dev)) {
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006465 i8xx_update_pll(crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306466 has_reduced_clock ? &reduced_clock : NULL,
6467 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006468 } else if (IS_CHERRYVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006469 chv_update_pll(crtc, crtc->new_config);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006470 } else if (IS_VALLEYVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006471 vlv_update_pll(crtc, crtc->new_config);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006472 } else {
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006473 i9xx_update_pll(crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006474 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006475 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006476 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006477
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006478 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006479}
6480
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006481static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6482 struct intel_crtc_config *pipe_config)
6483{
6484 struct drm_device *dev = crtc->base.dev;
6485 struct drm_i915_private *dev_priv = dev->dev_private;
6486 uint32_t tmp;
6487
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006488 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6489 return;
6490
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006491 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006492 if (!(tmp & PFIT_ENABLE))
6493 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006494
Daniel Vetter06922822013-07-11 13:35:40 +02006495 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006496 if (INTEL_INFO(dev)->gen < 4) {
6497 if (crtc->pipe != PIPE_B)
6498 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006499 } else {
6500 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6501 return;
6502 }
6503
Daniel Vetter06922822013-07-11 13:35:40 +02006504 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006505 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6506 if (INTEL_INFO(dev)->gen < 5)
6507 pipe_config->gmch_pfit.lvds_border_bits =
6508 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6509}
6510
Jesse Barnesacbec812013-09-20 11:29:32 -07006511static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6512 struct intel_crtc_config *pipe_config)
6513{
6514 struct drm_device *dev = crtc->base.dev;
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516 int pipe = pipe_config->cpu_transcoder;
6517 intel_clock_t clock;
6518 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006519 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006520
Shobhit Kumarf573de52014-07-30 20:32:37 +05306521 /* In case of MIPI DPLL will not even be used */
6522 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6523 return;
6524
Jesse Barnesacbec812013-09-20 11:29:32 -07006525 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006526 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006527 mutex_unlock(&dev_priv->dpio_lock);
6528
6529 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6530 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6531 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6532 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6533 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6534
Ville Syrjäläf6466282013-10-14 14:50:31 +03006535 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006536
Ville Syrjäläf6466282013-10-14 14:50:31 +03006537 /* clock.dot is the fast clock */
6538 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006539}
6540
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006541static void i9xx_get_plane_config(struct intel_crtc *crtc,
6542 struct intel_plane_config *plane_config)
6543{
6544 struct drm_device *dev = crtc->base.dev;
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6546 u32 val, base, offset;
6547 int pipe = crtc->pipe, plane = crtc->plane;
6548 int fourcc, pixel_format;
6549 int aligned_height;
6550
Dave Airlie66e514c2014-04-03 07:51:54 +10006551 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6552 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006553 DRM_DEBUG_KMS("failed to alloc fb\n");
6554 return;
6555 }
6556
6557 val = I915_READ(DSPCNTR(plane));
6558
6559 if (INTEL_INFO(dev)->gen >= 4)
6560 if (val & DISPPLANE_TILED)
6561 plane_config->tiled = true;
6562
6563 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6564 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006565 crtc->base.primary->fb->pixel_format = fourcc;
6566 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006567 drm_format_plane_cpp(fourcc, 0) * 8;
6568
6569 if (INTEL_INFO(dev)->gen >= 4) {
6570 if (plane_config->tiled)
6571 offset = I915_READ(DSPTILEOFF(plane));
6572 else
6573 offset = I915_READ(DSPLINOFF(plane));
6574 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6575 } else {
6576 base = I915_READ(DSPADDR(plane));
6577 }
6578 plane_config->base = base;
6579
6580 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006581 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6582 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006583
6584 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01006585 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006586
Dave Airlie66e514c2014-04-03 07:51:54 +10006587 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006588 plane_config->tiled);
6589
Fabian Frederick1267a262014-07-01 20:39:41 +02006590 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6591 aligned_height);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006592
6593 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006594 pipe, plane, crtc->base.primary->fb->width,
6595 crtc->base.primary->fb->height,
6596 crtc->base.primary->fb->bits_per_pixel, base,
6597 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006598 plane_config->size);
6599
6600}
6601
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006602static void chv_crtc_clock_get(struct intel_crtc *crtc,
6603 struct intel_crtc_config *pipe_config)
6604{
6605 struct drm_device *dev = crtc->base.dev;
6606 struct drm_i915_private *dev_priv = dev->dev_private;
6607 int pipe = pipe_config->cpu_transcoder;
6608 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6609 intel_clock_t clock;
6610 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6611 int refclk = 100000;
6612
6613 mutex_lock(&dev_priv->dpio_lock);
6614 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6615 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6616 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6617 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6618 mutex_unlock(&dev_priv->dpio_lock);
6619
6620 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6621 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6622 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6623 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6624 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6625
6626 chv_clock(refclk, &clock);
6627
6628 /* clock.dot is the fast clock */
6629 pipe_config->port_clock = clock.dot / 5;
6630}
6631
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006632static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6633 struct intel_crtc_config *pipe_config)
6634{
6635 struct drm_device *dev = crtc->base.dev;
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637 uint32_t tmp;
6638
Daniel Vetterf458ebb2014-09-30 10:56:39 +02006639 if (!intel_display_power_is_enabled(dev_priv,
6640 POWER_DOMAIN_PIPE(crtc->pipe)))
Imre Deakb5482bd2014-03-05 16:20:55 +02006641 return false;
6642
Daniel Vettere143a212013-07-04 12:01:15 +02006643 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006644 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006645
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006646 tmp = I915_READ(PIPECONF(crtc->pipe));
6647 if (!(tmp & PIPECONF_ENABLE))
6648 return false;
6649
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006650 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6651 switch (tmp & PIPECONF_BPC_MASK) {
6652 case PIPECONF_6BPC:
6653 pipe_config->pipe_bpp = 18;
6654 break;
6655 case PIPECONF_8BPC:
6656 pipe_config->pipe_bpp = 24;
6657 break;
6658 case PIPECONF_10BPC:
6659 pipe_config->pipe_bpp = 30;
6660 break;
6661 default:
6662 break;
6663 }
6664 }
6665
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006666 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6667 pipe_config->limited_color_range = true;
6668
Ville Syrjälä282740f2013-09-04 18:30:03 +03006669 if (INTEL_INFO(dev)->gen < 4)
6670 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6671
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006672 intel_get_pipe_timings(crtc, pipe_config);
6673
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006674 i9xx_get_pfit_config(crtc, pipe_config);
6675
Daniel Vetter6c49f242013-06-06 12:45:25 +02006676 if (INTEL_INFO(dev)->gen >= 4) {
6677 tmp = I915_READ(DPLL_MD(crtc->pipe));
6678 pipe_config->pixel_multiplier =
6679 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6680 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006681 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006682 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6683 tmp = I915_READ(DPLL(crtc->pipe));
6684 pipe_config->pixel_multiplier =
6685 ((tmp & SDVO_MULTIPLIER_MASK)
6686 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6687 } else {
6688 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6689 * port and will be fixed up in the encoder->get_config
6690 * function. */
6691 pipe_config->pixel_multiplier = 1;
6692 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006693 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6694 if (!IS_VALLEYVIEW(dev)) {
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03006695 /*
6696 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6697 * on 830. Filter it out here so that we don't
6698 * report errors due to that.
6699 */
6700 if (IS_I830(dev))
6701 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6702
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006703 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6704 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006705 } else {
6706 /* Mask out read-only status bits. */
6707 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6708 DPLL_PORTC_READY_MASK |
6709 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006710 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006711
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006712 if (IS_CHERRYVIEW(dev))
6713 chv_crtc_clock_get(crtc, pipe_config);
6714 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006715 vlv_crtc_clock_get(crtc, pipe_config);
6716 else
6717 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006718
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006719 return true;
6720}
6721
Paulo Zanonidde86e22012-12-01 12:04:25 -02006722static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006723{
6724 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006725 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006726 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006727 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006728 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006729 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006730 bool has_ck505 = false;
6731 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006732
6733 /* We need to take the global config into account */
Damien Lespiaub2784e12014-08-05 11:29:37 +01006734 for_each_intel_encoder(dev, encoder) {
Keith Packard199e5d72011-09-22 12:01:57 -07006735 switch (encoder->type) {
6736 case INTEL_OUTPUT_LVDS:
6737 has_panel = true;
6738 has_lvds = true;
6739 break;
6740 case INTEL_OUTPUT_EDP:
6741 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006742 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006743 has_cpu_edp = true;
6744 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02006745 default:
6746 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006747 }
6748 }
6749
Keith Packard99eb6a02011-09-26 14:29:12 -07006750 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006751 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006752 can_ssc = has_ck505;
6753 } else {
6754 has_ck505 = false;
6755 can_ssc = true;
6756 }
6757
Imre Deak2de69052013-05-08 13:14:04 +03006758 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6759 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006760
6761 /* Ironlake: try to setup display ref clock before DPLL
6762 * enabling. This is only under driver's control after
6763 * PCH B stepping, previous chipset stepping should be
6764 * ignoring this setting.
6765 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006766 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006767
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006768 /* As we must carefully and slowly disable/enable each source in turn,
6769 * compute the final state we want first and check if we need to
6770 * make any changes at all.
6771 */
6772 final = val;
6773 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006774 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006775 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006776 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006777 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6778
6779 final &= ~DREF_SSC_SOURCE_MASK;
6780 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6781 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006782
Keith Packard199e5d72011-09-22 12:01:57 -07006783 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006784 final |= DREF_SSC_SOURCE_ENABLE;
6785
6786 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6787 final |= DREF_SSC1_ENABLE;
6788
6789 if (has_cpu_edp) {
6790 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6791 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6792 else
6793 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6794 } else
6795 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6796 } else {
6797 final |= DREF_SSC_SOURCE_DISABLE;
6798 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6799 }
6800
6801 if (final == val)
6802 return;
6803
6804 /* Always enable nonspread source */
6805 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6806
6807 if (has_ck505)
6808 val |= DREF_NONSPREAD_CK505_ENABLE;
6809 else
6810 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6811
6812 if (has_panel) {
6813 val &= ~DREF_SSC_SOURCE_MASK;
6814 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006815
Keith Packard199e5d72011-09-22 12:01:57 -07006816 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006817 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006818 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006819 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006820 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006821 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006822
6823 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006824 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006825 POSTING_READ(PCH_DREF_CONTROL);
6826 udelay(200);
6827
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006828 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006829
6830 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006831 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006832 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006833 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006834 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006835 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006836 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006837 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006838 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006839
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006840 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006841 POSTING_READ(PCH_DREF_CONTROL);
6842 udelay(200);
6843 } else {
6844 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6845
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006846 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006847
6848 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006849 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006850
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006851 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006852 POSTING_READ(PCH_DREF_CONTROL);
6853 udelay(200);
6854
6855 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006856 val &= ~DREF_SSC_SOURCE_MASK;
6857 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006858
6859 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006860 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006861
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006862 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006863 POSTING_READ(PCH_DREF_CONTROL);
6864 udelay(200);
6865 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006866
6867 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006868}
6869
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006870static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006871{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006872 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006873
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006874 tmp = I915_READ(SOUTH_CHICKEN2);
6875 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6876 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006877
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006878 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6879 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6880 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006881
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006882 tmp = I915_READ(SOUTH_CHICKEN2);
6883 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6884 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006885
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006886 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6887 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6888 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006889}
6890
6891/* WaMPhyProgramming:hsw */
6892static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6893{
6894 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006895
6896 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6897 tmp &= ~(0xFF << 24);
6898 tmp |= (0x12 << 24);
6899 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6900
Paulo Zanonidde86e22012-12-01 12:04:25 -02006901 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6902 tmp |= (1 << 11);
6903 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6904
6905 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6906 tmp |= (1 << 11);
6907 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6908
Paulo Zanonidde86e22012-12-01 12:04:25 -02006909 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6910 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6911 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6912
6913 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6914 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6915 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6916
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006917 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6918 tmp &= ~(7 << 13);
6919 tmp |= (5 << 13);
6920 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006921
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006922 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6923 tmp &= ~(7 << 13);
6924 tmp |= (5 << 13);
6925 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006926
6927 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6928 tmp &= ~0xFF;
6929 tmp |= 0x1C;
6930 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6931
6932 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6933 tmp &= ~0xFF;
6934 tmp |= 0x1C;
6935 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6936
6937 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6938 tmp &= ~(0xFF << 16);
6939 tmp |= (0x1C << 16);
6940 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6941
6942 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6943 tmp &= ~(0xFF << 16);
6944 tmp |= (0x1C << 16);
6945 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6946
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006947 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6948 tmp |= (1 << 27);
6949 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006950
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006951 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6952 tmp |= (1 << 27);
6953 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006954
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006955 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6956 tmp &= ~(0xF << 28);
6957 tmp |= (4 << 28);
6958 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006959
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006960 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6961 tmp &= ~(0xF << 28);
6962 tmp |= (4 << 28);
6963 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006964}
6965
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006966/* Implements 3 different sequences from BSpec chapter "Display iCLK
6967 * Programming" based on the parameters passed:
6968 * - Sequence to enable CLKOUT_DP
6969 * - Sequence to enable CLKOUT_DP without spread
6970 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6971 */
6972static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6973 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006974{
6975 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006976 uint32_t reg, tmp;
6977
6978 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6979 with_spread = true;
6980 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6981 with_fdi, "LP PCH doesn't have FDI\n"))
6982 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006983
6984 mutex_lock(&dev_priv->dpio_lock);
6985
6986 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6987 tmp &= ~SBI_SSCCTL_DISABLE;
6988 tmp |= SBI_SSCCTL_PATHALT;
6989 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6990
6991 udelay(24);
6992
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006993 if (with_spread) {
6994 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6995 tmp &= ~SBI_SSCCTL_PATHALT;
6996 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006997
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006998 if (with_fdi) {
6999 lpt_reset_fdi_mphy(dev_priv);
7000 lpt_program_fdi_mphy(dev_priv);
7001 }
7002 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02007003
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03007004 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7005 SBI_GEN0 : SBI_DBUFF0;
7006 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7007 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7008 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01007009
7010 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02007011}
7012
Paulo Zanoni47701c32013-07-23 11:19:25 -03007013/* Sequence to disable CLKOUT_DP */
7014static void lpt_disable_clkout_dp(struct drm_device *dev)
7015{
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7017 uint32_t reg, tmp;
7018
7019 mutex_lock(&dev_priv->dpio_lock);
7020
7021 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7022 SBI_GEN0 : SBI_DBUFF0;
7023 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7024 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7025 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7026
7027 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7028 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7029 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7030 tmp |= SBI_SSCCTL_PATHALT;
7031 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7032 udelay(32);
7033 }
7034 tmp |= SBI_SSCCTL_DISABLE;
7035 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7036 }
7037
7038 mutex_unlock(&dev_priv->dpio_lock);
7039}
7040
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007041static void lpt_init_pch_refclk(struct drm_device *dev)
7042{
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007043 struct intel_encoder *encoder;
7044 bool has_vga = false;
7045
Damien Lespiaub2784e12014-08-05 11:29:37 +01007046 for_each_intel_encoder(dev, encoder) {
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007047 switch (encoder->type) {
7048 case INTEL_OUTPUT_ANALOG:
7049 has_vga = true;
7050 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007051 default:
7052 break;
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007053 }
7054 }
7055
Paulo Zanoni47701c32013-07-23 11:19:25 -03007056 if (has_vga)
7057 lpt_enable_clkout_dp(dev, true, true);
7058 else
7059 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007060}
7061
Paulo Zanonidde86e22012-12-01 12:04:25 -02007062/*
7063 * Initialize reference clocks when the driver loads
7064 */
7065void intel_init_pch_refclk(struct drm_device *dev)
7066{
7067 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7068 ironlake_init_pch_refclk(dev);
7069 else if (HAS_PCH_LPT(dev))
7070 lpt_init_pch_refclk(dev);
7071}
7072
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007073static int ironlake_get_refclk(struct drm_crtc *crtc)
7074{
7075 struct drm_device *dev = crtc->dev;
7076 struct drm_i915_private *dev_priv = dev->dev_private;
7077 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007078 int num_connectors = 0;
7079 bool is_lvds = false;
7080
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007081 for_each_intel_encoder(dev, encoder) {
7082 if (encoder->new_crtc != to_intel_crtc(crtc))
7083 continue;
7084
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007085 switch (encoder->type) {
7086 case INTEL_OUTPUT_LVDS:
7087 is_lvds = true;
7088 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007089 default:
7090 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007091 }
7092 num_connectors++;
7093 }
7094
7095 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007096 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03007097 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007098 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007099 }
7100
7101 return 120000;
7102}
7103
Daniel Vetter6ff93602013-04-19 11:24:36 +02007104static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03007105{
7106 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7108 int pipe = intel_crtc->pipe;
7109 uint32_t val;
7110
Daniel Vetter78114072013-06-13 00:54:57 +02007111 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03007112
Daniel Vetter965e0c42013-03-27 00:44:57 +01007113 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03007114 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007115 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007116 break;
7117 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007118 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007119 break;
7120 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007121 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007122 break;
7123 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007124 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007125 break;
7126 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03007127 /* Case prevented by intel_choose_pipe_bpp_dither. */
7128 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03007129 }
7130
Daniel Vetterd8b32242013-04-25 17:54:44 +02007131 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03007132 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7133
Daniel Vetter6ff93602013-04-19 11:24:36 +02007134 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03007135 val |= PIPECONF_INTERLACED_ILK;
7136 else
7137 val |= PIPECONF_PROGRESSIVE;
7138
Daniel Vetter50f3b012013-03-27 00:44:56 +01007139 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02007140 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02007141
Paulo Zanonic8203562012-09-12 10:06:29 -03007142 I915_WRITE(PIPECONF(pipe), val);
7143 POSTING_READ(PIPECONF(pipe));
7144}
7145
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007146/*
7147 * Set up the pipe CSC unit.
7148 *
7149 * Currently only full range RGB to limited range RGB conversion
7150 * is supported, but eventually this should handle various
7151 * RGB<->YCbCr scenarios as well.
7152 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01007153static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007154{
7155 struct drm_device *dev = crtc->dev;
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158 int pipe = intel_crtc->pipe;
7159 uint16_t coeff = 0x7800; /* 1.0 */
7160
7161 /*
7162 * TODO: Check what kind of values actually come out of the pipe
7163 * with these coeff/postoff values and adjust to get the best
7164 * accuracy. Perhaps we even need to take the bpc value into
7165 * consideration.
7166 */
7167
Daniel Vetter50f3b012013-03-27 00:44:56 +01007168 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007169 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7170
7171 /*
7172 * GY/GU and RY/RU should be the other way around according
7173 * to BSpec, but reality doesn't agree. Just set them up in
7174 * a way that results in the correct picture.
7175 */
7176 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7177 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7178
7179 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7180 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7181
7182 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7183 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7184
7185 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7186 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7187 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7188
7189 if (INTEL_INFO(dev)->gen > 6) {
7190 uint16_t postoff = 0;
7191
Daniel Vetter50f3b012013-03-27 00:44:56 +01007192 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02007193 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007194
7195 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7196 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7197 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7198
7199 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7200 } else {
7201 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7202
Daniel Vetter50f3b012013-03-27 00:44:56 +01007203 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007204 mode |= CSC_BLACK_SCREEN_OFFSET;
7205
7206 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7207 }
7208}
7209
Daniel Vetter6ff93602013-04-19 11:24:36 +02007210static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007211{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007212 struct drm_device *dev = crtc->dev;
7213 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007215 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02007216 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007217 uint32_t val;
7218
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02007219 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007220
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007221 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007222 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7223
Daniel Vetter6ff93602013-04-19 11:24:36 +02007224 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007225 val |= PIPECONF_INTERLACED_ILK;
7226 else
7227 val |= PIPECONF_PROGRESSIVE;
7228
Paulo Zanoni702e7a52012-10-23 18:29:59 -02007229 I915_WRITE(PIPECONF(cpu_transcoder), val);
7230 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02007231
7232 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7233 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007234
Satheeshakrishna M3cdf1222014-04-08 15:46:53 +05307235 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007236 val = 0;
7237
7238 switch (intel_crtc->config.pipe_bpp) {
7239 case 18:
7240 val |= PIPEMISC_DITHER_6_BPC;
7241 break;
7242 case 24:
7243 val |= PIPEMISC_DITHER_8_BPC;
7244 break;
7245 case 30:
7246 val |= PIPEMISC_DITHER_10_BPC;
7247 break;
7248 case 36:
7249 val |= PIPEMISC_DITHER_12_BPC;
7250 break;
7251 default:
7252 /* Case prevented by pipe_config_set_bpp. */
7253 BUG();
7254 }
7255
7256 if (intel_crtc->config.dither)
7257 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7258
7259 I915_WRITE(PIPEMISC(pipe), val);
7260 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007261}
7262
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007263static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007264 intel_clock_t *clock,
7265 bool *has_reduced_clock,
7266 intel_clock_t *reduced_clock)
7267{
7268 struct drm_device *dev = crtc->dev;
7269 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007271 int refclk;
7272 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02007273 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007274
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007275 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007276
7277 refclk = ironlake_get_refclk(crtc);
7278
7279 /*
7280 * Returns a set of divisors for the desired target clock with the given
7281 * refclk, or FALSE. The returned values represent the clock equation:
7282 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7283 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007284 limit = intel_limit(intel_crtc, refclk);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007285 ret = dev_priv->display.find_dpll(limit, intel_crtc,
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007286 intel_crtc->new_config->port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02007287 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007288 if (!ret)
7289 return false;
7290
7291 if (is_lvds && dev_priv->lvds_downclock_avail) {
7292 /*
7293 * Ensure we match the reduced clock's P to the target clock.
7294 * If the clocks don't match, we can't switch the display clock
7295 * by using the FP0/FP1. In such case we will disable the LVDS
7296 * downclock feature.
7297 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02007298 *has_reduced_clock =
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007299 dev_priv->display.find_dpll(limit, intel_crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +02007300 dev_priv->lvds_downclock,
7301 refclk, clock,
7302 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007303 }
7304
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007305 return true;
7306}
7307
Paulo Zanonid4b19312012-11-29 11:29:32 -02007308int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7309{
7310 /*
7311 * Account for spread spectrum to avoid
7312 * oversubscribing the link. Max center spread
7313 * is 2.5%; use 5% for safety's sake.
7314 */
7315 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02007316 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02007317}
7318
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007319static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02007320{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007321 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007322}
7323
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007324static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007325 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007326 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007327{
7328 struct drm_crtc *crtc = &intel_crtc->base;
7329 struct drm_device *dev = crtc->dev;
7330 struct drm_i915_private *dev_priv = dev->dev_private;
7331 struct intel_encoder *intel_encoder;
7332 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01007333 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02007334 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007335
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007336 for_each_intel_encoder(dev, intel_encoder) {
7337 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7338 continue;
7339
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007340 switch (intel_encoder->type) {
7341 case INTEL_OUTPUT_LVDS:
7342 is_lvds = true;
7343 break;
7344 case INTEL_OUTPUT_SDVO:
7345 case INTEL_OUTPUT_HDMI:
7346 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007347 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007348 default:
7349 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007350 }
7351
7352 num_connectors++;
7353 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007354
Chris Wilsonc1858122010-12-03 21:35:48 +00007355 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07007356 factor = 21;
7357 if (is_lvds) {
7358 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007359 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02007360 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07007361 factor = 25;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007362 } else if (intel_crtc->new_config->sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07007363 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00007364
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007365 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02007366 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00007367
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007368 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7369 *fp2 |= FP_CB_TUNE;
7370
Chris Wilson5eddb702010-09-11 13:48:45 +01007371 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08007372
Eric Anholta07d6782011-03-30 13:01:08 -07007373 if (is_lvds)
7374 dpll |= DPLLB_MODE_LVDS;
7375 else
7376 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007377
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007378 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02007379 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007380
7381 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007382 dpll |= DPLL_SDVO_HIGH_SPEED;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007383 if (intel_crtc->new_config->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007384 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08007385
Eric Anholta07d6782011-03-30 13:01:08 -07007386 /* compute bitmask from p1 value */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007387 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007388 /* also FPA1 */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007389 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007390
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007391 switch (intel_crtc->new_config->dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07007392 case 5:
7393 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7394 break;
7395 case 7:
7396 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7397 break;
7398 case 10:
7399 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7400 break;
7401 case 14:
7402 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7403 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007404 }
7405
Daniel Vetterb4c09f32013-04-30 14:01:42 +02007406 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05007407 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08007408 else
7409 dpll |= PLL_REF_INPUT_DREFCLK;
7410
Daniel Vetter959e16d2013-06-05 13:34:21 +02007411 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007412}
7413
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02007414static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08007415{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007416 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007417 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007418 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03007419 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01007420 bool is_lvds = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007421 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007422
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007423 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
Jesse Barnes79e53942008-11-07 14:24:08 -08007424
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007425 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7426 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7427
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007428 ok = ironlake_compute_clocks(&crtc->base, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007429 &has_reduced_clock, &reduced_clock);
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007430 if (!ok && !crtc->new_config->clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007431 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7432 return -EINVAL;
7433 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01007434 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007435 if (!crtc->new_config->clock_set) {
7436 crtc->new_config->dpll.n = clock.n;
7437 crtc->new_config->dpll.m1 = clock.m1;
7438 crtc->new_config->dpll.m2 = clock.m2;
7439 crtc->new_config->dpll.p1 = clock.p1;
7440 crtc->new_config->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01007441 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007442
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007443 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007444 if (crtc->new_config->has_pch_encoder) {
7445 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007446 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007447 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007448
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007449 dpll = ironlake_compute_dpll(crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007450 &fp, &reduced_clock,
7451 has_reduced_clock ? &fp2 : NULL);
7452
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007453 crtc->new_config->dpll_hw_state.dpll = dpll;
7454 crtc->new_config->dpll_hw_state.fp0 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007455 if (has_reduced_clock)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007456 crtc->new_config->dpll_hw_state.fp1 = fp2;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007457 else
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007458 crtc->new_config->dpll_hw_state.fp1 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007459
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007460 pll = intel_get_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007461 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03007462 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007463 pipe_name(crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07007464 return -EINVAL;
7465 }
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02007466 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007467
Jani Nikulad330a952014-01-21 11:24:25 +02007468 if (is_lvds && has_reduced_clock && i915.powersave)
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007469 crtc->lowfreq_avail = true;
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007470 else
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007471 crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007472
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007473 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007474}
7475
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007476static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7477 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007478{
7479 struct drm_device *dev = crtc->base.dev;
7480 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007481 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007482
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007483 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7484 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7485 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7486 & ~TU_SIZE_MASK;
7487 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7488 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7489 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7490}
7491
7492static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7493 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007494 struct intel_link_m_n *m_n,
7495 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007496{
7497 struct drm_device *dev = crtc->base.dev;
7498 struct drm_i915_private *dev_priv = dev->dev_private;
7499 enum pipe pipe = crtc->pipe;
7500
7501 if (INTEL_INFO(dev)->gen >= 5) {
7502 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7503 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7504 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7505 & ~TU_SIZE_MASK;
7506 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7507 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7508 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007509 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7510 * gen < 8) and if DRRS is supported (to make sure the
7511 * registers are not unnecessarily read).
7512 */
7513 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7514 crtc->config.has_drrs) {
7515 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7516 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7517 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7518 & ~TU_SIZE_MASK;
7519 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7520 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7521 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7522 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007523 } else {
7524 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7525 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7526 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7527 & ~TU_SIZE_MASK;
7528 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7529 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7530 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7531 }
7532}
7533
7534void intel_dp_get_m_n(struct intel_crtc *crtc,
7535 struct intel_crtc_config *pipe_config)
7536{
7537 if (crtc->config.has_pch_encoder)
7538 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7539 else
7540 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007541 &pipe_config->dp_m_n,
7542 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007543}
7544
Daniel Vetter72419202013-04-04 13:28:53 +02007545static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7546 struct intel_crtc_config *pipe_config)
7547{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007548 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007549 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02007550}
7551
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007552static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7553 struct intel_crtc_config *pipe_config)
7554{
7555 struct drm_device *dev = crtc->base.dev;
7556 struct drm_i915_private *dev_priv = dev->dev_private;
7557 uint32_t tmp;
7558
7559 tmp = I915_READ(PF_CTL(crtc->pipe));
7560
7561 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007562 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007563 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7564 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007565
7566 /* We currently do not free assignements of panel fitters on
7567 * ivb/hsw (since we don't use the higher upscaling modes which
7568 * differentiates them) so just WARN about this case for now. */
7569 if (IS_GEN7(dev)) {
7570 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7571 PF_PIPE_SEL_IVB(crtc->pipe));
7572 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007573 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007574}
7575
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007576static void ironlake_get_plane_config(struct intel_crtc *crtc,
7577 struct intel_plane_config *plane_config)
7578{
7579 struct drm_device *dev = crtc->base.dev;
7580 struct drm_i915_private *dev_priv = dev->dev_private;
7581 u32 val, base, offset;
7582 int pipe = crtc->pipe, plane = crtc->plane;
7583 int fourcc, pixel_format;
7584 int aligned_height;
7585
Dave Airlie66e514c2014-04-03 07:51:54 +10007586 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7587 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007588 DRM_DEBUG_KMS("failed to alloc fb\n");
7589 return;
7590 }
7591
7592 val = I915_READ(DSPCNTR(plane));
7593
7594 if (INTEL_INFO(dev)->gen >= 4)
7595 if (val & DISPPLANE_TILED)
7596 plane_config->tiled = true;
7597
7598 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7599 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007600 crtc->base.primary->fb->pixel_format = fourcc;
7601 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007602 drm_format_plane_cpp(fourcc, 0) * 8;
7603
7604 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7605 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7606 offset = I915_READ(DSPOFFSET(plane));
7607 } else {
7608 if (plane_config->tiled)
7609 offset = I915_READ(DSPTILEOFF(plane));
7610 else
7611 offset = I915_READ(DSPLINOFF(plane));
7612 }
7613 plane_config->base = base;
7614
7615 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007616 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7617 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007618
7619 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01007620 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007621
Dave Airlie66e514c2014-04-03 07:51:54 +10007622 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007623 plane_config->tiled);
7624
Fabian Frederick1267a262014-07-01 20:39:41 +02007625 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7626 aligned_height);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007627
7628 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007629 pipe, plane, crtc->base.primary->fb->width,
7630 crtc->base.primary->fb->height,
7631 crtc->base.primary->fb->bits_per_pixel, base,
7632 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007633 plane_config->size);
7634}
7635
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007636static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7637 struct intel_crtc_config *pipe_config)
7638{
7639 struct drm_device *dev = crtc->base.dev;
7640 struct drm_i915_private *dev_priv = dev->dev_private;
7641 uint32_t tmp;
7642
Daniel Vetterf458ebb2014-09-30 10:56:39 +02007643 if (!intel_display_power_is_enabled(dev_priv,
7644 POWER_DOMAIN_PIPE(crtc->pipe)))
Paulo Zanoni930e8c92014-07-04 13:38:34 -03007645 return false;
7646
Daniel Vettere143a212013-07-04 12:01:15 +02007647 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007648 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007649
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007650 tmp = I915_READ(PIPECONF(crtc->pipe));
7651 if (!(tmp & PIPECONF_ENABLE))
7652 return false;
7653
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007654 switch (tmp & PIPECONF_BPC_MASK) {
7655 case PIPECONF_6BPC:
7656 pipe_config->pipe_bpp = 18;
7657 break;
7658 case PIPECONF_8BPC:
7659 pipe_config->pipe_bpp = 24;
7660 break;
7661 case PIPECONF_10BPC:
7662 pipe_config->pipe_bpp = 30;
7663 break;
7664 case PIPECONF_12BPC:
7665 pipe_config->pipe_bpp = 36;
7666 break;
7667 default:
7668 break;
7669 }
7670
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007671 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7672 pipe_config->limited_color_range = true;
7673
Daniel Vetterab9412b2013-05-03 11:49:46 +02007674 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007675 struct intel_shared_dpll *pll;
7676
Daniel Vetter88adfff2013-03-28 10:42:01 +01007677 pipe_config->has_pch_encoder = true;
7678
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007679 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7680 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7681 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007682
7683 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007684
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007685 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007686 pipe_config->shared_dpll =
7687 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007688 } else {
7689 tmp = I915_READ(PCH_DPLL_SEL);
7690 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7691 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7692 else
7693 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7694 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007695
7696 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7697
7698 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7699 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007700
7701 tmp = pipe_config->dpll_hw_state.dpll;
7702 pipe_config->pixel_multiplier =
7703 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7704 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007705
7706 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007707 } else {
7708 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007709 }
7710
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007711 intel_get_pipe_timings(crtc, pipe_config);
7712
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007713 ironlake_get_pfit_config(crtc, pipe_config);
7714
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007715 return true;
7716}
7717
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007718static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7719{
7720 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007721 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007722
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007723 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007724 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007725 pipe_name(crtc->pipe));
7726
7727 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
Daniel Vetter8cc3e162014-06-25 22:01:46 +03007728 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7729 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7730 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007731 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7732 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7733 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -03007734 if (IS_HASWELL(dev))
7735 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7736 "CPU PWM2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007737 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7738 "PCH PWM1 enabled\n");
7739 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7740 "Utility pin enabled\n");
7741 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7742
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007743 /*
7744 * In theory we can still leave IRQs enabled, as long as only the HPD
7745 * interrupts remain enabled. We used to check for that, but since it's
7746 * gen-specific and since we only disable LCPLL after we fully disable
7747 * the interrupts, the check below should be enough.
7748 */
Jesse Barnes9df7575f2014-06-20 09:29:20 -07007749 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007750}
7751
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007752static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7753{
7754 struct drm_device *dev = dev_priv->dev;
7755
7756 if (IS_HASWELL(dev))
7757 return I915_READ(D_COMP_HSW);
7758 else
7759 return I915_READ(D_COMP_BDW);
7760}
7761
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007762static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7763{
7764 struct drm_device *dev = dev_priv->dev;
7765
7766 if (IS_HASWELL(dev)) {
7767 mutex_lock(&dev_priv->rps.hw_lock);
7768 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7769 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03007770 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007771 mutex_unlock(&dev_priv->rps.hw_lock);
7772 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007773 I915_WRITE(D_COMP_BDW, val);
7774 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007775 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007776}
7777
7778/*
7779 * This function implements pieces of two sequences from BSpec:
7780 * - Sequence for display software to disable LCPLL
7781 * - Sequence for display software to allow package C8+
7782 * The steps implemented here are just the steps that actually touch the LCPLL
7783 * register. Callers should take care of disabling all the display engine
7784 * functions, doing the mode unset, fixing interrupts, etc.
7785 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007786static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7787 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007788{
7789 uint32_t val;
7790
7791 assert_can_disable_lcpll(dev_priv);
7792
7793 val = I915_READ(LCPLL_CTL);
7794
7795 if (switch_to_fclk) {
7796 val |= LCPLL_CD_SOURCE_FCLK;
7797 I915_WRITE(LCPLL_CTL, val);
7798
7799 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7800 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7801 DRM_ERROR("Switching to FCLK failed\n");
7802
7803 val = I915_READ(LCPLL_CTL);
7804 }
7805
7806 val |= LCPLL_PLL_DISABLE;
7807 I915_WRITE(LCPLL_CTL, val);
7808 POSTING_READ(LCPLL_CTL);
7809
7810 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7811 DRM_ERROR("LCPLL still locked\n");
7812
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007813 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007814 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007815 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007816 ndelay(100);
7817
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007818 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7819 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007820 DRM_ERROR("D_COMP RCOMP still in progress\n");
7821
7822 if (allow_power_down) {
7823 val = I915_READ(LCPLL_CTL);
7824 val |= LCPLL_POWER_DOWN_ALLOW;
7825 I915_WRITE(LCPLL_CTL, val);
7826 POSTING_READ(LCPLL_CTL);
7827 }
7828}
7829
7830/*
7831 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7832 * source.
7833 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007834static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007835{
7836 uint32_t val;
7837
7838 val = I915_READ(LCPLL_CTL);
7839
7840 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7841 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7842 return;
7843
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007844 /*
7845 * Make sure we're not on PC8 state before disabling PC8, otherwise
7846 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7847 *
7848 * The other problem is that hsw_restore_lcpll() is called as part of
7849 * the runtime PM resume sequence, so we can't just call
7850 * gen6_gt_force_wake_get() because that function calls
7851 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7852 * while we are on the resume sequence. So to solve this problem we have
7853 * to call special forcewake code that doesn't touch runtime PM and
7854 * doesn't enable the forcewake delayed work.
7855 */
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007856 spin_lock_irq(&dev_priv->uncore.lock);
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007857 if (dev_priv->uncore.forcewake_count++ == 0)
7858 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007859 spin_unlock_irq(&dev_priv->uncore.lock);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007860
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007861 if (val & LCPLL_POWER_DOWN_ALLOW) {
7862 val &= ~LCPLL_POWER_DOWN_ALLOW;
7863 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007864 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007865 }
7866
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007867 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007868 val |= D_COMP_COMP_FORCE;
7869 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007870 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007871
7872 val = I915_READ(LCPLL_CTL);
7873 val &= ~LCPLL_PLL_DISABLE;
7874 I915_WRITE(LCPLL_CTL, val);
7875
7876 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7877 DRM_ERROR("LCPLL not locked yet\n");
7878
7879 if (val & LCPLL_CD_SOURCE_FCLK) {
7880 val = I915_READ(LCPLL_CTL);
7881 val &= ~LCPLL_CD_SOURCE_FCLK;
7882 I915_WRITE(LCPLL_CTL, val);
7883
7884 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7885 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7886 DRM_ERROR("Switching back to LCPLL failed\n");
7887 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007888
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007889 /* See the big comment above. */
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007890 spin_lock_irq(&dev_priv->uncore.lock);
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007891 if (--dev_priv->uncore.forcewake_count == 0)
7892 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007893 spin_unlock_irq(&dev_priv->uncore.lock);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007894}
7895
Paulo Zanoni765dab62014-03-07 20:08:18 -03007896/*
7897 * Package states C8 and deeper are really deep PC states that can only be
7898 * reached when all the devices on the system allow it, so even if the graphics
7899 * device allows PC8+, it doesn't mean the system will actually get to these
7900 * states. Our driver only allows PC8+ when going into runtime PM.
7901 *
7902 * The requirements for PC8+ are that all the outputs are disabled, the power
7903 * well is disabled and most interrupts are disabled, and these are also
7904 * requirements for runtime PM. When these conditions are met, we manually do
7905 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7906 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7907 * hang the machine.
7908 *
7909 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7910 * the state of some registers, so when we come back from PC8+ we need to
7911 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7912 * need to take care of the registers kept by RC6. Notice that this happens even
7913 * if we don't put the device in PCI D3 state (which is what currently happens
7914 * because of the runtime PM support).
7915 *
7916 * For more, read "Display Sequences for Package C8" on the hardware
7917 * documentation.
7918 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007919void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007920{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007921 struct drm_device *dev = dev_priv->dev;
7922 uint32_t val;
7923
Paulo Zanonic67a4702013-08-19 13:18:09 -03007924 DRM_DEBUG_KMS("Enabling package C8+\n");
7925
Paulo Zanonic67a4702013-08-19 13:18:09 -03007926 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7927 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7928 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7929 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7930 }
7931
7932 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007933 hsw_disable_lcpll(dev_priv, true, true);
7934}
7935
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007936void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007937{
7938 struct drm_device *dev = dev_priv->dev;
7939 uint32_t val;
7940
Paulo Zanonic67a4702013-08-19 13:18:09 -03007941 DRM_DEBUG_KMS("Disabling package C8+\n");
7942
7943 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007944 lpt_init_pch_refclk(dev);
7945
7946 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7947 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7948 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7949 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7950 }
7951
7952 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007953}
7954
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +02007955static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03007956{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007957 if (!intel_ddi_pll_select(crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03007958 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03007959
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007960 crtc->lowfreq_avail = false;
Daniel Vetter644cef32014-04-24 23:55:07 +02007961
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007962 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007963}
7964
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007965static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7966 enum port port,
7967 struct intel_crtc_config *pipe_config)
7968{
7969 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7970
7971 switch (pipe_config->ddi_pll_sel) {
7972 case PORT_CLK_SEL_WRPLL1:
7973 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7974 break;
7975 case PORT_CLK_SEL_WRPLL2:
7976 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7977 break;
7978 }
7979}
7980
Daniel Vetter26804af2014-06-25 22:01:55 +03007981static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7982 struct intel_crtc_config *pipe_config)
7983{
7984 struct drm_device *dev = crtc->base.dev;
7985 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007986 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03007987 enum port port;
7988 uint32_t tmp;
7989
7990 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7991
7992 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7993
Damien Lespiau7d2c8172014-07-29 18:06:18 +01007994 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +03007995
Daniel Vetterd452c5b2014-07-04 11:27:39 -03007996 if (pipe_config->shared_dpll >= 0) {
7997 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7998
7999 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8000 &pipe_config->dpll_hw_state));
8001 }
8002
Daniel Vetter26804af2014-06-25 22:01:55 +03008003 /*
8004 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8005 * DDI E. So just check whether this pipe is wired to DDI E and whether
8006 * the PCH transcoder is on.
8007 */
Damien Lespiauca370452013-12-03 13:56:24 +00008008 if (INTEL_INFO(dev)->gen < 9 &&
8009 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter26804af2014-06-25 22:01:55 +03008010 pipe_config->has_pch_encoder = true;
8011
8012 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8013 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8014 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8015
8016 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8017 }
8018}
8019
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008020static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8021 struct intel_crtc_config *pipe_config)
8022{
8023 struct drm_device *dev = crtc->base.dev;
8024 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008025 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008026 uint32_t tmp;
8027
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008028 if (!intel_display_power_is_enabled(dev_priv,
Imre Deakb5482bd2014-03-05 16:20:55 +02008029 POWER_DOMAIN_PIPE(crtc->pipe)))
8030 return false;
8031
Daniel Vettere143a212013-07-04 12:01:15 +02008032 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008033 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8034
Daniel Vettereccb1402013-05-22 00:50:22 +02008035 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8036 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8037 enum pipe trans_edp_pipe;
8038 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8039 default:
8040 WARN(1, "unknown pipe linked to edp transcoder\n");
8041 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8042 case TRANS_DDI_EDP_INPUT_A_ON:
8043 trans_edp_pipe = PIPE_A;
8044 break;
8045 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8046 trans_edp_pipe = PIPE_B;
8047 break;
8048 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8049 trans_edp_pipe = PIPE_C;
8050 break;
8051 }
8052
8053 if (trans_edp_pipe == crtc->pipe)
8054 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8055 }
8056
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008057 if (!intel_display_power_is_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02008058 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03008059 return false;
8060
Daniel Vettereccb1402013-05-22 00:50:22 +02008061 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008062 if (!(tmp & PIPECONF_ENABLE))
8063 return false;
8064
Daniel Vetter26804af2014-06-25 22:01:55 +03008065 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02008066
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008067 intel_get_pipe_timings(crtc, pipe_config);
8068
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008069 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008070 if (intel_display_power_is_enabled(dev_priv, pfit_domain))
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008071 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01008072
Jesse Barnese59150d2014-01-07 13:30:45 -08008073 if (IS_HASWELL(dev))
8074 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8075 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03008076
Clint Taylorebb69c92014-09-30 10:30:22 -07008077 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8078 pipe_config->pixel_multiplier =
8079 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8080 } else {
8081 pipe_config->pixel_multiplier = 1;
8082 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02008083
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008084 return true;
8085}
8086
Chris Wilson560b85b2010-08-07 11:01:38 +01008087static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8088{
8089 struct drm_device *dev = crtc->dev;
8090 struct drm_i915_private *dev_priv = dev->dev_private;
8091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälädc41c152014-08-13 11:57:05 +03008092 uint32_t cntl = 0, size = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01008093
Ville Syrjälädc41c152014-08-13 11:57:05 +03008094 if (base) {
8095 unsigned int width = intel_crtc->cursor_width;
8096 unsigned int height = intel_crtc->cursor_height;
8097 unsigned int stride = roundup_pow_of_two(width) * 4;
8098
8099 switch (stride) {
8100 default:
8101 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8102 width, stride);
8103 stride = 256;
8104 /* fallthrough */
8105 case 256:
8106 case 512:
8107 case 1024:
8108 case 2048:
8109 break;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008110 }
8111
Ville Syrjälädc41c152014-08-13 11:57:05 +03008112 cntl |= CURSOR_ENABLE |
8113 CURSOR_GAMMA_ENABLE |
8114 CURSOR_FORMAT_ARGB |
8115 CURSOR_STRIDE(stride);
8116
8117 size = (height << 12) | width;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008118 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008119
Ville Syrjälädc41c152014-08-13 11:57:05 +03008120 if (intel_crtc->cursor_cntl != 0 &&
8121 (intel_crtc->cursor_base != base ||
8122 intel_crtc->cursor_size != size ||
8123 intel_crtc->cursor_cntl != cntl)) {
8124 /* On these chipsets we can only modify the base/size/stride
8125 * whilst the cursor is disabled.
8126 */
8127 I915_WRITE(_CURACNTR, 0);
8128 POSTING_READ(_CURACNTR);
8129 intel_crtc->cursor_cntl = 0;
8130 }
8131
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008132 if (intel_crtc->cursor_base != base) {
Ville Syrjälädc41c152014-08-13 11:57:05 +03008133 I915_WRITE(_CURABASE, base);
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008134 intel_crtc->cursor_base = base;
8135 }
Ville Syrjälädc41c152014-08-13 11:57:05 +03008136
8137 if (intel_crtc->cursor_size != size) {
8138 I915_WRITE(CURSIZE, size);
8139 intel_crtc->cursor_size = size;
8140 }
8141
Chris Wilson4b0e3332014-05-30 16:35:26 +03008142 if (intel_crtc->cursor_cntl != cntl) {
8143 I915_WRITE(_CURACNTR, cntl);
8144 POSTING_READ(_CURACNTR);
8145 intel_crtc->cursor_cntl = cntl;
8146 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008147}
8148
8149static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8150{
8151 struct drm_device *dev = crtc->dev;
8152 struct drm_i915_private *dev_priv = dev->dev_private;
8153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8154 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008155 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01008156
Chris Wilson4b0e3332014-05-30 16:35:26 +03008157 cntl = 0;
8158 if (base) {
8159 cntl = MCURSOR_GAMMA_ENABLE;
8160 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308161 case 64:
8162 cntl |= CURSOR_MODE_64_ARGB_AX;
8163 break;
8164 case 128:
8165 cntl |= CURSOR_MODE_128_ARGB_AX;
8166 break;
8167 case 256:
8168 cntl |= CURSOR_MODE_256_ARGB_AX;
8169 break;
8170 default:
8171 WARN_ON(1);
8172 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01008173 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008174 cntl |= pipe << 28; /* Connect to correct pipe */
Ville Syrjälä47bf17a2014-09-12 20:53:33 +03008175
8176 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8177 cntl |= CURSOR_PIPE_CSC_ENABLE;
Chris Wilson560b85b2010-08-07 11:01:38 +01008178 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008179
Ville Syrjälä4398ad42014-10-23 07:41:34 -07008180 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8181 cntl |= CURSOR_ROTATE_180;
8182
Chris Wilson4b0e3332014-05-30 16:35:26 +03008183 if (intel_crtc->cursor_cntl != cntl) {
8184 I915_WRITE(CURCNTR(pipe), cntl);
8185 POSTING_READ(CURCNTR(pipe));
8186 intel_crtc->cursor_cntl = cntl;
8187 }
8188
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008189 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008190 I915_WRITE(CURBASE(pipe), base);
8191 POSTING_READ(CURBASE(pipe));
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008192
8193 intel_crtc->cursor_base = base;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008194}
8195
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008196/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01008197static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8198 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008199{
8200 struct drm_device *dev = crtc->dev;
8201 struct drm_i915_private *dev_priv = dev->dev_private;
8202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8203 int pipe = intel_crtc->pipe;
Matt Roper3d7d6512014-06-10 08:28:13 -07008204 int x = crtc->cursor_x;
8205 int y = crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008206 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008207
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008208 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008209 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008210
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008211 if (x >= intel_crtc->config.pipe_src_w)
8212 base = 0;
8213
8214 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008215 base = 0;
8216
8217 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008218 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008219 base = 0;
8220
8221 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8222 x = -x;
8223 }
8224 pos |= x << CURSOR_X_SHIFT;
8225
8226 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008227 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008228 base = 0;
8229
8230 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8231 y = -y;
8232 }
8233 pos |= y << CURSOR_Y_SHIFT;
8234
Chris Wilson4b0e3332014-05-30 16:35:26 +03008235 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008236 return;
8237
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008238 I915_WRITE(CURPOS(pipe), pos);
8239
Ville Syrjälä4398ad42014-10-23 07:41:34 -07008240 /* ILK+ do this automagically */
8241 if (HAS_GMCH_DISPLAY(dev) &&
8242 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8243 base += (intel_crtc->cursor_height *
8244 intel_crtc->cursor_width - 1) * 4;
8245 }
8246
Ville Syrjälä8ac54662014-08-12 19:39:54 +03008247 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008248 i845_update_cursor(crtc, base);
8249 else
8250 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008251}
8252
Ville Syrjälädc41c152014-08-13 11:57:05 +03008253static bool cursor_size_ok(struct drm_device *dev,
8254 uint32_t width, uint32_t height)
8255{
8256 if (width == 0 || height == 0)
8257 return false;
8258
8259 /*
8260 * 845g/865g are special in that they are only limited by
8261 * the width of their cursors, the height is arbitrary up to
8262 * the precision of the register. Everything else requires
8263 * square cursors, limited to a few power-of-two sizes.
8264 */
8265 if (IS_845G(dev) || IS_I865G(dev)) {
8266 if ((width & 63) != 0)
8267 return false;
8268
8269 if (width > (IS_845G(dev) ? 64 : 512))
8270 return false;
8271
8272 if (height > 1023)
8273 return false;
8274 } else {
8275 switch (width | height) {
8276 case 256:
8277 case 128:
8278 if (IS_GEN2(dev))
8279 return false;
8280 case 64:
8281 break;
8282 default:
8283 return false;
8284 }
8285 }
8286
8287 return true;
8288}
8289
Matt Ropere3287952014-06-10 08:28:12 -07008290static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8291 struct drm_i915_gem_object *obj,
8292 uint32_t width, uint32_t height)
Jesse Barnes79e53942008-11-07 14:24:08 -08008293{
8294 struct drm_device *dev = crtc->dev;
8295 struct drm_i915_private *dev_priv = dev->dev_private;
8296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02008297 enum pipe pipe = intel_crtc->pipe;
Gustavo Padovan757f9a32014-09-24 14:20:24 -03008298 unsigned old_width;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008299 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008300 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008301
Jesse Barnes79e53942008-11-07 14:24:08 -08008302 /* if we want to turn off the cursor ignore width and height */
Matt Ropere3287952014-06-10 08:28:12 -07008303 if (!obj) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008304 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008305 addr = 0;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008306 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008307 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008308 }
8309
Dave Airlie71acb5e2008-12-30 20:31:46 +10008310 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008311 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008312 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008313 unsigned alignment;
8314
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008315 /*
8316 * Global gtt pte registers are special registers which actually
8317 * forward writes to a chunk of system memory. Which means that
8318 * there is no risk that the register values disappear as soon
8319 * as we call intel_runtime_pm_put(), so it is correct to wrap
8320 * only the pin/unpin/fence and not more.
8321 */
8322 intel_runtime_pm_get(dev_priv);
8323
Chris Wilson693db182013-03-05 14:52:39 +00008324 /* Note that the w/a also requires 2 PTE of padding following
8325 * the bo. We currently fill all unused PTE with the shadow
8326 * page and so we should always have valid PTE following the
8327 * cursor preventing the VT-d warning.
8328 */
8329 alignment = 0;
8330 if (need_vtd_wa(dev))
8331 alignment = 64*1024;
8332
8333 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008334 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008335 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008336 intel_runtime_pm_put(dev_priv);
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008337 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008338 }
8339
Chris Wilsond9e86c02010-11-10 16:40:20 +00008340 ret = i915_gem_object_put_fence(obj);
8341 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008342 DRM_DEBUG_KMS("failed to release fence for cursor");
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008343 intel_runtime_pm_put(dev_priv);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008344 goto fail_unpin;
8345 }
8346
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008347 addr = i915_gem_obj_ggtt_offset(obj);
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008348
8349 intel_runtime_pm_put(dev_priv);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008350 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008351 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson00731152014-05-21 12:42:56 +01008352 ret = i915_gem_object_attach_phys(obj, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008353 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008354 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008355 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008356 }
Chris Wilson00731152014-05-21 12:42:56 +01008357 addr = obj->phys_handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008358 }
8359
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008360 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008361 if (intel_crtc->cursor_bo) {
Chris Wilson00731152014-05-21 12:42:56 +01008362 if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilsoncc98b412013-08-09 12:25:09 +01008363 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008364 }
Jesse Barnes80824002009-09-10 15:28:06 -07008365
Daniel Vettera071fa02014-06-18 23:28:09 +02008366 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8367 INTEL_FRONTBUFFER_CURSOR(pipe));
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008368 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008369
Chris Wilson64f962e2014-03-26 12:38:15 +00008370 old_width = intel_crtc->cursor_width;
8371
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008372 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008373 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008374 intel_crtc->cursor_width = width;
8375 intel_crtc->cursor_height = height;
8376
Chris Wilson64f962e2014-03-26 12:38:15 +00008377 if (intel_crtc->active) {
8378 if (old_width != width)
8379 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008380 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008381
Gustavo Padovan3f20df92014-10-24 14:51:34 +01008382 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8383 }
Daniel Vetterf99d7062014-06-19 16:01:59 +02008384
Jesse Barnes79e53942008-11-07 14:24:08 -08008385 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008386fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008387 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008388fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008389 mutex_unlock(&dev->struct_mutex);
8390 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008391}
8392
Jesse Barnes79e53942008-11-07 14:24:08 -08008393static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008394 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008395{
James Simmons72034252010-08-03 01:33:19 +01008396 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008398
James Simmons72034252010-08-03 01:33:19 +01008399 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008400 intel_crtc->lut_r[i] = red[i] >> 8;
8401 intel_crtc->lut_g[i] = green[i] >> 8;
8402 intel_crtc->lut_b[i] = blue[i] >> 8;
8403 }
8404
8405 intel_crtc_load_lut(crtc);
8406}
8407
Jesse Barnes79e53942008-11-07 14:24:08 -08008408/* VESA 640x480x72Hz mode to set on the pipe */
8409static struct drm_display_mode load_detect_mode = {
8410 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8411 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8412};
8413
Daniel Vettera8bb6812014-02-10 18:00:39 +01008414struct drm_framebuffer *
8415__intel_framebuffer_create(struct drm_device *dev,
8416 struct drm_mode_fb_cmd2 *mode_cmd,
8417 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008418{
8419 struct intel_framebuffer *intel_fb;
8420 int ret;
8421
8422 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8423 if (!intel_fb) {
Alexey Khoroshilov6ccb81f2014-11-08 01:41:23 +03008424 drm_gem_object_unreference(&obj->base);
Chris Wilsond2dff872011-04-19 08:36:26 +01008425 return ERR_PTR(-ENOMEM);
8426 }
8427
8428 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008429 if (ret)
8430 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008431
8432 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008433err:
Alexey Khoroshilov6ccb81f2014-11-08 01:41:23 +03008434 drm_gem_object_unreference(&obj->base);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008435 kfree(intel_fb);
8436
8437 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008438}
8439
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008440static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008441intel_framebuffer_create(struct drm_device *dev,
8442 struct drm_mode_fb_cmd2 *mode_cmd,
8443 struct drm_i915_gem_object *obj)
8444{
8445 struct drm_framebuffer *fb;
8446 int ret;
8447
8448 ret = i915_mutex_lock_interruptible(dev);
8449 if (ret)
8450 return ERR_PTR(ret);
8451 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8452 mutex_unlock(&dev->struct_mutex);
8453
8454 return fb;
8455}
8456
Chris Wilsond2dff872011-04-19 08:36:26 +01008457static u32
8458intel_framebuffer_pitch_for_width(int width, int bpp)
8459{
8460 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8461 return ALIGN(pitch, 64);
8462}
8463
8464static u32
8465intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8466{
8467 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +02008468 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +01008469}
8470
8471static struct drm_framebuffer *
8472intel_framebuffer_create_for_mode(struct drm_device *dev,
8473 struct drm_display_mode *mode,
8474 int depth, int bpp)
8475{
8476 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008477 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008478
8479 obj = i915_gem_alloc_object(dev,
8480 intel_framebuffer_size_for_mode(mode, bpp));
8481 if (obj == NULL)
8482 return ERR_PTR(-ENOMEM);
8483
8484 mode_cmd.width = mode->hdisplay;
8485 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008486 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8487 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008488 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008489
8490 return intel_framebuffer_create(dev, &mode_cmd, obj);
8491}
8492
8493static struct drm_framebuffer *
8494mode_fits_in_fbdev(struct drm_device *dev,
8495 struct drm_display_mode *mode)
8496{
Daniel Vetter4520f532013-10-09 09:18:51 +02008497#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008498 struct drm_i915_private *dev_priv = dev->dev_private;
8499 struct drm_i915_gem_object *obj;
8500 struct drm_framebuffer *fb;
8501
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008502 if (!dev_priv->fbdev)
8503 return NULL;
8504
8505 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008506 return NULL;
8507
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008508 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008509 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008510
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008511 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008512 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8513 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008514 return NULL;
8515
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008516 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008517 return NULL;
8518
8519 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008520#else
8521 return NULL;
8522#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008523}
8524
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008525bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008526 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05008527 struct intel_load_detect_pipe *old,
8528 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008529{
8530 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008531 struct intel_encoder *intel_encoder =
8532 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008533 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008534 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008535 struct drm_crtc *crtc = NULL;
8536 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008537 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05008538 struct drm_mode_config *config = &dev->mode_config;
8539 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008540
Chris Wilsond2dff872011-04-19 08:36:26 +01008541 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008542 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008543 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008544
Rob Clark51fd3712013-11-19 12:10:12 -05008545retry:
8546 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8547 if (ret)
8548 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008549
Jesse Barnes79e53942008-11-07 14:24:08 -08008550 /*
8551 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008552 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008553 * - if the connector already has an assigned crtc, use it (but make
8554 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008555 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008556 * - try to find the first unused crtc that can drive this connector,
8557 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008558 */
8559
8560 /* See if we already have a CRTC for this connector */
8561 if (encoder->crtc) {
8562 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008563
Rob Clark51fd3712013-11-19 12:10:12 -05008564 ret = drm_modeset_lock(&crtc->mutex, ctx);
8565 if (ret)
8566 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01008567
Daniel Vetter24218aa2012-08-12 19:27:11 +02008568 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008569 old->load_detect_temp = false;
8570
8571 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008572 if (connector->dpms != DRM_MODE_DPMS_ON)
8573 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008574
Chris Wilson71731882011-04-19 23:10:58 +01008575 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008576 }
8577
8578 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008579 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008580 i++;
8581 if (!(encoder->possible_crtcs & (1 << i)))
8582 continue;
Ville Syrjäläa4592492014-08-11 13:15:36 +03008583 if (possible_crtc->enabled)
8584 continue;
8585 /* This can occur when applying the pipe A quirk on resume. */
8586 if (to_intel_crtc(possible_crtc)->new_enabled)
8587 continue;
8588
8589 crtc = possible_crtc;
8590 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08008591 }
8592
8593 /*
8594 * If we didn't find an unused CRTC, don't use any.
8595 */
8596 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008597 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05008598 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08008599 }
8600
Rob Clark51fd3712013-11-19 12:10:12 -05008601 ret = drm_modeset_lock(&crtc->mutex, ctx);
8602 if (ret)
8603 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02008604 intel_encoder->new_crtc = to_intel_crtc(crtc);
8605 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008606
8607 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008608 intel_crtc->new_enabled = true;
8609 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008610 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008611 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008612 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008613
Chris Wilson64927112011-04-20 07:25:26 +01008614 if (!mode)
8615 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008616
Chris Wilsond2dff872011-04-19 08:36:26 +01008617 /* We need a framebuffer large enough to accommodate all accesses
8618 * that the plane may generate whilst we perform load detection.
8619 * We can not rely on the fbcon either being present (we get called
8620 * during its initialisation to detect all boot displays, or it may
8621 * not even exist) or that it is large enough to satisfy the
8622 * requested mode.
8623 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008624 fb = mode_fits_in_fbdev(dev, mode);
8625 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008626 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008627 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8628 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008629 } else
8630 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008631 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008632 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008633 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008634 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008635
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008636 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008637 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008638 if (old->release_fb)
8639 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008640 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008641 }
Chris Wilson71731882011-04-19 23:10:58 +01008642
Jesse Barnes79e53942008-11-07 14:24:08 -08008643 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008644 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008645 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008646
8647 fail:
8648 intel_crtc->new_enabled = crtc->enabled;
8649 if (intel_crtc->new_enabled)
8650 intel_crtc->new_config = &intel_crtc->config;
8651 else
8652 intel_crtc->new_config = NULL;
Rob Clark51fd3712013-11-19 12:10:12 -05008653fail_unlock:
8654 if (ret == -EDEADLK) {
8655 drm_modeset_backoff(ctx);
8656 goto retry;
8657 }
8658
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008659 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008660}
8661
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008662void intel_release_load_detect_pipe(struct drm_connector *connector,
Ville Syrjälä208bf9f2014-08-11 13:15:35 +03008663 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008664{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008665 struct intel_encoder *intel_encoder =
8666 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008667 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008668 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008670
Chris Wilsond2dff872011-04-19 08:36:26 +01008671 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008672 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008673 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008674
Chris Wilson8261b192011-04-19 23:18:09 +01008675 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008676 to_intel_connector(connector)->new_encoder = NULL;
8677 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008678 intel_crtc->new_enabled = false;
8679 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008680 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008681
Daniel Vetter36206362012-12-10 20:42:17 +01008682 if (old->release_fb) {
8683 drm_framebuffer_unregister_private(old->release_fb);
8684 drm_framebuffer_unreference(old->release_fb);
8685 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008686
Chris Wilson0622a532011-04-21 09:32:11 +01008687 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008688 }
8689
Eric Anholtc751ce42010-03-25 11:48:48 -07008690 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008691 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8692 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008693}
8694
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008695static int i9xx_pll_refclk(struct drm_device *dev,
8696 const struct intel_crtc_config *pipe_config)
8697{
8698 struct drm_i915_private *dev_priv = dev->dev_private;
8699 u32 dpll = pipe_config->dpll_hw_state.dpll;
8700
8701 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008702 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008703 else if (HAS_PCH_SPLIT(dev))
8704 return 120000;
8705 else if (!IS_GEN2(dev))
8706 return 96000;
8707 else
8708 return 48000;
8709}
8710
Jesse Barnes79e53942008-11-07 14:24:08 -08008711/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008712static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8713 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008714{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008715 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008716 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008717 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008718 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008719 u32 fp;
8720 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008721 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008722
8723 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008724 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008725 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008726 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008727
8728 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008729 if (IS_PINEVIEW(dev)) {
8730 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8731 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008732 } else {
8733 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8734 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8735 }
8736
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008737 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008738 if (IS_PINEVIEW(dev))
8739 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8740 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008741 else
8742 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008743 DPLL_FPA01_P1_POST_DIV_SHIFT);
8744
8745 switch (dpll & DPLL_MODE_MASK) {
8746 case DPLLB_MODE_DAC_SERIAL:
8747 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8748 5 : 10;
8749 break;
8750 case DPLLB_MODE_LVDS:
8751 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8752 7 : 14;
8753 break;
8754 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008755 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008756 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008757 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008758 }
8759
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008760 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008761 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008762 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008763 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008764 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008765 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008766 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008767
8768 if (is_lvds) {
8769 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8770 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008771
8772 if (lvds & LVDS_CLKB_POWER_UP)
8773 clock.p2 = 7;
8774 else
8775 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008776 } else {
8777 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8778 clock.p1 = 2;
8779 else {
8780 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8781 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8782 }
8783 if (dpll & PLL_P2_DIVIDE_BY_4)
8784 clock.p2 = 4;
8785 else
8786 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008787 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008788
8789 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008790 }
8791
Ville Syrjälä18442d02013-09-13 16:00:08 +03008792 /*
8793 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008794 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008795 * encoder's get_config() function.
8796 */
8797 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008798}
8799
Ville Syrjälä6878da02013-09-13 15:59:11 +03008800int intel_dotclock_calculate(int link_freq,
8801 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008802{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008803 /*
8804 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008805 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008806 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008807 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008808 *
8809 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008810 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008811 */
8812
Ville Syrjälä6878da02013-09-13 15:59:11 +03008813 if (!m_n->link_n)
8814 return 0;
8815
8816 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8817}
8818
Ville Syrjälä18442d02013-09-13 16:00:08 +03008819static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8820 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008821{
8822 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008823
8824 /* read out port_clock from the DPLL */
8825 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008826
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008827 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008828 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008829 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008830 * agree once we know their relationship in the encoder's
8831 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008832 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008833 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008834 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8835 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008836}
8837
8838/** Returns the currently programmed mode of the given pipe. */
8839struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8840 struct drm_crtc *crtc)
8841{
Jesse Barnes548f2452011-02-17 10:40:53 -08008842 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008844 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008845 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008846 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008847 int htot = I915_READ(HTOTAL(cpu_transcoder));
8848 int hsync = I915_READ(HSYNC(cpu_transcoder));
8849 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8850 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008851 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008852
8853 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8854 if (!mode)
8855 return NULL;
8856
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008857 /*
8858 * Construct a pipe_config sufficient for getting the clock info
8859 * back out of crtc_clock_get.
8860 *
8861 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8862 * to use a real value here instead.
8863 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008864 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008865 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008866 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8867 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8868 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008869 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8870
Ville Syrjälä773ae032013-09-23 17:48:20 +03008871 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008872 mode->hdisplay = (htot & 0xffff) + 1;
8873 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8874 mode->hsync_start = (hsync & 0xffff) + 1;
8875 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8876 mode->vdisplay = (vtot & 0xffff) + 1;
8877 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8878 mode->vsync_start = (vsync & 0xffff) + 1;
8879 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8880
8881 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008882
8883 return mode;
8884}
8885
Jesse Barnes652c3932009-08-17 13:31:43 -07008886static void intel_decrease_pllclock(struct drm_crtc *crtc)
8887{
8888 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008889 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008891
Sonika Jindalbaff2962014-07-22 11:16:35 +05308892 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008893 return;
8894
8895 if (!dev_priv->lvds_downclock_avail)
8896 return;
8897
8898 /*
8899 * Since this is called by a timer, we should never get here in
8900 * the manual case.
8901 */
8902 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008903 int pipe = intel_crtc->pipe;
8904 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008905 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008906
Zhao Yakui44d98a62009-10-09 11:39:40 +08008907 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008908
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008909 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008910
Chris Wilson074b5e12012-05-02 12:07:06 +01008911 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008912 dpll |= DISPLAY_RATE_SELECT_FPA1;
8913 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008914 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008915 dpll = I915_READ(dpll_reg);
8916 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008917 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008918 }
8919
8920}
8921
Chris Wilsonf047e392012-07-21 12:31:41 +01008922void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008923{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008924 struct drm_i915_private *dev_priv = dev->dev_private;
8925
Chris Wilsonf62a0072014-02-21 17:55:39 +00008926 if (dev_priv->mm.busy)
8927 return;
8928
Paulo Zanoni43694d62014-03-07 20:08:08 -03008929 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008930 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00008931 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01008932}
8933
8934void intel_mark_idle(struct drm_device *dev)
8935{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008936 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008937 struct drm_crtc *crtc;
8938
Chris Wilsonf62a0072014-02-21 17:55:39 +00008939 if (!dev_priv->mm.busy)
8940 return;
8941
8942 dev_priv->mm.busy = false;
8943
Jani Nikulad330a952014-01-21 11:24:25 +02008944 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008945 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00008946
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008947 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07008948 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00008949 continue;
8950
8951 intel_decrease_pllclock(crtc);
8952 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008953
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008954 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008955 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03008956
8957out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03008958 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008959}
8960
Jesse Barnes79e53942008-11-07 14:24:08 -08008961static void intel_crtc_destroy(struct drm_crtc *crtc)
8962{
8963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008964 struct drm_device *dev = crtc->dev;
8965 struct intel_unpin_work *work;
Daniel Vetter67e77c52010-08-20 22:26:30 +02008966
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02008967 spin_lock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008968 work = intel_crtc->unpin_work;
8969 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02008970 spin_unlock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008971
8972 if (work) {
8973 cancel_work_sync(&work->work);
8974 kfree(work);
8975 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008976
8977 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008978
Jesse Barnes79e53942008-11-07 14:24:08 -08008979 kfree(intel_crtc);
8980}
8981
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008982static void intel_unpin_work_fn(struct work_struct *__work)
8983{
8984 struct intel_unpin_work *work =
8985 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008986 struct drm_device *dev = work->crtc->dev;
Daniel Vetterf99d7062014-06-19 16:01:59 +02008987 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008988
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008989 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01008990 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00008991 drm_gem_object_unreference(&work->pending_flip_obj->base);
8992 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008993
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008994 intel_update_fbc(dev);
8995 mutex_unlock(&dev->struct_mutex);
8996
Daniel Vetterf99d7062014-06-19 16:01:59 +02008997 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8998
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008999 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9000 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9001
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009002 kfree(work);
9003}
9004
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009005static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01009006 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009007{
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9009 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009010 unsigned long flags;
9011
9012 /* Ignore early vblank irqs */
9013 if (intel_crtc == NULL)
9014 return;
9015
Daniel Vetterf3260382014-09-15 14:55:23 +02009016 /*
9017 * This is called both by irq handlers and the reset code (to complete
9018 * lost pageflips) so needs the full irqsave spinlocks.
9019 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009020 spin_lock_irqsave(&dev->event_lock, flags);
9021 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00009022
9023 /* Ensure we don't miss a work->pending update ... */
9024 smp_rmb();
9025
9026 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009027 spin_unlock_irqrestore(&dev->event_lock, flags);
9028 return;
9029 }
9030
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009031 page_flip_completed(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01009032
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009033 spin_unlock_irqrestore(&dev->event_lock, flags);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009034}
9035
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009036void intel_finish_page_flip(struct drm_device *dev, int pipe)
9037{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009038 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009039 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9040
Mario Kleiner49b14a52010-12-09 07:00:07 +01009041 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009042}
9043
9044void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9045{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009046 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009047 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9048
Mario Kleiner49b14a52010-12-09 07:00:07 +01009049 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009050}
9051
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009052/* Is 'a' after or equal to 'b'? */
9053static bool g4x_flip_count_after_eq(u32 a, u32 b)
9054{
9055 return !((a - b) & 0x80000000);
9056}
9057
9058static bool page_flip_finished(struct intel_crtc *crtc)
9059{
9060 struct drm_device *dev = crtc->base.dev;
9061 struct drm_i915_private *dev_priv = dev->dev_private;
9062
9063 /*
9064 * The relevant registers doen't exist on pre-ctg.
9065 * As the flip done interrupt doesn't trigger for mmio
9066 * flips on gmch platforms, a flip count check isn't
9067 * really needed there. But since ctg has the registers,
9068 * include it in the check anyway.
9069 */
9070 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9071 return true;
9072
9073 /*
9074 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9075 * used the same base address. In that case the mmio flip might
9076 * have completed, but the CS hasn't even executed the flip yet.
9077 *
9078 * A flip count check isn't enough as the CS might have updated
9079 * the base address just after start of vblank, but before we
9080 * managed to process the interrupt. This means we'd complete the
9081 * CS flip too soon.
9082 *
9083 * Combining both checks should get us a good enough result. It may
9084 * still happen that the CS flip has been executed, but has not
9085 * yet actually completed. But in case the base address is the same
9086 * anyway, we don't really care.
9087 */
9088 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9089 crtc->unpin_work->gtt_offset &&
9090 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9091 crtc->unpin_work->flip_count);
9092}
9093
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009094void intel_prepare_page_flip(struct drm_device *dev, int plane)
9095{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009096 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009097 struct intel_crtc *intel_crtc =
9098 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9099 unsigned long flags;
9100
Daniel Vetterf3260382014-09-15 14:55:23 +02009101
9102 /*
9103 * This is called both by irq handlers and the reset code (to complete
9104 * lost pageflips) so needs the full irqsave spinlocks.
9105 *
9106 * NB: An MMIO update of the plane base pointer will also
Chris Wilsone7d841c2012-12-03 11:36:30 +00009107 * generate a page-flip completion irq, i.e. every modeset
9108 * is also accompanied by a spurious intel_prepare_page_flip().
9109 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009110 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009111 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00009112 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009113 spin_unlock_irqrestore(&dev->event_lock, flags);
9114}
9115
Robin Schroereba905b2014-05-18 02:24:50 +02009116static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00009117{
9118 /* Ensure that the work item is consistent when activating it ... */
9119 smp_wmb();
9120 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9121 /* and that it is marked active as soon as the irq could fire. */
9122 smp_wmb();
9123}
9124
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009125static int intel_gen2_queue_flip(struct drm_device *dev,
9126 struct drm_crtc *crtc,
9127 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009128 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009129 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009130 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009131{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009133 u32 flip_mask;
9134 int ret;
9135
Daniel Vetter6d90c952012-04-26 23:28:05 +02009136 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009137 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009138 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009139
9140 /* Can't queue multiple flips, so wait for the previous
9141 * one to finish before executing the next.
9142 */
9143 if (intel_crtc->plane)
9144 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9145 else
9146 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009147 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9148 intel_ring_emit(ring, MI_NOOP);
9149 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9150 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9151 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009152 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009153 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00009154
9155 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009156 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009157 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009158}
9159
9160static int intel_gen3_queue_flip(struct drm_device *dev,
9161 struct drm_crtc *crtc,
9162 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009163 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009164 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009165 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009166{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009168 u32 flip_mask;
9169 int ret;
9170
Daniel Vetter6d90c952012-04-26 23:28:05 +02009171 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009172 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009173 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009174
9175 if (intel_crtc->plane)
9176 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9177 else
9178 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009179 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9180 intel_ring_emit(ring, MI_NOOP);
9181 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9182 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9183 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009184 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009185 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009186
Chris Wilsone7d841c2012-12-03 11:36:30 +00009187 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009188 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009189 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009190}
9191
9192static int intel_gen4_queue_flip(struct drm_device *dev,
9193 struct drm_crtc *crtc,
9194 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009195 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009196 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009197 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009198{
9199 struct drm_i915_private *dev_priv = dev->dev_private;
9200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9201 uint32_t pf, pipesrc;
9202 int ret;
9203
Daniel Vetter6d90c952012-04-26 23:28:05 +02009204 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009205 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009206 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009207
9208 /* i965+ uses the linear or tiled offsets from the
9209 * Display Registers (which do not change across a page-flip)
9210 * so we need only reprogram the base address.
9211 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009212 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9213 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9214 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009215 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009216 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009217
9218 /* XXX Enabling the panel-fitter across page-flip is so far
9219 * untested on non-native modes, so ignore it for now.
9220 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9221 */
9222 pf = 0;
9223 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009224 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009225
9226 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009227 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009228 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009229}
9230
9231static int intel_gen6_queue_flip(struct drm_device *dev,
9232 struct drm_crtc *crtc,
9233 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009234 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009235 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009236 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009237{
9238 struct drm_i915_private *dev_priv = dev->dev_private;
9239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9240 uint32_t pf, pipesrc;
9241 int ret;
9242
Daniel Vetter6d90c952012-04-26 23:28:05 +02009243 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009244 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009245 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009246
Daniel Vetter6d90c952012-04-26 23:28:05 +02009247 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9248 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9249 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009250 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009251
Chris Wilson99d9acd2012-04-17 20:37:00 +01009252 /* Contrary to the suggestions in the documentation,
9253 * "Enable Panel Fitter" does not seem to be required when page
9254 * flipping with a non-native mode, and worse causes a normal
9255 * modeset to fail.
9256 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9257 */
9258 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009259 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009260 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009261
9262 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009263 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009264 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009265}
9266
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009267static int intel_gen7_queue_flip(struct drm_device *dev,
9268 struct drm_crtc *crtc,
9269 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009270 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009271 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009272 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009273{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009275 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009276 int len, ret;
9277
Robin Schroereba905b2014-05-18 02:24:50 +02009278 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009279 case PLANE_A:
9280 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9281 break;
9282 case PLANE_B:
9283 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9284 break;
9285 case PLANE_C:
9286 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9287 break;
9288 default:
9289 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009290 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009291 }
9292
Chris Wilsonffe74d72013-08-26 20:58:12 +01009293 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009294 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009295 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009296 /*
9297 * On Gen 8, SRM is now taking an extra dword to accommodate
9298 * 48bits addresses, and we need a NOOP for the batch size to
9299 * stay even.
9300 */
9301 if (IS_GEN8(dev))
9302 len += 2;
9303 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009304
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009305 /*
9306 * BSpec MI_DISPLAY_FLIP for IVB:
9307 * "The full packet must be contained within the same cache line."
9308 *
9309 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9310 * cacheline, if we ever start emitting more commands before
9311 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9312 * then do the cacheline alignment, and finally emit the
9313 * MI_DISPLAY_FLIP.
9314 */
9315 ret = intel_ring_cacheline_align(ring);
9316 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009317 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009318
Chris Wilsonffe74d72013-08-26 20:58:12 +01009319 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009320 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009321 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009322
Chris Wilsonffe74d72013-08-26 20:58:12 +01009323 /* Unmask the flip-done completion message. Note that the bspec says that
9324 * we should do this for both the BCS and RCS, and that we must not unmask
9325 * more than one flip event at any time (or ensure that one flip message
9326 * can be sent by waiting for flip-done prior to queueing new flips).
9327 * Experimentation says that BCS works despite DERRMR masking all
9328 * flip-done completion events and that unmasking all planes at once
9329 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9330 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9331 */
9332 if (ring->id == RCS) {
9333 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9334 intel_ring_emit(ring, DERRMR);
9335 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9336 DERRMR_PIPEB_PRI_FLIP_DONE |
9337 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009338 if (IS_GEN8(dev))
9339 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9340 MI_SRM_LRM_GLOBAL_GTT);
9341 else
9342 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9343 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009344 intel_ring_emit(ring, DERRMR);
9345 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009346 if (IS_GEN8(dev)) {
9347 intel_ring_emit(ring, 0);
9348 intel_ring_emit(ring, MI_NOOP);
9349 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009350 }
9351
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009352 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009353 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009354 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009355 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009356
9357 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009358 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009359 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009360}
9361
Sourab Gupta84c33a62014-06-02 16:47:17 +05309362static bool use_mmio_flip(struct intel_engine_cs *ring,
9363 struct drm_i915_gem_object *obj)
9364{
9365 /*
9366 * This is not being used for older platforms, because
9367 * non-availability of flip done interrupt forces us to use
9368 * CS flips. Older platforms derive flip done using some clever
9369 * tricks involving the flip_pending status bits and vblank irqs.
9370 * So using MMIO flips there would disrupt this mechanism.
9371 */
9372
Chris Wilson8e09bf82014-07-08 10:40:30 +01009373 if (ring == NULL)
9374 return true;
9375
Sourab Gupta84c33a62014-06-02 16:47:17 +05309376 if (INTEL_INFO(ring->dev)->gen < 5)
9377 return false;
9378
9379 if (i915.use_mmio_flip < 0)
9380 return false;
9381 else if (i915.use_mmio_flip > 0)
9382 return true;
Oscar Mateo14bf9932014-07-24 17:04:34 +01009383 else if (i915.enable_execlists)
9384 return true;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309385 else
9386 return ring != obj->ring;
9387}
9388
9389static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9390{
9391 struct drm_device *dev = intel_crtc->base.dev;
9392 struct drm_i915_private *dev_priv = dev->dev_private;
9393 struct intel_framebuffer *intel_fb =
9394 to_intel_framebuffer(intel_crtc->base.primary->fb);
9395 struct drm_i915_gem_object *obj = intel_fb->obj;
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009396 bool atomic_update;
9397 u32 start_vbl_count;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309398 u32 dspcntr;
9399 u32 reg;
9400
9401 intel_mark_page_flip_active(intel_crtc);
9402
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009403 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9404
Sourab Gupta84c33a62014-06-02 16:47:17 +05309405 reg = DSPCNTR(intel_crtc->plane);
9406 dspcntr = I915_READ(reg);
9407
Damien Lespiauc5d97472014-10-25 00:11:11 +01009408 if (obj->tiling_mode != I915_TILING_NONE)
9409 dspcntr |= DISPPLANE_TILED;
9410 else
9411 dspcntr &= ~DISPPLANE_TILED;
9412
Sourab Gupta84c33a62014-06-02 16:47:17 +05309413 I915_WRITE(reg, dspcntr);
9414
9415 I915_WRITE(DSPSURF(intel_crtc->plane),
9416 intel_crtc->unpin_work->gtt_offset);
9417 POSTING_READ(DSPSURF(intel_crtc->plane));
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009418
9419 if (atomic_update)
9420 intel_pipe_update_end(intel_crtc, start_vbl_count);
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009421}
9422
9423static void intel_mmio_flip_work_func(struct work_struct *work)
9424{
9425 struct intel_crtc *intel_crtc =
9426 container_of(work, struct intel_crtc, mmio_flip.work);
Ander Conselvan de Oliveira536f5b52014-11-06 11:03:40 +02009427 struct intel_engine_cs *ring;
9428 uint32_t seqno;
9429
9430 seqno = intel_crtc->mmio_flip.seqno;
9431 ring = intel_crtc->mmio_flip.ring;
9432
9433 if (seqno)
9434 WARN_ON(__i915_wait_seqno(ring, seqno,
9435 intel_crtc->reset_counter,
9436 false, NULL, NULL) != 0);
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009437
9438 intel_do_mmio_flip(intel_crtc);
Sourab Gupta84c33a62014-06-02 16:47:17 +05309439}
9440
Sourab Gupta84c33a62014-06-02 16:47:17 +05309441static int intel_queue_mmio_flip(struct drm_device *dev,
9442 struct drm_crtc *crtc,
9443 struct drm_framebuffer *fb,
9444 struct drm_i915_gem_object *obj,
9445 struct intel_engine_cs *ring,
9446 uint32_t flags)
9447{
Sourab Gupta84c33a62014-06-02 16:47:17 +05309448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Sourab Gupta84c33a62014-06-02 16:47:17 +05309449
Sourab Gupta84c33a62014-06-02 16:47:17 +05309450 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
Ander Conselvan de Oliveira536f5b52014-11-06 11:03:40 +02009451 intel_crtc->mmio_flip.ring = obj->ring;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309452
Ander Conselvan de Oliveira536f5b52014-11-06 11:03:40 +02009453 schedule_work(&intel_crtc->mmio_flip.work);
9454
Sourab Gupta84c33a62014-06-02 16:47:17 +05309455 return 0;
9456}
9457
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009458static int intel_default_queue_flip(struct drm_device *dev,
9459 struct drm_crtc *crtc,
9460 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009461 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009462 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009463 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009464{
9465 return -ENODEV;
9466}
9467
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009468static bool __intel_pageflip_stall_check(struct drm_device *dev,
9469 struct drm_crtc *crtc)
9470{
9471 struct drm_i915_private *dev_priv = dev->dev_private;
9472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9473 struct intel_unpin_work *work = intel_crtc->unpin_work;
9474 u32 addr;
9475
9476 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9477 return true;
9478
9479 if (!work->enable_stall_check)
9480 return false;
9481
9482 if (work->flip_ready_vblank == 0) {
9483 if (work->flip_queued_ring &&
9484 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9485 work->flip_queued_seqno))
9486 return false;
9487
9488 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9489 }
9490
9491 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9492 return false;
9493
9494 /* Potential stall - if we see that the flip has happened,
9495 * assume a missed interrupt. */
9496 if (INTEL_INFO(dev)->gen >= 4)
9497 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9498 else
9499 addr = I915_READ(DSPADDR(intel_crtc->plane));
9500
9501 /* There is a potential issue here with a false positive after a flip
9502 * to the same address. We could address this by checking for a
9503 * non-incrementing frame counter.
9504 */
9505 return addr == work->gtt_offset;
9506}
9507
9508void intel_check_page_flip(struct drm_device *dev, int pipe)
9509{
9510 struct drm_i915_private *dev_priv = dev->dev_private;
9511 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterf3260382014-09-15 14:55:23 +02009513
9514 WARN_ON(!in_irq());
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009515
9516 if (crtc == NULL)
9517 return;
9518
Daniel Vetterf3260382014-09-15 14:55:23 +02009519 spin_lock(&dev->event_lock);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009520 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9521 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9522 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9523 page_flip_completed(intel_crtc);
9524 }
Daniel Vetterf3260382014-09-15 14:55:23 +02009525 spin_unlock(&dev->event_lock);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009526}
9527
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009528static int intel_crtc_page_flip(struct drm_crtc *crtc,
9529 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009530 struct drm_pending_vblank_event *event,
9531 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009532{
9533 struct drm_device *dev = crtc->dev;
9534 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009535 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009536 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02009538 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009539 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009540 struct intel_engine_cs *ring;
Chris Wilson52e68632010-08-08 10:15:59 +01009541 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009542
Matt Roper2ff8fde2014-07-08 07:50:07 -07009543 /*
9544 * drm_mode_page_flip_ioctl() should already catch this, but double
9545 * check to be safe. In the future we may enable pageflipping from
9546 * a disabled primary plane.
9547 */
9548 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9549 return -EBUSY;
9550
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009551 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009552 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009553 return -EINVAL;
9554
9555 /*
9556 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9557 * Note that pitch changes could also affect these register.
9558 */
9559 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009560 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9561 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009562 return -EINVAL;
9563
Chris Wilsonf900db42014-02-20 09:26:13 +00009564 if (i915_terminally_wedged(&dev_priv->gpu_error))
9565 goto out_hang;
9566
Daniel Vetterb14c5672013-09-19 12:18:32 +02009567 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009568 if (work == NULL)
9569 return -ENOMEM;
9570
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009571 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009572 work->crtc = crtc;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009573 work->old_fb_obj = intel_fb_obj(old_fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009574 INIT_WORK(&work->work, intel_unpin_work_fn);
9575
Daniel Vetter87b6b102014-05-15 15:33:46 +02009576 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009577 if (ret)
9578 goto free_work;
9579
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009580 /* We borrow the event spin lock for protecting unpin_work */
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009581 spin_lock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009582 if (intel_crtc->unpin_work) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009583 /* Before declaring the flip queue wedged, check if
9584 * the hardware completed the operation behind our backs.
9585 */
9586 if (__intel_pageflip_stall_check(dev, crtc)) {
9587 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9588 page_flip_completed(intel_crtc);
9589 } else {
9590 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009591 spin_unlock_irq(&dev->event_lock);
Chris Wilson468f0b42010-05-27 13:18:13 +01009592
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009593 drm_crtc_vblank_put(crtc);
9594 kfree(work);
9595 return -EBUSY;
9596 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009597 }
9598 intel_crtc->unpin_work = work;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009599 spin_unlock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009600
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009601 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9602 flush_workqueue(dev_priv->wq);
9603
Chris Wilson79158102012-05-23 11:13:58 +01009604 ret = i915_mutex_lock_interruptible(dev);
9605 if (ret)
9606 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009607
Jesse Barnes75dfca82010-02-10 15:09:44 -08009608 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009609 drm_gem_object_reference(&work->old_fb_obj->base);
9610 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009611
Matt Roperf4510a22014-04-01 15:22:40 -07009612 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009613
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009614 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009615
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009616 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009617 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009618
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009619 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Daniel Vettera071fa02014-06-18 23:28:09 +02009620 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009621
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009622 if (IS_VALLEYVIEW(dev)) {
9623 ring = &dev_priv->ring[BCS];
Chris Wilson8e09bf82014-07-08 10:40:30 +01009624 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9625 /* vlv: DISPLAY_FLIP fails to change tiling */
9626 ring = NULL;
Chris Wilson2a92d5b2014-07-08 10:40:29 +01009627 } else if (IS_IVYBRIDGE(dev)) {
9628 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009629 } else if (INTEL_INFO(dev)->gen >= 7) {
9630 ring = obj->ring;
9631 if (ring == NULL || ring->id != RCS)
9632 ring = &dev_priv->ring[BCS];
9633 } else {
9634 ring = &dev_priv->ring[RCS];
9635 }
9636
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00009637 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009638 if (ret)
9639 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009640
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009641 work->gtt_offset =
9642 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9643
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009644 if (use_mmio_flip(ring, obj)) {
Sourab Gupta84c33a62014-06-02 16:47:17 +05309645 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9646 page_flip_flags);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009647 if (ret)
9648 goto cleanup_unpin;
9649
9650 work->flip_queued_seqno = obj->last_write_seqno;
9651 work->flip_queued_ring = obj->ring;
9652 } else {
Sourab Gupta84c33a62014-06-02 16:47:17 +05309653 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009654 page_flip_flags);
9655 if (ret)
9656 goto cleanup_unpin;
9657
9658 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9659 work->flip_queued_ring = ring;
9660 }
9661
9662 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9663 work->enable_stall_check = true;
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009664
Daniel Vettera071fa02014-06-18 23:28:09 +02009665 i915_gem_track_fb(work->old_fb_obj, obj,
9666 INTEL_FRONTBUFFER_PRIMARY(pipe));
9667
Chris Wilson7782de32011-07-08 12:22:41 +01009668 intel_disable_fbc(dev);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009669 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009670 mutex_unlock(&dev->struct_mutex);
9671
Jesse Barnese5510fa2010-07-01 16:48:37 -07009672 trace_i915_flip_request(intel_crtc->plane, obj);
9673
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009674 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009675
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009676cleanup_unpin:
9677 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009678cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009679 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009680 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009681 drm_gem_object_unreference(&work->old_fb_obj->base);
9682 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009683 mutex_unlock(&dev->struct_mutex);
9684
Chris Wilson79158102012-05-23 11:13:58 +01009685cleanup:
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009686 spin_lock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +01009687 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009688 spin_unlock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +01009689
Daniel Vetter87b6b102014-05-15 15:33:46 +02009690 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009691free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009692 kfree(work);
9693
Chris Wilsonf900db42014-02-20 09:26:13 +00009694 if (ret == -EIO) {
9695out_hang:
9696 intel_crtc_wait_for_pending_flips(crtc);
9697 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +01009698 if (ret == 0 && event) {
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009699 spin_lock_irq(&dev->event_lock);
Daniel Vettera071fa02014-06-18 23:28:09 +02009700 drm_send_vblank_event(dev, pipe, event);
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009701 spin_unlock_irq(&dev->event_lock);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +01009702 }
Chris Wilsonf900db42014-02-20 09:26:13 +00009703 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009704 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009705}
9706
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009707static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009708 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9709 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009710};
9711
Daniel Vetter9a935852012-07-05 22:34:27 +02009712/**
9713 * intel_modeset_update_staged_output_state
9714 *
9715 * Updates the staged output configuration state, e.g. after we've read out the
9716 * current hw state.
9717 */
9718static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9719{
Ville Syrjälä76688512014-01-10 11:28:06 +02009720 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009721 struct intel_encoder *encoder;
9722 struct intel_connector *connector;
9723
9724 list_for_each_entry(connector, &dev->mode_config.connector_list,
9725 base.head) {
9726 connector->new_encoder =
9727 to_intel_encoder(connector->base.encoder);
9728 }
9729
Damien Lespiaub2784e12014-08-05 11:29:37 +01009730 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009731 encoder->new_crtc =
9732 to_intel_crtc(encoder->base.crtc);
9733 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009734
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009735 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009736 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009737
9738 if (crtc->new_enabled)
9739 crtc->new_config = &crtc->config;
9740 else
9741 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009742 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009743}
9744
9745/**
9746 * intel_modeset_commit_output_state
9747 *
9748 * This function copies the stage display pipe configuration to the real one.
9749 */
9750static void intel_modeset_commit_output_state(struct drm_device *dev)
9751{
Ville Syrjälä76688512014-01-10 11:28:06 +02009752 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009753 struct intel_encoder *encoder;
9754 struct intel_connector *connector;
9755
9756 list_for_each_entry(connector, &dev->mode_config.connector_list,
9757 base.head) {
9758 connector->base.encoder = &connector->new_encoder->base;
9759 }
9760
Damien Lespiaub2784e12014-08-05 11:29:37 +01009761 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009762 encoder->base.crtc = &encoder->new_crtc->base;
9763 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009764
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009765 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009766 crtc->base.enabled = crtc->new_enabled;
9767 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009768}
9769
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009770static void
Robin Schroereba905b2014-05-18 02:24:50 +02009771connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009772 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009773{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009774 int bpp = pipe_config->pipe_bpp;
9775
9776 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9777 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009778 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009779
9780 /* Don't use an invalid EDID bpc value */
9781 if (connector->base.display_info.bpc &&
9782 connector->base.display_info.bpc * 3 < bpp) {
9783 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9784 bpp, connector->base.display_info.bpc*3);
9785 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9786 }
9787
9788 /* Clamp bpp to 8 on screens without EDID 1.4 */
9789 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9790 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9791 bpp);
9792 pipe_config->pipe_bpp = 24;
9793 }
9794}
9795
9796static int
9797compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9798 struct drm_framebuffer *fb,
9799 struct intel_crtc_config *pipe_config)
9800{
9801 struct drm_device *dev = crtc->base.dev;
9802 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009803 int bpp;
9804
Daniel Vetterd42264b2013-03-28 16:38:08 +01009805 switch (fb->pixel_format) {
9806 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009807 bpp = 8*3; /* since we go through a colormap */
9808 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009809 case DRM_FORMAT_XRGB1555:
9810 case DRM_FORMAT_ARGB1555:
9811 /* checked in intel_framebuffer_init already */
9812 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9813 return -EINVAL;
9814 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009815 bpp = 6*3; /* min is 18bpp */
9816 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009817 case DRM_FORMAT_XBGR8888:
9818 case DRM_FORMAT_ABGR8888:
9819 /* checked in intel_framebuffer_init already */
9820 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9821 return -EINVAL;
9822 case DRM_FORMAT_XRGB8888:
9823 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009824 bpp = 8*3;
9825 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009826 case DRM_FORMAT_XRGB2101010:
9827 case DRM_FORMAT_ARGB2101010:
9828 case DRM_FORMAT_XBGR2101010:
9829 case DRM_FORMAT_ABGR2101010:
9830 /* checked in intel_framebuffer_init already */
9831 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01009832 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009833 bpp = 10*3;
9834 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01009835 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009836 default:
9837 DRM_DEBUG_KMS("unsupported depth\n");
9838 return -EINVAL;
9839 }
9840
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009841 pipe_config->pipe_bpp = bpp;
9842
9843 /* Clamp display bpp to EDID value */
9844 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009845 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02009846 if (!connector->new_encoder ||
9847 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009848 continue;
9849
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009850 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009851 }
9852
9853 return bpp;
9854}
9855
Daniel Vetter644db712013-09-19 14:53:58 +02009856static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9857{
9858 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9859 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +01009860 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +02009861 mode->crtc_hdisplay, mode->crtc_hsync_start,
9862 mode->crtc_hsync_end, mode->crtc_htotal,
9863 mode->crtc_vdisplay, mode->crtc_vsync_start,
9864 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9865}
9866
Daniel Vetterc0b03412013-05-28 12:05:54 +02009867static void intel_dump_pipe_config(struct intel_crtc *crtc,
9868 struct intel_crtc_config *pipe_config,
9869 const char *context)
9870{
9871 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9872 context, pipe_name(crtc->pipe));
9873
9874 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9875 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9876 pipe_config->pipe_bpp, pipe_config->dither);
9877 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9878 pipe_config->has_pch_encoder,
9879 pipe_config->fdi_lanes,
9880 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9881 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9882 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009883 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9884 pipe_config->has_dp_encoder,
9885 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9886 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9887 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009888
9889 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9890 pipe_config->has_dp_encoder,
9891 pipe_config->dp_m2_n2.gmch_m,
9892 pipe_config->dp_m2_n2.gmch_n,
9893 pipe_config->dp_m2_n2.link_m,
9894 pipe_config->dp_m2_n2.link_n,
9895 pipe_config->dp_m2_n2.tu);
9896
Daniel Vetterc0b03412013-05-28 12:05:54 +02009897 DRM_DEBUG_KMS("requested mode:\n");
9898 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9899 DRM_DEBUG_KMS("adjusted mode:\n");
9900 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +02009901 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009902 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009903 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9904 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009905 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9906 pipe_config->gmch_pfit.control,
9907 pipe_config->gmch_pfit.pgm_ratios,
9908 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009909 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +02009910 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009911 pipe_config->pch_pfit.size,
9912 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009913 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03009914 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009915}
9916
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009917static bool encoders_cloneable(const struct intel_encoder *a,
9918 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009919{
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009920 /* masks could be asymmetric, so check both ways */
9921 return a == b || (a->cloneable & (1 << b->type) &&
9922 b->cloneable & (1 << a->type));
9923}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009924
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009925static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9926 struct intel_encoder *encoder)
9927{
9928 struct drm_device *dev = crtc->base.dev;
9929 struct intel_encoder *source_encoder;
9930
Damien Lespiaub2784e12014-08-05 11:29:37 +01009931 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009932 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009933 continue;
9934
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009935 if (!encoders_cloneable(encoder, source_encoder))
9936 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009937 }
9938
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009939 return true;
9940}
9941
9942static bool check_encoder_cloning(struct intel_crtc *crtc)
9943{
9944 struct drm_device *dev = crtc->base.dev;
9945 struct intel_encoder *encoder;
9946
Damien Lespiaub2784e12014-08-05 11:29:37 +01009947 for_each_intel_encoder(dev, encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009948 if (encoder->new_crtc != crtc)
9949 continue;
9950
9951 if (!check_single_encoder_cloning(crtc, encoder))
9952 return false;
9953 }
9954
9955 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009956}
9957
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009958static struct intel_crtc_config *
9959intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009960 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009961 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02009962{
9963 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02009964 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009965 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +01009966 int plane_bpp, ret = -EINVAL;
9967 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +02009968
Ville Syrjäläbc079e82014-03-03 16:15:28 +02009969 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02009970 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9971 return ERR_PTR(-EINVAL);
9972 }
9973
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009974 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9975 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02009976 return ERR_PTR(-ENOMEM);
9977
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009978 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9979 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009980
Daniel Vettere143a212013-07-04 12:01:15 +02009981 pipe_config->cpu_transcoder =
9982 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009983 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009984
Imre Deak2960bc92013-07-30 13:36:32 +03009985 /*
9986 * Sanitize sync polarity flags based on requested ones. If neither
9987 * positive or negative polarity is requested, treat this as meaning
9988 * negative polarity.
9989 */
9990 if (!(pipe_config->adjusted_mode.flags &
9991 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9992 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9993
9994 if (!(pipe_config->adjusted_mode.flags &
9995 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9996 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9997
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009998 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9999 * plane pixel format and any sink constraints into account. Returns the
10000 * source plane bpp so that dithering can be selected on mismatches
10001 * after encoders and crtc also have had their say. */
10002 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10003 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010004 if (plane_bpp < 0)
10005 goto fail;
10006
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030010007 /*
10008 * Determine the real pipe dimensions. Note that stereo modes can
10009 * increase the actual pipe size due to the frame doubling and
10010 * insertion of additional space for blanks between the frame. This
10011 * is stored in the crtc timings. We use the requested mode to do this
10012 * computation to clearly distinguish it from the adjusted mode, which
10013 * can be changed by the connectors in the below retry loop.
10014 */
10015 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10016 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10017 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10018
Daniel Vettere29c22c2013-02-21 00:00:16 +010010019encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020010020 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020010021 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020010022 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010023
Daniel Vetter135c81b2013-07-21 21:37:09 +020010024 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +010010025 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020010026
Daniel Vetter7758a112012-07-08 19:40:39 +020010027 /* Pass our mode to the connectors and the CRTC to give them a chance to
10028 * adjust it according to limitations or connector properties, and also
10029 * a chance to reject the mode entirely.
10030 */
Damien Lespiaub2784e12014-08-05 11:29:37 +010010031 for_each_intel_encoder(dev, encoder) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010032
10033 if (&encoder->new_crtc->base != crtc)
10034 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +010010035
Daniel Vetterefea6e82013-07-21 21:36:59 +020010036 if (!(encoder->compute_config(encoder, pipe_config))) {
10037 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020010038 goto fail;
10039 }
10040 }
10041
Daniel Vetterff9a6752013-06-01 17:16:21 +020010042 /* Set default port clock if not overwritten by the encoder. Needs to be
10043 * done afterwards in case the encoder adjusts the mode. */
10044 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +010010045 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10046 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010047
Daniel Vettera43f6e02013-06-07 23:10:32 +020010048 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010049 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010050 DRM_DEBUG_KMS("CRTC fixup failed\n");
10051 goto fail;
10052 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010010053
10054 if (ret == RETRY) {
10055 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10056 ret = -EINVAL;
10057 goto fail;
10058 }
10059
10060 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10061 retry = false;
10062 goto encoder_retry;
10063 }
10064
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010065 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10066 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10067 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10068
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010069 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +020010070fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010071 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010072 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +020010073}
10074
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010075/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10076 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10077static void
10078intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10079 unsigned *prepare_pipes, unsigned *disable_pipes)
10080{
10081 struct intel_crtc *intel_crtc;
10082 struct drm_device *dev = crtc->dev;
10083 struct intel_encoder *encoder;
10084 struct intel_connector *connector;
10085 struct drm_crtc *tmp_crtc;
10086
10087 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10088
10089 /* Check which crtcs have changed outputs connected to them, these need
10090 * to be part of the prepare_pipes mask. We don't (yet) support global
10091 * modeset across multiple crtcs, so modeset_pipes will only have one
10092 * bit set at most. */
10093 list_for_each_entry(connector, &dev->mode_config.connector_list,
10094 base.head) {
10095 if (connector->base.encoder == &connector->new_encoder->base)
10096 continue;
10097
10098 if (connector->base.encoder) {
10099 tmp_crtc = connector->base.encoder->crtc;
10100
10101 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10102 }
10103
10104 if (connector->new_encoder)
10105 *prepare_pipes |=
10106 1 << connector->new_encoder->new_crtc->pipe;
10107 }
10108
Damien Lespiaub2784e12014-08-05 11:29:37 +010010109 for_each_intel_encoder(dev, encoder) {
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010110 if (encoder->base.crtc == &encoder->new_crtc->base)
10111 continue;
10112
10113 if (encoder->base.crtc) {
10114 tmp_crtc = encoder->base.crtc;
10115
10116 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10117 }
10118
10119 if (encoder->new_crtc)
10120 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10121 }
10122
Ville Syrjälä76688512014-01-10 11:28:06 +020010123 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010124 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010125 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010126 continue;
10127
Ville Syrjälä76688512014-01-10 11:28:06 +020010128 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010129 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +020010130 else
10131 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010132 }
10133
10134
10135 /* set_mode is also used to update properties on life display pipes. */
10136 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +020010137 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010138 *prepare_pipes |= 1 << intel_crtc->pipe;
10139
Daniel Vetterb6c51642013-04-12 18:48:43 +020010140 /*
10141 * For simplicity do a full modeset on any pipe where the output routing
10142 * changed. We could be more clever, but that would require us to be
10143 * more careful with calling the relevant encoder->mode_set functions.
10144 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010145 if (*prepare_pipes)
10146 *modeset_pipes = *prepare_pipes;
10147
10148 /* ... and mask these out. */
10149 *modeset_pipes &= ~(*disable_pipes);
10150 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +020010151
10152 /*
10153 * HACK: We don't (yet) fully support global modesets. intel_set_config
10154 * obies this rule, but the modeset restore mode of
10155 * intel_modeset_setup_hw_state does not.
10156 */
10157 *modeset_pipes &= 1 << intel_crtc->pipe;
10158 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +020010159
10160 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10161 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010162}
10163
Daniel Vetterea9d7582012-07-10 10:42:52 +020010164static bool intel_crtc_in_use(struct drm_crtc *crtc)
10165{
10166 struct drm_encoder *encoder;
10167 struct drm_device *dev = crtc->dev;
10168
10169 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10170 if (encoder->crtc == crtc)
10171 return true;
10172
10173 return false;
10174}
10175
10176static void
10177intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10178{
Daniel Vetterba41c0de2014-11-03 15:04:55 +010010179 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterea9d7582012-07-10 10:42:52 +020010180 struct intel_encoder *intel_encoder;
10181 struct intel_crtc *intel_crtc;
10182 struct drm_connector *connector;
10183
Daniel Vetterba41c0de2014-11-03 15:04:55 +010010184 intel_shared_dpll_commit(dev_priv);
10185
Damien Lespiaub2784e12014-08-05 11:29:37 +010010186 for_each_intel_encoder(dev, intel_encoder) {
Daniel Vetterea9d7582012-07-10 10:42:52 +020010187 if (!intel_encoder->base.crtc)
10188 continue;
10189
10190 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10191
10192 if (prepare_pipes & (1 << intel_crtc->pipe))
10193 intel_encoder->connectors_active = false;
10194 }
10195
10196 intel_modeset_commit_output_state(dev);
10197
Ville Syrjälä76688512014-01-10 11:28:06 +020010198 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010199 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010200 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010201 WARN_ON(intel_crtc->new_config &&
10202 intel_crtc->new_config != &intel_crtc->config);
10203 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010204 }
10205
10206 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10207 if (!connector->encoder || !connector->encoder->crtc)
10208 continue;
10209
10210 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10211
10212 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +020010213 struct drm_property *dpms_property =
10214 dev->mode_config.dpms_property;
10215
Daniel Vetterea9d7582012-07-10 10:42:52 +020010216 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -050010217 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +020010218 dpms_property,
10219 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010220
10221 intel_encoder = to_intel_encoder(connector->encoder);
10222 intel_encoder->connectors_active = true;
10223 }
10224 }
10225
10226}
10227
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010228static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010229{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010230 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010231
10232 if (clock1 == clock2)
10233 return true;
10234
10235 if (!clock1 || !clock2)
10236 return false;
10237
10238 diff = abs(clock1 - clock2);
10239
10240 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10241 return true;
10242
10243 return false;
10244}
10245
Daniel Vetter25c5b262012-07-08 22:08:04 +020010246#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10247 list_for_each_entry((intel_crtc), \
10248 &(dev)->mode_config.crtc_list, \
10249 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +020010250 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020010251
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010252static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010253intel_pipe_config_compare(struct drm_device *dev,
10254 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010255 struct intel_crtc_config *pipe_config)
10256{
Daniel Vetter66e985c2013-06-05 13:34:20 +020010257#define PIPE_CONF_CHECK_X(name) \
10258 if (current_config->name != pipe_config->name) { \
10259 DRM_ERROR("mismatch in " #name " " \
10260 "(expected 0x%08x, found 0x%08x)\n", \
10261 current_config->name, \
10262 pipe_config->name); \
10263 return false; \
10264 }
10265
Daniel Vetter08a24032013-04-19 11:25:34 +020010266#define PIPE_CONF_CHECK_I(name) \
10267 if (current_config->name != pipe_config->name) { \
10268 DRM_ERROR("mismatch in " #name " " \
10269 "(expected %i, found %i)\n", \
10270 current_config->name, \
10271 pipe_config->name); \
10272 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010010273 }
10274
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010275/* This is required for BDW+ where there is only one set of registers for
10276 * switching between high and low RR.
10277 * This macro can be used whenever a comparison has to be made between one
10278 * hw state and multiple sw state variables.
10279 */
10280#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10281 if ((current_config->name != pipe_config->name) && \
10282 (current_config->alt_name != pipe_config->name)) { \
10283 DRM_ERROR("mismatch in " #name " " \
10284 "(expected %i or %i, found %i)\n", \
10285 current_config->name, \
10286 current_config->alt_name, \
10287 pipe_config->name); \
10288 return false; \
10289 }
10290
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010291#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10292 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -070010293 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010294 "(expected %i, found %i)\n", \
10295 current_config->name & (mask), \
10296 pipe_config->name & (mask)); \
10297 return false; \
10298 }
10299
Ville Syrjälä5e550652013-09-06 23:29:07 +030010300#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10301 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10302 DRM_ERROR("mismatch in " #name " " \
10303 "(expected %i, found %i)\n", \
10304 current_config->name, \
10305 pipe_config->name); \
10306 return false; \
10307 }
10308
Daniel Vetterbb760062013-06-06 14:55:52 +020010309#define PIPE_CONF_QUIRK(quirk) \
10310 ((current_config->quirks | pipe_config->quirks) & (quirk))
10311
Daniel Vettereccb1402013-05-22 00:50:22 +020010312 PIPE_CONF_CHECK_I(cpu_transcoder);
10313
Daniel Vetter08a24032013-04-19 11:25:34 +020010314 PIPE_CONF_CHECK_I(has_pch_encoder);
10315 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +020010316 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10317 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10318 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10319 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10320 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +020010321
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010322 PIPE_CONF_CHECK_I(has_dp_encoder);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010323
10324 if (INTEL_INFO(dev)->gen < 8) {
10325 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10326 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10327 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10328 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10329 PIPE_CONF_CHECK_I(dp_m_n.tu);
10330
10331 if (current_config->has_drrs) {
10332 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10333 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10334 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10335 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10336 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10337 }
10338 } else {
10339 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10340 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10341 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10342 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10343 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10344 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010345
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010346 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10347 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10348 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10349 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10350 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10351 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10352
10353 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10354 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10355 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10356 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10357 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10358 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10359
Daniel Vetterc93f54c2013-06-27 19:47:19 +020010360 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +020010361 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020010362 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10363 IS_VALLEYVIEW(dev))
10364 PIPE_CONF_CHECK_I(limited_color_range);
Jesse Barnese43823e2014-11-05 14:26:08 -080010365 PIPE_CONF_CHECK_I(has_infoframe);
Daniel Vetter6c49f242013-06-06 12:45:25 +020010366
Daniel Vetter9ed109a2014-04-24 23:54:52 +020010367 PIPE_CONF_CHECK_I(has_audio);
10368
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010369 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10370 DRM_MODE_FLAG_INTERLACE);
10371
Daniel Vetterbb760062013-06-06 14:55:52 +020010372 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10373 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10374 DRM_MODE_FLAG_PHSYNC);
10375 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10376 DRM_MODE_FLAG_NHSYNC);
10377 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10378 DRM_MODE_FLAG_PVSYNC);
10379 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10380 DRM_MODE_FLAG_NVSYNC);
10381 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010382
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010383 PIPE_CONF_CHECK_I(pipe_src_w);
10384 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010385
Daniel Vetter99535992014-04-13 12:00:33 +020010386 /*
10387 * FIXME: BIOS likes to set up a cloned config with lvds+external
10388 * screen. Since we don't yet re-compute the pipe config when moving
10389 * just the lvds port away to another pipe the sw tracking won't match.
10390 *
10391 * Proper atomic modesets with recomputed global state will fix this.
10392 * Until then just don't check gmch state for inherited modes.
10393 */
10394 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10395 PIPE_CONF_CHECK_I(gmch_pfit.control);
10396 /* pfit ratios are autocomputed by the hw on gen4+ */
10397 if (INTEL_INFO(dev)->gen < 4)
10398 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10399 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10400 }
10401
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010402 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10403 if (current_config->pch_pfit.enabled) {
10404 PIPE_CONF_CHECK_I(pch_pfit.pos);
10405 PIPE_CONF_CHECK_I(pch_pfit.size);
10406 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010407
Jesse Barnese59150d2014-01-07 13:30:45 -080010408 /* BDW+ don't expose a synchronous way to read the state */
10409 if (IS_HASWELL(dev))
10410 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010411
Ville Syrjälä282740f2013-09-04 18:30:03 +030010412 PIPE_CONF_CHECK_I(double_wide);
10413
Daniel Vetter26804af2014-06-25 22:01:55 +030010414 PIPE_CONF_CHECK_X(ddi_pll_sel);
10415
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010416 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010417 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010418 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010419 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10420 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010421 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010422
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010423 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10424 PIPE_CONF_CHECK_I(pipe_bpp);
10425
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010426 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10427 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010428
Daniel Vetter66e985c2013-06-05 13:34:20 +020010429#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010430#undef PIPE_CONF_CHECK_I
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010431#undef PIPE_CONF_CHECK_I_ALT
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010432#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010433#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010434#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010435
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010436 return true;
10437}
10438
Damien Lespiau08db6652014-11-04 17:06:52 +000010439static void check_wm_state(struct drm_device *dev)
10440{
10441 struct drm_i915_private *dev_priv = dev->dev_private;
10442 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10443 struct intel_crtc *intel_crtc;
10444 int plane;
10445
10446 if (INTEL_INFO(dev)->gen < 9)
10447 return;
10448
10449 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10450 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10451
10452 for_each_intel_crtc(dev, intel_crtc) {
10453 struct skl_ddb_entry *hw_entry, *sw_entry;
10454 const enum pipe pipe = intel_crtc->pipe;
10455
10456 if (!intel_crtc->active)
10457 continue;
10458
10459 /* planes */
10460 for_each_plane(pipe, plane) {
10461 hw_entry = &hw_ddb.plane[pipe][plane];
10462 sw_entry = &sw_ddb->plane[pipe][plane];
10463
10464 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10465 continue;
10466
10467 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10468 "(expected (%u,%u), found (%u,%u))\n",
10469 pipe_name(pipe), plane + 1,
10470 sw_entry->start, sw_entry->end,
10471 hw_entry->start, hw_entry->end);
10472 }
10473
10474 /* cursor */
10475 hw_entry = &hw_ddb.cursor[pipe];
10476 sw_entry = &sw_ddb->cursor[pipe];
10477
10478 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10479 continue;
10480
10481 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10482 "(expected (%u,%u), found (%u,%u))\n",
10483 pipe_name(pipe),
10484 sw_entry->start, sw_entry->end,
10485 hw_entry->start, hw_entry->end);
10486 }
10487}
10488
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010489static void
10490check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010491{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010492 struct intel_connector *connector;
10493
10494 list_for_each_entry(connector, &dev->mode_config.connector_list,
10495 base.head) {
10496 /* This also checks the encoder/connector hw state with the
10497 * ->get_hw_state callbacks. */
10498 intel_connector_check_state(connector);
10499
10500 WARN(&connector->new_encoder->base != connector->base.encoder,
10501 "connector's staged encoder doesn't match current encoder\n");
10502 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010503}
10504
10505static void
10506check_encoder_state(struct drm_device *dev)
10507{
10508 struct intel_encoder *encoder;
10509 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010510
Damien Lespiaub2784e12014-08-05 11:29:37 +010010511 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010512 bool enabled = false;
10513 bool active = false;
10514 enum pipe pipe, tracked_pipe;
10515
10516 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10517 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030010518 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010519
10520 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10521 "encoder's stage crtc doesn't match current crtc\n");
10522 WARN(encoder->connectors_active && !encoder->base.crtc,
10523 "encoder's active_connectors set, but no crtc\n");
10524
10525 list_for_each_entry(connector, &dev->mode_config.connector_list,
10526 base.head) {
10527 if (connector->base.encoder != &encoder->base)
10528 continue;
10529 enabled = true;
10530 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10531 active = true;
10532 }
Dave Airlie0e32b392014-05-02 14:02:48 +100010533 /*
10534 * for MST connectors if we unplug the connector is gone
10535 * away but the encoder is still connected to a crtc
10536 * until a modeset happens in response to the hotplug.
10537 */
10538 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10539 continue;
10540
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010541 WARN(!!encoder->base.crtc != enabled,
10542 "encoder's enabled state mismatch "
10543 "(expected %i, found %i)\n",
10544 !!encoder->base.crtc, enabled);
10545 WARN(active && !encoder->base.crtc,
10546 "active encoder with no crtc\n");
10547
10548 WARN(encoder->connectors_active != active,
10549 "encoder's computed active state doesn't match tracked active state "
10550 "(expected %i, found %i)\n", active, encoder->connectors_active);
10551
10552 active = encoder->get_hw_state(encoder, &pipe);
10553 WARN(active != encoder->connectors_active,
10554 "encoder's hw state doesn't match sw tracking "
10555 "(expected %i, found %i)\n",
10556 encoder->connectors_active, active);
10557
10558 if (!encoder->base.crtc)
10559 continue;
10560
10561 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10562 WARN(active && pipe != tracked_pipe,
10563 "active encoder's pipe doesn't match"
10564 "(expected %i, found %i)\n",
10565 tracked_pipe, pipe);
10566
10567 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010568}
10569
10570static void
10571check_crtc_state(struct drm_device *dev)
10572{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010573 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010574 struct intel_crtc *crtc;
10575 struct intel_encoder *encoder;
10576 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010577
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010578 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010579 bool enabled = false;
10580 bool active = false;
10581
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010582 memset(&pipe_config, 0, sizeof(pipe_config));
10583
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010584 DRM_DEBUG_KMS("[CRTC:%d]\n",
10585 crtc->base.base.id);
10586
10587 WARN(crtc->active && !crtc->base.enabled,
10588 "active crtc, but not enabled in sw tracking\n");
10589
Damien Lespiaub2784e12014-08-05 11:29:37 +010010590 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010591 if (encoder->base.crtc != &crtc->base)
10592 continue;
10593 enabled = true;
10594 if (encoder->connectors_active)
10595 active = true;
10596 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010597
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010598 WARN(active != crtc->active,
10599 "crtc's computed active state doesn't match tracked active state "
10600 "(expected %i, found %i)\n", active, crtc->active);
10601 WARN(enabled != crtc->base.enabled,
10602 "crtc's computed enabled state doesn't match tracked enabled state "
10603 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10604
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010605 active = dev_priv->display.get_pipe_config(crtc,
10606 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010607
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030010608 /* hw state is inconsistent with the pipe quirk */
10609 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10610 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetterd62cf622013-05-29 10:41:29 +020010611 active = crtc->active;
10612
Damien Lespiaub2784e12014-08-05 11:29:37 +010010613 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010614 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010615 if (encoder->base.crtc != &crtc->base)
10616 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010617 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010618 encoder->get_config(encoder, &pipe_config);
10619 }
10620
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010621 WARN(crtc->active != active,
10622 "crtc active state doesn't match with hw state "
10623 "(expected %i, found %i)\n", crtc->active, active);
10624
Daniel Vetterc0b03412013-05-28 12:05:54 +020010625 if (active &&
10626 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10627 WARN(1, "pipe state doesn't match!\n");
10628 intel_dump_pipe_config(crtc, &pipe_config,
10629 "[hw state]");
10630 intel_dump_pipe_config(crtc, &crtc->config,
10631 "[sw state]");
10632 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010633 }
10634}
10635
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010636static void
10637check_shared_dpll_state(struct drm_device *dev)
10638{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010639 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010640 struct intel_crtc *crtc;
10641 struct intel_dpll_hw_state dpll_hw_state;
10642 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010643
10644 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10645 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10646 int enabled_crtcs = 0, active_crtcs = 0;
10647 bool active;
10648
10649 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10650
10651 DRM_DEBUG_KMS("%s\n", pll->name);
10652
10653 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10654
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010655 WARN(pll->active > hweight32(pll->config.crtc_mask),
Daniel Vetter53589012013-06-05 13:34:16 +020010656 "more active pll users than references: %i vs %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010657 pll->active, hweight32(pll->config.crtc_mask));
Daniel Vetter53589012013-06-05 13:34:16 +020010658 WARN(pll->active && !pll->on,
10659 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010660 WARN(pll->on && !pll->active,
10661 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010662 WARN(pll->on != active,
10663 "pll on state mismatch (expected %i, found %i)\n",
10664 pll->on, active);
10665
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010666 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010667 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10668 enabled_crtcs++;
10669 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10670 active_crtcs++;
10671 }
10672 WARN(pll->active != active_crtcs,
10673 "pll active crtcs mismatch (expected %i, found %i)\n",
10674 pll->active, active_crtcs);
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010675 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
Daniel Vetter53589012013-06-05 13:34:16 +020010676 "pll enabled crtcs mismatch (expected %i, found %i)\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010677 hweight32(pll->config.crtc_mask), enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010678
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010679 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
Daniel Vetter66e985c2013-06-05 13:34:20 +020010680 sizeof(dpll_hw_state)),
10681 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010682 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010683}
10684
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010685void
10686intel_modeset_check_state(struct drm_device *dev)
10687{
Damien Lespiau08db6652014-11-04 17:06:52 +000010688 check_wm_state(dev);
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010689 check_connector_state(dev);
10690 check_encoder_state(dev);
10691 check_crtc_state(dev);
10692 check_shared_dpll_state(dev);
10693}
10694
Ville Syrjälä18442d02013-09-13 16:00:08 +030010695void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10696 int dotclock)
10697{
10698 /*
10699 * FDI already provided one idea for the dotclock.
10700 * Yell if the encoder disagrees.
10701 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010702 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010703 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010704 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010705}
10706
Ville Syrjälä80715b22014-05-15 20:23:23 +030010707static void update_scanline_offset(struct intel_crtc *crtc)
10708{
10709 struct drm_device *dev = crtc->base.dev;
10710
10711 /*
10712 * The scanline counter increments at the leading edge of hsync.
10713 *
10714 * On most platforms it starts counting from vtotal-1 on the
10715 * first active line. That means the scanline counter value is
10716 * always one less than what we would expect. Ie. just after
10717 * start of vblank, which also occurs at start of hsync (on the
10718 * last active line), the scanline counter will read vblank_start-1.
10719 *
10720 * On gen2 the scanline counter starts counting from 1 instead
10721 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10722 * to keep the value positive), instead of adding one.
10723 *
10724 * On HSW+ the behaviour of the scanline counter depends on the output
10725 * type. For DP ports it behaves like most other platforms, but on HDMI
10726 * there's an extra 1 line difference. So we need to add two instead of
10727 * one to the value.
10728 */
10729 if (IS_GEN2(dev)) {
10730 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10731 int vtotal;
10732
10733 vtotal = mode->crtc_vtotal;
10734 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10735 vtotal /= 2;
10736
10737 crtc->scanline_offset = vtotal - 1;
10738 } else if (HAS_DDI(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +030010739 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
Ville Syrjälä80715b22014-05-15 20:23:23 +030010740 crtc->scanline_offset = 2;
10741 } else
10742 crtc->scanline_offset = 1;
10743}
10744
Jesse Barnes7f271262014-11-05 14:26:06 -080010745static struct intel_crtc_config *
10746intel_modeset_compute_config(struct drm_crtc *crtc,
10747 struct drm_display_mode *mode,
10748 struct drm_framebuffer *fb,
10749 unsigned *modeset_pipes,
10750 unsigned *prepare_pipes,
10751 unsigned *disable_pipes)
10752{
10753 struct intel_crtc_config *pipe_config = NULL;
10754
10755 intel_modeset_affected_pipes(crtc, modeset_pipes,
10756 prepare_pipes, disable_pipes);
10757
10758 if ((*modeset_pipes) == 0)
10759 goto out;
10760
10761 /*
10762 * Note this needs changes when we start tracking multiple modes
10763 * and crtcs. At that point we'll need to compute the whole config
10764 * (i.e. one pipe_config for each crtc) rather than just the one
10765 * for this crtc.
10766 */
10767 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10768 if (IS_ERR(pipe_config)) {
10769 goto out;
10770 }
10771 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10772 "[modeset]");
10773 to_intel_crtc(crtc)->new_config = pipe_config;
10774
10775out:
10776 return pipe_config;
10777}
10778
Daniel Vetterf30da182013-04-11 20:22:50 +020010779static int __intel_set_mode(struct drm_crtc *crtc,
10780 struct drm_display_mode *mode,
Jesse Barnes7f271262014-11-05 14:26:06 -080010781 int x, int y, struct drm_framebuffer *fb,
10782 struct intel_crtc_config *pipe_config,
10783 unsigned modeset_pipes,
10784 unsigned prepare_pipes,
10785 unsigned disable_pipes)
Daniel Vettera6778b32012-07-02 09:56:42 +020010786{
10787 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010788 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010789 struct drm_display_mode *saved_mode;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010790 struct intel_crtc *intel_crtc;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010791 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010792
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010793 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010794 if (!saved_mode)
10795 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010796
Tim Gardner3ac18232012-12-07 07:54:26 -070010797 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010798
Jesse Barnes30a970c2013-11-04 13:48:12 -080010799 /*
10800 * See if the config requires any additional preparation, e.g.
10801 * to adjust global state with pipes off. We need to do this
10802 * here so we can get the modeset_pipe updated config for the new
10803 * mode set on this crtc. For other crtcs we need to use the
10804 * adjusted_mode bits in the crtc directly.
10805 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010806 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010807 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010808
Ville Syrjäläc164f832013-11-05 22:34:12 +020010809 /* may have added more to prepare_pipes than we should */
10810 prepare_pipes &= ~disable_pipes;
10811 }
10812
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +020010813 if (dev_priv->display.crtc_compute_clock) {
10814 unsigned clear_pipes = modeset_pipes | disable_pipes;
10815
10816 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10817 if (ret)
10818 goto done;
10819
10820 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10821 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10822 if (ret) {
10823 intel_shared_dpll_abort_config(dev_priv);
10824 goto done;
10825 }
10826 }
10827 }
10828
Daniel Vetter460da9162013-03-27 00:44:51 +010010829 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10830 intel_crtc_disable(&intel_crtc->base);
10831
Daniel Vetterea9d7582012-07-10 10:42:52 +020010832 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10833 if (intel_crtc->base.enabled)
10834 dev_priv->display.crtc_disable(&intel_crtc->base);
10835 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010836
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010837 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10838 * to set it here already despite that we pass it down the callchain.
Jesse Barnes7f271262014-11-05 14:26:06 -080010839 *
10840 * Note we'll need to fix this up when we start tracking multiple
10841 * pipes; here we assume a single modeset_pipe and only track the
10842 * single crtc and mode.
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010843 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010844 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010845 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010846 /* mode_set/enable/disable functions rely on a correct pipe
10847 * config. */
10848 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010849 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010850
10851 /*
10852 * Calculate and store various constants which
10853 * are later needed by vblank and swap-completion
10854 * timestamping. They are derived from true hwmode.
10855 */
10856 drm_calc_timestamping_constants(crtc,
10857 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010858 }
Daniel Vetter7758a112012-07-08 19:40:39 +020010859
Daniel Vetterea9d7582012-07-10 10:42:52 +020010860 /* Only after disabling all output pipelines that will be changed can we
10861 * update the the output configuration. */
10862 intel_modeset_update_state(dev, prepare_pipes);
10863
Ville Syrjälä50f6e502014-11-06 14:49:12 +020010864 modeset_update_crtc_power_domains(dev);
Daniel Vetter47fab732012-10-26 10:58:18 +020010865
Daniel Vettera6778b32012-07-02 09:56:42 +020010866 /* Set up the DPLL and any encoders state that needs to adjust or depend
10867 * on the DPLL.
10868 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020010869 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070010870 struct drm_framebuffer *old_fb = crtc->primary->fb;
10871 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10872 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Daniel Vetter4c107942014-04-24 23:55:05 +020010873
10874 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +000010875 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
Daniel Vetter4c107942014-04-24 23:55:05 +020010876 if (ret != 0) {
10877 DRM_ERROR("pin & fence failed\n");
10878 mutex_unlock(&dev->struct_mutex);
10879 goto done;
10880 }
Matt Roper2ff8fde2014-07-08 07:50:07 -070010881 if (old_fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020010882 intel_unpin_fb_obj(old_obj);
Daniel Vettera071fa02014-06-18 23:28:09 +020010883 i915_gem_track_fb(old_obj, obj,
10884 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Daniel Vetter4c107942014-04-24 23:55:05 +020010885 mutex_unlock(&dev->struct_mutex);
10886
10887 crtc->primary->fb = fb;
10888 crtc->x = x;
10889 crtc->y = y;
Daniel Vettera6778b32012-07-02 09:56:42 +020010890 }
10891
10892 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030010893 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10894 update_scanline_offset(intel_crtc);
10895
Daniel Vetter25c5b262012-07-08 22:08:04 +020010896 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030010897 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010898
Daniel Vettera6778b32012-07-02 09:56:42 +020010899 /* FIXME: add subpixel order */
10900done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010901 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070010902 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010903
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010904 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070010905 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020010906 return ret;
10907}
10908
Jesse Barnes7f271262014-11-05 14:26:06 -080010909static int intel_set_mode_pipes(struct drm_crtc *crtc,
10910 struct drm_display_mode *mode,
10911 int x, int y, struct drm_framebuffer *fb,
10912 struct intel_crtc_config *pipe_config,
10913 unsigned modeset_pipes,
10914 unsigned prepare_pipes,
10915 unsigned disable_pipes)
10916{
10917 int ret;
10918
10919 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
10920 prepare_pipes, disable_pipes);
10921
10922 if (ret == 0)
10923 intel_modeset_check_state(crtc->dev);
10924
10925 return ret;
10926}
10927
Damien Lespiaue7457a92013-08-08 22:28:59 +010010928static int intel_set_mode(struct drm_crtc *crtc,
10929 struct drm_display_mode *mode,
10930 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020010931{
Jesse Barnes7f271262014-11-05 14:26:06 -080010932 struct intel_crtc_config *pipe_config;
10933 unsigned modeset_pipes, prepare_pipes, disable_pipes;
Daniel Vetterf30da182013-04-11 20:22:50 +020010934
Jesse Barnes7f271262014-11-05 14:26:06 -080010935 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
10936 &modeset_pipes,
10937 &prepare_pipes,
10938 &disable_pipes);
Daniel Vetterf30da182013-04-11 20:22:50 +020010939
Jesse Barnes7f271262014-11-05 14:26:06 -080010940 if (IS_ERR(pipe_config))
10941 return PTR_ERR(pipe_config);
Daniel Vetterf30da182013-04-11 20:22:50 +020010942
Jesse Barnes7f271262014-11-05 14:26:06 -080010943 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
10944 modeset_pipes, prepare_pipes,
10945 disable_pipes);
Daniel Vetterf30da182013-04-11 20:22:50 +020010946}
10947
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010948void intel_crtc_restore_mode(struct drm_crtc *crtc)
10949{
Matt Roperf4510a22014-04-01 15:22:40 -070010950 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010951}
10952
Daniel Vetter25c5b262012-07-08 22:08:04 +020010953#undef for_each_intel_crtc_masked
10954
Daniel Vetterd9e55602012-07-04 22:16:09 +020010955static void intel_set_config_free(struct intel_set_config *config)
10956{
10957 if (!config)
10958 return;
10959
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010960 kfree(config->save_connector_encoders);
10961 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020010962 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020010963 kfree(config);
10964}
10965
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010966static int intel_set_config_save_state(struct drm_device *dev,
10967 struct intel_set_config *config)
10968{
Ville Syrjälä76688512014-01-10 11:28:06 +020010969 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010970 struct drm_encoder *encoder;
10971 struct drm_connector *connector;
10972 int count;
10973
Ville Syrjälä76688512014-01-10 11:28:06 +020010974 config->save_crtc_enabled =
10975 kcalloc(dev->mode_config.num_crtc,
10976 sizeof(bool), GFP_KERNEL);
10977 if (!config->save_crtc_enabled)
10978 return -ENOMEM;
10979
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010980 config->save_encoder_crtcs =
10981 kcalloc(dev->mode_config.num_encoder,
10982 sizeof(struct drm_crtc *), GFP_KERNEL);
10983 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010984 return -ENOMEM;
10985
Daniel Vetter1aa4b622012-07-05 16:20:48 +020010986 config->save_connector_encoders =
10987 kcalloc(dev->mode_config.num_connector,
10988 sizeof(struct drm_encoder *), GFP_KERNEL);
10989 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020010990 return -ENOMEM;
10991
10992 /* Copy data. Note that driver private data is not affected.
10993 * Should anything bad happen only the expected state is
10994 * restored, not the drivers personal bookkeeping.
10995 */
10996 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010010997 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010998 config->save_crtc_enabled[count++] = crtc->enabled;
10999 }
11000
11001 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011002 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011003 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011004 }
11005
11006 count = 0;
11007 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011008 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011009 }
11010
11011 return 0;
11012}
11013
11014static void intel_set_config_restore_state(struct drm_device *dev,
11015 struct intel_set_config *config)
11016{
Ville Syrjälä76688512014-01-10 11:28:06 +020011017 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020011018 struct intel_encoder *encoder;
11019 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011020 int count;
11021
11022 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011023 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011024 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011025
11026 if (crtc->new_enabled)
11027 crtc->new_config = &crtc->config;
11028 else
11029 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011030 }
11031
11032 count = 0;
Damien Lespiaub2784e12014-08-05 11:29:37 +010011033 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011034 encoder->new_crtc =
11035 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011036 }
11037
11038 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011039 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11040 connector->new_encoder =
11041 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011042 }
11043}
11044
Imre Deake3de42b2013-05-03 19:44:07 +020011045static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010011046is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020011047{
11048 int i;
11049
Chris Wilson2e57f472013-07-17 12:14:40 +010011050 if (set->num_connectors == 0)
11051 return false;
11052
11053 if (WARN_ON(set->connectors == NULL))
11054 return false;
11055
11056 for (i = 0; i < set->num_connectors; i++)
11057 if (set->connectors[i]->encoder &&
11058 set->connectors[i]->encoder->crtc == set->crtc &&
11059 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020011060 return true;
11061
11062 return false;
11063}
11064
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011065static void
11066intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11067 struct intel_set_config *config)
11068{
11069
11070 /* We should be able to check here if the fb has the same properties
11071 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010011072 if (is_crtc_connector_off(set)) {
11073 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070011074 } else if (set->crtc->primary->fb != set->fb) {
Matt Roper3b150f02014-05-29 08:06:53 -070011075 /*
11076 * If we have no fb, we can only flip as long as the crtc is
11077 * active, otherwise we need a full mode set. The crtc may
11078 * be active if we've only disabled the primary plane, or
11079 * in fastboot situations.
11080 */
Matt Roperf4510a22014-04-01 15:22:40 -070011081 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011082 struct intel_crtc *intel_crtc =
11083 to_intel_crtc(set->crtc);
11084
Matt Roper3b150f02014-05-29 08:06:53 -070011085 if (intel_crtc->active) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011086 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11087 config->fb_changed = true;
11088 } else {
11089 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11090 config->mode_changed = true;
11091 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011092 } else if (set->fb == NULL) {
11093 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010011094 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070011095 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011096 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011097 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011098 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011099 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011100 }
11101
Daniel Vetter835c5872012-07-10 18:11:08 +020011102 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011103 config->fb_changed = true;
11104
11105 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11106 DRM_DEBUG_KMS("modes are different, full mode set\n");
11107 drm_mode_debug_printmodeline(&set->crtc->mode);
11108 drm_mode_debug_printmodeline(set->mode);
11109 config->mode_changed = true;
11110 }
Chris Wilsona1d95702013-08-13 18:48:47 +010011111
11112 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11113 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011114}
11115
Daniel Vetter2e431052012-07-04 22:42:15 +020011116static int
Daniel Vetter9a935852012-07-05 22:34:27 +020011117intel_modeset_stage_output_state(struct drm_device *dev,
11118 struct drm_mode_set *set,
11119 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020011120{
Daniel Vetter9a935852012-07-05 22:34:27 +020011121 struct intel_connector *connector;
11122 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020011123 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030011124 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020011125
Damien Lespiau9abdda72013-02-13 13:29:23 +000011126 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020011127 * of connectors. For paranoia, double-check this. */
11128 WARN_ON(!set->fb && (set->num_connectors != 0));
11129 WARN_ON(set->fb && (set->num_connectors == 0));
11130
Daniel Vetter9a935852012-07-05 22:34:27 +020011131 list_for_each_entry(connector, &dev->mode_config.connector_list,
11132 base.head) {
11133 /* Otherwise traverse passed in connector list and get encoders
11134 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020011135 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011136 if (set->connectors[ro] == &connector->base) {
Dave Airlie0e32b392014-05-02 14:02:48 +100011137 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
Daniel Vetter50f56112012-07-02 09:35:43 +020011138 break;
11139 }
11140 }
11141
Daniel Vetter9a935852012-07-05 22:34:27 +020011142 /* If we disable the crtc, disable all its connectors. Also, if
11143 * the connector is on the changing crtc but not on the new
11144 * connector list, disable it. */
11145 if ((!set->fb || ro == set->num_connectors) &&
11146 connector->base.encoder &&
11147 connector->base.encoder->crtc == set->crtc) {
11148 connector->new_encoder = NULL;
11149
11150 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11151 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011152 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020011153 }
11154
11155
11156 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011157 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011158 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011159 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011160 }
11161 /* connector->new_encoder is now updated for all connectors. */
11162
11163 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020011164 list_for_each_entry(connector, &dev->mode_config.connector_list,
11165 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011166 struct drm_crtc *new_crtc;
11167
Daniel Vetter9a935852012-07-05 22:34:27 +020011168 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020011169 continue;
11170
Daniel Vetter9a935852012-07-05 22:34:27 +020011171 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020011172
11173 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011174 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020011175 new_crtc = set->crtc;
11176 }
11177
11178 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010011179 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11180 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011181 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020011182 }
Dave Airlie0e32b392014-05-02 14:02:48 +100011183 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
Daniel Vetter9a935852012-07-05 22:34:27 +020011184
11185 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11186 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011187 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020011188 new_crtc->base.id);
11189 }
11190
11191 /* Check for any encoders that needs to be disabled. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010011192 for_each_intel_encoder(dev, encoder) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011193 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011194 list_for_each_entry(connector,
11195 &dev->mode_config.connector_list,
11196 base.head) {
11197 if (connector->new_encoder == encoder) {
11198 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011199 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020011200 }
11201 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011202
11203 if (num_connectors == 0)
11204 encoder->new_crtc = NULL;
11205 else if (num_connectors > 1)
11206 return -EINVAL;
11207
Daniel Vetter9a935852012-07-05 22:34:27 +020011208 /* Only now check for crtc changes so we don't miss encoders
11209 * that will be disabled. */
11210 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011211 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011212 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011213 }
11214 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011215 /* Now we've also updated encoder->new_crtc for all encoders. */
Dave Airlie0e32b392014-05-02 14:02:48 +100011216 list_for_each_entry(connector, &dev->mode_config.connector_list,
11217 base.head) {
11218 if (connector->new_encoder)
11219 if (connector->new_encoder != connector->encoder)
11220 connector->encoder = connector->new_encoder;
11221 }
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011222 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011223 crtc->new_enabled = false;
11224
Damien Lespiaub2784e12014-08-05 11:29:37 +010011225 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011226 if (encoder->new_crtc == crtc) {
11227 crtc->new_enabled = true;
11228 break;
11229 }
11230 }
11231
11232 if (crtc->new_enabled != crtc->base.enabled) {
11233 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11234 crtc->new_enabled ? "en" : "dis");
11235 config->mode_changed = true;
11236 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011237
11238 if (crtc->new_enabled)
11239 crtc->new_config = &crtc->config;
11240 else
11241 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011242 }
11243
Daniel Vetter2e431052012-07-04 22:42:15 +020011244 return 0;
11245}
11246
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011247static void disable_crtc_nofb(struct intel_crtc *crtc)
11248{
11249 struct drm_device *dev = crtc->base.dev;
11250 struct intel_encoder *encoder;
11251 struct intel_connector *connector;
11252
11253 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11254 pipe_name(crtc->pipe));
11255
11256 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11257 if (connector->new_encoder &&
11258 connector->new_encoder->new_crtc == crtc)
11259 connector->new_encoder = NULL;
11260 }
11261
Damien Lespiaub2784e12014-08-05 11:29:37 +010011262 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011263 if (encoder->new_crtc == crtc)
11264 encoder->new_crtc = NULL;
11265 }
11266
11267 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011268 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011269}
11270
Daniel Vetter2e431052012-07-04 22:42:15 +020011271static int intel_crtc_set_config(struct drm_mode_set *set)
11272{
11273 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020011274 struct drm_mode_set save_set;
11275 struct intel_set_config *config;
Jesse Barnes50f52752014-11-07 13:11:00 -080011276 struct intel_crtc_config *pipe_config;
11277 unsigned modeset_pipes, prepare_pipes, disable_pipes;
Daniel Vetter2e431052012-07-04 22:42:15 +020011278 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020011279
Daniel Vetter8d3e3752012-07-05 16:09:09 +020011280 BUG_ON(!set);
11281 BUG_ON(!set->crtc);
11282 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020011283
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010011284 /* Enforce sane interface api - has been abused by the fb helper. */
11285 BUG_ON(!set->mode && set->fb);
11286 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020011287
Daniel Vetter2e431052012-07-04 22:42:15 +020011288 if (set->fb) {
11289 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11290 set->crtc->base.id, set->fb->base.id,
11291 (int)set->num_connectors, set->x, set->y);
11292 } else {
11293 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020011294 }
11295
11296 dev = set->crtc->dev;
11297
11298 ret = -ENOMEM;
11299 config = kzalloc(sizeof(*config), GFP_KERNEL);
11300 if (!config)
11301 goto out_config;
11302
11303 ret = intel_set_config_save_state(dev, config);
11304 if (ret)
11305 goto out_config;
11306
11307 save_set.crtc = set->crtc;
11308 save_set.mode = &set->crtc->mode;
11309 save_set.x = set->crtc->x;
11310 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070011311 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020011312
11313 /* Compute whether we need a full modeset, only an fb base update or no
11314 * change at all. In the future we might also check whether only the
11315 * mode changed, e.g. for LVDS where we only change the panel fitter in
11316 * such cases. */
11317 intel_set_config_compute_mode_changes(set, config);
11318
Daniel Vetter9a935852012-07-05 22:34:27 +020011319 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020011320 if (ret)
11321 goto fail;
11322
Jesse Barnes50f52752014-11-07 13:11:00 -080011323 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11324 set->fb,
11325 &modeset_pipes,
11326 &prepare_pipes,
11327 &disable_pipes);
Jesse Barnes20664592014-11-05 14:26:09 -080011328 if (IS_ERR(pipe_config)) {
Jesse Barnes50f52752014-11-07 13:11:00 -080011329 goto fail;
Jesse Barnes20664592014-11-05 14:26:09 -080011330 } else if (pipe_config) {
11331 if (to_intel_crtc(set->crtc)->new_config->has_audio !=
11332 to_intel_crtc(set->crtc)->config.has_audio)
11333 config->mode_changed = true;
11334
11335 /* Force mode sets for any infoframe stuff */
11336 if (to_intel_crtc(set->crtc)->new_config->has_infoframe ||
11337 to_intel_crtc(set->crtc)->config.has_infoframe)
11338 config->mode_changed = true;
11339 }
Jesse Barnes50f52752014-11-07 13:11:00 -080011340
11341 /* set_mode will free it in the mode_changed case */
11342 if (!config->mode_changed)
11343 kfree(pipe_config);
11344
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011345 if (config->mode_changed) {
Jesse Barnes50f52752014-11-07 13:11:00 -080011346 ret = intel_set_mode_pipes(set->crtc, set->mode,
11347 set->x, set->y, set->fb, pipe_config,
11348 modeset_pipes, prepare_pipes,
11349 disable_pipes);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011350 } else if (config->fb_changed) {
Matt Roper3b150f02014-05-29 08:06:53 -070011351 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11352
Ville Syrjälä4878cae2013-02-18 19:08:48 +020011353 intel_crtc_wait_for_pending_flips(set->crtc);
11354
Daniel Vetter4f660f42012-07-02 09:47:37 +020011355 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020011356 set->x, set->y, set->fb);
Matt Roper3b150f02014-05-29 08:06:53 -070011357
11358 /*
11359 * We need to make sure the primary plane is re-enabled if it
11360 * has previously been turned off.
11361 */
11362 if (!intel_crtc->primary_enabled && ret == 0) {
11363 WARN_ON(!intel_crtc->active);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011364 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
Matt Roper3b150f02014-05-29 08:06:53 -070011365 }
11366
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011367 /*
11368 * In the fastboot case this may be our only check of the
11369 * state after boot. It would be better to only do it on
11370 * the first update, but we don't have a nice way of doing that
11371 * (and really, set_config isn't used much for high freq page
11372 * flipping, so increasing its cost here shouldn't be a big
11373 * deal).
11374 */
Jani Nikulad330a952014-01-21 11:24:25 +020011375 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011376 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020011377 }
11378
Chris Wilson2d05eae2013-05-03 17:36:25 +010011379 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020011380 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11381 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020011382fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010011383 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011384
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011385 /*
11386 * HACK: if the pipe was on, but we didn't have a framebuffer,
11387 * force the pipe off to avoid oopsing in the modeset code
11388 * due to fb==NULL. This should only happen during boot since
11389 * we don't yet reconstruct the FB from the hardware state.
11390 */
11391 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11392 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11393
Chris Wilson2d05eae2013-05-03 17:36:25 +010011394 /* Try to restore the config */
11395 if (config->mode_changed &&
11396 intel_set_mode(save_set.crtc, save_set.mode,
11397 save_set.x, save_set.y, save_set.fb))
11398 DRM_ERROR("failed to restore config after modeset failure\n");
11399 }
Daniel Vetter50f56112012-07-02 09:35:43 +020011400
Daniel Vetterd9e55602012-07-04 22:16:09 +020011401out_config:
11402 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011403 return ret;
11404}
11405
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011406static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011407 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020011408 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011409 .destroy = intel_crtc_destroy,
11410 .page_flip = intel_crtc_page_flip,
11411};
11412
Daniel Vetter53589012013-06-05 13:34:16 +020011413static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11414 struct intel_shared_dpll *pll,
11415 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011416{
Daniel Vetter53589012013-06-05 13:34:16 +020011417 uint32_t val;
11418
Daniel Vetterf458ebb2014-09-30 10:56:39 +020011419 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030011420 return false;
11421
Daniel Vetter53589012013-06-05 13:34:16 +020011422 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020011423 hw_state->dpll = val;
11424 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11425 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020011426
11427 return val & DPLL_VCO_ENABLE;
11428}
11429
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011430static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11431 struct intel_shared_dpll *pll)
11432{
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011433 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11434 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011435}
11436
Daniel Vettere7b903d2013-06-05 13:34:14 +020011437static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11438 struct intel_shared_dpll *pll)
11439{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011440 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020011441 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020011442
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011443 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011444
11445 /* Wait for the clocks to stabilize. */
11446 POSTING_READ(PCH_DPLL(pll->id));
11447 udelay(150);
11448
11449 /* The pixel multiplier can only be updated once the
11450 * DPLL is enabled and the clocks are stable.
11451 *
11452 * So write it again.
11453 */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011454 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011455 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011456 udelay(200);
11457}
11458
11459static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11460 struct intel_shared_dpll *pll)
11461{
11462 struct drm_device *dev = dev_priv->dev;
11463 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011464
11465 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011466 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020011467 if (intel_crtc_to_shared_dpll(crtc) == pll)
11468 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11469 }
11470
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011471 I915_WRITE(PCH_DPLL(pll->id), 0);
11472 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011473 udelay(200);
11474}
11475
Daniel Vetter46edb022013-06-05 13:34:12 +020011476static char *ibx_pch_dpll_names[] = {
11477 "PCH DPLL A",
11478 "PCH DPLL B",
11479};
11480
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011481static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011482{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011483 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011484 int i;
11485
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011486 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011487
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011488 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020011489 dev_priv->shared_dplls[i].id = i;
11490 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011491 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011492 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11493 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020011494 dev_priv->shared_dplls[i].get_hw_state =
11495 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011496 }
11497}
11498
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011499static void intel_shared_dpll_init(struct drm_device *dev)
11500{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011501 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011502
Daniel Vetter9cd86932014-06-25 22:01:57 +030011503 if (HAS_DDI(dev))
11504 intel_ddi_pll_init(dev);
11505 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011506 ibx_pch_dpll_init(dev);
11507 else
11508 dev_priv->num_shared_dpll = 0;
11509
11510 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011511}
11512
Matt Roper465c1202014-05-29 08:06:54 -070011513static int
11514intel_primary_plane_disable(struct drm_plane *plane)
11515{
11516 struct drm_device *dev = plane->dev;
Matt Roper465c1202014-05-29 08:06:54 -070011517 struct intel_crtc *intel_crtc;
11518
11519 if (!plane->fb)
11520 return 0;
11521
11522 BUG_ON(!plane->crtc);
11523
11524 intel_crtc = to_intel_crtc(plane->crtc);
11525
11526 /*
11527 * Even though we checked plane->fb above, it's still possible that
11528 * the primary plane has been implicitly disabled because the crtc
11529 * coordinates given weren't visible, or because we detected
11530 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11531 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11532 * In either case, we need to unpin the FB and let the fb pointer get
11533 * updated, but otherwise we don't need to touch the hardware.
11534 */
11535 if (!intel_crtc->primary_enabled)
11536 goto disable_unpin;
11537
11538 intel_crtc_wait_for_pending_flips(plane->crtc);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011539 intel_disable_primary_hw_plane(plane, plane->crtc);
11540
Matt Roper465c1202014-05-29 08:06:54 -070011541disable_unpin:
Matt Roper4c345742014-07-09 16:22:10 -070011542 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011543 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
Daniel Vettera071fa02014-06-18 23:28:09 +020011544 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper2ff8fde2014-07-08 07:50:07 -070011545 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
Matt Roper4c345742014-07-09 16:22:10 -070011546 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011547 plane->fb = NULL;
11548
11549 return 0;
11550}
11551
11552static int
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011553intel_check_primary_plane(struct drm_plane *plane,
11554 struct intel_plane_state *state)
Matt Roper465c1202014-05-29 08:06:54 -070011555{
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011556 struct drm_crtc *crtc = state->crtc;
11557 struct drm_framebuffer *fb = state->fb;
11558 struct drm_rect *dest = &state->dst;
11559 struct drm_rect *src = &state->src;
11560 const struct drm_rect *clip = &state->clip;
11561
Gustavo Padovan3ead8bb2014-10-24 19:00:18 +010011562 return drm_plane_helper_check_update(plane, crtc, fb,
11563 src, dest, clip,
11564 DRM_PLANE_HELPER_NO_SCALING,
11565 DRM_PLANE_HELPER_NO_SCALING,
11566 false, true, &state->visible);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011567}
11568
11569static int
Gustavo Padovan14af2932014-10-24 14:51:31 +010011570intel_prepare_primary_plane(struct drm_plane *plane,
11571 struct intel_plane_state *state)
11572{
11573 struct drm_crtc *crtc = state->crtc;
11574 struct drm_framebuffer *fb = state->fb;
11575 struct drm_device *dev = crtc->dev;
11576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11577 enum pipe pipe = intel_crtc->pipe;
11578 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11579 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11580 int ret;
11581
11582 intel_crtc_wait_for_pending_flips(crtc);
11583
11584 if (intel_crtc_has_pending_flip(crtc)) {
11585 DRM_ERROR("pipe is still busy with an old pageflip\n");
11586 return -EBUSY;
11587 }
11588
11589 if (old_obj != obj) {
11590 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +000011591 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
Gustavo Padovan14af2932014-10-24 14:51:31 +010011592 if (ret == 0)
11593 i915_gem_track_fb(old_obj, obj,
11594 INTEL_FRONTBUFFER_PRIMARY(pipe));
11595 mutex_unlock(&dev->struct_mutex);
11596 if (ret != 0) {
11597 DRM_DEBUG_KMS("pin & fence failed\n");
11598 return ret;
11599 }
11600 }
11601
11602 return 0;
11603}
11604
11605static void
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011606intel_commit_primary_plane(struct drm_plane *plane,
11607 struct intel_plane_state *state)
11608{
11609 struct drm_crtc *crtc = state->crtc;
11610 struct drm_framebuffer *fb = state->fb;
Matt Roper465c1202014-05-29 08:06:54 -070011611 struct drm_device *dev = crtc->dev;
Sonika Jindal48404c12014-08-22 14:06:04 +053011612 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper465c1202014-05-29 08:06:54 -070011613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011614 enum pipe pipe = intel_crtc->pipe;
11615 struct drm_framebuffer *old_fb = plane->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -070011616 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11617 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
Sonika Jindalce54d852014-08-21 11:44:39 +053011618 struct intel_plane *intel_plane = to_intel_plane(plane);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011619 struct drm_rect *src = &state->src;
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011620
11621 crtc->primary->fb = fb;
11622 crtc->x = src->x1;
11623 crtc->y = src->y1;
11624
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011625 intel_plane->crtc_x = state->orig_dst.x1;
11626 intel_plane->crtc_y = state->orig_dst.y1;
11627 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11628 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11629 intel_plane->src_x = state->orig_src.x1;
11630 intel_plane->src_y = state->orig_src.y1;
11631 intel_plane->src_w = drm_rect_width(&state->orig_src);
11632 intel_plane->src_h = drm_rect_height(&state->orig_src);
Sonika Jindalce54d852014-08-21 11:44:39 +053011633 intel_plane->obj = obj;
Matt Roper465c1202014-05-29 08:06:54 -070011634
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011635 if (intel_crtc->active) {
11636 /*
11637 * FBC does not work on some platforms for rotated
11638 * planes, so disable it when rotation is not 0 and
11639 * update it when rotation is set back to 0.
11640 *
11641 * FIXME: This is redundant with the fbc update done in
11642 * the primary plane enable function except that that
11643 * one is done too late. We eventually need to unify
11644 * this.
11645 */
11646 if (intel_crtc->primary_enabled &&
11647 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11648 dev_priv->fbc.plane == intel_crtc->plane &&
11649 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11650 intel_disable_fbc(dev);
11651 }
11652
11653 if (state->visible) {
11654 bool was_enabled = intel_crtc->primary_enabled;
11655
11656 /* FIXME: kill this fastboot hack */
11657 intel_update_pipe_size(intel_crtc);
11658
11659 intel_crtc->primary_enabled = true;
11660
11661 dev_priv->display.update_primary_plane(crtc, plane->fb,
11662 crtc->x, crtc->y);
11663
11664 /*
11665 * BDW signals flip done immediately if the plane
11666 * is disabled, even if the plane enable is already
11667 * armed to occur at the next vblank :(
11668 */
11669 if (IS_BROADWELL(dev) && !was_enabled)
11670 intel_wait_for_vblank(dev, intel_crtc->pipe);
11671 } else {
11672 /*
11673 * If clipping results in a non-visible primary plane,
11674 * we'll disable the primary plane. Note that this is
11675 * a bit different than what happens if userspace
11676 * explicitly disables the plane by passing fb=0
11677 * because plane->fb still gets set and pinned.
11678 */
11679 intel_disable_primary_hw_plane(plane, crtc);
11680 }
11681
11682 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11683
11684 mutex_lock(&dev->struct_mutex);
11685 intel_update_fbc(dev);
11686 mutex_unlock(&dev->struct_mutex);
11687 }
11688
11689 if (old_fb && old_fb != fb) {
11690 if (intel_crtc->active)
11691 intel_wait_for_vblank(dev, intel_crtc->pipe);
11692
11693 mutex_lock(&dev->struct_mutex);
11694 intel_unpin_fb_obj(old_obj);
11695 mutex_unlock(&dev->struct_mutex);
11696 }
Matt Roper465c1202014-05-29 08:06:54 -070011697}
11698
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011699static int
11700intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11701 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11702 unsigned int crtc_w, unsigned int crtc_h,
11703 uint32_t src_x, uint32_t src_y,
11704 uint32_t src_w, uint32_t src_h)
11705{
11706 struct intel_plane_state state;
11707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11708 int ret;
11709
11710 state.crtc = crtc;
11711 state.fb = fb;
11712
11713 /* sample coordinates in 16.16 fixed point */
11714 state.src.x1 = src_x;
11715 state.src.x2 = src_x + src_w;
11716 state.src.y1 = src_y;
11717 state.src.y2 = src_y + src_h;
11718
11719 /* integer pixels */
11720 state.dst.x1 = crtc_x;
11721 state.dst.x2 = crtc_x + crtc_w;
11722 state.dst.y1 = crtc_y;
11723 state.dst.y2 = crtc_y + crtc_h;
11724
11725 state.clip.x1 = 0;
11726 state.clip.y1 = 0;
11727 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11728 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11729
11730 state.orig_src = state.src;
11731 state.orig_dst = state.dst;
11732
11733 ret = intel_check_primary_plane(plane, &state);
11734 if (ret)
11735 return ret;
11736
Gustavo Padovan14af2932014-10-24 14:51:31 +010011737 ret = intel_prepare_primary_plane(plane, &state);
11738 if (ret)
11739 return ret;
11740
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011741 intel_commit_primary_plane(plane, &state);
11742
11743 return 0;
11744}
11745
Matt Roper3d7d6512014-06-10 08:28:13 -070011746/* Common destruction function for both primary and cursor planes */
11747static void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070011748{
11749 struct intel_plane *intel_plane = to_intel_plane(plane);
11750 drm_plane_cleanup(plane);
11751 kfree(intel_plane);
11752}
11753
11754static const struct drm_plane_funcs intel_primary_plane_funcs = {
11755 .update_plane = intel_primary_plane_setplane,
11756 .disable_plane = intel_primary_plane_disable,
Matt Roper3d7d6512014-06-10 08:28:13 -070011757 .destroy = intel_plane_destroy,
Sonika Jindal48404c12014-08-22 14:06:04 +053011758 .set_property = intel_plane_set_property
Matt Roper465c1202014-05-29 08:06:54 -070011759};
11760
11761static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11762 int pipe)
11763{
11764 struct intel_plane *primary;
11765 const uint32_t *intel_primary_formats;
11766 int num_formats;
11767
11768 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11769 if (primary == NULL)
11770 return NULL;
11771
11772 primary->can_scale = false;
11773 primary->max_downscale = 1;
11774 primary->pipe = pipe;
11775 primary->plane = pipe;
Sonika Jindal48404c12014-08-22 14:06:04 +053011776 primary->rotation = BIT(DRM_ROTATE_0);
Matt Roper465c1202014-05-29 08:06:54 -070011777 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11778 primary->plane = !pipe;
11779
11780 if (INTEL_INFO(dev)->gen <= 3) {
11781 intel_primary_formats = intel_primary_formats_gen2;
11782 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11783 } else {
11784 intel_primary_formats = intel_primary_formats_gen4;
11785 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11786 }
11787
11788 drm_universal_plane_init(dev, &primary->base, 0,
11789 &intel_primary_plane_funcs,
11790 intel_primary_formats, num_formats,
11791 DRM_PLANE_TYPE_PRIMARY);
Sonika Jindal48404c12014-08-22 14:06:04 +053011792
11793 if (INTEL_INFO(dev)->gen >= 4) {
11794 if (!dev->mode_config.rotation_property)
11795 dev->mode_config.rotation_property =
11796 drm_mode_create_rotation_property(dev,
11797 BIT(DRM_ROTATE_0) |
11798 BIT(DRM_ROTATE_180));
11799 if (dev->mode_config.rotation_property)
11800 drm_object_attach_property(&primary->base.base,
11801 dev->mode_config.rotation_property,
11802 primary->rotation);
11803 }
11804
Matt Roper465c1202014-05-29 08:06:54 -070011805 return &primary->base;
11806}
11807
Matt Roper3d7d6512014-06-10 08:28:13 -070011808static int
11809intel_cursor_plane_disable(struct drm_plane *plane)
11810{
11811 if (!plane->fb)
11812 return 0;
11813
11814 BUG_ON(!plane->crtc);
11815
11816 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11817}
11818
11819static int
Gustavo Padovan852e7872014-09-05 17:22:31 -030011820intel_check_cursor_plane(struct drm_plane *plane,
11821 struct intel_plane_state *state)
Matt Roper3d7d6512014-06-10 08:28:13 -070011822{
Gustavo Padovan852e7872014-09-05 17:22:31 -030011823 struct drm_crtc *crtc = state->crtc;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011824 struct drm_device *dev = crtc->dev;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011825 struct drm_framebuffer *fb = state->fb;
11826 struct drm_rect *dest = &state->dst;
11827 struct drm_rect *src = &state->src;
11828 const struct drm_rect *clip = &state->clip;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011829 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11830 int crtc_w, crtc_h;
11831 unsigned stride;
11832 int ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011833
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011834 ret = drm_plane_helper_check_update(plane, crtc, fb,
Gustavo Padovan852e7872014-09-05 17:22:31 -030011835 src, dest, clip,
11836 DRM_PLANE_HELPER_NO_SCALING,
11837 DRM_PLANE_HELPER_NO_SCALING,
11838 true, true, &state->visible);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011839 if (ret)
11840 return ret;
11841
11842
11843 /* if we want to turn off the cursor ignore width and height */
11844 if (!obj)
11845 return 0;
11846
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011847 /* Check for which cursor types we support */
11848 crtc_w = drm_rect_width(&state->orig_dst);
11849 crtc_h = drm_rect_height(&state->orig_dst);
11850 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11851 DRM_DEBUG("Cursor dimension not supported\n");
11852 return -EINVAL;
11853 }
11854
11855 stride = roundup_pow_of_two(crtc_w) * 4;
11856 if (obj->base.size < stride * crtc_h) {
11857 DRM_DEBUG_KMS("buffer is too small\n");
11858 return -ENOMEM;
11859 }
11860
Gustavo Padovane391ea82014-09-24 14:20:25 -030011861 if (fb == crtc->cursor->fb)
11862 return 0;
11863
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011864 /* we only need to pin inside GTT if cursor is non-phy */
11865 mutex_lock(&dev->struct_mutex);
11866 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11867 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11868 ret = -EINVAL;
11869 }
11870 mutex_unlock(&dev->struct_mutex);
11871
11872 return ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011873}
11874
11875static int
11876intel_commit_cursor_plane(struct drm_plane *plane,
11877 struct intel_plane_state *state)
11878{
11879 struct drm_crtc *crtc = state->crtc;
11880 struct drm_framebuffer *fb = state->fb;
Matt Roper3d7d6512014-06-10 08:28:13 -070011881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Sonika Jindala919db92014-10-23 07:41:33 -070011882 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper3d7d6512014-06-10 08:28:13 -070011883 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11884 struct drm_i915_gem_object *obj = intel_fb->obj;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011885 int crtc_w, crtc_h;
Matt Roper3d7d6512014-06-10 08:28:13 -070011886
Gustavo Padovan852e7872014-09-05 17:22:31 -030011887 crtc->cursor_x = state->orig_dst.x1;
11888 crtc->cursor_y = state->orig_dst.y1;
Sonika Jindala919db92014-10-23 07:41:33 -070011889
11890 intel_plane->crtc_x = state->orig_dst.x1;
11891 intel_plane->crtc_y = state->orig_dst.y1;
11892 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11893 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11894 intel_plane->src_x = state->orig_src.x1;
11895 intel_plane->src_y = state->orig_src.y1;
11896 intel_plane->src_w = drm_rect_width(&state->orig_src);
11897 intel_plane->src_h = drm_rect_height(&state->orig_src);
11898 intel_plane->obj = obj;
11899
Matt Roper3d7d6512014-06-10 08:28:13 -070011900 if (fb != crtc->cursor->fb) {
Gustavo Padovan852e7872014-09-05 17:22:31 -030011901 crtc_w = drm_rect_width(&state->orig_dst);
11902 crtc_h = drm_rect_height(&state->orig_dst);
Matt Roper3d7d6512014-06-10 08:28:13 -070011903 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11904 } else {
Gustavo Padovan852e7872014-09-05 17:22:31 -030011905 intel_crtc_update_cursor(crtc, state->visible);
Daniel Vetter4ed91092014-08-08 20:27:01 +020011906
11907 intel_frontbuffer_flip(crtc->dev,
11908 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11909
Matt Roper3d7d6512014-06-10 08:28:13 -070011910 return 0;
11911 }
11912}
Gustavo Padovan852e7872014-09-05 17:22:31 -030011913
11914static int
11915intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11916 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11917 unsigned int crtc_w, unsigned int crtc_h,
11918 uint32_t src_x, uint32_t src_y,
11919 uint32_t src_w, uint32_t src_h)
11920{
11921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11922 struct intel_plane_state state;
11923 int ret;
11924
11925 state.crtc = crtc;
11926 state.fb = fb;
11927
11928 /* sample coordinates in 16.16 fixed point */
11929 state.src.x1 = src_x;
11930 state.src.x2 = src_x + src_w;
11931 state.src.y1 = src_y;
11932 state.src.y2 = src_y + src_h;
11933
11934 /* integer pixels */
11935 state.dst.x1 = crtc_x;
11936 state.dst.x2 = crtc_x + crtc_w;
11937 state.dst.y1 = crtc_y;
11938 state.dst.y2 = crtc_y + crtc_h;
11939
11940 state.clip.x1 = 0;
11941 state.clip.y1 = 0;
11942 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11943 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11944
11945 state.orig_src = state.src;
11946 state.orig_dst = state.dst;
11947
11948 ret = intel_check_cursor_plane(plane, &state);
11949 if (ret)
11950 return ret;
11951
11952 return intel_commit_cursor_plane(plane, &state);
11953}
11954
Matt Roper3d7d6512014-06-10 08:28:13 -070011955static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11956 .update_plane = intel_cursor_plane_update,
11957 .disable_plane = intel_cursor_plane_disable,
11958 .destroy = intel_plane_destroy,
Ville Syrjälä4398ad42014-10-23 07:41:34 -070011959 .set_property = intel_plane_set_property,
Matt Roper3d7d6512014-06-10 08:28:13 -070011960};
11961
11962static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11963 int pipe)
11964{
11965 struct intel_plane *cursor;
11966
11967 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11968 if (cursor == NULL)
11969 return NULL;
11970
11971 cursor->can_scale = false;
11972 cursor->max_downscale = 1;
11973 cursor->pipe = pipe;
11974 cursor->plane = pipe;
Ville Syrjälä4398ad42014-10-23 07:41:34 -070011975 cursor->rotation = BIT(DRM_ROTATE_0);
Matt Roper3d7d6512014-06-10 08:28:13 -070011976
11977 drm_universal_plane_init(dev, &cursor->base, 0,
11978 &intel_cursor_plane_funcs,
11979 intel_cursor_formats,
11980 ARRAY_SIZE(intel_cursor_formats),
11981 DRM_PLANE_TYPE_CURSOR);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070011982
11983 if (INTEL_INFO(dev)->gen >= 4) {
11984 if (!dev->mode_config.rotation_property)
11985 dev->mode_config.rotation_property =
11986 drm_mode_create_rotation_property(dev,
11987 BIT(DRM_ROTATE_0) |
11988 BIT(DRM_ROTATE_180));
11989 if (dev->mode_config.rotation_property)
11990 drm_object_attach_property(&cursor->base.base,
11991 dev->mode_config.rotation_property,
11992 cursor->rotation);
11993 }
11994
Matt Roper3d7d6512014-06-10 08:28:13 -070011995 return &cursor->base;
11996}
11997
Hannes Ederb358d0a2008-12-18 21:18:47 +010011998static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080011999{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012000 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080012001 struct intel_crtc *intel_crtc;
Matt Roper3d7d6512014-06-10 08:28:13 -070012002 struct drm_plane *primary = NULL;
12003 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070012004 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080012005
Daniel Vetter955382f2013-09-19 14:05:45 +020012006 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080012007 if (intel_crtc == NULL)
12008 return;
12009
Matt Roper465c1202014-05-29 08:06:54 -070012010 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070012011 if (!primary)
12012 goto fail;
12013
12014 cursor = intel_cursor_plane_create(dev, pipe);
12015 if (!cursor)
12016 goto fail;
12017
Matt Roper465c1202014-05-29 08:06:54 -070012018 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070012019 cursor, &intel_crtc_funcs);
12020 if (ret)
12021 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080012022
12023 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080012024 for (i = 0; i < 256; i++) {
12025 intel_crtc->lut_r[i] = i;
12026 intel_crtc->lut_g[i] = i;
12027 intel_crtc->lut_b[i] = i;
12028 }
12029
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020012030 /*
12031 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020012032 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020012033 */
Jesse Barnes80824002009-09-10 15:28:06 -070012034 intel_crtc->pipe = pipe;
12035 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010012036 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080012037 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010012038 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070012039 }
12040
Chris Wilson4b0e3332014-05-30 16:35:26 +030012041 intel_crtc->cursor_base = ~0;
12042 intel_crtc->cursor_cntl = ~0;
Ville Syrjälädc41c152014-08-13 11:57:05 +030012043 intel_crtc->cursor_size = ~0;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030012044
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080012045 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12046 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12047 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12048 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12049
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +020012050 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12051
Jesse Barnes79e53942008-11-07 14:24:08 -080012052 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020012053
12054 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070012055 return;
12056
12057fail:
12058 if (primary)
12059 drm_plane_cleanup(primary);
12060 if (cursor)
12061 drm_plane_cleanup(cursor);
12062 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080012063}
12064
Jesse Barnes752aa882013-10-31 18:55:49 +020012065enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12066{
12067 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012068 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020012069
Rob Clark51fd3712013-11-19 12:10:12 -050012070 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020012071
Ville Syrjäläd3babd32014-11-07 11:16:01 +020012072 if (!encoder || WARN_ON(!encoder->crtc))
Jesse Barnes752aa882013-10-31 18:55:49 +020012073 return INVALID_PIPE;
12074
12075 return to_intel_crtc(encoder->crtc)->pipe;
12076}
12077
Carl Worth08d7b3d2009-04-29 14:43:54 -070012078int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000012079 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070012080{
Carl Worth08d7b3d2009-04-29 14:43:54 -070012081 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040012082 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020012083 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012084
Daniel Vetter1cff8f62012-04-24 09:55:08 +020012085 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12086 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012087
Rob Clark7707e652014-07-17 23:30:04 -040012088 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Carl Worth08d7b3d2009-04-29 14:43:54 -070012089
Rob Clark7707e652014-07-17 23:30:04 -040012090 if (!drmmode_crtc) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070012091 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030012092 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012093 }
12094
Rob Clark7707e652014-07-17 23:30:04 -040012095 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020012096 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012097
Daniel Vetterc05422d2009-08-11 16:05:30 +020012098 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012099}
12100
Daniel Vetter66a92782012-07-12 20:08:18 +020012101static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080012102{
Daniel Vetter66a92782012-07-12 20:08:18 +020012103 struct drm_device *dev = encoder->base.dev;
12104 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080012105 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080012106 int entry = 0;
12107
Damien Lespiaub2784e12014-08-05 11:29:37 +010012108 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020012109 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020012110 index_mask |= (1 << entry);
12111
Jesse Barnes79e53942008-11-07 14:24:08 -080012112 entry++;
12113 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010012114
Jesse Barnes79e53942008-11-07 14:24:08 -080012115 return index_mask;
12116}
12117
Chris Wilson4d302442010-12-14 19:21:29 +000012118static bool has_edp_a(struct drm_device *dev)
12119{
12120 struct drm_i915_private *dev_priv = dev->dev_private;
12121
12122 if (!IS_MOBILE(dev))
12123 return false;
12124
12125 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12126 return false;
12127
Damien Lespiaue3589902014-02-07 19:12:50 +000012128 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000012129 return false;
12130
12131 return true;
12132}
12133
Damien Lespiauba0fbca2014-01-08 14:18:23 +000012134const char *intel_output_name(int output)
12135{
12136 static const char *names[] = {
12137 [INTEL_OUTPUT_UNUSED] = "Unused",
12138 [INTEL_OUTPUT_ANALOG] = "Analog",
12139 [INTEL_OUTPUT_DVO] = "DVO",
12140 [INTEL_OUTPUT_SDVO] = "SDVO",
12141 [INTEL_OUTPUT_LVDS] = "LVDS",
12142 [INTEL_OUTPUT_TVOUT] = "TV",
12143 [INTEL_OUTPUT_HDMI] = "HDMI",
12144 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12145 [INTEL_OUTPUT_EDP] = "eDP",
12146 [INTEL_OUTPUT_DSI] = "DSI",
12147 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12148 };
12149
12150 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12151 return "Invalid";
12152
12153 return names[output];
12154}
12155
Jesse Barnes84b4e042014-06-25 08:24:29 -070012156static bool intel_crt_present(struct drm_device *dev)
12157{
12158 struct drm_i915_private *dev_priv = dev->dev_private;
12159
Damien Lespiau884497e2013-12-03 13:56:23 +000012160 if (INTEL_INFO(dev)->gen >= 9)
12161 return false;
12162
Damien Lespiaucf404ce2014-10-01 20:04:15 +010012163 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
Jesse Barnes84b4e042014-06-25 08:24:29 -070012164 return false;
12165
12166 if (IS_CHERRYVIEW(dev))
12167 return false;
12168
12169 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12170 return false;
12171
12172 return true;
12173}
12174
Jesse Barnes79e53942008-11-07 14:24:08 -080012175static void intel_setup_outputs(struct drm_device *dev)
12176{
Eric Anholt725e30a2009-01-22 13:01:02 -080012177 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010012178 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012179 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080012180
Daniel Vetterc9093352013-06-06 22:22:47 +020012181 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012182
Jesse Barnes84b4e042014-06-25 08:24:29 -070012183 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020012184 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012185
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012186 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030012187 int found;
12188
12189 /* Haswell uses DDI functions to detect digital outputs */
12190 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12191 /* DDI A only supports eDP */
12192 if (found)
12193 intel_ddi_init(dev, PORT_A);
12194
12195 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12196 * register */
12197 found = I915_READ(SFUSE_STRAP);
12198
12199 if (found & SFUSE_STRAP_DDIB_DETECTED)
12200 intel_ddi_init(dev, PORT_B);
12201 if (found & SFUSE_STRAP_DDIC_DETECTED)
12202 intel_ddi_init(dev, PORT_C);
12203 if (found & SFUSE_STRAP_DDID_DETECTED)
12204 intel_ddi_init(dev, PORT_D);
12205 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012206 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012207 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020012208
12209 if (has_edp_a(dev))
12210 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012211
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012212 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080012213 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010012214 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012215 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012216 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012217 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012218 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012219 }
12220
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012221 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012222 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012223
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012224 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012225 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012226
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012227 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012228 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012229
Daniel Vetter270b3042012-10-27 15:52:05 +020012230 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012231 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070012232 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012233 /*
12234 * The DP_DETECTED bit is the latched state of the DDC
12235 * SDA pin at boot. However since eDP doesn't require DDC
12236 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12237 * eDP ports may have been muxed to an alternate function.
12238 * Thus we can't rely on the DP_DETECTED bit alone to detect
12239 * eDP ports. Consult the VBT as well as DP_DETECTED to
12240 * detect eDP ports.
12241 */
12242 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012243 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12244 PORT_B);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012245 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12246 intel_dp_is_edp(dev, PORT_B))
12247 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012248
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012249 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012250 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12251 PORT_C);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012252 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12253 intel_dp_is_edp(dev, PORT_C))
12254 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +053012255
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012256 if (IS_CHERRYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012257 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012258 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12259 PORT_D);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012260 /* eDP not supported on port D, so don't check VBT */
12261 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12262 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012263 }
12264
Jani Nikula3cfca972013-08-27 15:12:26 +030012265 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080012266 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012267 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080012268
Paulo Zanonie2debe92013-02-18 19:00:27 -030012269 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012270 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012271 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012272 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12273 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012274 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012275 }
Ma Ling27185ae2009-08-24 13:50:23 +080012276
Imre Deake7281ea2013-05-08 13:14:08 +030012277 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012278 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080012279 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012280
12281 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012282
Paulo Zanonie2debe92013-02-18 19:00:27 -030012283 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012284 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012285 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012286 }
Ma Ling27185ae2009-08-24 13:50:23 +080012287
Paulo Zanonie2debe92013-02-18 19:00:27 -030012288 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012289
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012290 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12291 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012292 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012293 }
Imre Deake7281ea2013-05-08 13:14:08 +030012294 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012295 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080012296 }
Ma Ling27185ae2009-08-24 13:50:23 +080012297
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012298 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030012299 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012300 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070012301 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012302 intel_dvo_init(dev);
12303
Zhenyu Wang103a1962009-11-27 11:44:36 +080012304 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012305 intel_tv_init(dev);
12306
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070012307 intel_edp_psr_init(dev);
12308
Damien Lespiaub2784e12014-08-05 11:29:37 +010012309 for_each_intel_encoder(dev, encoder) {
Chris Wilson4ef69c72010-09-09 15:14:28 +010012310 encoder->base.possible_crtcs = encoder->crtc_mask;
12311 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020012312 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080012313 }
Chris Wilson47356eb2011-01-11 17:06:04 +000012314
Paulo Zanonidde86e22012-12-01 12:04:25 -020012315 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020012316
12317 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012318}
12319
12320static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12321{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012322 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080012323 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080012324
Daniel Vetteref2d6332014-02-10 18:00:38 +010012325 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012326 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010012327 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012328 drm_gem_object_unreference(&intel_fb->obj->base);
12329 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012330 kfree(intel_fb);
12331}
12332
12333static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000012334 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080012335 unsigned int *handle)
12336{
12337 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000012338 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012339
Chris Wilson05394f32010-11-08 19:18:58 +000012340 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080012341}
12342
12343static const struct drm_framebuffer_funcs intel_fb_funcs = {
12344 .destroy = intel_user_framebuffer_destroy,
12345 .create_handle = intel_user_framebuffer_create_handle,
12346};
12347
Daniel Vetterb5ea6422014-03-02 21:18:00 +010012348static int intel_framebuffer_init(struct drm_device *dev,
12349 struct intel_framebuffer *intel_fb,
12350 struct drm_mode_fb_cmd2 *mode_cmd,
12351 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080012352{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012353 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012354 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080012355 int ret;
12356
Daniel Vetterdd4916c2013-10-09 21:23:51 +020012357 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12358
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012359 if (obj->tiling_mode == I915_TILING_Y) {
12360 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010012361 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012362 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012363
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012364 if (mode_cmd->pitches[0] & 63) {
12365 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12366 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010012367 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012368 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012369
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012370 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12371 pitch_limit = 32*1024;
12372 } else if (INTEL_INFO(dev)->gen >= 4) {
12373 if (obj->tiling_mode)
12374 pitch_limit = 16*1024;
12375 else
12376 pitch_limit = 32*1024;
12377 } else if (INTEL_INFO(dev)->gen >= 3) {
12378 if (obj->tiling_mode)
12379 pitch_limit = 8*1024;
12380 else
12381 pitch_limit = 16*1024;
12382 } else
12383 /* XXX DSPC is limited to 4k tiled */
12384 pitch_limit = 8*1024;
12385
12386 if (mode_cmd->pitches[0] > pitch_limit) {
12387 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12388 obj->tiling_mode ? "tiled" : "linear",
12389 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012390 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012391 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012392
12393 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012394 mode_cmd->pitches[0] != obj->stride) {
12395 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12396 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012397 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012398 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012399
Ville Syrjälä57779d02012-10-31 17:50:14 +020012400 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012401 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020012402 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012403 case DRM_FORMAT_RGB565:
12404 case DRM_FORMAT_XRGB8888:
12405 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012406 break;
12407 case DRM_FORMAT_XRGB1555:
12408 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012409 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012410 DRM_DEBUG("unsupported pixel format: %s\n",
12411 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012412 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012413 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020012414 break;
12415 case DRM_FORMAT_XBGR8888:
12416 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012417 case DRM_FORMAT_XRGB2101010:
12418 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012419 case DRM_FORMAT_XBGR2101010:
12420 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012421 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012422 DRM_DEBUG("unsupported pixel format: %s\n",
12423 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012424 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012425 }
Jesse Barnesb5626742011-06-24 12:19:27 -070012426 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020012427 case DRM_FORMAT_YUYV:
12428 case DRM_FORMAT_UYVY:
12429 case DRM_FORMAT_YVYU:
12430 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012431 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012432 DRM_DEBUG("unsupported pixel format: %s\n",
12433 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012434 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012435 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012436 break;
12437 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012438 DRM_DEBUG("unsupported pixel format: %s\n",
12439 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010012440 return -EINVAL;
12441 }
12442
Ville Syrjälä90f9a332012-10-31 17:50:19 +020012443 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12444 if (mode_cmd->offsets[0] != 0)
12445 return -EINVAL;
12446
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012447 aligned_height = intel_align_height(dev, mode_cmd->height,
12448 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020012449 /* FIXME drm helper for size checks (especially planar formats)? */
12450 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12451 return -EINVAL;
12452
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012453 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12454 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020012455 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012456
Jesse Barnes79e53942008-11-07 14:24:08 -080012457 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12458 if (ret) {
12459 DRM_ERROR("framebuffer init failed %d\n", ret);
12460 return ret;
12461 }
12462
Jesse Barnes79e53942008-11-07 14:24:08 -080012463 return 0;
12464}
12465
Jesse Barnes79e53942008-11-07 14:24:08 -080012466static struct drm_framebuffer *
12467intel_user_framebuffer_create(struct drm_device *dev,
12468 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012469 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080012470{
Chris Wilson05394f32010-11-08 19:18:58 +000012471 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012472
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012473 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12474 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000012475 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010012476 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080012477
Chris Wilsond2dff872011-04-19 08:36:26 +010012478 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080012479}
12480
Daniel Vetter4520f532013-10-09 09:18:51 +020012481#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020012482static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020012483{
12484}
12485#endif
12486
Jesse Barnes79e53942008-11-07 14:24:08 -080012487static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080012488 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020012489 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080012490};
12491
Jesse Barnese70236a2009-09-21 10:42:27 -070012492/* Set up chip specific display functions */
12493static void intel_init_display(struct drm_device *dev)
12494{
12495 struct drm_i915_private *dev_priv = dev->dev_private;
12496
Daniel Vetteree9300b2013-06-03 22:40:22 +020012497 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12498 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030012499 else if (IS_CHERRYVIEW(dev))
12500 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020012501 else if (IS_VALLEYVIEW(dev))
12502 dev_priv->display.find_dpll = vlv_find_best_dpll;
12503 else if (IS_PINEVIEW(dev))
12504 dev_priv->display.find_dpll = pnv_find_best_dpll;
12505 else
12506 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12507
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012508 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012509 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012510 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +020012511 dev_priv->display.crtc_compute_clock =
12512 haswell_crtc_compute_clock;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020012513 dev_priv->display.crtc_enable = haswell_crtc_enable;
12514 dev_priv->display.crtc_disable = haswell_crtc_disable;
Daniel Vetterdf8ad702014-06-25 22:02:03 +030012515 dev_priv->display.off = ironlake_crtc_off;
Damien Lespiau70d21f02013-07-03 21:06:04 +010012516 if (INTEL_INFO(dev)->gen >= 9)
12517 dev_priv->display.update_primary_plane =
12518 skylake_update_primary_plane;
12519 else
12520 dev_priv->display.update_primary_plane =
12521 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012522 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012523 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012524 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +020012525 dev_priv->display.crtc_compute_clock =
12526 ironlake_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012527 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12528 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012529 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012530 dev_priv->display.update_primary_plane =
12531 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012532 } else if (IS_VALLEYVIEW(dev)) {
12533 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012534 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020012535 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012536 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12537 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12538 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012539 dev_priv->display.update_primary_plane =
12540 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012541 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012542 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012543 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020012544 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012545 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12546 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012547 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012548 dev_priv->display.update_primary_plane =
12549 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012550 }
Jesse Barnese70236a2009-09-21 10:42:27 -070012551
Jesse Barnese70236a2009-09-21 10:42:27 -070012552 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070012553 if (IS_VALLEYVIEW(dev))
12554 dev_priv->display.get_display_clock_speed =
12555 valleyview_get_display_clock_speed;
12556 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070012557 dev_priv->display.get_display_clock_speed =
12558 i945_get_display_clock_speed;
12559 else if (IS_I915G(dev))
12560 dev_priv->display.get_display_clock_speed =
12561 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012562 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012563 dev_priv->display.get_display_clock_speed =
12564 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012565 else if (IS_PINEVIEW(dev))
12566 dev_priv->display.get_display_clock_speed =
12567 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070012568 else if (IS_I915GM(dev))
12569 dev_priv->display.get_display_clock_speed =
12570 i915gm_get_display_clock_speed;
12571 else if (IS_I865G(dev))
12572 dev_priv->display.get_display_clock_speed =
12573 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020012574 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012575 dev_priv->display.get_display_clock_speed =
12576 i855_get_display_clock_speed;
12577 else /* 852, 830 */
12578 dev_priv->display.get_display_clock_speed =
12579 i830_get_display_clock_speed;
12580
Jani Nikula7c10a2b2014-10-27 16:26:43 +020012581 if (IS_GEN5(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012582 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012583 } else if (IS_GEN6(dev)) {
12584 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012585 } else if (IS_IVYBRIDGE(dev)) {
12586 /* FIXME: detect B0+ stepping and use auto training */
12587 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012588 dev_priv->display.modeset_global_resources =
12589 ivb_modeset_global_resources;
Paulo Zanoni059b2fe2014-09-02 16:53:57 -030012590 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012591 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Jesse Barnes30a970c2013-11-04 13:48:12 -080012592 } else if (IS_VALLEYVIEW(dev)) {
12593 dev_priv->display.modeset_global_resources =
12594 valleyview_modeset_global_resources;
Jesse Barnese70236a2009-09-21 10:42:27 -070012595 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012596
12597 /* Default just returns -ENODEV to indicate unsupported */
12598 dev_priv->display.queue_flip = intel_default_queue_flip;
12599
12600 switch (INTEL_INFO(dev)->gen) {
12601 case 2:
12602 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12603 break;
12604
12605 case 3:
12606 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12607 break;
12608
12609 case 4:
12610 case 5:
12611 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12612 break;
12613
12614 case 6:
12615 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12616 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012617 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012618 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012619 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12620 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012621 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020012622
12623 intel_panel_init_backlight_funcs(dev);
Ville Syrjäläe39b9992014-09-04 14:53:14 +030012624
12625 mutex_init(&dev_priv->pps_mutex);
Jesse Barnese70236a2009-09-21 10:42:27 -070012626}
12627
Jesse Barnesb690e962010-07-19 13:53:12 -070012628/*
12629 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12630 * resume, or other times. This quirk makes sure that's the case for
12631 * affected systems.
12632 */
Akshay Joshi0206e352011-08-16 15:34:10 -040012633static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070012634{
12635 struct drm_i915_private *dev_priv = dev->dev_private;
12636
12637 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012638 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012639}
12640
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030012641static void quirk_pipeb_force(struct drm_device *dev)
12642{
12643 struct drm_i915_private *dev_priv = dev->dev_private;
12644
12645 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12646 DRM_INFO("applying pipe b force quirk\n");
12647}
12648
Keith Packard435793d2011-07-12 14:56:22 -070012649/*
12650 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12651 */
12652static void quirk_ssc_force_disable(struct drm_device *dev)
12653{
12654 struct drm_i915_private *dev_priv = dev->dev_private;
12655 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012656 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070012657}
12658
Carsten Emde4dca20e2012-03-15 15:56:26 +010012659/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010012660 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12661 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010012662 */
12663static void quirk_invert_brightness(struct drm_device *dev)
12664{
12665 struct drm_i915_private *dev_priv = dev->dev_private;
12666 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012667 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012668}
12669
Scot Doyle9c72cc62014-07-03 23:27:50 +000012670/* Some VBT's incorrectly indicate no backlight is present */
12671static void quirk_backlight_present(struct drm_device *dev)
12672{
12673 struct drm_i915_private *dev_priv = dev->dev_private;
12674 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12675 DRM_INFO("applying backlight present quirk\n");
12676}
12677
Jesse Barnesb690e962010-07-19 13:53:12 -070012678struct intel_quirk {
12679 int device;
12680 int subsystem_vendor;
12681 int subsystem_device;
12682 void (*hook)(struct drm_device *dev);
12683};
12684
Egbert Eich5f85f1762012-10-14 15:46:38 +020012685/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12686struct intel_dmi_quirk {
12687 void (*hook)(struct drm_device *dev);
12688 const struct dmi_system_id (*dmi_id_list)[];
12689};
12690
12691static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12692{
12693 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12694 return 1;
12695}
12696
12697static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12698 {
12699 .dmi_id_list = &(const struct dmi_system_id[]) {
12700 {
12701 .callback = intel_dmi_reverse_brightness,
12702 .ident = "NCR Corporation",
12703 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12704 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12705 },
12706 },
12707 { } /* terminating entry */
12708 },
12709 .hook = quirk_invert_brightness,
12710 },
12711};
12712
Ben Widawskyc43b5632012-04-16 14:07:40 -070012713static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070012714 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040012715 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070012716
Jesse Barnesb690e962010-07-19 13:53:12 -070012717 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12718 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12719
Jesse Barnesb690e962010-07-19 13:53:12 -070012720 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12721 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12722
Ville Syrjälä5f080c02014-08-15 01:22:06 +030012723 /* 830 needs to leave pipe A & dpll A up */
12724 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12725
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030012726 /* 830 needs to leave pipe B & dpll B up */
12727 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12728
Keith Packard435793d2011-07-12 14:56:22 -070012729 /* Lenovo U160 cannot use SSC on LVDS */
12730 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020012731
12732 /* Sony Vaio Y cannot use SSC on LVDS */
12733 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010012734
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010012735 /* Acer Aspire 5734Z must invert backlight brightness */
12736 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12737
12738 /* Acer/eMachines G725 */
12739 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12740
12741 /* Acer/eMachines e725 */
12742 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12743
12744 /* Acer/Packard Bell NCL20 */
12745 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12746
12747 /* Acer Aspire 4736Z */
12748 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020012749
12750 /* Acer Aspire 5336 */
12751 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000012752
12753 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12754 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000012755
Scot Doyledfb3d47b2014-08-21 16:08:02 +000012756 /* Acer C720 Chromebook (Core i3 4005U) */
12757 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12758
Scot Doyled4967d82014-07-03 23:27:52 +000012759 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12760 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000012761
12762 /* HP Chromebook 14 (Celeron 2955U) */
12763 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070012764};
12765
12766static void intel_init_quirks(struct drm_device *dev)
12767{
12768 struct pci_dev *d = dev->pdev;
12769 int i;
12770
12771 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12772 struct intel_quirk *q = &intel_quirks[i];
12773
12774 if (d->device == q->device &&
12775 (d->subsystem_vendor == q->subsystem_vendor ||
12776 q->subsystem_vendor == PCI_ANY_ID) &&
12777 (d->subsystem_device == q->subsystem_device ||
12778 q->subsystem_device == PCI_ANY_ID))
12779 q->hook(dev);
12780 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020012781 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12782 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12783 intel_dmi_quirks[i].hook(dev);
12784 }
Jesse Barnesb690e962010-07-19 13:53:12 -070012785}
12786
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012787/* Disable the VGA plane that we never use */
12788static void i915_disable_vga(struct drm_device *dev)
12789{
12790 struct drm_i915_private *dev_priv = dev->dev_private;
12791 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012792 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012793
Ville Syrjälä2b37c612014-01-22 21:32:38 +020012794 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012795 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070012796 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012797 sr1 = inb(VGA_SR_DATA);
12798 outb(sr1 | 1<<5, VGA_SR_DATA);
12799 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12800 udelay(300);
12801
Ville Syrjälä69769f92014-08-15 01:22:08 +030012802 /*
12803 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12804 * from S3 without preserving (some of?) the other bits.
12805 */
12806 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012807 POSTING_READ(vga_reg);
12808}
12809
Daniel Vetterf8175862012-04-10 15:50:11 +020012810void intel_modeset_init_hw(struct drm_device *dev)
12811{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030012812 intel_prepare_ddi(dev);
12813
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +030012814 if (IS_VALLEYVIEW(dev))
12815 vlv_update_cdclk(dev);
12816
Daniel Vetterf8175862012-04-10 15:50:11 +020012817 intel_init_clock_gating(dev);
12818
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012819 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020012820}
12821
Jesse Barnes79e53942008-11-07 14:24:08 -080012822void intel_modeset_init(struct drm_device *dev)
12823{
Jesse Barnes652c3932009-08-17 13:31:43 -070012824 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000012825 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012826 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080012827 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080012828
12829 drm_mode_config_init(dev);
12830
12831 dev->mode_config.min_width = 0;
12832 dev->mode_config.min_height = 0;
12833
Dave Airlie019d96c2011-09-29 16:20:42 +010012834 dev->mode_config.preferred_depth = 24;
12835 dev->mode_config.prefer_shadow = 1;
12836
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020012837 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080012838
Jesse Barnesb690e962010-07-19 13:53:12 -070012839 intel_init_quirks(dev);
12840
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030012841 intel_init_pm(dev);
12842
Ben Widawskye3c74752013-04-05 13:12:39 -070012843 if (INTEL_INFO(dev)->num_pipes == 0)
12844 return;
12845
Jesse Barnese70236a2009-09-21 10:42:27 -070012846 intel_init_display(dev);
Jani Nikula7c10a2b2014-10-27 16:26:43 +020012847 intel_init_audio(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012848
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012849 if (IS_GEN2(dev)) {
12850 dev->mode_config.max_width = 2048;
12851 dev->mode_config.max_height = 2048;
12852 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070012853 dev->mode_config.max_width = 4096;
12854 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080012855 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012856 dev->mode_config.max_width = 8192;
12857 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080012858 }
Damien Lespiau068be562014-03-28 14:17:49 +000012859
Ville Syrjälädc41c152014-08-13 11:57:05 +030012860 if (IS_845G(dev) || IS_I865G(dev)) {
12861 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12862 dev->mode_config.cursor_height = 1023;
12863 } else if (IS_GEN2(dev)) {
Damien Lespiau068be562014-03-28 14:17:49 +000012864 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12865 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12866 } else {
12867 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12868 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12869 }
12870
Ben Widawsky5d4545a2013-01-17 12:45:15 -080012871 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080012872
Zhao Yakui28c97732009-10-09 11:39:41 +080012873 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012874 INTEL_INFO(dev)->num_pipes,
12875 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080012876
Damien Lespiau055e3932014-08-18 13:49:10 +010012877 for_each_pipe(dev_priv, pipe) {
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012878 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000012879 for_each_sprite(pipe, sprite) {
12880 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012881 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030012882 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000012883 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070012884 }
Jesse Barnes79e53942008-11-07 14:24:08 -080012885 }
12886
Jesse Barnesf42bb702013-12-16 16:34:23 -080012887 intel_init_dpio(dev);
12888
Daniel Vettere72f9fb2013-06-05 13:34:06 +020012889 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012890
Ville Syrjälä69769f92014-08-15 01:22:08 +030012891 /* save the BIOS value before clobbering it */
12892 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012893 /* Just disable it once at startup */
12894 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012895 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000012896
12897 /* Just in case the BIOS is doing something questionable. */
12898 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012899
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012900 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080012901 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012902 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012903
Damien Lespiaud3fcc802014-05-13 23:32:22 +010012904 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080012905 if (!crtc->active)
12906 continue;
12907
Jesse Barnes46f297f2014-03-07 08:57:48 -080012908 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080012909 * Note that reserving the BIOS fb up front prevents us
12910 * from stuffing other stolen allocations like the ring
12911 * on top. This prevents some ugliness at boot time, and
12912 * can even allow for smooth boot transitions if the BIOS
12913 * fb is large enough for the active pipe configuration.
12914 */
12915 if (dev_priv->display.get_plane_config) {
12916 dev_priv->display.get_plane_config(crtc,
12917 &crtc->plane_config);
12918 /*
12919 * If the fb is shared between multiple heads, we'll
12920 * just get the first one.
12921 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080012922 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080012923 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080012924 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010012925}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080012926
Daniel Vetter7fad7982012-07-04 17:51:47 +020012927static void intel_enable_pipe_a(struct drm_device *dev)
12928{
12929 struct intel_connector *connector;
12930 struct drm_connector *crt = NULL;
12931 struct intel_load_detect_pipe load_detect_temp;
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030012932 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020012933
12934 /* We can't just switch on the pipe A, we need to set things up with a
12935 * proper mode and output configuration. As a gross hack, enable pipe A
12936 * by enabling the load detect pipe once. */
12937 list_for_each_entry(connector,
12938 &dev->mode_config.connector_list,
12939 base.head) {
12940 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12941 crt = &connector->base;
12942 break;
12943 }
12944 }
12945
12946 if (!crt)
12947 return;
12948
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030012949 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12950 intel_release_load_detect_pipe(crt, &load_detect_temp);
Daniel Vetter7fad7982012-07-04 17:51:47 +020012951}
12952
Daniel Vetterfa555832012-10-10 23:14:00 +020012953static bool
12954intel_check_plane_mapping(struct intel_crtc *crtc)
12955{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012956 struct drm_device *dev = crtc->base.dev;
12957 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012958 u32 reg, val;
12959
Ben Widawsky7eb552a2013-03-13 14:05:41 -070012960 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020012961 return true;
12962
12963 reg = DSPCNTR(!crtc->plane);
12964 val = I915_READ(reg);
12965
12966 if ((val & DISPLAY_PLANE_ENABLE) &&
12967 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12968 return false;
12969
12970 return true;
12971}
12972
Daniel Vetter24929352012-07-02 20:28:59 +020012973static void intel_sanitize_crtc(struct intel_crtc *crtc)
12974{
12975 struct drm_device *dev = crtc->base.dev;
12976 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020012977 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020012978
Daniel Vetter24929352012-07-02 20:28:59 +020012979 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020012980 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020012981 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12982
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012983 /* restore vblank interrupts to correct state */
Ville Syrjäläd297e102014-08-06 14:50:01 +030012984 if (crtc->active) {
12985 update_scanline_offset(crtc);
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012986 drm_vblank_on(dev, crtc->pipe);
Ville Syrjäläd297e102014-08-06 14:50:01 +030012987 } else
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030012988 drm_vblank_off(dev, crtc->pipe);
12989
Daniel Vetter24929352012-07-02 20:28:59 +020012990 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020012991 * disable the crtc (and hence change the state) if it is wrong. Note
12992 * that gen4+ has a fixed plane -> pipe mapping. */
12993 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020012994 struct intel_connector *connector;
12995 bool plane;
12996
Daniel Vetter24929352012-07-02 20:28:59 +020012997 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12998 crtc->base.base.id);
12999
13000 /* Pipe has the wrong plane attached and the plane is active.
13001 * Temporarily change the plane mapping and disable everything
13002 * ... */
13003 plane = crtc->plane;
13004 crtc->plane = !plane;
Daniel Vetter9c8958b2014-07-14 19:35:31 +020013005 crtc->primary_enabled = true;
Daniel Vetter24929352012-07-02 20:28:59 +020013006 dev_priv->display.crtc_disable(&crtc->base);
13007 crtc->plane = plane;
13008
13009 /* ... and break all links. */
13010 list_for_each_entry(connector, &dev->mode_config.connector_list,
13011 base.head) {
13012 if (connector->encoder->base.crtc != &crtc->base)
13013 continue;
13014
Egbert Eich7f1950f2014-04-25 10:56:22 +020013015 connector->base.dpms = DRM_MODE_DPMS_OFF;
13016 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020013017 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020013018 /* multiple connectors may have the same encoder:
13019 * handle them and break crtc link separately */
13020 list_for_each_entry(connector, &dev->mode_config.connector_list,
13021 base.head)
13022 if (connector->encoder->base.crtc == &crtc->base) {
13023 connector->encoder->base.crtc = NULL;
13024 connector->encoder->connectors_active = false;
13025 }
Daniel Vetter24929352012-07-02 20:28:59 +020013026
13027 WARN_ON(crtc->active);
13028 crtc->base.enabled = false;
13029 }
Daniel Vetter24929352012-07-02 20:28:59 +020013030
Daniel Vetter7fad7982012-07-04 17:51:47 +020013031 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13032 crtc->pipe == PIPE_A && !crtc->active) {
13033 /* BIOS forgot to enable pipe A, this mostly happens after
13034 * resume. Force-enable the pipe to fix this, the update_dpms
13035 * call below we restore the pipe to the right state, but leave
13036 * the required bits on. */
13037 intel_enable_pipe_a(dev);
13038 }
13039
Daniel Vetter24929352012-07-02 20:28:59 +020013040 /* Adjust the state of the output pipe according to whether we
13041 * have active connectors/encoders. */
13042 intel_crtc_update_dpms(&crtc->base);
13043
13044 if (crtc->active != crtc->base.enabled) {
13045 struct intel_encoder *encoder;
13046
13047 /* This can happen either due to bugs in the get_hw_state
13048 * functions or because the pipe is force-enabled due to the
13049 * pipe A quirk. */
13050 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13051 crtc->base.base.id,
13052 crtc->base.enabled ? "enabled" : "disabled",
13053 crtc->active ? "enabled" : "disabled");
13054
13055 crtc->base.enabled = crtc->active;
13056
13057 /* Because we only establish the connector -> encoder ->
13058 * crtc links if something is active, this means the
13059 * crtc is now deactivated. Break the links. connector
13060 * -> encoder links are only establish when things are
13061 * actually up, hence no need to break them. */
13062 WARN_ON(crtc->active);
13063
13064 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13065 WARN_ON(encoder->connectors_active);
13066 encoder->base.crtc = NULL;
13067 }
13068 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020013069
Ville Syrjäläa3ed6aa2014-09-03 14:09:52 +030013070 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010013071 /*
13072 * We start out with underrun reporting disabled to avoid races.
13073 * For correct bookkeeping mark this on active crtcs.
13074 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020013075 * Also on gmch platforms we dont have any hardware bits to
13076 * disable the underrun reporting. Which means we need to start
13077 * out with underrun reporting disabled also on inactive pipes,
13078 * since otherwise we'll complain about the garbage we read when
13079 * e.g. coming up after runtime pm.
13080 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010013081 * No protection against concurrent access is required - at
13082 * worst a fifo underrun happens which also sets this to false.
13083 */
13084 crtc->cpu_fifo_underrun_disabled = true;
13085 crtc->pch_fifo_underrun_disabled = true;
13086 }
Daniel Vetter24929352012-07-02 20:28:59 +020013087}
13088
13089static void intel_sanitize_encoder(struct intel_encoder *encoder)
13090{
13091 struct intel_connector *connector;
13092 struct drm_device *dev = encoder->base.dev;
13093
13094 /* We need to check both for a crtc link (meaning that the
13095 * encoder is active and trying to read from a pipe) and the
13096 * pipe itself being active. */
13097 bool has_active_crtc = encoder->base.crtc &&
13098 to_intel_crtc(encoder->base.crtc)->active;
13099
13100 if (encoder->connectors_active && !has_active_crtc) {
13101 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13102 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013103 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020013104
13105 /* Connector is active, but has no active pipe. This is
13106 * fallout from our resume register restoring. Disable
13107 * the encoder manually again. */
13108 if (encoder->base.crtc) {
13109 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13110 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013111 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020013112 encoder->disable(encoder);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030013113 if (encoder->post_disable)
13114 encoder->post_disable(encoder);
Daniel Vetter24929352012-07-02 20:28:59 +020013115 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020013116 encoder->base.crtc = NULL;
13117 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020013118
13119 /* Inconsistent output/port/pipe state happens presumably due to
13120 * a bug in one of the get_hw_state functions. Or someplace else
13121 * in our code, like the register restore mess on resume. Clamp
13122 * things to off as a safer default. */
13123 list_for_each_entry(connector,
13124 &dev->mode_config.connector_list,
13125 base.head) {
13126 if (connector->encoder != encoder)
13127 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020013128 connector->base.dpms = DRM_MODE_DPMS_OFF;
13129 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020013130 }
13131 }
13132 /* Enabled encoders without active connectors will be fixed in
13133 * the crtc fixup. */
13134}
13135
Imre Deak04098752014-02-18 00:02:16 +020013136void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013137{
13138 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020013139 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013140
Imre Deak04098752014-02-18 00:02:16 +020013141 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13142 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13143 i915_disable_vga(dev);
13144 }
13145}
13146
13147void i915_redisable_vga(struct drm_device *dev)
13148{
13149 struct drm_i915_private *dev_priv = dev->dev_private;
13150
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013151 /* This function can be called both from intel_modeset_setup_hw_state or
13152 * at a very early point in our resume sequence, where the power well
13153 * structures are not yet restored. Since this function is at a very
13154 * paranoid "someone might have enabled VGA while we were not looking"
13155 * level, just check if the power well is enabled instead of trying to
13156 * follow the "don't touch the power well if we don't need it" policy
13157 * the rest of the driver uses. */
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013158 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013159 return;
13160
Imre Deak04098752014-02-18 00:02:16 +020013161 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013162}
13163
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013164static bool primary_get_hw_state(struct intel_crtc *crtc)
13165{
13166 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13167
13168 if (!crtc->active)
13169 return false;
13170
13171 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13172}
13173
Daniel Vetter30e984d2013-06-05 13:34:17 +020013174static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020013175{
13176 struct drm_i915_private *dev_priv = dev->dev_private;
13177 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020013178 struct intel_crtc *crtc;
13179 struct intel_encoder *encoder;
13180 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020013181 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020013182
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013183 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010013184 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020013185
Daniel Vetter99535992014-04-13 12:00:33 +020013186 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13187
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013188 crtc->active = dev_priv->display.get_pipe_config(crtc,
13189 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013190
13191 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013192 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020013193
13194 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13195 crtc->base.base.id,
13196 crtc->active ? "enabled" : "disabled");
13197 }
13198
Daniel Vetter53589012013-06-05 13:34:16 +020013199 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13200 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13201
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013202 pll->on = pll->get_hw_state(dev_priv, pll,
13203 &pll->config.hw_state);
Daniel Vetter53589012013-06-05 13:34:16 +020013204 pll->active = 0;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013205 pll->config.crtc_mask = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013206 for_each_intel_crtc(dev, crtc) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013207 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
Daniel Vetter53589012013-06-05 13:34:16 +020013208 pll->active++;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013209 pll->config.crtc_mask |= 1 << crtc->pipe;
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013210 }
Daniel Vetter53589012013-06-05 13:34:16 +020013211 }
Daniel Vetter53589012013-06-05 13:34:16 +020013212
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013213 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013214 pll->name, pll->config.crtc_mask, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013215
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013216 if (pll->config.crtc_mask)
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013217 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020013218 }
13219
Damien Lespiaub2784e12014-08-05 11:29:37 +010013220 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013221 pipe = 0;
13222
13223 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070013224 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13225 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010013226 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013227 } else {
13228 encoder->base.crtc = NULL;
13229 }
13230
13231 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013232 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020013233 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013234 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013235 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013236 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020013237 }
13238
13239 list_for_each_entry(connector, &dev->mode_config.connector_list,
13240 base.head) {
13241 if (connector->get_hw_state(connector)) {
13242 connector->base.dpms = DRM_MODE_DPMS_ON;
13243 connector->encoder->connectors_active = true;
13244 connector->base.encoder = &connector->encoder->base;
13245 } else {
13246 connector->base.dpms = DRM_MODE_DPMS_OFF;
13247 connector->base.encoder = NULL;
13248 }
13249 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13250 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030013251 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013252 connector->base.encoder ? "enabled" : "disabled");
13253 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020013254}
13255
13256/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13257 * and i915 state tracking structures. */
13258void intel_modeset_setup_hw_state(struct drm_device *dev,
13259 bool force_restore)
13260{
13261 struct drm_i915_private *dev_priv = dev->dev_private;
13262 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013263 struct intel_crtc *crtc;
13264 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020013265 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013266
13267 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020013268
Jesse Barnesbabea612013-06-26 18:57:38 +030013269 /*
13270 * Now that we have the config, copy it to each CRTC struct
13271 * Note that this could go away if we move to using crtc_config
13272 * checking everywhere.
13273 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013274 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020013275 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080013276 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030013277 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13278 crtc->base.base.id);
13279 drm_mode_debug_printmodeline(&crtc->base.mode);
13280 }
13281 }
13282
Daniel Vetter24929352012-07-02 20:28:59 +020013283 /* HW state is read out, now we need to sanitize this mess. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010013284 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013285 intel_sanitize_encoder(encoder);
13286 }
13287
Damien Lespiau055e3932014-08-18 13:49:10 +010013288 for_each_pipe(dev_priv, pipe) {
Daniel Vetter24929352012-07-02 20:28:59 +020013289 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13290 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020013291 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020013292 }
Daniel Vetter9a935852012-07-05 22:34:27 +020013293
Daniel Vetter35c95372013-07-17 06:55:04 +020013294 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13295 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13296
13297 if (!pll->on || pll->active)
13298 continue;
13299
13300 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13301
13302 pll->disable(dev_priv, pll);
13303 pll->on = false;
13304 }
13305
Pradeep Bhat30789992014-11-04 17:06:45 +000013306 if (IS_GEN9(dev))
13307 skl_wm_get_hw_state(dev);
13308 else if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030013309 ilk_wm_get_hw_state(dev);
13310
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013311 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030013312 i915_redisable_vga(dev);
13313
Daniel Vetterf30da182013-04-11 20:22:50 +020013314 /*
13315 * We need to use raw interfaces for restoring state to avoid
13316 * checking (bogus) intermediate states.
13317 */
Damien Lespiau055e3932014-08-18 13:49:10 +010013318 for_each_pipe(dev_priv, pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070013319 struct drm_crtc *crtc =
13320 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020013321
Jesse Barnes7f271262014-11-05 14:26:06 -080013322 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13323 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013324 }
13325 } else {
13326 intel_modeset_update_staged_output_state(dev);
13327 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013328
13329 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010013330}
13331
13332void intel_modeset_gem_init(struct drm_device *dev)
13333{
Jesse Barnes484b41d2014-03-07 08:57:55 -080013334 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070013335 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013336
Imre Deakae484342014-03-31 15:10:44 +030013337 mutex_lock(&dev->struct_mutex);
13338 intel_init_gt_powersave(dev);
13339 mutex_unlock(&dev->struct_mutex);
13340
Chris Wilson1833b132012-05-09 11:56:28 +010013341 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020013342
13343 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080013344
13345 /*
13346 * Make sure any fbs we allocated at startup are properly
13347 * pinned & fenced. When we do the allocation it's too early
13348 * for this.
13349 */
13350 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010013351 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070013352 obj = intel_fb_obj(c->primary->fb);
13353 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080013354 continue;
13355
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +000013356 if (intel_pin_and_fence_fb_obj(c->primary,
13357 c->primary->fb,
13358 NULL)) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080013359 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13360 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100013361 drm_framebuffer_unreference(c->primary->fb);
13362 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013363 }
13364 }
13365 mutex_unlock(&dev->struct_mutex);
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020013366
13367 intel_backlight_register(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080013368}
13369
Imre Deak4932e2c2014-02-11 17:12:48 +020013370void intel_connector_unregister(struct intel_connector *intel_connector)
13371{
13372 struct drm_connector *connector = &intel_connector->base;
13373
13374 intel_panel_destroy_backlight(connector);
Thomas Wood34ea3d32014-05-29 16:57:41 +010013375 drm_connector_unregister(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020013376}
13377
Jesse Barnes79e53942008-11-07 14:24:08 -080013378void intel_modeset_cleanup(struct drm_device *dev)
13379{
Jesse Barnes652c3932009-08-17 13:31:43 -070013380 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid9255d52013-09-26 20:05:59 -030013381 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070013382
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020013383 intel_backlight_unregister(dev);
13384
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013385 /*
13386 * Interrupts and polling as the first thing to avoid creating havoc.
13387 * Too much stuff here (turning of rps, connectors, ...) would
13388 * experience fancy races otherwise.
13389 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +020013390 intel_irq_uninstall(dev_priv);
Jesse Barneseb21b922014-06-20 11:57:33 -070013391
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013392 /*
13393 * Due to the hpd irq storm handling the hotplug work can re-arm the
13394 * poll handlers. Hence disable polling after hpd handling is shut down.
13395 */
Keith Packardf87ea762010-10-03 19:36:26 -070013396 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013397
Jesse Barnes652c3932009-08-17 13:31:43 -070013398 mutex_lock(&dev->struct_mutex);
13399
Jesse Barnes723bfd72010-10-07 16:01:13 -070013400 intel_unregister_dsm_handler();
13401
Chris Wilson973d04f2011-07-08 12:22:37 +010013402 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070013403
Daniel Vetter8090c6b2012-06-24 16:42:32 +020013404 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000013405
Daniel Vetter930ebb42012-06-29 23:32:16 +020013406 ironlake_teardown_rc6(dev);
13407
Kristian Høgsberg69341a52009-11-11 12:19:17 -050013408 mutex_unlock(&dev->struct_mutex);
13409
Chris Wilson1630fe72011-07-08 12:22:42 +010013410 /* flush any delayed tasks or pending work */
13411 flush_scheduled_work();
13412
Jani Nikuladb31af12013-11-08 16:48:53 +020013413 /* destroy the backlight and sysfs files before encoders/connectors */
13414 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020013415 struct intel_connector *intel_connector;
13416
13417 intel_connector = to_intel_connector(connector);
13418 intel_connector->unregister(intel_connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020013419 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030013420
Jesse Barnes79e53942008-11-07 14:24:08 -080013421 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010013422
13423 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030013424
13425 mutex_lock(&dev->struct_mutex);
13426 intel_cleanup_gt_powersave(dev);
13427 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013428}
13429
Dave Airlie28d52042009-09-21 14:33:58 +100013430/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080013431 * Return which encoder is currently attached for connector.
13432 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010013433struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080013434{
Chris Wilsondf0e9242010-09-09 16:20:55 +010013435 return &intel_attached_encoder(connector)->base;
13436}
Jesse Barnes79e53942008-11-07 14:24:08 -080013437
Chris Wilsondf0e9242010-09-09 16:20:55 +010013438void intel_connector_attach_encoder(struct intel_connector *connector,
13439 struct intel_encoder *encoder)
13440{
13441 connector->encoder = encoder;
13442 drm_mode_connector_attach_encoder(&connector->base,
13443 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080013444}
Dave Airlie28d52042009-09-21 14:33:58 +100013445
13446/*
13447 * set vga decode state - true == enable VGA decode
13448 */
13449int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13450{
13451 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000013452 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100013453 u16 gmch_ctrl;
13454
Chris Wilson75fa0412014-02-07 18:37:02 -020013455 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13456 DRM_ERROR("failed to read control word\n");
13457 return -EIO;
13458 }
13459
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020013460 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13461 return 0;
13462
Dave Airlie28d52042009-09-21 14:33:58 +100013463 if (state)
13464 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13465 else
13466 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020013467
13468 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13469 DRM_ERROR("failed to write control word\n");
13470 return -EIO;
13471 }
13472
Dave Airlie28d52042009-09-21 14:33:58 +100013473 return 0;
13474}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013475
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013476struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013477
13478 u32 power_well_driver;
13479
Chris Wilson63b66e52013-08-08 15:12:06 +020013480 int num_transcoders;
13481
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013482 struct intel_cursor_error_state {
13483 u32 control;
13484 u32 position;
13485 u32 base;
13486 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010013487 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013488
13489 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013490 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013491 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030013492 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010013493 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013494
13495 struct intel_plane_error_state {
13496 u32 control;
13497 u32 stride;
13498 u32 size;
13499 u32 pos;
13500 u32 addr;
13501 u32 surface;
13502 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010013503 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020013504
13505 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013506 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020013507 enum transcoder cpu_transcoder;
13508
13509 u32 conf;
13510
13511 u32 htotal;
13512 u32 hblank;
13513 u32 hsync;
13514 u32 vtotal;
13515 u32 vblank;
13516 u32 vsync;
13517 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013518};
13519
13520struct intel_display_error_state *
13521intel_display_capture_error_state(struct drm_device *dev)
13522{
Jani Nikulafbee40d2014-03-31 14:27:18 +030013523 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013524 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020013525 int transcoders[] = {
13526 TRANSCODER_A,
13527 TRANSCODER_B,
13528 TRANSCODER_C,
13529 TRANSCODER_EDP,
13530 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013531 int i;
13532
Chris Wilson63b66e52013-08-08 15:12:06 +020013533 if (INTEL_INFO(dev)->num_pipes == 0)
13534 return NULL;
13535
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013536 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013537 if (error == NULL)
13538 return NULL;
13539
Imre Deak190be112013-11-25 17:15:31 +020013540 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013541 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13542
Damien Lespiau055e3932014-08-18 13:49:10 +010013543 for_each_pipe(dev_priv, i) {
Imre Deakddf9c532013-11-27 22:02:02 +020013544 error->pipe[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013545 __intel_display_power_is_enabled(dev_priv,
13546 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020013547 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013548 continue;
13549
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030013550 error->cursor[i].control = I915_READ(CURCNTR(i));
13551 error->cursor[i].position = I915_READ(CURPOS(i));
13552 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013553
13554 error->plane[i].control = I915_READ(DSPCNTR(i));
13555 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013556 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030013557 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013558 error->plane[i].pos = I915_READ(DSPPOS(i));
13559 }
Paulo Zanonica291362013-03-06 20:03:14 -030013560 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13561 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013562 if (INTEL_INFO(dev)->gen >= 4) {
13563 error->plane[i].surface = I915_READ(DSPSURF(i));
13564 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13565 }
13566
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013567 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030013568
Sonika Jindal3abfce72014-07-21 15:23:43 +053013569 if (HAS_GMCH_DISPLAY(dev))
Imre Deakf301b1e2014-04-18 15:55:04 +030013570 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020013571 }
13572
13573 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13574 if (HAS_DDI(dev_priv->dev))
13575 error->num_transcoders++; /* Account for eDP. */
13576
13577 for (i = 0; i < error->num_transcoders; i++) {
13578 enum transcoder cpu_transcoder = transcoders[i];
13579
Imre Deakddf9c532013-11-27 22:02:02 +020013580 error->transcoder[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013581 __intel_display_power_is_enabled(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020013582 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013583 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013584 continue;
13585
Chris Wilson63b66e52013-08-08 15:12:06 +020013586 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13587
13588 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13589 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13590 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13591 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13592 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13593 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13594 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013595 }
13596
13597 return error;
13598}
13599
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013600#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13601
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013602void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013603intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013604 struct drm_device *dev,
13605 struct intel_display_error_state *error)
13606{
Damien Lespiau055e3932014-08-18 13:49:10 +010013607 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013608 int i;
13609
Chris Wilson63b66e52013-08-08 15:12:06 +020013610 if (!error)
13611 return;
13612
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013613 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020013614 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013615 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013616 error->power_well_driver);
Damien Lespiau055e3932014-08-18 13:49:10 +010013617 for_each_pipe(dev_priv, i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013618 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020013619 err_printf(m, " Power: %s\n",
13620 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013621 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030013622 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013623
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013624 err_printf(m, "Plane [%d]:\n", i);
13625 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13626 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013627 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013628 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13629 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013630 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030013631 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013632 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013633 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013634 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13635 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013636 }
13637
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013638 err_printf(m, "Cursor [%d]:\n", i);
13639 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13640 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13641 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013642 }
Chris Wilson63b66e52013-08-08 15:12:06 +020013643
13644 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010013645 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020013646 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013647 err_printf(m, " Power: %s\n",
13648 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020013649 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13650 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13651 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13652 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13653 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13654 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13655 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13656 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013657}
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013658
13659void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13660{
13661 struct intel_crtc *crtc;
13662
13663 for_each_intel_crtc(dev, crtc) {
13664 struct intel_unpin_work *work;
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013665
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020013666 spin_lock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013667
13668 work = crtc->unpin_work;
13669
13670 if (work && work->event &&
13671 work->event->base.file_priv == file) {
13672 kfree(work->event);
13673 work->event = NULL;
13674 }
13675
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020013676 spin_unlock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013677 }
13678}