blob: 2632f2adc319b7e2f5aba9ae1c2dc34e2d931d76 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070042#include <drm/drm_plane_helper.h>
43#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080044#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080045
Matt Roper465c1202014-05-29 08:06:54 -070046/* Primary plane formats supported by all gen */
47#define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53/* Primary plane formats for gen <= 3 */
54static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58};
59
60/* Primary plane formats for gen >= 4 */
61static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69};
70
Matt Roper3d7d6512014-06-10 08:28:13 -070071/* Cursor formats */
72static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74};
75
Chris Wilson6b383a72010-09-13 13:54:26 +010076static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080077
Jesse Barnesf1f644d2013-06-27 00:39:25 +030078static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030080static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030082
Damien Lespiaue7457a92013-08-08 22:28:59 +010083static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
Jesse Barneseb1bfe82014-02-12 12:26:25 -080085static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020089static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +020091static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -070092 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +020094static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +020095static void haswell_set_pipeconf(struct drm_crtc *crtc);
96static void intel_set_pipe_csc(struct drm_crtc *crtc);
Ville Syrjäläd288f652014-10-28 13:20:22 +020097static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100101
Dave Airlie0e32b392014-05-02 14:02:48 +1000102static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103{
104 if (!connector->mst_port)
105 return connector->encoder;
106 else
107 return &connector->mst_port->mst_encoders[pipe]->base;
108}
109
Jesse Barnes79e53942008-11-07 14:24:08 -0800110typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400111 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800112} intel_range_t;
113
114typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400115 int dot_limit;
116 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800117} intel_p2_t;
118
Ma Lingd4906092009-03-18 20:13:27 +0800119typedef struct intel_limit intel_limit_t;
120struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
122 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800123};
Jesse Barnes79e53942008-11-07 14:24:08 -0800124
Daniel Vetterd2acd212012-10-20 20:57:43 +0200125int
126intel_pch_rawclk(struct drm_device *dev)
127{
128 struct drm_i915_private *dev_priv = dev->dev_private;
129
130 WARN_ON(!HAS_PCH_SPLIT(dev));
131
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133}
134
Chris Wilson021357a2010-09-07 20:54:59 +0100135static inline u32 /* units of 100MHz */
136intel_fdi_link_freq(struct drm_device *dev)
137{
Chris Wilson8b99e682010-10-13 09:59:17 +0100138 if (IS_GEN5(dev)) {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141 } else
142 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100143}
144
Daniel Vetter5d536e22013-07-06 12:52:06 +0200145static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400146 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200147 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200148 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
Daniel Vetter5d536e22013-07-06 12:52:06 +0200158static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200160 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200161 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
169};
170
Keith Packarde4b36692009-06-05 19:22:17 -0700171static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400172 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200173 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200174 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700182};
Eric Anholt273e27c2011-03-30 13:01:10 -0700183
Keith Packarde4b36692009-06-05 19:22:17 -0700184static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700195};
196
197static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700208};
209
Eric Anholt273e27c2011-03-30 13:01:10 -0700210
Keith Packarde4b36692009-06-05 19:22:17 -0700211static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
221 .p2_slow = 10,
222 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800223 },
Keith Packarde4b36692009-06-05 19:22:17 -0700224};
225
226static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700237};
238
239static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800250 },
Keith Packarde4b36692009-06-05 19:22:17 -0700251};
252
253static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800264 },
Keith Packarde4b36692009-06-05 19:22:17 -0700265};
266
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500267static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700270 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700280};
281
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500282static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700293};
294
Eric Anholt273e27c2011-03-30 13:01:10 -0700295/* Ironlake / Sandybridge
296 *
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
299 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800300static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700311};
312
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800313static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800324};
325
326static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800337};
338
Eric Anholt273e27c2011-03-30 13:01:10 -0700339/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800340static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400348 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800351};
352
353static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400361 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800364};
365
Ville Syrjälädc730512013-09-24 21:26:30 +0300366static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300367 /*
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
372 */
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200374 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700375 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300378 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700380};
381
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300382static const intel_limit_t intel_limits_chv = {
383 /*
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
388 */
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396};
397
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300398static void vlv_clock(int refclk, intel_clock_t *clock)
399{
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200402 if (WARN_ON(clock->n == 0 || clock->p == 0))
403 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300406}
407
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300408/**
409 * Returns whether any output on the specified pipe is of the specified type
410 */
Damien Lespiau40935612014-10-29 11:16:59 +0000411bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300412{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300413 struct drm_device *dev = crtc->base.dev;
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300414 struct intel_encoder *encoder;
415
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300417 if (encoder->type == type)
418 return true;
419
420 return false;
421}
422
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200423/**
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427 * encoder->crtc.
428 */
429static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
430{
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
433
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
436 return true;
437
438 return false;
439}
440
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300441static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
Chris Wilson1b894b52010-12-14 20:04:54 +0000442 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800443{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300444 struct drm_device *dev = crtc->base.dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800445 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800446
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100448 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000449 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800450 limit = &intel_limits_ironlake_dual_lvds_100m;
451 else
452 limit = &intel_limits_ironlake_dual_lvds;
453 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000454 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800455 limit = &intel_limits_ironlake_single_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_single_lvds;
458 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200459 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800460 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800461
462 return limit;
463}
464
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300465static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
Ma Ling044c7c42009-03-18 20:13:23 +0800466{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300467 struct drm_device *dev = crtc->base.dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800468 const intel_limit_t *limit;
469
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100471 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700472 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800473 else
Keith Packarde4b36692009-06-05 19:22:17 -0700474 limit = &intel_limits_g4x_single_channel_lvds;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700477 limit = &intel_limits_g4x_hdmi;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700479 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800480 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700481 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800482
483 return limit;
484}
485
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300486static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800487{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300488 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800489 const intel_limit_t *limit;
490
Eric Anholtbad720f2009-10-22 16:11:14 -0700491 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000492 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800493 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800494 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500495 } else if (IS_PINEVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500497 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800498 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500499 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700502 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300503 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100504 } else if (!IS_GEN2(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100506 limit = &intel_limits_i9xx_lvds;
507 else
508 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800509 } else {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700511 limit = &intel_limits_i8xx_lvds;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700513 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200514 else
515 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800516 }
517 return limit;
518}
519
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500520/* m1 is reserved as 0 in Pineview, n is a ring counter */
521static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800522{
Shaohua Li21778322009-02-23 15:19:16 +0800523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800529}
530
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200531static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532{
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534}
535
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200536static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800537{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200538 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800539 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
541 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800544}
545
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300546static void chv_clock(int refclk, intel_clock_t *clock)
547{
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
553 clock->n << 22);
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555}
556
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800557#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800558/**
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
561 */
562
Chris Wilson1b894b52010-12-14 20:04:54 +0000563static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800566{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400570 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400572 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400574 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300575
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
579
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
585 }
586
Jesse Barnes79e53942008-11-07 14:24:08 -0800587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400588 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
591 */
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400593 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800594
595 return true;
596}
597
Ma Lingd4906092009-03-18 20:13:27 +0800598static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300599i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800602{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300603 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800604 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800605 int err = target;
606
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800608 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800612 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100613 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800614 clock.p2 = limit->p2.p2_fast;
615 else
616 clock.p2 = limit->p2.p2_slow;
617 } else {
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
620 else
621 clock.p2 = limit->p2.p2_fast;
622 }
623
Akshay Joshi0206e352011-08-16 15:34:10 -0400624 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800625
Zhao Yakui42158662009-11-20 11:24:18 +0800626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
627 clock.m1++) {
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200630 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800631 break;
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800636 int this_err;
637
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200638 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000639 if (!intel_PLL_is_valid(dev, limit,
640 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800641 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657}
658
Ma Lingd4906092009-03-18 20:13:27 +0800659static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300660pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200663{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300664 struct drm_device *dev = crtc->base.dev;
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200665 intel_clock_t clock;
666 int err = target;
667
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200669 /*
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
673 */
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
676 else
677 clock.p2 = limit->p2.p2_slow;
678 } else {
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
681 else
682 clock.p2 = limit->p2.p2_fast;
683 }
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800698 if (!intel_PLL_is_valid(dev, limit,
699 &clock))
700 continue;
701 if (match_clock &&
702 clock.p != match_clock->p)
703 continue;
704
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
707 *best_clock = clock;
708 err = this_err;
709 }
710 }
711 }
712 }
713 }
714
715 return (err != target);
716}
717
Ma Lingd4906092009-03-18 20:13:27 +0800718static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300719g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800722{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300723 struct drm_device *dev = crtc->base.dev;
Ma Lingd4906092009-03-18 20:13:27 +0800724 intel_clock_t clock;
725 int max_n;
726 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800729 found = false;
730
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100732 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800733 clock.p2 = limit->p2.p2_fast;
734 else
735 clock.p2 = limit->p2.p2_slow;
736 } else {
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
739 else
740 clock.p2 = limit->p2.p2_fast;
741 }
742
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200745 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200747 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
754 int this_err;
755
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200756 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800759 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000760
761 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800762 if (this_err < err_most) {
763 *best_clock = clock;
764 err_most = this_err;
765 max_n = clock.n;
766 found = true;
767 }
768 }
769 }
770 }
771 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800772 return found;
773}
Ma Lingd4906092009-03-18 20:13:27 +0800774
Zhenyu Wang2c072452009-06-05 15:38:42 +0800775static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300776vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700779{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300780 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300781 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300782 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300785 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700786
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300787 target *= 5; /* fast clock */
788
789 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700790
791 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300796 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700797 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300799 unsigned int ppm, diff;
800
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
802 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300803
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300804 vlv_clock(refclk, &clock);
805
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300808 continue;
809
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
812
813 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300814 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300815 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300816 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300817 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300818
Ville Syrjäläc6861222013-09-24 21:26:21 +0300819 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300820 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300821 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300822 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700823 }
824 }
825 }
826 }
827 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700828
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300829 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700830}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700831
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300832static bool
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300833chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
836{
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300837 struct drm_device *dev = crtc->base.dev;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300838 intel_clock_t clock;
839 uint64_t m2;
840 int found = false;
841
842 memset(best_clock, 0, sizeof(*best_clock));
843
844 /*
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
848 */
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
851
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856
857 clock.p = clock.p1 * clock.p2;
858
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
861
862 if (m2 > INT_MAX/clock.m1)
863 continue;
864
865 clock.m2 = m2;
866
867 chv_clock(refclk, &clock);
868
869 if (!intel_PLL_is_valid(dev, limit, &clock))
870 continue;
871
872 /* based on hardware requirement, prefer bigger p
873 */
874 if (clock.p > best_clock->p) {
875 *best_clock = clock;
876 found = true;
877 }
878 }
879 }
880
881 return found;
882}
883
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300884bool intel_crtc_active(struct drm_crtc *crtc)
885{
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
890 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100891 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300892 * as Haswell has gained clock readout/fastboot support.
893 *
Dave Airlie66e514c2014-04-03 07:51:54 +1000894 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300895 * properly reconstruct framebuffers.
896 */
Matt Roperf4510a22014-04-01 15:22:40 -0700897 return intel_crtc->active && crtc->primary->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100898 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300899}
900
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200901enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902 enum pipe pipe)
903{
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906
Daniel Vetter3b117c82013-04-17 20:15:07 +0200907 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200908}
909
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300910static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
911{
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
914 u32 line1, line2;
915 u32 line_mask;
916
917 if (IS_GEN2(dev))
918 line_mask = DSL_LINEMASK_GEN2;
919 else
920 line_mask = DSL_LINEMASK_GEN3;
921
922 line1 = I915_READ(reg) & line_mask;
923 mdelay(5);
924 line2 = I915_READ(reg) & line_mask;
925
926 return line1 == line2;
927}
928
Keith Packardab7ad7f2010-10-03 00:33:06 -0700929/*
930 * intel_wait_for_pipe_off - wait for pipe to turn off
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300931 * @crtc: crtc whose pipe to wait for
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700932 *
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
936 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700937 * On Gen4 and above:
938 * wait for the pipe register state bit to turn off
939 *
940 * Otherwise:
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100943 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700944 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300945static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700946{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300947 struct drm_device *dev = crtc->base.dev;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700948 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +0300949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700951
Keith Packardab7ad7f2010-10-03 00:33:06 -0700952 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200953 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700954
Keith Packardab7ad7f2010-10-03 00:33:06 -0700955 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
957 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200958 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700959 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700960 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200962 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700963 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800964}
965
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000966/*
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
970 *
971 * Returns true if @port is connected, false otherwise.
972 */
973bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
975{
976 u32 bit;
977
Damien Lespiauc36346e2012-12-13 16:09:03 +0000978 if (HAS_PCH_IBX(dev_priv->dev)) {
Robin Schroereba905b2014-05-18 02:24:50 +0200979 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000980 case PORT_B:
981 bit = SDE_PORTB_HOTPLUG;
982 break;
983 case PORT_C:
984 bit = SDE_PORTC_HOTPLUG;
985 break;
986 case PORT_D:
987 bit = SDE_PORTD_HOTPLUG;
988 break;
989 default:
990 return true;
991 }
992 } else {
Robin Schroereba905b2014-05-18 02:24:50 +0200993 switch (port->port) {
Damien Lespiauc36346e2012-12-13 16:09:03 +0000994 case PORT_B:
995 bit = SDE_PORTB_HOTPLUG_CPT;
996 break;
997 case PORT_C:
998 bit = SDE_PORTC_HOTPLUG_CPT;
999 break;
1000 case PORT_D:
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1002 break;
1003 default:
1004 return true;
1005 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001006 }
1007
1008 return I915_READ(SDEISR) & bit;
1009}
1010
Jesse Barnesb24e7172011-01-04 15:09:30 -08001011static const char *state_string(bool enabled)
1012{
1013 return enabled ? "on" : "off";
1014}
1015
1016/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001017void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001019{
1020 int reg;
1021 u32 val;
1022 bool cur_state;
1023
1024 reg = DPLL(pipe);
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1030}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001031
Jani Nikula23538ef2013-08-27 15:12:22 +03001032/* XXX: the dsi pll is shared between MIPI DSI ports */
1033static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034{
1035 u32 val;
1036 bool cur_state;
1037
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1041
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1046}
1047#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
Daniel Vetter55607e82013-06-16 21:42:39 +02001050struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001051intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001052{
Daniel Vettere2b78262013-06-07 23:10:03 +02001053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
Daniel Vettera43f6e02013-06-07 23:10:32 +02001055 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001056 return NULL;
1057
Daniel Vettera43f6e02013-06-07 23:10:32 +02001058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001059}
1060
Jesse Barnesb24e7172011-01-04 15:09:30 -08001061/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001062void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1064 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001065{
Jesse Barnes040484a2011-01-03 12:14:26 -08001066 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001067 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001068
Chris Wilson92b27b02012-05-20 18:10:50 +01001069 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001070 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001072
Daniel Vetter53589012013-06-05 13:34:16 +02001073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +01001074 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001077}
Jesse Barnes040484a2011-01-03 12:14:26 -08001078
1079static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081{
1082 int reg;
1083 u32 val;
1084 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001087
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001091 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101}
1102#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107{
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118}
1119#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001130 return;
1131
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001133 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001134 return;
1135
Jesse Barnes040484a2011-01-03 12:14:26 -08001136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139}
1140
Daniel Vetter55607e82013-06-16 21:42:39 +02001141void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001143{
1144 int reg;
1145 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001146 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001154}
1155
Daniel Vetterb680c372014-09-19 18:27:27 +02001156void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
Jesse Barnesea0760c2011-01-04 15:09:32 -08001158{
Jani Nikulabedd4db2014-08-22 15:04:13 +03001159 struct drm_device *dev = dev_priv->dev;
1160 int pp_reg;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001161 u32 val;
1162 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001163 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001164
Jani Nikulabedd4db2014-08-22 15:04:13 +03001165 if (WARN_ON(HAS_DDI(dev)))
1166 return;
1167
1168 if (HAS_PCH_SPLIT(dev)) {
1169 u32 port_sel;
1170
Jesse Barnesea0760c2011-01-04 15:09:32 -08001171 pp_reg = PCH_PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181 panel_pipe = pipe;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001182 } else {
1183 pp_reg = PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001186 }
1187
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
Jani Nikulaec49ba22014-08-21 15:06:25 +03001190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
Jesse Barnesea0760c2011-01-04 15:09:32 -08001191 locked = false;
1192
Jesse Barnesea0760c2011-01-04 15:09:32 -08001193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001195 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001196}
1197
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001198static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200{
1201 struct drm_device *dev = dev_priv->dev;
1202 bool cur_state;
1203
Paulo Zanonid9d82082014-02-27 16:30:56 -03001204 if (IS_845G(dev) || IS_I865G(dev))
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001206 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001208
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1212}
1213#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001216void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001218{
1219 int reg;
1220 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001221 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001224
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetter8e636782012-01-22 01:36:48 +01001228 state = true;
1229
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001230 if (!intel_display_power_is_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001241 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001242}
1243
Chris Wilson931872f2012-01-16 23:01:13 +00001244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001246{
1247 int reg;
1248 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001249 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001257}
1258
Chris Wilson931872f2012-01-16 23:01:13 +00001259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
Jesse Barnesb24e7172011-01-04 15:09:30 -08001262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001265 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001266 int reg, i;
1267 u32 val;
1268 int cur_pipe;
1269
Ville Syrjälä653e1022013-06-04 13:49:05 +03001270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001274 WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001275 "plane %c assertion failure, should be disabled but not\n",
1276 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001277 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001278 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001279
Jesse Barnesb24e7172011-01-04 15:09:30 -08001280 /* Need to check both planes against the pipe */
Damien Lespiau055e3932014-08-18 13:49:10 +01001281 for_each_pipe(dev_priv, i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001282 reg = DSPCNTR(i);
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001289 }
1290}
1291
Jesse Barnes19332d72013-03-28 09:55:38 -07001292static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe)
1294{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001295 struct drm_device *dev = dev_priv->dev;
Damien Lespiau1fe47782014-03-03 17:31:47 +00001296 int reg, sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001297 u32 val;
1298
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1305 }
1306 } else if (IS_VALLEYVIEW(dev)) {
Damien Lespiau1fe47782014-03-03 17:31:47 +00001307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001309 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001310 WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001312 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001313 }
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1315 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001316 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001317 WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
Damien Lespiau83f26f12014-03-17 17:59:48 +00001323 WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001326 }
1327}
1328
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001329static void assert_vblank_disabled(struct drm_crtc *crtc)
1330{
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1333}
1334
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001335static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001336{
1337 u32 val;
1338 bool enabled;
1339
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001341
Jesse Barnes92f25842011-01-04 15:09:34 -08001342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346}
1347
Daniel Vetterab9412b2013-05-03 11:49:46 +02001348static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001350{
1351 int reg;
1352 u32 val;
1353 bool enabled;
1354
Daniel Vetterab9412b2013-05-03 11:49:46 +02001355 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001358 WARN(enabled,
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001361}
1362
Keith Packard4e634382011-08-06 10:39:45 -07001363static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001365{
1366 if ((val & DP_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001377 } else {
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379 return false;
1380 }
1381 return true;
1382}
1383
Keith Packard1519b992011-08-06 10:35:34 -07001384static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1386{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001387 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001388 return false;
1389
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001392 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001396 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001398 return false;
1399 }
1400 return true;
1401}
1402
1403static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1405{
1406 if ((val & LVDS_PORT_EN) == 0)
1407 return false;
1408
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411 return false;
1412 } else {
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414 return false;
1415 }
1416 return true;
1417}
1418
1419static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421{
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1423 return false;
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426 return false;
1427 } else {
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429 return false;
1430 }
1431 return true;
1432}
1433
Jesse Barnes291906f2011-02-02 12:28:03 -08001434static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001435 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001436{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001437 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001440 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001441
Daniel Vetter75c5da22012-09-10 21:58:29 +02001442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001444 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001445}
1446
1447static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1449{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001450 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001453 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001454
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001456 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001457 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001458}
1459
1460static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe)
1462{
1463 int reg;
1464 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001465
Keith Packardf0575e92011-07-25 22:12:43 -07001466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001469
1470 reg = PCH_ADPA;
1471 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001473 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001474 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001475
1476 reg = PCH_LVDS;
1477 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001480 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001481
Paulo Zanonie2debe92013-02-18 19:00:27 -03001482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001485}
1486
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001487static void intel_init_dpio(struct drm_device *dev)
1488{
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491 if (!IS_VALLEYVIEW(dev))
1492 return;
1493
Chon Ming Leea09cadd2014-04-09 13:28:14 +03001494 /*
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498 */
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502 } else {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504 }
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001505}
1506
Ville Syrjäläd288f652014-10-28 13:20:22 +02001507static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001509{
Daniel Vetter426115c2013-07-11 22:13:42 +02001510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
Ville Syrjäläd288f652014-10-28 13:20:22 +02001513 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001514
Daniel Vetter426115c2013-07-11 22:13:42 +02001515 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001516
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001517 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520 /* PLL is protected by panel, make sure we can write it */
Jani Nikula6a9e7362014-08-22 15:06:35 +03001521 if (IS_MOBILE(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001522 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001523
Daniel Vetter426115c2013-07-11 22:13:42 +02001524 I915_WRITE(reg, dpll);
1525 POSTING_READ(reg);
1526 udelay(150);
1527
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
Ville Syrjäläd288f652014-10-28 13:20:22 +02001531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
Daniel Vetter426115c2013-07-11 22:13:42 +02001532 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001533
1534 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001535 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001536 POSTING_READ(reg);
1537 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001538 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001541 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544}
1545
Ville Syrjäläd288f652014-10-28 13:20:22 +02001546static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001548{
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001553 u32 tmp;
1554
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559 mutex_lock(&dev_priv->dpio_lock);
1560
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566 /*
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568 */
1569 udelay(1);
1570
1571 /* Enable PLL */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001573
1574 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001578 /* not sure when this should be written */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001580 POSTING_READ(DPLL_MD(pipe));
1581
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001582 mutex_unlock(&dev_priv->dpio_lock);
1583}
1584
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001585static int intel_num_dvo_pipes(struct drm_device *dev)
1586{
1587 struct intel_crtc *crtc;
1588 int count = 0;
1589
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001593
1594 return count;
1595}
1596
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001597static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001598{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001603
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001604 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001605
1606 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001608
1609 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001612
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615 /*
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1620 */
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001641
1642 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001643 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001646 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001649 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652}
1653
1654/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001655 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001663static void i9xx_disable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001664{
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1668
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677 }
1678
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001682 return;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
Daniel Vetter50b44a42013-06-05 13:34:33 +02001687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001689}
1690
Jesse Barnesf6071162013-10-01 10:41:38 -07001691static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692{
1693 u32 val = 0;
1694
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1697
Imre Deake5cbfbf2014-01-09 17:08:16 +02001698 /*
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1701 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001702 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001706
1707}
1708
1709static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001712 u32 val;
1713
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001716
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001717 /* Set PLL en = 0 */
Ville Syrjäläd17ec4c2014-06-28 02:03:59 +03001718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001719 if (pipe != PIPE_A)
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001723
1724 mutex_lock(&dev_priv->dpio_lock);
1725
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
Ville Syrjälä61407f62014-05-27 16:32:55 +03001731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736 } else {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740 }
1741
Ville Syrjäläd7520482014-04-09 13:28:59 +03001742 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001743}
1744
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001745void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001747{
1748 u32 port_mask;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001749 int dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001750
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001751 switch (dport->port) {
1752 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001753 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001754 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001755 break;
1756 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001757 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_D:
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001763 break;
1764 default:
1765 BUG();
1766 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001767
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
Jesse Barnes89b667f2013-04-18 14:51:36 -07001769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001770 port_name(dport->port), I915_READ(dpll_reg));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001771}
1772
Daniel Vetterb14b1052014-04-24 23:55:13 +02001773static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774{
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001779 if (WARN_ON(pll == NULL))
1780 return;
1781
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001782 WARN_ON(!pll->config.crtc_mask);
Daniel Vetterb14b1052014-04-24 23:55:13 +02001783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785 WARN_ON(pll->on);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788 pll->mode_set(dev_priv, pll);
1789 }
1790}
1791
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001792/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001793 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1796 *
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1799 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001800static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001801{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001805
Daniel Vetter87a875b2013-06-05 13:34:19 +02001806 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001807 return;
1808
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001809 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001810 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001811
Damien Lespiau74dd6922014-07-29 18:06:17 +01001812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
Daniel Vetter46edb022013-06-05 13:34:12 +02001813 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001814 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001815
Daniel Vettercdbd2312013-06-05 13:34:03 +02001816 if (pll->active++) {
1817 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001818 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001819 return;
1820 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001821 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001822
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
Daniel Vetter46edb022013-06-05 13:34:12 +02001825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001826 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001827 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001828}
1829
Damien Lespiauf6daaec2014-08-09 23:00:56 +01001830static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001831{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001835
Jesse Barnes92f25842011-01-04 15:09:34 -08001836 /* PCH only available on ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001837 BUG_ON(INTEL_INFO(dev)->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001838 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001839 return;
1840
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001841 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001842 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001843
Daniel Vetter46edb022013-06-05 13:34:12 +02001844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001846 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001847
Chris Wilson48da64a2012-05-13 20:16:12 +01001848 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001849 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001850 return;
1851 }
1852
Daniel Vettere9d69442013-06-05 13:34:15 +02001853 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001854 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001855 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001856 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001857
Daniel Vetter46edb022013-06-05 13:34:12 +02001858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001859 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001860 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001861
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001863}
1864
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001865static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001867{
Daniel Vetter23670b322012-11-01 09:15:30 +01001868 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001871 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001872
1873 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03001874 BUG_ON(!HAS_PCH_SPLIT(dev));
Jesse Barnes040484a2011-01-03 12:14:26 -08001875
1876 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001877 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001878 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1883
Daniel Vetter23670b322012-11-01 09:15:30 +01001884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001891 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001892
Daniel Vetterab9412b2013-05-03 11:49:46 +02001893 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001894 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001895 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001896
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1898 /*
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1901 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001904 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001905
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001908 if (HAS_PCH_IBX(dev_priv->dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001910 val |= TRANS_LEGACY_INTERLACED_ILK;
1911 else
1912 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001913 else
1914 val |= TRANS_PROGRESSIVE;
1915
Jesse Barnes040484a2011-01-03 12:14:26 -08001916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001919}
1920
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001921static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001922 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001923{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001924 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001925
1926 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03001927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001928
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001929 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001932
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001936 I915_WRITE(_TRANSA_CHICKEN2, val);
1937
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001938 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001940
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001943 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001944 else
1945 val |= TRANS_PROGRESSIVE;
1946
Daniel Vetterab9412b2013-05-03 11:49:46 +02001947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001949 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001950}
1951
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001952static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001954{
Daniel Vetter23670b322012-11-01 09:15:30 +01001955 struct drm_device *dev = dev_priv->dev;
1956 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001957
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1961
Jesse Barnes291906f2011-02-02 12:28:03 -08001962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1964
Daniel Vetterab9412b2013-05-03 11:49:46 +02001965 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001972
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1979 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001980}
1981
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001982static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001983{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001984 u32 val;
1985
Daniel Vetterab9412b2013-05-03 11:49:46 +02001986 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001987 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001988 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001989 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001991 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001992
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001996 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001997}
1998
1999/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002000 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02002001 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002002 *
Paulo Zanoni03722642014-01-17 13:51:09 -02002003 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002005 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02002006static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002007{
Paulo Zanoni03722642014-01-17 13:51:09 -02002008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002013 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002014 int reg;
2015 u32 val;
2016
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002017 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002018 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002019 assert_sprites_disabled(dev_priv, pipe);
2020
Paulo Zanoni681e5812012-12-06 11:12:38 -02002021 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002022 pch_transcoder = TRANSCODER_A;
2023 else
2024 pch_transcoder = pipe;
2025
Jesse Barnesb24e7172011-01-04 15:09:30 -08002026 /*
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2029 * need the check.
2030 */
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
Jani Nikula23538ef2013-08-27 15:12:22 +03002033 assert_dsi_pll_enabled(dev_priv);
2034 else
2035 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002036 else {
Paulo Zanoni30421c42014-01-17 13:51:10 -02002037 if (crtc->config.has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002038 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002042 }
2043 /* FIXME: assert CPU port conditions for SNB+ */
2044 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002045
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002046 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002047 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002048 if (val & PIPECONF_ENABLE) {
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
Chris Wilson00d70b12011-03-17 07:18:29 +00002051 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002052 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002053
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002055 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002056}
2057
2058/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002059 * intel_disable_pipe - disable a pipe, asserting requirements
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002060 * @crtc: crtc whose pipes is to be disabled
Jesse Barnesb24e7172011-01-04 15:09:30 -08002061 *
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002065 *
2066 * Will wait until the pipe has shut down before returning.
2067 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002068static void intel_disable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002069{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002073 int reg;
2074 u32 val;
2075
2076 /*
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2079 */
2080 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002081 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002082 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002083
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002084 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002085 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
Ville Syrjälä67adc642014-08-15 01:21:57 +03002089 /*
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2092 */
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096 /* Don't disable pipe or pipe PLLs if needed */
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Ville Syrjälä67adc642014-08-15 01:21:57 +03002099 val &= ~PIPECONF_ENABLE;
2100
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002104}
2105
Keith Packardd74362c2011-07-28 14:47:14 -07002106/*
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2109 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002110void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07002112{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00002113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03002115
2116 I915_WRITE(reg, I915_READ(reg));
2117 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07002118}
2119
Jesse Barnesb24e7172011-01-04 15:09:30 -08002120/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002124 *
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002125 * Enable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002126 */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002127static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002129{
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002133
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002136
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002137 if (intel_crtc->primary_enabled)
2138 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002139
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002140 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002141
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2143 crtc->x, crtc->y);
Ville Syrjälä33c3b0d2014-06-24 13:59:28 +03002144
2145 /*
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2149 */
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002152}
2153
Jesse Barnesb24e7172011-01-04 15:09:30 -08002154/**
Matt Roper262ca2b2014-03-18 17:22:55 -07002155 * intel_disable_primary_hw_plane - disable the primary hardware plane
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08002158 *
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002159 * Disable @plane on @crtc, making sure that the pipe is running first.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002160 */
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002161static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002163{
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002169
Ville Syrjälä98ec7732014-04-30 17:43:01 +03002170 if (!intel_crtc->primary_enabled)
2171 return;
Ville Syrjälä0037f712013-10-01 18:02:20 +03002172
Ville Syrjälä4c445e02013-10-09 17:24:58 +03002173 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03002174
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002177}
2178
Chris Wilson693db182013-03-05 14:52:39 +00002179static bool need_vtd_wa(struct drm_device *dev)
2180{
2181#ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184#endif
2185 return false;
2186}
2187
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002188static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189{
2190 int tile_height;
2191
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2194}
2195
Chris Wilson127bd2a2010-07-23 23:32:05 +01002196int
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002197intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198 struct drm_framebuffer *fb,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002199 struct intel_engine_cs *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002200{
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002201 struct drm_device *dev = fb->dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00002202 struct drm_i915_private *dev_priv = dev->dev_private;
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002203 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002204 u32 alignment;
2205 int ret;
2206
Matt Roperebcdd392014-07-09 16:22:11 -07002207 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
Chris Wilson05394f32010-11-08 19:18:58 +00002209 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002210 case I915_TILING_NONE:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002211 if (INTEL_INFO(dev)->gen >= 9)
2212 alignment = 256 * 1024;
2213 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
Chris Wilson534843d2010-07-05 18:01:46 +01002214 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002215 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002216 alignment = 4 * 1024;
2217 else
2218 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002219 break;
2220 case I915_TILING_X:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002221 if (INTEL_INFO(dev)->gen >= 9)
2222 alignment = 256 * 1024;
2223 else {
2224 /* pin() will align the object as required by fence */
2225 alignment = 0;
2226 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002227 break;
2228 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02002229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002230 return -EINVAL;
2231 default:
2232 BUG();
2233 }
2234
Chris Wilson693db182013-03-05 14:52:39 +00002235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2238 * the VT-d warning.
2239 */
2240 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241 alignment = 256 * 1024;
2242
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002243 /*
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2249 */
2250 intel_runtime_pm_get(dev_priv);
2251
Chris Wilsonce453d82011-02-21 14:43:56 +00002252 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002253 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002254 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002255 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002256
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2261 */
Chris Wilson06d98132012-04-17 15:31:24 +01002262 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002263 if (ret)
2264 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002265
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002266 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002267
Chris Wilsonce453d82011-02-21 14:43:56 +00002268 dev_priv->mm.interruptible = true;
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002269 intel_runtime_pm_put(dev_priv);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002270 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002271
2272err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01002273 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002274err_interruptible:
2275 dev_priv->mm.interruptible = true;
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002276 intel_runtime_pm_put(dev_priv);
Chris Wilson48b956c2010-09-14 12:50:34 +01002277 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002278}
2279
Chris Wilson1690e1e2011-12-14 13:57:08 +01002280void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281{
Matt Roperebcdd392014-07-09 16:22:11 -07002282 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
Chris Wilson1690e1e2011-12-14 13:57:08 +01002284 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002285 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002286}
2287
Daniel Vetterc2c75132012-07-05 12:17:30 +02002288/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002290unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291 unsigned int tiling_mode,
2292 unsigned int cpp,
2293 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002294{
Chris Wilsonbc752862013-02-21 20:04:31 +00002295 if (tiling_mode != I915_TILING_NONE) {
2296 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002297
Chris Wilsonbc752862013-02-21 20:04:31 +00002298 tile_rows = *y / 8;
2299 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002300
Chris Wilsonbc752862013-02-21 20:04:31 +00002301 tiles = *x / (512/cpp);
2302 *x %= 512/cpp;
2303
2304 return tile_rows * pitch * 8 + tiles * 4096;
2305 } else {
2306 unsigned int offset;
2307
2308 offset = *y * pitch + *x * cpp;
2309 *y = 0;
2310 *x = (offset & 4095) / cpp;
2311 return offset & -4096;
2312 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002313}
2314
Jesse Barnes46f297f2014-03-07 08:57:48 -08002315int intel_format_to_fourcc(int format)
2316{
2317 switch (format) {
2318 case DISPPLANE_8BPP:
2319 return DRM_FORMAT_C8;
2320 case DISPPLANE_BGRX555:
2321 return DRM_FORMAT_XRGB1555;
2322 case DISPPLANE_BGRX565:
2323 return DRM_FORMAT_RGB565;
2324 default:
2325 case DISPPLANE_BGRX888:
2326 return DRM_FORMAT_XRGB8888;
2327 case DISPPLANE_RGBX888:
2328 return DRM_FORMAT_XBGR8888;
2329 case DISPPLANE_BGRX101010:
2330 return DRM_FORMAT_XRGB2101010;
2331 case DISPPLANE_RGBX101010:
2332 return DRM_FORMAT_XBGR2101010;
2333 }
2334}
2335
Jesse Barnes484b41d2014-03-07 08:57:55 -08002336static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
Jesse Barnes46f297f2014-03-07 08:57:48 -08002337 struct intel_plane_config *plane_config)
2338{
2339 struct drm_device *dev = crtc->base.dev;
2340 struct drm_i915_gem_object *obj = NULL;
2341 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342 u32 base = plane_config->base;
2343
Chris Wilsonff2652e2014-03-10 08:07:02 +00002344 if (plane_config->size == 0)
2345 return false;
2346
Jesse Barnes46f297f2014-03-07 08:57:48 -08002347 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348 plane_config->size);
2349 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002350 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002351
2352 if (plane_config->tiled) {
2353 obj->tiling_mode = I915_TILING_X;
Dave Airlie66e514c2014-04-03 07:51:54 +10002354 obj->stride = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002355 }
2356
Dave Airlie66e514c2014-04-03 07:51:54 +10002357 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358 mode_cmd.width = crtc->base.primary->fb->width;
2359 mode_cmd.height = crtc->base.primary->fb->height;
2360 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002361
2362 mutex_lock(&dev->struct_mutex);
2363
Dave Airlie66e514c2014-04-03 07:51:54 +10002364 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002365 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002366 DRM_DEBUG_KMS("intel fb init failed\n");
2367 goto out_unref_obj;
2368 }
2369
Daniel Vettera071fa02014-06-18 23:28:09 +02002370 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002371 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002372
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002375
2376out_unref_obj:
2377 drm_gem_object_unreference(&obj->base);
2378 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002379 return false;
2380}
2381
2382static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383 struct intel_plane_config *plane_config)
2384{
2385 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002386 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002387 struct drm_crtc *c;
2388 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002389 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002390
Dave Airlie66e514c2014-04-03 07:51:54 +10002391 if (!intel_crtc->base.primary->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002392 return;
2393
2394 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395 return;
2396
Dave Airlie66e514c2014-04-03 07:51:54 +10002397 kfree(intel_crtc->base.primary->fb);
2398 intel_crtc->base.primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002399
2400 /*
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2403 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002404 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002405 i = to_intel_crtc(c);
2406
2407 if (c == &intel_crtc->base)
2408 continue;
2409
Matt Roper2ff8fde2014-07-08 07:50:07 -07002410 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002411 continue;
2412
Matt Roper2ff8fde2014-07-08 07:50:07 -07002413 obj = intel_fb_obj(c->primary->fb);
2414 if (obj == NULL)
2415 continue;
2416
2417 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002418 if (obj->tiling_mode != I915_TILING_NONE)
2419 dev_priv->preserve_bios_swizzle = true;
2420
Dave Airlie66e514c2014-04-03 07:51:54 +10002421 drm_framebuffer_reference(c->primary->fb);
2422 intel_crtc->base.primary->fb = c->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002423 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002424 break;
2425 }
2426 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002427}
2428
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002429static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430 struct drm_framebuffer *fb,
2431 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002432{
2433 struct drm_device *dev = crtc->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002436 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002437 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002438 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002439 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002440 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302441 int pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002442
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002443 if (!intel_crtc->primary_enabled) {
2444 I915_WRITE(reg, 0);
2445 if (INTEL_INFO(dev)->gen >= 4)
2446 I915_WRITE(DSPSURF(plane), 0);
2447 else
2448 I915_WRITE(DSPADDR(plane), 0);
2449 POSTING_READ(reg);
2450 return;
2451 }
2452
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002453 obj = intel_fb_obj(fb);
2454 if (WARN_ON(obj == NULL))
2455 return;
2456
2457 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002459 dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002461 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002462
2463 if (INTEL_INFO(dev)->gen < 4) {
2464 if (intel_crtc->pipe == PIPE_B)
2465 dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2469 */
2470 I915_WRITE(DSPSIZE(plane),
2471 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472 (intel_crtc->config.pipe_src_w - 1));
2473 I915_WRITE(DSPPOS(plane), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +03002474 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475 I915_WRITE(PRIMSIZE(plane),
2476 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477 (intel_crtc->config.pipe_src_w - 1));
2478 I915_WRITE(PRIMPOS(plane), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane), 0);
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002480 }
2481
Ville Syrjälä57779d02012-10-31 17:50:14 +02002482 switch (fb->pixel_format) {
2483 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002484 dspcntr |= DISPPLANE_8BPP;
2485 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002486 case DRM_FORMAT_XRGB1555:
2487 case DRM_FORMAT_ARGB1555:
2488 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002489 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002490 case DRM_FORMAT_RGB565:
2491 dspcntr |= DISPPLANE_BGRX565;
2492 break;
2493 case DRM_FORMAT_XRGB8888:
2494 case DRM_FORMAT_ARGB8888:
2495 dspcntr |= DISPPLANE_BGRX888;
2496 break;
2497 case DRM_FORMAT_XBGR8888:
2498 case DRM_FORMAT_ABGR8888:
2499 dspcntr |= DISPPLANE_RGBX888;
2500 break;
2501 case DRM_FORMAT_XRGB2101010:
2502 case DRM_FORMAT_ARGB2101010:
2503 dspcntr |= DISPPLANE_BGRX101010;
2504 break;
2505 case DRM_FORMAT_XBGR2101010:
2506 case DRM_FORMAT_ABGR2101010:
2507 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002508 break;
2509 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002510 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002511 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002512
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002513 if (INTEL_INFO(dev)->gen >= 4 &&
2514 obj->tiling_mode != I915_TILING_NONE)
2515 dspcntr |= DISPPLANE_TILED;
Jesse Barnes81255562010-08-02 12:07:50 -07002516
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002517 if (IS_G4X(dev))
2518 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
Ville Syrjäläb98971272014-08-27 16:51:22 +03002520 linear_offset = y * fb->pitches[0] + x * pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002521
Daniel Vetterc2c75132012-07-05 12:17:30 +02002522 if (INTEL_INFO(dev)->gen >= 4) {
2523 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002524 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002525 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002526 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002527 linear_offset -= intel_crtc->dspaddr_offset;
2528 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002529 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002530 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002531
Sonika Jindal48404c12014-08-22 14:06:04 +05302532 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535 x += (intel_crtc->config.pipe_src_w - 1);
2536 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2540 linear_offset +=
2541 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543 }
2544
2545 I915_WRITE(reg, dspcntr);
2546
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002550 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002551 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002554 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002555 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002556 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002557 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002558 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002559}
2560
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002561static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562 struct drm_framebuffer *fb,
2563 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002564{
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002568 struct drm_i915_gem_object *obj;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002569 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002570 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002571 u32 dspcntr;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002572 u32 reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302573 int pixel_size;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002574
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002575 if (!intel_crtc->primary_enabled) {
2576 I915_WRITE(reg, 0);
2577 I915_WRITE(DSPSURF(plane), 0);
2578 POSTING_READ(reg);
2579 return;
2580 }
2581
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002582 obj = intel_fb_obj(fb);
2583 if (WARN_ON(obj == NULL))
2584 return;
2585
2586 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002588 dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002590 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002591
2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
Ville Syrjälä57779d02012-10-31 17:50:14 +02002595 switch (fb->pixel_format) {
2596 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002597 dspcntr |= DISPPLANE_8BPP;
2598 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002599 case DRM_FORMAT_RGB565:
2600 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002601 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002602 case DRM_FORMAT_XRGB8888:
2603 case DRM_FORMAT_ARGB8888:
2604 dspcntr |= DISPPLANE_BGRX888;
2605 break;
2606 case DRM_FORMAT_XBGR8888:
2607 case DRM_FORMAT_ABGR8888:
2608 dspcntr |= DISPPLANE_RGBX888;
2609 break;
2610 case DRM_FORMAT_XRGB2101010:
2611 case DRM_FORMAT_ARGB2101010:
2612 dspcntr |= DISPPLANE_BGRX101010;
2613 break;
2614 case DRM_FORMAT_XBGR2101010:
2615 case DRM_FORMAT_ABGR2101010:
2616 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002617 break;
2618 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002619 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002620 }
2621
2622 if (obj->tiling_mode != I915_TILING_NONE)
2623 dspcntr |= DISPPLANE_TILED;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002624
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002625 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002626 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002627
Ville Syrjäläb98971272014-08-27 16:51:22 +03002628 linear_offset = y * fb->pitches[0] + x * pixel_size;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002629 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002630 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002631 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002632 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002633 linear_offset -= intel_crtc->dspaddr_offset;
Sonika Jindal48404c12014-08-22 14:06:04 +05302634 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638 x += (intel_crtc->config.pipe_src_w - 1);
2639 y += (intel_crtc->config.pipe_src_h - 1);
2640
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2643 linear_offset +=
2644 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646 }
2647 }
2648
2649 I915_WRITE(reg, dspcntr);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002650
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002654 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002655 I915_WRITE(DSPSURF(plane),
2656 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002657 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002658 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659 } else {
2660 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002663 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002664}
2665
Damien Lespiau70d21f02013-07-03 21:06:04 +01002666static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667 struct drm_framebuffer *fb,
2668 int x, int y)
2669{
2670 struct drm_device *dev = crtc->dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673 struct intel_framebuffer *intel_fb;
2674 struct drm_i915_gem_object *obj;
2675 int pipe = intel_crtc->pipe;
2676 u32 plane_ctl, stride;
2677
2678 if (!intel_crtc->primary_enabled) {
2679 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe, 0));
2682 return;
2683 }
2684
2685 plane_ctl = PLANE_CTL_ENABLE |
2686 PLANE_CTL_PIPE_GAMMA_ENABLE |
2687 PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689 switch (fb->pixel_format) {
2690 case DRM_FORMAT_RGB565:
2691 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692 break;
2693 case DRM_FORMAT_XRGB8888:
2694 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695 break;
2696 case DRM_FORMAT_XBGR8888:
2697 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699 break;
2700 case DRM_FORMAT_XRGB2101010:
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702 break;
2703 case DRM_FORMAT_XBGR2101010:
2704 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706 break;
2707 default:
2708 BUG();
2709 }
2710
2711 intel_fb = to_intel_framebuffer(fb);
2712 obj = intel_fb->obj;
2713
2714 /*
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2717 */
2718 switch (obj->tiling_mode) {
2719 case I915_TILING_NONE:
2720 stride = fb->pitches[0] >> 6;
2721 break;
2722 case I915_TILING_X:
2723 plane_ctl |= PLANE_CTL_TILED_X;
2724 stride = fb->pitches[0] >> 9;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
Sonika Jindal1447dde2014-10-04 10:53:31 +01002731 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732 plane_ctl |= PLANE_CTL_ROTATE_180;
Damien Lespiau70d21f02013-07-03 21:06:04 +01002733
2734 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj),
2738 x, y, fb->width, fb->height,
2739 fb->pitches[0]);
2740
2741 I915_WRITE(PLANE_POS(pipe, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743 I915_WRITE(PLANE_SIZE(pipe, 0),
2744 (intel_crtc->config.pipe_src_h - 1) << 16 |
2745 (intel_crtc->config.pipe_src_w - 1));
2746 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749 POSTING_READ(PLANE_SURF(pipe, 0));
2750}
2751
Jesse Barnes17638cd2011-06-24 12:19:23 -07002752/* Assume fb object is pinned & idle & fenced and just update base pointers */
2753static int
2754intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755 int x, int y, enum mode_set_atomic state)
2756{
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002759
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002760 if (dev_priv->display.disable_fbc)
2761 dev_priv->display.disable_fbc(dev);
Jesse Barnes81255562010-08-02 12:07:50 -07002762
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002763 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07002766}
2767
Ville Syrjälä96a02912013-02-18 19:08:49 +02002768void intel_display_handle_reset(struct drm_device *dev)
2769{
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct drm_crtc *crtc;
2772
2773 /*
2774 * Flips in the rings have been nuked by the reset,
2775 * so complete all pending flips so that user space
2776 * will get its events and not get stuck.
2777 *
2778 * Also update the base address of all primary
2779 * planes to the the last fb to make sure we're
2780 * showing the correct fb after a reset.
2781 *
2782 * Need to make two loops over the crtcs so that we
2783 * don't try to grab a crtc mutex before the
2784 * pending_flip_queue really got woken up.
2785 */
2786
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002787 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 enum plane plane = intel_crtc->plane;
2790
2791 intel_prepare_page_flip(dev, plane);
2792 intel_finish_page_flip_plane(dev, plane);
2793 }
2794
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002795 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02002796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
Rob Clark51fd3712013-11-19 12:10:12 -05002798 drm_modeset_lock(&crtc->mutex, NULL);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002799 /*
2800 * FIXME: Once we have proper support for primary planes (and
2801 * disabling them without disabling the entire crtc) allow again
Dave Airlie66e514c2014-04-03 07:51:54 +10002802 * a NULL crtc->primary->fb.
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002803 */
Matt Roperf4510a22014-04-01 15:22:40 -07002804 if (intel_crtc->active && crtc->primary->fb)
Matt Roper262ca2b2014-03-18 17:22:55 -07002805 dev_priv->display.update_primary_plane(crtc,
Dave Airlie66e514c2014-04-03 07:51:54 +10002806 crtc->primary->fb,
Matt Roper262ca2b2014-03-18 17:22:55 -07002807 crtc->x,
2808 crtc->y);
Rob Clark51fd3712013-11-19 12:10:12 -05002809 drm_modeset_unlock(&crtc->mutex);
Ville Syrjälä96a02912013-02-18 19:08:49 +02002810 }
2811}
2812
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002813static int
Chris Wilson14667a42012-04-03 17:58:35 +01002814intel_finish_fb(struct drm_framebuffer *old_fb)
2815{
Matt Roper2ff8fde2014-07-08 07:50:07 -07002816 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
Chris Wilson14667a42012-04-03 17:58:35 +01002817 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818 bool was_interruptible = dev_priv->mm.interruptible;
2819 int ret;
2820
Chris Wilson14667a42012-04-03 17:58:35 +01002821 /* Big Hammer, we also need to ensure that any pending
2822 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823 * current scanout is retired before unpinning the old
2824 * framebuffer.
2825 *
2826 * This should only fail upon a hung GPU, in which case we
2827 * can safely continue.
2828 */
2829 dev_priv->mm.interruptible = false;
2830 ret = i915_gem_object_finish_gpu(obj);
2831 dev_priv->mm.interruptible = was_interruptible;
2832
2833 return ret;
2834}
2835
Chris Wilson7d5e3792014-03-04 13:15:08 +00002836static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002841 bool pending;
2842
2843 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845 return false;
2846
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02002847 spin_lock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002848 pending = to_intel_crtc(crtc)->unpin_work != NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02002849 spin_unlock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00002850
2851 return pending;
2852}
2853
Gustavo Padovane30e8f72014-09-10 12:04:17 -03002854static void intel_update_pipe_size(struct intel_crtc *crtc)
2855{
2856 struct drm_device *dev = crtc->base.dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858 const struct drm_display_mode *adjusted_mode;
2859
2860 if (!i915.fastboot)
2861 return;
2862
2863 /*
2864 * Update pipe size and adjust fitter if needed: the reason for this is
2865 * that in compute_mode_changes we check the native mode (not the pfit
2866 * mode) to see if we can flip rather than do a full mode set. In the
2867 * fastboot case, we'll flip, but if we don't update the pipesrc and
2868 * pfit state, we'll end up with a big fb scanned out into the wrong
2869 * sized surface.
2870 *
2871 * To fix this properly, we need to hoist the checks up into
2872 * compute_mode_changes (or above), check the actual pfit state and
2873 * whether the platform allows pfit disable with pipe active, and only
2874 * then update the pipesrc and pfit state, even on the flip path.
2875 */
2876
2877 adjusted_mode = &crtc->config.adjusted_mode;
2878
2879 I915_WRITE(PIPESRC(crtc->pipe),
2880 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881 (adjusted_mode->crtc_vdisplay - 1));
2882 if (!crtc->config.pch_pfit.enabled &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002883 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Gustavo Padovane30e8f72014-09-10 12:04:17 -03002885 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888 }
2889 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891}
2892
Chris Wilson14667a42012-04-03 17:58:35 +01002893static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002894intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002895 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002896{
2897 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002898 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02002900 enum pipe pipe = intel_crtc->pipe;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002901 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002902 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002903 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002904
Chris Wilson7d5e3792014-03-04 13:15:08 +00002905 if (intel_crtc_has_pending_flip(crtc)) {
2906 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907 return -EBUSY;
2908 }
2909
Jesse Barnes79e53942008-11-07 14:24:08 -08002910 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002911 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002912 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002913 return 0;
2914 }
2915
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002916 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002917 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918 plane_name(intel_crtc->plane),
2919 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002920 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002921 }
2922
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002923 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002924 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
Daniel Vettera071fa02014-06-18 23:28:09 +02002925 if (ret == 0)
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002926 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
Daniel Vettera071fa02014-06-18 23:28:09 +02002927 INTEL_FRONTBUFFER_PRIMARY(pipe));
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002928 mutex_unlock(&dev->struct_mutex);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002929 if (ret != 0) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002930 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002931 return ret;
2932 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002933
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002934 dev_priv->display.update_primary_plane(crtc, fb, x, y);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002935
Daniel Vetterf99d7062014-06-19 16:01:59 +02002936 if (intel_crtc->active)
2937 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2938
Matt Roperf4510a22014-04-01 15:22:40 -07002939 crtc->primary->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002940 crtc->x = x;
2941 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002942
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002943 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002944 if (intel_crtc->active && old_fb != fb)
2945 intel_wait_for_vblank(dev, intel_crtc->pipe);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002946 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002947 intel_unpin_fb_obj(old_obj);
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002948 mutex_unlock(&dev->struct_mutex);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002949 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002950
Ville Syrjälä8ac36ec2014-03-11 19:37:33 +02002951 mutex_lock(&dev->struct_mutex);
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002952 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002953 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002954
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002955 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002956}
2957
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002958static void intel_fdi_normal_train(struct drm_crtc *crtc)
2959{
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
2964 u32 reg, temp;
2965
2966 /* enable normal train */
2967 reg = FDI_TX_CTL(pipe);
2968 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002969 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002970 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2971 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002972 } else {
2973 temp &= ~FDI_LINK_TRAIN_NONE;
2974 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002975 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002976 I915_WRITE(reg, temp);
2977
2978 reg = FDI_RX_CTL(pipe);
2979 temp = I915_READ(reg);
2980 if (HAS_PCH_CPT(dev)) {
2981 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2982 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2983 } else {
2984 temp &= ~FDI_LINK_TRAIN_NONE;
2985 temp |= FDI_LINK_TRAIN_NONE;
2986 }
2987 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2988
2989 /* wait one idle pattern time */
2990 POSTING_READ(reg);
2991 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002992
2993 /* IVB wants error correction enabled */
2994 if (IS_IVYBRIDGE(dev))
2995 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2996 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002997}
2998
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002999static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01003000{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003001 return crtc->base.enabled && crtc->active &&
3002 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01003003}
3004
Daniel Vetter01a415f2012-10-27 15:58:40 +02003005static void ivb_modeset_global_resources(struct drm_device *dev)
3006{
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 struct intel_crtc *pipe_B_crtc =
3009 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3010 struct intel_crtc *pipe_C_crtc =
3011 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3012 uint32_t temp;
3013
Daniel Vetter1e833f42013-02-19 22:31:57 +01003014 /*
3015 * When everything is off disable fdi C so that we could enable fdi B
3016 * with all lanes. Note that we don't care about enabled pipes without
3017 * an enabled pch encoder.
3018 */
3019 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3020 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02003021 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3022 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3023
3024 temp = I915_READ(SOUTH_CHICKEN1);
3025 temp &= ~FDI_BC_BIFURCATION_SELECT;
3026 DRM_DEBUG_KMS("disabling fdi C rx\n");
3027 I915_WRITE(SOUTH_CHICKEN1, temp);
3028 }
3029}
3030
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003031/* The FDI link training functions for ILK/Ibexpeak. */
3032static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3033{
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003038 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003039
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03003040 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003041 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003042
Adam Jacksone1a44742010-06-25 15:32:14 -04003043 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3044 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003045 reg = FDI_RX_IMR(pipe);
3046 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003047 temp &= ~FDI_RX_SYMBOL_LOCK;
3048 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003049 I915_WRITE(reg, temp);
3050 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003051 udelay(150);
3052
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003053 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003054 reg = FDI_TX_CTL(pipe);
3055 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003056 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3057 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003058 temp &= ~FDI_LINK_TRAIN_NONE;
3059 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003060 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003061
Chris Wilson5eddb702010-09-11 13:48:45 +01003062 reg = FDI_RX_CTL(pipe);
3063 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003064 temp &= ~FDI_LINK_TRAIN_NONE;
3065 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003066 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3067
3068 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003069 udelay(150);
3070
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003071 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01003072 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3073 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3074 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003075
Chris Wilson5eddb702010-09-11 13:48:45 +01003076 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003077 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003078 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003079 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3080
3081 if ((temp & FDI_RX_BIT_LOCK)) {
3082 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003083 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003084 break;
3085 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003086 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003087 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003088 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003089
3090 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003091 reg = FDI_TX_CTL(pipe);
3092 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003093 temp &= ~FDI_LINK_TRAIN_NONE;
3094 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003095 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003096
Chris Wilson5eddb702010-09-11 13:48:45 +01003097 reg = FDI_RX_CTL(pipe);
3098 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003099 temp &= ~FDI_LINK_TRAIN_NONE;
3100 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003101 I915_WRITE(reg, temp);
3102
3103 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003104 udelay(150);
3105
Chris Wilson5eddb702010-09-11 13:48:45 +01003106 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003107 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003108 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003109 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3110
3111 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003112 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003113 DRM_DEBUG_KMS("FDI train 2 done.\n");
3114 break;
3115 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003116 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003117 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003118 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003119
3120 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07003121
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003122}
3123
Akshay Joshi0206e352011-08-16 15:34:10 -04003124static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003125 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3126 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3127 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3128 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3129};
3130
3131/* The FDI link training functions for SNB/Cougarpoint. */
3132static void gen6_fdi_link_train(struct drm_crtc *crtc)
3133{
3134 struct drm_device *dev = crtc->dev;
3135 struct drm_i915_private *dev_priv = dev->dev_private;
3136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3137 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05003138 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003139
Adam Jacksone1a44742010-06-25 15:32:14 -04003140 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3141 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003142 reg = FDI_RX_IMR(pipe);
3143 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003144 temp &= ~FDI_RX_SYMBOL_LOCK;
3145 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003146 I915_WRITE(reg, temp);
3147
3148 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003149 udelay(150);
3150
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003151 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003152 reg = FDI_TX_CTL(pipe);
3153 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003154 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3155 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003156 temp &= ~FDI_LINK_TRAIN_NONE;
3157 temp |= FDI_LINK_TRAIN_PATTERN_1;
3158 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3159 /* SNB-B */
3160 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01003161 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003162
Daniel Vetterd74cf322012-10-26 10:58:13 +02003163 I915_WRITE(FDI_RX_MISC(pipe),
3164 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3165
Chris Wilson5eddb702010-09-11 13:48:45 +01003166 reg = FDI_RX_CTL(pipe);
3167 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003168 if (HAS_PCH_CPT(dev)) {
3169 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3170 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3171 } else {
3172 temp &= ~FDI_LINK_TRAIN_NONE;
3173 temp |= FDI_LINK_TRAIN_PATTERN_1;
3174 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003175 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3176
3177 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003178 udelay(150);
3179
Akshay Joshi0206e352011-08-16 15:34:10 -04003180 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003181 reg = FDI_TX_CTL(pipe);
3182 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003183 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3184 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003185 I915_WRITE(reg, temp);
3186
3187 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003188 udelay(500);
3189
Sean Paulfa37d392012-03-02 12:53:39 -05003190 for (retry = 0; retry < 5; retry++) {
3191 reg = FDI_RX_IIR(pipe);
3192 temp = I915_READ(reg);
3193 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3194 if (temp & FDI_RX_BIT_LOCK) {
3195 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3196 DRM_DEBUG_KMS("FDI train 1 done.\n");
3197 break;
3198 }
3199 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003200 }
Sean Paulfa37d392012-03-02 12:53:39 -05003201 if (retry < 5)
3202 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003203 }
3204 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003205 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003206
3207 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003208 reg = FDI_TX_CTL(pipe);
3209 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003210 temp &= ~FDI_LINK_TRAIN_NONE;
3211 temp |= FDI_LINK_TRAIN_PATTERN_2;
3212 if (IS_GEN6(dev)) {
3213 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3214 /* SNB-B */
3215 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3216 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003217 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003218
Chris Wilson5eddb702010-09-11 13:48:45 +01003219 reg = FDI_RX_CTL(pipe);
3220 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003221 if (HAS_PCH_CPT(dev)) {
3222 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3223 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3224 } else {
3225 temp &= ~FDI_LINK_TRAIN_NONE;
3226 temp |= FDI_LINK_TRAIN_PATTERN_2;
3227 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003228 I915_WRITE(reg, temp);
3229
3230 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003231 udelay(150);
3232
Akshay Joshi0206e352011-08-16 15:34:10 -04003233 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003234 reg = FDI_TX_CTL(pipe);
3235 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003236 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3237 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003238 I915_WRITE(reg, temp);
3239
3240 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003241 udelay(500);
3242
Sean Paulfa37d392012-03-02 12:53:39 -05003243 for (retry = 0; retry < 5; retry++) {
3244 reg = FDI_RX_IIR(pipe);
3245 temp = I915_READ(reg);
3246 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3247 if (temp & FDI_RX_SYMBOL_LOCK) {
3248 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3249 DRM_DEBUG_KMS("FDI train 2 done.\n");
3250 break;
3251 }
3252 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003253 }
Sean Paulfa37d392012-03-02 12:53:39 -05003254 if (retry < 5)
3255 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003256 }
3257 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003258 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003259
3260 DRM_DEBUG_KMS("FDI train done.\n");
3261}
3262
Jesse Barnes357555c2011-04-28 15:09:55 -07003263/* Manual link training for Ivy Bridge A0 parts */
3264static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003270 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003271
3272 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3273 for train result */
3274 reg = FDI_RX_IMR(pipe);
3275 temp = I915_READ(reg);
3276 temp &= ~FDI_RX_SYMBOL_LOCK;
3277 temp &= ~FDI_RX_BIT_LOCK;
3278 I915_WRITE(reg, temp);
3279
3280 POSTING_READ(reg);
3281 udelay(150);
3282
Daniel Vetter01a415f2012-10-27 15:58:40 +02003283 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3284 I915_READ(FDI_RX_IIR(pipe)));
3285
Jesse Barnes139ccd32013-08-19 11:04:55 -07003286 /* Try each vswing and preemphasis setting twice before moving on */
3287 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3288 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003289 reg = FDI_TX_CTL(pipe);
3290 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003291 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3292 temp &= ~FDI_TX_ENABLE;
3293 I915_WRITE(reg, temp);
3294
3295 reg = FDI_RX_CTL(pipe);
3296 temp = I915_READ(reg);
3297 temp &= ~FDI_LINK_TRAIN_AUTO;
3298 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3299 temp &= ~FDI_RX_ENABLE;
3300 I915_WRITE(reg, temp);
3301
3302 /* enable CPU FDI TX and PCH FDI RX */
3303 reg = FDI_TX_CTL(pipe);
3304 temp = I915_READ(reg);
3305 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3306 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3307 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003308 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003309 temp |= snb_b_fdi_train_param[j/2];
3310 temp |= FDI_COMPOSITE_SYNC;
3311 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3312
3313 I915_WRITE(FDI_RX_MISC(pipe),
3314 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3315
3316 reg = FDI_RX_CTL(pipe);
3317 temp = I915_READ(reg);
3318 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3319 temp |= FDI_COMPOSITE_SYNC;
3320 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3321
3322 POSTING_READ(reg);
3323 udelay(1); /* should be 0.5us */
3324
3325 for (i = 0; i < 4; i++) {
3326 reg = FDI_RX_IIR(pipe);
3327 temp = I915_READ(reg);
3328 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330 if (temp & FDI_RX_BIT_LOCK ||
3331 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3332 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3333 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3334 i);
3335 break;
3336 }
3337 udelay(1); /* should be 0.5us */
3338 }
3339 if (i == 4) {
3340 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3341 continue;
3342 }
3343
3344 /* Train 2 */
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
3347 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3348 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3349 I915_WRITE(reg, temp);
3350
3351 reg = FDI_RX_CTL(pipe);
3352 temp = I915_READ(reg);
3353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3354 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003355 I915_WRITE(reg, temp);
3356
3357 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003358 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003359
Jesse Barnes139ccd32013-08-19 11:04:55 -07003360 for (i = 0; i < 4; i++) {
3361 reg = FDI_RX_IIR(pipe);
3362 temp = I915_READ(reg);
3363 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003364
Jesse Barnes139ccd32013-08-19 11:04:55 -07003365 if (temp & FDI_RX_SYMBOL_LOCK ||
3366 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3367 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3368 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3369 i);
3370 goto train_done;
3371 }
3372 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003373 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003374 if (i == 4)
3375 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003376 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003377
Jesse Barnes139ccd32013-08-19 11:04:55 -07003378train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003379 DRM_DEBUG_KMS("FDI train done.\n");
3380}
3381
Daniel Vetter88cefb62012-08-12 19:27:14 +02003382static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003383{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003384 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003385 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003386 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01003387 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003388
Jesse Barnesc64e3112010-09-10 11:27:03 -07003389
Jesse Barnes0e23b992010-09-10 11:10:00 -07003390 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003391 reg = FDI_RX_CTL(pipe);
3392 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003393 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3394 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003395 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003396 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3397
3398 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003399 udelay(200);
3400
3401 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003402 temp = I915_READ(reg);
3403 I915_WRITE(reg, temp | FDI_PCDCLK);
3404
3405 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003406 udelay(200);
3407
Paulo Zanoni20749732012-11-23 15:30:38 -02003408 /* Enable CPU FDI TX PLL, always on for Ironlake */
3409 reg = FDI_TX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3412 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003413
Paulo Zanoni20749732012-11-23 15:30:38 -02003414 POSTING_READ(reg);
3415 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003416 }
3417}
3418
Daniel Vetter88cefb62012-08-12 19:27:14 +02003419static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3420{
3421 struct drm_device *dev = intel_crtc->base.dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 int pipe = intel_crtc->pipe;
3424 u32 reg, temp;
3425
3426 /* Switch from PCDclk to Rawclk */
3427 reg = FDI_RX_CTL(pipe);
3428 temp = I915_READ(reg);
3429 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3430
3431 /* Disable CPU FDI TX PLL */
3432 reg = FDI_TX_CTL(pipe);
3433 temp = I915_READ(reg);
3434 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3435
3436 POSTING_READ(reg);
3437 udelay(100);
3438
3439 reg = FDI_RX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3442
3443 /* Wait for the clocks to turn off. */
3444 POSTING_READ(reg);
3445 udelay(100);
3446}
3447
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003448static void ironlake_fdi_disable(struct drm_crtc *crtc)
3449{
3450 struct drm_device *dev = crtc->dev;
3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453 int pipe = intel_crtc->pipe;
3454 u32 reg, temp;
3455
3456 /* disable CPU FDI tx and PCH FDI rx */
3457 reg = FDI_TX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3460 POSTING_READ(reg);
3461
3462 reg = FDI_RX_CTL(pipe);
3463 temp = I915_READ(reg);
3464 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003465 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003466 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3467
3468 POSTING_READ(reg);
3469 udelay(100);
3470
3471 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003472 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003473 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003474
3475 /* still set train pattern 1 */
3476 reg = FDI_TX_CTL(pipe);
3477 temp = I915_READ(reg);
3478 temp &= ~FDI_LINK_TRAIN_NONE;
3479 temp |= FDI_LINK_TRAIN_PATTERN_1;
3480 I915_WRITE(reg, temp);
3481
3482 reg = FDI_RX_CTL(pipe);
3483 temp = I915_READ(reg);
3484 if (HAS_PCH_CPT(dev)) {
3485 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3486 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3487 } else {
3488 temp &= ~FDI_LINK_TRAIN_NONE;
3489 temp |= FDI_LINK_TRAIN_PATTERN_1;
3490 }
3491 /* BPC in FDI rx is consistent with that in PIPECONF */
3492 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003493 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003494 I915_WRITE(reg, temp);
3495
3496 POSTING_READ(reg);
3497 udelay(100);
3498}
3499
Chris Wilson5dce5b932014-01-20 10:17:36 +00003500bool intel_has_pending_fb_unpin(struct drm_device *dev)
3501{
3502 struct intel_crtc *crtc;
3503
3504 /* Note that we don't need to be called with mode_config.lock here
3505 * as our list of CRTC objects is static for the lifetime of the
3506 * device and so cannot disappear as we iterate. Similarly, we can
3507 * happily treat the predicates as racy, atomic checks as userspace
3508 * cannot claim and pin a new fb without at least acquring the
3509 * struct_mutex and so serialising with us.
3510 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003511 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003512 if (atomic_read(&crtc->unpin_work_count) == 0)
3513 continue;
3514
3515 if (crtc->unpin_work)
3516 intel_wait_for_vblank(dev, crtc->pipe);
3517
3518 return true;
3519 }
3520
3521 return false;
3522}
3523
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003524static void page_flip_completed(struct intel_crtc *intel_crtc)
3525{
3526 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3527 struct intel_unpin_work *work = intel_crtc->unpin_work;
3528
3529 /* ensure that the unpin work is consistent wrt ->pending. */
3530 smp_rmb();
3531 intel_crtc->unpin_work = NULL;
3532
3533 if (work->event)
3534 drm_send_vblank_event(intel_crtc->base.dev,
3535 intel_crtc->pipe,
3536 work->event);
3537
3538 drm_crtc_vblank_put(&intel_crtc->base);
3539
3540 wake_up_all(&dev_priv->pending_flip_queue);
3541 queue_work(dev_priv->wq, &work->work);
3542
3543 trace_i915_flip_complete(intel_crtc->plane,
3544 work->pending_flip_obj);
3545}
3546
Ville Syrjälä46a55d32014-05-21 14:04:46 +03003547void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003548{
Chris Wilson0f911282012-04-17 10:05:38 +01003549 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003550 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003551
Daniel Vetter2c10d572012-12-20 21:24:07 +01003552 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
Chris Wilson9c787942014-09-05 07:13:25 +01003553 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3554 !intel_crtc_has_pending_flip(crtc),
3555 60*HZ) == 0)) {
3556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter2c10d572012-12-20 21:24:07 +01003557
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003558 spin_lock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003559 if (intel_crtc->unpin_work) {
3560 WARN_ONCE(1, "Removing stuck page flip\n");
3561 page_flip_completed(intel_crtc);
3562 }
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003563 spin_unlock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003564 }
Chris Wilson5bb61642012-09-27 21:25:58 +01003565
Chris Wilson975d5682014-08-20 13:13:34 +01003566 if (crtc->primary->fb) {
3567 mutex_lock(&dev->struct_mutex);
3568 intel_finish_fb(crtc->primary->fb);
3569 mutex_unlock(&dev->struct_mutex);
3570 }
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003571}
3572
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003573/* Program iCLKIP clock to the desired frequency */
3574static void lpt_program_iclkip(struct drm_crtc *crtc)
3575{
3576 struct drm_device *dev = crtc->dev;
3577 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003578 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003579 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3580 u32 temp;
3581
Daniel Vetter09153002012-12-12 14:06:44 +01003582 mutex_lock(&dev_priv->dpio_lock);
3583
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003584 /* It is necessary to ungate the pixclk gate prior to programming
3585 * the divisors, and gate it back when it is done.
3586 */
3587 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3588
3589 /* Disable SSCCTL */
3590 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003591 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3592 SBI_SSCCTL_DISABLE,
3593 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003594
3595 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003596 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003597 auxdiv = 1;
3598 divsel = 0x41;
3599 phaseinc = 0x20;
3600 } else {
3601 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003602 * but the adjusted_mode->crtc_clock in in KHz. To get the
3603 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003604 * convert the virtual clock precision to KHz here for higher
3605 * precision.
3606 */
3607 u32 iclk_virtual_root_freq = 172800 * 1000;
3608 u32 iclk_pi_range = 64;
3609 u32 desired_divisor, msb_divisor_value, pi_value;
3610
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003611 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003612 msb_divisor_value = desired_divisor / iclk_pi_range;
3613 pi_value = desired_divisor % iclk_pi_range;
3614
3615 auxdiv = 0;
3616 divsel = msb_divisor_value - 2;
3617 phaseinc = pi_value;
3618 }
3619
3620 /* This should not happen with any sane values */
3621 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3622 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3624 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3625
3626 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003627 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003628 auxdiv,
3629 divsel,
3630 phasedir,
3631 phaseinc);
3632
3633 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003634 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003635 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3636 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3637 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3638 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3639 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3640 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003641 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003642
3643 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003644 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003645 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3646 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003647 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003648
3649 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003650 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003651 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003652 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003653
3654 /* Wait for initialization time */
3655 udelay(24);
3656
3657 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003658
3659 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003660}
3661
Daniel Vetter275f01b22013-05-03 11:49:47 +02003662static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3663 enum pipe pch_transcoder)
3664{
3665 struct drm_device *dev = crtc->base.dev;
3666 struct drm_i915_private *dev_priv = dev->dev_private;
3667 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3668
3669 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3670 I915_READ(HTOTAL(cpu_transcoder)));
3671 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3672 I915_READ(HBLANK(cpu_transcoder)));
3673 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3674 I915_READ(HSYNC(cpu_transcoder)));
3675
3676 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3677 I915_READ(VTOTAL(cpu_transcoder)));
3678 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3679 I915_READ(VBLANK(cpu_transcoder)));
3680 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3681 I915_READ(VSYNC(cpu_transcoder)));
3682 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3683 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3684}
3685
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003686static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3687{
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 uint32_t temp;
3690
3691 temp = I915_READ(SOUTH_CHICKEN1);
3692 if (temp & FDI_BC_BIFURCATION_SELECT)
3693 return;
3694
3695 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3696 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3697
3698 temp |= FDI_BC_BIFURCATION_SELECT;
3699 DRM_DEBUG_KMS("enabling fdi C rx\n");
3700 I915_WRITE(SOUTH_CHICKEN1, temp);
3701 POSTING_READ(SOUTH_CHICKEN1);
3702}
3703
3704static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3705{
3706 struct drm_device *dev = intel_crtc->base.dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708
3709 switch (intel_crtc->pipe) {
3710 case PIPE_A:
3711 break;
3712 case PIPE_B:
3713 if (intel_crtc->config.fdi_lanes > 2)
3714 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3715 else
3716 cpt_enable_fdi_bc_bifurcation(dev);
3717
3718 break;
3719 case PIPE_C:
3720 cpt_enable_fdi_bc_bifurcation(dev);
3721
3722 break;
3723 default:
3724 BUG();
3725 }
3726}
3727
Jesse Barnesf67a5592011-01-05 10:31:48 -08003728/*
3729 * Enable PCH resources required for PCH ports:
3730 * - PCH PLLs
3731 * - FDI training & RX/TX
3732 * - update transcoder timings
3733 * - DP transcoding bits
3734 * - transcoder
3735 */
3736static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003737{
3738 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003742 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003743
Daniel Vetterab9412b2013-05-03 11:49:46 +02003744 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003745
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003746 if (IS_IVYBRIDGE(dev))
3747 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3748
Daniel Vettercd986ab2012-10-26 10:58:12 +02003749 /* Write the TU size bits before fdi link training, so that error
3750 * detection works. */
3751 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3752 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3753
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003754 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003755 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003756
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003757 /* We need to program the right clock selection before writing the pixel
3758 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003759 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003760 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003761
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003762 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003763 temp |= TRANS_DPLL_ENABLE(pipe);
3764 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003765 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003766 temp |= sel;
3767 else
3768 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003769 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003770 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003771
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003772 /* XXX: pch pll's can be enabled any time before we enable the PCH
3773 * transcoder, and we actually should do this to not upset any PCH
3774 * transcoder that already use the clock when we share it.
3775 *
3776 * Note that enable_shared_dpll tries to do the right thing, but
3777 * get_shared_dpll unconditionally resets the pll - we need that to have
3778 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02003779 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003780
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003781 /* set transcoder timing, panel must allow it */
3782 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003783 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003784
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003785 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003786
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003787 /* For PCH DP, enable TRANS_DP_CTL */
Daniel Vetter0a888182014-11-03 14:37:38 +01003788 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003789 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003790 reg = TRANS_DP_CTL(pipe);
3791 temp = I915_READ(reg);
3792 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003793 TRANS_DP_SYNC_MASK |
3794 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003795 temp |= (TRANS_DP_OUTPUT_ENABLE |
3796 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003797 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003798
3799 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003800 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003801 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003802 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003803
3804 switch (intel_trans_dp_port_sel(crtc)) {
3805 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003806 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003807 break;
3808 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003809 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003810 break;
3811 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003812 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003813 break;
3814 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003815 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003816 }
3817
Chris Wilson5eddb702010-09-11 13:48:45 +01003818 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003819 }
3820
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003821 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003822}
3823
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003824static void lpt_pch_enable(struct drm_crtc *crtc)
3825{
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003829 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003830
Daniel Vetterab9412b2013-05-03 11:49:46 +02003831 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003832
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003833 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003834
Paulo Zanoni0540e482012-10-31 18:12:40 -02003835 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003836 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003837
Paulo Zanoni937bb612012-10-31 18:12:47 -02003838 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003839}
3840
Daniel Vetter716c2e52014-06-25 22:02:02 +03003841void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003842{
Daniel Vettere2b78262013-06-07 23:10:03 +02003843 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003844
3845 if (pll == NULL)
3846 return;
3847
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02003848 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02003849 WARN(1, "bad %s crtc mask\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003850 return;
3851 }
3852
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02003853 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3854 if (pll->config.crtc_mask == 0) {
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003855 WARN_ON(pll->on);
3856 WARN_ON(pll->active);
3857 }
3858
Daniel Vettera43f6e02013-06-07 23:10:32 +02003859 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003860}
3861
Daniel Vetter716c2e52014-06-25 22:02:02 +03003862struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003863{
Daniel Vettere2b78262013-06-07 23:10:03 +02003864 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003865 struct intel_shared_dpll *pll;
Daniel Vettere2b78262013-06-07 23:10:03 +02003866 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003867
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003868 if (HAS_PCH_IBX(dev_priv->dev)) {
3869 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003870 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003871 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003872
Daniel Vetter46edb022013-06-05 13:34:12 +02003873 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3874 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003875
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003876 WARN_ON(pll->new_config->crtc_mask);
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003877
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003878 goto found;
3879 }
3880
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003881 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3882 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003883
3884 /* Only want to check enabled timings first */
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003885 if (pll->new_config->crtc_mask == 0)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003886 continue;
3887
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003888 if (memcmp(&crtc->new_config->dpll_hw_state,
3889 &pll->new_config->hw_state,
3890 sizeof(pll->new_config->hw_state)) == 0) {
3891 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02003892 crtc->base.base.id, pll->name,
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003893 pll->new_config->crtc_mask,
3894 pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003895 goto found;
3896 }
3897 }
3898
3899 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003900 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3901 pll = &dev_priv->shared_dplls[i];
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003902 if (pll->new_config->crtc_mask == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003903 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3904 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003905 goto found;
3906 }
3907 }
3908
3909 return NULL;
3910
3911found:
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003912 if (pll->new_config->crtc_mask == 0)
3913 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
Daniel Vetterf2a69f42014-05-20 15:19:19 +02003914
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003915 crtc->new_config->shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003916 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3917 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003918
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003919 pll->new_config->crtc_mask |= 1 << crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003920
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003921 return pll;
3922}
3923
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003924/**
3925 * intel_shared_dpll_start_config - start a new PLL staged config
3926 * @dev_priv: DRM device
3927 * @clear_pipes: mask of pipes that will have their PLLs freed
3928 *
3929 * Starts a new PLL staged config, copying the current config but
3930 * releasing the references of pipes specified in clear_pipes.
3931 */
3932static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3933 unsigned clear_pipes)
3934{
3935 struct intel_shared_dpll *pll;
3936 enum intel_dpll_id i;
3937
3938 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3939 pll = &dev_priv->shared_dplls[i];
3940
3941 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3942 GFP_KERNEL);
3943 if (!pll->new_config)
3944 goto cleanup;
3945
3946 pll->new_config->crtc_mask &= ~clear_pipes;
3947 }
3948
3949 return 0;
3950
3951cleanup:
3952 while (--i >= 0) {
3953 pll = &dev_priv->shared_dplls[i];
Ander Conselvan de Oliveiraf354d732014-11-07 14:07:41 +02003954 kfree(pll->new_config);
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02003955 pll->new_config = NULL;
3956 }
3957
3958 return -ENOMEM;
3959}
3960
3961static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3962{
3963 struct intel_shared_dpll *pll;
3964 enum intel_dpll_id i;
3965
3966 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3967 pll = &dev_priv->shared_dplls[i];
3968
3969 WARN_ON(pll->new_config == &pll->config);
3970
3971 pll->config = *pll->new_config;
3972 kfree(pll->new_config);
3973 pll->new_config = NULL;
3974 }
3975}
3976
3977static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3978{
3979 struct intel_shared_dpll *pll;
3980 enum intel_dpll_id i;
3981
3982 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3983 pll = &dev_priv->shared_dplls[i];
3984
3985 WARN_ON(pll->new_config == &pll->config);
3986
3987 kfree(pll->new_config);
3988 pll->new_config = NULL;
3989 }
3990}
3991
Daniel Vettera1520312013-05-03 11:49:50 +02003992static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003993{
3994 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003995 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003996 u32 temp;
3997
3998 temp = I915_READ(dslreg);
3999 udelay(500);
4000 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07004001 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03004002 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07004003 }
4004}
4005
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004006static void skylake_pfit_enable(struct intel_crtc *crtc)
4007{
4008 struct drm_device *dev = crtc->base.dev;
4009 struct drm_i915_private *dev_priv = dev->dev_private;
4010 int pipe = crtc->pipe;
4011
4012 if (crtc->config.pch_pfit.enabled) {
4013 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4014 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4015 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4016 }
4017}
4018
Jesse Barnesb074cec2013-04-25 12:55:02 -07004019static void ironlake_pfit_enable(struct intel_crtc *crtc)
4020{
4021 struct drm_device *dev = crtc->base.dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 int pipe = crtc->pipe;
4024
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004025 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07004026 /* Force use of hard-coded filter coefficients
4027 * as some pre-programmed values are broken,
4028 * e.g. x201.
4029 */
4030 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4031 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4032 PF_PIPE_SEL_IVB(pipe));
4033 else
4034 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4035 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4036 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08004037 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004038}
4039
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004040static void intel_enable_planes(struct drm_crtc *crtc)
4041{
4042 struct drm_device *dev = crtc->dev;
4043 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07004044 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004045 struct intel_plane *intel_plane;
4046
Matt Roperaf2b6532014-04-01 15:22:32 -07004047 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4048 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004049 if (intel_plane->pipe == pipe)
4050 intel_plane_restore(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07004051 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004052}
4053
4054static void intel_disable_planes(struct drm_crtc *crtc)
4055{
4056 struct drm_device *dev = crtc->dev;
4057 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Matt Roperaf2b6532014-04-01 15:22:32 -07004058 struct drm_plane *plane;
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004059 struct intel_plane *intel_plane;
4060
Matt Roperaf2b6532014-04-01 15:22:32 -07004061 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4062 intel_plane = to_intel_plane(plane);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004063 if (intel_plane->pipe == pipe)
4064 intel_plane_disable(&intel_plane->base);
Matt Roperaf2b6532014-04-01 15:22:32 -07004065 }
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004066}
4067
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004068void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004069{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004070 struct drm_device *dev = crtc->base.dev;
4071 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03004072
4073 if (!crtc->config.ips_enabled)
4074 return;
4075
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004076 /* We can only enable IPS after we enable a plane and wait for a vblank */
4077 intel_wait_for_vblank(dev, crtc->pipe);
4078
Paulo Zanonid77e4532013-09-24 13:52:55 -03004079 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004080 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004081 mutex_lock(&dev_priv->rps.hw_lock);
4082 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4083 mutex_unlock(&dev_priv->rps.hw_lock);
4084 /* Quoting Art Runyan: "its not safe to expect any particular
4085 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08004086 * mailbox." Moreover, the mailbox may return a bogus state,
4087 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004088 */
4089 } else {
4090 I915_WRITE(IPS_CTL, IPS_ENABLE);
4091 /* The bit only becomes 1 in the next vblank, so this wait here
4092 * is essentially intel_wait_for_vblank. If we don't have this
4093 * and don't wait for vblanks until the end of crtc_enable, then
4094 * the HW state readout code will complain that the expected
4095 * IPS_CTL value is not the one we read. */
4096 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4097 DRM_ERROR("Timed out waiting for IPS enable\n");
4098 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004099}
4100
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004101void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004102{
4103 struct drm_device *dev = crtc->base.dev;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105
4106 if (!crtc->config.ips_enabled)
4107 return;
4108
4109 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004110 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004111 mutex_lock(&dev_priv->rps.hw_lock);
4112 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4113 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004114 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4115 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4116 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08004117 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004118 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08004119 POSTING_READ(IPS_CTL);
4120 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004121
4122 /* We need to wait for a vblank before we can disable the plane. */
4123 intel_wait_for_vblank(dev, crtc->pipe);
4124}
4125
4126/** Loads the palette/gamma unit for the CRTC with the prepared values */
4127static void intel_crtc_load_lut(struct drm_crtc *crtc)
4128{
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132 enum pipe pipe = intel_crtc->pipe;
4133 int palreg = PALETTE(pipe);
4134 int i;
4135 bool reenable_ips = false;
4136
4137 /* The clocks have to be on to load the palette. */
4138 if (!crtc->enabled || !intel_crtc->active)
4139 return;
4140
4141 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03004142 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
Paulo Zanonid77e4532013-09-24 13:52:55 -03004143 assert_dsi_pll_enabled(dev_priv);
4144 else
4145 assert_pll_enabled(dev_priv, pipe);
4146 }
4147
4148 /* use legacy palette for Ironlake */
Sonika Jindal7a1db492014-07-22 11:18:27 +05304149 if (!HAS_GMCH_DISPLAY(dev))
Paulo Zanonid77e4532013-09-24 13:52:55 -03004150 palreg = LGC_PALETTE(pipe);
4151
4152 /* Workaround : Do not read or write the pipe palette/gamma data while
4153 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4154 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02004155 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03004156 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4157 GAMMA_MODE_MODE_SPLIT)) {
4158 hsw_disable_ips(intel_crtc);
4159 reenable_ips = true;
4160 }
4161
4162 for (i = 0; i < 256; i++) {
4163 I915_WRITE(palreg + 4 * i,
4164 (intel_crtc->lut_r[i] << 16) |
4165 (intel_crtc->lut_g[i] << 8) |
4166 intel_crtc->lut_b[i]);
4167 }
4168
4169 if (reenable_ips)
4170 hsw_enable_ips(intel_crtc);
4171}
4172
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004173static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4174{
4175 if (!enable && intel_crtc->overlay) {
4176 struct drm_device *dev = intel_crtc->base.dev;
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178
4179 mutex_lock(&dev->struct_mutex);
4180 dev_priv->mm.interruptible = false;
4181 (void) intel_overlay_switch_off(intel_crtc->overlay);
4182 dev_priv->mm.interruptible = true;
4183 mutex_unlock(&dev->struct_mutex);
4184 }
4185
4186 /* Let userspace switch the overlay on again. In most cases userspace
4187 * has to recompute where to put it anyway.
4188 */
4189}
4190
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004191static void intel_crtc_enable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004192{
4193 struct drm_device *dev = crtc->dev;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4195 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004196
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03004197 intel_enable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004198 intel_enable_planes(crtc);
4199 intel_crtc_update_cursor(crtc, true);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004200 intel_crtc_dpms_overlay(intel_crtc, true);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004201
4202 hsw_enable_ips(intel_crtc);
4203
4204 mutex_lock(&dev->struct_mutex);
4205 intel_update_fbc(dev);
4206 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf99d7062014-06-19 16:01:59 +02004207
4208 /*
4209 * FIXME: Once we grow proper nuclear flip support out of this we need
4210 * to compute the mask of flip planes precisely. For the time being
4211 * consider this a flip from a NULL plane.
4212 */
4213 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004214}
4215
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004216static void intel_crtc_disable_planes(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004217{
4218 struct drm_device *dev = crtc->dev;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4221 int pipe = intel_crtc->pipe;
4222 int plane = intel_crtc->plane;
4223
4224 intel_crtc_wait_for_pending_flips(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004225
4226 if (dev_priv->fbc.plane == plane)
4227 intel_disable_fbc(dev);
4228
4229 hsw_disable_ips(intel_crtc);
4230
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004231 intel_crtc_dpms_overlay(intel_crtc, false);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004232 intel_crtc_update_cursor(crtc, false);
4233 intel_disable_planes(crtc);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03004234 intel_disable_primary_hw_plane(crtc->primary, crtc);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03004235
Daniel Vetterf99d7062014-06-19 16:01:59 +02004236 /*
4237 * FIXME: Once we grow proper nuclear flip support out of this we need
4238 * to compute the mask of flip planes precisely. For the time being
4239 * consider this a flip to a NULL plane.
4240 */
4241 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004242}
4243
Jesse Barnesf67a5592011-01-05 10:31:48 -08004244static void ironlake_crtc_enable(struct drm_crtc *crtc)
4245{
4246 struct drm_device *dev = crtc->dev;
4247 struct drm_i915_private *dev_priv = dev->dev_private;
4248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004249 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004250 int pipe = intel_crtc->pipe;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004251
Daniel Vetter08a48462012-07-02 11:43:47 +02004252 WARN_ON(!crtc->enabled);
4253
Jesse Barnesf67a5592011-01-05 10:31:48 -08004254 if (intel_crtc->active)
4255 return;
4256
Daniel Vetterb14b1052014-04-24 23:55:13 +02004257 if (intel_crtc->config.has_pch_encoder)
4258 intel_prepare_shared_dpll(intel_crtc);
4259
Daniel Vetter29407aa2014-04-24 23:55:08 +02004260 if (intel_crtc->config.has_dp_encoder)
4261 intel_dp_set_m_n(intel_crtc);
4262
4263 intel_set_pipe_timings(intel_crtc);
4264
4265 if (intel_crtc->config.has_pch_encoder) {
4266 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004267 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004268 }
4269
4270 ironlake_set_pipeconf(crtc);
4271
Jesse Barnesf67a5592011-01-05 10:31:48 -08004272 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004273
Daniel Vettera72e4c92014-09-30 10:56:47 +02004274 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4275 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni86642812013-04-12 17:57:57 -03004276
Daniel Vetterf6736a12013-06-05 13:34:30 +02004277 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02004278 if (encoder->pre_enable)
4279 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004280
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004281 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02004282 /* Note: FDI PLL enabling _must_ be done before we enable the
4283 * cpu pipes, hence this is separate from all the other fdi/pch
4284 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02004285 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02004286 } else {
4287 assert_fdi_tx_disabled(dev_priv, pipe);
4288 assert_fdi_rx_disabled(dev_priv, pipe);
4289 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004290
Jesse Barnesb074cec2013-04-25 12:55:02 -07004291 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004292
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02004293 /*
4294 * On ILK+ LUT must be loaded before the pipe is running but with
4295 * clocks enabled
4296 */
4297 intel_crtc_load_lut(crtc);
4298
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004299 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004300 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004301
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004302 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004303 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004304
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004305 for_each_encoder_on_crtc(dev, crtc, encoder)
4306 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004307
4308 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004309 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02004310
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004311 assert_vblank_disabled(crtc);
4312 drm_crtc_vblank_on(crtc);
4313
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004314 intel_crtc_enable_planes(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004315}
4316
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004317/* IPS only exists on ULT machines and is tied to pipe A. */
4318static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4319{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004320 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004321}
4322
Paulo Zanonie4916942013-09-20 16:21:19 -03004323/*
4324 * This implements the workaround described in the "notes" section of the mode
4325 * set sequence documentation. When going from no pipes or single pipe to
4326 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4327 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4328 */
4329static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4330{
4331 struct drm_device *dev = crtc->base.dev;
4332 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4333
4334 /* We want to get the other_active_crtc only if there's only 1 other
4335 * active crtc. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004336 for_each_intel_crtc(dev, crtc_it) {
Paulo Zanonie4916942013-09-20 16:21:19 -03004337 if (!crtc_it->active || crtc_it == crtc)
4338 continue;
4339
4340 if (other_active_crtc)
4341 return;
4342
4343 other_active_crtc = crtc_it;
4344 }
4345 if (!other_active_crtc)
4346 return;
4347
4348 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4349 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4350}
4351
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004352static void haswell_crtc_enable(struct drm_crtc *crtc)
4353{
4354 struct drm_device *dev = crtc->dev;
4355 struct drm_i915_private *dev_priv = dev->dev_private;
4356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4357 struct intel_encoder *encoder;
4358 int pipe = intel_crtc->pipe;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004359
4360 WARN_ON(!crtc->enabled);
4361
4362 if (intel_crtc->active)
4363 return;
4364
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004365 if (intel_crtc_to_shared_dpll(intel_crtc))
4366 intel_enable_shared_dpll(intel_crtc);
4367
Daniel Vetter229fca92014-04-24 23:55:09 +02004368 if (intel_crtc->config.has_dp_encoder)
4369 intel_dp_set_m_n(intel_crtc);
4370
4371 intel_set_pipe_timings(intel_crtc);
4372
Clint Taylorebb69c92014-09-30 10:30:22 -07004373 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4374 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4375 intel_crtc->config.pixel_multiplier - 1);
4376 }
4377
Daniel Vetter229fca92014-04-24 23:55:09 +02004378 if (intel_crtc->config.has_pch_encoder) {
4379 intel_cpu_transcoder_set_m_n(intel_crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07004380 &intel_crtc->config.fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02004381 }
4382
4383 haswell_set_pipeconf(crtc);
4384
4385 intel_set_pipe_csc(crtc);
4386
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004387 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004388
Daniel Vettera72e4c92014-09-30 10:56:47 +02004389 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004390 for_each_encoder_on_crtc(dev, crtc, encoder)
4391 if (encoder->pre_enable)
4392 encoder->pre_enable(encoder);
4393
Imre Deak4fe94672014-06-25 22:01:49 +03004394 if (intel_crtc->config.has_pch_encoder) {
Daniel Vettera72e4c92014-09-30 10:56:47 +02004395 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4396 true);
Imre Deak4fe94672014-06-25 22:01:49 +03004397 dev_priv->display.fdi_link_train(crtc);
4398 }
4399
Paulo Zanoni1f544382012-10-24 11:32:00 -02004400 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004401
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004402 if (IS_SKYLAKE(dev))
4403 skylake_pfit_enable(intel_crtc);
4404 else
4405 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004406
4407 /*
4408 * On ILK+ LUT must be loaded before the pipe is running but with
4409 * clocks enabled
4410 */
4411 intel_crtc_load_lut(crtc);
4412
Paulo Zanoni1f544382012-10-24 11:32:00 -02004413 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00004414 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004415
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004416 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004417 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004418
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004419 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004420 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004421
Dave Airlie0e32b392014-05-02 14:02:48 +10004422 if (intel_crtc->config.dp_encoder_is_mst)
4423 intel_ddi_set_vc_payload_alloc(crtc, true);
4424
Jani Nikula8807e552013-08-30 19:40:32 +03004425 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004426 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004427 intel_opregion_notify_encoder(encoder, true);
4428 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004429
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004430 assert_vblank_disabled(crtc);
4431 drm_crtc_vblank_on(crtc);
4432
Paulo Zanonie4916942013-09-20 16:21:19 -03004433 /* If we change the relative order between pipe/planes enabling, we need
4434 * to change the workaround. */
4435 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004436 intel_crtc_enable_planes(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004437}
4438
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004439static void skylake_pfit_disable(struct intel_crtc *crtc)
4440{
4441 struct drm_device *dev = crtc->base.dev;
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 int pipe = crtc->pipe;
4444
4445 /* To avoid upsetting the power well on haswell only disable the pfit if
4446 * it's in use. The hw state code will make sure we get this right. */
4447 if (crtc->config.pch_pfit.enabled) {
4448 I915_WRITE(PS_CTL(pipe), 0);
4449 I915_WRITE(PS_WIN_POS(pipe), 0);
4450 I915_WRITE(PS_WIN_SZ(pipe), 0);
4451 }
4452}
4453
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004454static void ironlake_pfit_disable(struct intel_crtc *crtc)
4455{
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 int pipe = crtc->pipe;
4459
4460 /* To avoid upsetting the power well on haswell only disable the pfit if
4461 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01004462 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004463 I915_WRITE(PF_CTL(pipe), 0);
4464 I915_WRITE(PF_WIN_POS(pipe), 0);
4465 I915_WRITE(PF_WIN_SZ(pipe), 0);
4466 }
4467}
4468
Jesse Barnes6be4a602010-09-10 10:26:01 -07004469static void ironlake_crtc_disable(struct drm_crtc *crtc)
4470{
4471 struct drm_device *dev = crtc->dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004474 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004475 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01004476 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004477
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004478 if (!intel_crtc->active)
4479 return;
4480
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004481 intel_crtc_disable_planes(crtc);
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004482
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004483 drm_crtc_vblank_off(crtc);
4484 assert_vblank_disabled(crtc);
4485
Daniel Vetterea9d7582012-07-10 10:42:52 +02004486 for_each_encoder_on_crtc(dev, crtc, encoder)
4487 encoder->disable(encoder);
4488
Daniel Vetterd925c592013-06-05 13:34:04 +02004489 if (intel_crtc->config.has_pch_encoder)
Daniel Vettera72e4c92014-09-30 10:56:47 +02004490 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
Daniel Vetterd925c592013-06-05 13:34:04 +02004491
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03004492 intel_disable_pipe(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004493
Daniel Vetter3f8dce32013-05-08 10:36:30 +02004494 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004495
Daniel Vetterbf49ec82012-09-06 22:15:40 +02004496 for_each_encoder_on_crtc(dev, crtc, encoder)
4497 if (encoder->post_disable)
4498 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004499
Daniel Vetterd925c592013-06-05 13:34:04 +02004500 if (intel_crtc->config.has_pch_encoder) {
4501 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004502
Daniel Vetterd925c592013-06-05 13:34:04 +02004503 ironlake_disable_pch_transcoder(dev_priv, pipe);
Daniel Vettera72e4c92014-09-30 10:56:47 +02004504 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004505
Daniel Vetterd925c592013-06-05 13:34:04 +02004506 if (HAS_PCH_CPT(dev)) {
4507 /* disable TRANS_DP_CTL */
4508 reg = TRANS_DP_CTL(pipe);
4509 temp = I915_READ(reg);
4510 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4511 TRANS_DP_PORT_SEL_MASK);
4512 temp |= TRANS_DP_PORT_SEL_NONE;
4513 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004514
Daniel Vetterd925c592013-06-05 13:34:04 +02004515 /* disable DPLL_SEL */
4516 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004517 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02004518 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004519 }
Daniel Vetterd925c592013-06-05 13:34:04 +02004520
4521 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004522 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02004523
4524 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004525 }
4526
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004527 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004528 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004529
4530 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01004531 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01004532 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004533}
4534
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004535static void haswell_crtc_disable(struct drm_crtc *crtc)
4536{
4537 struct drm_device *dev = crtc->dev;
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4540 struct intel_encoder *encoder;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004541 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004542
4543 if (!intel_crtc->active)
4544 return;
4545
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004546 intel_crtc_disable_planes(crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03004547
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03004548 drm_crtc_vblank_off(crtc);
4549 assert_vblank_disabled(crtc);
4550
Jani Nikula8807e552013-08-30 19:40:32 +03004551 for_each_encoder_on_crtc(dev, crtc, encoder) {
4552 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004553 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03004554 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004555
Paulo Zanoni86642812013-04-12 17:57:57 -03004556 if (intel_crtc->config.has_pch_encoder)
Daniel Vettera72e4c92014-09-30 10:56:47 +02004557 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4558 false);
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03004559 intel_disable_pipe(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004560
Ville Syrjäläa4bf2142014-08-18 21:27:34 +03004561 if (intel_crtc->config.dp_encoder_is_mst)
4562 intel_ddi_set_vc_payload_alloc(crtc, false);
4563
Paulo Zanoniad80a812012-10-24 16:06:19 -02004564 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004565
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004566 if (IS_SKYLAKE(dev))
4567 skylake_pfit_disable(intel_crtc);
4568 else
4569 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004570
Paulo Zanoni1f544382012-10-24 11:32:00 -02004571 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004572
Daniel Vetter88adfff2013-03-28 10:42:01 +01004573 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02004574 lpt_disable_pch_transcoder(dev_priv);
Daniel Vettera72e4c92014-09-30 10:56:47 +02004575 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4576 true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02004577 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02004578 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004579
Imre Deak97b040a2014-06-25 22:01:50 +03004580 for_each_encoder_on_crtc(dev, crtc, encoder)
4581 if (encoder->post_disable)
4582 encoder->post_disable(encoder);
4583
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004584 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004585 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004586
4587 mutex_lock(&dev->struct_mutex);
4588 intel_update_fbc(dev);
4589 mutex_unlock(&dev->struct_mutex);
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004590
4591 if (intel_crtc_to_shared_dpll(intel_crtc))
4592 intel_disable_shared_dpll(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004593}
4594
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004595static void ironlake_crtc_off(struct drm_crtc *crtc)
4596{
4597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004598 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004599}
4600
Paulo Zanoni6441ab52012-10-05 12:05:58 -03004601
Jesse Barnes2dd24552013-04-25 12:55:01 -07004602static void i9xx_pfit_enable(struct intel_crtc *crtc)
4603{
4604 struct drm_device *dev = crtc->base.dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 struct intel_crtc_config *pipe_config = &crtc->config;
4607
Daniel Vetter328d8e82013-05-08 10:36:31 +02004608 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07004609 return;
4610
Daniel Vetterc0b03412013-05-28 12:05:54 +02004611 /*
4612 * The panel fitter should only be adjusted whilst the pipe is disabled,
4613 * according to register description and PRM.
4614 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07004615 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4616 assert_pipe_disabled(dev_priv, crtc->pipe);
4617
Jesse Barnesb074cec2013-04-25 12:55:02 -07004618 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4619 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02004620
4621 /* Border color in case we don't scale up to the full screen. Black by
4622 * default, change to something else for debugging. */
4623 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07004624}
4625
Dave Airlied05410f2014-06-05 13:22:59 +10004626static enum intel_display_power_domain port_to_power_domain(enum port port)
4627{
4628 switch (port) {
4629 case PORT_A:
4630 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4631 case PORT_B:
4632 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4633 case PORT_C:
4634 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4635 case PORT_D:
4636 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4637 default:
4638 WARN_ON_ONCE(1);
4639 return POWER_DOMAIN_PORT_OTHER;
4640 }
4641}
4642
Imre Deak77d22dc2014-03-05 16:20:52 +02004643#define for_each_power_domain(domain, mask) \
4644 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4645 if ((1 << (domain)) & (mask))
4646
Imre Deak319be8a2014-03-04 19:22:57 +02004647enum intel_display_power_domain
4648intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02004649{
Imre Deak319be8a2014-03-04 19:22:57 +02004650 struct drm_device *dev = intel_encoder->base.dev;
4651 struct intel_digital_port *intel_dig_port;
4652
4653 switch (intel_encoder->type) {
4654 case INTEL_OUTPUT_UNKNOWN:
4655 /* Only DDI platforms should ever use this output type */
4656 WARN_ON_ONCE(!HAS_DDI(dev));
4657 case INTEL_OUTPUT_DISPLAYPORT:
4658 case INTEL_OUTPUT_HDMI:
4659 case INTEL_OUTPUT_EDP:
4660 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10004661 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10004662 case INTEL_OUTPUT_DP_MST:
4663 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4664 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02004665 case INTEL_OUTPUT_ANALOG:
4666 return POWER_DOMAIN_PORT_CRT;
4667 case INTEL_OUTPUT_DSI:
4668 return POWER_DOMAIN_PORT_DSI;
4669 default:
4670 return POWER_DOMAIN_PORT_OTHER;
4671 }
4672}
4673
4674static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4675{
4676 struct drm_device *dev = crtc->dev;
4677 struct intel_encoder *intel_encoder;
4678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4679 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02004680 unsigned long mask;
4681 enum transcoder transcoder;
4682
4683 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4684
4685 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4686 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Daniel Vetterfabf6e52014-05-29 14:10:22 +02004687 if (intel_crtc->config.pch_pfit.enabled ||
4688 intel_crtc->config.pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02004689 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4690
Imre Deak319be8a2014-03-04 19:22:57 +02004691 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4692 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4693
Imre Deak77d22dc2014-03-05 16:20:52 +02004694 return mask;
4695}
4696
Imre Deak77d22dc2014-03-05 16:20:52 +02004697static void modeset_update_crtc_power_domains(struct drm_device *dev)
4698{
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4701 struct intel_crtc *crtc;
4702
4703 /*
4704 * First get all needed power domains, then put all unneeded, to avoid
4705 * any unnecessary toggling of the power wells.
4706 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004707 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004708 enum intel_display_power_domain domain;
4709
4710 if (!crtc->base.enabled)
4711 continue;
4712
Imre Deak319be8a2014-03-04 19:22:57 +02004713 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
Imre Deak77d22dc2014-03-05 16:20:52 +02004714
4715 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4716 intel_display_power_get(dev_priv, domain);
4717 }
4718
Ville Syrjälä50f6e502014-11-06 14:49:12 +02004719 if (dev_priv->display.modeset_global_resources)
4720 dev_priv->display.modeset_global_resources(dev);
4721
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004722 for_each_intel_crtc(dev, crtc) {
Imre Deak77d22dc2014-03-05 16:20:52 +02004723 enum intel_display_power_domain domain;
4724
4725 for_each_power_domain(domain, crtc->enabled_power_domains)
4726 intel_display_power_put(dev_priv, domain);
4727
4728 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4729 }
4730
4731 intel_display_set_init_power(dev_priv, false);
4732}
4733
Ville Syrjälädfcab172014-06-13 13:37:47 +03004734/* returns HPLL frequency in kHz */
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004735static int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004736{
Jesse Barnes586f49d2013-11-04 16:06:59 -08004737 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08004738
Jesse Barnes586f49d2013-11-04 16:06:59 -08004739 /* Obtain SKU information */
4740 mutex_lock(&dev_priv->dpio_lock);
4741 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4742 CCK_FUSE_HPLL_FREQ_MASK;
4743 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004744
Ville Syrjälädfcab172014-06-13 13:37:47 +03004745 return vco_freq[hpll_freq] * 1000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004746}
4747
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004748static void vlv_update_cdclk(struct drm_device *dev)
4749{
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4751
4752 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
Ville Syrjälä43dc52c2014-10-07 17:41:20 +03004753 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004754 dev_priv->vlv_cdclk_freq);
4755
4756 /*
4757 * Program the gmbus_freq based on the cdclk frequency.
4758 * BSpec erroneously claims we should aim for 4MHz, but
4759 * in fact 1MHz is the correct frequency.
4760 */
4761 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4762}
4763
Jesse Barnes30a970c2013-11-04 13:48:12 -08004764/* Adjust CDclk dividers to allow high res or save power if possible */
4765static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4766{
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 u32 val, cmd;
4769
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03004770 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02004771
Ville Syrjälädfcab172014-06-13 13:37:47 +03004772 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08004773 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03004774 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004775 cmd = 1;
4776 else
4777 cmd = 0;
4778
4779 mutex_lock(&dev_priv->rps.hw_lock);
4780 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4781 val &= ~DSPFREQGUAR_MASK;
4782 val |= (cmd << DSPFREQGUAR_SHIFT);
4783 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4784 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4785 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4786 50)) {
4787 DRM_ERROR("timed out waiting for CDclk change\n");
4788 }
4789 mutex_unlock(&dev_priv->rps.hw_lock);
4790
Ville Syrjälädfcab172014-06-13 13:37:47 +03004791 if (cdclk == 400000) {
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03004792 u32 divider;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004793
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03004794 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004795
4796 mutex_lock(&dev_priv->dpio_lock);
4797 /* adjust cdclk divider */
4798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Ville Syrjälä9cf33db2014-06-13 13:37:48 +03004799 val &= ~DISPLAY_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004800 val |= divider;
4801 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03004802
4803 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4804 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4805 50))
4806 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08004807 mutex_unlock(&dev_priv->dpio_lock);
4808 }
4809
4810 mutex_lock(&dev_priv->dpio_lock);
4811 /* adjust self-refresh exit latency value */
4812 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4813 val &= ~0x7f;
4814
4815 /*
4816 * For high bandwidth configs, we set a higher latency in the bunit
4817 * so that the core display fetch happens in time to avoid underruns.
4818 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03004819 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004820 val |= 4500 / 250; /* 4.5 usec */
4821 else
4822 val |= 3000 / 250; /* 3.0 usec */
4823 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4824 mutex_unlock(&dev_priv->dpio_lock);
4825
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +03004826 vlv_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004827}
4828
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004829static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4830{
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 u32 val, cmd;
4833
4834 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4835
4836 switch (cdclk) {
4837 case 400000:
4838 cmd = 3;
4839 break;
4840 case 333333:
4841 case 320000:
4842 cmd = 2;
4843 break;
4844 case 266667:
4845 cmd = 1;
4846 break;
4847 case 200000:
4848 cmd = 0;
4849 break;
4850 default:
4851 WARN_ON(1);
4852 return;
4853 }
4854
4855 mutex_lock(&dev_priv->rps.hw_lock);
4856 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4857 val &= ~DSPFREQGUAR_MASK_CHV;
4858 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4859 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4860 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4861 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4862 50)) {
4863 DRM_ERROR("timed out waiting for CDclk change\n");
4864 }
4865 mutex_unlock(&dev_priv->rps.hw_lock);
4866
4867 vlv_update_cdclk(dev);
4868}
4869
Jesse Barnes30a970c2013-11-04 13:48:12 -08004870static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4871 int max_pixclk)
4872{
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03004873 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004874
Ville Syrjäläd49a3402014-06-28 02:03:58 +03004875 /* FIXME: Punit isn't quite ready yet */
4876 if (IS_CHERRYVIEW(dev_priv->dev))
4877 return 400000;
4878
Jesse Barnes30a970c2013-11-04 13:48:12 -08004879 /*
4880 * Really only a few cases to deal with, as only 4 CDclks are supported:
4881 * 200MHz
4882 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004883 * 320/333MHz (depends on HPLL freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004884 * 400MHz
4885 * So we check to see whether we're above 90% of the lower bin and
4886 * adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004887 *
4888 * We seem to get an unstable or solid color picture at 200MHz.
4889 * Not sure what's wrong. For now use 200MHz only when all pipes
4890 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08004891 */
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004892 if (max_pixclk > freq_320*9/10)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004893 return 400000;
4894 else if (max_pixclk > 266667*9/10)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03004895 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004896 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03004897 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03004898 else
4899 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08004900}
4901
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004902/* compute the max pixel clock for new configuration */
4903static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004904{
4905 struct drm_device *dev = dev_priv->dev;
4906 struct intel_crtc *intel_crtc;
4907 int max_pixclk = 0;
4908
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004909 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004910 if (intel_crtc->new_enabled)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004911 max_pixclk = max(max_pixclk,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004912 intel_crtc->new_config->adjusted_mode.crtc_clock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004913 }
4914
4915 return max_pixclk;
4916}
4917
4918static void valleyview_modeset_global_pipes(struct drm_device *dev,
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004919 unsigned *prepare_pipes)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004920{
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct intel_crtc *intel_crtc;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004923 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004924
Imre Deakd60c4472014-03-27 17:45:10 +02004925 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4926 dev_priv->vlv_cdclk_freq)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004927 return;
4928
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004929 /* disable/enable all currently active pipes while we change cdclk */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01004930 for_each_intel_crtc(dev, intel_crtc)
Jesse Barnes30a970c2013-11-04 13:48:12 -08004931 if (intel_crtc->base.enabled)
4932 *prepare_pipes |= (1 << intel_crtc->pipe);
4933}
4934
4935static void valleyview_modeset_global_resources(struct drm_device *dev)
4936{
4937 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +02004938 int max_pixclk = intel_mode_max_pixclk(dev_priv);
Jesse Barnes30a970c2013-11-04 13:48:12 -08004939 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4940
Ville Syrjälä383c5a62014-06-28 02:03:57 +03004941 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4942 if (IS_CHERRYVIEW(dev))
4943 cherryview_set_cdclk(dev, req_cdclk);
4944 else
4945 valleyview_set_cdclk(dev, req_cdclk);
4946 }
Jesse Barnes30a970c2013-11-04 13:48:12 -08004947}
4948
Jesse Barnes89b667f2013-04-18 14:51:36 -07004949static void valleyview_crtc_enable(struct drm_crtc *crtc)
4950{
4951 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02004952 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4954 struct intel_encoder *encoder;
4955 int pipe = intel_crtc->pipe;
Jani Nikula23538ef2013-08-27 15:12:22 +03004956 bool is_dsi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004957
4958 WARN_ON(!crtc->enabled);
4959
4960 if (intel_crtc->active)
4961 return;
4962
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03004963 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
Shobhit Kumar8525a232014-06-25 12:20:39 +05304964
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004965 if (!is_dsi) {
4966 if (IS_CHERRYVIEW(dev))
Ville Syrjäläd288f652014-10-28 13:20:22 +02004967 chv_prepare_pll(intel_crtc, &intel_crtc->config);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004968 else
Ville Syrjäläd288f652014-10-28 13:20:22 +02004969 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03004970 }
Daniel Vetter5b18e572014-04-24 23:55:06 +02004971
4972 if (intel_crtc->config.has_dp_encoder)
4973 intel_dp_set_m_n(intel_crtc);
4974
4975 intel_set_pipe_timings(intel_crtc);
4976
Ville Syrjäläc14b0482014-10-16 20:52:34 +03004977 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979
4980 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4981 I915_WRITE(CHV_CANVAS(pipe), 0);
4982 }
4983
Daniel Vetter5b18e572014-04-24 23:55:06 +02004984 i9xx_set_pipeconf(intel_crtc);
4985
Jesse Barnes89b667f2013-04-18 14:51:36 -07004986 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004987
Daniel Vettera72e4c92014-09-30 10:56:47 +02004988 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03004989
Jesse Barnes89b667f2013-04-18 14:51:36 -07004990 for_each_encoder_on_crtc(dev, crtc, encoder)
4991 if (encoder->pre_pll_enable)
4992 encoder->pre_pll_enable(encoder);
4993
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004994 if (!is_dsi) {
4995 if (IS_CHERRYVIEW(dev))
Ville Syrjäläd288f652014-10-28 13:20:22 +02004996 chv_enable_pll(intel_crtc, &intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004997 else
Ville Syrjäläd288f652014-10-28 13:20:22 +02004998 vlv_enable_pll(intel_crtc, &intel_crtc->config);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03004999 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07005000
5001 for_each_encoder_on_crtc(dev, crtc, encoder)
5002 if (encoder->pre_enable)
5003 encoder->pre_enable(encoder);
5004
Jesse Barnes2dd24552013-04-25 12:55:01 -07005005 i9xx_pfit_enable(intel_crtc);
5006
Ville Syrjälä63cbb072013-06-04 13:48:59 +03005007 intel_crtc_load_lut(crtc);
5008
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005009 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005010 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02005011
Jani Nikula50049452013-07-30 12:20:32 +03005012 for_each_encoder_on_crtc(dev, crtc, encoder)
5013 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005014
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005015 assert_vblank_disabled(crtc);
5016 drm_crtc_vblank_on(crtc);
5017
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005018 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02005019
Ville Syrjälä56b80e12014-05-16 19:40:22 +03005020 /* Underruns don't raise interrupts, so check manually. */
Daniel Vettera72e4c92014-09-30 10:56:47 +02005021 i9xx_check_fifo_underruns(dev_priv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005022}
5023
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02005024static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5025{
5026 struct drm_device *dev = crtc->base.dev;
5027 struct drm_i915_private *dev_priv = dev->dev_private;
5028
5029 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
5030 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5031}
5032
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005033static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005034{
5035 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02005036 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08005037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005038 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005039 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08005040
Daniel Vetter08a48462012-07-02 11:43:47 +02005041 WARN_ON(!crtc->enabled);
5042
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005043 if (intel_crtc->active)
5044 return;
5045
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02005046 i9xx_set_pll_dividers(intel_crtc);
5047
Daniel Vetter5b18e572014-04-24 23:55:06 +02005048 if (intel_crtc->config.has_dp_encoder)
5049 intel_dp_set_m_n(intel_crtc);
5050
5051 intel_set_pipe_timings(intel_crtc);
5052
Daniel Vetter5b18e572014-04-24 23:55:06 +02005053 i9xx_set_pipeconf(intel_crtc);
5054
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005055 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01005056
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005057 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005058 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005059
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02005060 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02005061 if (encoder->pre_enable)
5062 encoder->pre_enable(encoder);
5063
Daniel Vetterf6736a12013-06-05 13:34:30 +02005064 i9xx_enable_pll(intel_crtc);
5065
Jesse Barnes2dd24552013-04-25 12:55:01 -07005066 i9xx_pfit_enable(intel_crtc);
5067
Ville Syrjälä63cbb072013-06-04 13:48:59 +03005068 intel_crtc_load_lut(crtc);
5069
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005070 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005071 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02005072
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02005073 for_each_encoder_on_crtc(dev, crtc, encoder)
5074 encoder->enable(encoder);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005075
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005076 assert_vblank_disabled(crtc);
5077 drm_crtc_vblank_on(crtc);
5078
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005079 intel_crtc_enable_planes(crtc);
Daniel Vetterd40d9182014-05-21 11:45:40 +02005080
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005081 /*
5082 * Gen2 reports pipe underruns whenever all planes are disabled.
5083 * So don't enable underrun reporting before at least some planes
5084 * are enabled.
5085 * FIXME: Need to fix the logic to work when we turn off all planes
5086 * but leave the pipe running.
5087 */
5088 if (IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005089 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005090
Ville Syrjälä56b80e12014-05-16 19:40:22 +03005091 /* Underruns don't raise interrupts, so check manually. */
Daniel Vettera72e4c92014-09-30 10:56:47 +02005092 i9xx_check_fifo_underruns(dev_priv);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005093}
5094
Daniel Vetter87476d62013-04-11 16:29:06 +02005095static void i9xx_pfit_disable(struct intel_crtc *crtc)
5096{
5097 struct drm_device *dev = crtc->base.dev;
5098 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02005099
5100 if (!crtc->config.gmch_pfit.control)
5101 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02005102
5103 assert_pipe_disabled(dev_priv, crtc->pipe);
5104
Daniel Vetter328d8e82013-05-08 10:36:31 +02005105 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5106 I915_READ(PFIT_CONTROL));
5107 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02005108}
5109
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005110static void i9xx_crtc_disable(struct drm_crtc *crtc)
5111{
5112 struct drm_device *dev = crtc->dev;
5113 struct drm_i915_private *dev_priv = dev->dev_private;
5114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005115 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005116 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005117
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005118 if (!intel_crtc->active)
5119 return;
5120
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005121 /*
5122 * Gen2 reports pipe underruns whenever all planes are disabled.
5123 * So diasble underrun reporting before all the planes get disabled.
5124 * FIXME: Need to fix the logic to work when we turn off all planes
5125 * but leave the pipe running.
5126 */
5127 if (IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005128 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005129
Imre Deak564ed192014-06-13 14:54:21 +03005130 /*
5131 * Vblank time updates from the shadow to live plane control register
5132 * are blocked if the memory self-refresh mode is active at that
5133 * moment. So to make sure the plane gets truly disabled, disable
5134 * first the self-refresh mode. The self-refresh enable bit in turn
5135 * will be checked/applied by the HW only at the next frame start
5136 * event which is after the vblank start event, so we need to have a
5137 * wait-for-vblank between disabling the plane and the pipe.
5138 */
5139 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä9ab04602014-05-08 19:23:14 +03005140 intel_crtc_disable_planes(crtc);
5141
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005142 /*
5143 * On gen2 planes are double buffered but the pipe isn't, so we must
5144 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03005145 * We also need to wait on all gmch platforms because of the
5146 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005147 */
Imre Deak564ed192014-06-13 14:54:21 +03005148 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03005149
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03005150 drm_crtc_vblank_off(crtc);
5151 assert_vblank_disabled(crtc);
5152
5153 for_each_encoder_on_crtc(dev, crtc, encoder)
5154 encoder->disable(encoder);
5155
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03005156 intel_disable_pipe(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02005157
Daniel Vetter87476d62013-04-11 16:29:06 +02005158 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02005159
Jesse Barnes89b667f2013-04-18 14:51:36 -07005160 for_each_encoder_on_crtc(dev, crtc, encoder)
5161 if (encoder->post_disable)
5162 encoder->post_disable(encoder);
5163
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005164 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03005165 if (IS_CHERRYVIEW(dev))
5166 chv_disable_pll(dev_priv, pipe);
5167 else if (IS_VALLEYVIEW(dev))
5168 vlv_disable_pll(dev_priv, pipe);
5169 else
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03005170 i9xx_disable_pll(intel_crtc);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03005171 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005172
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005173 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02005174 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03005175
Chris Wilsonf7abfe82010-09-13 14:19:16 +01005176 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03005177 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005178
Daniel Vetterefa96242014-04-24 23:55:02 +02005179 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01005180 intel_update_fbc(dev);
Daniel Vetterefa96242014-04-24 23:55:02 +02005181 mutex_unlock(&dev->struct_mutex);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07005182}
5183
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005184static void i9xx_crtc_off(struct drm_crtc *crtc)
5185{
5186}
5187
Daniel Vetter976f8a22012-07-08 22:34:21 +02005188static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5189 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005190{
5191 struct drm_device *dev = crtc->dev;
5192 struct drm_i915_master_private *master_priv;
5193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5194 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08005195
5196 if (!dev->primary->master)
5197 return;
5198
5199 master_priv = dev->primary->master->driver_priv;
5200 if (!master_priv->sarea_priv)
5201 return;
5202
Jesse Barnes79e53942008-11-07 14:24:08 -08005203 switch (pipe) {
5204 case 0:
5205 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5206 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5207 break;
5208 case 1:
5209 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5210 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5211 break;
5212 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005213 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005214 break;
5215 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005216}
5217
Borun Fub04c5bd2014-07-12 10:02:27 +05305218/* Master function to enable/disable CRTC and corresponding power wells */
5219void intel_crtc_control(struct drm_crtc *crtc, bool enable)
Chris Wilsoncdd59982010-09-08 16:30:16 +01005220{
Chris Wilsoncdd59982010-09-08 16:30:16 +01005221 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005222 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005224 enum intel_display_power_domain domain;
5225 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005226
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005227 if (enable) {
5228 if (!intel_crtc->active) {
Daniel Vettere1e9fb82014-06-25 22:02:04 +03005229 domains = get_crtc_power_domains(crtc);
5230 for_each_power_domain(domain, domains)
5231 intel_display_power_get(dev_priv, domain);
5232 intel_crtc->enabled_power_domains = domains;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005233
5234 dev_priv->display.crtc_enable(crtc);
5235 }
5236 } else {
5237 if (intel_crtc->active) {
5238 dev_priv->display.crtc_disable(crtc);
5239
Daniel Vettere1e9fb82014-06-25 22:02:04 +03005240 domains = intel_crtc->enabled_power_domains;
5241 for_each_power_domain(domain, domains)
5242 intel_display_power_put(dev_priv, domain);
5243 intel_crtc->enabled_power_domains = 0;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02005244 }
5245 }
Borun Fub04c5bd2014-07-12 10:02:27 +05305246}
5247
5248/**
5249 * Sets the power management mode of the pipe and plane.
5250 */
5251void intel_crtc_update_dpms(struct drm_crtc *crtc)
5252{
5253 struct drm_device *dev = crtc->dev;
5254 struct intel_encoder *intel_encoder;
5255 bool enable = false;
5256
5257 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5258 enable |= intel_encoder->connectors_active;
5259
5260 intel_crtc_control(crtc, enable);
Daniel Vetter976f8a22012-07-08 22:34:21 +02005261
5262 intel_crtc_update_sarea(crtc, enable);
5263}
5264
Daniel Vetter976f8a22012-07-08 22:34:21 +02005265static void intel_crtc_disable(struct drm_crtc *crtc)
5266{
5267 struct drm_device *dev = crtc->dev;
5268 struct drm_connector *connector;
5269 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper2ff8fde2014-07-08 07:50:07 -07005270 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
Daniel Vettera071fa02014-06-18 23:28:09 +02005271 enum pipe pipe = to_intel_crtc(crtc)->pipe;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005272
5273 /* crtc should still be enabled when we disable it. */
5274 WARN_ON(!crtc->enabled);
5275
5276 dev_priv->display.crtc_disable(crtc);
5277 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005278 dev_priv->display.off(crtc);
5279
Matt Roperf4510a22014-04-01 15:22:40 -07005280 if (crtc->primary->fb) {
Chris Wilsoncdd59982010-09-08 16:30:16 +01005281 mutex_lock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +02005282 intel_unpin_fb_obj(old_obj);
5283 i915_gem_track_fb(old_obj, NULL,
5284 INTEL_FRONTBUFFER_PRIMARY(pipe));
Chris Wilsoncdd59982010-09-08 16:30:16 +01005285 mutex_unlock(&dev->struct_mutex);
Matt Roperf4510a22014-04-01 15:22:40 -07005286 crtc->primary->fb = NULL;
Daniel Vetter976f8a22012-07-08 22:34:21 +02005287 }
5288
5289 /* Update computed state. */
5290 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5291 if (!connector->encoder || !connector->encoder->crtc)
5292 continue;
5293
5294 if (connector->encoder->crtc != crtc)
5295 continue;
5296
5297 connector->dpms = DRM_MODE_DPMS_OFF;
5298 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01005299 }
5300}
5301
Chris Wilsonea5b2132010-08-04 13:50:23 +01005302void intel_encoder_destroy(struct drm_encoder *encoder)
5303{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005304 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01005305
Chris Wilsonea5b2132010-08-04 13:50:23 +01005306 drm_encoder_cleanup(encoder);
5307 kfree(intel_encoder);
5308}
5309
Damien Lespiau92373292013-08-08 22:28:57 +01005310/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005311 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5312 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01005313static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005314{
5315 if (mode == DRM_MODE_DPMS_ON) {
5316 encoder->connectors_active = true;
5317
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005318 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005319 } else {
5320 encoder->connectors_active = false;
5321
Daniel Vetterb2cabb02012-07-01 22:42:24 +02005322 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005323 }
5324}
5325
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005326/* Cross check the actual hw state with our own modeset state tracking (and it's
5327 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02005328static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005329{
5330 if (connector->get_hw_state(connector)) {
5331 struct intel_encoder *encoder = connector->encoder;
5332 struct drm_crtc *crtc;
5333 bool encoder_enabled;
5334 enum pipe pipe;
5335
5336 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5337 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03005338 connector->base.name);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005339
Dave Airlie0e32b392014-05-02 14:02:48 +10005340 /* there is no real hw state for MST connectors */
5341 if (connector->mst_port)
5342 return;
5343
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005344 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5345 "wrong connector dpms state\n");
5346 WARN(connector->base.encoder != &encoder->base,
5347 "active connector not linked to encoder\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005348
Dave Airlie36cd7442014-05-02 13:44:18 +10005349 if (encoder) {
5350 WARN(!encoder->connectors_active,
5351 "encoder->connectors_active not set\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005352
Dave Airlie36cd7442014-05-02 13:44:18 +10005353 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5354 WARN(!encoder_enabled, "encoder not enabled\n");
5355 if (WARN_ON(!encoder->base.crtc))
5356 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005357
Dave Airlie36cd7442014-05-02 13:44:18 +10005358 crtc = encoder->base.crtc;
5359
5360 WARN(!crtc->enabled, "crtc not enabled\n");
5361 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5362 WARN(pipe != to_intel_crtc(crtc)->pipe,
5363 "encoder active on the wrong pipe\n");
5364 }
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005365 }
5366}
5367
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005368/* Even simpler default implementation, if there's really no special case to
5369 * consider. */
5370void intel_connector_dpms(struct drm_connector *connector, int mode)
5371{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005372 /* All the simple cases only support two dpms states. */
5373 if (mode != DRM_MODE_DPMS_ON)
5374 mode = DRM_MODE_DPMS_OFF;
5375
5376 if (mode == connector->dpms)
5377 return;
5378
5379 connector->dpms = mode;
5380
5381 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01005382 if (connector->encoder)
5383 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02005384
Daniel Vetterb9805142012-08-31 17:37:33 +02005385 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02005386}
5387
Daniel Vetterf0947c32012-07-02 13:10:34 +02005388/* Simple connector->get_hw_state implementation for encoders that support only
5389 * one connector and no cloning and hence the encoder state determines the state
5390 * of the connector. */
5391bool intel_connector_get_hw_state(struct intel_connector *connector)
5392{
Daniel Vetter24929352012-07-02 20:28:59 +02005393 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02005394 struct intel_encoder *encoder = connector->encoder;
5395
5396 return encoder->get_hw_state(encoder, &pipe);
5397}
5398
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005399static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5400 struct intel_crtc_config *pipe_config)
5401{
5402 struct drm_i915_private *dev_priv = dev->dev_private;
5403 struct intel_crtc *pipe_B_crtc =
5404 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5405
5406 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5407 pipe_name(pipe), pipe_config->fdi_lanes);
5408 if (pipe_config->fdi_lanes > 4) {
5409 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5410 pipe_name(pipe), pipe_config->fdi_lanes);
5411 return false;
5412 }
5413
Paulo Zanonibafb6552013-11-02 21:07:44 -07005414 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005415 if (pipe_config->fdi_lanes > 2) {
5416 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5417 pipe_config->fdi_lanes);
5418 return false;
5419 } else {
5420 return true;
5421 }
5422 }
5423
5424 if (INTEL_INFO(dev)->num_pipes == 2)
5425 return true;
5426
5427 /* Ivybridge 3 pipe is really complicated */
5428 switch (pipe) {
5429 case PIPE_A:
5430 return true;
5431 case PIPE_B:
5432 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5433 pipe_config->fdi_lanes > 2) {
5434 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5435 pipe_name(pipe), pipe_config->fdi_lanes);
5436 return false;
5437 }
5438 return true;
5439 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01005440 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005441 pipe_B_crtc->config.fdi_lanes <= 2) {
5442 if (pipe_config->fdi_lanes > 2) {
5443 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5444 pipe_name(pipe), pipe_config->fdi_lanes);
5445 return false;
5446 }
5447 } else {
5448 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5449 return false;
5450 }
5451 return true;
5452 default:
5453 BUG();
5454 }
5455}
5456
Daniel Vettere29c22c2013-02-21 00:00:16 +01005457#define RETRY 1
5458static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5459 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02005460{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005461 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005462 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02005463 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01005464 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005465
Daniel Vettere29c22c2013-02-21 00:00:16 +01005466retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02005467 /* FDI is a binary signal running at ~2.7GHz, encoding
5468 * each output octet as 10 bits. The actual frequency
5469 * is stored as a divider into a 100MHz clock, and the
5470 * mode pixel clock is stored in units of 1KHz.
5471 * Hence the bw of each lane in terms of the mode signal
5472 * is:
5473 */
5474 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5475
Damien Lespiau241bfc32013-09-25 16:45:37 +01005476 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005477
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005478 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005479 pipe_config->pipe_bpp);
5480
5481 pipe_config->fdi_lanes = lane;
5482
Daniel Vetter2bd89a02013-06-01 17:16:19 +02005483 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02005484 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005485
Daniel Vettere29c22c2013-02-21 00:00:16 +01005486 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5487 intel_crtc->pipe, pipe_config);
5488 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5489 pipe_config->pipe_bpp -= 2*3;
5490 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5491 pipe_config->pipe_bpp);
5492 needs_recompute = true;
5493 pipe_config->bw_constrained = true;
5494
5495 goto retry;
5496 }
5497
5498 if (needs_recompute)
5499 return RETRY;
5500
5501 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02005502}
5503
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005504static void hsw_compute_ips_config(struct intel_crtc *crtc,
5505 struct intel_crtc_config *pipe_config)
5506{
Jani Nikulad330a952014-01-21 11:24:25 +02005507 pipe_config->ips_enabled = i915.enable_ips &&
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03005508 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07005509 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005510}
5511
Daniel Vettera43f6e02013-06-07 23:10:32 +02005512static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01005513 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08005514{
Daniel Vettera43f6e02013-06-07 23:10:32 +02005515 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02005516 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005517 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01005518
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005519 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005520 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005521 int clock_limit =
5522 dev_priv->display.get_display_clock_speed(dev);
5523
5524 /*
5525 * Enable pixel doubling when the dot clock
5526 * is > 90% of the (display) core speed.
5527 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03005528 * GDG double wide on either pipe,
5529 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005530 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03005531 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01005532 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005533 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005534 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03005535 }
5536
Damien Lespiau241bfc32013-09-25 16:45:37 +01005537 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005538 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005539 }
Chris Wilson89749352010-09-12 18:25:19 +01005540
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005541 /*
5542 * Pipe horizontal size must be even in:
5543 * - DVO ganged mode
5544 * - LVDS dual channel mode
5545 * - Double wide pipe
5546 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005547 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03005548 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5549 pipe_config->pipe_src_w &= ~1;
5550
Damien Lespiau8693a822013-05-03 18:48:11 +01005551 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5552 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03005553 */
5554 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5555 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01005556 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03005557
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005558 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005559 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02005560 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01005561 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5562 * for lvds. */
5563 pipe_config->pipe_bpp = 8*3;
5564 }
5565
Damien Lespiauf5adf942013-06-24 18:29:34 +01005566 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02005567 hsw_compute_ips_config(crtc, pipe_config);
5568
Daniel Vetter877d48d2013-04-19 11:24:43 +02005569 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02005570 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02005571
Daniel Vettere29c22c2013-02-21 00:00:16 +01005572 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005573}
5574
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005575static int valleyview_get_display_clock_speed(struct drm_device *dev)
5576{
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005577 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005578 u32 val;
5579 int divider;
5580
Ville Syrjäläd49a3402014-06-28 02:03:58 +03005581 /* FIXME: Punit isn't quite ready yet */
5582 if (IS_CHERRYVIEW(dev))
5583 return 400000;
5584
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005585 if (dev_priv->hpll_freq == 0)
5586 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5587
Ville Syrjäläd197b7d2014-06-13 13:37:49 +03005588 mutex_lock(&dev_priv->dpio_lock);
5589 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5590 mutex_unlock(&dev_priv->dpio_lock);
5591
5592 divider = val & DISPLAY_FREQUENCY_VALUES;
5593
Ville Syrjälä7d007f42014-06-13 13:37:53 +03005594 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5595 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5596 "cdclk change in progress\n");
5597
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005598 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07005599}
5600
Jesse Barnese70236a2009-09-21 10:42:27 -07005601static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08005602{
Jesse Barnese70236a2009-09-21 10:42:27 -07005603 return 400000;
5604}
Jesse Barnes79e53942008-11-07 14:24:08 -08005605
Jesse Barnese70236a2009-09-21 10:42:27 -07005606static int i915_get_display_clock_speed(struct drm_device *dev)
5607{
5608 return 333000;
5609}
Jesse Barnes79e53942008-11-07 14:24:08 -08005610
Jesse Barnese70236a2009-09-21 10:42:27 -07005611static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5612{
5613 return 200000;
5614}
Jesse Barnes79e53942008-11-07 14:24:08 -08005615
Daniel Vetter257a7ff2013-07-26 08:35:42 +02005616static int pnv_get_display_clock_speed(struct drm_device *dev)
5617{
5618 u16 gcfgc = 0;
5619
5620 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5621
5622 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5623 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5624 return 267000;
5625 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5626 return 333000;
5627 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5628 return 444000;
5629 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5630 return 200000;
5631 default:
5632 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5633 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5634 return 133000;
5635 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5636 return 167000;
5637 }
5638}
5639
Jesse Barnese70236a2009-09-21 10:42:27 -07005640static int i915gm_get_display_clock_speed(struct drm_device *dev)
5641{
5642 u16 gcfgc = 0;
5643
5644 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5645
5646 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08005647 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07005648 else {
5649 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5650 case GC_DISPLAY_CLOCK_333_MHZ:
5651 return 333000;
5652 default:
5653 case GC_DISPLAY_CLOCK_190_200_MHZ:
5654 return 190000;
5655 }
5656 }
5657}
Jesse Barnes79e53942008-11-07 14:24:08 -08005658
Jesse Barnese70236a2009-09-21 10:42:27 -07005659static int i865_get_display_clock_speed(struct drm_device *dev)
5660{
5661 return 266000;
5662}
5663
5664static int i855_get_display_clock_speed(struct drm_device *dev)
5665{
5666 u16 hpllcc = 0;
5667 /* Assume that the hardware is in the high speed state. This
5668 * should be the default.
5669 */
5670 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5671 case GC_CLOCK_133_200:
5672 case GC_CLOCK_100_200:
5673 return 200000;
5674 case GC_CLOCK_166_250:
5675 return 250000;
5676 case GC_CLOCK_100_133:
5677 return 133000;
5678 }
5679
5680 /* Shouldn't happen */
5681 return 0;
5682}
5683
5684static int i830_get_display_clock_speed(struct drm_device *dev)
5685{
5686 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08005687}
5688
Zhenyu Wang2c072452009-06-05 15:38:42 +08005689static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005690intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005691{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005692 while (*num > DATA_LINK_M_N_MASK ||
5693 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08005694 *num >>= 1;
5695 *den >>= 1;
5696 }
5697}
5698
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005699static void compute_m_n(unsigned int m, unsigned int n,
5700 uint32_t *ret_m, uint32_t *ret_n)
5701{
5702 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5703 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5704 intel_reduce_m_n_ratio(ret_m, ret_n);
5705}
5706
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005707void
5708intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5709 int pixel_clock, int link_clock,
5710 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08005711{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005712 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03005713
5714 compute_m_n(bits_per_pixel * pixel_clock,
5715 link_clock * nlanes * 8,
5716 &m_n->gmch_m, &m_n->gmch_n);
5717
5718 compute_m_n(pixel_clock, link_clock,
5719 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005720}
5721
Chris Wilsona7615032011-01-12 17:04:08 +00005722static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5723{
Jani Nikulad330a952014-01-21 11:24:25 +02005724 if (i915.panel_use_ssc >= 0)
5725 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005726 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07005727 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00005728}
5729
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005730static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005731{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005732 struct drm_device *dev = crtc->base.dev;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005733 struct drm_i915_private *dev_priv = dev->dev_private;
5734 int refclk;
5735
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005736 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02005737 refclk = 100000;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02005738 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005739 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005740 refclk = dev_priv->vbt.lvds_ssc_freq;
5741 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005742 } else if (!IS_GEN2(dev)) {
5743 refclk = 96000;
5744 } else {
5745 refclk = 48000;
5746 }
5747
5748 return refclk;
5749}
5750
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005751static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005752{
Daniel Vetter7df00d72013-05-21 21:54:55 +02005753 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005754}
Daniel Vetterf47709a2013-03-28 10:42:02 +01005755
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005756static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5757{
5758 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005759}
5760
Daniel Vetterf47709a2013-03-28 10:42:02 +01005761static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08005762 intel_clock_t *reduced_clock)
5763{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005764 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005765 u32 fp, fp2 = 0;
5766
5767 if (IS_PINEVIEW(dev)) {
Bob Paauwee1f234b2014-11-11 09:29:18 -08005768 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005769 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005770 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005771 } else {
Bob Paauwee1f234b2014-11-11 09:29:18 -08005772 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005773 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005774 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08005775 }
5776
Bob Paauwee1f234b2014-11-11 09:29:18 -08005777 crtc->new_config->dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005778
Daniel Vetterf47709a2013-03-28 10:42:02 +01005779 crtc->lowfreq_avail = false;
Bob Paauwee1f234b2014-11-11 09:29:18 -08005780 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Jani Nikulad330a952014-01-21 11:24:25 +02005781 reduced_clock && i915.powersave) {
Bob Paauwee1f234b2014-11-11 09:29:18 -08005782 crtc->new_config->dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005783 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005784 } else {
Bob Paauwee1f234b2014-11-11 09:29:18 -08005785 crtc->new_config->dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005786 }
5787}
5788
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005789static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5790 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005791{
5792 u32 reg_val;
5793
5794 /*
5795 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5796 * and set it to a reasonable value instead.
5797 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005798 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005799 reg_val &= 0xffffff00;
5800 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005801 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005802
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005803 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005804 reg_val &= 0x8cffffff;
5805 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005806 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005807
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005808 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005809 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005810 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005811
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005812 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005813 reg_val &= 0x00ffffff;
5814 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005815 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005816}
5817
Daniel Vetterb5518422013-05-03 11:49:48 +02005818static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5819 struct intel_link_m_n *m_n)
5820{
5821 struct drm_device *dev = crtc->base.dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 int pipe = crtc->pipe;
5824
Daniel Vettere3b95f12013-05-03 11:49:49 +02005825 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5826 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5827 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5828 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005829}
5830
5831static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07005832 struct intel_link_m_n *m_n,
5833 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02005834{
5835 struct drm_device *dev = crtc->base.dev;
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 int pipe = crtc->pipe;
5838 enum transcoder transcoder = crtc->config.cpu_transcoder;
5839
5840 if (INTEL_INFO(dev)->gen >= 5) {
5841 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5842 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5843 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5844 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07005845 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5846 * for gen < 8) and if DRRS is supported (to make sure the
5847 * registers are not unnecessarily accessed).
5848 */
5849 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5850 crtc->config.has_drrs) {
5851 I915_WRITE(PIPE_DATA_M2(transcoder),
5852 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5853 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5854 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5855 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5856 }
Daniel Vetterb5518422013-05-03 11:49:48 +02005857 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02005858 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5859 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5860 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5861 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02005862 }
5863}
5864
Vandana Kannanf769cd22014-08-05 07:51:22 -07005865void intel_dp_set_m_n(struct intel_crtc *crtc)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005866{
5867 if (crtc->config.has_pch_encoder)
5868 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5869 else
Vandana Kannanf769cd22014-08-05 07:51:22 -07005870 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5871 &crtc->config.dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005872}
5873
Ville Syrjäläd288f652014-10-28 13:20:22 +02005874static void vlv_update_pll(struct intel_crtc *crtc,
5875 struct intel_crtc_config *pipe_config)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005876{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005877 u32 dpll, dpll_md;
5878
5879 /*
5880 * Enable DPIO clock input. We should never disable the reference
5881 * clock for pipe B, since VGA hotplug / manual detection depends
5882 * on it.
5883 */
5884 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5885 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5886 /* We should never disable this, set it here for state tracking */
5887 if (crtc->pipe == PIPE_B)
5888 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5889 dpll |= DPLL_VCO_ENABLE;
Ville Syrjäläd288f652014-10-28 13:20:22 +02005890 pipe_config->dpll_hw_state.dpll = dpll;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005891
Ville Syrjäläd288f652014-10-28 13:20:22 +02005892 dpll_md = (pipe_config->pixel_multiplier - 1)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005893 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjäläd288f652014-10-28 13:20:22 +02005894 pipe_config->dpll_hw_state.dpll_md = dpll_md;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005895}
5896
Ville Syrjäläd288f652014-10-28 13:20:22 +02005897static void vlv_prepare_pll(struct intel_crtc *crtc,
5898 const struct intel_crtc_config *pipe_config)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005899{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005900 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005901 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005902 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005903 u32 mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005904 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005905 u32 coreclk, reg_val;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005906
Daniel Vetter09153002012-12-12 14:06:44 +01005907 mutex_lock(&dev_priv->dpio_lock);
5908
Ville Syrjäläd288f652014-10-28 13:20:22 +02005909 bestn = pipe_config->dpll.n;
5910 bestm1 = pipe_config->dpll.m1;
5911 bestm2 = pipe_config->dpll.m2;
5912 bestp1 = pipe_config->dpll.p1;
5913 bestp2 = pipe_config->dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005914
Jesse Barnes89b667f2013-04-18 14:51:36 -07005915 /* See eDP HDMI DPIO driver vbios notes doc */
5916
5917 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005918 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08005919 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005920
5921 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005922 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005923
5924 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005925 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005926 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005928
5929 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005930 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005931
5932 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005933 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5934 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5935 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005936 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07005937
5938 /*
5939 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5940 * but we don't support that).
5941 * Note: don't use the DAC post divider as it seems unstable.
5942 */
5943 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005945
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005946 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005948
Jesse Barnes89b667f2013-04-18 14:51:36 -07005949 /* Set HBR and RBR LPF coefficients */
Ville Syrjäläd288f652014-10-28 13:20:22 +02005950 if (pipe_config->port_clock == 162000 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005951 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5952 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03005954 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005955 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005957 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005958
Daniel Vetter0a888182014-11-03 14:37:38 +01005959 if (crtc->config.has_dp_encoder) {
Jesse Barnes89b667f2013-04-18 14:51:36 -07005960 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005961 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005963 0x0df40000);
5964 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005966 0x0df70000);
5967 } else { /* HDMI or VGA */
5968 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02005969 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005971 0x0df70000);
5972 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07005974 0x0df40000);
5975 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005976
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005977 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07005978 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03005979 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5980 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
Jesse Barnes89b667f2013-04-18 14:51:36 -07005981 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005982 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07005983
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005984 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Daniel Vetter09153002012-12-12 14:06:44 +01005985 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005986}
5987
Ville Syrjäläd288f652014-10-28 13:20:22 +02005988static void chv_update_pll(struct intel_crtc *crtc,
5989 struct intel_crtc_config *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03005990{
Ville Syrjäläd288f652014-10-28 13:20:22 +02005991 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005992 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5993 DPLL_VCO_ENABLE;
5994 if (crtc->pipe != PIPE_A)
Ville Syrjäläd288f652014-10-28 13:20:22 +02005995 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005996
Ville Syrjäläd288f652014-10-28 13:20:22 +02005997 pipe_config->dpll_hw_state.dpll_md =
5998 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03005999}
6000
Ville Syrjäläd288f652014-10-28 13:20:22 +02006001static void chv_prepare_pll(struct intel_crtc *crtc,
6002 const struct intel_crtc_config *pipe_config)
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03006003{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006004 struct drm_device *dev = crtc->base.dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 int pipe = crtc->pipe;
6007 int dpll_reg = DPLL(crtc->pipe);
6008 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Ville Syrjälä580d3812014-04-09 13:29:00 +03006009 u32 loopfilter, intcoeff;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006010 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6011 int refclk;
6012
Ville Syrjäläd288f652014-10-28 13:20:22 +02006013 bestn = pipe_config->dpll.n;
6014 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6015 bestm1 = pipe_config->dpll.m1;
6016 bestm2 = pipe_config->dpll.m2 >> 22;
6017 bestp1 = pipe_config->dpll.p1;
6018 bestp2 = pipe_config->dpll.p2;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006019
6020 /*
6021 * Enable Refclk and SSC
6022 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03006023 I915_WRITE(dpll_reg,
Ville Syrjäläd288f652014-10-28 13:20:22 +02006024 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03006025
6026 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006027
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006028 /* p1 and p2 divider */
6029 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6030 5 << DPIO_CHV_S1_DIV_SHIFT |
6031 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6032 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6033 1 << DPIO_CHV_K_DIV_SHIFT);
6034
6035 /* Feedback post-divider - m2 */
6036 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6037
6038 /* Feedback refclk divider - n and m1 */
6039 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6040 DPIO_CHV_M1_DIV_BY_2 |
6041 1 << DPIO_CHV_N_DIV_SHIFT);
6042
6043 /* M2 fraction division */
6044 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6045
6046 /* M2 fraction division enable */
6047 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6048 DPIO_CHV_FRAC_DIV_EN |
6049 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6050
6051 /* Loop filter */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006052 refclk = i9xx_get_refclk(crtc, 0);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006053 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6054 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6055 if (refclk == 100000)
6056 intcoeff = 11;
6057 else if (refclk == 38400)
6058 intcoeff = 10;
6059 else
6060 intcoeff = 9;
6061 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6062 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6063
6064 /* AFC Recal */
6065 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6066 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6067 DPIO_AFC_RECAL);
6068
6069 mutex_unlock(&dev_priv->dpio_lock);
6070}
6071
Ville Syrjäläd288f652014-10-28 13:20:22 +02006072/**
6073 * vlv_force_pll_on - forcibly enable just the PLL
6074 * @dev_priv: i915 private structure
6075 * @pipe: pipe PLL to enable
6076 * @dpll: PLL configuration
6077 *
6078 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6079 * in cases where we need the PLL enabled even when @pipe is not going to
6080 * be enabled.
6081 */
6082void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6083 const struct dpll *dpll)
6084{
6085 struct intel_crtc *crtc =
6086 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6087 struct intel_crtc_config pipe_config = {
6088 .pixel_multiplier = 1,
6089 .dpll = *dpll,
6090 };
6091
6092 if (IS_CHERRYVIEW(dev)) {
6093 chv_update_pll(crtc, &pipe_config);
6094 chv_prepare_pll(crtc, &pipe_config);
6095 chv_enable_pll(crtc, &pipe_config);
6096 } else {
6097 vlv_update_pll(crtc, &pipe_config);
6098 vlv_prepare_pll(crtc, &pipe_config);
6099 vlv_enable_pll(crtc, &pipe_config);
6100 }
6101}
6102
6103/**
6104 * vlv_force_pll_off - forcibly disable just the PLL
6105 * @dev_priv: i915 private structure
6106 * @pipe: pipe PLL to disable
6107 *
6108 * Disable the PLL for @pipe. To be used in cases where we need
6109 * the PLL enabled even when @pipe is not going to be enabled.
6110 */
6111void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6112{
6113 if (IS_CHERRYVIEW(dev))
6114 chv_disable_pll(to_i915(dev), pipe);
6115 else
6116 vlv_disable_pll(to_i915(dev), pipe);
6117}
6118
Daniel Vetterf47709a2013-03-28 10:42:02 +01006119static void i9xx_update_pll(struct intel_crtc *crtc,
6120 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006121 int num_connectors)
6122{
Daniel Vetterf47709a2013-03-28 10:42:02 +01006123 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006124 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006125 u32 dpll;
6126 bool is_sdvo;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006127 struct dpll *clock = &crtc->new_config->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006128
Daniel Vetterf47709a2013-03-28 10:42:02 +01006129 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306130
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006131 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6132 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006133
6134 dpll = DPLL_VGA_MODE_DIS;
6135
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006136 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006137 dpll |= DPLLB_MODE_LVDS;
6138 else
6139 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006140
Daniel Vetteref1b4602013-06-01 17:17:04 +02006141 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006142 dpll |= (crtc->new_config->pixel_multiplier - 1)
Daniel Vetter198a037f2013-04-19 11:14:37 +02006143 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006144 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02006145
6146 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006147 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006148
Daniel Vetter0a888182014-11-03 14:37:38 +01006149 if (crtc->new_config->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006150 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006151
6152 /* compute bitmask from p1 value */
6153 if (IS_PINEVIEW(dev))
6154 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6155 else {
6156 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6157 if (IS_G4X(dev) && reduced_clock)
6158 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6159 }
6160 switch (clock->p2) {
6161 case 5:
6162 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6163 break;
6164 case 7:
6165 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6166 break;
6167 case 10:
6168 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6169 break;
6170 case 14:
6171 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6172 break;
6173 }
6174 if (INTEL_INFO(dev)->gen >= 4)
6175 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6176
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006177 if (crtc->new_config->sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006178 dpll |= PLL_REF_INPUT_TVCLKINBC;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006179 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006180 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6181 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6182 else
6183 dpll |= PLL_REF_INPUT_DREFCLK;
6184
6185 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006186 crtc->new_config->dpll_hw_state.dpll = dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006187
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006188 if (INTEL_INFO(dev)->gen >= 4) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006189 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02006190 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006191 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006192 }
6193}
6194
Daniel Vetterf47709a2013-03-28 10:42:02 +01006195static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01006196 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006197 int num_connectors)
6198{
Daniel Vetterf47709a2013-03-28 10:42:02 +01006199 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006200 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006201 u32 dpll;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006202 struct dpll *clock = &crtc->new_config->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006203
Daniel Vetterf47709a2013-03-28 10:42:02 +01006204 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306205
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006206 dpll = DPLL_VGA_MODE_DIS;
6207
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006208 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006209 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6210 } else {
6211 if (clock->p1 == 2)
6212 dpll |= PLL_P1_DIVIDE_BY_TWO;
6213 else
6214 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6215 if (clock->p2 == 4)
6216 dpll |= PLL_P2_DIVIDE_BY_4;
6217 }
6218
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006219 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
Daniel Vetter4a33e482013-07-06 12:52:05 +02006220 dpll |= DPLL_DVO_2X_MODE;
6221
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006222 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006223 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6224 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6225 else
6226 dpll |= PLL_REF_INPUT_DREFCLK;
6227
6228 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006229 crtc->new_config->dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006230}
6231
Daniel Vetter8a654f32013-06-01 17:16:22 +02006232static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006233{
6234 struct drm_device *dev = intel_crtc->base.dev;
6235 struct drm_i915_private *dev_priv = dev->dev_private;
6236 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006237 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02006238 struct drm_display_mode *adjusted_mode =
6239 &intel_crtc->config.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02006240 uint32_t crtc_vtotal, crtc_vblank_end;
6241 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006242
6243 /* We need to be careful not to changed the adjusted mode, for otherwise
6244 * the hw state checker will get angry at the mismatch. */
6245 crtc_vtotal = adjusted_mode->crtc_vtotal;
6246 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006247
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006248 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006249 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006250 crtc_vtotal -= 1;
6251 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006252
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006253 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjälä609aeac2014-03-28 23:29:30 +02006254 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6255 else
6256 vsyncshift = adjusted_mode->crtc_hsync_start -
6257 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02006258 if (vsyncshift < 0)
6259 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006260 }
6261
6262 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006263 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006264
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006265 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006266 (adjusted_mode->crtc_hdisplay - 1) |
6267 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006268 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006269 (adjusted_mode->crtc_hblank_start - 1) |
6270 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006271 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006272 (adjusted_mode->crtc_hsync_start - 1) |
6273 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6274
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006275 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006276 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006277 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006278 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006279 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02006280 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006281 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006282 (adjusted_mode->crtc_vsync_start - 1) |
6283 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6284
Paulo Zanonib5e508d2012-10-24 11:34:43 -02006285 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6286 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6287 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6288 * bits. */
6289 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6290 (pipe == PIPE_B || pipe == PIPE_C))
6291 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6292
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006293 /* pipesrc controls the size that is scaled from, which should
6294 * always be the user's requested size.
6295 */
6296 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03006297 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6298 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03006299}
6300
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006301static void intel_get_pipe_timings(struct intel_crtc *crtc,
6302 struct intel_crtc_config *pipe_config)
6303{
6304 struct drm_device *dev = crtc->base.dev;
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6307 uint32_t tmp;
6308
6309 tmp = I915_READ(HTOTAL(cpu_transcoder));
6310 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6311 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6312 tmp = I915_READ(HBLANK(cpu_transcoder));
6313 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6314 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6315 tmp = I915_READ(HSYNC(cpu_transcoder));
6316 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6317 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6318
6319 tmp = I915_READ(VTOTAL(cpu_transcoder));
6320 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6321 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6322 tmp = I915_READ(VBLANK(cpu_transcoder));
6323 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6324 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6325 tmp = I915_READ(VSYNC(cpu_transcoder));
6326 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6327 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6328
6329 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6330 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6331 pipe_config->adjusted_mode.crtc_vtotal += 1;
6332 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6333 }
6334
6335 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03006336 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6337 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6338
6339 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6340 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006341}
6342
Daniel Vetterf6a83282014-02-11 15:28:57 -08006343void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6344 struct intel_crtc_config *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03006345{
Daniel Vetterf6a83282014-02-11 15:28:57 -08006346 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6347 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6348 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6349 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006350
Daniel Vetterf6a83282014-02-11 15:28:57 -08006351 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6352 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6353 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6354 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03006355
Daniel Vetterf6a83282014-02-11 15:28:57 -08006356 mode->flags = pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006357
Daniel Vetterf6a83282014-02-11 15:28:57 -08006358 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6359 mode->flags |= pipe_config->adjusted_mode.flags;
Jesse Barnesbabea612013-06-26 18:57:38 +03006360}
6361
Daniel Vetter84b046f2013-02-19 18:48:54 +01006362static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6363{
6364 struct drm_device *dev = intel_crtc->base.dev;
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 uint32_t pipeconf;
6367
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006368 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006369
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03006370 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6371 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6372 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
Daniel Vetter67c72a12013-09-24 11:46:14 +02006373
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006374 if (intel_crtc->config.double_wide)
6375 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01006376
Daniel Vetterff9ce462013-04-24 14:57:17 +02006377 /* only g4x and later have fancy bpc/dither controls */
6378 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02006379 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6380 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6381 pipeconf |= PIPECONF_DITHER_EN |
6382 PIPECONF_DITHER_TYPE_SP;
6383
6384 switch (intel_crtc->config.pipe_bpp) {
6385 case 18:
6386 pipeconf |= PIPECONF_6BPC;
6387 break;
6388 case 24:
6389 pipeconf |= PIPECONF_8BPC;
6390 break;
6391 case 30:
6392 pipeconf |= PIPECONF_10BPC;
6393 break;
6394 default:
6395 /* Case prevented by intel_choose_pipe_bpp_dither. */
6396 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01006397 }
6398 }
6399
6400 if (HAS_PIPE_CXSR(dev)) {
6401 if (intel_crtc->lowfreq_avail) {
6402 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6403 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6404 } else {
6405 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01006406 }
6407 }
6408
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006409 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6410 if (INTEL_INFO(dev)->gen < 4 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006411 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02006412 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6413 else
6414 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6415 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01006416 pipeconf |= PIPECONF_PROGRESSIVE;
6417
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02006418 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6419 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03006420
Daniel Vetter84b046f2013-02-19 18:48:54 +01006421 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6422 POSTING_READ(PIPECONF(intel_crtc->pipe));
6423}
6424
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +02006425static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08006426{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006427 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08006428 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholtc751ce42010-03-25 11:48:48 -07006429 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07006430 intel_clock_t clock, reduced_clock;
Daniel Vettera16af7212013-04-30 14:01:44 +02006431 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006432 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01006433 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08006434 const intel_limit_t *limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08006435
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006436 for_each_intel_encoder(dev, encoder) {
6437 if (encoder->new_crtc != crtc)
6438 continue;
6439
Chris Wilson5eddb702010-09-11 13:48:45 +01006440 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006441 case INTEL_OUTPUT_LVDS:
6442 is_lvds = true;
6443 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006444 case INTEL_OUTPUT_DSI:
6445 is_dsi = true;
6446 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02006447 default:
6448 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006449 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006450
Eric Anholtc751ce42010-03-25 11:48:48 -07006451 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08006452 }
6453
Jani Nikulaf2335332013-09-13 11:03:09 +03006454 if (is_dsi)
Daniel Vetter5b18e572014-04-24 23:55:06 +02006455 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006456
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006457 if (!crtc->new_config->clock_set) {
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006458 refclk = i9xx_get_refclk(crtc, num_connectors);
Jani Nikulaf2335332013-09-13 11:03:09 +03006459
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006460 /*
6461 * Returns a set of divisors for the desired target clock with
6462 * the given refclk, or FALSE. The returned values represent
6463 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6464 * 2) / p1 / p2.
6465 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03006466 limit = intel_limit(crtc, refclk);
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006467 ok = dev_priv->display.find_dpll(limit, crtc,
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006468 crtc->new_config->port_clock,
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006469 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03006470 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006471 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6472 return -EINVAL;
6473 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006474
Jani Nikulaf2335332013-09-13 11:03:09 +03006475 if (is_lvds && dev_priv->lvds_downclock_avail) {
6476 /*
6477 * Ensure we match the reduced clock's P to the target
6478 * clock. If the clocks don't match, we can't switch
6479 * the display clock by using the FP0/FP1. In such case
6480 * we will disable the LVDS downclock feature.
6481 */
6482 has_reduced_clock =
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006483 dev_priv->display.find_dpll(limit, crtc,
Jani Nikulaf2335332013-09-13 11:03:09 +03006484 dev_priv->lvds_downclock,
6485 refclk, &clock,
6486 &reduced_clock);
6487 }
6488 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006489 crtc->new_config->dpll.n = clock.n;
6490 crtc->new_config->dpll.m1 = clock.m1;
6491 crtc->new_config->dpll.m2 = clock.m2;
6492 crtc->new_config->dpll.p1 = clock.p1;
6493 crtc->new_config->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01006494 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006495
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006496 if (IS_GEN2(dev)) {
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006497 i8xx_update_pll(crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05306498 has_reduced_clock ? &reduced_clock : NULL,
6499 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006500 } else if (IS_CHERRYVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006501 chv_update_pll(crtc, crtc->new_config);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006502 } else if (IS_VALLEYVIEW(dev)) {
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02006503 vlv_update_pll(crtc, crtc->new_config);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006504 } else {
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03006505 i9xx_update_pll(crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02006506 has_reduced_clock ? &reduced_clock : NULL,
Robin Schroereba905b2014-05-18 02:24:50 +02006507 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03006508 }
Eric Anholtf564048e2011-03-30 13:01:02 -07006509
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02006510 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07006511}
6512
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006513static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6514 struct intel_crtc_config *pipe_config)
6515{
6516 struct drm_device *dev = crtc->base.dev;
6517 struct drm_i915_private *dev_priv = dev->dev_private;
6518 uint32_t tmp;
6519
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02006520 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6521 return;
6522
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006523 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02006524 if (!(tmp & PFIT_ENABLE))
6525 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006526
Daniel Vetter06922822013-07-11 13:35:40 +02006527 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006528 if (INTEL_INFO(dev)->gen < 4) {
6529 if (crtc->pipe != PIPE_B)
6530 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006531 } else {
6532 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6533 return;
6534 }
6535
Daniel Vetter06922822013-07-11 13:35:40 +02006536 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006537 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6538 if (INTEL_INFO(dev)->gen < 5)
6539 pipe_config->gmch_pfit.lvds_border_bits =
6540 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6541}
6542
Jesse Barnesacbec812013-09-20 11:29:32 -07006543static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6544 struct intel_crtc_config *pipe_config)
6545{
6546 struct drm_device *dev = crtc->base.dev;
6547 struct drm_i915_private *dev_priv = dev->dev_private;
6548 int pipe = pipe_config->cpu_transcoder;
6549 intel_clock_t clock;
6550 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07006551 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07006552
Shobhit Kumarf573de52014-07-30 20:32:37 +05306553 /* In case of MIPI DPLL will not even be used */
6554 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6555 return;
6556
Jesse Barnesacbec812013-09-20 11:29:32 -07006557 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08006558 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07006559 mutex_unlock(&dev_priv->dpio_lock);
6560
6561 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6562 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6563 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6564 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6565 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6566
Ville Syrjäläf6466282013-10-14 14:50:31 +03006567 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07006568
Ville Syrjäläf6466282013-10-14 14:50:31 +03006569 /* clock.dot is the fast clock */
6570 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07006571}
6572
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006573static void i9xx_get_plane_config(struct intel_crtc *crtc,
6574 struct intel_plane_config *plane_config)
6575{
6576 struct drm_device *dev = crtc->base.dev;
6577 struct drm_i915_private *dev_priv = dev->dev_private;
6578 u32 val, base, offset;
6579 int pipe = crtc->pipe, plane = crtc->plane;
6580 int fourcc, pixel_format;
6581 int aligned_height;
6582
Dave Airlie66e514c2014-04-03 07:51:54 +10006583 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6584 if (!crtc->base.primary->fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006585 DRM_DEBUG_KMS("failed to alloc fb\n");
6586 return;
6587 }
6588
6589 val = I915_READ(DSPCNTR(plane));
6590
6591 if (INTEL_INFO(dev)->gen >= 4)
6592 if (val & DISPPLANE_TILED)
6593 plane_config->tiled = true;
6594
6595 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6596 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10006597 crtc->base.primary->fb->pixel_format = fourcc;
6598 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006599 drm_format_plane_cpp(fourcc, 0) * 8;
6600
6601 if (INTEL_INFO(dev)->gen >= 4) {
6602 if (plane_config->tiled)
6603 offset = I915_READ(DSPTILEOFF(plane));
6604 else
6605 offset = I915_READ(DSPLINOFF(plane));
6606 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6607 } else {
6608 base = I915_READ(DSPADDR(plane));
6609 }
6610 plane_config->base = base;
6611
6612 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10006613 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6614 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006615
6616 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01006617 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006618
Dave Airlie66e514c2014-04-03 07:51:54 +10006619 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006620 plane_config->tiled);
6621
Fabian Frederick1267a262014-07-01 20:39:41 +02006622 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6623 aligned_height);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006624
6625 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10006626 pipe, plane, crtc->base.primary->fb->width,
6627 crtc->base.primary->fb->height,
6628 crtc->base.primary->fb->bits_per_pixel, base,
6629 crtc->base.primary->fb->pitches[0],
Jesse Barnes1ad292b2014-03-07 08:57:49 -08006630 plane_config->size);
6631
6632}
6633
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006634static void chv_crtc_clock_get(struct intel_crtc *crtc,
6635 struct intel_crtc_config *pipe_config)
6636{
6637 struct drm_device *dev = crtc->base.dev;
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 int pipe = pipe_config->cpu_transcoder;
6640 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6641 intel_clock_t clock;
6642 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6643 int refclk = 100000;
6644
6645 mutex_lock(&dev_priv->dpio_lock);
6646 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6647 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6648 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6649 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6650 mutex_unlock(&dev_priv->dpio_lock);
6651
6652 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6653 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6654 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6655 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6656 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6657
6658 chv_clock(refclk, &clock);
6659
6660 /* clock.dot is the fast clock */
6661 pipe_config->port_clock = clock.dot / 5;
6662}
6663
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006664static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6665 struct intel_crtc_config *pipe_config)
6666{
6667 struct drm_device *dev = crtc->base.dev;
6668 struct drm_i915_private *dev_priv = dev->dev_private;
6669 uint32_t tmp;
6670
Daniel Vetterf458ebb2014-09-30 10:56:39 +02006671 if (!intel_display_power_is_enabled(dev_priv,
6672 POWER_DOMAIN_PIPE(crtc->pipe)))
Imre Deakb5482bd2014-03-05 16:20:55 +02006673 return false;
6674
Daniel Vettere143a212013-07-04 12:01:15 +02006675 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006676 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006677
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006678 tmp = I915_READ(PIPECONF(crtc->pipe));
6679 if (!(tmp & PIPECONF_ENABLE))
6680 return false;
6681
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006682 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6683 switch (tmp & PIPECONF_BPC_MASK) {
6684 case PIPECONF_6BPC:
6685 pipe_config->pipe_bpp = 18;
6686 break;
6687 case PIPECONF_8BPC:
6688 pipe_config->pipe_bpp = 24;
6689 break;
6690 case PIPECONF_10BPC:
6691 pipe_config->pipe_bpp = 30;
6692 break;
6693 default:
6694 break;
6695 }
6696 }
6697
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02006698 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6699 pipe_config->limited_color_range = true;
6700
Ville Syrjälä282740f2013-09-04 18:30:03 +03006701 if (INTEL_INFO(dev)->gen < 4)
6702 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6703
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006704 intel_get_pipe_timings(crtc, pipe_config);
6705
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006706 i9xx_get_pfit_config(crtc, pipe_config);
6707
Daniel Vetter6c49f242013-06-06 12:45:25 +02006708 if (INTEL_INFO(dev)->gen >= 4) {
6709 tmp = I915_READ(DPLL_MD(crtc->pipe));
6710 pipe_config->pixel_multiplier =
6711 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6712 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006713 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02006714 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6715 tmp = I915_READ(DPLL(crtc->pipe));
6716 pipe_config->pixel_multiplier =
6717 ((tmp & SDVO_MULTIPLIER_MASK)
6718 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6719 } else {
6720 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6721 * port and will be fixed up in the encoder->get_config
6722 * function. */
6723 pipe_config->pixel_multiplier = 1;
6724 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006725 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6726 if (!IS_VALLEYVIEW(dev)) {
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03006727 /*
6728 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6729 * on 830. Filter it out here so that we don't
6730 * report errors due to that.
6731 */
6732 if (IS_I830(dev))
6733 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6734
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006735 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6736 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03006737 } else {
6738 /* Mask out read-only status bits. */
6739 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6740 DPLL_PORTC_READY_MASK |
6741 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02006742 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02006743
Ville Syrjälä70b23a92014-04-09 13:28:22 +03006744 if (IS_CHERRYVIEW(dev))
6745 chv_crtc_clock_get(crtc, pipe_config);
6746 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07006747 vlv_crtc_clock_get(crtc, pipe_config);
6748 else
6749 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03006750
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006751 return true;
6752}
6753
Paulo Zanonidde86e22012-12-01 12:04:25 -02006754static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07006755{
6756 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006757 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006758 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006759 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006760 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07006761 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07006762 bool has_ck505 = false;
6763 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006764
6765 /* We need to take the global config into account */
Damien Lespiaub2784e12014-08-05 11:29:37 +01006766 for_each_intel_encoder(dev, encoder) {
Keith Packard199e5d72011-09-22 12:01:57 -07006767 switch (encoder->type) {
6768 case INTEL_OUTPUT_LVDS:
6769 has_panel = true;
6770 has_lvds = true;
6771 break;
6772 case INTEL_OUTPUT_EDP:
6773 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03006774 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07006775 has_cpu_edp = true;
6776 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02006777 default:
6778 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006779 }
6780 }
6781
Keith Packard99eb6a02011-09-26 14:29:12 -07006782 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006783 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07006784 can_ssc = has_ck505;
6785 } else {
6786 has_ck505 = false;
6787 can_ssc = true;
6788 }
6789
Imre Deak2de69052013-05-08 13:14:04 +03006790 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6791 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006792
6793 /* Ironlake: try to setup display ref clock before DPLL
6794 * enabling. This is only under driver's control after
6795 * PCH B stepping, previous chipset stepping should be
6796 * ignoring this setting.
6797 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006798 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006799
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006800 /* As we must carefully and slowly disable/enable each source in turn,
6801 * compute the final state we want first and check if we need to
6802 * make any changes at all.
6803 */
6804 final = val;
6805 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07006806 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006807 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07006808 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006809 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6810
6811 final &= ~DREF_SSC_SOURCE_MASK;
6812 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6813 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006814
Keith Packard199e5d72011-09-22 12:01:57 -07006815 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006816 final |= DREF_SSC_SOURCE_ENABLE;
6817
6818 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6819 final |= DREF_SSC1_ENABLE;
6820
6821 if (has_cpu_edp) {
6822 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6823 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6824 else
6825 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6826 } else
6827 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6828 } else {
6829 final |= DREF_SSC_SOURCE_DISABLE;
6830 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6831 }
6832
6833 if (final == val)
6834 return;
6835
6836 /* Always enable nonspread source */
6837 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6838
6839 if (has_ck505)
6840 val |= DREF_NONSPREAD_CK505_ENABLE;
6841 else
6842 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6843
6844 if (has_panel) {
6845 val &= ~DREF_SSC_SOURCE_MASK;
6846 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006847
Keith Packard199e5d72011-09-22 12:01:57 -07006848 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07006849 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006850 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006851 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02006852 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006853 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006854
6855 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006856 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006857 POSTING_READ(PCH_DREF_CONTROL);
6858 udelay(200);
6859
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006860 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07006861
6862 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07006863 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07006864 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07006865 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006866 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02006867 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006868 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07006869 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006870 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006871
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006872 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006873 POSTING_READ(PCH_DREF_CONTROL);
6874 udelay(200);
6875 } else {
6876 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6877
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006878 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07006879
6880 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006881 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006882
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006883 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07006884 POSTING_READ(PCH_DREF_CONTROL);
6885 udelay(200);
6886
6887 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006888 val &= ~DREF_SSC_SOURCE_MASK;
6889 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006890
6891 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006892 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07006893
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006894 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006895 POSTING_READ(PCH_DREF_CONTROL);
6896 udelay(200);
6897 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07006898
6899 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07006900}
6901
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006902static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02006903{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006904 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006905
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006906 tmp = I915_READ(SOUTH_CHICKEN2);
6907 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6908 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006909
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006910 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6911 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6912 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02006913
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006914 tmp = I915_READ(SOUTH_CHICKEN2);
6915 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6916 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006917
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006918 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6919 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6920 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006921}
6922
6923/* WaMPhyProgramming:hsw */
6924static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6925{
6926 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02006927
6928 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6929 tmp &= ~(0xFF << 24);
6930 tmp |= (0x12 << 24);
6931 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6932
Paulo Zanonidde86e22012-12-01 12:04:25 -02006933 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6934 tmp |= (1 << 11);
6935 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6936
6937 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6938 tmp |= (1 << 11);
6939 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6940
Paulo Zanonidde86e22012-12-01 12:04:25 -02006941 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6942 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6943 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6944
6945 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6946 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6947 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6948
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006949 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6950 tmp &= ~(7 << 13);
6951 tmp |= (5 << 13);
6952 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006953
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006954 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6955 tmp &= ~(7 << 13);
6956 tmp |= (5 << 13);
6957 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006958
6959 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6960 tmp &= ~0xFF;
6961 tmp |= 0x1C;
6962 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6963
6964 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6965 tmp &= ~0xFF;
6966 tmp |= 0x1C;
6967 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6968
6969 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6970 tmp &= ~(0xFF << 16);
6971 tmp |= (0x1C << 16);
6972 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6973
6974 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6975 tmp &= ~(0xFF << 16);
6976 tmp |= (0x1C << 16);
6977 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6978
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006979 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6980 tmp |= (1 << 27);
6981 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006982
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006983 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6984 tmp |= (1 << 27);
6985 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006986
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006987 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6988 tmp &= ~(0xF << 28);
6989 tmp |= (4 << 28);
6990 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02006991
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03006992 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6993 tmp &= ~(0xF << 28);
6994 tmp |= (4 << 28);
6995 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03006996}
6997
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03006998/* Implements 3 different sequences from BSpec chapter "Display iCLK
6999 * Programming" based on the parameters passed:
7000 * - Sequence to enable CLKOUT_DP
7001 * - Sequence to enable CLKOUT_DP without spread
7002 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7003 */
7004static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7005 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03007006{
7007 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03007008 uint32_t reg, tmp;
7009
7010 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7011 with_spread = true;
7012 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7013 with_fdi, "LP PCH doesn't have FDI\n"))
7014 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03007015
7016 mutex_lock(&dev_priv->dpio_lock);
7017
7018 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7019 tmp &= ~SBI_SSCCTL_DISABLE;
7020 tmp |= SBI_SSCCTL_PATHALT;
7021 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7022
7023 udelay(24);
7024
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03007025 if (with_spread) {
7026 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7027 tmp &= ~SBI_SSCCTL_PATHALT;
7028 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03007029
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03007030 if (with_fdi) {
7031 lpt_reset_fdi_mphy(dev_priv);
7032 lpt_program_fdi_mphy(dev_priv);
7033 }
7034 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02007035
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03007036 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7037 SBI_GEN0 : SBI_DBUFF0;
7038 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7039 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7040 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01007041
7042 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02007043}
7044
Paulo Zanoni47701c32013-07-23 11:19:25 -03007045/* Sequence to disable CLKOUT_DP */
7046static void lpt_disable_clkout_dp(struct drm_device *dev)
7047{
7048 struct drm_i915_private *dev_priv = dev->dev_private;
7049 uint32_t reg, tmp;
7050
7051 mutex_lock(&dev_priv->dpio_lock);
7052
7053 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7054 SBI_GEN0 : SBI_DBUFF0;
7055 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7056 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7057 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7058
7059 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7060 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7061 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7062 tmp |= SBI_SSCCTL_PATHALT;
7063 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7064 udelay(32);
7065 }
7066 tmp |= SBI_SSCCTL_DISABLE;
7067 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7068 }
7069
7070 mutex_unlock(&dev_priv->dpio_lock);
7071}
7072
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007073static void lpt_init_pch_refclk(struct drm_device *dev)
7074{
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007075 struct intel_encoder *encoder;
7076 bool has_vga = false;
7077
Damien Lespiaub2784e12014-08-05 11:29:37 +01007078 for_each_intel_encoder(dev, encoder) {
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007079 switch (encoder->type) {
7080 case INTEL_OUTPUT_ANALOG:
7081 has_vga = true;
7082 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007083 default:
7084 break;
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007085 }
7086 }
7087
Paulo Zanoni47701c32013-07-23 11:19:25 -03007088 if (has_vga)
7089 lpt_enable_clkout_dp(dev, true, true);
7090 else
7091 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03007092}
7093
Paulo Zanonidde86e22012-12-01 12:04:25 -02007094/*
7095 * Initialize reference clocks when the driver loads
7096 */
7097void intel_init_pch_refclk(struct drm_device *dev)
7098{
7099 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7100 ironlake_init_pch_refclk(dev);
7101 else if (HAS_PCH_LPT(dev))
7102 lpt_init_pch_refclk(dev);
7103}
7104
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007105static int ironlake_get_refclk(struct drm_crtc *crtc)
7106{
7107 struct drm_device *dev = crtc->dev;
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007110 int num_connectors = 0;
7111 bool is_lvds = false;
7112
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007113 for_each_intel_encoder(dev, encoder) {
7114 if (encoder->new_crtc != to_intel_crtc(crtc))
7115 continue;
7116
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007117 switch (encoder->type) {
7118 case INTEL_OUTPUT_LVDS:
7119 is_lvds = true;
7120 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007121 default:
7122 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007123 }
7124 num_connectors++;
7125 }
7126
7127 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007128 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03007129 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007130 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07007131 }
7132
7133 return 120000;
7134}
7135
Daniel Vetter6ff93602013-04-19 11:24:36 +02007136static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03007137{
7138 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140 int pipe = intel_crtc->pipe;
7141 uint32_t val;
7142
Daniel Vetter78114072013-06-13 00:54:57 +02007143 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03007144
Daniel Vetter965e0c42013-03-27 00:44:57 +01007145 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03007146 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007147 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007148 break;
7149 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007150 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007151 break;
7152 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007153 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007154 break;
7155 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01007156 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03007157 break;
7158 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03007159 /* Case prevented by intel_choose_pipe_bpp_dither. */
7160 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03007161 }
7162
Daniel Vetterd8b32242013-04-25 17:54:44 +02007163 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03007164 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7165
Daniel Vetter6ff93602013-04-19 11:24:36 +02007166 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03007167 val |= PIPECONF_INTERLACED_ILK;
7168 else
7169 val |= PIPECONF_PROGRESSIVE;
7170
Daniel Vetter50f3b012013-03-27 00:44:56 +01007171 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02007172 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02007173
Paulo Zanonic8203562012-09-12 10:06:29 -03007174 I915_WRITE(PIPECONF(pipe), val);
7175 POSTING_READ(PIPECONF(pipe));
7176}
7177
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007178/*
7179 * Set up the pipe CSC unit.
7180 *
7181 * Currently only full range RGB to limited range RGB conversion
7182 * is supported, but eventually this should handle various
7183 * RGB<->YCbCr scenarios as well.
7184 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01007185static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007186{
7187 struct drm_device *dev = crtc->dev;
7188 struct drm_i915_private *dev_priv = dev->dev_private;
7189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7190 int pipe = intel_crtc->pipe;
7191 uint16_t coeff = 0x7800; /* 1.0 */
7192
7193 /*
7194 * TODO: Check what kind of values actually come out of the pipe
7195 * with these coeff/postoff values and adjust to get the best
7196 * accuracy. Perhaps we even need to take the bpc value into
7197 * consideration.
7198 */
7199
Daniel Vetter50f3b012013-03-27 00:44:56 +01007200 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007201 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7202
7203 /*
7204 * GY/GU and RY/RU should be the other way around according
7205 * to BSpec, but reality doesn't agree. Just set them up in
7206 * a way that results in the correct picture.
7207 */
7208 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7209 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7210
7211 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7212 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7213
7214 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7215 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7216
7217 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7218 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7219 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7220
7221 if (INTEL_INFO(dev)->gen > 6) {
7222 uint16_t postoff = 0;
7223
Daniel Vetter50f3b012013-03-27 00:44:56 +01007224 if (intel_crtc->config.limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02007225 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007226
7227 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7228 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7229 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7230
7231 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7232 } else {
7233 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7234
Daniel Vetter50f3b012013-03-27 00:44:56 +01007235 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007236 mode |= CSC_BLACK_SCREEN_OFFSET;
7237
7238 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7239 }
7240}
7241
Daniel Vetter6ff93602013-04-19 11:24:36 +02007242static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007243{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007244 struct drm_device *dev = crtc->dev;
7245 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007247 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02007248 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007249 uint32_t val;
7250
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02007251 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007252
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007253 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007254 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7255
Daniel Vetter6ff93602013-04-19 11:24:36 +02007256 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007257 val |= PIPECONF_INTERLACED_ILK;
7258 else
7259 val |= PIPECONF_PROGRESSIVE;
7260
Paulo Zanoni702e7a52012-10-23 18:29:59 -02007261 I915_WRITE(PIPECONF(cpu_transcoder), val);
7262 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02007263
7264 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7265 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007266
Satheeshakrishna M3cdf1222014-04-08 15:46:53 +05307267 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
Paulo Zanoni756f85c2013-11-02 21:07:38 -07007268 val = 0;
7269
7270 switch (intel_crtc->config.pipe_bpp) {
7271 case 18:
7272 val |= PIPEMISC_DITHER_6_BPC;
7273 break;
7274 case 24:
7275 val |= PIPEMISC_DITHER_8_BPC;
7276 break;
7277 case 30:
7278 val |= PIPEMISC_DITHER_10_BPC;
7279 break;
7280 case 36:
7281 val |= PIPEMISC_DITHER_12_BPC;
7282 break;
7283 default:
7284 /* Case prevented by pipe_config_set_bpp. */
7285 BUG();
7286 }
7287
7288 if (intel_crtc->config.dither)
7289 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7290
7291 I915_WRITE(PIPEMISC(pipe), val);
7292 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03007293}
7294
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007295static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007296 intel_clock_t *clock,
7297 bool *has_reduced_clock,
7298 intel_clock_t *reduced_clock)
7299{
7300 struct drm_device *dev = crtc->dev;
7301 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007303 int refclk;
7304 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02007305 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007306
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007307 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007308
7309 refclk = ironlake_get_refclk(crtc);
7310
7311 /*
7312 * Returns a set of divisors for the desired target clock with the given
7313 * refclk, or FALSE. The returned values represent the clock equation:
7314 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7315 */
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007316 limit = intel_limit(intel_crtc, refclk);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007317 ret = dev_priv->display.find_dpll(limit, intel_crtc,
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007318 intel_crtc->new_config->port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02007319 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007320 if (!ret)
7321 return false;
7322
7323 if (is_lvds && dev_priv->lvds_downclock_avail) {
7324 /*
7325 * Ensure we match the reduced clock's P to the target clock.
7326 * If the clocks don't match, we can't switch the display clock
7327 * by using the FP0/FP1. In such case we will disable the LVDS
7328 * downclock feature.
7329 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02007330 *has_reduced_clock =
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03007331 dev_priv->display.find_dpll(limit, intel_crtc,
Daniel Vetteree9300b2013-06-03 22:40:22 +02007332 dev_priv->lvds_downclock,
7333 refclk, clock,
7334 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007335 }
7336
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007337 return true;
7338}
7339
Paulo Zanonid4b19312012-11-29 11:29:32 -02007340int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7341{
7342 /*
7343 * Account for spread spectrum to avoid
7344 * oversubscribing the link. Max center spread
7345 * is 2.5%; use 5% for safety's sake.
7346 */
7347 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02007348 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02007349}
7350
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007351static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02007352{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007353 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03007354}
7355
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007356static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007357 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007358 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007359{
7360 struct drm_crtc *crtc = &intel_crtc->base;
7361 struct drm_device *dev = crtc->dev;
7362 struct drm_i915_private *dev_priv = dev->dev_private;
7363 struct intel_encoder *intel_encoder;
7364 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01007365 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02007366 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007367
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007368 for_each_intel_encoder(dev, intel_encoder) {
7369 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7370 continue;
7371
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007372 switch (intel_encoder->type) {
7373 case INTEL_OUTPUT_LVDS:
7374 is_lvds = true;
7375 break;
7376 case INTEL_OUTPUT_SDVO:
7377 case INTEL_OUTPUT_HDMI:
7378 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007379 break;
Paulo Zanoni6847d712014-10-27 17:47:52 -02007380 default:
7381 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007382 }
7383
7384 num_connectors++;
7385 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007386
Chris Wilsonc1858122010-12-03 21:35:48 +00007387 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07007388 factor = 21;
7389 if (is_lvds) {
7390 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007391 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02007392 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07007393 factor = 25;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007394 } else if (intel_crtc->new_config->sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07007395 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00007396
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007397 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02007398 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00007399
Daniel Vetter9a7c7892013-04-04 22:20:34 +02007400 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7401 *fp2 |= FP_CB_TUNE;
7402
Chris Wilson5eddb702010-09-11 13:48:45 +01007403 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08007404
Eric Anholta07d6782011-03-30 13:01:08 -07007405 if (is_lvds)
7406 dpll |= DPLLB_MODE_LVDS;
7407 else
7408 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007409
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007410 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02007411 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007412
7413 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007414 dpll |= DPLL_SDVO_HIGH_SPEED;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007415 if (intel_crtc->new_config->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007416 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08007417
Eric Anholta07d6782011-03-30 13:01:08 -07007418 /* compute bitmask from p1 value */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007419 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007420 /* also FPA1 */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007421 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07007422
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007423 switch (intel_crtc->new_config->dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07007424 case 5:
7425 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7426 break;
7427 case 7:
7428 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7429 break;
7430 case 10:
7431 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7432 break;
7433 case 14:
7434 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7435 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08007436 }
7437
Daniel Vetterb4c09f32013-04-30 14:01:42 +02007438 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05007439 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08007440 else
7441 dpll |= PLL_REF_INPUT_DREFCLK;
7442
Daniel Vetter959e16d2013-06-05 13:34:21 +02007443 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03007444}
7445
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02007446static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08007447{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007448 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007449 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007450 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03007451 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01007452 bool is_lvds = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007453 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007454
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007455 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
Jesse Barnes79e53942008-11-07 14:24:08 -08007456
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007457 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7458 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7459
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007460 ok = ironlake_compute_clocks(&crtc->base, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03007461 &has_reduced_clock, &reduced_clock);
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007462 if (!ok && !crtc->new_config->clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007463 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7464 return -EINVAL;
7465 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01007466 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007467 if (!crtc->new_config->clock_set) {
7468 crtc->new_config->dpll.n = clock.n;
7469 crtc->new_config->dpll.m1 = clock.m1;
7470 crtc->new_config->dpll.m2 = clock.m2;
7471 crtc->new_config->dpll.p1 = clock.p1;
7472 crtc->new_config->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01007473 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007474
Paulo Zanoni5dc52982012-10-05 12:05:56 -03007475 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007476 if (crtc->new_config->has_pch_encoder) {
7477 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007478 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007479 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007480
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007481 dpll = ironlake_compute_dpll(crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02007482 &fp, &reduced_clock,
7483 has_reduced_clock ? &fp2 : NULL);
7484
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007485 crtc->new_config->dpll_hw_state.dpll = dpll;
7486 crtc->new_config->dpll_hw_state.fp0 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007487 if (has_reduced_clock)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007488 crtc->new_config->dpll_hw_state.fp1 = fp2;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007489 else
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +02007490 crtc->new_config->dpll_hw_state.fp1 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02007491
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007492 pll = intel_get_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007493 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03007494 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007495 pipe_name(crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07007496 return -EINVAL;
7497 }
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02007498 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007499
Jani Nikulad330a952014-01-21 11:24:25 +02007500 if (is_lvds && has_reduced_clock && i915.powersave)
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007501 crtc->lowfreq_avail = true;
Daniel Vetterbcd644e2013-06-05 13:34:22 +02007502 else
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007503 crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02007504
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02007505 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007506}
7507
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007508static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7509 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02007510{
7511 struct drm_device *dev = crtc->base.dev;
7512 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007513 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02007514
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007515 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7516 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7517 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7518 & ~TU_SIZE_MASK;
7519 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7520 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7521 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7522}
7523
7524static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7525 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007526 struct intel_link_m_n *m_n,
7527 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007528{
7529 struct drm_device *dev = crtc->base.dev;
7530 struct drm_i915_private *dev_priv = dev->dev_private;
7531 enum pipe pipe = crtc->pipe;
7532
7533 if (INTEL_INFO(dev)->gen >= 5) {
7534 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7535 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7536 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7537 & ~TU_SIZE_MASK;
7538 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7539 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7540 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007541 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7542 * gen < 8) and if DRRS is supported (to make sure the
7543 * registers are not unnecessarily read).
7544 */
7545 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7546 crtc->config.has_drrs) {
7547 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7548 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7549 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7550 & ~TU_SIZE_MASK;
7551 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7552 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7553 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7554 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007555 } else {
7556 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7557 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7558 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7559 & ~TU_SIZE_MASK;
7560 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7561 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7562 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7563 }
7564}
7565
7566void intel_dp_get_m_n(struct intel_crtc *crtc,
7567 struct intel_crtc_config *pipe_config)
7568{
7569 if (crtc->config.has_pch_encoder)
7570 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7571 else
7572 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007573 &pipe_config->dp_m_n,
7574 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007575}
7576
Daniel Vetter72419202013-04-04 13:28:53 +02007577static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7578 struct intel_crtc_config *pipe_config)
7579{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03007580 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07007581 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02007582}
7583
Jesse Barnesbd2e2442014-11-13 17:51:47 +00007584static void skylake_get_pfit_config(struct intel_crtc *crtc,
7585 struct intel_crtc_config *pipe_config)
7586{
7587 struct drm_device *dev = crtc->base.dev;
7588 struct drm_i915_private *dev_priv = dev->dev_private;
7589 uint32_t tmp;
7590
7591 tmp = I915_READ(PS_CTL(crtc->pipe));
7592
7593 if (tmp & PS_ENABLE) {
7594 pipe_config->pch_pfit.enabled = true;
7595 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7596 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7597 }
7598}
7599
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007600static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7601 struct intel_crtc_config *pipe_config)
7602{
7603 struct drm_device *dev = crtc->base.dev;
7604 struct drm_i915_private *dev_priv = dev->dev_private;
7605 uint32_t tmp;
7606
7607 tmp = I915_READ(PF_CTL(crtc->pipe));
7608
7609 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01007610 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007611 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7612 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02007613
7614 /* We currently do not free assignements of panel fitters on
7615 * ivb/hsw (since we don't use the higher upscaling modes which
7616 * differentiates them) so just WARN about this case for now. */
7617 if (IS_GEN7(dev)) {
7618 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7619 PF_PIPE_SEL_IVB(crtc->pipe));
7620 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007621 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007622}
7623
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007624static void ironlake_get_plane_config(struct intel_crtc *crtc,
7625 struct intel_plane_config *plane_config)
7626{
7627 struct drm_device *dev = crtc->base.dev;
7628 struct drm_i915_private *dev_priv = dev->dev_private;
7629 u32 val, base, offset;
7630 int pipe = crtc->pipe, plane = crtc->plane;
7631 int fourcc, pixel_format;
7632 int aligned_height;
7633
Dave Airlie66e514c2014-04-03 07:51:54 +10007634 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7635 if (!crtc->base.primary->fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007636 DRM_DEBUG_KMS("failed to alloc fb\n");
7637 return;
7638 }
7639
7640 val = I915_READ(DSPCNTR(plane));
7641
7642 if (INTEL_INFO(dev)->gen >= 4)
7643 if (val & DISPPLANE_TILED)
7644 plane_config->tiled = true;
7645
7646 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7647 fourcc = intel_format_to_fourcc(pixel_format);
Dave Airlie66e514c2014-04-03 07:51:54 +10007648 crtc->base.primary->fb->pixel_format = fourcc;
7649 crtc->base.primary->fb->bits_per_pixel =
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007650 drm_format_plane_cpp(fourcc, 0) * 8;
7651
7652 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7653 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7654 offset = I915_READ(DSPOFFSET(plane));
7655 } else {
7656 if (plane_config->tiled)
7657 offset = I915_READ(DSPTILEOFF(plane));
7658 else
7659 offset = I915_READ(DSPLINOFF(plane));
7660 }
7661 plane_config->base = base;
7662
7663 val = I915_READ(PIPESRC(pipe));
Dave Airlie66e514c2014-04-03 07:51:54 +10007664 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7665 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007666
7667 val = I915_READ(DSPSTRIDE(pipe));
Rafael Barbalho026b96e2014-07-28 19:56:27 +01007668 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007669
Dave Airlie66e514c2014-04-03 07:51:54 +10007670 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007671 plane_config->tiled);
7672
Fabian Frederick1267a262014-07-01 20:39:41 +02007673 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7674 aligned_height);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007675
7676 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
Dave Airlie66e514c2014-04-03 07:51:54 +10007677 pipe, plane, crtc->base.primary->fb->width,
7678 crtc->base.primary->fb->height,
7679 crtc->base.primary->fb->bits_per_pixel, base,
7680 crtc->base.primary->fb->pitches[0],
Jesse Barnes4c6baa52014-03-07 08:57:50 -08007681 plane_config->size);
7682}
7683
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007684static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7685 struct intel_crtc_config *pipe_config)
7686{
7687 struct drm_device *dev = crtc->base.dev;
7688 struct drm_i915_private *dev_priv = dev->dev_private;
7689 uint32_t tmp;
7690
Daniel Vetterf458ebb2014-09-30 10:56:39 +02007691 if (!intel_display_power_is_enabled(dev_priv,
7692 POWER_DOMAIN_PIPE(crtc->pipe)))
Paulo Zanoni930e8c92014-07-04 13:38:34 -03007693 return false;
7694
Daniel Vettere143a212013-07-04 12:01:15 +02007695 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007696 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02007697
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007698 tmp = I915_READ(PIPECONF(crtc->pipe));
7699 if (!(tmp & PIPECONF_ENABLE))
7700 return false;
7701
Ville Syrjälä42571ae2013-09-06 23:29:00 +03007702 switch (tmp & PIPECONF_BPC_MASK) {
7703 case PIPECONF_6BPC:
7704 pipe_config->pipe_bpp = 18;
7705 break;
7706 case PIPECONF_8BPC:
7707 pipe_config->pipe_bpp = 24;
7708 break;
7709 case PIPECONF_10BPC:
7710 pipe_config->pipe_bpp = 30;
7711 break;
7712 case PIPECONF_12BPC:
7713 pipe_config->pipe_bpp = 36;
7714 break;
7715 default:
7716 break;
7717 }
7718
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02007719 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7720 pipe_config->limited_color_range = true;
7721
Daniel Vetterab9412b2013-05-03 11:49:46 +02007722 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02007723 struct intel_shared_dpll *pll;
7724
Daniel Vetter88adfff2013-03-28 10:42:01 +01007725 pipe_config->has_pch_encoder = true;
7726
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007727 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7728 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7729 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02007730
7731 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007732
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007733 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02007734 pipe_config->shared_dpll =
7735 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007736 } else {
7737 tmp = I915_READ(PCH_DPLL_SEL);
7738 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7739 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7740 else
7741 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7742 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02007743
7744 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7745
7746 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7747 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02007748
7749 tmp = pipe_config->dpll_hw_state.dpll;
7750 pipe_config->pixel_multiplier =
7751 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7752 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007753
7754 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02007755 } else {
7756 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02007757 }
7758
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007759 intel_get_pipe_timings(crtc, pipe_config);
7760
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02007761 ironlake_get_pfit_config(crtc, pipe_config);
7762
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01007763 return true;
7764}
7765
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007766static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7767{
7768 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007769 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007770
Damien Lespiaud3fcc802014-05-13 23:32:22 +01007771 for_each_intel_crtc(dev, crtc)
Paulo Zanoni798183c2013-12-06 20:29:01 -02007772 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007773 pipe_name(crtc->pipe));
7774
7775 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
Daniel Vetter8cc3e162014-06-25 22:01:46 +03007776 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7777 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7778 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007779 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7780 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7781 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -03007782 if (IS_HASWELL(dev))
7783 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7784 "CPU PWM2 enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007785 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7786 "PCH PWM1 enabled\n");
7787 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7788 "Utility pin enabled\n");
7789 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7790
Paulo Zanoni9926ada2014-04-01 19:39:47 -03007791 /*
7792 * In theory we can still leave IRQs enabled, as long as only the HPD
7793 * interrupts remain enabled. We used to check for that, but since it's
7794 * gen-specific and since we only disable LCPLL after we fully disable
7795 * the interrupts, the check below should be enough.
7796 */
Jesse Barnes9df7575f2014-06-20 09:29:20 -07007797 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007798}
7799
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007800static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7801{
7802 struct drm_device *dev = dev_priv->dev;
7803
7804 if (IS_HASWELL(dev))
7805 return I915_READ(D_COMP_HSW);
7806 else
7807 return I915_READ(D_COMP_BDW);
7808}
7809
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007810static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7811{
7812 struct drm_device *dev = dev_priv->dev;
7813
7814 if (IS_HASWELL(dev)) {
7815 mutex_lock(&dev_priv->rps.hw_lock);
7816 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7817 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03007818 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007819 mutex_unlock(&dev_priv->rps.hw_lock);
7820 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007821 I915_WRITE(D_COMP_BDW, val);
7822 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007823 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007824}
7825
7826/*
7827 * This function implements pieces of two sequences from BSpec:
7828 * - Sequence for display software to disable LCPLL
7829 * - Sequence for display software to allow package C8+
7830 * The steps implemented here are just the steps that actually touch the LCPLL
7831 * register. Callers should take care of disabling all the display engine
7832 * functions, doing the mode unset, fixing interrupts, etc.
7833 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007834static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7835 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007836{
7837 uint32_t val;
7838
7839 assert_can_disable_lcpll(dev_priv);
7840
7841 val = I915_READ(LCPLL_CTL);
7842
7843 if (switch_to_fclk) {
7844 val |= LCPLL_CD_SOURCE_FCLK;
7845 I915_WRITE(LCPLL_CTL, val);
7846
7847 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7848 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7849 DRM_ERROR("Switching to FCLK failed\n");
7850
7851 val = I915_READ(LCPLL_CTL);
7852 }
7853
7854 val |= LCPLL_PLL_DISABLE;
7855 I915_WRITE(LCPLL_CTL, val);
7856 POSTING_READ(LCPLL_CTL);
7857
7858 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7859 DRM_ERROR("LCPLL still locked\n");
7860
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007861 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007862 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007863 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007864 ndelay(100);
7865
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007866 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7867 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007868 DRM_ERROR("D_COMP RCOMP still in progress\n");
7869
7870 if (allow_power_down) {
7871 val = I915_READ(LCPLL_CTL);
7872 val |= LCPLL_POWER_DOWN_ALLOW;
7873 I915_WRITE(LCPLL_CTL, val);
7874 POSTING_READ(LCPLL_CTL);
7875 }
7876}
7877
7878/*
7879 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7880 * source.
7881 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03007882static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007883{
7884 uint32_t val;
7885
7886 val = I915_READ(LCPLL_CTL);
7887
7888 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7889 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7890 return;
7891
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007892 /*
7893 * Make sure we're not on PC8 state before disabling PC8, otherwise
7894 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7895 *
7896 * The other problem is that hsw_restore_lcpll() is called as part of
7897 * the runtime PM resume sequence, so we can't just call
7898 * gen6_gt_force_wake_get() because that function calls
7899 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7900 * while we are on the resume sequence. So to solve this problem we have
7901 * to call special forcewake code that doesn't touch runtime PM and
7902 * doesn't enable the forcewake delayed work.
7903 */
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007904 spin_lock_irq(&dev_priv->uncore.lock);
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007905 if (dev_priv->uncore.forcewake_count++ == 0)
7906 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007907 spin_unlock_irq(&dev_priv->uncore.lock);
Paulo Zanoni215733f2013-08-19 13:18:07 -03007908
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007909 if (val & LCPLL_POWER_DOWN_ALLOW) {
7910 val &= ~LCPLL_POWER_DOWN_ALLOW;
7911 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02007912 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007913 }
7914
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03007915 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007916 val |= D_COMP_COMP_FORCE;
7917 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03007918 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007919
7920 val = I915_READ(LCPLL_CTL);
7921 val &= ~LCPLL_PLL_DISABLE;
7922 I915_WRITE(LCPLL_CTL, val);
7923
7924 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7925 DRM_ERROR("LCPLL not locked yet\n");
7926
7927 if (val & LCPLL_CD_SOURCE_FCLK) {
7928 val = I915_READ(LCPLL_CTL);
7929 val &= ~LCPLL_CD_SOURCE_FCLK;
7930 I915_WRITE(LCPLL_CTL, val);
7931
7932 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7933 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7934 DRM_ERROR("Switching back to LCPLL failed\n");
7935 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03007936
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007937 /* See the big comment above. */
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007938 spin_lock_irq(&dev_priv->uncore.lock);
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03007939 if (--dev_priv->uncore.forcewake_count == 0)
7940 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
Daniel Vetterd2e40e22014-09-15 14:55:31 +02007941 spin_unlock_irq(&dev_priv->uncore.lock);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03007942}
7943
Paulo Zanoni765dab62014-03-07 20:08:18 -03007944/*
7945 * Package states C8 and deeper are really deep PC states that can only be
7946 * reached when all the devices on the system allow it, so even if the graphics
7947 * device allows PC8+, it doesn't mean the system will actually get to these
7948 * states. Our driver only allows PC8+ when going into runtime PM.
7949 *
7950 * The requirements for PC8+ are that all the outputs are disabled, the power
7951 * well is disabled and most interrupts are disabled, and these are also
7952 * requirements for runtime PM. When these conditions are met, we manually do
7953 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7954 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7955 * hang the machine.
7956 *
7957 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7958 * the state of some registers, so when we come back from PC8+ we need to
7959 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7960 * need to take care of the registers kept by RC6. Notice that this happens even
7961 * if we don't put the device in PCI D3 state (which is what currently happens
7962 * because of the runtime PM support).
7963 *
7964 * For more, read "Display Sequences for Package C8" on the hardware
7965 * documentation.
7966 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007967void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007968{
Paulo Zanonic67a4702013-08-19 13:18:09 -03007969 struct drm_device *dev = dev_priv->dev;
7970 uint32_t val;
7971
Paulo Zanonic67a4702013-08-19 13:18:09 -03007972 DRM_DEBUG_KMS("Enabling package C8+\n");
7973
Paulo Zanonic67a4702013-08-19 13:18:09 -03007974 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7975 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7976 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7977 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7978 }
7979
7980 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007981 hsw_disable_lcpll(dev_priv, true, true);
7982}
7983
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03007984void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03007985{
7986 struct drm_device *dev = dev_priv->dev;
7987 uint32_t val;
7988
Paulo Zanonic67a4702013-08-19 13:18:09 -03007989 DRM_DEBUG_KMS("Disabling package C8+\n");
7990
7991 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03007992 lpt_init_pch_refclk(dev);
7993
7994 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7995 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7996 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7997 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7998 }
7999
8000 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03008001}
8002
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +02008003static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03008004{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03008005 if (!intel_ddi_pll_select(crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03008006 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03008007
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03008008 crtc->lowfreq_avail = false;
Daniel Vetter644cef32014-04-24 23:55:07 +02008009
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02008010 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008011}
8012
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00008013static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8014 enum port port,
8015 struct intel_crtc_config *pipe_config)
8016{
8017 u32 temp;
8018
8019 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8020 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8021
8022 switch (pipe_config->ddi_pll_sel) {
8023 case SKL_DPLL1:
8024 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8025 break;
8026 case SKL_DPLL2:
8027 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8028 break;
8029 case SKL_DPLL3:
8030 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8031 break;
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00008032 }
8033}
8034
Damien Lespiau7d2c8172014-07-29 18:06:18 +01008035static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8036 enum port port,
8037 struct intel_crtc_config *pipe_config)
8038{
8039 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8040
8041 switch (pipe_config->ddi_pll_sel) {
8042 case PORT_CLK_SEL_WRPLL1:
8043 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8044 break;
8045 case PORT_CLK_SEL_WRPLL2:
8046 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8047 break;
8048 }
8049}
8050
Daniel Vetter26804af2014-06-25 22:01:55 +03008051static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8052 struct intel_crtc_config *pipe_config)
8053{
8054 struct drm_device *dev = crtc->base.dev;
8055 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03008056 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03008057 enum port port;
8058 uint32_t tmp;
8059
8060 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8061
8062 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8063
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00008064 if (IS_SKYLAKE(dev))
8065 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8066 else
8067 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +03008068
Daniel Vetterd452c5b2014-07-04 11:27:39 -03008069 if (pipe_config->shared_dpll >= 0) {
8070 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8071
8072 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8073 &pipe_config->dpll_hw_state));
8074 }
8075
Daniel Vetter26804af2014-06-25 22:01:55 +03008076 /*
8077 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8078 * DDI E. So just check whether this pipe is wired to DDI E and whether
8079 * the PCH transcoder is on.
8080 */
Damien Lespiauca370452013-12-03 13:56:24 +00008081 if (INTEL_INFO(dev)->gen < 9 &&
8082 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter26804af2014-06-25 22:01:55 +03008083 pipe_config->has_pch_encoder = true;
8084
8085 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8086 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8087 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8088
8089 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8090 }
8091}
8092
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008093static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8094 struct intel_crtc_config *pipe_config)
8095{
8096 struct drm_device *dev = crtc->base.dev;
8097 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008098 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008099 uint32_t tmp;
8100
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008101 if (!intel_display_power_is_enabled(dev_priv,
Imre Deakb5482bd2014-03-05 16:20:55 +02008102 POWER_DOMAIN_PIPE(crtc->pipe)))
8103 return false;
8104
Daniel Vettere143a212013-07-04 12:01:15 +02008105 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008106 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8107
Daniel Vettereccb1402013-05-22 00:50:22 +02008108 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8109 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8110 enum pipe trans_edp_pipe;
8111 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8112 default:
8113 WARN(1, "unknown pipe linked to edp transcoder\n");
8114 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8115 case TRANS_DDI_EDP_INPUT_A_ON:
8116 trans_edp_pipe = PIPE_A;
8117 break;
8118 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8119 trans_edp_pipe = PIPE_B;
8120 break;
8121 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8122 trans_edp_pipe = PIPE_C;
8123 break;
8124 }
8125
8126 if (trans_edp_pipe == crtc->pipe)
8127 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8128 }
8129
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008130 if (!intel_display_power_is_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +02008131 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03008132 return false;
8133
Daniel Vettereccb1402013-05-22 00:50:22 +02008134 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008135 if (!(tmp & PIPECONF_ENABLE))
8136 return false;
8137
Daniel Vetter26804af2014-06-25 22:01:55 +03008138 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02008139
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008140 intel_get_pipe_timings(crtc, pipe_config);
8141
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008142 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00008143 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8144 if (IS_SKYLAKE(dev))
8145 skylake_get_pfit_config(crtc, pipe_config);
8146 else
8147 ironlake_get_pfit_config(crtc, pipe_config);
8148 }
Daniel Vetter88adfff2013-03-28 10:42:01 +01008149
Jesse Barnese59150d2014-01-07 13:30:45 -08008150 if (IS_HASWELL(dev))
8151 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8152 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03008153
Clint Taylorebb69c92014-09-30 10:30:22 -07008154 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8155 pipe_config->pixel_multiplier =
8156 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8157 } else {
8158 pipe_config->pixel_multiplier = 1;
8159 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02008160
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008161 return true;
8162}
8163
Chris Wilson560b85b2010-08-07 11:01:38 +01008164static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8165{
8166 struct drm_device *dev = crtc->dev;
8167 struct drm_i915_private *dev_priv = dev->dev_private;
8168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälädc41c152014-08-13 11:57:05 +03008169 uint32_t cntl = 0, size = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01008170
Ville Syrjälädc41c152014-08-13 11:57:05 +03008171 if (base) {
8172 unsigned int width = intel_crtc->cursor_width;
8173 unsigned int height = intel_crtc->cursor_height;
8174 unsigned int stride = roundup_pow_of_two(width) * 4;
8175
8176 switch (stride) {
8177 default:
8178 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8179 width, stride);
8180 stride = 256;
8181 /* fallthrough */
8182 case 256:
8183 case 512:
8184 case 1024:
8185 case 2048:
8186 break;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008187 }
8188
Ville Syrjälädc41c152014-08-13 11:57:05 +03008189 cntl |= CURSOR_ENABLE |
8190 CURSOR_GAMMA_ENABLE |
8191 CURSOR_FORMAT_ARGB |
8192 CURSOR_STRIDE(stride);
8193
8194 size = (height << 12) | width;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008195 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008196
Ville Syrjälädc41c152014-08-13 11:57:05 +03008197 if (intel_crtc->cursor_cntl != 0 &&
8198 (intel_crtc->cursor_base != base ||
8199 intel_crtc->cursor_size != size ||
8200 intel_crtc->cursor_cntl != cntl)) {
8201 /* On these chipsets we can only modify the base/size/stride
8202 * whilst the cursor is disabled.
8203 */
8204 I915_WRITE(_CURACNTR, 0);
8205 POSTING_READ(_CURACNTR);
8206 intel_crtc->cursor_cntl = 0;
8207 }
8208
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008209 if (intel_crtc->cursor_base != base) {
Ville Syrjälädc41c152014-08-13 11:57:05 +03008210 I915_WRITE(_CURABASE, base);
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008211 intel_crtc->cursor_base = base;
8212 }
Ville Syrjälädc41c152014-08-13 11:57:05 +03008213
8214 if (intel_crtc->cursor_size != size) {
8215 I915_WRITE(CURSIZE, size);
8216 intel_crtc->cursor_size = size;
8217 }
8218
Chris Wilson4b0e3332014-05-30 16:35:26 +03008219 if (intel_crtc->cursor_cntl != cntl) {
8220 I915_WRITE(_CURACNTR, cntl);
8221 POSTING_READ(_CURACNTR);
8222 intel_crtc->cursor_cntl = cntl;
8223 }
Chris Wilson560b85b2010-08-07 11:01:38 +01008224}
8225
8226static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8227{
8228 struct drm_device *dev = crtc->dev;
8229 struct drm_i915_private *dev_priv = dev->dev_private;
8230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8231 int pipe = intel_crtc->pipe;
Chris Wilson4b0e3332014-05-30 16:35:26 +03008232 uint32_t cntl;
Chris Wilson560b85b2010-08-07 11:01:38 +01008233
Chris Wilson4b0e3332014-05-30 16:35:26 +03008234 cntl = 0;
8235 if (base) {
8236 cntl = MCURSOR_GAMMA_ENABLE;
8237 switch (intel_crtc->cursor_width) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +05308238 case 64:
8239 cntl |= CURSOR_MODE_64_ARGB_AX;
8240 break;
8241 case 128:
8242 cntl |= CURSOR_MODE_128_ARGB_AX;
8243 break;
8244 case 256:
8245 cntl |= CURSOR_MODE_256_ARGB_AX;
8246 break;
8247 default:
8248 WARN_ON(1);
8249 return;
Chris Wilson560b85b2010-08-07 11:01:38 +01008250 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008251 cntl |= pipe << 28; /* Connect to correct pipe */
Ville Syrjälä47bf17a2014-09-12 20:53:33 +03008252
8253 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8254 cntl |= CURSOR_PIPE_CSC_ENABLE;
Chris Wilson560b85b2010-08-07 11:01:38 +01008255 }
Chris Wilson4b0e3332014-05-30 16:35:26 +03008256
Ville Syrjälä4398ad42014-10-23 07:41:34 -07008257 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8258 cntl |= CURSOR_ROTATE_180;
8259
Chris Wilson4b0e3332014-05-30 16:35:26 +03008260 if (intel_crtc->cursor_cntl != cntl) {
8261 I915_WRITE(CURCNTR(pipe), cntl);
8262 POSTING_READ(CURCNTR(pipe));
8263 intel_crtc->cursor_cntl = cntl;
8264 }
8265
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008266 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008267 I915_WRITE(CURBASE(pipe), base);
8268 POSTING_READ(CURBASE(pipe));
Ville Syrjälä99d1f382014-09-12 20:53:32 +03008269
8270 intel_crtc->cursor_base = base;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07008271}
8272
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008273/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01008274static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8275 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008276{
8277 struct drm_device *dev = crtc->dev;
8278 struct drm_i915_private *dev_priv = dev->dev_private;
8279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8280 int pipe = intel_crtc->pipe;
Matt Roper3d7d6512014-06-10 08:28:13 -07008281 int x = crtc->cursor_x;
8282 int y = crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008283 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008284
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008285 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008286 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008287
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03008288 if (x >= intel_crtc->config.pipe_src_w)
8289 base = 0;
8290
8291 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008292 base = 0;
8293
8294 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008295 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008296 base = 0;
8297
8298 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8299 x = -x;
8300 }
8301 pos |= x << CURSOR_X_SHIFT;
8302
8303 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03008304 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008305 base = 0;
8306
8307 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8308 y = -y;
8309 }
8310 pos |= y << CURSOR_Y_SHIFT;
8311
Chris Wilson4b0e3332014-05-30 16:35:26 +03008312 if (base == 0 && intel_crtc->cursor_base == 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008313 return;
8314
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008315 I915_WRITE(CURPOS(pipe), pos);
8316
Ville Syrjälä4398ad42014-10-23 07:41:34 -07008317 /* ILK+ do this automagically */
8318 if (HAS_GMCH_DISPLAY(dev) &&
8319 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8320 base += (intel_crtc->cursor_height *
8321 intel_crtc->cursor_width - 1) * 4;
8322 }
8323
Ville Syrjälä8ac54662014-08-12 19:39:54 +03008324 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03008325 i845_update_cursor(crtc, base);
8326 else
8327 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008328}
8329
Ville Syrjälädc41c152014-08-13 11:57:05 +03008330static bool cursor_size_ok(struct drm_device *dev,
8331 uint32_t width, uint32_t height)
8332{
8333 if (width == 0 || height == 0)
8334 return false;
8335
8336 /*
8337 * 845g/865g are special in that they are only limited by
8338 * the width of their cursors, the height is arbitrary up to
8339 * the precision of the register. Everything else requires
8340 * square cursors, limited to a few power-of-two sizes.
8341 */
8342 if (IS_845G(dev) || IS_I865G(dev)) {
8343 if ((width & 63) != 0)
8344 return false;
8345
8346 if (width > (IS_845G(dev) ? 64 : 512))
8347 return false;
8348
8349 if (height > 1023)
8350 return false;
8351 } else {
8352 switch (width | height) {
8353 case 256:
8354 case 128:
8355 if (IS_GEN2(dev))
8356 return false;
8357 case 64:
8358 break;
8359 default:
8360 return false;
8361 }
8362 }
8363
8364 return true;
8365}
8366
Matt Ropere3287952014-06-10 08:28:12 -07008367static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8368 struct drm_i915_gem_object *obj,
8369 uint32_t width, uint32_t height)
Jesse Barnes79e53942008-11-07 14:24:08 -08008370{
8371 struct drm_device *dev = crtc->dev;
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02008374 enum pipe pipe = intel_crtc->pipe;
Gustavo Padovan757f9a32014-09-24 14:20:24 -03008375 unsigned old_width;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008376 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008377 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008378
Jesse Barnes79e53942008-11-07 14:24:08 -08008379 /* if we want to turn off the cursor ignore width and height */
Matt Ropere3287952014-06-10 08:28:12 -07008380 if (!obj) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008381 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008382 addr = 0;
Pierre Willenbrock50044172009-02-23 10:12:15 +10008383 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008384 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08008385 }
8386
Dave Airlie71acb5e2008-12-30 20:31:46 +10008387 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008388 mutex_lock(&dev->struct_mutex);
Damien Lespiau3d13ef22014-02-07 19:12:47 +00008389 if (!INTEL_INFO(dev)->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00008390 unsigned alignment;
8391
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008392 /*
8393 * Global gtt pte registers are special registers which actually
8394 * forward writes to a chunk of system memory. Which means that
8395 * there is no risk that the register values disappear as soon
8396 * as we call intel_runtime_pm_put(), so it is correct to wrap
8397 * only the pin/unpin/fence and not more.
8398 */
8399 intel_runtime_pm_get(dev_priv);
8400
Chris Wilson693db182013-03-05 14:52:39 +00008401 /* Note that the w/a also requires 2 PTE of padding following
8402 * the bo. We currently fill all unused PTE with the shadow
8403 * page and so we should always have valid PTE following the
8404 * cursor preventing the VT-d warning.
8405 */
8406 alignment = 0;
8407 if (need_vtd_wa(dev))
8408 alignment = 64*1024;
8409
8410 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01008411 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008412 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008413 intel_runtime_pm_put(dev_priv);
Chris Wilson2da3b9b2011-04-14 09:41:17 +01008414 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008415 }
8416
Chris Wilsond9e86c02010-11-10 16:40:20 +00008417 ret = i915_gem_object_put_fence(obj);
8418 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008419 DRM_DEBUG_KMS("failed to release fence for cursor");
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008420 intel_runtime_pm_put(dev_priv);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008421 goto fail_unpin;
8422 }
8423
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008424 addr = i915_gem_obj_ggtt_offset(obj);
Paulo Zanonid6dd6842014-08-15 15:59:32 -03008425
8426 intel_runtime_pm_put(dev_priv);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008427 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01008428 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson00731152014-05-21 12:42:56 +01008429 ret = i915_gem_object_attach_phys(obj, align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10008430 if (ret) {
Daniel Vetter3b25b312014-02-14 14:06:06 +01008431 DRM_DEBUG_KMS("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008432 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10008433 }
Chris Wilson00731152014-05-21 12:42:56 +01008434 addr = obj->phys_handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008435 }
8436
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008437 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008438 if (intel_crtc->cursor_bo) {
Chris Wilson00731152014-05-21 12:42:56 +01008439 if (!INTEL_INFO(dev)->cursor_needs_physical)
Chris Wilsoncc98b412013-08-09 12:25:09 +01008440 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008441 }
Jesse Barnes80824002009-09-10 15:28:06 -07008442
Daniel Vettera071fa02014-06-18 23:28:09 +02008443 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8444 INTEL_FRONTBUFFER_CURSOR(pipe));
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008445 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008446
Chris Wilson64f962e2014-03-26 12:38:15 +00008447 old_width = intel_crtc->cursor_width;
8448
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008449 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00008450 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01008451 intel_crtc->cursor_width = width;
8452 intel_crtc->cursor_height = height;
8453
Chris Wilson64f962e2014-03-26 12:38:15 +00008454 if (intel_crtc->active) {
8455 if (old_width != width)
8456 intel_update_watermarks(crtc);
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03008457 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05008458
Gustavo Padovan3f20df92014-10-24 14:51:34 +01008459 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8460 }
Daniel Vetterf99d7062014-06-19 16:01:59 +02008461
Jesse Barnes79e53942008-11-07 14:24:08 -08008462 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01008463fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01008464 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05008465fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10008466 mutex_unlock(&dev->struct_mutex);
8467 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008468}
8469
Jesse Barnes79e53942008-11-07 14:24:08 -08008470static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01008471 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08008472{
James Simmons72034252010-08-03 01:33:19 +01008473 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08008474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008475
James Simmons72034252010-08-03 01:33:19 +01008476 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008477 intel_crtc->lut_r[i] = red[i] >> 8;
8478 intel_crtc->lut_g[i] = green[i] >> 8;
8479 intel_crtc->lut_b[i] = blue[i] >> 8;
8480 }
8481
8482 intel_crtc_load_lut(crtc);
8483}
8484
Jesse Barnes79e53942008-11-07 14:24:08 -08008485/* VESA 640x480x72Hz mode to set on the pipe */
8486static struct drm_display_mode load_detect_mode = {
8487 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8488 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8489};
8490
Daniel Vettera8bb6812014-02-10 18:00:39 +01008491struct drm_framebuffer *
8492__intel_framebuffer_create(struct drm_device *dev,
8493 struct drm_mode_fb_cmd2 *mode_cmd,
8494 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +01008495{
8496 struct intel_framebuffer *intel_fb;
8497 int ret;
8498
8499 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8500 if (!intel_fb) {
Alexey Khoroshilov6ccb81f2014-11-08 01:41:23 +03008501 drm_gem_object_unreference(&obj->base);
Chris Wilsond2dff872011-04-19 08:36:26 +01008502 return ERR_PTR(-ENOMEM);
8503 }
8504
8505 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008506 if (ret)
8507 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01008508
8509 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008510err:
Alexey Khoroshilov6ccb81f2014-11-08 01:41:23 +03008511 drm_gem_object_unreference(&obj->base);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02008512 kfree(intel_fb);
8513
8514 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01008515}
8516
Daniel Vetterb5ea6422014-03-02 21:18:00 +01008517static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +01008518intel_framebuffer_create(struct drm_device *dev,
8519 struct drm_mode_fb_cmd2 *mode_cmd,
8520 struct drm_i915_gem_object *obj)
8521{
8522 struct drm_framebuffer *fb;
8523 int ret;
8524
8525 ret = i915_mutex_lock_interruptible(dev);
8526 if (ret)
8527 return ERR_PTR(ret);
8528 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8529 mutex_unlock(&dev->struct_mutex);
8530
8531 return fb;
8532}
8533
Chris Wilsond2dff872011-04-19 08:36:26 +01008534static u32
8535intel_framebuffer_pitch_for_width(int width, int bpp)
8536{
8537 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8538 return ALIGN(pitch, 64);
8539}
8540
8541static u32
8542intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8543{
8544 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +02008545 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +01008546}
8547
8548static struct drm_framebuffer *
8549intel_framebuffer_create_for_mode(struct drm_device *dev,
8550 struct drm_display_mode *mode,
8551 int depth, int bpp)
8552{
8553 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00008554 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01008555
8556 obj = i915_gem_alloc_object(dev,
8557 intel_framebuffer_size_for_mode(mode, bpp));
8558 if (obj == NULL)
8559 return ERR_PTR(-ENOMEM);
8560
8561 mode_cmd.width = mode->hdisplay;
8562 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008563 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8564 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00008565 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01008566
8567 return intel_framebuffer_create(dev, &mode_cmd, obj);
8568}
8569
8570static struct drm_framebuffer *
8571mode_fits_in_fbdev(struct drm_device *dev,
8572 struct drm_display_mode *mode)
8573{
Daniel Vetter4520f532013-10-09 09:18:51 +02008574#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01008575 struct drm_i915_private *dev_priv = dev->dev_private;
8576 struct drm_i915_gem_object *obj;
8577 struct drm_framebuffer *fb;
8578
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008579 if (!dev_priv->fbdev)
8580 return NULL;
8581
8582 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +01008583 return NULL;
8584
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008585 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +01008586 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +01008587
Jesse Barnes8bcd4552014-02-07 12:10:38 -08008588 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008589 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8590 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01008591 return NULL;
8592
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008593 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01008594 return NULL;
8595
8596 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02008597#else
8598 return NULL;
8599#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01008600}
8601
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008602bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01008603 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05008604 struct intel_load_detect_pipe *old,
8605 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -08008606{
8607 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008608 struct intel_encoder *intel_encoder =
8609 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08008610 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008611 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008612 struct drm_crtc *crtc = NULL;
8613 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02008614 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -05008615 struct drm_mode_config *config = &dev->mode_config;
8616 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008617
Chris Wilsond2dff872011-04-19 08:36:26 +01008618 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008619 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008620 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008621
Rob Clark51fd3712013-11-19 12:10:12 -05008622retry:
8623 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8624 if (ret)
8625 goto fail_unlock;
Daniel Vetter6e9f7982014-05-29 23:54:47 +02008626
Jesse Barnes79e53942008-11-07 14:24:08 -08008627 /*
8628 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01008629 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008630 * - if the connector already has an assigned crtc, use it (but make
8631 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01008632 *
Jesse Barnes79e53942008-11-07 14:24:08 -08008633 * - try to find the first unused crtc that can drive this connector,
8634 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08008635 */
8636
8637 /* See if we already have a CRTC for this connector */
8638 if (encoder->crtc) {
8639 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01008640
Rob Clark51fd3712013-11-19 12:10:12 -05008641 ret = drm_modeset_lock(&crtc->mutex, ctx);
8642 if (ret)
8643 goto fail_unlock;
Daniel Vetter7b240562012-12-12 00:35:33 +01008644
Daniel Vetter24218aa2012-08-12 19:27:11 +02008645 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008646 old->load_detect_temp = false;
8647
8648 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008649 if (connector->dpms != DRM_MODE_DPMS_ON)
8650 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01008651
Chris Wilson71731882011-04-19 23:10:58 +01008652 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08008653 }
8654
8655 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01008656 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008657 i++;
8658 if (!(encoder->possible_crtcs & (1 << i)))
8659 continue;
Ville Syrjäläa4592492014-08-11 13:15:36 +03008660 if (possible_crtc->enabled)
8661 continue;
8662 /* This can occur when applying the pipe A quirk on resume. */
8663 if (to_intel_crtc(possible_crtc)->new_enabled)
8664 continue;
8665
8666 crtc = possible_crtc;
8667 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08008668 }
8669
8670 /*
8671 * If we didn't find an unused CRTC, don't use any.
8672 */
8673 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01008674 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Rob Clark51fd3712013-11-19 12:10:12 -05008675 goto fail_unlock;
Jesse Barnes79e53942008-11-07 14:24:08 -08008676 }
8677
Rob Clark51fd3712013-11-19 12:10:12 -05008678 ret = drm_modeset_lock(&crtc->mutex, ctx);
8679 if (ret)
8680 goto fail_unlock;
Daniel Vetterfc303102012-07-09 10:40:58 +02008681 intel_encoder->new_crtc = to_intel_crtc(crtc);
8682 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008683
8684 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008685 intel_crtc->new_enabled = true;
8686 intel_crtc->new_config = &intel_crtc->config;
Daniel Vetter24218aa2012-08-12 19:27:11 +02008687 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01008688 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01008689 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08008690
Chris Wilson64927112011-04-20 07:25:26 +01008691 if (!mode)
8692 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08008693
Chris Wilsond2dff872011-04-19 08:36:26 +01008694 /* We need a framebuffer large enough to accommodate all accesses
8695 * that the plane may generate whilst we perform load detection.
8696 * We can not rely on the fbcon either being present (we get called
8697 * during its initialisation to detect all boot displays, or it may
8698 * not even exist) or that it is large enough to satisfy the
8699 * requested mode.
8700 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02008701 fb = mode_fits_in_fbdev(dev, mode);
8702 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008703 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008704 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8705 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01008706 } else
8707 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02008708 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01008709 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008710 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008711 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008712
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008713 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01008714 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01008715 if (old->release_fb)
8716 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008717 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08008718 }
Chris Wilson71731882011-04-19 23:10:58 +01008719
Jesse Barnes79e53942008-11-07 14:24:08 -08008720 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008721 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01008722 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008723
8724 fail:
8725 intel_crtc->new_enabled = crtc->enabled;
8726 if (intel_crtc->new_enabled)
8727 intel_crtc->new_config = &intel_crtc->config;
8728 else
8729 intel_crtc->new_config = NULL;
Rob Clark51fd3712013-11-19 12:10:12 -05008730fail_unlock:
8731 if (ret == -EDEADLK) {
8732 drm_modeset_backoff(ctx);
8733 goto retry;
8734 }
8735
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008736 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008737}
8738
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008739void intel_release_load_detect_pipe(struct drm_connector *connector,
Ville Syrjälä208bf9f2014-08-11 13:15:35 +03008740 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08008741{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02008742 struct intel_encoder *intel_encoder =
8743 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01008744 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01008745 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08008747
Chris Wilsond2dff872011-04-19 08:36:26 +01008748 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03008749 connector->base.id, connector->name,
Jani Nikula8e329a02014-06-03 14:56:21 +03008750 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +01008751
Chris Wilson8261b192011-04-19 23:18:09 +01008752 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02008753 to_intel_connector(connector)->new_encoder = NULL;
8754 intel_encoder->new_crtc = NULL;
Ville Syrjälä412b61d2014-01-17 15:59:39 +02008755 intel_crtc->new_enabled = false;
8756 intel_crtc->new_config = NULL;
Daniel Vetterfc303102012-07-09 10:40:58 +02008757 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01008758
Daniel Vetter36206362012-12-10 20:42:17 +01008759 if (old->release_fb) {
8760 drm_framebuffer_unregister_private(old->release_fb);
8761 drm_framebuffer_unreference(old->release_fb);
8762 }
Chris Wilsond2dff872011-04-19 08:36:26 +01008763
Chris Wilson0622a532011-04-21 09:32:11 +01008764 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008765 }
8766
Eric Anholtc751ce42010-03-25 11:48:48 -07008767 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02008768 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8769 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008770}
8771
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008772static int i9xx_pll_refclk(struct drm_device *dev,
8773 const struct intel_crtc_config *pipe_config)
8774{
8775 struct drm_i915_private *dev_priv = dev->dev_private;
8776 u32 dpll = pipe_config->dpll_hw_state.dpll;
8777
8778 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008779 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008780 else if (HAS_PCH_SPLIT(dev))
8781 return 120000;
8782 else if (!IS_GEN2(dev))
8783 return 96000;
8784 else
8785 return 48000;
8786}
8787
Jesse Barnes79e53942008-11-07 14:24:08 -08008788/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008789static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8790 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08008791{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008792 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08008793 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008794 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008795 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08008796 u32 fp;
8797 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008798 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08008799
8800 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03008801 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008802 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03008803 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08008804
8805 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008806 if (IS_PINEVIEW(dev)) {
8807 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8808 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08008809 } else {
8810 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8811 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8812 }
8813
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008814 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008815 if (IS_PINEVIEW(dev))
8816 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8817 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08008818 else
8819 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08008820 DPLL_FPA01_P1_POST_DIV_SHIFT);
8821
8822 switch (dpll & DPLL_MODE_MASK) {
8823 case DPLLB_MODE_DAC_SERIAL:
8824 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8825 5 : 10;
8826 break;
8827 case DPLLB_MODE_LVDS:
8828 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8829 7 : 14;
8830 break;
8831 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08008832 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08008833 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008834 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08008835 }
8836
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008837 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008838 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02008839 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008840 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008841 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02008842 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008843 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08008844
8845 if (is_lvds) {
8846 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8847 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02008848
8849 if (lvds & LVDS_CLKB_POWER_UP)
8850 clock.p2 = 7;
8851 else
8852 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08008853 } else {
8854 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8855 clock.p1 = 2;
8856 else {
8857 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8858 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8859 }
8860 if (dpll & PLL_P2_DIVIDE_BY_4)
8861 clock.p2 = 4;
8862 else
8863 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08008864 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008865
8866 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008867 }
8868
Ville Syrjälä18442d02013-09-13 16:00:08 +03008869 /*
8870 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008871 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008872 * encoder's get_config() function.
8873 */
8874 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008875}
8876
Ville Syrjälä6878da02013-09-13 15:59:11 +03008877int intel_dotclock_calculate(int link_freq,
8878 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008879{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008880 /*
8881 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008882 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008883 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008884 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008885 *
8886 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008887 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008888 */
8889
Ville Syrjälä6878da02013-09-13 15:59:11 +03008890 if (!m_n->link_n)
8891 return 0;
8892
8893 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8894}
8895
Ville Syrjälä18442d02013-09-13 16:00:08 +03008896static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8897 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008898{
8899 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008900
8901 /* read out port_clock from the DPLL */
8902 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008903
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008904 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008905 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008906 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008907 * agree once we know their relationship in the encoder's
8908 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008909 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008910 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008911 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8912 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008913}
8914
8915/** Returns the currently programmed mode of the given pipe. */
8916struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8917 struct drm_crtc *crtc)
8918{
Jesse Barnes548f2452011-02-17 10:40:53 -08008919 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008921 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008922 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008923 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008924 int htot = I915_READ(HTOTAL(cpu_transcoder));
8925 int hsync = I915_READ(HSYNC(cpu_transcoder));
8926 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8927 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008928 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008929
8930 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8931 if (!mode)
8932 return NULL;
8933
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008934 /*
8935 * Construct a pipe_config sufficient for getting the clock info
8936 * back out of crtc_clock_get.
8937 *
8938 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8939 * to use a real value here instead.
8940 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008941 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008942 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008943 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8944 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8945 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008946 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8947
Ville Syrjälä773ae032013-09-23 17:48:20 +03008948 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008949 mode->hdisplay = (htot & 0xffff) + 1;
8950 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8951 mode->hsync_start = (hsync & 0xffff) + 1;
8952 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8953 mode->vdisplay = (vtot & 0xffff) + 1;
8954 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8955 mode->vsync_start = (vsync & 0xffff) + 1;
8956 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8957
8958 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008959
8960 return mode;
8961}
8962
Jesse Barnes652c3932009-08-17 13:31:43 -07008963static void intel_decrease_pllclock(struct drm_crtc *crtc)
8964{
8965 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +03008966 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008968
Sonika Jindalbaff2962014-07-22 11:16:35 +05308969 if (!HAS_GMCH_DISPLAY(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008970 return;
8971
8972 if (!dev_priv->lvds_downclock_avail)
8973 return;
8974
8975 /*
8976 * Since this is called by a timer, we should never get here in
8977 * the manual case.
8978 */
8979 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008980 int pipe = intel_crtc->pipe;
8981 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008982 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008983
Zhao Yakui44d98a62009-10-09 11:39:40 +08008984 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008985
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008986 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008987
Chris Wilson074b5e12012-05-02 12:07:06 +01008988 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008989 dpll |= DISPLAY_RATE_SELECT_FPA1;
8990 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008991 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008992 dpll = I915_READ(dpll_reg);
8993 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008994 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008995 }
8996
8997}
8998
Chris Wilsonf047e392012-07-21 12:31:41 +01008999void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07009000{
Paulo Zanonic67a4702013-08-19 13:18:09 -03009001 struct drm_i915_private *dev_priv = dev->dev_private;
9002
Chris Wilsonf62a0072014-02-21 17:55:39 +00009003 if (dev_priv->mm.busy)
9004 return;
9005
Paulo Zanoni43694d62014-03-07 20:08:08 -03009006 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03009007 i915_update_gfx_val(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +00009008 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +01009009}
9010
9011void intel_mark_idle(struct drm_device *dev)
9012{
Paulo Zanonic67a4702013-08-19 13:18:09 -03009013 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00009014 struct drm_crtc *crtc;
9015
Chris Wilsonf62a0072014-02-21 17:55:39 +00009016 if (!dev_priv->mm.busy)
9017 return;
9018
9019 dev_priv->mm.busy = false;
9020
Jani Nikulad330a952014-01-21 11:24:25 +02009021 if (!i915.powersave)
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03009022 goto out;
Chris Wilson725a5b52013-01-08 11:02:57 +00009023
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01009024 for_each_crtc(dev, crtc) {
Matt Roperf4510a22014-04-01 15:22:40 -07009025 if (!crtc->primary->fb)
Chris Wilson725a5b52013-01-08 11:02:57 +00009026 continue;
9027
9028 intel_decrease_pllclock(crtc);
9029 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01009030
Damien Lespiau3d13ef22014-02-07 19:12:47 +00009031 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +01009032 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -03009033
9034out:
Paulo Zanoni43694d62014-03-07 20:08:08 -03009035 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01009036}
9037
Jesse Barnes79e53942008-11-07 14:24:08 -08009038static void intel_crtc_destroy(struct drm_crtc *crtc)
9039{
9040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009041 struct drm_device *dev = crtc->dev;
9042 struct intel_unpin_work *work;
Daniel Vetter67e77c52010-08-20 22:26:30 +02009043
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009044 spin_lock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009045 work = intel_crtc->unpin_work;
9046 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009047 spin_unlock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009048
9049 if (work) {
9050 cancel_work_sync(&work->work);
9051 kfree(work);
9052 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009053
9054 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02009055
Jesse Barnes79e53942008-11-07 14:24:08 -08009056 kfree(intel_crtc);
9057}
9058
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009059static void intel_unpin_work_fn(struct work_struct *__work)
9060{
9061 struct intel_unpin_work *work =
9062 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009063 struct drm_device *dev = work->crtc->dev;
Daniel Vetterf99d7062014-06-19 16:01:59 +02009064 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009065
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009066 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01009067 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00009068 drm_gem_object_unreference(&work->pending_flip_obj->base);
9069 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00009070
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009071 intel_update_fbc(dev);
9072 mutex_unlock(&dev->struct_mutex);
9073
Daniel Vetterf99d7062014-06-19 16:01:59 +02009074 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9075
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009076 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9077 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9078
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009079 kfree(work);
9080}
9081
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009082static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01009083 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009084{
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9086 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009087 unsigned long flags;
9088
9089 /* Ignore early vblank irqs */
9090 if (intel_crtc == NULL)
9091 return;
9092
Daniel Vetterf3260382014-09-15 14:55:23 +02009093 /*
9094 * This is called both by irq handlers and the reset code (to complete
9095 * lost pageflips) so needs the full irqsave spinlocks.
9096 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009097 spin_lock_irqsave(&dev->event_lock, flags);
9098 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00009099
9100 /* Ensure we don't miss a work->pending update ... */
9101 smp_rmb();
9102
9103 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009104 spin_unlock_irqrestore(&dev->event_lock, flags);
9105 return;
9106 }
9107
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009108 page_flip_completed(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01009109
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009110 spin_unlock_irqrestore(&dev->event_lock, flags);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009111}
9112
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009113void intel_finish_page_flip(struct drm_device *dev, int pipe)
9114{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009115 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009116 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9117
Mario Kleiner49b14a52010-12-09 07:00:07 +01009118 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009119}
9120
9121void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9122{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009123 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009124 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9125
Mario Kleiner49b14a52010-12-09 07:00:07 +01009126 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07009127}
9128
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009129/* Is 'a' after or equal to 'b'? */
9130static bool g4x_flip_count_after_eq(u32 a, u32 b)
9131{
9132 return !((a - b) & 0x80000000);
9133}
9134
9135static bool page_flip_finished(struct intel_crtc *crtc)
9136{
9137 struct drm_device *dev = crtc->base.dev;
9138 struct drm_i915_private *dev_priv = dev->dev_private;
9139
9140 /*
9141 * The relevant registers doen't exist on pre-ctg.
9142 * As the flip done interrupt doesn't trigger for mmio
9143 * flips on gmch platforms, a flip count check isn't
9144 * really needed there. But since ctg has the registers,
9145 * include it in the check anyway.
9146 */
9147 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9148 return true;
9149
9150 /*
9151 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9152 * used the same base address. In that case the mmio flip might
9153 * have completed, but the CS hasn't even executed the flip yet.
9154 *
9155 * A flip count check isn't enough as the CS might have updated
9156 * the base address just after start of vblank, but before we
9157 * managed to process the interrupt. This means we'd complete the
9158 * CS flip too soon.
9159 *
9160 * Combining both checks should get us a good enough result. It may
9161 * still happen that the CS flip has been executed, but has not
9162 * yet actually completed. But in case the base address is the same
9163 * anyway, we don't really care.
9164 */
9165 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9166 crtc->unpin_work->gtt_offset &&
9167 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9168 crtc->unpin_work->flip_count);
9169}
9170
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009171void intel_prepare_page_flip(struct drm_device *dev, int plane)
9172{
Jani Nikulafbee40d2014-03-31 14:27:18 +03009173 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009174 struct intel_crtc *intel_crtc =
9175 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9176 unsigned long flags;
9177
Daniel Vetterf3260382014-09-15 14:55:23 +02009178
9179 /*
9180 * This is called both by irq handlers and the reset code (to complete
9181 * lost pageflips) so needs the full irqsave spinlocks.
9182 *
9183 * NB: An MMIO update of the plane base pointer will also
Chris Wilsone7d841c2012-12-03 11:36:30 +00009184 * generate a page-flip completion irq, i.e. every modeset
9185 * is also accompanied by a spurious intel_prepare_page_flip().
9186 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009187 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009188 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +00009189 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009190 spin_unlock_irqrestore(&dev->event_lock, flags);
9191}
9192
Robin Schroereba905b2014-05-18 02:24:50 +02009193static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
Chris Wilsone7d841c2012-12-03 11:36:30 +00009194{
9195 /* Ensure that the work item is consistent when activating it ... */
9196 smp_wmb();
9197 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9198 /* and that it is marked active as soon as the irq could fire. */
9199 smp_wmb();
9200}
9201
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009202static int intel_gen2_queue_flip(struct drm_device *dev,
9203 struct drm_crtc *crtc,
9204 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009205 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009206 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009207 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009208{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009210 u32 flip_mask;
9211 int ret;
9212
Daniel Vetter6d90c952012-04-26 23:28:05 +02009213 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009214 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009215 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009216
9217 /* Can't queue multiple flips, so wait for the previous
9218 * one to finish before executing the next.
9219 */
9220 if (intel_crtc->plane)
9221 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9222 else
9223 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009224 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9225 intel_ring_emit(ring, MI_NOOP);
9226 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9227 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9228 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009229 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009230 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00009231
9232 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009233 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009234 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009235}
9236
9237static int intel_gen3_queue_flip(struct drm_device *dev,
9238 struct drm_crtc *crtc,
9239 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009240 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009241 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009242 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009243{
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009245 u32 flip_mask;
9246 int ret;
9247
Daniel Vetter6d90c952012-04-26 23:28:05 +02009248 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009249 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009250 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009251
9252 if (intel_crtc->plane)
9253 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9254 else
9255 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009256 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9257 intel_ring_emit(ring, MI_NOOP);
9258 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9259 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9260 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009261 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02009262 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009263
Chris Wilsone7d841c2012-12-03 11:36:30 +00009264 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009265 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009266 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009267}
9268
9269static int intel_gen4_queue_flip(struct drm_device *dev,
9270 struct drm_crtc *crtc,
9271 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009272 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009273 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009274 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009275{
9276 struct drm_i915_private *dev_priv = dev->dev_private;
9277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9278 uint32_t pf, pipesrc;
9279 int ret;
9280
Daniel Vetter6d90c952012-04-26 23:28:05 +02009281 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009282 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009283 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009284
9285 /* i965+ uses the linear or tiled offsets from the
9286 * Display Registers (which do not change across a page-flip)
9287 * so we need only reprogram the base address.
9288 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02009289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9291 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009292 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +02009293 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009294
9295 /* XXX Enabling the panel-fitter across page-flip is so far
9296 * untested on non-native modes, so ignore it for now.
9297 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9298 */
9299 pf = 0;
9300 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009301 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009302
9303 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009304 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009305 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009306}
9307
9308static int intel_gen6_queue_flip(struct drm_device *dev,
9309 struct drm_crtc *crtc,
9310 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009311 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009312 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009313 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009314{
9315 struct drm_i915_private *dev_priv = dev->dev_private;
9316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9317 uint32_t pf, pipesrc;
9318 int ret;
9319
Daniel Vetter6d90c952012-04-26 23:28:05 +02009320 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009321 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009322 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009323
Daniel Vetter6d90c952012-04-26 23:28:05 +02009324 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9326 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009327 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009328
Chris Wilson99d9acd2012-04-17 20:37:00 +01009329 /* Contrary to the suggestions in the documentation,
9330 * "Enable Panel Fitter" does not seem to be required when page
9331 * flipping with a non-native mode, and worse causes a normal
9332 * modeset to fail.
9333 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9334 */
9335 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009336 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02009337 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00009338
9339 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009340 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009341 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009342}
9343
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009344static int intel_gen7_queue_flip(struct drm_device *dev,
9345 struct drm_crtc *crtc,
9346 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009347 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009348 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009349 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009350{
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009352 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01009353 int len, ret;
9354
Robin Schroereba905b2014-05-18 02:24:50 +02009355 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009356 case PLANE_A:
9357 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9358 break;
9359 case PLANE_B:
9360 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9361 break;
9362 case PLANE_C:
9363 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9364 break;
9365 default:
9366 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009367 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009368 }
9369
Chris Wilsonffe74d72013-08-26 20:58:12 +01009370 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +01009371 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +01009372 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +01009373 /*
9374 * On Gen 8, SRM is now taking an extra dword to accommodate
9375 * 48bits addresses, and we need a NOOP for the batch size to
9376 * stay even.
9377 */
9378 if (IS_GEN8(dev))
9379 len += 2;
9380 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009381
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009382 /*
9383 * BSpec MI_DISPLAY_FLIP for IVB:
9384 * "The full packet must be contained within the same cache line."
9385 *
9386 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9387 * cacheline, if we ever start emitting more commands before
9388 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9389 * then do the cacheline alignment, and finally emit the
9390 * MI_DISPLAY_FLIP.
9391 */
9392 ret = intel_ring_cacheline_align(ring);
9393 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009394 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +02009395
Chris Wilsonffe74d72013-08-26 20:58:12 +01009396 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009397 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009398 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009399
Chris Wilsonffe74d72013-08-26 20:58:12 +01009400 /* Unmask the flip-done completion message. Note that the bspec says that
9401 * we should do this for both the BCS and RCS, and that we must not unmask
9402 * more than one flip event at any time (or ensure that one flip message
9403 * can be sent by waiting for flip-done prior to queueing new flips).
9404 * Experimentation says that BCS works despite DERRMR masking all
9405 * flip-done completion events and that unmasking all planes at once
9406 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9407 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9408 */
9409 if (ring->id == RCS) {
9410 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9411 intel_ring_emit(ring, DERRMR);
9412 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9413 DERRMR_PIPEB_PRI_FLIP_DONE |
9414 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +01009415 if (IS_GEN8(dev))
9416 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9417 MI_SRM_LRM_GLOBAL_GTT);
9418 else
9419 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9420 MI_SRM_LRM_GLOBAL_GTT);
Chris Wilsonffe74d72013-08-26 20:58:12 +01009421 intel_ring_emit(ring, DERRMR);
9422 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +01009423 if (IS_GEN8(dev)) {
9424 intel_ring_emit(ring, 0);
9425 intel_ring_emit(ring, MI_NOOP);
9426 }
Chris Wilsonffe74d72013-08-26 20:58:12 +01009427 }
9428
Daniel Vettercb05d8d2012-05-23 14:02:00 +02009429 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02009430 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009431 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009432 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00009433
9434 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01009435 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01009436 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009437}
9438
Sourab Gupta84c33a62014-06-02 16:47:17 +05309439static bool use_mmio_flip(struct intel_engine_cs *ring,
9440 struct drm_i915_gem_object *obj)
9441{
9442 /*
9443 * This is not being used for older platforms, because
9444 * non-availability of flip done interrupt forces us to use
9445 * CS flips. Older platforms derive flip done using some clever
9446 * tricks involving the flip_pending status bits and vblank irqs.
9447 * So using MMIO flips there would disrupt this mechanism.
9448 */
9449
Chris Wilson8e09bf82014-07-08 10:40:30 +01009450 if (ring == NULL)
9451 return true;
9452
Sourab Gupta84c33a62014-06-02 16:47:17 +05309453 if (INTEL_INFO(ring->dev)->gen < 5)
9454 return false;
9455
9456 if (i915.use_mmio_flip < 0)
9457 return false;
9458 else if (i915.use_mmio_flip > 0)
9459 return true;
Oscar Mateo14bf9932014-07-24 17:04:34 +01009460 else if (i915.enable_execlists)
9461 return true;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309462 else
9463 return ring != obj->ring;
9464}
9465
9466static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9467{
9468 struct drm_device *dev = intel_crtc->base.dev;
9469 struct drm_i915_private *dev_priv = dev->dev_private;
9470 struct intel_framebuffer *intel_fb =
9471 to_intel_framebuffer(intel_crtc->base.primary->fb);
9472 struct drm_i915_gem_object *obj = intel_fb->obj;
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009473 bool atomic_update;
9474 u32 start_vbl_count;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309475 u32 dspcntr;
9476 u32 reg;
9477
9478 intel_mark_page_flip_active(intel_crtc);
9479
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009480 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9481
Sourab Gupta84c33a62014-06-02 16:47:17 +05309482 reg = DSPCNTR(intel_crtc->plane);
9483 dspcntr = I915_READ(reg);
9484
Damien Lespiauc5d97472014-10-25 00:11:11 +01009485 if (obj->tiling_mode != I915_TILING_NONE)
9486 dspcntr |= DISPPLANE_TILED;
9487 else
9488 dspcntr &= ~DISPPLANE_TILED;
9489
Sourab Gupta84c33a62014-06-02 16:47:17 +05309490 I915_WRITE(reg, dspcntr);
9491
9492 I915_WRITE(DSPSURF(intel_crtc->plane),
9493 intel_crtc->unpin_work->gtt_offset);
9494 POSTING_READ(DSPSURF(intel_crtc->plane));
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009495
9496 if (atomic_update)
9497 intel_pipe_update_end(intel_crtc, start_vbl_count);
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009498}
9499
9500static void intel_mmio_flip_work_func(struct work_struct *work)
9501{
9502 struct intel_crtc *intel_crtc =
9503 container_of(work, struct intel_crtc, mmio_flip.work);
Ander Conselvan de Oliveira536f5b52014-11-06 11:03:40 +02009504 struct intel_engine_cs *ring;
9505 uint32_t seqno;
9506
9507 seqno = intel_crtc->mmio_flip.seqno;
9508 ring = intel_crtc->mmio_flip.ring;
9509
9510 if (seqno)
9511 WARN_ON(__i915_wait_seqno(ring, seqno,
9512 intel_crtc->reset_counter,
9513 false, NULL, NULL) != 0);
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02009514
9515 intel_do_mmio_flip(intel_crtc);
Sourab Gupta84c33a62014-06-02 16:47:17 +05309516}
9517
Sourab Gupta84c33a62014-06-02 16:47:17 +05309518static int intel_queue_mmio_flip(struct drm_device *dev,
9519 struct drm_crtc *crtc,
9520 struct drm_framebuffer *fb,
9521 struct drm_i915_gem_object *obj,
9522 struct intel_engine_cs *ring,
9523 uint32_t flags)
9524{
Sourab Gupta84c33a62014-06-02 16:47:17 +05309525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Sourab Gupta84c33a62014-06-02 16:47:17 +05309526
Sourab Gupta84c33a62014-06-02 16:47:17 +05309527 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
Ander Conselvan de Oliveira536f5b52014-11-06 11:03:40 +02009528 intel_crtc->mmio_flip.ring = obj->ring;
Sourab Gupta84c33a62014-06-02 16:47:17 +05309529
Ander Conselvan de Oliveira536f5b52014-11-06 11:03:40 +02009530 schedule_work(&intel_crtc->mmio_flip.work);
9531
Sourab Gupta84c33a62014-06-02 16:47:17 +05309532 return 0;
9533}
9534
Damien Lespiau830c81d2014-11-13 17:51:46 +00009535static int intel_gen9_queue_flip(struct drm_device *dev,
9536 struct drm_crtc *crtc,
9537 struct drm_framebuffer *fb,
9538 struct drm_i915_gem_object *obj,
9539 struct intel_engine_cs *ring,
9540 uint32_t flags)
9541{
9542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9543 uint32_t plane = 0, stride;
9544 int ret;
9545
9546 switch(intel_crtc->pipe) {
9547 case PIPE_A:
9548 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9549 break;
9550 case PIPE_B:
9551 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9552 break;
9553 case PIPE_C:
9554 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9555 break;
9556 default:
9557 WARN_ONCE(1, "unknown plane in flip command\n");
9558 return -ENODEV;
9559 }
9560
9561 switch (obj->tiling_mode) {
9562 case I915_TILING_NONE:
9563 stride = fb->pitches[0] >> 6;
9564 break;
9565 case I915_TILING_X:
9566 stride = fb->pitches[0] >> 9;
9567 break;
9568 default:
9569 WARN_ONCE(1, "unknown tiling in flip command\n");
9570 return -ENODEV;
9571 }
9572
9573 ret = intel_ring_begin(ring, 10);
9574 if (ret)
9575 return ret;
9576
9577 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9578 intel_ring_emit(ring, DERRMR);
9579 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9580 DERRMR_PIPEB_PRI_FLIP_DONE |
9581 DERRMR_PIPEC_PRI_FLIP_DONE));
9582 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9583 MI_SRM_LRM_GLOBAL_GTT);
9584 intel_ring_emit(ring, DERRMR);
9585 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9586 intel_ring_emit(ring, 0);
9587
9588 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9589 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9590 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9591
9592 intel_mark_page_flip_active(intel_crtc);
9593 __intel_ring_advance(ring);
9594
9595 return 0;
9596}
9597
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009598static int intel_default_queue_flip(struct drm_device *dev,
9599 struct drm_crtc *crtc,
9600 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009601 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009602 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -07009603 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009604{
9605 return -ENODEV;
9606}
9607
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009608static bool __intel_pageflip_stall_check(struct drm_device *dev,
9609 struct drm_crtc *crtc)
9610{
9611 struct drm_i915_private *dev_priv = dev->dev_private;
9612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9613 struct intel_unpin_work *work = intel_crtc->unpin_work;
9614 u32 addr;
9615
9616 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9617 return true;
9618
9619 if (!work->enable_stall_check)
9620 return false;
9621
9622 if (work->flip_ready_vblank == 0) {
9623 if (work->flip_queued_ring &&
9624 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9625 work->flip_queued_seqno))
9626 return false;
9627
9628 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9629 }
9630
9631 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9632 return false;
9633
9634 /* Potential stall - if we see that the flip has happened,
9635 * assume a missed interrupt. */
9636 if (INTEL_INFO(dev)->gen >= 4)
9637 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9638 else
9639 addr = I915_READ(DSPADDR(intel_crtc->plane));
9640
9641 /* There is a potential issue here with a false positive after a flip
9642 * to the same address. We could address this by checking for a
9643 * non-incrementing frame counter.
9644 */
9645 return addr == work->gtt_offset;
9646}
9647
9648void intel_check_page_flip(struct drm_device *dev, int pipe)
9649{
9650 struct drm_i915_private *dev_priv = dev->dev_private;
9651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterf3260382014-09-15 14:55:23 +02009653
9654 WARN_ON(!in_irq());
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009655
9656 if (crtc == NULL)
9657 return;
9658
Daniel Vetterf3260382014-09-15 14:55:23 +02009659 spin_lock(&dev->event_lock);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009660 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9661 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9662 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9663 page_flip_completed(intel_crtc);
9664 }
Daniel Vetterf3260382014-09-15 14:55:23 +02009665 spin_unlock(&dev->event_lock);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009666}
9667
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009668static int intel_crtc_page_flip(struct drm_crtc *crtc,
9669 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07009670 struct drm_pending_vblank_event *event,
9671 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009672{
9673 struct drm_device *dev = crtc->dev;
9674 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -07009675 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009676 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettera071fa02014-06-18 23:28:09 +02009678 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009679 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01009680 struct intel_engine_cs *ring;
Chris Wilson52e68632010-08-08 10:15:59 +01009681 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009682
Matt Roper2ff8fde2014-07-08 07:50:07 -07009683 /*
9684 * drm_mode_page_flip_ioctl() should already catch this, but double
9685 * check to be safe. In the future we may enable pageflipping from
9686 * a disabled primary plane.
9687 */
9688 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9689 return -EBUSY;
9690
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009691 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -07009692 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009693 return -EINVAL;
9694
9695 /*
9696 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9697 * Note that pitch changes could also affect these register.
9698 */
9699 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -07009700 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9701 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03009702 return -EINVAL;
9703
Chris Wilsonf900db42014-02-20 09:26:13 +00009704 if (i915_terminally_wedged(&dev_priv->gpu_error))
9705 goto out_hang;
9706
Daniel Vetterb14c5672013-09-19 12:18:32 +02009707 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009708 if (work == NULL)
9709 return -ENOMEM;
9710
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009711 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009712 work->crtc = crtc;
Matt Roper2ff8fde2014-07-08 07:50:07 -07009713 work->old_fb_obj = intel_fb_obj(old_fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009714 INIT_WORK(&work->work, intel_unpin_work_fn);
9715
Daniel Vetter87b6b102014-05-15 15:33:46 +02009716 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009717 if (ret)
9718 goto free_work;
9719
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009720 /* We borrow the event spin lock for protecting unpin_work */
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009721 spin_lock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009722 if (intel_crtc->unpin_work) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009723 /* Before declaring the flip queue wedged, check if
9724 * the hardware completed the operation behind our backs.
9725 */
9726 if (__intel_pageflip_stall_check(dev, crtc)) {
9727 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9728 page_flip_completed(intel_crtc);
9729 } else {
9730 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009731 spin_unlock_irq(&dev->event_lock);
Chris Wilson468f0b42010-05-27 13:18:13 +01009732
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009733 drm_crtc_vblank_put(crtc);
9734 kfree(work);
9735 return -EBUSY;
9736 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009737 }
9738 intel_crtc->unpin_work = work;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009739 spin_unlock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009740
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009741 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9742 flush_workqueue(dev_priv->wq);
9743
Chris Wilson79158102012-05-23 11:13:58 +01009744 ret = i915_mutex_lock_interruptible(dev);
9745 if (ret)
9746 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009747
Jesse Barnes75dfca82010-02-10 15:09:44 -08009748 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00009749 drm_gem_object_reference(&work->old_fb_obj->base);
9750 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009751
Matt Roperf4510a22014-04-01 15:22:40 -07009752 crtc->primary->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01009753
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009754 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009755
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009756 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02009757 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01009758
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009759 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Daniel Vettera071fa02014-06-18 23:28:09 +02009760 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +03009761
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009762 if (IS_VALLEYVIEW(dev)) {
9763 ring = &dev_priv->ring[BCS];
Chris Wilson8e09bf82014-07-08 10:40:30 +01009764 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9765 /* vlv: DISPLAY_FLIP fails to change tiling */
9766 ring = NULL;
Chris Wilson2a92d5b2014-07-08 10:40:29 +01009767 } else if (IS_IVYBRIDGE(dev)) {
9768 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009769 } else if (INTEL_INFO(dev)->gen >= 7) {
9770 ring = obj->ring;
9771 if (ring == NULL || ring->id != RCS)
9772 ring = &dev_priv->ring[BCS];
9773 } else {
9774 ring = &dev_priv->ring[RCS];
9775 }
9776
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00009777 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009778 if (ret)
9779 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009780
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009781 work->gtt_offset =
9782 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9783
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009784 if (use_mmio_flip(ring, obj)) {
Sourab Gupta84c33a62014-06-02 16:47:17 +05309785 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9786 page_flip_flags);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009787 if (ret)
9788 goto cleanup_unpin;
9789
9790 work->flip_queued_seqno = obj->last_write_seqno;
9791 work->flip_queued_ring = obj->ring;
9792 } else {
Sourab Gupta84c33a62014-06-02 16:47:17 +05309793 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
Chris Wilsond6bbafa2014-09-05 07:13:24 +01009794 page_flip_flags);
9795 if (ret)
9796 goto cleanup_unpin;
9797
9798 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9799 work->flip_queued_ring = ring;
9800 }
9801
9802 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9803 work->enable_stall_check = true;
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009804
Daniel Vettera071fa02014-06-18 23:28:09 +02009805 i915_gem_track_fb(work->old_fb_obj, obj,
9806 INTEL_FRONTBUFFER_PRIMARY(pipe));
9807
Chris Wilson7782de32011-07-08 12:22:41 +01009808 intel_disable_fbc(dev);
Daniel Vetterf99d7062014-06-19 16:01:59 +02009809 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009810 mutex_unlock(&dev->struct_mutex);
9811
Jesse Barnese5510fa2010-07-01 16:48:37 -07009812 trace_i915_flip_request(intel_crtc->plane, obj);
9813
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009814 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01009815
Ville Syrjälä4fa62c82014-04-15 21:41:38 +03009816cleanup_unpin:
9817 intel_unpin_fb_obj(obj);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009818cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00009819 atomic_dec(&intel_crtc->unpin_work_count);
Matt Roperf4510a22014-04-01 15:22:40 -07009820 crtc->primary->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00009821 drm_gem_object_unreference(&work->old_fb_obj->base);
9822 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01009823 mutex_unlock(&dev->struct_mutex);
9824
Chris Wilson79158102012-05-23 11:13:58 +01009825cleanup:
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009826 spin_lock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +01009827 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009828 spin_unlock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +01009829
Daniel Vetter87b6b102014-05-15 15:33:46 +02009830 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07009831free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01009832 kfree(work);
9833
Chris Wilsonf900db42014-02-20 09:26:13 +00009834 if (ret == -EIO) {
9835out_hang:
9836 intel_crtc_wait_for_pending_flips(crtc);
9837 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +01009838 if (ret == 0 && event) {
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009839 spin_lock_irq(&dev->event_lock);
Daniel Vettera071fa02014-06-18 23:28:09 +02009840 drm_send_vblank_event(dev, pipe, event);
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02009841 spin_unlock_irq(&dev->event_lock);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +01009842 }
Chris Wilsonf900db42014-02-20 09:26:13 +00009843 }
Chris Wilson96b099f2010-06-07 14:03:04 +01009844 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05009845}
9846
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009847static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009848 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9849 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009850};
9851
Daniel Vetter9a935852012-07-05 22:34:27 +02009852/**
9853 * intel_modeset_update_staged_output_state
9854 *
9855 * Updates the staged output configuration state, e.g. after we've read out the
9856 * current hw state.
9857 */
9858static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9859{
Ville Syrjälä76688512014-01-10 11:28:06 +02009860 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009861 struct intel_encoder *encoder;
9862 struct intel_connector *connector;
9863
9864 list_for_each_entry(connector, &dev->mode_config.connector_list,
9865 base.head) {
9866 connector->new_encoder =
9867 to_intel_encoder(connector->base.encoder);
9868 }
9869
Damien Lespiaub2784e12014-08-05 11:29:37 +01009870 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009871 encoder->new_crtc =
9872 to_intel_crtc(encoder->base.crtc);
9873 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009874
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009875 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009876 crtc->new_enabled = crtc->base.enabled;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +02009877
9878 if (crtc->new_enabled)
9879 crtc->new_config = &crtc->config;
9880 else
9881 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +02009882 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009883}
9884
9885/**
9886 * intel_modeset_commit_output_state
9887 *
9888 * This function copies the stage display pipe configuration to the real one.
9889 */
9890static void intel_modeset_commit_output_state(struct drm_device *dev)
9891{
Ville Syrjälä76688512014-01-10 11:28:06 +02009892 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009893 struct intel_encoder *encoder;
9894 struct intel_connector *connector;
9895
9896 list_for_each_entry(connector, &dev->mode_config.connector_list,
9897 base.head) {
9898 connector->base.encoder = &connector->new_encoder->base;
9899 }
9900
Damien Lespiaub2784e12014-08-05 11:29:37 +01009901 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009902 encoder->base.crtc = &encoder->new_crtc->base;
9903 }
Ville Syrjälä76688512014-01-10 11:28:06 +02009904
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009905 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +02009906 crtc->base.enabled = crtc->new_enabled;
9907 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009908}
9909
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009910static void
Robin Schroereba905b2014-05-18 02:24:50 +02009911connected_sink_compute_bpp(struct intel_connector *connector,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009912 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009913{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009914 int bpp = pipe_config->pipe_bpp;
9915
9916 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9917 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +03009918 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009919
9920 /* Don't use an invalid EDID bpc value */
9921 if (connector->base.display_info.bpc &&
9922 connector->base.display_info.bpc * 3 < bpp) {
9923 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9924 bpp, connector->base.display_info.bpc*3);
9925 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9926 }
9927
9928 /* Clamp bpp to 8 on screens without EDID 1.4 */
9929 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9930 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9931 bpp);
9932 pipe_config->pipe_bpp = 24;
9933 }
9934}
9935
9936static int
9937compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9938 struct drm_framebuffer *fb,
9939 struct intel_crtc_config *pipe_config)
9940{
9941 struct drm_device *dev = crtc->base.dev;
9942 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009943 int bpp;
9944
Daniel Vetterd42264b2013-03-28 16:38:08 +01009945 switch (fb->pixel_format) {
9946 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009947 bpp = 8*3; /* since we go through a colormap */
9948 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009949 case DRM_FORMAT_XRGB1555:
9950 case DRM_FORMAT_ARGB1555:
9951 /* checked in intel_framebuffer_init already */
9952 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9953 return -EINVAL;
9954 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009955 bpp = 6*3; /* min is 18bpp */
9956 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009957 case DRM_FORMAT_XBGR8888:
9958 case DRM_FORMAT_ABGR8888:
9959 /* checked in intel_framebuffer_init already */
9960 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9961 return -EINVAL;
9962 case DRM_FORMAT_XRGB8888:
9963 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009964 bpp = 8*3;
9965 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01009966 case DRM_FORMAT_XRGB2101010:
9967 case DRM_FORMAT_ARGB2101010:
9968 case DRM_FORMAT_XBGR2101010:
9969 case DRM_FORMAT_ABGR2101010:
9970 /* checked in intel_framebuffer_init already */
9971 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01009972 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009973 bpp = 10*3;
9974 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01009975 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009976 default:
9977 DRM_DEBUG_KMS("unsupported depth\n");
9978 return -EINVAL;
9979 }
9980
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009981 pipe_config->pipe_bpp = bpp;
9982
9983 /* Clamp display bpp to EDID value */
9984 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009985 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02009986 if (!connector->new_encoder ||
9987 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009988 continue;
9989
Daniel Vetter050f7ae2013-06-02 13:26:23 +02009990 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009991 }
9992
9993 return bpp;
9994}
9995
Daniel Vetter644db712013-09-19 14:53:58 +02009996static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9997{
9998 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9999 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +010010000 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +020010001 mode->crtc_hdisplay, mode->crtc_hsync_start,
10002 mode->crtc_hsync_end, mode->crtc_htotal,
10003 mode->crtc_vdisplay, mode->crtc_vsync_start,
10004 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10005}
10006
Daniel Vetterc0b03412013-05-28 12:05:54 +020010007static void intel_dump_pipe_config(struct intel_crtc *crtc,
10008 struct intel_crtc_config *pipe_config,
10009 const char *context)
10010{
10011 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10012 context, pipe_name(crtc->pipe));
10013
10014 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10015 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10016 pipe_config->pipe_bpp, pipe_config->dither);
10017 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10018 pipe_config->has_pch_encoder,
10019 pipe_config->fdi_lanes,
10020 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10021 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10022 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010023 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10024 pipe_config->has_dp_encoder,
10025 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10026 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10027 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010028
10029 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10030 pipe_config->has_dp_encoder,
10031 pipe_config->dp_m2_n2.gmch_m,
10032 pipe_config->dp_m2_n2.gmch_n,
10033 pipe_config->dp_m2_n2.link_m,
10034 pipe_config->dp_m2_n2.link_n,
10035 pipe_config->dp_m2_n2.tu);
10036
Daniel Vetterc0b03412013-05-28 12:05:54 +020010037 DRM_DEBUG_KMS("requested mode:\n");
10038 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10039 DRM_DEBUG_KMS("adjusted mode:\n");
10040 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +020010041 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +030010042 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010043 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10044 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010045 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10046 pipe_config->gmch_pfit.control,
10047 pipe_config->gmch_pfit.pgm_ratios,
10048 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010049 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +020010050 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010051 pipe_config->pch_pfit.size,
10052 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010053 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +030010054 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010055}
10056
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010057static bool encoders_cloneable(const struct intel_encoder *a,
10058 const struct intel_encoder *b)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010059{
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010060 /* masks could be asymmetric, so check both ways */
10061 return a == b || (a->cloneable & (1 << b->type) &&
10062 b->cloneable & (1 << a->type));
10063}
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010064
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010065static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10066 struct intel_encoder *encoder)
10067{
10068 struct drm_device *dev = crtc->base.dev;
10069 struct intel_encoder *source_encoder;
10070
Damien Lespiaub2784e12014-08-05 11:29:37 +010010071 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010072 if (source_encoder->new_crtc != crtc)
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010073 continue;
10074
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010075 if (!encoders_cloneable(encoder, source_encoder))
10076 return false;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010077 }
10078
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010079 return true;
10080}
10081
10082static bool check_encoder_cloning(struct intel_crtc *crtc)
10083{
10084 struct drm_device *dev = crtc->base.dev;
10085 struct intel_encoder *encoder;
10086
Damien Lespiaub2784e12014-08-05 11:29:37 +010010087 for_each_intel_encoder(dev, encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010088 if (encoder->new_crtc != crtc)
10089 continue;
10090
10091 if (!check_single_encoder_cloning(crtc, encoder))
10092 return false;
10093 }
10094
10095 return true;
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010096}
10097
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010098static struct intel_crtc_config *
10099intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010100 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010101 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +020010102{
10103 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +020010104 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010105 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +010010106 int plane_bpp, ret = -EINVAL;
10107 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020010108
Ville Syrjäläbc079e82014-03-03 16:15:28 +020010109 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
Daniel Vetteraccfc0c2013-05-30 15:04:25 +020010110 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10111 return ERR_PTR(-EINVAL);
10112 }
10113
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010114 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10115 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020010116 return ERR_PTR(-ENOMEM);
10117
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010118 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10119 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010120
Daniel Vettere143a212013-07-04 12:01:15 +020010121 pipe_config->cpu_transcoder =
10122 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010123 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010124
Imre Deak2960bc92013-07-30 13:36:32 +030010125 /*
10126 * Sanitize sync polarity flags based on requested ones. If neither
10127 * positive or negative polarity is requested, treat this as meaning
10128 * negative polarity.
10129 */
10130 if (!(pipe_config->adjusted_mode.flags &
10131 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10132 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10133
10134 if (!(pipe_config->adjusted_mode.flags &
10135 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10136 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10137
Daniel Vetter050f7ae2013-06-02 13:26:23 +020010138 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10139 * plane pixel format and any sink constraints into account. Returns the
10140 * source plane bpp so that dithering can be selected on mismatches
10141 * after encoders and crtc also have had their say. */
10142 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10143 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010144 if (plane_bpp < 0)
10145 goto fail;
10146
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030010147 /*
10148 * Determine the real pipe dimensions. Note that stereo modes can
10149 * increase the actual pipe size due to the frame doubling and
10150 * insertion of additional space for blanks between the frame. This
10151 * is stored in the crtc timings. We use the requested mode to do this
10152 * computation to clearly distinguish it from the adjusted mode, which
10153 * can be changed by the connectors in the below retry loop.
10154 */
10155 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10156 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10157 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10158
Daniel Vettere29c22c2013-02-21 00:00:16 +010010159encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020010160 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020010161 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020010162 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010163
Daniel Vetter135c81b2013-07-21 21:37:09 +020010164 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +010010165 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020010166
Daniel Vetter7758a112012-07-08 19:40:39 +020010167 /* Pass our mode to the connectors and the CRTC to give them a chance to
10168 * adjust it according to limitations or connector properties, and also
10169 * a chance to reject the mode entirely.
10170 */
Damien Lespiaub2784e12014-08-05 11:29:37 +010010171 for_each_intel_encoder(dev, encoder) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010172
10173 if (&encoder->new_crtc->base != crtc)
10174 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +010010175
Daniel Vetterefea6e82013-07-21 21:36:59 +020010176 if (!(encoder->compute_config(encoder, pipe_config))) {
10177 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020010178 goto fail;
10179 }
10180 }
10181
Daniel Vetterff9a6752013-06-01 17:16:21 +020010182 /* Set default port clock if not overwritten by the encoder. Needs to be
10183 * done afterwards in case the encoder adjusts the mode. */
10184 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +010010185 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10186 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020010187
Daniel Vettera43f6e02013-06-07 23:10:32 +020010188 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010189 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020010190 DRM_DEBUG_KMS("CRTC fixup failed\n");
10191 goto fail;
10192 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010010193
10194 if (ret == RETRY) {
10195 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10196 ret = -EINVAL;
10197 goto fail;
10198 }
10199
10200 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10201 retry = false;
10202 goto encoder_retry;
10203 }
10204
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010010205 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10206 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10207 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10208
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010209 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +020010210fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010211 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010010212 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +020010213}
10214
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010215/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10216 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10217static void
10218intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10219 unsigned *prepare_pipes, unsigned *disable_pipes)
10220{
10221 struct intel_crtc *intel_crtc;
10222 struct drm_device *dev = crtc->dev;
10223 struct intel_encoder *encoder;
10224 struct intel_connector *connector;
10225 struct drm_crtc *tmp_crtc;
10226
10227 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10228
10229 /* Check which crtcs have changed outputs connected to them, these need
10230 * to be part of the prepare_pipes mask. We don't (yet) support global
10231 * modeset across multiple crtcs, so modeset_pipes will only have one
10232 * bit set at most. */
10233 list_for_each_entry(connector, &dev->mode_config.connector_list,
10234 base.head) {
10235 if (connector->base.encoder == &connector->new_encoder->base)
10236 continue;
10237
10238 if (connector->base.encoder) {
10239 tmp_crtc = connector->base.encoder->crtc;
10240
10241 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10242 }
10243
10244 if (connector->new_encoder)
10245 *prepare_pipes |=
10246 1 << connector->new_encoder->new_crtc->pipe;
10247 }
10248
Damien Lespiaub2784e12014-08-05 11:29:37 +010010249 for_each_intel_encoder(dev, encoder) {
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010250 if (encoder->base.crtc == &encoder->new_crtc->base)
10251 continue;
10252
10253 if (encoder->base.crtc) {
10254 tmp_crtc = encoder->base.crtc;
10255
10256 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10257 }
10258
10259 if (encoder->new_crtc)
10260 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10261 }
10262
Ville Syrjälä76688512014-01-10 11:28:06 +020010263 /* Check for pipes that will be enabled/disabled ... */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010264 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010265 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010266 continue;
10267
Ville Syrjälä76688512014-01-10 11:28:06 +020010268 if (!intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010269 *disable_pipes |= 1 << intel_crtc->pipe;
Ville Syrjälä76688512014-01-10 11:28:06 +020010270 else
10271 *prepare_pipes |= 1 << intel_crtc->pipe;
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010272 }
10273
10274
10275 /* set_mode is also used to update properties on life display pipes. */
10276 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä76688512014-01-10 11:28:06 +020010277 if (intel_crtc->new_enabled)
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010278 *prepare_pipes |= 1 << intel_crtc->pipe;
10279
Daniel Vetterb6c51642013-04-12 18:48:43 +020010280 /*
10281 * For simplicity do a full modeset on any pipe where the output routing
10282 * changed. We could be more clever, but that would require us to be
10283 * more careful with calling the relevant encoder->mode_set functions.
10284 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010285 if (*prepare_pipes)
10286 *modeset_pipes = *prepare_pipes;
10287
10288 /* ... and mask these out. */
10289 *modeset_pipes &= ~(*disable_pipes);
10290 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +020010291
10292 /*
10293 * HACK: We don't (yet) fully support global modesets. intel_set_config
10294 * obies this rule, but the modeset restore mode of
10295 * intel_modeset_setup_hw_state does not.
10296 */
10297 *modeset_pipes &= 1 << intel_crtc->pipe;
10298 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +020010299
10300 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10301 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +020010302}
10303
Daniel Vetterea9d7582012-07-10 10:42:52 +020010304static bool intel_crtc_in_use(struct drm_crtc *crtc)
10305{
10306 struct drm_encoder *encoder;
10307 struct drm_device *dev = crtc->dev;
10308
10309 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10310 if (encoder->crtc == crtc)
10311 return true;
10312
10313 return false;
10314}
10315
10316static void
10317intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10318{
Daniel Vetterba41c0de2014-11-03 15:04:55 +010010319 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterea9d7582012-07-10 10:42:52 +020010320 struct intel_encoder *intel_encoder;
10321 struct intel_crtc *intel_crtc;
10322 struct drm_connector *connector;
10323
Daniel Vetterba41c0de2014-11-03 15:04:55 +010010324 intel_shared_dpll_commit(dev_priv);
10325
Damien Lespiaub2784e12014-08-05 11:29:37 +010010326 for_each_intel_encoder(dev, intel_encoder) {
Daniel Vetterea9d7582012-07-10 10:42:52 +020010327 if (!intel_encoder->base.crtc)
10328 continue;
10329
10330 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10331
10332 if (prepare_pipes & (1 << intel_crtc->pipe))
10333 intel_encoder->connectors_active = false;
10334 }
10335
10336 intel_modeset_commit_output_state(dev);
10337
Ville Syrjälä76688512014-01-10 11:28:06 +020010338 /* Double check state. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010339 for_each_intel_crtc(dev, intel_crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020010340 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020010341 WARN_ON(intel_crtc->new_config &&
10342 intel_crtc->new_config != &intel_crtc->config);
10343 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010344 }
10345
10346 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10347 if (!connector->encoder || !connector->encoder->crtc)
10348 continue;
10349
10350 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10351
10352 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +020010353 struct drm_property *dpms_property =
10354 dev->mode_config.dpms_property;
10355
Daniel Vetterea9d7582012-07-10 10:42:52 +020010356 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -050010357 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +020010358 dpms_property,
10359 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +020010360
10361 intel_encoder = to_intel_encoder(connector->encoder);
10362 intel_encoder->connectors_active = true;
10363 }
10364 }
10365
10366}
10367
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010368static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010369{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030010370 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010371
10372 if (clock1 == clock2)
10373 return true;
10374
10375 if (!clock1 || !clock2)
10376 return false;
10377
10378 diff = abs(clock1 - clock2);
10379
10380 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10381 return true;
10382
10383 return false;
10384}
10385
Daniel Vetter25c5b262012-07-08 22:08:04 +020010386#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10387 list_for_each_entry((intel_crtc), \
10388 &(dev)->mode_config.crtc_list, \
10389 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +020010390 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020010391
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010392static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010393intel_pipe_config_compare(struct drm_device *dev,
10394 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010395 struct intel_crtc_config *pipe_config)
10396{
Daniel Vetter66e985c2013-06-05 13:34:20 +020010397#define PIPE_CONF_CHECK_X(name) \
10398 if (current_config->name != pipe_config->name) { \
10399 DRM_ERROR("mismatch in " #name " " \
10400 "(expected 0x%08x, found 0x%08x)\n", \
10401 current_config->name, \
10402 pipe_config->name); \
10403 return false; \
10404 }
10405
Daniel Vetter08a24032013-04-19 11:25:34 +020010406#define PIPE_CONF_CHECK_I(name) \
10407 if (current_config->name != pipe_config->name) { \
10408 DRM_ERROR("mismatch in " #name " " \
10409 "(expected %i, found %i)\n", \
10410 current_config->name, \
10411 pipe_config->name); \
10412 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010010413 }
10414
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010415/* This is required for BDW+ where there is only one set of registers for
10416 * switching between high and low RR.
10417 * This macro can be used whenever a comparison has to be made between one
10418 * hw state and multiple sw state variables.
10419 */
10420#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10421 if ((current_config->name != pipe_config->name) && \
10422 (current_config->alt_name != pipe_config->name)) { \
10423 DRM_ERROR("mismatch in " #name " " \
10424 "(expected %i or %i, found %i)\n", \
10425 current_config->name, \
10426 current_config->alt_name, \
10427 pipe_config->name); \
10428 return false; \
10429 }
10430
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010431#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10432 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -070010433 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010434 "(expected %i, found %i)\n", \
10435 current_config->name & (mask), \
10436 pipe_config->name & (mask)); \
10437 return false; \
10438 }
10439
Ville Syrjälä5e550652013-09-06 23:29:07 +030010440#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10441 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10442 DRM_ERROR("mismatch in " #name " " \
10443 "(expected %i, found %i)\n", \
10444 current_config->name, \
10445 pipe_config->name); \
10446 return false; \
10447 }
10448
Daniel Vetterbb760062013-06-06 14:55:52 +020010449#define PIPE_CONF_QUIRK(quirk) \
10450 ((current_config->quirks | pipe_config->quirks) & (quirk))
10451
Daniel Vettereccb1402013-05-22 00:50:22 +020010452 PIPE_CONF_CHECK_I(cpu_transcoder);
10453
Daniel Vetter08a24032013-04-19 11:25:34 +020010454 PIPE_CONF_CHECK_I(has_pch_encoder);
10455 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +020010456 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10457 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10458 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10459 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10460 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +020010461
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010462 PIPE_CONF_CHECK_I(has_dp_encoder);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010463
10464 if (INTEL_INFO(dev)->gen < 8) {
10465 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10466 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10467 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10468 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10469 PIPE_CONF_CHECK_I(dp_m_n.tu);
10470
10471 if (current_config->has_drrs) {
10472 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10473 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10474 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10475 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10476 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10477 }
10478 } else {
10479 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10480 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10481 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10482 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10483 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10484 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030010485
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010486 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10487 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10488 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10489 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10490 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10491 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10492
10493 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10494 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10495 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10496 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10497 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10498 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10499
Daniel Vetterc93f54c2013-06-27 19:47:19 +020010500 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +020010501 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020010502 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10503 IS_VALLEYVIEW(dev))
10504 PIPE_CONF_CHECK_I(limited_color_range);
Jesse Barnese43823e2014-11-05 14:26:08 -080010505 PIPE_CONF_CHECK_I(has_infoframe);
Daniel Vetter6c49f242013-06-06 12:45:25 +020010506
Daniel Vetter9ed109a2014-04-24 23:54:52 +020010507 PIPE_CONF_CHECK_I(has_audio);
10508
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010509 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10510 DRM_MODE_FLAG_INTERLACE);
10511
Daniel Vetterbb760062013-06-06 14:55:52 +020010512 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10513 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10514 DRM_MODE_FLAG_PHSYNC);
10515 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10516 DRM_MODE_FLAG_NHSYNC);
10517 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10518 DRM_MODE_FLAG_PVSYNC);
10519 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10520 DRM_MODE_FLAG_NVSYNC);
10521 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010522
Ville Syrjälä37327ab2013-09-04 18:25:28 +030010523 PIPE_CONF_CHECK_I(pipe_src_w);
10524 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010525
Daniel Vetter99535992014-04-13 12:00:33 +020010526 /*
10527 * FIXME: BIOS likes to set up a cloned config with lvds+external
10528 * screen. Since we don't yet re-compute the pipe config when moving
10529 * just the lvds port away to another pipe the sw tracking won't match.
10530 *
10531 * Proper atomic modesets with recomputed global state will fix this.
10532 * Until then just don't check gmch state for inherited modes.
10533 */
10534 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10535 PIPE_CONF_CHECK_I(gmch_pfit.control);
10536 /* pfit ratios are autocomputed by the hw on gen4+ */
10537 if (INTEL_INFO(dev)->gen < 4)
10538 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10539 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10540 }
10541
Chris Wilsonfd4daa92013-08-27 17:04:17 +010010542 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10543 if (current_config->pch_pfit.enabled) {
10544 PIPE_CONF_CHECK_I(pch_pfit.pos);
10545 PIPE_CONF_CHECK_I(pch_pfit.size);
10546 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010547
Jesse Barnese59150d2014-01-07 13:30:45 -080010548 /* BDW+ don't expose a synchronous way to read the state */
10549 if (IS_HASWELL(dev))
10550 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010551
Ville Syrjälä282740f2013-09-04 18:30:03 +030010552 PIPE_CONF_CHECK_I(double_wide);
10553
Daniel Vetter26804af2014-06-25 22:01:55 +030010554 PIPE_CONF_CHECK_X(ddi_pll_sel);
10555
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010556 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010557 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020010558 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010559 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10560 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030010561 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Damien Lespiau3f4cd192014-11-13 14:55:21 +000010562 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10563 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10564 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020010565
Ville Syrjälä42571ae2013-09-06 23:29:00 +030010566 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10567 PIPE_CONF_CHECK_I(pipe_bpp);
10568
Jesse Barnesa9a7e982014-01-20 14:18:04 -080010569 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10570 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030010571
Daniel Vetter66e985c2013-06-05 13:34:20 +020010572#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020010573#undef PIPE_CONF_CHECK_I
Vandana Kannanb95af8b2014-08-05 07:51:23 -070010574#undef PIPE_CONF_CHECK_I_ALT
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010575#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030010576#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020010577#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010578
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010579 return true;
10580}
10581
Damien Lespiau08db6652014-11-04 17:06:52 +000010582static void check_wm_state(struct drm_device *dev)
10583{
10584 struct drm_i915_private *dev_priv = dev->dev_private;
10585 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10586 struct intel_crtc *intel_crtc;
10587 int plane;
10588
10589 if (INTEL_INFO(dev)->gen < 9)
10590 return;
10591
10592 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10593 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10594
10595 for_each_intel_crtc(dev, intel_crtc) {
10596 struct skl_ddb_entry *hw_entry, *sw_entry;
10597 const enum pipe pipe = intel_crtc->pipe;
10598
10599 if (!intel_crtc->active)
10600 continue;
10601
10602 /* planes */
10603 for_each_plane(pipe, plane) {
10604 hw_entry = &hw_ddb.plane[pipe][plane];
10605 sw_entry = &sw_ddb->plane[pipe][plane];
10606
10607 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10608 continue;
10609
10610 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10611 "(expected (%u,%u), found (%u,%u))\n",
10612 pipe_name(pipe), plane + 1,
10613 sw_entry->start, sw_entry->end,
10614 hw_entry->start, hw_entry->end);
10615 }
10616
10617 /* cursor */
10618 hw_entry = &hw_ddb.cursor[pipe];
10619 sw_entry = &sw_ddb->cursor[pipe];
10620
10621 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10622 continue;
10623
10624 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10625 "(expected (%u,%u), found (%u,%u))\n",
10626 pipe_name(pipe),
10627 sw_entry->start, sw_entry->end,
10628 hw_entry->start, hw_entry->end);
10629 }
10630}
10631
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010632static void
10633check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010634{
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010635 struct intel_connector *connector;
10636
10637 list_for_each_entry(connector, &dev->mode_config.connector_list,
10638 base.head) {
10639 /* This also checks the encoder/connector hw state with the
10640 * ->get_hw_state callbacks. */
10641 intel_connector_check_state(connector);
10642
10643 WARN(&connector->new_encoder->base != connector->base.encoder,
10644 "connector's staged encoder doesn't match current encoder\n");
10645 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010646}
10647
10648static void
10649check_encoder_state(struct drm_device *dev)
10650{
10651 struct intel_encoder *encoder;
10652 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010653
Damien Lespiaub2784e12014-08-05 11:29:37 +010010654 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010655 bool enabled = false;
10656 bool active = false;
10657 enum pipe pipe, tracked_pipe;
10658
10659 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10660 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030010661 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010662
10663 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10664 "encoder's stage crtc doesn't match current crtc\n");
10665 WARN(encoder->connectors_active && !encoder->base.crtc,
10666 "encoder's active_connectors set, but no crtc\n");
10667
10668 list_for_each_entry(connector, &dev->mode_config.connector_list,
10669 base.head) {
10670 if (connector->base.encoder != &encoder->base)
10671 continue;
10672 enabled = true;
10673 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10674 active = true;
10675 }
Dave Airlie0e32b392014-05-02 14:02:48 +100010676 /*
10677 * for MST connectors if we unplug the connector is gone
10678 * away but the encoder is still connected to a crtc
10679 * until a modeset happens in response to the hotplug.
10680 */
10681 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10682 continue;
10683
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010684 WARN(!!encoder->base.crtc != enabled,
10685 "encoder's enabled state mismatch "
10686 "(expected %i, found %i)\n",
10687 !!encoder->base.crtc, enabled);
10688 WARN(active && !encoder->base.crtc,
10689 "active encoder with no crtc\n");
10690
10691 WARN(encoder->connectors_active != active,
10692 "encoder's computed active state doesn't match tracked active state "
10693 "(expected %i, found %i)\n", active, encoder->connectors_active);
10694
10695 active = encoder->get_hw_state(encoder, &pipe);
10696 WARN(active != encoder->connectors_active,
10697 "encoder's hw state doesn't match sw tracking "
10698 "(expected %i, found %i)\n",
10699 encoder->connectors_active, active);
10700
10701 if (!encoder->base.crtc)
10702 continue;
10703
10704 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10705 WARN(active && pipe != tracked_pipe,
10706 "active encoder's pipe doesn't match"
10707 "(expected %i, found %i)\n",
10708 tracked_pipe, pipe);
10709
10710 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010711}
10712
10713static void
10714check_crtc_state(struct drm_device *dev)
10715{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010716 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010717 struct intel_crtc *crtc;
10718 struct intel_encoder *encoder;
10719 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010720
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010721 for_each_intel_crtc(dev, crtc) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010722 bool enabled = false;
10723 bool active = false;
10724
Jesse Barnes045ac3b2013-05-14 17:08:26 -070010725 memset(&pipe_config, 0, sizeof(pipe_config));
10726
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010727 DRM_DEBUG_KMS("[CRTC:%d]\n",
10728 crtc->base.base.id);
10729
10730 WARN(crtc->active && !crtc->base.enabled,
10731 "active crtc, but not enabled in sw tracking\n");
10732
Damien Lespiaub2784e12014-08-05 11:29:37 +010010733 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010734 if (encoder->base.crtc != &crtc->base)
10735 continue;
10736 enabled = true;
10737 if (encoder->connectors_active)
10738 active = true;
10739 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010740
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010741 WARN(active != crtc->active,
10742 "crtc's computed active state doesn't match tracked active state "
10743 "(expected %i, found %i)\n", active, crtc->active);
10744 WARN(enabled != crtc->base.enabled,
10745 "crtc's computed enabled state doesn't match tracked enabled state "
10746 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10747
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010748 active = dev_priv->display.get_pipe_config(crtc,
10749 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +020010750
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030010751 /* hw state is inconsistent with the pipe quirk */
10752 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10753 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetterd62cf622013-05-29 10:41:29 +020010754 active = crtc->active;
10755
Damien Lespiaub2784e12014-08-05 11:29:37 +010010756 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +030010757 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +020010758 if (encoder->base.crtc != &crtc->base)
10759 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +010010760 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +020010761 encoder->get_config(encoder, &pipe_config);
10762 }
10763
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010764 WARN(crtc->active != active,
10765 "crtc active state doesn't match with hw state "
10766 "(expected %i, found %i)\n", crtc->active, active);
10767
Daniel Vetterc0b03412013-05-28 12:05:54 +020010768 if (active &&
10769 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10770 WARN(1, "pipe state doesn't match!\n");
10771 intel_dump_pipe_config(crtc, &pipe_config,
10772 "[hw state]");
10773 intel_dump_pipe_config(crtc, &crtc->config,
10774 "[sw state]");
10775 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010776 }
10777}
10778
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010779static void
10780check_shared_dpll_state(struct drm_device *dev)
10781{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010782 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010783 struct intel_crtc *crtc;
10784 struct intel_dpll_hw_state dpll_hw_state;
10785 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020010786
10787 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10788 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10789 int enabled_crtcs = 0, active_crtcs = 0;
10790 bool active;
10791
10792 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10793
10794 DRM_DEBUG_KMS("%s\n", pll->name);
10795
10796 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10797
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010798 WARN(pll->active > hweight32(pll->config.crtc_mask),
Daniel Vetter53589012013-06-05 13:34:16 +020010799 "more active pll users than references: %i vs %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010800 pll->active, hweight32(pll->config.crtc_mask));
Daniel Vetter53589012013-06-05 13:34:16 +020010801 WARN(pll->active && !pll->on,
10802 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +020010803 WARN(pll->on && !pll->active,
10804 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010805 WARN(pll->on != active,
10806 "pll on state mismatch (expected %i, found %i)\n",
10807 pll->on, active);
10808
Damien Lespiaud3fcc802014-05-13 23:32:22 +010010809 for_each_intel_crtc(dev, crtc) {
Daniel Vetter53589012013-06-05 13:34:16 +020010810 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10811 enabled_crtcs++;
10812 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10813 active_crtcs++;
10814 }
10815 WARN(pll->active != active_crtcs,
10816 "pll active crtcs mismatch (expected %i, found %i)\n",
10817 pll->active, active_crtcs);
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010818 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
Daniel Vetter53589012013-06-05 13:34:16 +020010819 "pll enabled crtcs mismatch (expected %i, found %i)\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010820 hweight32(pll->config.crtc_mask), enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020010821
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020010822 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
Daniel Vetter66e985c2013-06-05 13:34:20 +020010823 sizeof(dpll_hw_state)),
10824 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020010825 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010826}
10827
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010828void
10829intel_modeset_check_state(struct drm_device *dev)
10830{
Damien Lespiau08db6652014-11-04 17:06:52 +000010831 check_wm_state(dev);
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020010832 check_connector_state(dev);
10833 check_encoder_state(dev);
10834 check_crtc_state(dev);
10835 check_shared_dpll_state(dev);
10836}
10837
Ville Syrjälä18442d02013-09-13 16:00:08 +030010838void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10839 int dotclock)
10840{
10841 /*
10842 * FDI already provided one idea for the dotclock.
10843 * Yell if the encoder disagrees.
10844 */
Damien Lespiau241bfc32013-09-25 16:45:37 +010010845 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030010846 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +010010847 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030010848}
10849
Ville Syrjälä80715b22014-05-15 20:23:23 +030010850static void update_scanline_offset(struct intel_crtc *crtc)
10851{
10852 struct drm_device *dev = crtc->base.dev;
10853
10854 /*
10855 * The scanline counter increments at the leading edge of hsync.
10856 *
10857 * On most platforms it starts counting from vtotal-1 on the
10858 * first active line. That means the scanline counter value is
10859 * always one less than what we would expect. Ie. just after
10860 * start of vblank, which also occurs at start of hsync (on the
10861 * last active line), the scanline counter will read vblank_start-1.
10862 *
10863 * On gen2 the scanline counter starts counting from 1 instead
10864 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10865 * to keep the value positive), instead of adding one.
10866 *
10867 * On HSW+ the behaviour of the scanline counter depends on the output
10868 * type. For DP ports it behaves like most other platforms, but on HDMI
10869 * there's an extra 1 line difference. So we need to add two instead of
10870 * one to the value.
10871 */
10872 if (IS_GEN2(dev)) {
10873 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10874 int vtotal;
10875
10876 vtotal = mode->crtc_vtotal;
10877 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10878 vtotal /= 2;
10879
10880 crtc->scanline_offset = vtotal - 1;
10881 } else if (HAS_DDI(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +030010882 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
Ville Syrjälä80715b22014-05-15 20:23:23 +030010883 crtc->scanline_offset = 2;
10884 } else
10885 crtc->scanline_offset = 1;
10886}
10887
Jesse Barnes7f271262014-11-05 14:26:06 -080010888static struct intel_crtc_config *
10889intel_modeset_compute_config(struct drm_crtc *crtc,
10890 struct drm_display_mode *mode,
10891 struct drm_framebuffer *fb,
10892 unsigned *modeset_pipes,
10893 unsigned *prepare_pipes,
10894 unsigned *disable_pipes)
10895{
10896 struct intel_crtc_config *pipe_config = NULL;
10897
10898 intel_modeset_affected_pipes(crtc, modeset_pipes,
10899 prepare_pipes, disable_pipes);
10900
10901 if ((*modeset_pipes) == 0)
10902 goto out;
10903
10904 /*
10905 * Note this needs changes when we start tracking multiple modes
10906 * and crtcs. At that point we'll need to compute the whole config
10907 * (i.e. one pipe_config for each crtc) rather than just the one
10908 * for this crtc.
10909 */
10910 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10911 if (IS_ERR(pipe_config)) {
10912 goto out;
10913 }
10914 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10915 "[modeset]");
10916 to_intel_crtc(crtc)->new_config = pipe_config;
10917
10918out:
10919 return pipe_config;
10920}
10921
Daniel Vetterf30da182013-04-11 20:22:50 +020010922static int __intel_set_mode(struct drm_crtc *crtc,
10923 struct drm_display_mode *mode,
Jesse Barnes7f271262014-11-05 14:26:06 -080010924 int x, int y, struct drm_framebuffer *fb,
10925 struct intel_crtc_config *pipe_config,
10926 unsigned modeset_pipes,
10927 unsigned prepare_pipes,
10928 unsigned disable_pipes)
Daniel Vettera6778b32012-07-02 09:56:42 +020010929{
10930 struct drm_device *dev = crtc->dev;
Jani Nikulafbee40d2014-03-31 14:27:18 +030010931 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010932 struct drm_display_mode *saved_mode;
Daniel Vetter25c5b262012-07-08 22:08:04 +020010933 struct intel_crtc *intel_crtc;
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010934 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020010935
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030010936 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010937 if (!saved_mode)
10938 return -ENOMEM;
Daniel Vettera6778b32012-07-02 09:56:42 +020010939
Tim Gardner3ac18232012-12-07 07:54:26 -070010940 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020010941
Jesse Barnes30a970c2013-11-04 13:48:12 -080010942 /*
10943 * See if the config requires any additional preparation, e.g.
10944 * to adjust global state with pipes off. We need to do this
10945 * here so we can get the modeset_pipe updated config for the new
10946 * mode set on this crtc. For other crtcs we need to use the
10947 * adjusted_mode bits in the crtc directly.
10948 */
Ville Syrjäläc164f832013-11-05 22:34:12 +020010949 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2f2d7aa2014-01-10 11:28:08 +020010950 valleyview_modeset_global_pipes(dev, &prepare_pipes);
Jesse Barnes30a970c2013-11-04 13:48:12 -080010951
Ville Syrjäläc164f832013-11-05 22:34:12 +020010952 /* may have added more to prepare_pipes than we should */
10953 prepare_pipes &= ~disable_pipes;
10954 }
10955
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +020010956 if (dev_priv->display.crtc_compute_clock) {
10957 unsigned clear_pipes = modeset_pipes | disable_pipes;
10958
10959 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10960 if (ret)
10961 goto done;
10962
10963 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10964 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10965 if (ret) {
10966 intel_shared_dpll_abort_config(dev_priv);
10967 goto done;
10968 }
10969 }
10970 }
10971
Daniel Vetter460da9162013-03-27 00:44:51 +010010972 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10973 intel_crtc_disable(&intel_crtc->base);
10974
Daniel Vetterea9d7582012-07-10 10:42:52 +020010975 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10976 if (intel_crtc->base.enabled)
10977 dev_priv->display.crtc_disable(&intel_crtc->base);
10978 }
Daniel Vettera6778b32012-07-02 09:56:42 +020010979
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010980 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10981 * to set it here already despite that we pass it down the callchain.
Jesse Barnes7f271262014-11-05 14:26:06 -080010982 *
10983 * Note we'll need to fix this up when we start tracking multiple
10984 * pipes; here we assume a single modeset_pipe and only track the
10985 * single crtc and mode.
Daniel Vetter6c4c86f2012-09-10 21:58:30 +020010986 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010987 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +020010988 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010010989 /* mode_set/enable/disable functions rely on a correct pipe
10990 * config. */
10991 to_intel_crtc(crtc)->config = *pipe_config;
Ville Syrjälä50741ab2014-01-10 11:28:07 +020010992 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
Ville Syrjäläc326c0a2013-10-28 12:53:41 +020010993
10994 /*
10995 * Calculate and store various constants which
10996 * are later needed by vblank and swap-completion
10997 * timestamping. They are derived from true hwmode.
10998 */
10999 drm_calc_timestamping_constants(crtc,
11000 &pipe_config->adjusted_mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010011001 }
Daniel Vetter7758a112012-07-08 19:40:39 +020011002
Daniel Vetterea9d7582012-07-10 10:42:52 +020011003 /* Only after disabling all output pipelines that will be changed can we
11004 * update the the output configuration. */
11005 intel_modeset_update_state(dev, prepare_pipes);
11006
Ville Syrjälä50f6e502014-11-06 14:49:12 +020011007 modeset_update_crtc_power_domains(dev);
Daniel Vetter47fab732012-10-26 10:58:18 +020011008
Daniel Vettera6778b32012-07-02 09:56:42 +020011009 /* Set up the DPLL and any encoders state that needs to adjust or depend
11010 * on the DPLL.
11011 */
Daniel Vetter25c5b262012-07-08 22:08:04 +020011012 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070011013 struct drm_framebuffer *old_fb = crtc->primary->fb;
11014 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11015 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Daniel Vetter4c107942014-04-24 23:55:05 +020011016
11017 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +000011018 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
Daniel Vetter4c107942014-04-24 23:55:05 +020011019 if (ret != 0) {
11020 DRM_ERROR("pin & fence failed\n");
11021 mutex_unlock(&dev->struct_mutex);
11022 goto done;
11023 }
Matt Roper2ff8fde2014-07-08 07:50:07 -070011024 if (old_fb)
Daniel Vettera071fa02014-06-18 23:28:09 +020011025 intel_unpin_fb_obj(old_obj);
Daniel Vettera071fa02014-06-18 23:28:09 +020011026 i915_gem_track_fb(old_obj, obj,
11027 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Daniel Vetter4c107942014-04-24 23:55:05 +020011028 mutex_unlock(&dev->struct_mutex);
11029
11030 crtc->primary->fb = fb;
11031 crtc->x = x;
11032 crtc->y = y;
Daniel Vettera6778b32012-07-02 09:56:42 +020011033 }
11034
11035 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ville Syrjälä80715b22014-05-15 20:23:23 +030011036 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11037 update_scanline_offset(intel_crtc);
11038
Daniel Vetter25c5b262012-07-08 22:08:04 +020011039 dev_priv->display.crtc_enable(&intel_crtc->base);
Ville Syrjälä80715b22014-05-15 20:23:23 +030011040 }
Daniel Vettera6778b32012-07-02 09:56:42 +020011041
Daniel Vettera6778b32012-07-02 09:56:42 +020011042 /* FIXME: add subpixel order */
11043done:
Ville Syrjälä4b4b9232013-10-26 17:59:30 +030011044 if (ret && crtc->enabled)
Tim Gardner3ac18232012-12-07 07:54:26 -070011045 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +020011046
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010011047 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -070011048 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +020011049 return ret;
11050}
11051
Jesse Barnes7f271262014-11-05 14:26:06 -080011052static int intel_set_mode_pipes(struct drm_crtc *crtc,
11053 struct drm_display_mode *mode,
11054 int x, int y, struct drm_framebuffer *fb,
11055 struct intel_crtc_config *pipe_config,
11056 unsigned modeset_pipes,
11057 unsigned prepare_pipes,
11058 unsigned disable_pipes)
11059{
11060 int ret;
11061
11062 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11063 prepare_pipes, disable_pipes);
11064
11065 if (ret == 0)
11066 intel_modeset_check_state(crtc->dev);
11067
11068 return ret;
11069}
11070
Damien Lespiaue7457a92013-08-08 22:28:59 +010011071static int intel_set_mode(struct drm_crtc *crtc,
11072 struct drm_display_mode *mode,
11073 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +020011074{
Jesse Barnes7f271262014-11-05 14:26:06 -080011075 struct intel_crtc_config *pipe_config;
11076 unsigned modeset_pipes, prepare_pipes, disable_pipes;
Daniel Vetterf30da182013-04-11 20:22:50 +020011077
Jesse Barnes7f271262014-11-05 14:26:06 -080011078 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11079 &modeset_pipes,
11080 &prepare_pipes,
11081 &disable_pipes);
Daniel Vetterf30da182013-04-11 20:22:50 +020011082
Jesse Barnes7f271262014-11-05 14:26:06 -080011083 if (IS_ERR(pipe_config))
11084 return PTR_ERR(pipe_config);
Daniel Vetterf30da182013-04-11 20:22:50 +020011085
Jesse Barnes7f271262014-11-05 14:26:06 -080011086 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11087 modeset_pipes, prepare_pipes,
11088 disable_pipes);
Daniel Vetterf30da182013-04-11 20:22:50 +020011089}
11090
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011091void intel_crtc_restore_mode(struct drm_crtc *crtc)
11092{
Matt Roperf4510a22014-04-01 15:22:40 -070011093 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000011094}
11095
Daniel Vetter25c5b262012-07-08 22:08:04 +020011096#undef for_each_intel_crtc_masked
11097
Daniel Vetterd9e55602012-07-04 22:16:09 +020011098static void intel_set_config_free(struct intel_set_config *config)
11099{
11100 if (!config)
11101 return;
11102
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011103 kfree(config->save_connector_encoders);
11104 kfree(config->save_encoder_crtcs);
Ville Syrjälä76688512014-01-10 11:28:06 +020011105 kfree(config->save_crtc_enabled);
Daniel Vetterd9e55602012-07-04 22:16:09 +020011106 kfree(config);
11107}
11108
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011109static int intel_set_config_save_state(struct drm_device *dev,
11110 struct intel_set_config *config)
11111{
Ville Syrjälä76688512014-01-10 11:28:06 +020011112 struct drm_crtc *crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011113 struct drm_encoder *encoder;
11114 struct drm_connector *connector;
11115 int count;
11116
Ville Syrjälä76688512014-01-10 11:28:06 +020011117 config->save_crtc_enabled =
11118 kcalloc(dev->mode_config.num_crtc,
11119 sizeof(bool), GFP_KERNEL);
11120 if (!config->save_crtc_enabled)
11121 return -ENOMEM;
11122
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011123 config->save_encoder_crtcs =
11124 kcalloc(dev->mode_config.num_encoder,
11125 sizeof(struct drm_crtc *), GFP_KERNEL);
11126 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011127 return -ENOMEM;
11128
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011129 config->save_connector_encoders =
11130 kcalloc(dev->mode_config.num_connector,
11131 sizeof(struct drm_encoder *), GFP_KERNEL);
11132 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011133 return -ENOMEM;
11134
11135 /* Copy data. Note that driver private data is not affected.
11136 * Should anything bad happen only the expected state is
11137 * restored, not the drivers personal bookkeeping.
11138 */
11139 count = 0;
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010011140 for_each_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011141 config->save_crtc_enabled[count++] = crtc->enabled;
11142 }
11143
11144 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011145 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011146 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011147 }
11148
11149 count = 0;
11150 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +020011151 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011152 }
11153
11154 return 0;
11155}
11156
11157static void intel_set_config_restore_state(struct drm_device *dev,
11158 struct intel_set_config *config)
11159{
Ville Syrjälä76688512014-01-10 11:28:06 +020011160 struct intel_crtc *crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +020011161 struct intel_encoder *encoder;
11162 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011163 int count;
11164
11165 count = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011166 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011167 crtc->new_enabled = config->save_crtc_enabled[count++];
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011168
11169 if (crtc->new_enabled)
11170 crtc->new_config = &crtc->config;
11171 else
11172 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011173 }
11174
11175 count = 0;
Damien Lespiaub2784e12014-08-05 11:29:37 +010011176 for_each_intel_encoder(dev, encoder) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011177 encoder->new_crtc =
11178 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011179 }
11180
11181 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011182 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11183 connector->new_encoder =
11184 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +020011185 }
11186}
11187
Imre Deake3de42b2013-05-03 19:44:07 +020011188static bool
Chris Wilson2e57f472013-07-17 12:14:40 +010011189is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +020011190{
11191 int i;
11192
Chris Wilson2e57f472013-07-17 12:14:40 +010011193 if (set->num_connectors == 0)
11194 return false;
11195
11196 if (WARN_ON(set->connectors == NULL))
11197 return false;
11198
11199 for (i = 0; i < set->num_connectors; i++)
11200 if (set->connectors[i]->encoder &&
11201 set->connectors[i]->encoder->crtc == set->crtc &&
11202 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +020011203 return true;
11204
11205 return false;
11206}
11207
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011208static void
11209intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11210 struct intel_set_config *config)
11211{
11212
11213 /* We should be able to check here if the fb has the same properties
11214 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +010011215 if (is_crtc_connector_off(set)) {
11216 config->mode_changed = true;
Matt Roperf4510a22014-04-01 15:22:40 -070011217 } else if (set->crtc->primary->fb != set->fb) {
Matt Roper3b150f02014-05-29 08:06:53 -070011218 /*
11219 * If we have no fb, we can only flip as long as the crtc is
11220 * active, otherwise we need a full mode set. The crtc may
11221 * be active if we've only disabled the primary plane, or
11222 * in fastboot situations.
11223 */
Matt Roperf4510a22014-04-01 15:22:40 -070011224 if (set->crtc->primary->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011225 struct intel_crtc *intel_crtc =
11226 to_intel_crtc(set->crtc);
11227
Matt Roper3b150f02014-05-29 08:06:53 -070011228 if (intel_crtc->active) {
Jesse Barnes319d9822013-06-26 01:38:19 +030011229 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11230 config->fb_changed = true;
11231 } else {
11232 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11233 config->mode_changed = true;
11234 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011235 } else if (set->fb == NULL) {
11236 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +010011237 } else if (set->fb->pixel_format !=
Matt Roperf4510a22014-04-01 15:22:40 -070011238 set->crtc->primary->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011239 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011240 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011241 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +020011242 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011243 }
11244
Daniel Vetter835c5872012-07-10 18:11:08 +020011245 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011246 config->fb_changed = true;
11247
11248 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11249 DRM_DEBUG_KMS("modes are different, full mode set\n");
11250 drm_mode_debug_printmodeline(&set->crtc->mode);
11251 drm_mode_debug_printmodeline(set->mode);
11252 config->mode_changed = true;
11253 }
Chris Wilsona1d95702013-08-13 18:48:47 +010011254
11255 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11256 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011257}
11258
Daniel Vetter2e431052012-07-04 22:42:15 +020011259static int
Daniel Vetter9a935852012-07-05 22:34:27 +020011260intel_modeset_stage_output_state(struct drm_device *dev,
11261 struct drm_mode_set *set,
11262 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +020011263{
Daniel Vetter9a935852012-07-05 22:34:27 +020011264 struct intel_connector *connector;
11265 struct intel_encoder *encoder;
Ville Syrjälä76688512014-01-10 11:28:06 +020011266 struct intel_crtc *crtc;
Paulo Zanonif3f08572013-08-12 14:56:53 -030011267 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +020011268
Damien Lespiau9abdda72013-02-13 13:29:23 +000011269 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +020011270 * of connectors. For paranoia, double-check this. */
11271 WARN_ON(!set->fb && (set->num_connectors != 0));
11272 WARN_ON(set->fb && (set->num_connectors == 0));
11273
Daniel Vetter9a935852012-07-05 22:34:27 +020011274 list_for_each_entry(connector, &dev->mode_config.connector_list,
11275 base.head) {
11276 /* Otherwise traverse passed in connector list and get encoders
11277 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +020011278 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011279 if (set->connectors[ro] == &connector->base) {
Dave Airlie0e32b392014-05-02 14:02:48 +100011280 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
Daniel Vetter50f56112012-07-02 09:35:43 +020011281 break;
11282 }
11283 }
11284
Daniel Vetter9a935852012-07-05 22:34:27 +020011285 /* If we disable the crtc, disable all its connectors. Also, if
11286 * the connector is on the changing crtc but not on the new
11287 * connector list, disable it. */
11288 if ((!set->fb || ro == set->num_connectors) &&
11289 connector->base.encoder &&
11290 connector->base.encoder->crtc == set->crtc) {
11291 connector->new_encoder = NULL;
11292
11293 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11294 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011295 connector->base.name);
Daniel Vetter9a935852012-07-05 22:34:27 +020011296 }
11297
11298
11299 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011300 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011301 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011302 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011303 }
11304 /* connector->new_encoder is now updated for all connectors. */
11305
11306 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +020011307 list_for_each_entry(connector, &dev->mode_config.connector_list,
11308 base.head) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011309 struct drm_crtc *new_crtc;
11310
Daniel Vetter9a935852012-07-05 22:34:27 +020011311 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +020011312 continue;
11313
Daniel Vetter9a935852012-07-05 22:34:27 +020011314 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +020011315
11316 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +020011317 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +020011318 new_crtc = set->crtc;
11319 }
11320
11321 /* Make sure the new CRTC will work with the encoder */
Thierry Reding14509912014-01-13 12:00:22 +010011322 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11323 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011324 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +020011325 }
Dave Airlie0e32b392014-05-02 14:02:48 +100011326 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
Daniel Vetter9a935852012-07-05 22:34:27 +020011327
11328 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11329 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030011330 connector->base.name,
Daniel Vetter9a935852012-07-05 22:34:27 +020011331 new_crtc->base.id);
11332 }
11333
11334 /* Check for any encoders that needs to be disabled. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010011335 for_each_intel_encoder(dev, encoder) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011336 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +020011337 list_for_each_entry(connector,
11338 &dev->mode_config.connector_list,
11339 base.head) {
11340 if (connector->new_encoder == encoder) {
11341 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011342 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +020011343 }
11344 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -020011345
11346 if (num_connectors == 0)
11347 encoder->new_crtc = NULL;
11348 else if (num_connectors > 1)
11349 return -EINVAL;
11350
Daniel Vetter9a935852012-07-05 22:34:27 +020011351 /* Only now check for crtc changes so we don't miss encoders
11352 * that will be disabled. */
11353 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +020011354 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011355 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +020011356 }
11357 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011358 /* Now we've also updated encoder->new_crtc for all encoders. */
Dave Airlie0e32b392014-05-02 14:02:48 +100011359 list_for_each_entry(connector, &dev->mode_config.connector_list,
11360 base.head) {
11361 if (connector->new_encoder)
11362 if (connector->new_encoder != connector->encoder)
11363 connector->encoder = connector->new_encoder;
11364 }
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011365 for_each_intel_crtc(dev, crtc) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011366 crtc->new_enabled = false;
11367
Damien Lespiaub2784e12014-08-05 11:29:37 +010011368 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä76688512014-01-10 11:28:06 +020011369 if (encoder->new_crtc == crtc) {
11370 crtc->new_enabled = true;
11371 break;
11372 }
11373 }
11374
11375 if (crtc->new_enabled != crtc->base.enabled) {
11376 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11377 crtc->new_enabled ? "en" : "dis");
11378 config->mode_changed = true;
11379 }
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011380
11381 if (crtc->new_enabled)
11382 crtc->new_config = &crtc->config;
11383 else
11384 crtc->new_config = NULL;
Ville Syrjälä76688512014-01-10 11:28:06 +020011385 }
11386
Daniel Vetter2e431052012-07-04 22:42:15 +020011387 return 0;
11388}
11389
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011390static void disable_crtc_nofb(struct intel_crtc *crtc)
11391{
11392 struct drm_device *dev = crtc->base.dev;
11393 struct intel_encoder *encoder;
11394 struct intel_connector *connector;
11395
11396 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11397 pipe_name(crtc->pipe));
11398
11399 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11400 if (connector->new_encoder &&
11401 connector->new_encoder->new_crtc == crtc)
11402 connector->new_encoder = NULL;
11403 }
11404
Damien Lespiaub2784e12014-08-05 11:29:37 +010011405 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011406 if (encoder->new_crtc == crtc)
11407 encoder->new_crtc = NULL;
11408 }
11409
11410 crtc->new_enabled = false;
Ville Syrjälä7bd0a8e2014-01-14 14:31:38 +020011411 crtc->new_config = NULL;
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011412}
11413
Daniel Vetter2e431052012-07-04 22:42:15 +020011414static int intel_crtc_set_config(struct drm_mode_set *set)
11415{
11416 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +020011417 struct drm_mode_set save_set;
11418 struct intel_set_config *config;
Jesse Barnes50f52752014-11-07 13:11:00 -080011419 struct intel_crtc_config *pipe_config;
11420 unsigned modeset_pipes, prepare_pipes, disable_pipes;
Daniel Vetter2e431052012-07-04 22:42:15 +020011421 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +020011422
Daniel Vetter8d3e3752012-07-05 16:09:09 +020011423 BUG_ON(!set);
11424 BUG_ON(!set->crtc);
11425 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +020011426
Daniel Vetter7e53f3a2013-01-21 10:52:17 +010011427 /* Enforce sane interface api - has been abused by the fb helper. */
11428 BUG_ON(!set->mode && set->fb);
11429 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +020011430
Daniel Vetter2e431052012-07-04 22:42:15 +020011431 if (set->fb) {
11432 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11433 set->crtc->base.id, set->fb->base.id,
11434 (int)set->num_connectors, set->x, set->y);
11435 } else {
11436 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +020011437 }
11438
11439 dev = set->crtc->dev;
11440
11441 ret = -ENOMEM;
11442 config = kzalloc(sizeof(*config), GFP_KERNEL);
11443 if (!config)
11444 goto out_config;
11445
11446 ret = intel_set_config_save_state(dev, config);
11447 if (ret)
11448 goto out_config;
11449
11450 save_set.crtc = set->crtc;
11451 save_set.mode = &set->crtc->mode;
11452 save_set.x = set->crtc->x;
11453 save_set.y = set->crtc->y;
Matt Roperf4510a22014-04-01 15:22:40 -070011454 save_set.fb = set->crtc->primary->fb;
Daniel Vetter2e431052012-07-04 22:42:15 +020011455
11456 /* Compute whether we need a full modeset, only an fb base update or no
11457 * change at all. In the future we might also check whether only the
11458 * mode changed, e.g. for LVDS where we only change the panel fitter in
11459 * such cases. */
11460 intel_set_config_compute_mode_changes(set, config);
11461
Daniel Vetter9a935852012-07-05 22:34:27 +020011462 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020011463 if (ret)
11464 goto fail;
11465
Jesse Barnes50f52752014-11-07 13:11:00 -080011466 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11467 set->fb,
11468 &modeset_pipes,
11469 &prepare_pipes,
11470 &disable_pipes);
Jesse Barnes20664592014-11-05 14:26:09 -080011471 if (IS_ERR(pipe_config)) {
Jesse Barnes50f52752014-11-07 13:11:00 -080011472 goto fail;
Jesse Barnes20664592014-11-05 14:26:09 -080011473 } else if (pipe_config) {
11474 if (to_intel_crtc(set->crtc)->new_config->has_audio !=
11475 to_intel_crtc(set->crtc)->config.has_audio)
11476 config->mode_changed = true;
11477
11478 /* Force mode sets for any infoframe stuff */
11479 if (to_intel_crtc(set->crtc)->new_config->has_infoframe ||
11480 to_intel_crtc(set->crtc)->config.has_infoframe)
11481 config->mode_changed = true;
11482 }
Jesse Barnes50f52752014-11-07 13:11:00 -080011483
11484 /* set_mode will free it in the mode_changed case */
11485 if (!config->mode_changed)
11486 kfree(pipe_config);
11487
Jesse Barnes1f9954d2014-11-05 14:26:10 -080011488 intel_update_pipe_size(to_intel_crtc(set->crtc));
11489
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011490 if (config->mode_changed) {
Jesse Barnes50f52752014-11-07 13:11:00 -080011491 ret = intel_set_mode_pipes(set->crtc, set->mode,
11492 set->x, set->y, set->fb, pipe_config,
11493 modeset_pipes, prepare_pipes,
11494 disable_pipes);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020011495 } else if (config->fb_changed) {
Matt Roper3b150f02014-05-29 08:06:53 -070011496 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11497
Ville Syrjälä4878cae2013-02-18 19:08:48 +020011498 intel_crtc_wait_for_pending_flips(set->crtc);
11499
Daniel Vetter4f660f42012-07-02 09:47:37 +020011500 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020011501 set->x, set->y, set->fb);
Matt Roper3b150f02014-05-29 08:06:53 -070011502
11503 /*
11504 * We need to make sure the primary plane is re-enabled if it
11505 * has previously been turned off.
11506 */
11507 if (!intel_crtc->primary_enabled && ret == 0) {
11508 WARN_ON(!intel_crtc->active);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011509 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
Matt Roper3b150f02014-05-29 08:06:53 -070011510 }
11511
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011512 /*
11513 * In the fastboot case this may be our only check of the
11514 * state after boot. It would be better to only do it on
11515 * the first update, but we don't have a nice way of doing that
11516 * (and really, set_config isn't used much for high freq page
11517 * flipping, so increasing its cost here shouldn't be a big
11518 * deal).
11519 */
Jani Nikulad330a952014-01-21 11:24:25 +020011520 if (i915.fastboot && ret == 0)
Jesse Barnes7ca51a32014-01-07 13:50:49 -080011521 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020011522 }
11523
Chris Wilson2d05eae2013-05-03 17:36:25 +010011524 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020011525 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11526 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020011527fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010011528 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011529
Ville Syrjälä7d00a1f2014-01-10 11:28:09 +020011530 /*
11531 * HACK: if the pipe was on, but we didn't have a framebuffer,
11532 * force the pipe off to avoid oopsing in the modeset code
11533 * due to fb==NULL. This should only happen during boot since
11534 * we don't yet reconstruct the FB from the hardware state.
11535 */
11536 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11537 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11538
Chris Wilson2d05eae2013-05-03 17:36:25 +010011539 /* Try to restore the config */
11540 if (config->mode_changed &&
11541 intel_set_mode(save_set.crtc, save_set.mode,
11542 save_set.x, save_set.y, save_set.fb))
11543 DRM_ERROR("failed to restore config after modeset failure\n");
11544 }
Daniel Vetter50f56112012-07-02 09:35:43 +020011545
Daniel Vetterd9e55602012-07-04 22:16:09 +020011546out_config:
11547 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020011548 return ret;
11549}
11550
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011551static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011552 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020011553 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010011554 .destroy = intel_crtc_destroy,
11555 .page_flip = intel_crtc_page_flip,
11556};
11557
Daniel Vetter53589012013-06-05 13:34:16 +020011558static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11559 struct intel_shared_dpll *pll,
11560 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011561{
Daniel Vetter53589012013-06-05 13:34:16 +020011562 uint32_t val;
11563
Daniel Vetterf458ebb2014-09-30 10:56:39 +020011564 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030011565 return false;
11566
Daniel Vetter53589012013-06-05 13:34:16 +020011567 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020011568 hw_state->dpll = val;
11569 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11570 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020011571
11572 return val & DPLL_VCO_ENABLE;
11573}
11574
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011575static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11576 struct intel_shared_dpll *pll)
11577{
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011578 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11579 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011580}
11581
Daniel Vettere7b903d2013-06-05 13:34:14 +020011582static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11583 struct intel_shared_dpll *pll)
11584{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011585 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020011586 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020011587
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011588 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011589
11590 /* Wait for the clocks to stabilize. */
11591 POSTING_READ(PCH_DPLL(pll->id));
11592 udelay(150);
11593
11594 /* The pixel multiplier can only be updated once the
11595 * DPLL is enabled and the clocks are stable.
11596 *
11597 * So write it again.
11598 */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020011599 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011600 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011601 udelay(200);
11602}
11603
11604static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11605 struct intel_shared_dpll *pll)
11606{
11607 struct drm_device *dev = dev_priv->dev;
11608 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011609
11610 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010011611 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020011612 if (intel_crtc_to_shared_dpll(crtc) == pll)
11613 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11614 }
11615
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011616 I915_WRITE(PCH_DPLL(pll->id), 0);
11617 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020011618 udelay(200);
11619}
11620
Daniel Vetter46edb022013-06-05 13:34:12 +020011621static char *ibx_pch_dpll_names[] = {
11622 "PCH DPLL A",
11623 "PCH DPLL B",
11624};
11625
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011626static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011627{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011628 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011629 int i;
11630
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011631 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011632
Daniel Vettere72f9fb2013-06-05 13:34:06 +020011633 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020011634 dev_priv->shared_dplls[i].id = i;
11635 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020011636 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020011637 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11638 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020011639 dev_priv->shared_dplls[i].get_hw_state =
11640 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010011641 }
11642}
11643
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011644static void intel_shared_dpll_init(struct drm_device *dev)
11645{
Daniel Vettere7b903d2013-06-05 13:34:14 +020011646 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011647
Daniel Vetter9cd86932014-06-25 22:01:57 +030011648 if (HAS_DDI(dev))
11649 intel_ddi_pll_init(dev);
11650 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011651 ibx_pch_dpll_init(dev);
11652 else
11653 dev_priv->num_shared_dpll = 0;
11654
11655 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020011656}
11657
Matt Roper465c1202014-05-29 08:06:54 -070011658static int
11659intel_primary_plane_disable(struct drm_plane *plane)
11660{
11661 struct drm_device *dev = plane->dev;
Matt Roper465c1202014-05-29 08:06:54 -070011662 struct intel_crtc *intel_crtc;
11663
11664 if (!plane->fb)
11665 return 0;
11666
11667 BUG_ON(!plane->crtc);
11668
11669 intel_crtc = to_intel_crtc(plane->crtc);
11670
11671 /*
11672 * Even though we checked plane->fb above, it's still possible that
11673 * the primary plane has been implicitly disabled because the crtc
11674 * coordinates given weren't visible, or because we detected
11675 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11676 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11677 * In either case, we need to unpin the FB and let the fb pointer get
11678 * updated, but otherwise we don't need to touch the hardware.
11679 */
11680 if (!intel_crtc->primary_enabled)
11681 goto disable_unpin;
11682
11683 intel_crtc_wait_for_pending_flips(plane->crtc);
Ville Syrjäläfdd508a2014-08-08 21:51:11 +030011684 intel_disable_primary_hw_plane(plane, plane->crtc);
11685
Matt Roper465c1202014-05-29 08:06:54 -070011686disable_unpin:
Matt Roper4c345742014-07-09 16:22:10 -070011687 mutex_lock(&dev->struct_mutex);
Matt Roper2ff8fde2014-07-08 07:50:07 -070011688 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
Daniel Vettera071fa02014-06-18 23:28:09 +020011689 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
Matt Roper2ff8fde2014-07-08 07:50:07 -070011690 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
Matt Roper4c345742014-07-09 16:22:10 -070011691 mutex_unlock(&dev->struct_mutex);
Matt Roper465c1202014-05-29 08:06:54 -070011692 plane->fb = NULL;
11693
11694 return 0;
11695}
11696
11697static int
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011698intel_check_primary_plane(struct drm_plane *plane,
11699 struct intel_plane_state *state)
Matt Roper465c1202014-05-29 08:06:54 -070011700{
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011701 struct drm_crtc *crtc = state->crtc;
11702 struct drm_framebuffer *fb = state->fb;
11703 struct drm_rect *dest = &state->dst;
11704 struct drm_rect *src = &state->src;
11705 const struct drm_rect *clip = &state->clip;
11706
Gustavo Padovan3ead8bb2014-10-24 19:00:18 +010011707 return drm_plane_helper_check_update(plane, crtc, fb,
11708 src, dest, clip,
11709 DRM_PLANE_HELPER_NO_SCALING,
11710 DRM_PLANE_HELPER_NO_SCALING,
11711 false, true, &state->visible);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011712}
11713
11714static int
Gustavo Padovan14af2932014-10-24 14:51:31 +010011715intel_prepare_primary_plane(struct drm_plane *plane,
11716 struct intel_plane_state *state)
11717{
11718 struct drm_crtc *crtc = state->crtc;
11719 struct drm_framebuffer *fb = state->fb;
11720 struct drm_device *dev = crtc->dev;
11721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11722 enum pipe pipe = intel_crtc->pipe;
11723 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11724 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11725 int ret;
11726
11727 intel_crtc_wait_for_pending_flips(crtc);
11728
11729 if (intel_crtc_has_pending_flip(crtc)) {
11730 DRM_ERROR("pipe is still busy with an old pageflip\n");
11731 return -EBUSY;
11732 }
11733
11734 if (old_obj != obj) {
11735 mutex_lock(&dev->struct_mutex);
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +000011736 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
Gustavo Padovan14af2932014-10-24 14:51:31 +010011737 if (ret == 0)
11738 i915_gem_track_fb(old_obj, obj,
11739 INTEL_FRONTBUFFER_PRIMARY(pipe));
11740 mutex_unlock(&dev->struct_mutex);
11741 if (ret != 0) {
11742 DRM_DEBUG_KMS("pin & fence failed\n");
11743 return ret;
11744 }
11745 }
11746
11747 return 0;
11748}
11749
11750static void
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011751intel_commit_primary_plane(struct drm_plane *plane,
11752 struct intel_plane_state *state)
11753{
11754 struct drm_crtc *crtc = state->crtc;
11755 struct drm_framebuffer *fb = state->fb;
Matt Roper465c1202014-05-29 08:06:54 -070011756 struct drm_device *dev = crtc->dev;
Sonika Jindal48404c12014-08-22 14:06:04 +053011757 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roper465c1202014-05-29 08:06:54 -070011758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011759 enum pipe pipe = intel_crtc->pipe;
11760 struct drm_framebuffer *old_fb = plane->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -070011761 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11762 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
Sonika Jindalce54d852014-08-21 11:44:39 +053011763 struct intel_plane *intel_plane = to_intel_plane(plane);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011764 struct drm_rect *src = &state->src;
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011765
11766 crtc->primary->fb = fb;
11767 crtc->x = src->x1;
11768 crtc->y = src->y1;
11769
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011770 intel_plane->crtc_x = state->orig_dst.x1;
11771 intel_plane->crtc_y = state->orig_dst.y1;
11772 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11773 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11774 intel_plane->src_x = state->orig_src.x1;
11775 intel_plane->src_y = state->orig_src.y1;
11776 intel_plane->src_w = drm_rect_width(&state->orig_src);
11777 intel_plane->src_h = drm_rect_height(&state->orig_src);
Sonika Jindalce54d852014-08-21 11:44:39 +053011778 intel_plane->obj = obj;
Matt Roper465c1202014-05-29 08:06:54 -070011779
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030011780 if (intel_crtc->active) {
11781 /*
11782 * FBC does not work on some platforms for rotated
11783 * planes, so disable it when rotation is not 0 and
11784 * update it when rotation is set back to 0.
11785 *
11786 * FIXME: This is redundant with the fbc update done in
11787 * the primary plane enable function except that that
11788 * one is done too late. We eventually need to unify
11789 * this.
11790 */
11791 if (intel_crtc->primary_enabled &&
11792 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11793 dev_priv->fbc.plane == intel_crtc->plane &&
11794 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11795 intel_disable_fbc(dev);
11796 }
11797
11798 if (state->visible) {
11799 bool was_enabled = intel_crtc->primary_enabled;
11800
11801 /* FIXME: kill this fastboot hack */
11802 intel_update_pipe_size(intel_crtc);
11803
11804 intel_crtc->primary_enabled = true;
11805
11806 dev_priv->display.update_primary_plane(crtc, plane->fb,
11807 crtc->x, crtc->y);
11808
11809 /*
11810 * BDW signals flip done immediately if the plane
11811 * is disabled, even if the plane enable is already
11812 * armed to occur at the next vblank :(
11813 */
11814 if (IS_BROADWELL(dev) && !was_enabled)
11815 intel_wait_for_vblank(dev, intel_crtc->pipe);
11816 } else {
11817 /*
11818 * If clipping results in a non-visible primary plane,
11819 * we'll disable the primary plane. Note that this is
11820 * a bit different than what happens if userspace
11821 * explicitly disables the plane by passing fb=0
11822 * because plane->fb still gets set and pinned.
11823 */
11824 intel_disable_primary_hw_plane(plane, crtc);
11825 }
11826
11827 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11828
11829 mutex_lock(&dev->struct_mutex);
11830 intel_update_fbc(dev);
11831 mutex_unlock(&dev->struct_mutex);
11832 }
11833
11834 if (old_fb && old_fb != fb) {
11835 if (intel_crtc->active)
11836 intel_wait_for_vblank(dev, intel_crtc->pipe);
11837
11838 mutex_lock(&dev->struct_mutex);
11839 intel_unpin_fb_obj(old_obj);
11840 mutex_unlock(&dev->struct_mutex);
11841 }
Matt Roper465c1202014-05-29 08:06:54 -070011842}
11843
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011844static int
11845intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11846 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11847 unsigned int crtc_w, unsigned int crtc_h,
11848 uint32_t src_x, uint32_t src_y,
11849 uint32_t src_w, uint32_t src_h)
11850{
11851 struct intel_plane_state state;
11852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11853 int ret;
11854
11855 state.crtc = crtc;
11856 state.fb = fb;
11857
11858 /* sample coordinates in 16.16 fixed point */
11859 state.src.x1 = src_x;
11860 state.src.x2 = src_x + src_w;
11861 state.src.y1 = src_y;
11862 state.src.y2 = src_y + src_h;
11863
11864 /* integer pixels */
11865 state.dst.x1 = crtc_x;
11866 state.dst.x2 = crtc_x + crtc_w;
11867 state.dst.y1 = crtc_y;
11868 state.dst.y2 = crtc_y + crtc_h;
11869
11870 state.clip.x1 = 0;
11871 state.clip.y1 = 0;
11872 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11873 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11874
11875 state.orig_src = state.src;
11876 state.orig_dst = state.dst;
11877
11878 ret = intel_check_primary_plane(plane, &state);
11879 if (ret)
11880 return ret;
11881
Gustavo Padovan14af2932014-10-24 14:51:31 +010011882 ret = intel_prepare_primary_plane(plane, &state);
11883 if (ret)
11884 return ret;
11885
Gustavo Padovan3c692a42014-09-05 17:04:49 -030011886 intel_commit_primary_plane(plane, &state);
11887
11888 return 0;
11889}
11890
Matt Roper3d7d6512014-06-10 08:28:13 -070011891/* Common destruction function for both primary and cursor planes */
11892static void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070011893{
11894 struct intel_plane *intel_plane = to_intel_plane(plane);
11895 drm_plane_cleanup(plane);
11896 kfree(intel_plane);
11897}
11898
11899static const struct drm_plane_funcs intel_primary_plane_funcs = {
11900 .update_plane = intel_primary_plane_setplane,
11901 .disable_plane = intel_primary_plane_disable,
Matt Roper3d7d6512014-06-10 08:28:13 -070011902 .destroy = intel_plane_destroy,
Sonika Jindal48404c12014-08-22 14:06:04 +053011903 .set_property = intel_plane_set_property
Matt Roper465c1202014-05-29 08:06:54 -070011904};
11905
11906static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11907 int pipe)
11908{
11909 struct intel_plane *primary;
11910 const uint32_t *intel_primary_formats;
11911 int num_formats;
11912
11913 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11914 if (primary == NULL)
11915 return NULL;
11916
11917 primary->can_scale = false;
11918 primary->max_downscale = 1;
11919 primary->pipe = pipe;
11920 primary->plane = pipe;
Sonika Jindal48404c12014-08-22 14:06:04 +053011921 primary->rotation = BIT(DRM_ROTATE_0);
Matt Roper465c1202014-05-29 08:06:54 -070011922 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11923 primary->plane = !pipe;
11924
11925 if (INTEL_INFO(dev)->gen <= 3) {
11926 intel_primary_formats = intel_primary_formats_gen2;
11927 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11928 } else {
11929 intel_primary_formats = intel_primary_formats_gen4;
11930 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11931 }
11932
11933 drm_universal_plane_init(dev, &primary->base, 0,
11934 &intel_primary_plane_funcs,
11935 intel_primary_formats, num_formats,
11936 DRM_PLANE_TYPE_PRIMARY);
Sonika Jindal48404c12014-08-22 14:06:04 +053011937
11938 if (INTEL_INFO(dev)->gen >= 4) {
11939 if (!dev->mode_config.rotation_property)
11940 dev->mode_config.rotation_property =
11941 drm_mode_create_rotation_property(dev,
11942 BIT(DRM_ROTATE_0) |
11943 BIT(DRM_ROTATE_180));
11944 if (dev->mode_config.rotation_property)
11945 drm_object_attach_property(&primary->base.base,
11946 dev->mode_config.rotation_property,
11947 primary->rotation);
11948 }
11949
Matt Roper465c1202014-05-29 08:06:54 -070011950 return &primary->base;
11951}
11952
Matt Roper3d7d6512014-06-10 08:28:13 -070011953static int
11954intel_cursor_plane_disable(struct drm_plane *plane)
11955{
11956 if (!plane->fb)
11957 return 0;
11958
11959 BUG_ON(!plane->crtc);
11960
11961 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11962}
11963
11964static int
Gustavo Padovan852e7872014-09-05 17:22:31 -030011965intel_check_cursor_plane(struct drm_plane *plane,
11966 struct intel_plane_state *state)
Matt Roper3d7d6512014-06-10 08:28:13 -070011967{
Gustavo Padovan852e7872014-09-05 17:22:31 -030011968 struct drm_crtc *crtc = state->crtc;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011969 struct drm_device *dev = crtc->dev;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011970 struct drm_framebuffer *fb = state->fb;
11971 struct drm_rect *dest = &state->dst;
11972 struct drm_rect *src = &state->src;
11973 const struct drm_rect *clip = &state->clip;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011974 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11975 int crtc_w, crtc_h;
11976 unsigned stride;
11977 int ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030011978
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011979 ret = drm_plane_helper_check_update(plane, crtc, fb,
Gustavo Padovan852e7872014-09-05 17:22:31 -030011980 src, dest, clip,
11981 DRM_PLANE_HELPER_NO_SCALING,
11982 DRM_PLANE_HELPER_NO_SCALING,
11983 true, true, &state->visible);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011984 if (ret)
11985 return ret;
11986
11987
11988 /* if we want to turn off the cursor ignore width and height */
11989 if (!obj)
11990 return 0;
11991
Gustavo Padovan757f9a32014-09-24 14:20:24 -030011992 /* Check for which cursor types we support */
11993 crtc_w = drm_rect_width(&state->orig_dst);
11994 crtc_h = drm_rect_height(&state->orig_dst);
11995 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11996 DRM_DEBUG("Cursor dimension not supported\n");
11997 return -EINVAL;
11998 }
11999
12000 stride = roundup_pow_of_two(crtc_w) * 4;
12001 if (obj->base.size < stride * crtc_h) {
12002 DRM_DEBUG_KMS("buffer is too small\n");
12003 return -ENOMEM;
12004 }
12005
Gustavo Padovane391ea82014-09-24 14:20:25 -030012006 if (fb == crtc->cursor->fb)
12007 return 0;
12008
Gustavo Padovan757f9a32014-09-24 14:20:24 -030012009 /* we only need to pin inside GTT if cursor is non-phy */
12010 mutex_lock(&dev->struct_mutex);
12011 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12012 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12013 ret = -EINVAL;
12014 }
12015 mutex_unlock(&dev->struct_mutex);
12016
12017 return ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030012018}
12019
12020static int
12021intel_commit_cursor_plane(struct drm_plane *plane,
12022 struct intel_plane_state *state)
12023{
12024 struct drm_crtc *crtc = state->crtc;
12025 struct drm_framebuffer *fb = state->fb;
Matt Roper3d7d6512014-06-10 08:28:13 -070012026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Sonika Jindala919db92014-10-23 07:41:33 -070012027 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper3d7d6512014-06-10 08:28:13 -070012028 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12029 struct drm_i915_gem_object *obj = intel_fb->obj;
Gustavo Padovan852e7872014-09-05 17:22:31 -030012030 int crtc_w, crtc_h;
Matt Roper3d7d6512014-06-10 08:28:13 -070012031
Gustavo Padovan852e7872014-09-05 17:22:31 -030012032 crtc->cursor_x = state->orig_dst.x1;
12033 crtc->cursor_y = state->orig_dst.y1;
Sonika Jindala919db92014-10-23 07:41:33 -070012034
12035 intel_plane->crtc_x = state->orig_dst.x1;
12036 intel_plane->crtc_y = state->orig_dst.y1;
12037 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
12038 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
12039 intel_plane->src_x = state->orig_src.x1;
12040 intel_plane->src_y = state->orig_src.y1;
12041 intel_plane->src_w = drm_rect_width(&state->orig_src);
12042 intel_plane->src_h = drm_rect_height(&state->orig_src);
12043 intel_plane->obj = obj;
12044
Matt Roper3d7d6512014-06-10 08:28:13 -070012045 if (fb != crtc->cursor->fb) {
Gustavo Padovan852e7872014-09-05 17:22:31 -030012046 crtc_w = drm_rect_width(&state->orig_dst);
12047 crtc_h = drm_rect_height(&state->orig_dst);
Matt Roper3d7d6512014-06-10 08:28:13 -070012048 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12049 } else {
Gustavo Padovan852e7872014-09-05 17:22:31 -030012050 intel_crtc_update_cursor(crtc, state->visible);
Daniel Vetter4ed91092014-08-08 20:27:01 +020012051
12052 intel_frontbuffer_flip(crtc->dev,
12053 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12054
Matt Roper3d7d6512014-06-10 08:28:13 -070012055 return 0;
12056 }
12057}
Gustavo Padovan852e7872014-09-05 17:22:31 -030012058
12059static int
12060intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12061 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12062 unsigned int crtc_w, unsigned int crtc_h,
12063 uint32_t src_x, uint32_t src_y,
12064 uint32_t src_w, uint32_t src_h)
12065{
12066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12067 struct intel_plane_state state;
12068 int ret;
12069
12070 state.crtc = crtc;
12071 state.fb = fb;
12072
12073 /* sample coordinates in 16.16 fixed point */
12074 state.src.x1 = src_x;
12075 state.src.x2 = src_x + src_w;
12076 state.src.y1 = src_y;
12077 state.src.y2 = src_y + src_h;
12078
12079 /* integer pixels */
12080 state.dst.x1 = crtc_x;
12081 state.dst.x2 = crtc_x + crtc_w;
12082 state.dst.y1 = crtc_y;
12083 state.dst.y2 = crtc_y + crtc_h;
12084
12085 state.clip.x1 = 0;
12086 state.clip.y1 = 0;
12087 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12088 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12089
12090 state.orig_src = state.src;
12091 state.orig_dst = state.dst;
12092
12093 ret = intel_check_cursor_plane(plane, &state);
12094 if (ret)
12095 return ret;
12096
12097 return intel_commit_cursor_plane(plane, &state);
12098}
12099
Matt Roper3d7d6512014-06-10 08:28:13 -070012100static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12101 .update_plane = intel_cursor_plane_update,
12102 .disable_plane = intel_cursor_plane_disable,
12103 .destroy = intel_plane_destroy,
Ville Syrjälä4398ad42014-10-23 07:41:34 -070012104 .set_property = intel_plane_set_property,
Matt Roper3d7d6512014-06-10 08:28:13 -070012105};
12106
12107static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12108 int pipe)
12109{
12110 struct intel_plane *cursor;
12111
12112 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12113 if (cursor == NULL)
12114 return NULL;
12115
12116 cursor->can_scale = false;
12117 cursor->max_downscale = 1;
12118 cursor->pipe = pipe;
12119 cursor->plane = pipe;
Ville Syrjälä4398ad42014-10-23 07:41:34 -070012120 cursor->rotation = BIT(DRM_ROTATE_0);
Matt Roper3d7d6512014-06-10 08:28:13 -070012121
12122 drm_universal_plane_init(dev, &cursor->base, 0,
12123 &intel_cursor_plane_funcs,
12124 intel_cursor_formats,
12125 ARRAY_SIZE(intel_cursor_formats),
12126 DRM_PLANE_TYPE_CURSOR);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070012127
12128 if (INTEL_INFO(dev)->gen >= 4) {
12129 if (!dev->mode_config.rotation_property)
12130 dev->mode_config.rotation_property =
12131 drm_mode_create_rotation_property(dev,
12132 BIT(DRM_ROTATE_0) |
12133 BIT(DRM_ROTATE_180));
12134 if (dev->mode_config.rotation_property)
12135 drm_object_attach_property(&cursor->base.base,
12136 dev->mode_config.rotation_property,
12137 cursor->rotation);
12138 }
12139
Matt Roper3d7d6512014-06-10 08:28:13 -070012140 return &cursor->base;
12141}
12142
Hannes Ederb358d0a2008-12-18 21:18:47 +010012143static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080012144{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012145 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080012146 struct intel_crtc *intel_crtc;
Matt Roper3d7d6512014-06-10 08:28:13 -070012147 struct drm_plane *primary = NULL;
12148 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070012149 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080012150
Daniel Vetter955382f2013-09-19 14:05:45 +020012151 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080012152 if (intel_crtc == NULL)
12153 return;
12154
Matt Roper465c1202014-05-29 08:06:54 -070012155 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070012156 if (!primary)
12157 goto fail;
12158
12159 cursor = intel_cursor_plane_create(dev, pipe);
12160 if (!cursor)
12161 goto fail;
12162
Matt Roper465c1202014-05-29 08:06:54 -070012163 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070012164 cursor, &intel_crtc_funcs);
12165 if (ret)
12166 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080012167
12168 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080012169 for (i = 0; i < 256; i++) {
12170 intel_crtc->lut_r[i] = i;
12171 intel_crtc->lut_g[i] = i;
12172 intel_crtc->lut_b[i] = i;
12173 }
12174
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020012175 /*
12176 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020012177 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020012178 */
Jesse Barnes80824002009-09-10 15:28:06 -070012179 intel_crtc->pipe = pipe;
12180 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010012181 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080012182 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010012183 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070012184 }
12185
Chris Wilson4b0e3332014-05-30 16:35:26 +030012186 intel_crtc->cursor_base = ~0;
12187 intel_crtc->cursor_cntl = ~0;
Ville Syrjälädc41c152014-08-13 11:57:05 +030012188 intel_crtc->cursor_size = ~0;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030012189
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080012190 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12191 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12193 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12194
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +020012195 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12196
Jesse Barnes79e53942008-11-07 14:24:08 -080012197 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020012198
12199 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070012200 return;
12201
12202fail:
12203 if (primary)
12204 drm_plane_cleanup(primary);
12205 if (cursor)
12206 drm_plane_cleanup(cursor);
12207 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080012208}
12209
Jesse Barnes752aa882013-10-31 18:55:49 +020012210enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12211{
12212 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020012213 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020012214
Rob Clark51fd3712013-11-19 12:10:12 -050012215 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020012216
Ville Syrjäläd3babd32014-11-07 11:16:01 +020012217 if (!encoder || WARN_ON(!encoder->crtc))
Jesse Barnes752aa882013-10-31 18:55:49 +020012218 return INVALID_PIPE;
12219
12220 return to_intel_crtc(encoder->crtc)->pipe;
12221}
12222
Carl Worth08d7b3d2009-04-29 14:43:54 -070012223int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000012224 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070012225{
Carl Worth08d7b3d2009-04-29 14:43:54 -070012226 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040012227 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020012228 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012229
Daniel Vetter1cff8f62012-04-24 09:55:08 +020012230 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12231 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012232
Rob Clark7707e652014-07-17 23:30:04 -040012233 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Carl Worth08d7b3d2009-04-29 14:43:54 -070012234
Rob Clark7707e652014-07-17 23:30:04 -040012235 if (!drmmode_crtc) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070012236 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030012237 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012238 }
12239
Rob Clark7707e652014-07-17 23:30:04 -040012240 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020012241 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012242
Daniel Vetterc05422d2009-08-11 16:05:30 +020012243 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070012244}
12245
Daniel Vetter66a92782012-07-12 20:08:18 +020012246static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080012247{
Daniel Vetter66a92782012-07-12 20:08:18 +020012248 struct drm_device *dev = encoder->base.dev;
12249 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080012250 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080012251 int entry = 0;
12252
Damien Lespiaub2784e12014-08-05 11:29:37 +010012253 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020012254 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020012255 index_mask |= (1 << entry);
12256
Jesse Barnes79e53942008-11-07 14:24:08 -080012257 entry++;
12258 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010012259
Jesse Barnes79e53942008-11-07 14:24:08 -080012260 return index_mask;
12261}
12262
Chris Wilson4d302442010-12-14 19:21:29 +000012263static bool has_edp_a(struct drm_device *dev)
12264{
12265 struct drm_i915_private *dev_priv = dev->dev_private;
12266
12267 if (!IS_MOBILE(dev))
12268 return false;
12269
12270 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12271 return false;
12272
Damien Lespiaue3589902014-02-07 19:12:50 +000012273 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000012274 return false;
12275
12276 return true;
12277}
12278
Damien Lespiauba0fbca2014-01-08 14:18:23 +000012279const char *intel_output_name(int output)
12280{
12281 static const char *names[] = {
12282 [INTEL_OUTPUT_UNUSED] = "Unused",
12283 [INTEL_OUTPUT_ANALOG] = "Analog",
12284 [INTEL_OUTPUT_DVO] = "DVO",
12285 [INTEL_OUTPUT_SDVO] = "SDVO",
12286 [INTEL_OUTPUT_LVDS] = "LVDS",
12287 [INTEL_OUTPUT_TVOUT] = "TV",
12288 [INTEL_OUTPUT_HDMI] = "HDMI",
12289 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12290 [INTEL_OUTPUT_EDP] = "eDP",
12291 [INTEL_OUTPUT_DSI] = "DSI",
12292 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12293 };
12294
12295 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12296 return "Invalid";
12297
12298 return names[output];
12299}
12300
Jesse Barnes84b4e042014-06-25 08:24:29 -070012301static bool intel_crt_present(struct drm_device *dev)
12302{
12303 struct drm_i915_private *dev_priv = dev->dev_private;
12304
Damien Lespiau884497e2013-12-03 13:56:23 +000012305 if (INTEL_INFO(dev)->gen >= 9)
12306 return false;
12307
Damien Lespiaucf404ce2014-10-01 20:04:15 +010012308 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
Jesse Barnes84b4e042014-06-25 08:24:29 -070012309 return false;
12310
12311 if (IS_CHERRYVIEW(dev))
12312 return false;
12313
12314 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12315 return false;
12316
12317 return true;
12318}
12319
Jesse Barnes79e53942008-11-07 14:24:08 -080012320static void intel_setup_outputs(struct drm_device *dev)
12321{
Eric Anholt725e30a2009-01-22 13:01:02 -080012322 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010012323 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012324 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080012325
Daniel Vetterc9093352013-06-06 22:22:47 +020012326 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012327
Jesse Barnes84b4e042014-06-25 08:24:29 -070012328 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020012329 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012330
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012331 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030012332 int found;
12333
12334 /* Haswell uses DDI functions to detect digital outputs */
12335 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12336 /* DDI A only supports eDP */
12337 if (found)
12338 intel_ddi_init(dev, PORT_A);
12339
12340 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12341 * register */
12342 found = I915_READ(SFUSE_STRAP);
12343
12344 if (found & SFUSE_STRAP_DDIB_DETECTED)
12345 intel_ddi_init(dev, PORT_B);
12346 if (found & SFUSE_STRAP_DDIC_DETECTED)
12347 intel_ddi_init(dev, PORT_C);
12348 if (found & SFUSE_STRAP_DDID_DETECTED)
12349 intel_ddi_init(dev, PORT_D);
12350 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012351 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020012352 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020012353
12354 if (has_edp_a(dev))
12355 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040012356
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012357 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080012358 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010012359 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012360 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012361 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012362 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012363 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012364 }
12365
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012366 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012367 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012368
Paulo Zanonidc0fa712013-02-19 16:21:46 -030012369 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030012370 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080012371
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012372 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012373 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080012374
Daniel Vetter270b3042012-10-27 15:52:05 +020012375 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012376 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070012377 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012378 /*
12379 * The DP_DETECTED bit is the latched state of the DDC
12380 * SDA pin at boot. However since eDP doesn't require DDC
12381 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12382 * eDP ports may have been muxed to an alternate function.
12383 * Thus we can't rely on the DP_DETECTED bit alone to detect
12384 * eDP ports. Consult the VBT as well as DP_DETECTED to
12385 * detect eDP ports.
12386 */
12387 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012388 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12389 PORT_B);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012390 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12391 intel_dp_is_edp(dev, PORT_B))
12392 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030012393
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012394 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
Jesse Barnes6f6005a2013-08-09 09:34:35 -070012395 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12396 PORT_C);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012397 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12398 intel_dp_is_edp(dev, PORT_C))
12399 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +053012400
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012401 if (IS_CHERRYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012402 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012403 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12404 PORT_D);
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030012405 /* eDP not supported on port D, so don't check VBT */
12406 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12407 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030012408 }
12409
Jani Nikula3cfca972013-08-27 15:12:26 +030012410 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080012411 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012412 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080012413
Paulo Zanonie2debe92013-02-18 19:00:27 -030012414 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012415 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012416 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012417 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12418 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012419 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012420 }
Ma Ling27185ae2009-08-24 13:50:23 +080012421
Imre Deake7281ea2013-05-08 13:14:08 +030012422 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012423 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080012424 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012425
12426 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040012427
Paulo Zanonie2debe92013-02-18 19:00:27 -030012428 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012429 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012430 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012431 }
Ma Ling27185ae2009-08-24 13:50:23 +080012432
Paulo Zanonie2debe92013-02-18 19:00:27 -030012433 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080012434
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012435 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12436 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030012437 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012438 }
Imre Deake7281ea2013-05-08 13:14:08 +030012439 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012440 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080012441 }
Ma Ling27185ae2009-08-24 13:50:23 +080012442
Jesse Barnesb01f2c32009-12-11 11:07:17 -080012443 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030012444 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030012445 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070012446 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012447 intel_dvo_init(dev);
12448
Zhenyu Wang103a1962009-11-27 11:44:36 +080012449 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080012450 intel_tv_init(dev);
12451
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -080012452 intel_psr_init(dev);
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070012453
Damien Lespiaub2784e12014-08-05 11:29:37 +010012454 for_each_intel_encoder(dev, encoder) {
Chris Wilson4ef69c72010-09-09 15:14:28 +010012455 encoder->base.possible_crtcs = encoder->crtc_mask;
12456 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020012457 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080012458 }
Chris Wilson47356eb2011-01-11 17:06:04 +000012459
Paulo Zanonidde86e22012-12-01 12:04:25 -020012460 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020012461
12462 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080012463}
12464
12465static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12466{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012467 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080012468 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080012469
Daniel Vetteref2d6332014-02-10 18:00:38 +010012470 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012471 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010012472 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030012473 drm_gem_object_unreference(&intel_fb->obj->base);
12474 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080012475 kfree(intel_fb);
12476}
12477
12478static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000012479 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080012480 unsigned int *handle)
12481{
12482 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000012483 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012484
Chris Wilson05394f32010-11-08 19:18:58 +000012485 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080012486}
12487
12488static const struct drm_framebuffer_funcs intel_fb_funcs = {
12489 .destroy = intel_user_framebuffer_destroy,
12490 .create_handle = intel_user_framebuffer_create_handle,
12491};
12492
Daniel Vetterb5ea6422014-03-02 21:18:00 +010012493static int intel_framebuffer_init(struct drm_device *dev,
12494 struct intel_framebuffer *intel_fb,
12495 struct drm_mode_fb_cmd2 *mode_cmd,
12496 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080012497{
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012498 int aligned_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012499 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080012500 int ret;
12501
Daniel Vetterdd4916c2013-10-09 21:23:51 +020012502 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12503
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012504 if (obj->tiling_mode == I915_TILING_Y) {
12505 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010012506 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012507 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012508
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012509 if (mode_cmd->pitches[0] & 63) {
12510 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12511 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010012512 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012513 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012514
Chris Wilsona35cdaa2013-06-25 17:26:45 +010012515 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12516 pitch_limit = 32*1024;
12517 } else if (INTEL_INFO(dev)->gen >= 4) {
12518 if (obj->tiling_mode)
12519 pitch_limit = 16*1024;
12520 else
12521 pitch_limit = 32*1024;
12522 } else if (INTEL_INFO(dev)->gen >= 3) {
12523 if (obj->tiling_mode)
12524 pitch_limit = 8*1024;
12525 else
12526 pitch_limit = 16*1024;
12527 } else
12528 /* XXX DSPC is limited to 4k tiled */
12529 pitch_limit = 8*1024;
12530
12531 if (mode_cmd->pitches[0] > pitch_limit) {
12532 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12533 obj->tiling_mode ? "tiled" : "linear",
12534 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012535 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012536 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012537
12538 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012539 mode_cmd->pitches[0] != obj->stride) {
12540 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12541 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012542 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012543 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020012544
Ville Syrjälä57779d02012-10-31 17:50:14 +020012545 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012546 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020012547 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012548 case DRM_FORMAT_RGB565:
12549 case DRM_FORMAT_XRGB8888:
12550 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012551 break;
12552 case DRM_FORMAT_XRGB1555:
12553 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012554 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012555 DRM_DEBUG("unsupported pixel format: %s\n",
12556 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012557 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012558 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020012559 break;
12560 case DRM_FORMAT_XBGR8888:
12561 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020012562 case DRM_FORMAT_XRGB2101010:
12563 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020012564 case DRM_FORMAT_XBGR2101010:
12565 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012566 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012567 DRM_DEBUG("unsupported pixel format: %s\n",
12568 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012569 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012570 }
Jesse Barnesb5626742011-06-24 12:19:27 -070012571 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020012572 case DRM_FORMAT_YUYV:
12573 case DRM_FORMAT_UYVY:
12574 case DRM_FORMAT_YVYU:
12575 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012576 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012577 DRM_DEBUG("unsupported pixel format: %s\n",
12578 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020012579 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000012580 }
Chris Wilson57cd6502010-08-08 12:34:44 +010012581 break;
12582 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000012583 DRM_DEBUG("unsupported pixel format: %s\n",
12584 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010012585 return -EINVAL;
12586 }
12587
Ville Syrjälä90f9a332012-10-31 17:50:19 +020012588 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12589 if (mode_cmd->offsets[0] != 0)
12590 return -EINVAL;
12591
Jesse Barnesa57ce0b2014-02-07 12:10:35 -080012592 aligned_height = intel_align_height(dev, mode_cmd->height,
12593 obj->tiling_mode);
Daniel Vetter53155c02013-10-09 21:55:33 +020012594 /* FIXME drm helper for size checks (especially planar formats)? */
12595 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12596 return -EINVAL;
12597
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012598 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12599 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020012600 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010012601
Jesse Barnes79e53942008-11-07 14:24:08 -080012602 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12603 if (ret) {
12604 DRM_ERROR("framebuffer init failed %d\n", ret);
12605 return ret;
12606 }
12607
Jesse Barnes79e53942008-11-07 14:24:08 -080012608 return 0;
12609}
12610
Jesse Barnes79e53942008-11-07 14:24:08 -080012611static struct drm_framebuffer *
12612intel_user_framebuffer_create(struct drm_device *dev,
12613 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012614 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080012615{
Chris Wilson05394f32010-11-08 19:18:58 +000012616 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080012617
Jesse Barnes308e5bc2011-11-14 14:51:28 -080012618 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12619 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000012620 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010012621 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080012622
Chris Wilsond2dff872011-04-19 08:36:26 +010012623 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080012624}
12625
Daniel Vetter4520f532013-10-09 09:18:51 +020012626#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020012627static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020012628{
12629}
12630#endif
12631
Jesse Barnes79e53942008-11-07 14:24:08 -080012632static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080012633 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020012634 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080012635};
12636
Jesse Barnese70236a2009-09-21 10:42:27 -070012637/* Set up chip specific display functions */
12638static void intel_init_display(struct drm_device *dev)
12639{
12640 struct drm_i915_private *dev_priv = dev->dev_private;
12641
Daniel Vetteree9300b2013-06-03 22:40:22 +020012642 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12643 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030012644 else if (IS_CHERRYVIEW(dev))
12645 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020012646 else if (IS_VALLEYVIEW(dev))
12647 dev_priv->display.find_dpll = vlv_find_best_dpll;
12648 else if (IS_PINEVIEW(dev))
12649 dev_priv->display.find_dpll = pnv_find_best_dpll;
12650 else
12651 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12652
Paulo Zanoniaffa9352012-11-23 15:30:39 -020012653 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012654 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012655 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +020012656 dev_priv->display.crtc_compute_clock =
12657 haswell_crtc_compute_clock;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020012658 dev_priv->display.crtc_enable = haswell_crtc_enable;
12659 dev_priv->display.crtc_disable = haswell_crtc_disable;
Daniel Vetterdf8ad702014-06-25 22:02:03 +030012660 dev_priv->display.off = ironlake_crtc_off;
Damien Lespiau70d21f02013-07-03 21:06:04 +010012661 if (INTEL_INFO(dev)->gen >= 9)
12662 dev_priv->display.update_primary_plane =
12663 skylake_update_primary_plane;
12664 else
12665 dev_priv->display.update_primary_plane =
12666 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030012667 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012668 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnes4c6baa52014-03-07 08:57:50 -080012669 dev_priv->display.get_plane_config = ironlake_get_plane_config;
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +020012670 dev_priv->display.crtc_compute_clock =
12671 ironlake_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012672 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12673 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012674 dev_priv->display.off = ironlake_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012675 dev_priv->display.update_primary_plane =
12676 ironlake_update_primary_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012677 } else if (IS_VALLEYVIEW(dev)) {
12678 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012679 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020012680 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Jesse Barnes89b667f2013-04-18 14:51:36 -070012681 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12682 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12683 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012684 dev_priv->display.update_primary_plane =
12685 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012686 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012687 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnes1ad292b2014-03-07 08:57:49 -080012688 dev_priv->display.get_plane_config = i9xx_get_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020012689 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020012690 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12691 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010012692 dev_priv->display.off = i9xx_crtc_off;
Matt Roper262ca2b2014-03-18 17:22:55 -070012693 dev_priv->display.update_primary_plane =
12694 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070012695 }
Jesse Barnese70236a2009-09-21 10:42:27 -070012696
Jesse Barnese70236a2009-09-21 10:42:27 -070012697 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070012698 if (IS_VALLEYVIEW(dev))
12699 dev_priv->display.get_display_clock_speed =
12700 valleyview_get_display_clock_speed;
12701 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070012702 dev_priv->display.get_display_clock_speed =
12703 i945_get_display_clock_speed;
12704 else if (IS_I915G(dev))
12705 dev_priv->display.get_display_clock_speed =
12706 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012707 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012708 dev_priv->display.get_display_clock_speed =
12709 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020012710 else if (IS_PINEVIEW(dev))
12711 dev_priv->display.get_display_clock_speed =
12712 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070012713 else if (IS_I915GM(dev))
12714 dev_priv->display.get_display_clock_speed =
12715 i915gm_get_display_clock_speed;
12716 else if (IS_I865G(dev))
12717 dev_priv->display.get_display_clock_speed =
12718 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020012719 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070012720 dev_priv->display.get_display_clock_speed =
12721 i855_get_display_clock_speed;
12722 else /* 852, 830 */
12723 dev_priv->display.get_display_clock_speed =
12724 i830_get_display_clock_speed;
12725
Jani Nikula7c10a2b2014-10-27 16:26:43 +020012726 if (IS_GEN5(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012727 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012728 } else if (IS_GEN6(dev)) {
12729 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012730 } else if (IS_IVYBRIDGE(dev)) {
12731 /* FIXME: detect B0+ stepping and use auto training */
12732 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012733 dev_priv->display.modeset_global_resources =
12734 ivb_modeset_global_resources;
Paulo Zanoni059b2fe2014-09-02 16:53:57 -030012735 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053012736 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Jesse Barnes30a970c2013-11-04 13:48:12 -080012737 } else if (IS_VALLEYVIEW(dev)) {
12738 dev_priv->display.modeset_global_resources =
12739 valleyview_modeset_global_resources;
Jesse Barnese70236a2009-09-21 10:42:27 -070012740 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012741
12742 /* Default just returns -ENODEV to indicate unsupported */
12743 dev_priv->display.queue_flip = intel_default_queue_flip;
12744
12745 switch (INTEL_INFO(dev)->gen) {
12746 case 2:
12747 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12748 break;
12749
12750 case 3:
12751 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12752 break;
12753
12754 case 4:
12755 case 5:
12756 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12757 break;
12758
12759 case 6:
12760 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12761 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012762 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070012763 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070012764 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12765 break;
Damien Lespiau830c81d2014-11-13 17:51:46 +000012766 case 9:
12767 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12768 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070012769 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020012770
12771 intel_panel_init_backlight_funcs(dev);
Ville Syrjäläe39b9992014-09-04 14:53:14 +030012772
12773 mutex_init(&dev_priv->pps_mutex);
Jesse Barnese70236a2009-09-21 10:42:27 -070012774}
12775
Jesse Barnesb690e962010-07-19 13:53:12 -070012776/*
12777 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12778 * resume, or other times. This quirk makes sure that's the case for
12779 * affected systems.
12780 */
Akshay Joshi0206e352011-08-16 15:34:10 -040012781static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070012782{
12783 struct drm_i915_private *dev_priv = dev->dev_private;
12784
12785 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012786 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012787}
12788
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030012789static void quirk_pipeb_force(struct drm_device *dev)
12790{
12791 struct drm_i915_private *dev_priv = dev->dev_private;
12792
12793 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12794 DRM_INFO("applying pipe b force quirk\n");
12795}
12796
Keith Packard435793d2011-07-12 14:56:22 -070012797/*
12798 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12799 */
12800static void quirk_ssc_force_disable(struct drm_device *dev)
12801{
12802 struct drm_i915_private *dev_priv = dev->dev_private;
12803 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012804 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070012805}
12806
Carsten Emde4dca20e2012-03-15 15:56:26 +010012807/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010012808 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12809 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010012810 */
12811static void quirk_invert_brightness(struct drm_device *dev)
12812{
12813 struct drm_i915_private *dev_priv = dev->dev_private;
12814 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020012815 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070012816}
12817
Scot Doyle9c72cc62014-07-03 23:27:50 +000012818/* Some VBT's incorrectly indicate no backlight is present */
12819static void quirk_backlight_present(struct drm_device *dev)
12820{
12821 struct drm_i915_private *dev_priv = dev->dev_private;
12822 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12823 DRM_INFO("applying backlight present quirk\n");
12824}
12825
Jesse Barnesb690e962010-07-19 13:53:12 -070012826struct intel_quirk {
12827 int device;
12828 int subsystem_vendor;
12829 int subsystem_device;
12830 void (*hook)(struct drm_device *dev);
12831};
12832
Egbert Eich5f85f1762012-10-14 15:46:38 +020012833/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12834struct intel_dmi_quirk {
12835 void (*hook)(struct drm_device *dev);
12836 const struct dmi_system_id (*dmi_id_list)[];
12837};
12838
12839static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12840{
12841 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12842 return 1;
12843}
12844
12845static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12846 {
12847 .dmi_id_list = &(const struct dmi_system_id[]) {
12848 {
12849 .callback = intel_dmi_reverse_brightness,
12850 .ident = "NCR Corporation",
12851 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12852 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12853 },
12854 },
12855 { } /* terminating entry */
12856 },
12857 .hook = quirk_invert_brightness,
12858 },
12859};
12860
Ben Widawskyc43b5632012-04-16 14:07:40 -070012861static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070012862 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040012863 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070012864
Jesse Barnesb690e962010-07-19 13:53:12 -070012865 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12866 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12867
Jesse Barnesb690e962010-07-19 13:53:12 -070012868 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12869 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12870
Ville Syrjälä5f080c02014-08-15 01:22:06 +030012871 /* 830 needs to leave pipe A & dpll A up */
12872 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12873
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030012874 /* 830 needs to leave pipe B & dpll B up */
12875 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12876
Keith Packard435793d2011-07-12 14:56:22 -070012877 /* Lenovo U160 cannot use SSC on LVDS */
12878 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020012879
12880 /* Sony Vaio Y cannot use SSC on LVDS */
12881 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010012882
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010012883 /* Acer Aspire 5734Z must invert backlight brightness */
12884 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12885
12886 /* Acer/eMachines G725 */
12887 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12888
12889 /* Acer/eMachines e725 */
12890 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12891
12892 /* Acer/Packard Bell NCL20 */
12893 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12894
12895 /* Acer Aspire 4736Z */
12896 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020012897
12898 /* Acer Aspire 5336 */
12899 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000012900
12901 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12902 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000012903
Scot Doyledfb3d47b2014-08-21 16:08:02 +000012904 /* Acer C720 Chromebook (Core i3 4005U) */
12905 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12906
Scot Doyled4967d82014-07-03 23:27:52 +000012907 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12908 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000012909
12910 /* HP Chromebook 14 (Celeron 2955U) */
12911 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070012912};
12913
12914static void intel_init_quirks(struct drm_device *dev)
12915{
12916 struct pci_dev *d = dev->pdev;
12917 int i;
12918
12919 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12920 struct intel_quirk *q = &intel_quirks[i];
12921
12922 if (d->device == q->device &&
12923 (d->subsystem_vendor == q->subsystem_vendor ||
12924 q->subsystem_vendor == PCI_ANY_ID) &&
12925 (d->subsystem_device == q->subsystem_device ||
12926 q->subsystem_device == PCI_ANY_ID))
12927 q->hook(dev);
12928 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020012929 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12930 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12931 intel_dmi_quirks[i].hook(dev);
12932 }
Jesse Barnesb690e962010-07-19 13:53:12 -070012933}
12934
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012935/* Disable the VGA plane that we never use */
12936static void i915_disable_vga(struct drm_device *dev)
12937{
12938 struct drm_i915_private *dev_priv = dev->dev_private;
12939 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020012940 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012941
Ville Syrjälä2b37c612014-01-22 21:32:38 +020012942 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012943 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070012944 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012945 sr1 = inb(VGA_SR_DATA);
12946 outb(sr1 | 1<<5, VGA_SR_DATA);
12947 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12948 udelay(300);
12949
Ville Syrjälä69769f92014-08-15 01:22:08 +030012950 /*
12951 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12952 * from S3 without preserving (some of?) the other bits.
12953 */
12954 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070012955 POSTING_READ(vga_reg);
12956}
12957
Daniel Vetterf8175862012-04-10 15:50:11 +020012958void intel_modeset_init_hw(struct drm_device *dev)
12959{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030012960 intel_prepare_ddi(dev);
12961
Ville Syrjäläf8bf63f2014-06-13 13:37:54 +030012962 if (IS_VALLEYVIEW(dev))
12963 vlv_update_cdclk(dev);
12964
Daniel Vetterf8175862012-04-10 15:50:11 +020012965 intel_init_clock_gating(dev);
12966
Daniel Vetter8090c6b2012-06-24 16:42:32 +020012967 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020012968}
12969
Jesse Barnes79e53942008-11-07 14:24:08 -080012970void intel_modeset_init(struct drm_device *dev)
12971{
Jesse Barnes652c3932009-08-17 13:31:43 -070012972 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000012973 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000012974 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080012975 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080012976
12977 drm_mode_config_init(dev);
12978
12979 dev->mode_config.min_width = 0;
12980 dev->mode_config.min_height = 0;
12981
Dave Airlie019d96c2011-09-29 16:20:42 +010012982 dev->mode_config.preferred_depth = 24;
12983 dev->mode_config.prefer_shadow = 1;
12984
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020012985 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080012986
Jesse Barnesb690e962010-07-19 13:53:12 -070012987 intel_init_quirks(dev);
12988
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030012989 intel_init_pm(dev);
12990
Ben Widawskye3c74752013-04-05 13:12:39 -070012991 if (INTEL_INFO(dev)->num_pipes == 0)
12992 return;
12993
Jesse Barnese70236a2009-09-21 10:42:27 -070012994 intel_init_display(dev);
Jani Nikula7c10a2b2014-10-27 16:26:43 +020012995 intel_init_audio(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070012996
Chris Wilsona6c45cf2010-09-17 00:32:17 +010012997 if (IS_GEN2(dev)) {
12998 dev->mode_config.max_width = 2048;
12999 dev->mode_config.max_height = 2048;
13000 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070013001 dev->mode_config.max_width = 4096;
13002 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080013003 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010013004 dev->mode_config.max_width = 8192;
13005 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080013006 }
Damien Lespiau068be562014-03-28 14:17:49 +000013007
Ville Syrjälädc41c152014-08-13 11:57:05 +030013008 if (IS_845G(dev) || IS_I865G(dev)) {
13009 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13010 dev->mode_config.cursor_height = 1023;
13011 } else if (IS_GEN2(dev)) {
Damien Lespiau068be562014-03-28 14:17:49 +000013012 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13013 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13014 } else {
13015 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13016 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13017 }
13018
Ben Widawsky5d4545a2013-01-17 12:45:15 -080013019 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080013020
Zhao Yakui28c97732009-10-09 11:39:41 +080013021 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070013022 INTEL_INFO(dev)->num_pipes,
13023 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080013024
Damien Lespiau055e3932014-08-18 13:49:10 +010013025 for_each_pipe(dev_priv, pipe) {
Damien Lespiau8cc87b72014-03-03 17:31:44 +000013026 intel_crtc_init(dev, pipe);
Damien Lespiau1fe47782014-03-03 17:31:47 +000013027 for_each_sprite(pipe, sprite) {
13028 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070013029 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030013030 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000013031 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070013032 }
Jesse Barnes79e53942008-11-07 14:24:08 -080013033 }
13034
Jesse Barnesf42bb702013-12-16 16:34:23 -080013035 intel_init_dpio(dev);
13036
Daniel Vettere72f9fb2013-06-05 13:34:06 +020013037 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010013038
Ville Syrjälä69769f92014-08-15 01:22:08 +030013039 /* save the BIOS value before clobbering it */
13040 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
Jesse Barnes9cce37f2010-08-13 15:11:26 -070013041 /* Just disable it once at startup */
13042 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080013043 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000013044
13045 /* Just in case the BIOS is doing something questionable. */
13046 intel_disable_fbc(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080013047
Daniel Vetter6e9f7982014-05-29 23:54:47 +020013048 drm_modeset_lock_all(dev);
Jesse Barnesfa9fa082014-02-11 15:28:56 -080013049 intel_modeset_setup_hw_state(dev, false);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020013050 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080013051
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013052 for_each_intel_crtc(dev, crtc) {
Jesse Barnes46f297f2014-03-07 08:57:48 -080013053 if (!crtc->active)
13054 continue;
13055
Jesse Barnes46f297f2014-03-07 08:57:48 -080013056 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080013057 * Note that reserving the BIOS fb up front prevents us
13058 * from stuffing other stolen allocations like the ring
13059 * on top. This prevents some ugliness at boot time, and
13060 * can even allow for smooth boot transitions if the BIOS
13061 * fb is large enough for the active pipe configuration.
13062 */
13063 if (dev_priv->display.get_plane_config) {
13064 dev_priv->display.get_plane_config(crtc,
13065 &crtc->plane_config);
13066 /*
13067 * If the fb is shared between multiple heads, we'll
13068 * just get the first one.
13069 */
Jesse Barnes484b41d2014-03-07 08:57:55 -080013070 intel_find_plane_obj(crtc, &crtc->plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080013071 }
Jesse Barnes46f297f2014-03-07 08:57:48 -080013072 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010013073}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080013074
Daniel Vetter7fad7982012-07-04 17:51:47 +020013075static void intel_enable_pipe_a(struct drm_device *dev)
13076{
13077 struct intel_connector *connector;
13078 struct drm_connector *crt = NULL;
13079 struct intel_load_detect_pipe load_detect_temp;
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030013080 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020013081
13082 /* We can't just switch on the pipe A, we need to set things up with a
13083 * proper mode and output configuration. As a gross hack, enable pipe A
13084 * by enabling the load detect pipe once. */
13085 list_for_each_entry(connector,
13086 &dev->mode_config.connector_list,
13087 base.head) {
13088 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13089 crt = &connector->base;
13090 break;
13091 }
13092 }
13093
13094 if (!crt)
13095 return;
13096
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030013097 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13098 intel_release_load_detect_pipe(crt, &load_detect_temp);
Daniel Vetter7fad7982012-07-04 17:51:47 +020013099}
13100
Daniel Vetterfa555832012-10-10 23:14:00 +020013101static bool
13102intel_check_plane_mapping(struct intel_crtc *crtc)
13103{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070013104 struct drm_device *dev = crtc->base.dev;
13105 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020013106 u32 reg, val;
13107
Ben Widawsky7eb552a2013-03-13 14:05:41 -070013108 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020013109 return true;
13110
13111 reg = DSPCNTR(!crtc->plane);
13112 val = I915_READ(reg);
13113
13114 if ((val & DISPLAY_PLANE_ENABLE) &&
13115 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13116 return false;
13117
13118 return true;
13119}
13120
Daniel Vetter24929352012-07-02 20:28:59 +020013121static void intel_sanitize_crtc(struct intel_crtc *crtc)
13122{
13123 struct drm_device *dev = crtc->base.dev;
13124 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020013125 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020013126
Daniel Vetter24929352012-07-02 20:28:59 +020013127 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020013128 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020013129 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13130
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030013131 /* restore vblank interrupts to correct state */
Ville Syrjäläd297e102014-08-06 14:50:01 +030013132 if (crtc->active) {
13133 update_scanline_offset(crtc);
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030013134 drm_vblank_on(dev, crtc->pipe);
Ville Syrjäläd297e102014-08-06 14:50:01 +030013135 } else
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030013136 drm_vblank_off(dev, crtc->pipe);
13137
Daniel Vetter24929352012-07-02 20:28:59 +020013138 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020013139 * disable the crtc (and hence change the state) if it is wrong. Note
13140 * that gen4+ has a fixed plane -> pipe mapping. */
13141 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020013142 struct intel_connector *connector;
13143 bool plane;
13144
Daniel Vetter24929352012-07-02 20:28:59 +020013145 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13146 crtc->base.base.id);
13147
13148 /* Pipe has the wrong plane attached and the plane is active.
13149 * Temporarily change the plane mapping and disable everything
13150 * ... */
13151 plane = crtc->plane;
13152 crtc->plane = !plane;
Daniel Vetter9c8958b2014-07-14 19:35:31 +020013153 crtc->primary_enabled = true;
Daniel Vetter24929352012-07-02 20:28:59 +020013154 dev_priv->display.crtc_disable(&crtc->base);
13155 crtc->plane = plane;
13156
13157 /* ... and break all links. */
13158 list_for_each_entry(connector, &dev->mode_config.connector_list,
13159 base.head) {
13160 if (connector->encoder->base.crtc != &crtc->base)
13161 continue;
13162
Egbert Eich7f1950f2014-04-25 10:56:22 +020013163 connector->base.dpms = DRM_MODE_DPMS_OFF;
13164 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020013165 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020013166 /* multiple connectors may have the same encoder:
13167 * handle them and break crtc link separately */
13168 list_for_each_entry(connector, &dev->mode_config.connector_list,
13169 base.head)
13170 if (connector->encoder->base.crtc == &crtc->base) {
13171 connector->encoder->base.crtc = NULL;
13172 connector->encoder->connectors_active = false;
13173 }
Daniel Vetter24929352012-07-02 20:28:59 +020013174
13175 WARN_ON(crtc->active);
13176 crtc->base.enabled = false;
13177 }
Daniel Vetter24929352012-07-02 20:28:59 +020013178
Daniel Vetter7fad7982012-07-04 17:51:47 +020013179 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13180 crtc->pipe == PIPE_A && !crtc->active) {
13181 /* BIOS forgot to enable pipe A, this mostly happens after
13182 * resume. Force-enable the pipe to fix this, the update_dpms
13183 * call below we restore the pipe to the right state, but leave
13184 * the required bits on. */
13185 intel_enable_pipe_a(dev);
13186 }
13187
Daniel Vetter24929352012-07-02 20:28:59 +020013188 /* Adjust the state of the output pipe according to whether we
13189 * have active connectors/encoders. */
13190 intel_crtc_update_dpms(&crtc->base);
13191
13192 if (crtc->active != crtc->base.enabled) {
13193 struct intel_encoder *encoder;
13194
13195 /* This can happen either due to bugs in the get_hw_state
13196 * functions or because the pipe is force-enabled due to the
13197 * pipe A quirk. */
13198 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13199 crtc->base.base.id,
13200 crtc->base.enabled ? "enabled" : "disabled",
13201 crtc->active ? "enabled" : "disabled");
13202
13203 crtc->base.enabled = crtc->active;
13204
13205 /* Because we only establish the connector -> encoder ->
13206 * crtc links if something is active, this means the
13207 * crtc is now deactivated. Break the links. connector
13208 * -> encoder links are only establish when things are
13209 * actually up, hence no need to break them. */
13210 WARN_ON(crtc->active);
13211
13212 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13213 WARN_ON(encoder->connectors_active);
13214 encoder->base.crtc = NULL;
13215 }
13216 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020013217
Ville Syrjäläa3ed6aa2014-09-03 14:09:52 +030013218 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010013219 /*
13220 * We start out with underrun reporting disabled to avoid races.
13221 * For correct bookkeeping mark this on active crtcs.
13222 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020013223 * Also on gmch platforms we dont have any hardware bits to
13224 * disable the underrun reporting. Which means we need to start
13225 * out with underrun reporting disabled also on inactive pipes,
13226 * since otherwise we'll complain about the garbage we read when
13227 * e.g. coming up after runtime pm.
13228 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010013229 * No protection against concurrent access is required - at
13230 * worst a fifo underrun happens which also sets this to false.
13231 */
13232 crtc->cpu_fifo_underrun_disabled = true;
13233 crtc->pch_fifo_underrun_disabled = true;
13234 }
Daniel Vetter24929352012-07-02 20:28:59 +020013235}
13236
13237static void intel_sanitize_encoder(struct intel_encoder *encoder)
13238{
13239 struct intel_connector *connector;
13240 struct drm_device *dev = encoder->base.dev;
13241
13242 /* We need to check both for a crtc link (meaning that the
13243 * encoder is active and trying to read from a pipe) and the
13244 * pipe itself being active. */
13245 bool has_active_crtc = encoder->base.crtc &&
13246 to_intel_crtc(encoder->base.crtc)->active;
13247
13248 if (encoder->connectors_active && !has_active_crtc) {
13249 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13250 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013251 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020013252
13253 /* Connector is active, but has no active pipe. This is
13254 * fallout from our resume register restoring. Disable
13255 * the encoder manually again. */
13256 if (encoder->base.crtc) {
13257 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13258 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013259 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020013260 encoder->disable(encoder);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030013261 if (encoder->post_disable)
13262 encoder->post_disable(encoder);
Daniel Vetter24929352012-07-02 20:28:59 +020013263 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020013264 encoder->base.crtc = NULL;
13265 encoder->connectors_active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020013266
13267 /* Inconsistent output/port/pipe state happens presumably due to
13268 * a bug in one of the get_hw_state functions. Or someplace else
13269 * in our code, like the register restore mess on resume. Clamp
13270 * things to off as a safer default. */
13271 list_for_each_entry(connector,
13272 &dev->mode_config.connector_list,
13273 base.head) {
13274 if (connector->encoder != encoder)
13275 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020013276 connector->base.dpms = DRM_MODE_DPMS_OFF;
13277 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020013278 }
13279 }
13280 /* Enabled encoders without active connectors will be fixed in
13281 * the crtc fixup. */
13282}
13283
Imre Deak04098752014-02-18 00:02:16 +020013284void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013285{
13286 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020013287 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013288
Imre Deak04098752014-02-18 00:02:16 +020013289 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13290 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13291 i915_disable_vga(dev);
13292 }
13293}
13294
13295void i915_redisable_vga(struct drm_device *dev)
13296{
13297 struct drm_i915_private *dev_priv = dev->dev_private;
13298
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013299 /* This function can be called both from intel_modeset_setup_hw_state or
13300 * at a very early point in our resume sequence, where the power well
13301 * structures are not yet restored. Since this function is at a very
13302 * paranoid "someone might have enabled VGA while we were not looking"
13303 * level, just check if the power well is enabled instead of trying to
13304 * follow the "don't touch the power well if we don't need it" policy
13305 * the rest of the driver uses. */
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013306 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030013307 return;
13308
Imre Deak04098752014-02-18 00:02:16 +020013309 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010013310}
13311
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013312static bool primary_get_hw_state(struct intel_crtc *crtc)
13313{
13314 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13315
13316 if (!crtc->active)
13317 return false;
13318
13319 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13320}
13321
Daniel Vetter30e984d2013-06-05 13:34:17 +020013322static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020013323{
13324 struct drm_i915_private *dev_priv = dev->dev_private;
13325 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020013326 struct intel_crtc *crtc;
13327 struct intel_encoder *encoder;
13328 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020013329 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020013330
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013331 for_each_intel_crtc(dev, crtc) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010013332 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020013333
Daniel Vetter99535992014-04-13 12:00:33 +020013334 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13335
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010013336 crtc->active = dev_priv->display.get_pipe_config(crtc,
13337 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013338
13339 crtc->base.enabled = crtc->active;
Ville Syrjälä98ec7732014-04-30 17:43:01 +030013340 crtc->primary_enabled = primary_get_hw_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020013341
13342 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13343 crtc->base.base.id,
13344 crtc->active ? "enabled" : "disabled");
13345 }
13346
Daniel Vetter53589012013-06-05 13:34:16 +020013347 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13348 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13349
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013350 pll->on = pll->get_hw_state(dev_priv, pll,
13351 &pll->config.hw_state);
Daniel Vetter53589012013-06-05 13:34:16 +020013352 pll->active = 0;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013353 pll->config.crtc_mask = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013354 for_each_intel_crtc(dev, crtc) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013355 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
Daniel Vetter53589012013-06-05 13:34:16 +020013356 pll->active++;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013357 pll->config.crtc_mask |= 1 << crtc->pipe;
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013358 }
Daniel Vetter53589012013-06-05 13:34:16 +020013359 }
Daniel Vetter53589012013-06-05 13:34:16 +020013360
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020013361 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013362 pll->name, pll->config.crtc_mask, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013363
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013364 if (pll->config.crtc_mask)
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013365 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020013366 }
13367
Damien Lespiaub2784e12014-08-05 11:29:37 +010013368 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013369 pipe = 0;
13370
13371 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070013372 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13373 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010013374 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020013375 } else {
13376 encoder->base.crtc = NULL;
13377 }
13378
13379 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013380 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020013381 encoder->base.base.id,
Jani Nikula8e329a02014-06-03 14:56:21 +030013382 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013383 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010013384 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020013385 }
13386
13387 list_for_each_entry(connector, &dev->mode_config.connector_list,
13388 base.head) {
13389 if (connector->get_hw_state(connector)) {
13390 connector->base.dpms = DRM_MODE_DPMS_ON;
13391 connector->encoder->connectors_active = true;
13392 connector->base.encoder = &connector->encoder->base;
13393 } else {
13394 connector->base.dpms = DRM_MODE_DPMS_OFF;
13395 connector->base.encoder = NULL;
13396 }
13397 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13398 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030013399 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020013400 connector->base.encoder ? "enabled" : "disabled");
13401 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020013402}
13403
13404/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13405 * and i915 state tracking structures. */
13406void intel_modeset_setup_hw_state(struct drm_device *dev,
13407 bool force_restore)
13408{
13409 struct drm_i915_private *dev_priv = dev->dev_private;
13410 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013411 struct intel_crtc *crtc;
13412 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020013413 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020013414
13415 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020013416
Jesse Barnesbabea612013-06-26 18:57:38 +030013417 /*
13418 * Now that we have the config, copy it to each CRTC struct
13419 * Note that this could go away if we move to using crtc_config
13420 * checking everywhere.
13421 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013422 for_each_intel_crtc(dev, crtc) {
Jani Nikulad330a952014-01-21 11:24:25 +020013423 if (crtc->active && i915.fastboot) {
Daniel Vetterf6a83282014-02-11 15:28:57 -080013424 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
Jesse Barnesbabea612013-06-26 18:57:38 +030013425 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13426 crtc->base.base.id);
13427 drm_mode_debug_printmodeline(&crtc->base.mode);
13428 }
13429 }
13430
Daniel Vetter24929352012-07-02 20:28:59 +020013431 /* HW state is read out, now we need to sanitize this mess. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010013432 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020013433 intel_sanitize_encoder(encoder);
13434 }
13435
Damien Lespiau055e3932014-08-18 13:49:10 +010013436 for_each_pipe(dev_priv, pipe) {
Daniel Vetter24929352012-07-02 20:28:59 +020013437 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13438 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020013439 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020013440 }
Daniel Vetter9a935852012-07-05 22:34:27 +020013441
Daniel Vetter35c95372013-07-17 06:55:04 +020013442 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13443 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13444
13445 if (!pll->on || pll->active)
13446 continue;
13447
13448 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13449
13450 pll->disable(dev_priv, pll);
13451 pll->on = false;
13452 }
13453
Pradeep Bhat30789992014-11-04 17:06:45 +000013454 if (IS_GEN9(dev))
13455 skl_wm_get_hw_state(dev);
13456 else if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030013457 ilk_wm_get_hw_state(dev);
13458
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013459 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030013460 i915_redisable_vga(dev);
13461
Daniel Vetterf30da182013-04-11 20:22:50 +020013462 /*
13463 * We need to use raw interfaces for restoring state to avoid
13464 * checking (bogus) intermediate states.
13465 */
Damien Lespiau055e3932014-08-18 13:49:10 +010013466 for_each_pipe(dev_priv, pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070013467 struct drm_crtc *crtc =
13468 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020013469
Jesse Barnes7f271262014-11-05 14:26:06 -080013470 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13471 crtc->primary->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010013472 }
13473 } else {
13474 intel_modeset_update_staged_output_state(dev);
13475 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020013476
13477 intel_modeset_check_state(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010013478}
13479
13480void intel_modeset_gem_init(struct drm_device *dev)
13481{
Jesse Barnes92122782014-10-09 12:57:42 -070013482 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013483 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070013484 struct drm_i915_gem_object *obj;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013485
Imre Deakae484342014-03-31 15:10:44 +030013486 mutex_lock(&dev->struct_mutex);
13487 intel_init_gt_powersave(dev);
13488 mutex_unlock(&dev->struct_mutex);
13489
Jesse Barnes92122782014-10-09 12:57:42 -070013490 /*
13491 * There may be no VBT; and if the BIOS enabled SSC we can
13492 * just keep using it to avoid unnecessary flicker. Whereas if the
13493 * BIOS isn't using it, don't assume it will work even if the VBT
13494 * indicates as much.
13495 */
13496 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13497 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13498 DREF_SSC1_ENABLE);
13499
Chris Wilson1833b132012-05-09 11:56:28 +010013500 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020013501
13502 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080013503
13504 /*
13505 * Make sure any fbs we allocated at startup are properly
13506 * pinned & fenced. When we do the allocation it's too early
13507 * for this.
13508 */
13509 mutex_lock(&dev->struct_mutex);
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010013510 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070013511 obj = intel_fb_obj(c->primary->fb);
13512 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080013513 continue;
13514
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +000013515 if (intel_pin_and_fence_fb_obj(c->primary,
13516 c->primary->fb,
13517 NULL)) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080013518 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13519 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100013520 drm_framebuffer_unreference(c->primary->fb);
13521 c->primary->fb = NULL;
Jesse Barnes484b41d2014-03-07 08:57:55 -080013522 }
13523 }
13524 mutex_unlock(&dev->struct_mutex);
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020013525
13526 intel_backlight_register(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080013527}
13528
Imre Deak4932e2c2014-02-11 17:12:48 +020013529void intel_connector_unregister(struct intel_connector *intel_connector)
13530{
13531 struct drm_connector *connector = &intel_connector->base;
13532
13533 intel_panel_destroy_backlight(connector);
Thomas Wood34ea3d32014-05-29 16:57:41 +010013534 drm_connector_unregister(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020013535}
13536
Jesse Barnes79e53942008-11-07 14:24:08 -080013537void intel_modeset_cleanup(struct drm_device *dev)
13538{
Jesse Barnes652c3932009-08-17 13:31:43 -070013539 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid9255d52013-09-26 20:05:59 -030013540 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070013541
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020013542 intel_backlight_unregister(dev);
13543
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013544 /*
13545 * Interrupts and polling as the first thing to avoid creating havoc.
13546 * Too much stuff here (turning of rps, connectors, ...) would
13547 * experience fancy races otherwise.
13548 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +020013549 intel_irq_uninstall(dev_priv);
Jesse Barneseb21b922014-06-20 11:57:33 -070013550
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013551 /*
13552 * Due to the hpd irq storm handling the hotplug work can re-arm the
13553 * poll handlers. Hence disable polling after hpd handling is shut down.
13554 */
Keith Packardf87ea762010-10-03 19:36:26 -070013555 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020013556
Jesse Barnes652c3932009-08-17 13:31:43 -070013557 mutex_lock(&dev->struct_mutex);
13558
Jesse Barnes723bfd72010-10-07 16:01:13 -070013559 intel_unregister_dsm_handler();
13560
Chris Wilson973d04f2011-07-08 12:22:37 +010013561 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070013562
Daniel Vetter8090c6b2012-06-24 16:42:32 +020013563 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000013564
Daniel Vetter930ebb42012-06-29 23:32:16 +020013565 ironlake_teardown_rc6(dev);
13566
Kristian Høgsberg69341a52009-11-11 12:19:17 -050013567 mutex_unlock(&dev->struct_mutex);
13568
Chris Wilson1630fe72011-07-08 12:22:42 +010013569 /* flush any delayed tasks or pending work */
13570 flush_scheduled_work();
13571
Jani Nikuladb31af12013-11-08 16:48:53 +020013572 /* destroy the backlight and sysfs files before encoders/connectors */
13573 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Imre Deak4932e2c2014-02-11 17:12:48 +020013574 struct intel_connector *intel_connector;
13575
13576 intel_connector = to_intel_connector(connector);
13577 intel_connector->unregister(intel_connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020013578 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030013579
Jesse Barnes79e53942008-11-07 14:24:08 -080013580 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010013581
13582 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030013583
13584 mutex_lock(&dev->struct_mutex);
13585 intel_cleanup_gt_powersave(dev);
13586 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080013587}
13588
Dave Airlie28d52042009-09-21 14:33:58 +100013589/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080013590 * Return which encoder is currently attached for connector.
13591 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010013592struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080013593{
Chris Wilsondf0e9242010-09-09 16:20:55 +010013594 return &intel_attached_encoder(connector)->base;
13595}
Jesse Barnes79e53942008-11-07 14:24:08 -080013596
Chris Wilsondf0e9242010-09-09 16:20:55 +010013597void intel_connector_attach_encoder(struct intel_connector *connector,
13598 struct intel_encoder *encoder)
13599{
13600 connector->encoder = encoder;
13601 drm_mode_connector_attach_encoder(&connector->base,
13602 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080013603}
Dave Airlie28d52042009-09-21 14:33:58 +100013604
13605/*
13606 * set vga decode state - true == enable VGA decode
13607 */
13608int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13609{
13610 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000013611 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100013612 u16 gmch_ctrl;
13613
Chris Wilson75fa0412014-02-07 18:37:02 -020013614 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13615 DRM_ERROR("failed to read control word\n");
13616 return -EIO;
13617 }
13618
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020013619 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13620 return 0;
13621
Dave Airlie28d52042009-09-21 14:33:58 +100013622 if (state)
13623 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13624 else
13625 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020013626
13627 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13628 DRM_ERROR("failed to write control word\n");
13629 return -EIO;
13630 }
13631
Dave Airlie28d52042009-09-21 14:33:58 +100013632 return 0;
13633}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013634
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013635struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013636
13637 u32 power_well_driver;
13638
Chris Wilson63b66e52013-08-08 15:12:06 +020013639 int num_transcoders;
13640
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013641 struct intel_cursor_error_state {
13642 u32 control;
13643 u32 position;
13644 u32 base;
13645 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010013646 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013647
13648 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013649 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013650 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030013651 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010013652 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013653
13654 struct intel_plane_error_state {
13655 u32 control;
13656 u32 stride;
13657 u32 size;
13658 u32 pos;
13659 u32 addr;
13660 u32 surface;
13661 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010013662 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020013663
13664 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020013665 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020013666 enum transcoder cpu_transcoder;
13667
13668 u32 conf;
13669
13670 u32 htotal;
13671 u32 hblank;
13672 u32 hsync;
13673 u32 vtotal;
13674 u32 vblank;
13675 u32 vsync;
13676 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013677};
13678
13679struct intel_display_error_state *
13680intel_display_capture_error_state(struct drm_device *dev)
13681{
Jani Nikulafbee40d2014-03-31 14:27:18 +030013682 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013683 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020013684 int transcoders[] = {
13685 TRANSCODER_A,
13686 TRANSCODER_B,
13687 TRANSCODER_C,
13688 TRANSCODER_EDP,
13689 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013690 int i;
13691
Chris Wilson63b66e52013-08-08 15:12:06 +020013692 if (INTEL_INFO(dev)->num_pipes == 0)
13693 return NULL;
13694
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013695 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013696 if (error == NULL)
13697 return NULL;
13698
Imre Deak190be112013-11-25 17:15:31 +020013699 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013700 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13701
Damien Lespiau055e3932014-08-18 13:49:10 +010013702 for_each_pipe(dev_priv, i) {
Imre Deakddf9c532013-11-27 22:02:02 +020013703 error->pipe[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013704 __intel_display_power_is_enabled(dev_priv,
13705 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020013706 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013707 continue;
13708
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030013709 error->cursor[i].control = I915_READ(CURCNTR(i));
13710 error->cursor[i].position = I915_READ(CURPOS(i));
13711 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013712
13713 error->plane[i].control = I915_READ(DSPCNTR(i));
13714 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013715 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030013716 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013717 error->plane[i].pos = I915_READ(DSPPOS(i));
13718 }
Paulo Zanonica291362013-03-06 20:03:14 -030013719 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13720 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013721 if (INTEL_INFO(dev)->gen >= 4) {
13722 error->plane[i].surface = I915_READ(DSPSURF(i));
13723 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13724 }
13725
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013726 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030013727
Sonika Jindal3abfce72014-07-21 15:23:43 +053013728 if (HAS_GMCH_DISPLAY(dev))
Imre Deakf301b1e2014-04-18 15:55:04 +030013729 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020013730 }
13731
13732 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13733 if (HAS_DDI(dev_priv->dev))
13734 error->num_transcoders++; /* Account for eDP. */
13735
13736 for (i = 0; i < error->num_transcoders; i++) {
13737 enum transcoder cpu_transcoder = transcoders[i];
13738
Imre Deakddf9c532013-11-27 22:02:02 +020013739 error->transcoder[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013740 __intel_display_power_is_enabled(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020013741 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013742 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020013743 continue;
13744
Chris Wilson63b66e52013-08-08 15:12:06 +020013745 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13746
13747 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13748 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13749 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13750 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13751 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13752 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13753 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013754 }
13755
13756 return error;
13757}
13758
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013759#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13760
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013761void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013762intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013763 struct drm_device *dev,
13764 struct intel_display_error_state *error)
13765{
Damien Lespiau055e3932014-08-18 13:49:10 +010013766 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013767 int i;
13768
Chris Wilson63b66e52013-08-08 15:12:06 +020013769 if (!error)
13770 return;
13771
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013772 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020013773 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013774 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030013775 error->power_well_driver);
Damien Lespiau055e3932014-08-18 13:49:10 +010013776 for_each_pipe(dev_priv, i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013777 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020013778 err_printf(m, " Power: %s\n",
13779 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013780 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030013781 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013782
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013783 err_printf(m, "Plane [%d]:\n", i);
13784 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13785 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013786 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013787 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13788 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030013789 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030013790 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013791 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013792 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013793 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13794 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013795 }
13796
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030013797 err_printf(m, "Cursor [%d]:\n", i);
13798 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13799 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13800 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013801 }
Chris Wilson63b66e52013-08-08 15:12:06 +020013802
13803 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010013804 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020013805 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020013806 err_printf(m, " Power: %s\n",
13807 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020013808 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13809 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13810 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13811 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13812 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13813 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13814 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13815 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000013816}
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013817
13818void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13819{
13820 struct intel_crtc *crtc;
13821
13822 for_each_intel_crtc(dev, crtc) {
13823 struct intel_unpin_work *work;
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013824
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020013825 spin_lock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013826
13827 work = crtc->unpin_work;
13828
13829 if (work && work->event &&
13830 work->event->base.file_priv == file) {
13831 kfree(work->event);
13832 work->event = NULL;
13833 }
13834
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020013835 spin_unlock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030013836 }
13837}