blob: 536efa277b0131a857d0a30e1481478709c34f4f [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Joe Perchesa70491c2012-03-18 13:00:11 -070029#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
Jesse Barnes63eeaf32009-06-18 16:56:52 -070031#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Damien Lespiaub2c88f52013-10-15 18:55:29 +010033#include <linux/circ_buf.h>
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/drmP.h>
35#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010037#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Daniel Vetterfca52a52014-09-30 10:56:45 +020040/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
Egbert Eiche5868a32013-02-28 04:17:12 -050048static const u32 hpd_ibx[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54};
55
56static const u32 hpd_cpt[] = {
57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
Daniel Vetter73c352a2013-03-26 22:38:43 +010058 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
Egbert Eiche5868a32013-02-28 04:17:12 -050059 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62};
63
64static const u32 hpd_mask_i915[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71};
72
Daniel Vetter704cfb82013-12-18 09:08:43 +010073static const u32 hpd_status_g4x[] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050074 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
Egbert Eiche5868a32013-02-28 04:17:12 -050082static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
Paulo Zanoni5c502442014-04-01 15:37:11 -030091/* IIR can theoretically queue up two events. Be paranoid. */
Paulo Zanonif86f3fb2014-04-01 15:37:14 -030092#define GEN8_IRQ_RESET_NDX(type, which) do { \
Paulo Zanoni5c502442014-04-01 15:37:11 -030093 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
94 POSTING_READ(GEN8_##type##_IMR(which)); \
95 I915_WRITE(GEN8_##type##_IER(which), 0); \
96 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
97 POSTING_READ(GEN8_##type##_IIR(which)); \
98 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
99 POSTING_READ(GEN8_##type##_IIR(which)); \
100} while (0)
101
Paulo Zanonif86f3fb2014-04-01 15:37:14 -0300102#define GEN5_IRQ_RESET(type) do { \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300103 I915_WRITE(type##IMR, 0xffffffff); \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300104 POSTING_READ(type##IMR); \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300105 I915_WRITE(type##IER, 0); \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300106 I915_WRITE(type##IIR, 0xffffffff); \
107 POSTING_READ(type##IIR); \
108 I915_WRITE(type##IIR, 0xffffffff); \
109 POSTING_READ(type##IIR); \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300110} while (0)
111
Paulo Zanoni337ba012014-04-01 15:37:16 -0300112/*
113 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
114 */
115#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
116 u32 val = I915_READ(reg); \
117 if (val) { \
118 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
119 (reg), val); \
120 I915_WRITE((reg), 0xffffffff); \
121 POSTING_READ(reg); \
122 I915_WRITE((reg), 0xffffffff); \
123 POSTING_READ(reg); \
124 } \
125} while (0)
126
Paulo Zanoni35079892014-04-01 15:37:15 -0300127#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
Paulo Zanoni337ba012014-04-01 15:37:16 -0300128 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300129 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
130 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
131 POSTING_READ(GEN8_##type##_IER(which)); \
132} while (0)
133
134#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
Paulo Zanoni337ba012014-04-01 15:37:16 -0300135 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300136 I915_WRITE(type##IMR, (imr_val)); \
137 I915_WRITE(type##IER, (ier_val)); \
138 POSTING_READ(type##IER); \
139} while (0)
140
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800141/* For display hotplug interrupt */
Daniel Vetter47339cd2014-09-30 10:56:46 +0200142void
Jani Nikula2d1013d2014-03-31 14:27:17 +0300143ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800144{
Daniel Vetter4bc9d432013-06-27 13:44:58 +0200145 assert_spin_locked(&dev_priv->irq_lock);
146
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700147 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300148 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300149
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000150 if ((dev_priv->irq_mask & mask) != 0) {
151 dev_priv->irq_mask &= ~mask;
152 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000153 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800154 }
155}
156
Daniel Vetter47339cd2014-09-30 10:56:46 +0200157void
Jani Nikula2d1013d2014-03-31 14:27:17 +0300158ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800159{
Daniel Vetter4bc9d432013-06-27 13:44:58 +0200160 assert_spin_locked(&dev_priv->irq_lock);
161
Paulo Zanoni06ffc772014-07-17 17:43:46 -0300162 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300163 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300164
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000165 if ((dev_priv->irq_mask & mask) != mask) {
166 dev_priv->irq_mask |= mask;
167 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000168 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800169 }
170}
171
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300172/**
173 * ilk_update_gt_irq - update GTIMR
174 * @dev_priv: driver private
175 * @interrupt_mask: mask of interrupt bits to update
176 * @enabled_irq_mask: mask of interrupt bits to enable
177 */
178static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
179 uint32_t interrupt_mask,
180 uint32_t enabled_irq_mask)
181{
182 assert_spin_locked(&dev_priv->irq_lock);
183
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700184 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300185 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300186
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300187 dev_priv->gt_irq_mask &= ~interrupt_mask;
188 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
189 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
190 POSTING_READ(GTIMR);
191}
192
Daniel Vetter480c8032014-07-16 09:49:40 +0200193void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300194{
195 ilk_update_gt_irq(dev_priv, mask, mask);
196}
197
Daniel Vetter480c8032014-07-16 09:49:40 +0200198void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300199{
200 ilk_update_gt_irq(dev_priv, mask, 0);
201}
202
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300203/**
204 * snb_update_pm_irq - update GEN6_PMIMR
205 * @dev_priv: driver private
206 * @interrupt_mask: mask of interrupt bits to update
207 * @enabled_irq_mask: mask of interrupt bits to enable
208 */
209static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
210 uint32_t interrupt_mask,
211 uint32_t enabled_irq_mask)
212{
Paulo Zanoni605cd252013-08-06 18:57:15 -0300213 uint32_t new_val;
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300214
215 assert_spin_locked(&dev_priv->irq_lock);
216
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700217 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300218 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300219
Paulo Zanoni605cd252013-08-06 18:57:15 -0300220 new_val = dev_priv->pm_irq_mask;
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300221 new_val &= ~interrupt_mask;
222 new_val |= (~enabled_irq_mask & interrupt_mask);
223
Paulo Zanoni605cd252013-08-06 18:57:15 -0300224 if (new_val != dev_priv->pm_irq_mask) {
225 dev_priv->pm_irq_mask = new_val;
226 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300227 POSTING_READ(GEN6_PMIMR);
228 }
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300229}
230
Daniel Vetter480c8032014-07-16 09:49:40 +0200231void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300232{
233 snb_update_pm_irq(dev_priv, mask, mask);
234}
235
Daniel Vetter480c8032014-07-16 09:49:40 +0200236void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300237{
238 snb_update_pm_irq(dev_priv, mask, 0);
239}
240
Ben Widawsky09610212014-05-15 20:58:08 +0300241/**
242 * bdw_update_pm_irq - update GT interrupt 2
243 * @dev_priv: driver private
244 * @interrupt_mask: mask of interrupt bits to update
245 * @enabled_irq_mask: mask of interrupt bits to enable
246 *
247 * Copied from the snb function, updated with relevant register offsets
248 */
249static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
250 uint32_t interrupt_mask,
251 uint32_t enabled_irq_mask)
252{
253 uint32_t new_val;
254
255 assert_spin_locked(&dev_priv->irq_lock);
256
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Ben Widawsky09610212014-05-15 20:58:08 +0300258 return;
259
260 new_val = dev_priv->pm_irq_mask;
261 new_val &= ~interrupt_mask;
262 new_val |= (~enabled_irq_mask & interrupt_mask);
263
264 if (new_val != dev_priv->pm_irq_mask) {
265 dev_priv->pm_irq_mask = new_val;
266 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
267 POSTING_READ(GEN8_GT_IMR(2));
268 }
269}
270
Daniel Vetter480c8032014-07-16 09:49:40 +0200271void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Ben Widawsky09610212014-05-15 20:58:08 +0300272{
273 bdw_update_pm_irq(dev_priv, mask, mask);
274}
275
Daniel Vetter480c8032014-07-16 09:49:40 +0200276void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Ben Widawsky09610212014-05-15 20:58:08 +0300277{
278 bdw_update_pm_irq(dev_priv, mask, 0);
279}
280
Daniel Vetterfee884e2013-07-04 23:35:21 +0200281/**
282 * ibx_display_interrupt_update - update SDEIMR
283 * @dev_priv: driver private
284 * @interrupt_mask: mask of interrupt bits to update
285 * @enabled_irq_mask: mask of interrupt bits to enable
286 */
Daniel Vetter47339cd2014-09-30 10:56:46 +0200287void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
288 uint32_t interrupt_mask,
289 uint32_t enabled_irq_mask)
Daniel Vetterfee884e2013-07-04 23:35:21 +0200290{
291 uint32_t sdeimr = I915_READ(SDEIMR);
292 sdeimr &= ~interrupt_mask;
293 sdeimr |= (~enabled_irq_mask & interrupt_mask);
294
295 assert_spin_locked(&dev_priv->irq_lock);
296
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700297 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300298 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300299
Daniel Vetterfee884e2013-07-04 23:35:21 +0200300 I915_WRITE(SDEIMR, sdeimr);
301 POSTING_READ(SDEIMR);
302}
Paulo Zanoni86642812013-04-12 17:57:57 -0300303
Daniel Vetterb5ea6422014-03-02 21:18:00 +0100304static void
Imre Deak755e9012014-02-10 18:42:47 +0200305__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
306 u32 enable_mask, u32 status_mask)
Keith Packard7c463582008-11-04 02:03:27 -0800307{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200308 u32 reg = PIPESTAT(pipe);
Imre Deak755e9012014-02-10 18:42:47 +0200309 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
Keith Packard7c463582008-11-04 02:03:27 -0800310
Daniel Vetterb79480b2013-06-27 17:52:10 +0200311 assert_spin_locked(&dev_priv->irq_lock);
Daniel Vetterd518ce52014-08-27 10:43:37 +0200312 WARN_ON(!intel_irqs_enabled(dev_priv));
Daniel Vetterb79480b2013-06-27 17:52:10 +0200313
Ville Syrjälä04feced2014-04-03 13:28:33 +0300314 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
315 status_mask & ~PIPESTAT_INT_STATUS_MASK,
316 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
317 pipe_name(pipe), enable_mask, status_mask))
Imre Deak755e9012014-02-10 18:42:47 +0200318 return;
319
320 if ((pipestat & enable_mask) == enable_mask)
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200321 return;
322
Imre Deak91d181d2014-02-10 18:42:49 +0200323 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
324
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200325 /* Enable the interrupt, clear any pending status */
Imre Deak755e9012014-02-10 18:42:47 +0200326 pipestat |= enable_mask | status_mask;
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200327 I915_WRITE(reg, pipestat);
328 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800329}
330
Daniel Vetterb5ea6422014-03-02 21:18:00 +0100331static void
Imre Deak755e9012014-02-10 18:42:47 +0200332__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
333 u32 enable_mask, u32 status_mask)
Keith Packard7c463582008-11-04 02:03:27 -0800334{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200335 u32 reg = PIPESTAT(pipe);
Imre Deak755e9012014-02-10 18:42:47 +0200336 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
Keith Packard7c463582008-11-04 02:03:27 -0800337
Daniel Vetterb79480b2013-06-27 17:52:10 +0200338 assert_spin_locked(&dev_priv->irq_lock);
Daniel Vetterd518ce52014-08-27 10:43:37 +0200339 WARN_ON(!intel_irqs_enabled(dev_priv));
Daniel Vetterb79480b2013-06-27 17:52:10 +0200340
Ville Syrjälä04feced2014-04-03 13:28:33 +0300341 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
342 status_mask & ~PIPESTAT_INT_STATUS_MASK,
343 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
344 pipe_name(pipe), enable_mask, status_mask))
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200345 return;
346
Imre Deak755e9012014-02-10 18:42:47 +0200347 if ((pipestat & enable_mask) == 0)
348 return;
349
Imre Deak91d181d2014-02-10 18:42:49 +0200350 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
351
Imre Deak755e9012014-02-10 18:42:47 +0200352 pipestat &= ~enable_mask;
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200353 I915_WRITE(reg, pipestat);
354 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800355}
356
Imre Deak10c59c52014-02-10 18:42:48 +0200357static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
358{
359 u32 enable_mask = status_mask << 16;
360
361 /*
Ville Syrjälä724a6902014-04-09 13:28:48 +0300362 * On pipe A we don't support the PSR interrupt yet,
363 * on pipe B and C the same bit MBZ.
Imre Deak10c59c52014-02-10 18:42:48 +0200364 */
365 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
366 return 0;
Ville Syrjälä724a6902014-04-09 13:28:48 +0300367 /*
368 * On pipe B and C we don't support the PSR interrupt yet, on pipe
369 * A the same bit is for perf counters which we don't use either.
370 */
371 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
372 return 0;
Imre Deak10c59c52014-02-10 18:42:48 +0200373
374 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
375 SPRITE0_FLIP_DONE_INT_EN_VLV |
376 SPRITE1_FLIP_DONE_INT_EN_VLV);
377 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
378 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
379 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
380 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
381
382 return enable_mask;
383}
384
Imre Deak755e9012014-02-10 18:42:47 +0200385void
386i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
387 u32 status_mask)
388{
389 u32 enable_mask;
390
Imre Deak10c59c52014-02-10 18:42:48 +0200391 if (IS_VALLEYVIEW(dev_priv->dev))
392 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
393 status_mask);
394 else
395 enable_mask = status_mask << 16;
Imre Deak755e9012014-02-10 18:42:47 +0200396 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
397}
398
399void
400i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
401 u32 status_mask)
402{
403 u32 enable_mask;
404
Imre Deak10c59c52014-02-10 18:42:48 +0200405 if (IS_VALLEYVIEW(dev_priv->dev))
406 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
407 status_mask);
408 else
409 enable_mask = status_mask << 16;
Imre Deak755e9012014-02-10 18:42:47 +0200410 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
411}
412
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000413/**
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300414 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
Zhao Yakui01c66882009-10-28 05:10:00 +0000415 */
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300416static void i915_enable_asle_pipestat(struct drm_device *dev)
Zhao Yakui01c66882009-10-28 05:10:00 +0000417{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300418 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000419
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300420 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
421 return;
422
Daniel Vetter13321782014-09-15 14:55:29 +0200423 spin_lock_irq(&dev_priv->irq_lock);
Zhao Yakui01c66882009-10-28 05:10:00 +0000424
Imre Deak755e9012014-02-10 18:42:47 +0200425 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
Jani Nikulaf8987802013-04-29 13:02:53 +0300426 if (INTEL_INFO(dev)->gen >= 4)
Daniel Vetter3b6c42e2013-10-21 18:04:35 +0200427 i915_enable_pipestat(dev_priv, PIPE_A,
Imre Deak755e9012014-02-10 18:42:47 +0200428 PIPE_LEGACY_BLC_EVENT_STATUS);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000429
Daniel Vetter13321782014-09-15 14:55:29 +0200430 spin_unlock_irq(&dev_priv->irq_lock);
Zhao Yakui01c66882009-10-28 05:10:00 +0000431}
432
433/**
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700434 * i915_pipe_enabled - check if a pipe is enabled
435 * @dev: DRM device
436 * @pipe: pipe to check
437 *
438 * Reading certain registers when the pipe is disabled can hang the chip.
439 * Use this routine to make sure the PLL is running and the pipe is active
440 * before reading such registers if unsure.
441 */
442static int
443i915_pipe_enabled(struct drm_device *dev, int pipe)
444{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300445 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200446
Daniel Vettera01025a2013-05-22 00:50:23 +0200447 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
448 /* Locking is horribly broken here, but whatever. */
449 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni71f8ba62013-05-03 12:15:39 -0300451
Daniel Vettera01025a2013-05-22 00:50:23 +0200452 return intel_crtc->active;
453 } else {
454 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
455 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700456}
457
Ville Syrjäläf75f3742014-05-15 20:20:36 +0300458/*
459 * This timing diagram depicts the video signal in and
460 * around the vertical blanking period.
461 *
462 * Assumptions about the fictitious mode used in this example:
463 * vblank_start >= 3
464 * vsync_start = vblank_start + 1
465 * vsync_end = vblank_start + 2
466 * vtotal = vblank_start + 3
467 *
468 * start of vblank:
469 * latch double buffered registers
470 * increment frame counter (ctg+)
471 * generate start of vblank interrupt (gen4+)
472 * |
473 * | frame start:
474 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
475 * | may be shifted forward 1-3 extra lines via PIPECONF
476 * | |
477 * | | start of vsync:
478 * | | generate vsync interrupt
479 * | | |
480 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
481 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
482 * ----va---> <-----------------vb--------------------> <--------va-------------
483 * | | <----vs-----> |
484 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
485 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
486 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
487 * | | |
488 * last visible pixel first visible pixel
489 * | increment frame counter (gen3/4)
490 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
491 *
492 * x = horizontal active
493 * _ = horizontal blanking
494 * hs = horizontal sync
495 * va = vertical active
496 * vb = vertical blanking
497 * vs = vertical sync
498 * vbs = vblank_start (number)
499 *
500 * Summary:
501 * - most events happen at the start of horizontal sync
502 * - frame start happens at the start of horizontal blank, 1-4 lines
503 * (depending on PIPECONF settings) after the start of vblank
504 * - gen3/4 pixel and frame counter are synchronized with the start
505 * of horizontal active on the first line of vertical active
506 */
507
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +0300508static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
509{
510 /* Gen2 doesn't have a hardware frame counter */
511 return 0;
512}
513
Keith Packard42f52ef2008-10-18 19:39:29 -0700514/* Called from drm generic code, passed a 'crtc', which
515 * we use as a pipe index
516 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700517static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700518{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300519 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700520 unsigned long high_frame;
521 unsigned long low_frame;
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300522 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700523
524 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800525 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800526 "pipe %c\n", pipe_name(pipe));
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700527 return 0;
528 }
529
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300530 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
531 struct intel_crtc *intel_crtc =
532 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
533 const struct drm_display_mode *mode =
534 &intel_crtc->config.adjusted_mode;
535
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300536 htotal = mode->crtc_htotal;
537 hsync_start = mode->crtc_hsync_start;
538 vbl_start = mode->crtc_vblank_start;
539 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
540 vbl_start = DIV_ROUND_UP(vbl_start, 2);
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300541 } else {
Daniel Vettera2d213d2014-02-07 16:34:05 +0100542 enum transcoder cpu_transcoder = (enum transcoder) pipe;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300543
544 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300545 hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300546 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300547 if ((I915_READ(PIPECONF(cpu_transcoder)) &
548 PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
549 vbl_start = DIV_ROUND_UP(vbl_start, 2);
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300550 }
551
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300552 /* Convert to pixel count */
553 vbl_start *= htotal;
554
555 /* Start of vblank event occurs at start of hsync */
556 vbl_start -= htotal - hsync_start;
557
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800558 high_frame = PIPEFRAME(pipe);
559 low_frame = PIPEFRAMEPIXEL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +0100560
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700561 /*
562 * High & low register fields aren't synchronized, so make sure
563 * we get a low value that's stable across two reads of the high
564 * register.
565 */
566 do {
Chris Wilson5eddb702010-09-11 13:48:45 +0100567 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300568 low = I915_READ(low_frame);
Chris Wilson5eddb702010-09-11 13:48:45 +0100569 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700570 } while (high1 != high2);
571
Chris Wilson5eddb702010-09-11 13:48:45 +0100572 high1 >>= PIPE_FRAME_HIGH_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300573 pixel = low & PIPE_PIXEL_MASK;
Chris Wilson5eddb702010-09-11 13:48:45 +0100574 low >>= PIPE_FRAME_LOW_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300575
576 /*
577 * The frame counter increments at beginning of active.
578 * Cook up a vblank counter by also checking the pixel
579 * counter against vblank start.
580 */
Ville Syrjäläedc08d02013-11-06 13:56:27 -0200581 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700582}
583
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700584static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800585{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300586 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800587 int reg = PIPE_FRMCOUNT_GM45(pipe);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800588
589 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800590 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800591 "pipe %c\n", pipe_name(pipe));
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800592 return 0;
593 }
594
595 return I915_READ(reg);
596}
597
Mario Kleinerad3543e2013-10-30 05:13:08 +0100598/* raw reads, only for fast reads of display block, no need for forcewake etc. */
599#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
Mario Kleinerad3543e2013-10-30 05:13:08 +0100600
Ville Syrjäläa225f072014-04-29 13:35:45 +0300601static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
602{
603 struct drm_device *dev = crtc->base.dev;
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
606 enum pipe pipe = crtc->pipe;
Ville Syrjälä80715b22014-05-15 20:23:23 +0300607 int position, vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300608
Ville Syrjälä80715b22014-05-15 20:23:23 +0300609 vtotal = mode->crtc_vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300610 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
611 vtotal /= 2;
612
613 if (IS_GEN2(dev))
614 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
615 else
616 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
617
618 /*
Ville Syrjälä80715b22014-05-15 20:23:23 +0300619 * See update_scanline_offset() for the details on the
620 * scanline_offset adjustment.
Ville Syrjäläa225f072014-04-29 13:35:45 +0300621 */
Ville Syrjälä80715b22014-05-15 20:23:23 +0300622 return (position + crtc->scanline_offset) % vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300623}
624
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700625static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
Ville Syrjäläabca9e42013-10-28 20:50:48 +0200626 unsigned int flags, int *vpos, int *hpos,
627 ktime_t *stime, ktime_t *etime)
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100628{
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300629 struct drm_i915_private *dev_priv = dev->dev_private;
630 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
632 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300633 int position;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300634 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100635 bool in_vbl = true;
636 int ret = 0;
Mario Kleinerad3543e2013-10-30 05:13:08 +0100637 unsigned long irqflags;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100638
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300639 if (!intel_crtc->active) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100640 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800641 "pipe %c\n", pipe_name(pipe));
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100642 return 0;
643 }
644
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300645 htotal = mode->crtc_htotal;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300646 hsync_start = mode->crtc_hsync_start;
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300647 vtotal = mode->crtc_vtotal;
648 vbl_start = mode->crtc_vblank_start;
649 vbl_end = mode->crtc_vblank_end;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100650
Ville Syrjäläd31faf62013-10-28 16:31:41 +0200651 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
652 vbl_start = DIV_ROUND_UP(vbl_start, 2);
653 vbl_end /= 2;
654 vtotal /= 2;
655 }
656
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300657 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
658
Mario Kleinerad3543e2013-10-30 05:13:08 +0100659 /*
660 * Lock uncore.lock, as we will do multiple timing critical raw
661 * register reads, potentially with preemption disabled, so the
662 * following code must not block on uncore.lock.
663 */
664 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300665
Mario Kleinerad3543e2013-10-30 05:13:08 +0100666 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
667
668 /* Get optional system timestamp before query. */
669 if (stime)
670 *stime = ktime_get();
671
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300672 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100673 /* No obvious pixelcount register. Only query vertical
674 * scanout position from Display scan line register.
675 */
Ville Syrjäläa225f072014-04-29 13:35:45 +0300676 position = __intel_get_crtc_scanline(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100677 } else {
678 /* Have access to pixelcount since start of frame.
679 * We can split this into vertical and horizontal
680 * scanout position.
681 */
Mario Kleinerad3543e2013-10-30 05:13:08 +0100682 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100683
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300684 /* convert to pixel counts */
685 vbl_start *= htotal;
686 vbl_end *= htotal;
687 vtotal *= htotal;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300688
689 /*
Ville Syrjälä7e78f1cb2014-04-29 13:35:49 +0300690 * In interlaced modes, the pixel counter counts all pixels,
691 * so one field will have htotal more pixels. In order to avoid
692 * the reported position from jumping backwards when the pixel
693 * counter is beyond the length of the shorter field, just
694 * clamp the position the length of the shorter field. This
695 * matches how the scanline counter based position works since
696 * the scanline counter doesn't count the two half lines.
697 */
698 if (position >= vtotal)
699 position = vtotal - 1;
700
701 /*
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300702 * Start of vblank interrupt is triggered at start of hsync,
703 * just prior to the first active line of vblank. However we
704 * consider lines to start at the leading edge of horizontal
705 * active. So, should we get here before we've crossed into
706 * the horizontal active of the first line in vblank, we would
707 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
708 * always add htotal-hsync_start to the current pixel position.
709 */
710 position = (position + htotal - hsync_start) % vtotal;
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300711 }
712
Mario Kleinerad3543e2013-10-30 05:13:08 +0100713 /* Get optional system timestamp after query. */
714 if (etime)
715 *etime = ktime_get();
716
717 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
718
719 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
720
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300721 in_vbl = position >= vbl_start && position < vbl_end;
722
723 /*
724 * While in vblank, position will be negative
725 * counting up towards 0 at vbl_end. And outside
726 * vblank, position will be positive counting
727 * up since vbl_end.
728 */
729 if (position >= vbl_start)
730 position -= vbl_end;
731 else
732 position += vtotal - vbl_end;
733
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300734 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300735 *vpos = position;
736 *hpos = 0;
737 } else {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100738 *vpos = position / htotal;
739 *hpos = position - (*vpos * htotal);
740 }
741
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100742 /* In vblank? */
743 if (in_vbl)
Daniel Vetter3d3cbd82014-09-10 17:36:11 +0200744 ret |= DRM_SCANOUTPOS_IN_VBLANK;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100745
746 return ret;
747}
748
Ville Syrjäläa225f072014-04-29 13:35:45 +0300749int intel_get_crtc_scanline(struct intel_crtc *crtc)
750{
751 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
752 unsigned long irqflags;
753 int position;
754
755 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
756 position = __intel_get_crtc_scanline(crtc);
757 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
758
759 return position;
760}
761
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700762static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100763 int *max_error,
764 struct timeval *vblank_time,
765 unsigned flags)
766{
Chris Wilson4041b852011-01-22 10:07:56 +0000767 struct drm_crtc *crtc;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100768
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700769 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
Chris Wilson4041b852011-01-22 10:07:56 +0000770 DRM_ERROR("Invalid crtc %d\n", pipe);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100771 return -EINVAL;
772 }
773
774 /* Get drm_crtc to timestamp: */
Chris Wilson4041b852011-01-22 10:07:56 +0000775 crtc = intel_get_crtc_for_pipe(dev, pipe);
776 if (crtc == NULL) {
777 DRM_ERROR("Invalid crtc %d\n", pipe);
778 return -EINVAL;
779 }
780
781 if (!crtc->enabled) {
782 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
783 return -EBUSY;
784 }
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100785
786 /* Helper routine in DRM core does all the work: */
Chris Wilson4041b852011-01-22 10:07:56 +0000787 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
788 vblank_time, flags,
Ville Syrjälä7da903e2013-10-26 17:57:31 +0300789 crtc,
790 &to_intel_crtc(crtc)->config.adjusted_mode);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100791}
792
Jani Nikula67c347f2013-09-17 14:26:34 +0300793static bool intel_hpd_irq_event(struct drm_device *dev,
794 struct drm_connector *connector)
Egbert Eich321a1b32013-04-11 16:00:26 +0200795{
796 enum drm_connector_status old_status;
797
798 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
799 old_status = connector->status;
800
801 connector->status = connector->funcs->detect(connector, false);
Jani Nikula67c347f2013-09-17 14:26:34 +0300802 if (old_status == connector->status)
803 return false;
804
805 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
Egbert Eich321a1b32013-04-11 16:00:26 +0200806 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +0300807 connector->name,
Jani Nikula67c347f2013-09-17 14:26:34 +0300808 drm_get_connector_status_name(old_status),
809 drm_get_connector_status_name(connector->status));
810
811 return true;
Egbert Eich321a1b32013-04-11 16:00:26 +0200812}
813
Dave Airlie13cf5502014-06-18 11:29:35 +1000814static void i915_digport_work_func(struct work_struct *work)
815{
816 struct drm_i915_private *dev_priv =
817 container_of(work, struct drm_i915_private, dig_port_work);
Dave Airlie13cf5502014-06-18 11:29:35 +1000818 u32 long_port_mask, short_port_mask;
819 struct intel_digital_port *intel_dig_port;
820 int i, ret;
821 u32 old_bits = 0;
822
Daniel Vetter4cb21832014-09-15 14:55:26 +0200823 spin_lock_irq(&dev_priv->irq_lock);
Dave Airlie13cf5502014-06-18 11:29:35 +1000824 long_port_mask = dev_priv->long_hpd_port_mask;
825 dev_priv->long_hpd_port_mask = 0;
826 short_port_mask = dev_priv->short_hpd_port_mask;
827 dev_priv->short_hpd_port_mask = 0;
Daniel Vetter4cb21832014-09-15 14:55:26 +0200828 spin_unlock_irq(&dev_priv->irq_lock);
Dave Airlie13cf5502014-06-18 11:29:35 +1000829
830 for (i = 0; i < I915_MAX_PORTS; i++) {
831 bool valid = false;
832 bool long_hpd = false;
833 intel_dig_port = dev_priv->hpd_irq_port[i];
834 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
835 continue;
836
837 if (long_port_mask & (1 << i)) {
838 valid = true;
839 long_hpd = true;
840 } else if (short_port_mask & (1 << i))
841 valid = true;
842
843 if (valid) {
844 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
845 if (ret == true) {
846 /* if we get true fallback to old school hpd */
847 old_bits |= (1 << intel_dig_port->base.hpd_pin);
848 }
849 }
850 }
851
852 if (old_bits) {
Daniel Vetter4cb21832014-09-15 14:55:26 +0200853 spin_lock_irq(&dev_priv->irq_lock);
Dave Airlie13cf5502014-06-18 11:29:35 +1000854 dev_priv->hpd_event_bits |= old_bits;
Daniel Vetter4cb21832014-09-15 14:55:26 +0200855 spin_unlock_irq(&dev_priv->irq_lock);
Dave Airlie13cf5502014-06-18 11:29:35 +1000856 schedule_work(&dev_priv->hotplug_work);
857 }
858}
859
Jesse Barnes5ca58282009-03-31 14:11:15 -0700860/*
861 * Handle hotplug events outside the interrupt handler proper.
862 */
Egbert Eichac4c16c2013-04-16 13:36:58 +0200863#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
864
Jesse Barnes5ca58282009-03-31 14:11:15 -0700865static void i915_hotplug_work_func(struct work_struct *work)
866{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300867 struct drm_i915_private *dev_priv =
868 container_of(work, struct drm_i915_private, hotplug_work);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700869 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700870 struct drm_mode_config *mode_config = &dev->mode_config;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200871 struct intel_connector *intel_connector;
872 struct intel_encoder *intel_encoder;
873 struct drm_connector *connector;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200874 bool hpd_disabled = false;
Egbert Eich321a1b32013-04-11 16:00:26 +0200875 bool changed = false;
Egbert Eich142e2392013-04-11 15:57:57 +0200876 u32 hpd_event_bits;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700877
Keith Packarda65e34c2011-07-25 10:04:56 -0700878 mutex_lock(&mode_config->mutex);
Jesse Barnese67189ab2011-02-11 14:44:51 -0800879 DRM_DEBUG_KMS("running encoder hotplug functions\n");
880
Daniel Vetter4cb21832014-09-15 14:55:26 +0200881 spin_lock_irq(&dev_priv->irq_lock);
Egbert Eich142e2392013-04-11 15:57:57 +0200882
883 hpd_event_bits = dev_priv->hpd_event_bits;
884 dev_priv->hpd_event_bits = 0;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200885 list_for_each_entry(connector, &mode_config->connector_list, head) {
886 intel_connector = to_intel_connector(connector);
Dave Airlie36cd7442014-05-02 13:44:18 +1000887 if (!intel_connector->encoder)
888 continue;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200889 intel_encoder = intel_connector->encoder;
890 if (intel_encoder->hpd_pin > HPD_NONE &&
891 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
892 connector->polled == DRM_CONNECTOR_POLL_HPD) {
893 DRM_INFO("HPD interrupt storm detected on connector %s: "
894 "switching from hotplug detection to polling\n",
Jani Nikulac23cc412014-06-03 14:56:17 +0300895 connector->name);
Egbert Eichcd569ae2013-04-16 13:36:57 +0200896 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
897 connector->polled = DRM_CONNECTOR_POLL_CONNECT
898 | DRM_CONNECTOR_POLL_DISCONNECT;
899 hpd_disabled = true;
900 }
Egbert Eich142e2392013-04-11 15:57:57 +0200901 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
902 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
Jani Nikulac23cc412014-06-03 14:56:17 +0300903 connector->name, intel_encoder->hpd_pin);
Egbert Eich142e2392013-04-11 15:57:57 +0200904 }
Egbert Eichcd569ae2013-04-16 13:36:57 +0200905 }
906 /* if there were no outputs to poll, poll was disabled,
907 * therefore make sure it's enabled when disabling HPD on
908 * some connectors */
Egbert Eichac4c16c2013-04-16 13:36:58 +0200909 if (hpd_disabled) {
Egbert Eichcd569ae2013-04-16 13:36:57 +0200910 drm_kms_helper_poll_enable(dev);
Imre Deak63237512014-08-18 15:37:02 +0300911 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
912 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
Egbert Eichac4c16c2013-04-16 13:36:58 +0200913 }
Egbert Eichcd569ae2013-04-16 13:36:57 +0200914
Daniel Vetter4cb21832014-09-15 14:55:26 +0200915 spin_unlock_irq(&dev_priv->irq_lock);
Egbert Eichcd569ae2013-04-16 13:36:57 +0200916
Egbert Eich321a1b32013-04-11 16:00:26 +0200917 list_for_each_entry(connector, &mode_config->connector_list, head) {
918 intel_connector = to_intel_connector(connector);
Dave Airlie36cd7442014-05-02 13:44:18 +1000919 if (!intel_connector->encoder)
920 continue;
Egbert Eich321a1b32013-04-11 16:00:26 +0200921 intel_encoder = intel_connector->encoder;
922 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
923 if (intel_encoder->hot_plug)
924 intel_encoder->hot_plug(intel_encoder);
925 if (intel_hpd_irq_event(dev, connector))
926 changed = true;
927 }
928 }
Keith Packard40ee3382011-07-28 15:31:19 -0700929 mutex_unlock(&mode_config->mutex);
930
Egbert Eich321a1b32013-04-11 16:00:26 +0200931 if (changed)
932 drm_kms_helper_hotplug_event(dev);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700933}
934
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200935static void ironlake_rps_change_irq_handler(struct drm_device *dev)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800936{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300937 struct drm_i915_private *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000938 u32 busy_up, busy_down, max_avg, min_avg;
Daniel Vetter92703882012-08-09 16:46:01 +0200939 u8 new_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200940
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200941 spin_lock(&mchdev_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800942
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200943 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
944
Daniel Vetter20e4d402012-08-08 23:35:39 +0200945 new_delay = dev_priv->ips.cur_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200946
Jesse Barnes7648fa92010-05-20 14:28:11 -0700947 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000948 busy_up = I915_READ(RCPREVBSYTUPAVG);
949 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800950 max_avg = I915_READ(RCBMAXAVG);
951 min_avg = I915_READ(RCBMINAVG);
952
953 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000954 if (busy_up > max_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200955 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
956 new_delay = dev_priv->ips.cur_delay - 1;
957 if (new_delay < dev_priv->ips.max_delay)
958 new_delay = dev_priv->ips.max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000959 } else if (busy_down < min_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200960 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
961 new_delay = dev_priv->ips.cur_delay + 1;
962 if (new_delay > dev_priv->ips.min_delay)
963 new_delay = dev_priv->ips.min_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800964 }
965
Jesse Barnes7648fa92010-05-20 14:28:11 -0700966 if (ironlake_set_drps(dev, new_delay))
Daniel Vetter20e4d402012-08-08 23:35:39 +0200967 dev_priv->ips.cur_delay = new_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800968
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200969 spin_unlock(&mchdev_lock);
Daniel Vetter92703882012-08-09 16:46:01 +0200970
Jesse Barnesf97108d2010-01-29 11:27:07 -0800971 return;
972}
973
Chris Wilson549f7362010-10-19 11:19:32 +0100974static void notify_ring(struct drm_device *dev,
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100975 struct intel_engine_cs *ring)
Chris Wilson549f7362010-10-19 11:19:32 +0100976{
Oscar Mateo93b0a4e2014-05-22 14:13:36 +0100977 if (!intel_ring_initialized(ring))
Chris Wilson475553d2011-01-20 09:52:56 +0000978 return;
979
Chris Wilson814e9b52013-09-23 17:33:19 -0300980 trace_i915_gem_request_complete(ring);
Chris Wilson9862e602011-01-04 22:22:17 +0000981
Sourab Gupta84c33a62014-06-02 16:47:17 +0530982 if (drm_core_check_feature(dev, DRIVER_MODESET))
983 intel_notify_mmio_flip(ring);
984
Chris Wilson549f7362010-10-19 11:19:32 +0100985 wake_up_all(&ring->irq_queue);
Mika Kuoppala10cd45b2013-07-03 17:22:08 +0300986 i915_queue_hangcheck(dev);
Chris Wilson549f7362010-10-19 11:19:32 +0100987}
988
Deepak S31685c22014-07-03 17:33:01 -0400989static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
Chris Wilsonbf225f22014-07-10 20:31:18 +0100990 struct intel_rps_ei *rps_ei)
Deepak S31685c22014-07-03 17:33:01 -0400991{
992 u32 cz_ts, cz_freq_khz;
993 u32 render_count, media_count;
994 u32 elapsed_render, elapsed_media, elapsed_time;
995 u32 residency = 0;
996
997 cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
998 cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
999
1000 render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1001 media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1002
Chris Wilsonbf225f22014-07-10 20:31:18 +01001003 if (rps_ei->cz_clock == 0) {
1004 rps_ei->cz_clock = cz_ts;
1005 rps_ei->render_c0 = render_count;
1006 rps_ei->media_c0 = media_count;
Deepak S31685c22014-07-03 17:33:01 -04001007
1008 return dev_priv->rps.cur_freq;
1009 }
1010
Chris Wilsonbf225f22014-07-10 20:31:18 +01001011 elapsed_time = cz_ts - rps_ei->cz_clock;
1012 rps_ei->cz_clock = cz_ts;
Deepak S31685c22014-07-03 17:33:01 -04001013
Chris Wilsonbf225f22014-07-10 20:31:18 +01001014 elapsed_render = render_count - rps_ei->render_c0;
1015 rps_ei->render_c0 = render_count;
Deepak S31685c22014-07-03 17:33:01 -04001016
Chris Wilsonbf225f22014-07-10 20:31:18 +01001017 elapsed_media = media_count - rps_ei->media_c0;
1018 rps_ei->media_c0 = media_count;
Deepak S31685c22014-07-03 17:33:01 -04001019
1020 /* Convert all the counters into common unit of milli sec */
1021 elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1022 elapsed_render /= cz_freq_khz;
1023 elapsed_media /= cz_freq_khz;
1024
1025 /*
1026 * Calculate overall C0 residency percentage
1027 * only if elapsed time is non zero
1028 */
1029 if (elapsed_time) {
1030 residency =
1031 ((max(elapsed_render, elapsed_media) * 100)
1032 / elapsed_time);
1033 }
1034
1035 return residency;
1036}
1037
1038/**
1039 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1040 * busy-ness calculated from C0 counters of render & media power wells
1041 * @dev_priv: DRM device private
1042 *
1043 */
Damien Lespiau4fa79042014-08-08 19:25:57 +01001044static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
Deepak S31685c22014-07-03 17:33:01 -04001045{
1046 u32 residency_C0_up = 0, residency_C0_down = 0;
Damien Lespiau4fa79042014-08-08 19:25:57 +01001047 int new_delay, adj;
Deepak S31685c22014-07-03 17:33:01 -04001048
1049 dev_priv->rps.ei_interrupt_count++;
1050
1051 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1052
1053
Chris Wilsonbf225f22014-07-10 20:31:18 +01001054 if (dev_priv->rps.up_ei.cz_clock == 0) {
1055 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1056 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
Deepak S31685c22014-07-03 17:33:01 -04001057 return dev_priv->rps.cur_freq;
1058 }
1059
1060
1061 /*
1062 * To down throttle, C0 residency should be less than down threshold
1063 * for continous EI intervals. So calculate down EI counters
1064 * once in VLV_INT_COUNT_FOR_DOWN_EI
1065 */
1066 if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1067
1068 dev_priv->rps.ei_interrupt_count = 0;
1069
1070 residency_C0_down = vlv_c0_residency(dev_priv,
Chris Wilsonbf225f22014-07-10 20:31:18 +01001071 &dev_priv->rps.down_ei);
Deepak S31685c22014-07-03 17:33:01 -04001072 } else {
1073 residency_C0_up = vlv_c0_residency(dev_priv,
Chris Wilsonbf225f22014-07-10 20:31:18 +01001074 &dev_priv->rps.up_ei);
Deepak S31685c22014-07-03 17:33:01 -04001075 }
1076
1077 new_delay = dev_priv->rps.cur_freq;
1078
1079 adj = dev_priv->rps.last_adj;
1080 /* C0 residency is greater than UP threshold. Increase Frequency */
1081 if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1082 if (adj > 0)
1083 adj *= 2;
1084 else
1085 adj = 1;
1086
1087 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1088 new_delay = dev_priv->rps.cur_freq + adj;
1089
1090 /*
1091 * For better performance, jump directly
1092 * to RPe if we're below it.
1093 */
1094 if (new_delay < dev_priv->rps.efficient_freq)
1095 new_delay = dev_priv->rps.efficient_freq;
1096
1097 } else if (!dev_priv->rps.ei_interrupt_count &&
1098 (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1099 if (adj < 0)
1100 adj *= 2;
1101 else
1102 adj = -1;
1103 /*
1104 * This means, C0 residency is less than down threshold over
1105 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1106 */
1107 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1108 new_delay = dev_priv->rps.cur_freq + adj;
1109 }
1110
1111 return new_delay;
1112}
1113
Ben Widawsky4912d042011-04-25 11:25:20 -07001114static void gen6_pm_rps_work(struct work_struct *work)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001115{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001116 struct drm_i915_private *dev_priv =
1117 container_of(work, struct drm_i915_private, rps.work);
Paulo Zanoniedbfdb42013-08-06 18:57:13 -03001118 u32 pm_iir;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001119 int new_delay, adj;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001120
Daniel Vetter59cdb632013-07-04 23:35:28 +02001121 spin_lock_irq(&dev_priv->irq_lock);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001122 pm_iir = dev_priv->rps.pm_iir;
1123 dev_priv->rps.pm_iir = 0;
Damien Lespiau6af257c2014-07-15 09:17:41 +02001124 if (INTEL_INFO(dev_priv->dev)->gen >= 8)
Daniel Vetter480c8032014-07-16 09:49:40 +02001125 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Ben Widawsky09610212014-05-15 20:58:08 +03001126 else {
1127 /* Make sure not to corrupt PMIMR state used by ringbuffer */
Daniel Vetter480c8032014-07-16 09:49:40 +02001128 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Ben Widawsky09610212014-05-15 20:58:08 +03001129 }
Daniel Vetter59cdb632013-07-04 23:35:28 +02001130 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawsky4912d042011-04-25 11:25:20 -07001131
Paulo Zanoni60611c12013-08-15 11:50:01 -03001132 /* Make sure we didn't queue anything we're not going to process. */
Deepak Sa6706b42014-03-15 20:23:22 +05301133 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
Paulo Zanoni60611c12013-08-15 11:50:01 -03001134
Deepak Sa6706b42014-03-15 20:23:22 +05301135 if ((pm_iir & dev_priv->pm_rps_events) == 0)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001136 return;
1137
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001138 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01001139
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001140 adj = dev_priv->rps.last_adj;
Ville Syrjälä74250342013-06-25 21:38:11 +03001141 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001142 if (adj > 0)
1143 adj *= 2;
Deepak S13a56602014-05-23 21:00:21 +05301144 else {
1145 /* CHV needs even encode values */
1146 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1147 }
Ben Widawskyb39fb292014-03-19 18:31:11 -07001148 new_delay = dev_priv->rps.cur_freq + adj;
Ville Syrjälä74250342013-06-25 21:38:11 +03001149
1150 /*
1151 * For better performance, jump directly
1152 * to RPe if we're below it.
1153 */
Ben Widawskyb39fb292014-03-19 18:31:11 -07001154 if (new_delay < dev_priv->rps.efficient_freq)
1155 new_delay = dev_priv->rps.efficient_freq;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001156 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
Ben Widawskyb39fb292014-03-19 18:31:11 -07001157 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1158 new_delay = dev_priv->rps.efficient_freq;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001159 else
Ben Widawskyb39fb292014-03-19 18:31:11 -07001160 new_delay = dev_priv->rps.min_freq_softlimit;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001161 adj = 0;
Deepak S31685c22014-07-03 17:33:01 -04001162 } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1163 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001164 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1165 if (adj < 0)
1166 adj *= 2;
Deepak S13a56602014-05-23 21:00:21 +05301167 else {
1168 /* CHV needs even encode values */
1169 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1170 }
Ben Widawskyb39fb292014-03-19 18:31:11 -07001171 new_delay = dev_priv->rps.cur_freq + adj;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001172 } else { /* unknown event */
Ben Widawskyb39fb292014-03-19 18:31:11 -07001173 new_delay = dev_priv->rps.cur_freq;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001174 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001175
Ben Widawsky79249632012-09-07 19:43:42 -07001176 /* sysfs frequency interfaces may have snuck in while servicing the
1177 * interrupt
1178 */
Ville Syrjälä1272e7b2013-11-07 19:57:49 +02001179 new_delay = clamp_t(int, new_delay,
Ben Widawskyb39fb292014-03-19 18:31:11 -07001180 dev_priv->rps.min_freq_softlimit,
1181 dev_priv->rps.max_freq_softlimit);
Deepak S27544362014-01-27 21:35:05 +05301182
Ben Widawskyb39fb292014-03-19 18:31:11 -07001183 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001184
1185 if (IS_VALLEYVIEW(dev_priv->dev))
1186 valleyview_set_rps(dev_priv->dev, new_delay);
1187 else
1188 gen6_set_rps(dev_priv->dev, new_delay);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001189
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001190 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001191}
1192
Ben Widawskye3689192012-05-25 16:56:22 -07001193
1194/**
1195 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1196 * occurred.
1197 * @work: workqueue struct
1198 *
1199 * Doesn't actually do anything except notify userspace. As a consequence of
1200 * this event, userspace should try to remap the bad rows since statistically
1201 * it is likely the same row is more likely to go bad again.
1202 */
1203static void ivybridge_parity_work(struct work_struct *work)
1204{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001205 struct drm_i915_private *dev_priv =
1206 container_of(work, struct drm_i915_private, l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001207 u32 error_status, row, bank, subbank;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001208 char *parity_event[6];
Ben Widawskye3689192012-05-25 16:56:22 -07001209 uint32_t misccpctl;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001210 uint8_t slice = 0;
Ben Widawskye3689192012-05-25 16:56:22 -07001211
1212 /* We must turn off DOP level clock gating to access the L3 registers.
1213 * In order to prevent a get/put style interface, acquire struct mutex
1214 * any time we access those registers.
1215 */
1216 mutex_lock(&dev_priv->dev->struct_mutex);
1217
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001218 /* If we've screwed up tracking, just let the interrupt fire again */
1219 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1220 goto out;
1221
Ben Widawskye3689192012-05-25 16:56:22 -07001222 misccpctl = I915_READ(GEN7_MISCCPCTL);
1223 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1224 POSTING_READ(GEN7_MISCCPCTL);
1225
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001226 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1227 u32 reg;
Ben Widawskye3689192012-05-25 16:56:22 -07001228
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001229 slice--;
1230 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1231 break;
1232
1233 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1234
1235 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1236
1237 error_status = I915_READ(reg);
1238 row = GEN7_PARITY_ERROR_ROW(error_status);
1239 bank = GEN7_PARITY_ERROR_BANK(error_status);
1240 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1241
1242 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1243 POSTING_READ(reg);
1244
1245 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1246 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1247 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1248 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1249 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1250 parity_event[5] = NULL;
1251
Dave Airlie5bdebb12013-10-11 14:07:25 +10001252 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001253 KOBJ_CHANGE, parity_event);
1254
1255 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1256 slice, row, bank, subbank);
1257
1258 kfree(parity_event[4]);
1259 kfree(parity_event[3]);
1260 kfree(parity_event[2]);
1261 kfree(parity_event[1]);
1262 }
Ben Widawskye3689192012-05-25 16:56:22 -07001263
1264 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1265
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001266out:
1267 WARN_ON(dev_priv->l3_parity.which_slice);
Daniel Vetter4cb21832014-09-15 14:55:26 +02001268 spin_lock_irq(&dev_priv->irq_lock);
Daniel Vetter480c8032014-07-16 09:49:40 +02001269 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
Daniel Vetter4cb21832014-09-15 14:55:26 +02001270 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001271
1272 mutex_unlock(&dev_priv->dev->struct_mutex);
Ben Widawskye3689192012-05-25 16:56:22 -07001273}
1274
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001275static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
Ben Widawskye3689192012-05-25 16:56:22 -07001276{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001277 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskye3689192012-05-25 16:56:22 -07001278
Ben Widawsky040d2ba2013-09-19 11:01:40 -07001279 if (!HAS_L3_DPF(dev))
Ben Widawskye3689192012-05-25 16:56:22 -07001280 return;
1281
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001282 spin_lock(&dev_priv->irq_lock);
Daniel Vetter480c8032014-07-16 09:49:40 +02001283 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001284 spin_unlock(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001285
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001286 iir &= GT_PARITY_ERROR(dev);
1287 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1288 dev_priv->l3_parity.which_slice |= 1 << 1;
1289
1290 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1291 dev_priv->l3_parity.which_slice |= 1 << 0;
1292
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001293 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001294}
1295
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001296static void ilk_gt_irq_handler(struct drm_device *dev,
1297 struct drm_i915_private *dev_priv,
1298 u32 gt_iir)
1299{
1300 if (gt_iir &
1301 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1302 notify_ring(dev, &dev_priv->ring[RCS]);
1303 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1304 notify_ring(dev, &dev_priv->ring[VCS]);
1305}
1306
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001307static void snb_gt_irq_handler(struct drm_device *dev,
1308 struct drm_i915_private *dev_priv,
1309 u32 gt_iir)
1310{
1311
Ben Widawskycc609d52013-05-28 19:22:29 -07001312 if (gt_iir &
1313 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001314 notify_ring(dev, &dev_priv->ring[RCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001315 if (gt_iir & GT_BSD_USER_INTERRUPT)
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001316 notify_ring(dev, &dev_priv->ring[VCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001317 if (gt_iir & GT_BLT_USER_INTERRUPT)
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001318 notify_ring(dev, &dev_priv->ring[BCS]);
1319
Ben Widawskycc609d52013-05-28 19:22:29 -07001320 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1321 GT_BSD_CS_ERROR_INTERRUPT |
1322 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
Mika Kuoppala58174462014-02-25 17:11:26 +02001323 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1324 gt_iir);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001325 }
Ben Widawskye3689192012-05-25 16:56:22 -07001326
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001327 if (gt_iir & GT_PARITY_ERROR(dev))
1328 ivybridge_parity_error_irq_handler(dev, gt_iir);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001329}
1330
Ben Widawsky09610212014-05-15 20:58:08 +03001331static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1332{
1333 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1334 return;
1335
1336 spin_lock(&dev_priv->irq_lock);
1337 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
Daniel Vetter480c8032014-07-16 09:49:40 +02001338 gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
Ben Widawsky09610212014-05-15 20:58:08 +03001339 spin_unlock(&dev_priv->irq_lock);
1340
1341 queue_work(dev_priv->wq, &dev_priv->rps.work);
1342}
1343
Ben Widawskyabd58f02013-11-02 21:07:09 -07001344static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1345 struct drm_i915_private *dev_priv,
1346 u32 master_ctl)
1347{
Thomas Daniele981e7b2014-07-24 17:04:39 +01001348 struct intel_engine_cs *ring;
Ben Widawskyabd58f02013-11-02 21:07:09 -07001349 u32 rcs, bcs, vcs;
1350 uint32_t tmp = 0;
1351 irqreturn_t ret = IRQ_NONE;
1352
1353 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1354 tmp = I915_READ(GEN8_GT_IIR(0));
1355 if (tmp) {
Oscar Mateo38cc46d2014-06-16 16:10:59 +01001356 I915_WRITE(GEN8_GT_IIR(0), tmp);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001357 ret = IRQ_HANDLED;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001358
Ben Widawskyabd58f02013-11-02 21:07:09 -07001359 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001360 ring = &dev_priv->ring[RCS];
Ben Widawskyabd58f02013-11-02 21:07:09 -07001361 if (rcs & GT_RENDER_USER_INTERRUPT)
Thomas Daniele981e7b2014-07-24 17:04:39 +01001362 notify_ring(dev, ring);
1363 if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1364 intel_execlists_handle_ctx_events(ring);
1365
1366 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1367 ring = &dev_priv->ring[BCS];
Ben Widawskyabd58f02013-11-02 21:07:09 -07001368 if (bcs & GT_RENDER_USER_INTERRUPT)
Thomas Daniele981e7b2014-07-24 17:04:39 +01001369 notify_ring(dev, ring);
1370 if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1371 intel_execlists_handle_ctx_events(ring);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001372 } else
1373 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1374 }
1375
Zhao Yakui85f9b5f2014-04-17 10:37:38 +08001376 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
Ben Widawskyabd58f02013-11-02 21:07:09 -07001377 tmp = I915_READ(GEN8_GT_IIR(1));
1378 if (tmp) {
Oscar Mateo38cc46d2014-06-16 16:10:59 +01001379 I915_WRITE(GEN8_GT_IIR(1), tmp);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001380 ret = IRQ_HANDLED;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001381
Ben Widawskyabd58f02013-11-02 21:07:09 -07001382 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001383 ring = &dev_priv->ring[VCS];
Ben Widawskyabd58f02013-11-02 21:07:09 -07001384 if (vcs & GT_RENDER_USER_INTERRUPT)
Thomas Daniele981e7b2014-07-24 17:04:39 +01001385 notify_ring(dev, ring);
Oscar Mateo73d477f2014-07-24 17:04:31 +01001386 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
Thomas Daniele981e7b2014-07-24 17:04:39 +01001387 intel_execlists_handle_ctx_events(ring);
1388
Zhao Yakui85f9b5f2014-04-17 10:37:38 +08001389 vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001390 ring = &dev_priv->ring[VCS2];
Zhao Yakui85f9b5f2014-04-17 10:37:38 +08001391 if (vcs & GT_RENDER_USER_INTERRUPT)
Thomas Daniele981e7b2014-07-24 17:04:39 +01001392 notify_ring(dev, ring);
Oscar Mateo73d477f2014-07-24 17:04:31 +01001393 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
Thomas Daniele981e7b2014-07-24 17:04:39 +01001394 intel_execlists_handle_ctx_events(ring);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001395 } else
1396 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1397 }
1398
Ben Widawsky09610212014-05-15 20:58:08 +03001399 if (master_ctl & GEN8_GT_PM_IRQ) {
1400 tmp = I915_READ(GEN8_GT_IIR(2));
1401 if (tmp & dev_priv->pm_rps_events) {
Ben Widawsky09610212014-05-15 20:58:08 +03001402 I915_WRITE(GEN8_GT_IIR(2),
1403 tmp & dev_priv->pm_rps_events);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01001404 ret = IRQ_HANDLED;
1405 gen8_rps_irq_handler(dev_priv, tmp);
Ben Widawsky09610212014-05-15 20:58:08 +03001406 } else
1407 DRM_ERROR("The master control interrupt lied (PM)!\n");
1408 }
1409
Ben Widawskyabd58f02013-11-02 21:07:09 -07001410 if (master_ctl & GEN8_GT_VECS_IRQ) {
1411 tmp = I915_READ(GEN8_GT_IIR(3));
1412 if (tmp) {
Oscar Mateo38cc46d2014-06-16 16:10:59 +01001413 I915_WRITE(GEN8_GT_IIR(3), tmp);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001414 ret = IRQ_HANDLED;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001415
Ben Widawskyabd58f02013-11-02 21:07:09 -07001416 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001417 ring = &dev_priv->ring[VECS];
Ben Widawskyabd58f02013-11-02 21:07:09 -07001418 if (vcs & GT_RENDER_USER_INTERRUPT)
Thomas Daniele981e7b2014-07-24 17:04:39 +01001419 notify_ring(dev, ring);
Oscar Mateo73d477f2014-07-24 17:04:31 +01001420 if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
Thomas Daniele981e7b2014-07-24 17:04:39 +01001421 intel_execlists_handle_ctx_events(ring);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001422 } else
1423 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1424 }
1425
1426 return ret;
1427}
1428
Egbert Eichb543fb02013-04-16 13:36:54 +02001429#define HPD_STORM_DETECT_PERIOD 1000
1430#define HPD_STORM_THRESHOLD 5
1431
Jani Nikula07c338c2014-10-02 11:16:32 +03001432static int pch_port_to_hotplug_shift(enum port port)
Dave Airlie13cf5502014-06-18 11:29:35 +10001433{
1434 switch (port) {
1435 case PORT_A:
1436 case PORT_E:
1437 default:
1438 return -1;
1439 case PORT_B:
1440 return 0;
1441 case PORT_C:
1442 return 8;
1443 case PORT_D:
1444 return 16;
1445 }
1446}
1447
Jani Nikula07c338c2014-10-02 11:16:32 +03001448static int i915_port_to_hotplug_shift(enum port port)
Dave Airlie13cf5502014-06-18 11:29:35 +10001449{
1450 switch (port) {
1451 case PORT_A:
1452 case PORT_E:
1453 default:
1454 return -1;
1455 case PORT_B:
1456 return 17;
1457 case PORT_C:
1458 return 19;
1459 case PORT_D:
1460 return 21;
1461 }
1462}
1463
1464static inline enum port get_port_from_pin(enum hpd_pin pin)
1465{
1466 switch (pin) {
1467 case HPD_PORT_B:
1468 return PORT_B;
1469 case HPD_PORT_C:
1470 return PORT_C;
1471 case HPD_PORT_D:
1472 return PORT_D;
1473 default:
1474 return PORT_A; /* no hpd */
1475 }
1476}
1477
Daniel Vetter10a504d2013-06-27 17:52:12 +02001478static inline void intel_hpd_irq_handler(struct drm_device *dev,
Daniel Vetter22062db2013-06-27 17:52:11 +02001479 u32 hotplug_trigger,
Dave Airlie13cf5502014-06-18 11:29:35 +10001480 u32 dig_hotplug_reg,
Daniel Vetter22062db2013-06-27 17:52:11 +02001481 const u32 *hpd)
Egbert Eichb543fb02013-04-16 13:36:54 +02001482{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001483 struct drm_i915_private *dev_priv = dev->dev_private;
Egbert Eichb543fb02013-04-16 13:36:54 +02001484 int i;
Dave Airlie13cf5502014-06-18 11:29:35 +10001485 enum port port;
Daniel Vetter10a504d2013-06-27 17:52:12 +02001486 bool storm_detected = false;
Dave Airlie13cf5502014-06-18 11:29:35 +10001487 bool queue_dig = false, queue_hp = false;
1488 u32 dig_shift;
1489 u32 dig_port_mask = 0;
Egbert Eichb543fb02013-04-16 13:36:54 +02001490
Daniel Vetter91d131d2013-06-27 17:52:14 +02001491 if (!hotplug_trigger)
1492 return;
1493
Dave Airlie13cf5502014-06-18 11:29:35 +10001494 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1495 hotplug_trigger, dig_hotplug_reg);
Imre Deakcc9bd492014-01-16 19:56:54 +02001496
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02001497 spin_lock(&dev_priv->irq_lock);
Egbert Eichb543fb02013-04-16 13:36:54 +02001498 for (i = 1; i < HPD_NUM_PINS; i++) {
Dave Airlie13cf5502014-06-18 11:29:35 +10001499 if (!(hpd[i] & hotplug_trigger))
1500 continue;
Egbert Eich821450c2013-04-16 13:36:55 +02001501
Dave Airlie13cf5502014-06-18 11:29:35 +10001502 port = get_port_from_pin(i);
1503 if (port && dev_priv->hpd_irq_port[port]) {
1504 bool long_hpd;
1505
Jani Nikula07c338c2014-10-02 11:16:32 +03001506 if (HAS_PCH_SPLIT(dev)) {
1507 dig_shift = pch_port_to_hotplug_shift(port);
Dave Airlie13cf5502014-06-18 11:29:35 +10001508 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
Jani Nikula07c338c2014-10-02 11:16:32 +03001509 } else {
1510 dig_shift = i915_port_to_hotplug_shift(port);
1511 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
Dave Airlie13cf5502014-06-18 11:29:35 +10001512 }
1513
Ville Syrjälä26fbb772014-08-11 18:37:37 +03001514 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1515 port_name(port),
1516 long_hpd ? "long" : "short");
Dave Airlie13cf5502014-06-18 11:29:35 +10001517 /* for long HPD pulses we want to have the digital queue happen,
1518 but we still want HPD storm detection to function. */
1519 if (long_hpd) {
1520 dev_priv->long_hpd_port_mask |= (1 << port);
1521 dig_port_mask |= hpd[i];
1522 } else {
1523 /* for short HPD just trigger the digital queue */
1524 dev_priv->short_hpd_port_mask |= (1 << port);
1525 hotplug_trigger &= ~hpd[i];
1526 }
1527 queue_dig = true;
1528 }
1529 }
1530
1531 for (i = 1; i < HPD_NUM_PINS; i++) {
Daniel Vetter3ff04a162014-04-24 12:03:17 +02001532 if (hpd[i] & hotplug_trigger &&
1533 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1534 /*
1535 * On GMCH platforms the interrupt mask bits only
1536 * prevent irq generation, not the setting of the
1537 * hotplug bits itself. So only WARN about unexpected
1538 * interrupts on saner platforms.
1539 */
1540 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1541 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1542 hotplug_trigger, i, hpd[i]);
1543
1544 continue;
1545 }
Egbert Eichb8f102e2013-07-26 14:14:24 +02001546
Egbert Eichb543fb02013-04-16 13:36:54 +02001547 if (!(hpd[i] & hotplug_trigger) ||
1548 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1549 continue;
1550
Dave Airlie13cf5502014-06-18 11:29:35 +10001551 if (!(dig_port_mask & hpd[i])) {
1552 dev_priv->hpd_event_bits |= (1 << i);
1553 queue_hp = true;
1554 }
1555
Egbert Eichb543fb02013-04-16 13:36:54 +02001556 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1557 dev_priv->hpd_stats[i].hpd_last_jiffies
1558 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1559 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1560 dev_priv->hpd_stats[i].hpd_cnt = 0;
Egbert Eichb8f102e2013-07-26 14:14:24 +02001561 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
Egbert Eichb543fb02013-04-16 13:36:54 +02001562 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1563 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
Egbert Eich142e2392013-04-11 15:57:57 +02001564 dev_priv->hpd_event_bits &= ~(1 << i);
Egbert Eichb543fb02013-04-16 13:36:54 +02001565 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
Daniel Vetter10a504d2013-06-27 17:52:12 +02001566 storm_detected = true;
Egbert Eichb543fb02013-04-16 13:36:54 +02001567 } else {
1568 dev_priv->hpd_stats[i].hpd_cnt++;
Egbert Eichb8f102e2013-07-26 14:14:24 +02001569 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1570 dev_priv->hpd_stats[i].hpd_cnt);
Egbert Eichb543fb02013-04-16 13:36:54 +02001571 }
1572 }
1573
Daniel Vetter10a504d2013-06-27 17:52:12 +02001574 if (storm_detected)
1575 dev_priv->display.hpd_irq_setup(dev);
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02001576 spin_unlock(&dev_priv->irq_lock);
Daniel Vetter5876fa02013-06-27 17:52:13 +02001577
Daniel Vetter645416f2013-09-02 16:22:25 +02001578 /*
1579 * Our hotplug handler can grab modeset locks (by calling down into the
1580 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1581 * queue for otherwise the flush_work in the pageflip code will
1582 * deadlock.
1583 */
Dave Airlie13cf5502014-06-18 11:29:35 +10001584 if (queue_dig)
Dave Airlie0e32b392014-05-02 14:02:48 +10001585 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
Dave Airlie13cf5502014-06-18 11:29:35 +10001586 if (queue_hp)
1587 schedule_work(&dev_priv->hotplug_work);
Egbert Eichb543fb02013-04-16 13:36:54 +02001588}
1589
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001590static void gmbus_irq_handler(struct drm_device *dev)
1591{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001592 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter28c70f12012-12-01 13:53:45 +01001593
Daniel Vetter28c70f12012-12-01 13:53:45 +01001594 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001595}
1596
Daniel Vetterce99c252012-12-01 13:53:47 +01001597static void dp_aux_irq_handler(struct drm_device *dev)
1598{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001599 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001600
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001601 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetterce99c252012-12-01 13:53:47 +01001602}
1603
Shuang He8bf1e9f2013-10-15 18:55:27 +01001604#if defined(CONFIG_DEBUG_FS)
Daniel Vetter277de952013-10-18 16:37:07 +02001605static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1606 uint32_t crc0, uint32_t crc1,
1607 uint32_t crc2, uint32_t crc3,
1608 uint32_t crc4)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001609{
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1612 struct intel_pipe_crc_entry *entry;
Damien Lespiauac2300d2013-10-15 18:55:30 +01001613 int head, tail;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001614
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001615 spin_lock(&pipe_crc->lock);
1616
Damien Lespiau0c912c72013-10-15 18:55:37 +01001617 if (!pipe_crc->entries) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001618 spin_unlock(&pipe_crc->lock);
Damien Lespiau0c912c72013-10-15 18:55:37 +01001619 DRM_ERROR("spurious interrupt\n");
1620 return;
1621 }
1622
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001623 head = pipe_crc->head;
1624 tail = pipe_crc->tail;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001625
1626 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001627 spin_unlock(&pipe_crc->lock);
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001628 DRM_ERROR("CRC buffer overflowing\n");
1629 return;
1630 }
1631
1632 entry = &pipe_crc->entries[head];
Shuang He8bf1e9f2013-10-15 18:55:27 +01001633
Daniel Vetter8bc5e952013-10-16 22:55:49 +02001634 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
Daniel Vettereba94eb2013-10-16 22:55:46 +02001635 entry->crc[0] = crc0;
1636 entry->crc[1] = crc1;
1637 entry->crc[2] = crc2;
1638 entry->crc[3] = crc3;
1639 entry->crc[4] = crc4;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001640
1641 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001642 pipe_crc->head = head;
1643
1644 spin_unlock(&pipe_crc->lock);
Damien Lespiau07144422013-10-15 18:55:40 +01001645
1646 wake_up_interruptible(&pipe_crc->wq);
Shuang He8bf1e9f2013-10-15 18:55:27 +01001647}
Daniel Vetter277de952013-10-18 16:37:07 +02001648#else
1649static inline void
1650display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1651 uint32_t crc0, uint32_t crc1,
1652 uint32_t crc2, uint32_t crc3,
1653 uint32_t crc4) {}
1654#endif
Daniel Vettereba94eb2013-10-16 22:55:46 +02001655
Daniel Vetter277de952013-10-18 16:37:07 +02001656
1657static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vetter5a69b892013-10-16 22:55:52 +02001658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
Daniel Vetter277de952013-10-18 16:37:07 +02001661 display_pipe_crc_irq_handler(dev, pipe,
1662 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1663 0, 0, 0, 0);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001664}
1665
Daniel Vetter277de952013-10-18 16:37:07 +02001666static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vettereba94eb2013-10-16 22:55:46 +02001667{
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669
Daniel Vetter277de952013-10-18 16:37:07 +02001670 display_pipe_crc_irq_handler(dev, pipe,
1671 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1672 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1673 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1674 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1675 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
Daniel Vettereba94eb2013-10-16 22:55:46 +02001676}
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001677
Daniel Vetter277de952013-10-18 16:37:07 +02001678static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001679{
1680 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02001681 uint32_t res1, res2;
1682
1683 if (INTEL_INFO(dev)->gen >= 3)
1684 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1685 else
1686 res1 = 0;
1687
1688 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1689 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1690 else
1691 res2 = 0;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001692
Daniel Vetter277de952013-10-18 16:37:07 +02001693 display_pipe_crc_irq_handler(dev, pipe,
1694 I915_READ(PIPE_CRC_RES_RED(pipe)),
1695 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1696 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1697 res1, res2);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001698}
Shuang He8bf1e9f2013-10-15 18:55:27 +01001699
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001700/* The RPS events need forcewake, so we add them to a work queue and mask their
1701 * IMR bits until the work is done. Other interrupts can be processed without
1702 * the work queue. */
1703static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
Ben Widawskybaf02a12013-05-28 19:22:24 -07001704{
Deepak Sa6706b42014-03-15 20:23:22 +05301705 if (pm_iir & dev_priv->pm_rps_events) {
Daniel Vetter59cdb632013-07-04 23:35:28 +02001706 spin_lock(&dev_priv->irq_lock);
Deepak Sa6706b42014-03-15 20:23:22 +05301707 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
Daniel Vetter480c8032014-07-16 09:49:40 +02001708 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
Daniel Vetter59cdb632013-07-04 23:35:28 +02001709 spin_unlock(&dev_priv->irq_lock);
Daniel Vetter2adbee62013-07-04 23:35:27 +02001710
1711 queue_work(dev_priv->wq, &dev_priv->rps.work);
Ben Widawskybaf02a12013-05-28 19:22:24 -07001712 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001713
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001714 if (HAS_VEBOX(dev_priv->dev)) {
1715 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1716 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
Ben Widawsky12638c52013-05-28 19:22:31 -07001717
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001718 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
Mika Kuoppala58174462014-02-25 17:11:26 +02001719 i915_handle_error(dev_priv->dev, false,
1720 "VEBOX CS error interrupt 0x%08x",
1721 pm_iir);
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001722 }
Ben Widawsky12638c52013-05-28 19:22:31 -07001723 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001724}
1725
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001726static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1727{
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001728 if (!drm_handle_vblank(dev, pipe))
1729 return false;
1730
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001731 return true;
1732}
1733
Imre Deakc1874ed2014-02-04 21:35:46 +02001734static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1735{
1736 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak91d181d2014-02-10 18:42:49 +02001737 u32 pipe_stats[I915_MAX_PIPES] = { };
Imre Deakc1874ed2014-02-04 21:35:46 +02001738 int pipe;
1739
Imre Deak58ead0d2014-02-04 21:35:47 +02001740 spin_lock(&dev_priv->irq_lock);
Damien Lespiau055e3932014-08-18 13:49:10 +01001741 for_each_pipe(dev_priv, pipe) {
Imre Deak91d181d2014-02-10 18:42:49 +02001742 int reg;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001743 u32 mask, iir_bit = 0;
Imre Deak91d181d2014-02-10 18:42:49 +02001744
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001745 /*
1746 * PIPESTAT bits get signalled even when the interrupt is
1747 * disabled with the mask bits, and some of the status bits do
1748 * not generate interrupts at all (like the underrun bit). Hence
1749 * we need to be careful that we only handle what we want to
1750 * handle.
1751 */
1752 mask = 0;
1753 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1754 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1755
1756 switch (pipe) {
1757 case PIPE_A:
1758 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1759 break;
1760 case PIPE_B:
1761 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1762 break;
Ville Syrjälä3278f672014-04-09 13:28:49 +03001763 case PIPE_C:
1764 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1765 break;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001766 }
1767 if (iir & iir_bit)
1768 mask |= dev_priv->pipestat_irq_mask[pipe];
1769
1770 if (!mask)
Imre Deak91d181d2014-02-10 18:42:49 +02001771 continue;
1772
1773 reg = PIPESTAT(pipe);
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001774 mask |= PIPESTAT_INT_ENABLE_MASK;
1775 pipe_stats[pipe] = I915_READ(reg) & mask;
Imre Deakc1874ed2014-02-04 21:35:46 +02001776
1777 /*
1778 * Clear the PIPE*STAT regs before the IIR
1779 */
Imre Deak91d181d2014-02-10 18:42:49 +02001780 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1781 PIPESTAT_INT_STATUS_MASK))
Imre Deakc1874ed2014-02-04 21:35:46 +02001782 I915_WRITE(reg, pipe_stats[pipe]);
1783 }
Imre Deak58ead0d2014-02-04 21:35:47 +02001784 spin_unlock(&dev_priv->irq_lock);
Imre Deakc1874ed2014-02-04 21:35:46 +02001785
Damien Lespiau055e3932014-08-18 13:49:10 +01001786 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01001787 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1788 intel_pipe_handle_vblank(dev, pipe))
1789 intel_check_page_flip(dev, pipe);
Imre Deakc1874ed2014-02-04 21:35:46 +02001790
Imre Deak579a9b02014-02-04 21:35:48 +02001791 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
Imre Deakc1874ed2014-02-04 21:35:46 +02001792 intel_prepare_page_flip(dev, pipe);
1793 intel_finish_page_flip(dev, pipe);
1794 }
1795
1796 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1797 i9xx_pipe_crc_irq_handler(dev, pipe);
1798
1799 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1800 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1801 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1802 }
1803
1804 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1805 gmbus_irq_handler(dev);
1806}
1807
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001808static void i9xx_hpd_irq_handler(struct drm_device *dev)
1809{
1810 struct drm_i915_private *dev_priv = dev->dev_private;
1811 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1812
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001813 if (hotplug_status) {
1814 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1815 /*
1816 * Make sure hotplug status is cleared before we clear IIR, or else we
1817 * may miss hotplug events.
1818 */
1819 POSTING_READ(PORT_HOTPLUG_STAT);
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001820
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001821 if (IS_G4X(dev)) {
1822 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001823
Dave Airlie13cf5502014-06-18 11:29:35 +10001824 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001825 } else {
1826 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1827
Dave Airlie13cf5502014-06-18 11:29:35 +10001828 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001829 }
1830
1831 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1832 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1833 dp_aux_irq_handler(dev);
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001834 }
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001835}
1836
Daniel Vetterff1f5252012-10-02 15:10:55 +02001837static irqreturn_t valleyview_irq_handler(int irq, void *arg)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001838{
Daniel Vetter45a83f82014-05-12 19:17:55 +02001839 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03001840 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001841 u32 iir, gt_iir, pm_iir;
1842 irqreturn_t ret = IRQ_NONE;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001843
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001844 while (true) {
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001845 /* Find, clear, then process each source of interrupt */
1846
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001847 gt_iir = I915_READ(GTIIR);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001848 if (gt_iir)
1849 I915_WRITE(GTIIR, gt_iir);
1850
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001851 pm_iir = I915_READ(GEN6_PMIIR);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001852 if (pm_iir)
1853 I915_WRITE(GEN6_PMIIR, pm_iir);
1854
1855 iir = I915_READ(VLV_IIR);
1856 if (iir) {
1857 /* Consume port before clearing IIR or we'll miss events */
1858 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1859 i9xx_hpd_irq_handler(dev);
1860 I915_WRITE(VLV_IIR, iir);
1861 }
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001862
1863 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1864 goto out;
1865
1866 ret = IRQ_HANDLED;
1867
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001868 if (gt_iir)
1869 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Paulo Zanoni60611c12013-08-15 11:50:01 -03001870 if (pm_iir)
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001871 gen6_rps_irq_handler(dev_priv, pm_iir);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001872 /* Call regardless, as some status bits might not be
1873 * signalled in iir */
1874 valleyview_pipestat_irq_handler(dev, iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001875 }
1876
1877out:
1878 return ret;
1879}
1880
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001881static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1882{
Daniel Vetter45a83f82014-05-12 19:17:55 +02001883 struct drm_device *dev = arg;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 u32 master_ctl, iir;
1886 irqreturn_t ret = IRQ_NONE;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001887
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001888 for (;;) {
1889 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1890 iir = I915_READ(VLV_IIR);
Ville Syrjälä3278f672014-04-09 13:28:49 +03001891
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001892 if (master_ctl == 0 && iir == 0)
1893 break;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001894
Oscar Mateo27b6c122014-06-16 16:11:00 +01001895 ret = IRQ_HANDLED;
1896
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001897 I915_WRITE(GEN8_MASTER_IRQ, 0);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001898
Oscar Mateo27b6c122014-06-16 16:11:00 +01001899 /* Find, clear, then process each source of interrupt */
1900
1901 if (iir) {
1902 /* Consume port before clearing IIR or we'll miss events */
1903 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1904 i9xx_hpd_irq_handler(dev);
1905 I915_WRITE(VLV_IIR, iir);
1906 }
1907
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001908 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001909
Oscar Mateo27b6c122014-06-16 16:11:00 +01001910 /* Call regardless, as some status bits might not be
1911 * signalled in iir */
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001912 valleyview_pipestat_irq_handler(dev, iir);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001913
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001914 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1915 POSTING_READ(GEN8_MASTER_IRQ);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001916 }
1917
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001918 return ret;
1919}
1920
Adam Jackson23e81d62012-06-06 15:45:44 -04001921static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
Jesse Barnes776ad802011-01-04 15:09:39 -08001922{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001923 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001924 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02001925 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
Dave Airlie13cf5502014-06-18 11:29:35 +10001926 u32 dig_hotplug_reg;
Jesse Barnes776ad802011-01-04 15:09:39 -08001927
Dave Airlie13cf5502014-06-18 11:29:35 +10001928 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1929 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1930
1931 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
Daniel Vetter91d131d2013-06-27 17:52:14 +02001932
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001933 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1934 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1935 SDE_AUDIO_POWER_SHIFT);
Jesse Barnes776ad802011-01-04 15:09:39 -08001936 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001937 port_name(port));
1938 }
Jesse Barnes776ad802011-01-04 15:09:39 -08001939
Daniel Vetterce99c252012-12-01 13:53:47 +01001940 if (pch_iir & SDE_AUX_MASK)
1941 dp_aux_irq_handler(dev);
1942
Jesse Barnes776ad802011-01-04 15:09:39 -08001943 if (pch_iir & SDE_GMBUS)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001944 gmbus_irq_handler(dev);
Jesse Barnes776ad802011-01-04 15:09:39 -08001945
1946 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1947 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1948
1949 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1950 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1951
1952 if (pch_iir & SDE_POISON)
1953 DRM_ERROR("PCH poison interrupt\n");
1954
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001955 if (pch_iir & SDE_FDI_MASK)
Damien Lespiau055e3932014-08-18 13:49:10 +01001956 for_each_pipe(dev_priv, pipe)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001957 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1958 pipe_name(pipe),
1959 I915_READ(FDI_RX_IIR(pipe)));
Jesse Barnes776ad802011-01-04 15:09:39 -08001960
1961 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1962 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1963
1964 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1965 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1966
Jesse Barnes776ad802011-01-04 15:09:39 -08001967 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
Paulo Zanoni86642812013-04-12 17:57:57 -03001968 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1969 false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02001970 DRM_ERROR("PCH transcoder A FIFO underrun\n");
Paulo Zanoni86642812013-04-12 17:57:57 -03001971
1972 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1973 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1974 false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02001975 DRM_ERROR("PCH transcoder B FIFO underrun\n");
Paulo Zanoni86642812013-04-12 17:57:57 -03001976}
1977
1978static void ivb_err_int_handler(struct drm_device *dev)
1979{
1980 struct drm_i915_private *dev_priv = dev->dev_private;
1981 u32 err_int = I915_READ(GEN7_ERR_INT);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001982 enum pipe pipe;
Paulo Zanoni86642812013-04-12 17:57:57 -03001983
Paulo Zanonide032bf2013-04-12 17:57:58 -03001984 if (err_int & ERR_INT_POISON)
1985 DRM_ERROR("Poison interrupt\n");
1986
Damien Lespiau055e3932014-08-18 13:49:10 +01001987 for_each_pipe(dev_priv, pipe) {
Daniel Vetter5a69b892013-10-16 22:55:52 +02001988 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1989 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1990 false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02001991 DRM_ERROR("Pipe %c FIFO underrun\n",
1992 pipe_name(pipe));
Daniel Vetter5a69b892013-10-16 22:55:52 +02001993 }
Paulo Zanoni86642812013-04-12 17:57:57 -03001994
Daniel Vetter5a69b892013-10-16 22:55:52 +02001995 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1996 if (IS_IVYBRIDGE(dev))
Daniel Vetter277de952013-10-18 16:37:07 +02001997 ivb_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001998 else
Daniel Vetter277de952013-10-18 16:37:07 +02001999 hsw_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5a69b892013-10-16 22:55:52 +02002000 }
2001 }
Shuang He8bf1e9f2013-10-15 18:55:27 +01002002
Paulo Zanoni86642812013-04-12 17:57:57 -03002003 I915_WRITE(GEN7_ERR_INT, err_int);
2004}
2005
2006static void cpt_serr_int_handler(struct drm_device *dev)
2007{
2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009 u32 serr_int = I915_READ(SERR_INT);
2010
Paulo Zanonide032bf2013-04-12 17:57:58 -03002011 if (serr_int & SERR_INT_POISON)
2012 DRM_ERROR("PCH poison interrupt\n");
2013
Paulo Zanoni86642812013-04-12 17:57:57 -03002014 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2015 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2016 false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02002017 DRM_ERROR("PCH transcoder A FIFO underrun\n");
Paulo Zanoni86642812013-04-12 17:57:57 -03002018
2019 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2020 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2021 false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02002022 DRM_ERROR("PCH transcoder B FIFO underrun\n");
Paulo Zanoni86642812013-04-12 17:57:57 -03002023
2024 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2025 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2026 false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02002027 DRM_ERROR("PCH transcoder C FIFO underrun\n");
Paulo Zanoni86642812013-04-12 17:57:57 -03002028
2029 I915_WRITE(SERR_INT, serr_int);
Jesse Barnes776ad802011-01-04 15:09:39 -08002030}
2031
Adam Jackson23e81d62012-06-06 15:45:44 -04002032static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2033{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002034 struct drm_i915_private *dev_priv = dev->dev_private;
Adam Jackson23e81d62012-06-06 15:45:44 -04002035 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02002036 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
Dave Airlie13cf5502014-06-18 11:29:35 +10002037 u32 dig_hotplug_reg;
Adam Jackson23e81d62012-06-06 15:45:44 -04002038
Dave Airlie13cf5502014-06-18 11:29:35 +10002039 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2040 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2041
2042 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
Daniel Vetter91d131d2013-06-27 17:52:14 +02002043
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03002044 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2045 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2046 SDE_AUDIO_POWER_SHIFT_CPT);
2047 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2048 port_name(port));
2049 }
Adam Jackson23e81d62012-06-06 15:45:44 -04002050
2051 if (pch_iir & SDE_AUX_MASK_CPT)
Daniel Vetterce99c252012-12-01 13:53:47 +01002052 dp_aux_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04002053
2054 if (pch_iir & SDE_GMBUS_CPT)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01002055 gmbus_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04002056
2057 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2058 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2059
2060 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2061 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2062
2063 if (pch_iir & SDE_FDI_MASK_CPT)
Damien Lespiau055e3932014-08-18 13:49:10 +01002064 for_each_pipe(dev_priv, pipe)
Adam Jackson23e81d62012-06-06 15:45:44 -04002065 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2066 pipe_name(pipe),
2067 I915_READ(FDI_RX_IIR(pipe)));
Paulo Zanoni86642812013-04-12 17:57:57 -03002068
2069 if (pch_iir & SDE_ERROR_CPT)
2070 cpt_serr_int_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04002071}
2072
Paulo Zanonic008bc62013-07-12 16:35:10 -03002073static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2074{
2075 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter40da17c2013-10-21 18:04:36 +02002076 enum pipe pipe;
Paulo Zanonic008bc62013-07-12 16:35:10 -03002077
2078 if (de_iir & DE_AUX_CHANNEL_A)
2079 dp_aux_irq_handler(dev);
2080
2081 if (de_iir & DE_GSE)
2082 intel_opregion_asle_intr(dev);
2083
Paulo Zanonic008bc62013-07-12 16:35:10 -03002084 if (de_iir & DE_POISON)
2085 DRM_ERROR("Poison interrupt\n");
2086
Damien Lespiau055e3932014-08-18 13:49:10 +01002087 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002088 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2089 intel_pipe_handle_vblank(dev, pipe))
2090 intel_check_page_flip(dev, pipe);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002091
Daniel Vetter40da17c2013-10-21 18:04:36 +02002092 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2093 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02002094 DRM_ERROR("Pipe %c FIFO underrun\n",
2095 pipe_name(pipe));
Paulo Zanonic008bc62013-07-12 16:35:10 -03002096
Daniel Vetter40da17c2013-10-21 18:04:36 +02002097 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2098 i9xx_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002099
Daniel Vetter40da17c2013-10-21 18:04:36 +02002100 /* plane/pipes map 1:1 on ilk+ */
2101 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2102 intel_prepare_page_flip(dev, pipe);
2103 intel_finish_page_flip_plane(dev, pipe);
2104 }
Paulo Zanonic008bc62013-07-12 16:35:10 -03002105 }
2106
2107 /* check event from PCH */
2108 if (de_iir & DE_PCH_EVENT) {
2109 u32 pch_iir = I915_READ(SDEIIR);
2110
2111 if (HAS_PCH_CPT(dev))
2112 cpt_irq_handler(dev, pch_iir);
2113 else
2114 ibx_irq_handler(dev, pch_iir);
2115
2116 /* should clear PCH hotplug event before clear CPU irq */
2117 I915_WRITE(SDEIIR, pch_iir);
2118 }
2119
2120 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2121 ironlake_rps_change_irq_handler(dev);
2122}
2123
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002124static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2125{
2126 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau07d27e22014-03-03 17:31:46 +00002127 enum pipe pipe;
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002128
2129 if (de_iir & DE_ERR_INT_IVB)
2130 ivb_err_int_handler(dev);
2131
2132 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2133 dp_aux_irq_handler(dev);
2134
2135 if (de_iir & DE_GSE_IVB)
2136 intel_opregion_asle_intr(dev);
2137
Damien Lespiau055e3932014-08-18 13:49:10 +01002138 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002139 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2140 intel_pipe_handle_vblank(dev, pipe))
2141 intel_check_page_flip(dev, pipe);
Daniel Vetter40da17c2013-10-21 18:04:36 +02002142
2143 /* plane/pipes map 1:1 on ilk+ */
Damien Lespiau07d27e22014-03-03 17:31:46 +00002144 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2145 intel_prepare_page_flip(dev, pipe);
2146 intel_finish_page_flip_plane(dev, pipe);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002147 }
2148 }
2149
2150 /* check event from PCH */
2151 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2152 u32 pch_iir = I915_READ(SDEIIR);
2153
2154 cpt_irq_handler(dev, pch_iir);
2155
2156 /* clear PCH hotplug event before clear CPU irq */
2157 I915_WRITE(SDEIIR, pch_iir);
2158 }
2159}
2160
Oscar Mateo72c90f62014-06-16 16:10:57 +01002161/*
2162 * To handle irqs with the minimum potential races with fresh interrupts, we:
2163 * 1 - Disable Master Interrupt Control.
2164 * 2 - Find the source(s) of the interrupt.
2165 * 3 - Clear the Interrupt Identity bits (IIR).
2166 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2167 * 5 - Re-enable Master Interrupt Control.
2168 */
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002169static irqreturn_t ironlake_irq_handler(int irq, void *arg)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002170{
Daniel Vetter45a83f82014-05-12 19:17:55 +02002171 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03002172 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002173 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
Chris Wilson0e434062012-05-09 21:45:44 +01002174 irqreturn_t ret = IRQ_NONE;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002175
Paulo Zanoni86642812013-04-12 17:57:57 -03002176 /* We get interrupts on unclaimed registers, so check for this before we
2177 * do any I915_{READ,WRITE}. */
Chris Wilson907b28c2013-07-19 20:36:52 +01002178 intel_uncore_check_errors(dev);
Paulo Zanoni86642812013-04-12 17:57:57 -03002179
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002180 /* disable master interrupt before clearing iir */
2181 de_ier = I915_READ(DEIER);
2182 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Paulo Zanoni23a78512013-07-12 16:35:14 -03002183 POSTING_READ(DEIER);
Chris Wilson0e434062012-05-09 21:45:44 +01002184
Paulo Zanoni44498ae2013-02-22 17:05:28 -03002185 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2186 * interrupts will will be stored on its back queue, and then we'll be
2187 * able to process them after we restore SDEIER (as soon as we restore
2188 * it, we'll get an interrupt if SDEIIR still has something to process
2189 * due to its back queue). */
Ben Widawskyab5c6082013-04-05 13:12:41 -07002190 if (!HAS_PCH_NOP(dev)) {
2191 sde_ier = I915_READ(SDEIER);
2192 I915_WRITE(SDEIER, 0);
2193 POSTING_READ(SDEIER);
2194 }
Paulo Zanoni44498ae2013-02-22 17:05:28 -03002195
Oscar Mateo72c90f62014-06-16 16:10:57 +01002196 /* Find, clear, then process each source of interrupt */
2197
Chris Wilson0e434062012-05-09 21:45:44 +01002198 gt_iir = I915_READ(GTIIR);
2199 if (gt_iir) {
Oscar Mateo72c90f62014-06-16 16:10:57 +01002200 I915_WRITE(GTIIR, gt_iir);
2201 ret = IRQ_HANDLED;
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03002202 if (INTEL_INFO(dev)->gen >= 6)
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002203 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03002204 else
2205 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01002206 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002207
2208 de_iir = I915_READ(DEIIR);
Chris Wilson0e434062012-05-09 21:45:44 +01002209 if (de_iir) {
Oscar Mateo72c90f62014-06-16 16:10:57 +01002210 I915_WRITE(DEIIR, de_iir);
2211 ret = IRQ_HANDLED;
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002212 if (INTEL_INFO(dev)->gen >= 7)
2213 ivb_display_irq_handler(dev, de_iir);
2214 else
2215 ilk_display_irq_handler(dev, de_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01002216 }
2217
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002218 if (INTEL_INFO(dev)->gen >= 6) {
2219 u32 pm_iir = I915_READ(GEN6_PMIIR);
2220 if (pm_iir) {
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002221 I915_WRITE(GEN6_PMIIR, pm_iir);
2222 ret = IRQ_HANDLED;
Oscar Mateo72c90f62014-06-16 16:10:57 +01002223 gen6_rps_irq_handler(dev_priv, pm_iir);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002224 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002225 }
2226
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002227 I915_WRITE(DEIER, de_ier);
2228 POSTING_READ(DEIER);
Ben Widawskyab5c6082013-04-05 13:12:41 -07002229 if (!HAS_PCH_NOP(dev)) {
2230 I915_WRITE(SDEIER, sde_ier);
2231 POSTING_READ(SDEIER);
2232 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002233
2234 return ret;
2235}
2236
Ben Widawskyabd58f02013-11-02 21:07:09 -07002237static irqreturn_t gen8_irq_handler(int irq, void *arg)
2238{
2239 struct drm_device *dev = arg;
2240 struct drm_i915_private *dev_priv = dev->dev_private;
2241 u32 master_ctl;
2242 irqreturn_t ret = IRQ_NONE;
2243 uint32_t tmp = 0;
Daniel Vetterc42664c2013-11-07 11:05:40 +01002244 enum pipe pipe;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002245
Ben Widawskyabd58f02013-11-02 21:07:09 -07002246 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2247 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2248 if (!master_ctl)
2249 return IRQ_NONE;
2250
2251 I915_WRITE(GEN8_MASTER_IRQ, 0);
2252 POSTING_READ(GEN8_MASTER_IRQ);
2253
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002254 /* Find, clear, then process each source of interrupt */
2255
Ben Widawskyabd58f02013-11-02 21:07:09 -07002256 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2257
2258 if (master_ctl & GEN8_DE_MISC_IRQ) {
2259 tmp = I915_READ(GEN8_DE_MISC_IIR);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002260 if (tmp) {
2261 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2262 ret = IRQ_HANDLED;
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002263 if (tmp & GEN8_DE_MISC_GSE)
2264 intel_opregion_asle_intr(dev);
2265 else
2266 DRM_ERROR("Unexpected DE Misc interrupt\n");
Ben Widawskyabd58f02013-11-02 21:07:09 -07002267 }
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002268 else
2269 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
Ben Widawskyabd58f02013-11-02 21:07:09 -07002270 }
2271
Daniel Vetter6d766f02013-11-07 14:49:55 +01002272 if (master_ctl & GEN8_DE_PORT_IRQ) {
2273 tmp = I915_READ(GEN8_DE_PORT_IIR);
Daniel Vetter6d766f02013-11-07 14:49:55 +01002274 if (tmp) {
2275 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2276 ret = IRQ_HANDLED;
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002277 if (tmp & GEN8_AUX_CHANNEL_A)
2278 dp_aux_irq_handler(dev);
2279 else
2280 DRM_ERROR("Unexpected DE Port interrupt\n");
Daniel Vetter6d766f02013-11-07 14:49:55 +01002281 }
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002282 else
2283 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
Daniel Vetter6d766f02013-11-07 14:49:55 +01002284 }
2285
Damien Lespiau055e3932014-08-18 13:49:10 +01002286 for_each_pipe(dev_priv, pipe) {
Damien Lespiau770de832014-03-20 20:45:01 +00002287 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002288
Daniel Vetterc42664c2013-11-07 11:05:40 +01002289 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2290 continue;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002291
Daniel Vetterc42664c2013-11-07 11:05:40 +01002292 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
Daniel Vetterc42664c2013-11-07 11:05:40 +01002293 if (pipe_iir) {
2294 ret = IRQ_HANDLED;
2295 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
Damien Lespiau770de832014-03-20 20:45:01 +00002296
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002297 if (pipe_iir & GEN8_PIPE_VBLANK &&
2298 intel_pipe_handle_vblank(dev, pipe))
2299 intel_check_page_flip(dev, pipe);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002300
Damien Lespiau770de832014-03-20 20:45:01 +00002301 if (IS_GEN9(dev))
2302 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2303 else
2304 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2305
2306 if (flip_done) {
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002307 intel_prepare_page_flip(dev, pipe);
2308 intel_finish_page_flip_plane(dev, pipe);
2309 }
2310
2311 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2312 hsw_pipe_crc_irq_handler(dev, pipe);
2313
2314 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2315 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2316 false))
2317 DRM_ERROR("Pipe %c FIFO underrun\n",
2318 pipe_name(pipe));
2319 }
2320
Damien Lespiau770de832014-03-20 20:45:01 +00002321
2322 if (IS_GEN9(dev))
2323 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2324 else
2325 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2326
2327 if (fault_errors)
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002328 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2329 pipe_name(pipe),
2330 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
Daniel Vetterc42664c2013-11-07 11:05:40 +01002331 } else
Ben Widawskyabd58f02013-11-02 21:07:09 -07002332 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2333 }
2334
Daniel Vetter92d03a82013-11-07 11:05:43 +01002335 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2336 /*
2337 * FIXME(BDW): Assume for now that the new interrupt handling
2338 * scheme also closed the SDE interrupt handling race we've seen
2339 * on older pch-split platforms. But this needs testing.
2340 */
2341 u32 pch_iir = I915_READ(SDEIIR);
Daniel Vetter92d03a82013-11-07 11:05:43 +01002342 if (pch_iir) {
2343 I915_WRITE(SDEIIR, pch_iir);
2344 ret = IRQ_HANDLED;
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002345 cpt_irq_handler(dev, pch_iir);
2346 } else
2347 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2348
Daniel Vetter92d03a82013-11-07 11:05:43 +01002349 }
2350
Ben Widawskyabd58f02013-11-02 21:07:09 -07002351 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2352 POSTING_READ(GEN8_MASTER_IRQ);
2353
2354 return ret;
2355}
2356
Daniel Vetter17e1df02013-09-08 21:57:13 +02002357static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2358 bool reset_completed)
2359{
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002360 struct intel_engine_cs *ring;
Daniel Vetter17e1df02013-09-08 21:57:13 +02002361 int i;
2362
2363 /*
2364 * Notify all waiters for GPU completion events that reset state has
2365 * been changed, and that they need to restart their wait after
2366 * checking for potential errors (and bail out to drop locks if there is
2367 * a gpu reset pending so that i915_error_work_func can acquire them).
2368 */
2369
2370 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2371 for_each_ring(ring, dev_priv, i)
2372 wake_up_all(&ring->irq_queue);
2373
2374 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2375 wake_up_all(&dev_priv->pending_flip_queue);
2376
2377 /*
2378 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2379 * reset state is cleared.
2380 */
2381 if (reset_completed)
2382 wake_up_all(&dev_priv->gpu_error.reset_queue);
2383}
2384
Jesse Barnes8a905232009-07-11 16:48:03 -04002385/**
2386 * i915_error_work_func - do process context error handling work
2387 * @work: work struct
2388 *
2389 * Fire an error uevent so userspace can see that a hang or error
2390 * was detected.
2391 */
2392static void i915_error_work_func(struct work_struct *work)
2393{
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002394 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2395 work);
Jani Nikula2d1013d2014-03-31 14:27:17 +03002396 struct drm_i915_private *dev_priv =
2397 container_of(error, struct drm_i915_private, gpu_error);
Jesse Barnes8a905232009-07-11 16:48:03 -04002398 struct drm_device *dev = dev_priv->dev;
Ben Widawskycce723e2013-07-19 09:16:42 -07002399 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2400 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2401 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
Daniel Vetter17e1df02013-09-08 21:57:13 +02002402 int ret;
Jesse Barnes8a905232009-07-11 16:48:03 -04002403
Dave Airlie5bdebb12013-10-11 14:07:25 +10002404 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -04002405
Daniel Vetter7db0ba22012-12-06 16:23:37 +01002406 /*
2407 * Note that there's only one work item which does gpu resets, so we
2408 * need not worry about concurrent gpu resets potentially incrementing
2409 * error->reset_counter twice. We only need to take care of another
2410 * racing irq/hangcheck declaring the gpu dead for a second time. A
2411 * quick check for that is good enough: schedule_work ensures the
2412 * correct ordering between hang detection and this work item, and since
2413 * the reset in-progress bit is only ever set by code outside of this
2414 * work we don't need to worry about any other races.
2415 */
2416 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
Chris Wilsonf803aa52010-09-19 12:38:26 +01002417 DRM_DEBUG_DRIVER("resetting chip\n");
Dave Airlie5bdebb12013-10-11 14:07:25 +10002418 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
Daniel Vetter7db0ba22012-12-06 16:23:37 +01002419 reset_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002420
Daniel Vetter17e1df02013-09-08 21:57:13 +02002421 /*
Imre Deakf454c692014-04-23 01:09:04 +03002422 * In most cases it's guaranteed that we get here with an RPM
2423 * reference held, for example because there is a pending GPU
2424 * request that won't finish until the reset is done. This
2425 * isn't the case at least when we get here by doing a
2426 * simulated reset via debugs, so get an RPM reference.
2427 */
2428 intel_runtime_pm_get(dev_priv);
2429 /*
Daniel Vetter17e1df02013-09-08 21:57:13 +02002430 * All state reset _must_ be completed before we update the
2431 * reset counter, for otherwise waiters might miss the reset
2432 * pending state and not properly drop locks, resulting in
2433 * deadlocks with the reset work.
2434 */
Daniel Vetterf69061b2012-12-06 09:01:42 +01002435 ret = i915_reset(dev);
2436
Daniel Vetter17e1df02013-09-08 21:57:13 +02002437 intel_display_handle_reset(dev);
2438
Imre Deakf454c692014-04-23 01:09:04 +03002439 intel_runtime_pm_put(dev_priv);
2440
Daniel Vetterf69061b2012-12-06 09:01:42 +01002441 if (ret == 0) {
2442 /*
2443 * After all the gem state is reset, increment the reset
2444 * counter and wake up everyone waiting for the reset to
2445 * complete.
2446 *
2447 * Since unlock operations are a one-sided barrier only,
2448 * we need to insert a barrier here to order any seqno
2449 * updates before
2450 * the counter increment.
2451 */
Peter Zijlstra4e857c52014-03-17 18:06:10 +01002452 smp_mb__before_atomic();
Daniel Vetterf69061b2012-12-06 09:01:42 +01002453 atomic_inc(&dev_priv->gpu_error.reset_counter);
2454
Dave Airlie5bdebb12013-10-11 14:07:25 +10002455 kobject_uevent_env(&dev->primary->kdev->kobj,
Daniel Vetterf69061b2012-12-06 09:01:42 +01002456 KOBJ_CHANGE, reset_done_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002457 } else {
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002458 atomic_set_mask(I915_WEDGED, &error->reset_counter);
Ben Gamarif316a422009-09-14 17:48:46 -04002459 }
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002460
Daniel Vetter17e1df02013-09-08 21:57:13 +02002461 /*
2462 * Note: The wake_up also serves as a memory barrier so that
2463 * waiters see the update value of the reset counter atomic_t.
2464 */
2465 i915_error_wake_up(dev_priv, true);
Ben Gamarif316a422009-09-14 17:48:46 -04002466 }
Jesse Barnes8a905232009-07-11 16:48:03 -04002467}
2468
Chris Wilson35aed2e2010-05-27 13:18:12 +01002469static void i915_report_and_clear_eir(struct drm_device *dev)
Jesse Barnes8a905232009-07-11 16:48:03 -04002470{
2471 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybd9854f2012-08-23 15:18:09 -07002472 uint32_t instdone[I915_NUM_INSTDONE_REG];
Jesse Barnes8a905232009-07-11 16:48:03 -04002473 u32 eir = I915_READ(EIR);
Ben Widawsky050ee912012-08-22 11:32:15 -07002474 int pipe, i;
Jesse Barnes8a905232009-07-11 16:48:03 -04002475
Chris Wilson35aed2e2010-05-27 13:18:12 +01002476 if (!eir)
2477 return;
Jesse Barnes8a905232009-07-11 16:48:03 -04002478
Joe Perchesa70491c2012-03-18 13:00:11 -07002479 pr_err("render error detected, EIR: 0x%08x\n", eir);
Jesse Barnes8a905232009-07-11 16:48:03 -04002480
Ben Widawskybd9854f2012-08-23 15:18:09 -07002481 i915_get_extra_instdone(dev, instdone);
2482
Jesse Barnes8a905232009-07-11 16:48:03 -04002483 if (IS_G4X(dev)) {
2484 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2485 u32 ipeir = I915_READ(IPEIR_I965);
2486
Joe Perchesa70491c2012-03-18 13:00:11 -07002487 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2488 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Ben Widawsky050ee912012-08-22 11:32:15 -07002489 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2490 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Joe Perchesa70491c2012-03-18 13:00:11 -07002491 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07002492 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04002493 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002494 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04002495 }
2496 if (eir & GM45_ERROR_PAGE_TABLE) {
2497 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07002498 pr_err("page table error\n");
2499 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04002500 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002501 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04002502 }
2503 }
2504
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002505 if (!IS_GEN2(dev)) {
Jesse Barnes8a905232009-07-11 16:48:03 -04002506 if (eir & I915_ERROR_PAGE_TABLE) {
2507 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07002508 pr_err("page table error\n");
2509 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04002510 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002511 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04002512 }
2513 }
2514
2515 if (eir & I915_ERROR_MEMORY_REFRESH) {
Joe Perchesa70491c2012-03-18 13:00:11 -07002516 pr_err("memory refresh error:\n");
Damien Lespiau055e3932014-08-18 13:49:10 +01002517 for_each_pipe(dev_priv, pipe)
Joe Perchesa70491c2012-03-18 13:00:11 -07002518 pr_err("pipe %c stat: 0x%08x\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002519 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
Jesse Barnes8a905232009-07-11 16:48:03 -04002520 /* pipestat has already been acked */
2521 }
2522 if (eir & I915_ERROR_INSTRUCTION) {
Joe Perchesa70491c2012-03-18 13:00:11 -07002523 pr_err("instruction error\n");
2524 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
Ben Widawsky050ee912012-08-22 11:32:15 -07002525 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2526 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002527 if (INTEL_INFO(dev)->gen < 4) {
Jesse Barnes8a905232009-07-11 16:48:03 -04002528 u32 ipeir = I915_READ(IPEIR);
2529
Joe Perchesa70491c2012-03-18 13:00:11 -07002530 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2531 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
Joe Perchesa70491c2012-03-18 13:00:11 -07002532 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
Jesse Barnes8a905232009-07-11 16:48:03 -04002533 I915_WRITE(IPEIR, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002534 POSTING_READ(IPEIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04002535 } else {
2536 u32 ipeir = I915_READ(IPEIR_I965);
2537
Joe Perchesa70491c2012-03-18 13:00:11 -07002538 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2539 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Joe Perchesa70491c2012-03-18 13:00:11 -07002540 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07002541 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04002542 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002543 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04002544 }
2545 }
2546
2547 I915_WRITE(EIR, eir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002548 POSTING_READ(EIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04002549 eir = I915_READ(EIR);
2550 if (eir) {
2551 /*
2552 * some errors might have become stuck,
2553 * mask them.
2554 */
2555 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2556 I915_WRITE(EMR, I915_READ(EMR) | eir);
2557 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2558 }
Chris Wilson35aed2e2010-05-27 13:18:12 +01002559}
2560
2561/**
2562 * i915_handle_error - handle an error interrupt
2563 * @dev: drm device
2564 *
2565 * Do some basic checking of regsiter state at error interrupt time and
2566 * dump it to the syslog. Also call i915_capture_error_state() to make
2567 * sure we get a record and make it available in debugfs. Fire a uevent
2568 * so userspace knows something bad happened (should trigger collection
2569 * of a ring dump etc.).
2570 */
Mika Kuoppala58174462014-02-25 17:11:26 +02002571void i915_handle_error(struct drm_device *dev, bool wedged,
2572 const char *fmt, ...)
Chris Wilson35aed2e2010-05-27 13:18:12 +01002573{
2574 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppala58174462014-02-25 17:11:26 +02002575 va_list args;
2576 char error_msg[80];
Chris Wilson35aed2e2010-05-27 13:18:12 +01002577
Mika Kuoppala58174462014-02-25 17:11:26 +02002578 va_start(args, fmt);
2579 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2580 va_end(args);
2581
2582 i915_capture_error_state(dev, wedged, error_msg);
Chris Wilson35aed2e2010-05-27 13:18:12 +01002583 i915_report_and_clear_eir(dev);
Jesse Barnes8a905232009-07-11 16:48:03 -04002584
Ben Gamariba1234d2009-09-14 17:48:47 -04002585 if (wedged) {
Daniel Vetterf69061b2012-12-06 09:01:42 +01002586 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2587 &dev_priv->gpu_error.reset_counter);
Ben Gamariba1234d2009-09-14 17:48:47 -04002588
Ben Gamari11ed50e2009-09-14 17:48:45 -04002589 /*
Daniel Vetter17e1df02013-09-08 21:57:13 +02002590 * Wakeup waiting processes so that the reset work function
2591 * i915_error_work_func doesn't deadlock trying to grab various
2592 * locks. By bumping the reset counter first, the woken
2593 * processes will see a reset in progress and back off,
2594 * releasing their locks and then wait for the reset completion.
2595 * We must do this for _all_ gpu waiters that might hold locks
2596 * that the reset work needs to acquire.
2597 *
2598 * Note: The wake_up serves as the required memory barrier to
2599 * ensure that the waiters see the updated value of the reset
2600 * counter atomic_t.
Ben Gamari11ed50e2009-09-14 17:48:45 -04002601 */
Daniel Vetter17e1df02013-09-08 21:57:13 +02002602 i915_error_wake_up(dev_priv, false);
Ben Gamari11ed50e2009-09-14 17:48:45 -04002603 }
2604
Daniel Vetter122f46b2013-09-04 17:36:14 +02002605 /*
2606 * Our reset work can grab modeset locks (since it needs to reset the
2607 * state of outstanding pagelips). Hence it must not be run on our own
2608 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2609 * code will deadlock.
2610 */
2611 schedule_work(&dev_priv->gpu_error.work);
Jesse Barnes8a905232009-07-11 16:48:03 -04002612}
2613
Keith Packard42f52ef2008-10-18 19:39:29 -07002614/* Called from drm generic code, passed 'crtc' which
2615 * we use as a pipe index
2616 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002617static int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002618{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002619 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002620 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08002621
Chris Wilson5eddb702010-09-11 13:48:45 +01002622 if (!i915_pipe_enabled(dev, pipe))
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08002623 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002624
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002625 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002626 if (INTEL_INFO(dev)->gen >= 4)
Keith Packard7c463582008-11-04 02:03:27 -08002627 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002628 PIPE_START_VBLANK_INTERRUPT_STATUS);
Keith Packarde9d21d72008-10-16 11:31:38 -07002629 else
Keith Packard7c463582008-11-04 02:03:27 -08002630 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002631 PIPE_VBLANK_INTERRUPT_STATUS);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002632 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00002633
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002634 return 0;
2635}
2636
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002637static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002638{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002639 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf796cf82011-04-07 13:58:17 -07002640 unsigned long irqflags;
Paulo Zanonib5184212013-07-12 20:00:08 -03002641 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
Daniel Vetter40da17c2013-10-21 18:04:36 +02002642 DE_PIPE_VBLANK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002643
2644 if (!i915_pipe_enabled(dev, pipe))
2645 return -EINVAL;
2646
2647 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Paulo Zanonib5184212013-07-12 20:00:08 -03002648 ironlake_enable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002649 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2650
2651 return 0;
2652}
2653
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002654static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2655{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002656 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002657 unsigned long irqflags;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002658
2659 if (!i915_pipe_enabled(dev, pipe))
2660 return -EINVAL;
2661
2662 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002663 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002664 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002665 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2666
2667 return 0;
2668}
2669
Ben Widawskyabd58f02013-11-02 21:07:09 -07002670static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2671{
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 unsigned long irqflags;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002674
2675 if (!i915_pipe_enabled(dev, pipe))
2676 return -EINVAL;
2677
2678 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Daniel Vetter7167d7c2013-11-07 11:05:45 +01002679 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2680 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2681 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
Ben Widawskyabd58f02013-11-02 21:07:09 -07002682 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2683 return 0;
2684}
2685
Keith Packard42f52ef2008-10-18 19:39:29 -07002686/* Called from drm generic code, passed 'crtc' which
2687 * we use as a pipe index
2688 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002689static void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002690{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002691 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002692 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002693
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002694 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002695 i915_disable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002696 PIPE_VBLANK_INTERRUPT_STATUS |
2697 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002698 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2699}
2700
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002701static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002702{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002703 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf796cf82011-04-07 13:58:17 -07002704 unsigned long irqflags;
Paulo Zanonib5184212013-07-12 20:00:08 -03002705 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
Daniel Vetter40da17c2013-10-21 18:04:36 +02002706 DE_PIPE_VBLANK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002707
2708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Paulo Zanonib5184212013-07-12 20:00:08 -03002709 ironlake_disable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002710 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2711}
2712
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002713static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2714{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002715 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002716 unsigned long irqflags;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002717
2718 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002719 i915_disable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002720 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002721 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2722}
2723
Ben Widawskyabd58f02013-11-02 21:07:09 -07002724static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2725{
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 unsigned long irqflags;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002728
2729 if (!i915_pipe_enabled(dev, pipe))
2730 return;
2731
2732 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Daniel Vetter7167d7c2013-11-07 11:05:45 +01002733 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2734 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2735 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
Ben Widawskyabd58f02013-11-02 21:07:09 -07002736 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2737}
2738
Chris Wilson893eead2010-10-27 14:44:35 +01002739static u32
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002740ring_last_seqno(struct intel_engine_cs *ring)
Zou Nan hai852835f2010-05-21 09:08:56 +08002741{
Chris Wilson893eead2010-10-27 14:44:35 +01002742 return list_entry(ring->request_list.prev,
2743 struct drm_i915_gem_request, list)->seqno;
2744}
2745
Chris Wilson9107e9d2013-06-10 11:20:20 +01002746static bool
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002747ring_idle(struct intel_engine_cs *ring, u32 seqno)
Chris Wilson893eead2010-10-27 14:44:35 +01002748{
Chris Wilson9107e9d2013-06-10 11:20:20 +01002749 return (list_empty(&ring->request_list) ||
2750 i915_seqno_passed(seqno, ring_last_seqno(ring)));
Ben Gamarif65d9422009-09-14 17:48:44 -04002751}
2752
Daniel Vettera028c4b2014-03-15 00:08:56 +01002753static bool
2754ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2755{
2756 if (INTEL_INFO(dev)->gen >= 8) {
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002757 return (ipehr >> 23) == 0x1c;
Daniel Vettera028c4b2014-03-15 00:08:56 +01002758 } else {
2759 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2760 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2761 MI_SEMAPHORE_REGISTER);
2762 }
2763}
2764
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002765static struct intel_engine_cs *
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002766semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
Daniel Vetter921d42e2014-03-18 10:26:04 +01002767{
2768 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002769 struct intel_engine_cs *signaller;
Daniel Vetter921d42e2014-03-18 10:26:04 +01002770 int i;
2771
2772 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002773 for_each_ring(signaller, dev_priv, i) {
2774 if (ring == signaller)
2775 continue;
2776
2777 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2778 return signaller;
2779 }
Daniel Vetter921d42e2014-03-18 10:26:04 +01002780 } else {
2781 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2782
2783 for_each_ring(signaller, dev_priv, i) {
2784 if(ring == signaller)
2785 continue;
2786
Ben Widawskyebc348b2014-04-29 14:52:28 -07002787 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
Daniel Vetter921d42e2014-03-18 10:26:04 +01002788 return signaller;
2789 }
2790 }
2791
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002792 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2793 ring->id, ipehr, offset);
Daniel Vetter921d42e2014-03-18 10:26:04 +01002794
2795 return NULL;
2796}
2797
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002798static struct intel_engine_cs *
2799semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
Chris Wilsona24a11e2013-03-14 17:52:05 +02002800{
2801 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002802 u32 cmd, ipehr, head;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002803 u64 offset = 0;
2804 int i, backwards;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002805
2806 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
Daniel Vettera028c4b2014-03-15 00:08:56 +01002807 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
Chris Wilson6274f212013-06-10 11:20:21 +01002808 return NULL;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002809
Daniel Vetter88fe4292014-03-15 00:08:55 +01002810 /*
2811 * HEAD is likely pointing to the dword after the actual command,
2812 * so scan backwards until we find the MBOX. But limit it to just 3
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002813 * or 4 dwords depending on the semaphore wait command size.
2814 * Note that we don't care about ACTHD here since that might
Daniel Vetter88fe4292014-03-15 00:08:55 +01002815 * point at at batch, and semaphores are always emitted into the
2816 * ringbuffer itself.
Chris Wilsona24a11e2013-03-14 17:52:05 +02002817 */
Daniel Vetter88fe4292014-03-15 00:08:55 +01002818 head = I915_READ_HEAD(ring) & HEAD_ADDR;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002819 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002820
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002821 for (i = backwards; i; --i) {
Daniel Vetter88fe4292014-03-15 00:08:55 +01002822 /*
2823 * Be paranoid and presume the hw has gone off into the wild -
2824 * our ring is smaller than what the hardware (and hence
2825 * HEAD_ADDR) allows. Also handles wrap-around.
2826 */
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002827 head &= ring->buffer->size - 1;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002828
2829 /* This here seems to blow up */
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002830 cmd = ioread32(ring->buffer->virtual_start + head);
Chris Wilsona24a11e2013-03-14 17:52:05 +02002831 if (cmd == ipehr)
2832 break;
2833
Daniel Vetter88fe4292014-03-15 00:08:55 +01002834 head -= 4;
2835 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02002836
Daniel Vetter88fe4292014-03-15 00:08:55 +01002837 if (!i)
2838 return NULL;
2839
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002840 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002841 if (INTEL_INFO(ring->dev)->gen >= 8) {
2842 offset = ioread32(ring->buffer->virtual_start + head + 12);
2843 offset <<= 32;
2844 offset = ioread32(ring->buffer->virtual_start + head + 8);
2845 }
2846 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
Chris Wilsona24a11e2013-03-14 17:52:05 +02002847}
2848
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002849static int semaphore_passed(struct intel_engine_cs *ring)
Chris Wilson6274f212013-06-10 11:20:21 +01002850{
2851 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002852 struct intel_engine_cs *signaller;
Chris Wilsona0d036b2014-07-19 12:40:42 +01002853 u32 seqno;
Chris Wilson6274f212013-06-10 11:20:21 +01002854
Chris Wilson4be17382014-06-06 10:22:29 +01002855 ring->hangcheck.deadlock++;
Chris Wilson6274f212013-06-10 11:20:21 +01002856
2857 signaller = semaphore_waits_for(ring, &seqno);
Chris Wilson4be17382014-06-06 10:22:29 +01002858 if (signaller == NULL)
2859 return -1;
2860
2861 /* Prevent pathological recursion due to driver bugs */
2862 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
Chris Wilson6274f212013-06-10 11:20:21 +01002863 return -1;
2864
Chris Wilson4be17382014-06-06 10:22:29 +01002865 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2866 return 1;
2867
Chris Wilsona0d036b2014-07-19 12:40:42 +01002868 /* cursory check for an unkickable deadlock */
2869 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2870 semaphore_passed(signaller) < 0)
Chris Wilson4be17382014-06-06 10:22:29 +01002871 return -1;
2872
2873 return 0;
Chris Wilson6274f212013-06-10 11:20:21 +01002874}
2875
2876static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2877{
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002878 struct intel_engine_cs *ring;
Chris Wilson6274f212013-06-10 11:20:21 +01002879 int i;
2880
2881 for_each_ring(ring, dev_priv, i)
Chris Wilson4be17382014-06-06 10:22:29 +01002882 ring->hangcheck.deadlock = 0;
Chris Wilson6274f212013-06-10 11:20:21 +01002883}
2884
Mika Kuoppalaad8beae2013-06-12 12:35:32 +03002885static enum intel_ring_hangcheck_action
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002886ring_stuck(struct intel_engine_cs *ring, u64 acthd)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002887{
2888 struct drm_device *dev = ring->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002890 u32 tmp;
2891
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03002892 if (acthd != ring->hangcheck.acthd) {
2893 if (acthd > ring->hangcheck.max_acthd) {
2894 ring->hangcheck.max_acthd = acthd;
2895 return HANGCHECK_ACTIVE;
2896 }
2897
2898 return HANGCHECK_ACTIVE_LOOP;
2899 }
Chris Wilson6274f212013-06-10 11:20:21 +01002900
Chris Wilson9107e9d2013-06-10 11:20:20 +01002901 if (IS_GEN2(dev))
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002902 return HANGCHECK_HUNG;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002903
2904 /* Is the chip hanging on a WAIT_FOR_EVENT?
2905 * If so we can simply poke the RB_WAIT bit
2906 * and break the hang. This should work on
2907 * all but the second generation chipsets.
2908 */
2909 tmp = I915_READ_CTL(ring);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002910 if (tmp & RING_WAIT) {
Mika Kuoppala58174462014-02-25 17:11:26 +02002911 i915_handle_error(dev, false,
2912 "Kicking stuck wait on %s",
2913 ring->name);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002914 I915_WRITE_CTL(ring, tmp);
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002915 return HANGCHECK_KICK;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002916 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02002917
Chris Wilson6274f212013-06-10 11:20:21 +01002918 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2919 switch (semaphore_passed(ring)) {
2920 default:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002921 return HANGCHECK_HUNG;
Chris Wilson6274f212013-06-10 11:20:21 +01002922 case 1:
Mika Kuoppala58174462014-02-25 17:11:26 +02002923 i915_handle_error(dev, false,
2924 "Kicking stuck semaphore on %s",
2925 ring->name);
Chris Wilson6274f212013-06-10 11:20:21 +01002926 I915_WRITE_CTL(ring, tmp);
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002927 return HANGCHECK_KICK;
Chris Wilson6274f212013-06-10 11:20:21 +01002928 case 0:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002929 return HANGCHECK_WAIT;
Chris Wilson6274f212013-06-10 11:20:21 +01002930 }
Chris Wilson9107e9d2013-06-10 11:20:20 +01002931 }
Mika Kuoppalaed5cbb02013-05-13 16:32:11 +03002932
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002933 return HANGCHECK_HUNG;
Mika Kuoppalaed5cbb02013-05-13 16:32:11 +03002934}
2935
Ben Gamarif65d9422009-09-14 17:48:44 -04002936/**
2937 * This is called when the chip hasn't reported back with completed
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002938 * batchbuffers in a long time. We keep track per ring seqno progress and
2939 * if there are no progress, hangcheck score for that ring is increased.
2940 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2941 * we kick the ring. If we see no progress on three subsequent calls
2942 * we assume chip is wedged and try to fix it by resetting the chip.
Ben Gamarif65d9422009-09-14 17:48:44 -04002943 */
Damien Lespiaua658b5d2013-08-08 22:28:56 +01002944static void i915_hangcheck_elapsed(unsigned long data)
Ben Gamarif65d9422009-09-14 17:48:44 -04002945{
2946 struct drm_device *dev = (struct drm_device *)data;
Jani Nikula2d1013d2014-03-31 14:27:17 +03002947 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002948 struct intel_engine_cs *ring;
Chris Wilsonb4519512012-05-11 14:29:30 +01002949 int i;
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002950 int busy_count = 0, rings_hung = 0;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002951 bool stuck[I915_NUM_RINGS] = { 0 };
2952#define BUSY 1
2953#define KICK 5
2954#define HUNG 20
Chris Wilson893eead2010-10-27 14:44:35 +01002955
Jani Nikulad330a952014-01-21 11:24:25 +02002956 if (!i915.enable_hangcheck)
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -07002957 return;
2958
Chris Wilsonb4519512012-05-11 14:29:30 +01002959 for_each_ring(ring, dev_priv, i) {
Chris Wilson50877442014-03-21 12:41:53 +00002960 u64 acthd;
2961 u32 seqno;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002962 bool busy = true;
Chris Wilsonb4519512012-05-11 14:29:30 +01002963
Chris Wilson6274f212013-06-10 11:20:21 +01002964 semaphore_clear_deadlocks(dev_priv);
2965
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002966 seqno = ring->get_seqno(ring, false);
2967 acthd = intel_ring_get_active_head(ring);
Chris Wilsond1e61e72012-04-10 17:00:41 +01002968
Chris Wilson9107e9d2013-06-10 11:20:20 +01002969 if (ring->hangcheck.seqno == seqno) {
2970 if (ring_idle(ring, seqno)) {
Mika Kuoppalada661462013-09-06 16:03:28 +03002971 ring->hangcheck.action = HANGCHECK_IDLE;
2972
Chris Wilson9107e9d2013-06-10 11:20:20 +01002973 if (waitqueue_active(&ring->irq_queue)) {
2974 /* Issue a wake-up to catch stuck h/w. */
Chris Wilson094f9a52013-09-25 17:34:55 +01002975 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
Daniel Vetterf4adcd22013-10-28 09:24:13 +01002976 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2977 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2978 ring->name);
2979 else
2980 DRM_INFO("Fake missed irq on %s\n",
2981 ring->name);
Chris Wilson094f9a52013-09-25 17:34:55 +01002982 wake_up_all(&ring->irq_queue);
2983 }
2984 /* Safeguard against driver failure */
2985 ring->hangcheck.score += BUSY;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002986 } else
2987 busy = false;
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002988 } else {
Chris Wilson6274f212013-06-10 11:20:21 +01002989 /* We always increment the hangcheck score
2990 * if the ring is busy and still processing
2991 * the same request, so that no single request
2992 * can run indefinitely (such as a chain of
2993 * batches). The only time we do not increment
2994 * the hangcheck score on this ring, if this
2995 * ring is in a legitimate wait for another
2996 * ring. In that case the waiting ring is a
2997 * victim and we want to be sure we catch the
2998 * right culprit. Then every time we do kick
2999 * the ring, add a small increment to the
3000 * score so that we can catch a batch that is
3001 * being repeatedly kicked and so responsible
3002 * for stalling the machine.
3003 */
Mika Kuoppalaad8beae2013-06-12 12:35:32 +03003004 ring->hangcheck.action = ring_stuck(ring,
3005 acthd);
3006
3007 switch (ring->hangcheck.action) {
Mika Kuoppalada661462013-09-06 16:03:28 +03003008 case HANGCHECK_IDLE:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03003009 case HANGCHECK_WAIT:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03003010 case HANGCHECK_ACTIVE:
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03003011 break;
3012 case HANGCHECK_ACTIVE_LOOP:
Jani Nikulaea04cb32013-08-11 12:44:02 +03003013 ring->hangcheck.score += BUSY;
Chris Wilson6274f212013-06-10 11:20:21 +01003014 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03003015 case HANGCHECK_KICK:
Jani Nikulaea04cb32013-08-11 12:44:02 +03003016 ring->hangcheck.score += KICK;
Chris Wilson6274f212013-06-10 11:20:21 +01003017 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03003018 case HANGCHECK_HUNG:
Jani Nikulaea04cb32013-08-11 12:44:02 +03003019 ring->hangcheck.score += HUNG;
Chris Wilson6274f212013-06-10 11:20:21 +01003020 stuck[i] = true;
3021 break;
3022 }
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003023 }
Chris Wilson9107e9d2013-06-10 11:20:20 +01003024 } else {
Mika Kuoppalada661462013-09-06 16:03:28 +03003025 ring->hangcheck.action = HANGCHECK_ACTIVE;
3026
Chris Wilson9107e9d2013-06-10 11:20:20 +01003027 /* Gradually reduce the count so that we catch DoS
3028 * attempts across multiple batches.
3029 */
3030 if (ring->hangcheck.score > 0)
3031 ring->hangcheck.score--;
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03003032
3033 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
Chris Wilsond1e61e72012-04-10 17:00:41 +01003034 }
3035
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003036 ring->hangcheck.seqno = seqno;
3037 ring->hangcheck.acthd = acthd;
Chris Wilson9107e9d2013-06-10 11:20:20 +01003038 busy_count += busy;
Chris Wilson893eead2010-10-27 14:44:35 +01003039 }
Eric Anholtb9201c12010-01-08 14:25:16 -08003040
Mika Kuoppala92cab732013-05-24 17:16:07 +03003041 for_each_ring(ring, dev_priv, i) {
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02003042 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
Daniel Vetterb8d88d12013-08-28 10:57:59 +02003043 DRM_INFO("%s on %s\n",
3044 stuck[i] ? "stuck" : "no progress",
3045 ring->name);
Chris Wilsona43adf02013-06-10 11:20:22 +01003046 rings_hung++;
Mika Kuoppala92cab732013-05-24 17:16:07 +03003047 }
3048 }
3049
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003050 if (rings_hung)
Mika Kuoppala58174462014-02-25 17:11:26 +02003051 return i915_handle_error(dev, true, "Ring hung");
Ben Gamarif65d9422009-09-14 17:48:44 -04003052
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003053 if (busy_count)
3054 /* Reset timer case chip hangs without another request
3055 * being added */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03003056 i915_queue_hangcheck(dev);
3057}
3058
3059void i915_queue_hangcheck(struct drm_device *dev)
3060{
3061 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikulad330a952014-01-21 11:24:25 +02003062 if (!i915.enable_hangcheck)
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03003063 return;
3064
3065 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3066 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
Ben Gamarif65d9422009-09-14 17:48:44 -04003067}
3068
Paulo Zanoni1c69eb42014-04-01 15:37:23 -03003069static void ibx_irq_reset(struct drm_device *dev)
Paulo Zanoni91738a92013-06-05 14:21:51 -03003070{
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072
3073 if (HAS_PCH_NOP(dev))
3074 return;
3075
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003076 GEN5_IRQ_RESET(SDE);
Paulo Zanoni105b1222014-04-01 15:37:17 -03003077
3078 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3079 I915_WRITE(SERR_INT, 0xffffffff);
Paulo Zanoni622364b2014-04-01 15:37:22 -03003080}
Paulo Zanoni105b1222014-04-01 15:37:17 -03003081
Paulo Zanoni622364b2014-04-01 15:37:22 -03003082/*
3083 * SDEIER is also touched by the interrupt handler to work around missed PCH
3084 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3085 * instead we unconditionally enable all PCH interrupt sources here, but then
3086 * only unmask them as needed with SDEIMR.
3087 *
3088 * This function needs to be called before interrupts are enabled.
3089 */
3090static void ibx_irq_pre_postinstall(struct drm_device *dev)
3091{
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093
3094 if (HAS_PCH_NOP(dev))
3095 return;
3096
3097 WARN_ON(I915_READ(SDEIER) != 0);
Paulo Zanoni91738a92013-06-05 14:21:51 -03003098 I915_WRITE(SDEIER, 0xffffffff);
3099 POSTING_READ(SDEIER);
3100}
3101
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003102static void gen5_gt_irq_reset(struct drm_device *dev)
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02003103{
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3105
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003106 GEN5_IRQ_RESET(GT);
Paulo Zanonia9d356a2014-04-01 15:37:09 -03003107 if (INTEL_INFO(dev)->gen >= 6)
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003108 GEN5_IRQ_RESET(GEN6_PM);
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02003109}
3110
Linus Torvalds1da177e2005-04-16 15:20:36 -07003111/* drm_dma.h hooks
3112*/
Paulo Zanonibe30b292014-04-01 15:37:25 -03003113static void ironlake_irq_reset(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003114{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003115 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003116
Paulo Zanoni0c841212014-04-01 15:37:27 -03003117 I915_WRITE(HWSTAM, 0xffffffff);
Daniel Vetterbdfcdb62012-01-05 01:05:26 +01003118
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003119 GEN5_IRQ_RESET(DE);
Paulo Zanonic6d954c2014-04-01 15:37:18 -03003120 if (IS_GEN7(dev))
3121 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003122
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003123 gen5_gt_irq_reset(dev);
Zhenyu Wangc6501562009-11-03 18:57:21 +00003124
Paulo Zanoni1c69eb42014-04-01 15:37:23 -03003125 ibx_irq_reset(dev);
Ben Widawsky7d991632013-05-28 19:22:25 -07003126}
3127
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003128static void valleyview_irq_preinstall(struct drm_device *dev)
3129{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003130 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003131 int pipe;
3132
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003133 /* VLV magic */
3134 I915_WRITE(VLV_IMR, 0);
3135 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3136 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3137 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3138
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003139 /* and GT */
3140 I915_WRITE(GTIIR, I915_READ(GTIIR));
3141 I915_WRITE(GTIIR, I915_READ(GTIIR));
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02003142
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003143 gen5_gt_irq_reset(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003144
3145 I915_WRITE(DPINVGTT, 0xff);
3146
3147 I915_WRITE(PORT_HOTPLUG_EN, 0);
3148 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Damien Lespiau055e3932014-08-18 13:49:10 +01003149 for_each_pipe(dev_priv, pipe)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003150 I915_WRITE(PIPESTAT(pipe), 0xffff);
3151 I915_WRITE(VLV_IIR, 0xffffffff);
3152 I915_WRITE(VLV_IMR, 0xffffffff);
3153 I915_WRITE(VLV_IER, 0x0);
3154 POSTING_READ(VLV_IER);
3155}
3156
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003157static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3158{
3159 GEN8_IRQ_RESET_NDX(GT, 0);
3160 GEN8_IRQ_RESET_NDX(GT, 1);
3161 GEN8_IRQ_RESET_NDX(GT, 2);
3162 GEN8_IRQ_RESET_NDX(GT, 3);
3163}
3164
Paulo Zanoni823f6b32014-04-01 15:37:26 -03003165static void gen8_irq_reset(struct drm_device *dev)
Ben Widawskyabd58f02013-11-02 21:07:09 -07003166{
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 int pipe;
3169
Ben Widawskyabd58f02013-11-02 21:07:09 -07003170 I915_WRITE(GEN8_MASTER_IRQ, 0);
3171 POSTING_READ(GEN8_MASTER_IRQ);
3172
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003173 gen8_gt_irq_reset(dev_priv);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003174
Damien Lespiau055e3932014-08-18 13:49:10 +01003175 for_each_pipe(dev_priv, pipe)
Daniel Vetterf458ebb2014-09-30 10:56:39 +02003176 if (intel_display_power_is_enabled(dev_priv,
3177 POWER_DOMAIN_PIPE(pipe)))
Paulo Zanoni813bde42014-07-04 11:50:29 -03003178 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003179
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003180 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3181 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3182 GEN5_IRQ_RESET(GEN8_PCU_);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003183
Paulo Zanoni1c69eb42014-04-01 15:37:23 -03003184 ibx_irq_reset(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003185}
Ben Widawskyabd58f02013-11-02 21:07:09 -07003186
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003187void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3188{
Paulo Zanoni1180e202014-10-07 18:02:52 -03003189 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003190
Daniel Vetter13321782014-09-15 14:55:29 +02003191 spin_lock_irq(&dev_priv->irq_lock);
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003192 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
Paulo Zanoni1180e202014-10-07 18:02:52 -03003193 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003194 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
Paulo Zanoni1180e202014-10-07 18:02:52 -03003195 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
Daniel Vetter13321782014-09-15 14:55:29 +02003196 spin_unlock_irq(&dev_priv->irq_lock);
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003197}
3198
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003199static void cherryview_irq_preinstall(struct drm_device *dev)
3200{
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 int pipe;
3203
3204 I915_WRITE(GEN8_MASTER_IRQ, 0);
3205 POSTING_READ(GEN8_MASTER_IRQ);
3206
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003207 gen8_gt_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003208
3209 GEN5_IRQ_RESET(GEN8_PCU_);
3210
3211 POSTING_READ(GEN8_PCU_IIR);
3212
3213 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3214
3215 I915_WRITE(PORT_HOTPLUG_EN, 0);
3216 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3217
Damien Lespiau055e3932014-08-18 13:49:10 +01003218 for_each_pipe(dev_priv, pipe)
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003219 I915_WRITE(PIPESTAT(pipe), 0xffff);
3220
3221 I915_WRITE(VLV_IMR, 0xffffffff);
3222 I915_WRITE(VLV_IER, 0x0);
3223 I915_WRITE(VLV_IIR, 0xffffffff);
3224 POSTING_READ(VLV_IIR);
3225}
3226
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003227static void ibx_hpd_irq_setup(struct drm_device *dev)
Keith Packard7fe0b972011-09-19 13:31:02 -07003228{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003229 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003230 struct intel_encoder *intel_encoder;
Daniel Vetterfee884e2013-07-04 23:35:21 +02003231 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
Keith Packard7fe0b972011-09-19 13:31:02 -07003232
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003233 if (HAS_PCH_IBX(dev)) {
Daniel Vetterfee884e2013-07-04 23:35:21 +02003234 hotplug_irqs = SDE_HOTPLUG_MASK;
Damien Lespiaub2784e12014-08-05 11:29:37 +01003235 for_each_intel_encoder(dev, intel_encoder)
Egbert Eichcd569ae2013-04-16 13:36:57 +02003236 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
Daniel Vetterfee884e2013-07-04 23:35:21 +02003237 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003238 } else {
Daniel Vetterfee884e2013-07-04 23:35:21 +02003239 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
Damien Lespiaub2784e12014-08-05 11:29:37 +01003240 for_each_intel_encoder(dev, intel_encoder)
Egbert Eichcd569ae2013-04-16 13:36:57 +02003241 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
Daniel Vetterfee884e2013-07-04 23:35:21 +02003242 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003243 }
3244
Daniel Vetterfee884e2013-07-04 23:35:21 +02003245 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003246
3247 /*
3248 * Enable digital hotplug on the PCH, and configure the DP short pulse
3249 * duration to 2ms (which is the minimum in the Display Port spec)
3250 *
3251 * This register is the same on all known PCH chips.
3252 */
Keith Packard7fe0b972011-09-19 13:31:02 -07003253 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3254 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3255 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3256 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3257 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3258 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3259}
3260
Paulo Zanonid46da432013-02-08 17:35:15 -02003261static void ibx_irq_postinstall(struct drm_device *dev)
3262{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003263 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003264 u32 mask;
Paulo Zanonid46da432013-02-08 17:35:15 -02003265
Daniel Vetter692a04c2013-05-29 21:43:05 +02003266 if (HAS_PCH_NOP(dev))
3267 return;
3268
Paulo Zanoni105b1222014-04-01 15:37:17 -03003269 if (HAS_PCH_IBX(dev))
Daniel Vetter5c673b62014-03-07 20:34:46 +01003270 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
Paulo Zanoni105b1222014-04-01 15:37:17 -03003271 else
Daniel Vetter5c673b62014-03-07 20:34:46 +01003272 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
Paulo Zanoni86642812013-04-12 17:57:57 -03003273
Paulo Zanoni337ba012014-04-01 15:37:16 -03003274 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
Paulo Zanonid46da432013-02-08 17:35:15 -02003275 I915_WRITE(SDEIMR, ~mask);
Paulo Zanonid46da432013-02-08 17:35:15 -02003276}
3277
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003278static void gen5_gt_irq_postinstall(struct drm_device *dev)
3279{
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 u32 pm_irqs, gt_irqs;
3282
3283 pm_irqs = gt_irqs = 0;
3284
3285 dev_priv->gt_irq_mask = ~0;
Ben Widawsky040d2ba2013-09-19 11:01:40 -07003286 if (HAS_L3_DPF(dev)) {
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003287 /* L3 parity interrupt is always unmasked. */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07003288 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3289 gt_irqs |= GT_PARITY_ERROR(dev);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003290 }
3291
3292 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3293 if (IS_GEN5(dev)) {
3294 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3295 ILK_BSD_USER_INTERRUPT;
3296 } else {
3297 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3298 }
3299
Paulo Zanoni35079892014-04-01 15:37:15 -03003300 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003301
3302 if (INTEL_INFO(dev)->gen >= 6) {
Deepak Sa6706b42014-03-15 20:23:22 +05303303 pm_irqs |= dev_priv->pm_rps_events;
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003304
3305 if (HAS_VEBOX(dev))
3306 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3307
Paulo Zanoni605cd252013-08-06 18:57:15 -03003308 dev_priv->pm_irq_mask = 0xffffffff;
Paulo Zanoni35079892014-04-01 15:37:15 -03003309 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003310 }
3311}
3312
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003313static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003314{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003315 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003316 u32 display_mask, extra_mask;
3317
3318 if (INTEL_INFO(dev)->gen >= 7) {
3319 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3320 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3321 DE_PLANEB_FLIP_DONE_IVB |
Daniel Vetter5c673b62014-03-07 20:34:46 +01003322 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003323 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
Daniel Vetter5c673b62014-03-07 20:34:46 +01003324 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003325 } else {
3326 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3327 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003328 DE_AUX_CHANNEL_A |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003329 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3330 DE_POISON);
Daniel Vetter5c673b62014-03-07 20:34:46 +01003331 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3332 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003333 }
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003334
Chris Wilson1ec14ad2010-12-04 11:30:53 +00003335 dev_priv->irq_mask = ~display_mask;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003336
Paulo Zanoni0c841212014-04-01 15:37:27 -03003337 I915_WRITE(HWSTAM, 0xeffe);
3338
Paulo Zanoni622364b2014-04-01 15:37:22 -03003339 ibx_irq_pre_postinstall(dev);
3340
Paulo Zanoni35079892014-04-01 15:37:15 -03003341 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003342
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003343 gen5_gt_irq_postinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003344
Paulo Zanonid46da432013-02-08 17:35:15 -02003345 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07003346
Jesse Barnesf97108d2010-01-29 11:27:07 -08003347 if (IS_IRONLAKE_M(dev)) {
Daniel Vetter6005ce42013-06-27 13:44:59 +02003348 /* Enable PCU event interrupts
3349 *
3350 * spinlocking not required here for correctness since interrupt
Daniel Vetter4bc9d432013-06-27 13:44:58 +02003351 * setup is guaranteed to run in single-threaded context. But we
3352 * need it to make the assert_spin_locked happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003353 spin_lock_irq(&dev_priv->irq_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -08003354 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
Daniel Vetterd6207432014-09-15 14:55:27 +02003355 spin_unlock_irq(&dev_priv->irq_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -08003356 }
3357
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003358 return 0;
3359}
3360
Imre Deakf8b79e52014-03-04 19:23:07 +02003361static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3362{
3363 u32 pipestat_mask;
3364 u32 iir_mask;
3365
3366 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3367 PIPE_FIFO_UNDERRUN_STATUS;
3368
3369 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3370 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3371 POSTING_READ(PIPESTAT(PIPE_A));
3372
3373 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3374 PIPE_CRC_DONE_INTERRUPT_STATUS;
3375
3376 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3377 PIPE_GMBUS_INTERRUPT_STATUS);
3378 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3379
3380 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3381 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3382 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3383 dev_priv->irq_mask &= ~iir_mask;
3384
3385 I915_WRITE(VLV_IIR, iir_mask);
3386 I915_WRITE(VLV_IIR, iir_mask);
3387 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3388 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3389 POSTING_READ(VLV_IER);
3390}
3391
3392static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3393{
3394 u32 pipestat_mask;
3395 u32 iir_mask;
3396
3397 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3398 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
Imre Deak6c7fba02014-03-10 19:44:48 +02003399 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
Imre Deakf8b79e52014-03-04 19:23:07 +02003400
3401 dev_priv->irq_mask |= iir_mask;
3402 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3403 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3404 I915_WRITE(VLV_IIR, iir_mask);
3405 I915_WRITE(VLV_IIR, iir_mask);
3406 POSTING_READ(VLV_IIR);
3407
3408 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3409 PIPE_CRC_DONE_INTERRUPT_STATUS;
3410
3411 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3412 PIPE_GMBUS_INTERRUPT_STATUS);
3413 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3414
3415 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3416 PIPE_FIFO_UNDERRUN_STATUS;
3417 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3418 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3419 POSTING_READ(PIPESTAT(PIPE_A));
3420}
3421
3422void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3423{
3424 assert_spin_locked(&dev_priv->irq_lock);
3425
3426 if (dev_priv->display_irqs_enabled)
3427 return;
3428
3429 dev_priv->display_irqs_enabled = true;
3430
Imre Deak950eaba2014-09-08 15:21:09 +03003431 if (intel_irqs_enabled(dev_priv))
Imre Deakf8b79e52014-03-04 19:23:07 +02003432 valleyview_display_irqs_install(dev_priv);
3433}
3434
3435void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3436{
3437 assert_spin_locked(&dev_priv->irq_lock);
3438
3439 if (!dev_priv->display_irqs_enabled)
3440 return;
3441
3442 dev_priv->display_irqs_enabled = false;
3443
Imre Deak950eaba2014-09-08 15:21:09 +03003444 if (intel_irqs_enabled(dev_priv))
Imre Deakf8b79e52014-03-04 19:23:07 +02003445 valleyview_display_irqs_uninstall(dev_priv);
3446}
3447
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003448static int valleyview_irq_postinstall(struct drm_device *dev)
3449{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003450 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003451
Imre Deakf8b79e52014-03-04 19:23:07 +02003452 dev_priv->irq_mask = ~0;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003453
Daniel Vetter20afbda2012-12-11 14:05:07 +01003454 I915_WRITE(PORT_HOTPLUG_EN, 0);
3455 POSTING_READ(PORT_HOTPLUG_EN);
3456
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003457 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003458 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003459 I915_WRITE(VLV_IIR, 0xffffffff);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003460 POSTING_READ(VLV_IER);
3461
Daniel Vetterb79480b2013-06-27 17:52:10 +02003462 /* Interrupt setup is already guaranteed to be single-threaded, this is
3463 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003464 spin_lock_irq(&dev_priv->irq_lock);
Imre Deakf8b79e52014-03-04 19:23:07 +02003465 if (dev_priv->display_irqs_enabled)
3466 valleyview_display_irqs_install(dev_priv);
Daniel Vetterd6207432014-09-15 14:55:27 +02003467 spin_unlock_irq(&dev_priv->irq_lock);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07003468
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003469 I915_WRITE(VLV_IIR, 0xffffffff);
3470 I915_WRITE(VLV_IIR, 0xffffffff);
3471
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003472 gen5_gt_irq_postinstall(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003473
3474 /* ack & enable invalid PTE error interrupts */
3475#if 0 /* FIXME: add support to irq handler for checking these bits */
3476 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3477 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3478#endif
3479
3480 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003481
3482 return 0;
3483}
3484
Ben Widawskyabd58f02013-11-02 21:07:09 -07003485static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3486{
Ben Widawskyabd58f02013-11-02 21:07:09 -07003487 /* These are interrupts we'll toggle with the ring mask register */
3488 uint32_t gt_interrupts[] = {
3489 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003490 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
Ben Widawskyabd58f02013-11-02 21:07:09 -07003491 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003492 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3493 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
Ben Widawskyabd58f02013-11-02 21:07:09 -07003494 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003495 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3496 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3497 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
Ben Widawskyabd58f02013-11-02 21:07:09 -07003498 0,
Oscar Mateo73d477f2014-07-24 17:04:31 +01003499 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3500 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
Ben Widawskyabd58f02013-11-02 21:07:09 -07003501 };
3502
Ben Widawsky09610212014-05-15 20:58:08 +03003503 dev_priv->pm_irq_mask = 0xffffffff;
Deepak S9a2d2d82014-08-22 08:32:40 +05303504 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3505 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3506 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
3507 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003508}
3509
3510static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3511{
Damien Lespiau770de832014-03-20 20:45:01 +00003512 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3513 uint32_t de_pipe_enables;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003514 int pipe;
Damien Lespiau770de832014-03-20 20:45:01 +00003515
3516 if (IS_GEN9(dev_priv))
3517 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3518 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3519 else
3520 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3521 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3522
3523 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3524 GEN8_PIPE_FIFO_UNDERRUN;
3525
Daniel Vetter13b3a0a2013-11-07 15:31:52 +01003526 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3527 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3528 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003529
Damien Lespiau055e3932014-08-18 13:49:10 +01003530 for_each_pipe(dev_priv, pipe)
Daniel Vetterf458ebb2014-09-30 10:56:39 +02003531 if (intel_display_power_is_enabled(dev_priv,
Paulo Zanoni813bde42014-07-04 11:50:29 -03003532 POWER_DOMAIN_PIPE(pipe)))
3533 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3534 dev_priv->de_irq_mask[pipe],
3535 de_pipe_enables);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003536
Paulo Zanoni35079892014-04-01 15:37:15 -03003537 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003538}
3539
3540static int gen8_irq_postinstall(struct drm_device *dev)
3541{
3542 struct drm_i915_private *dev_priv = dev->dev_private;
3543
Paulo Zanoni622364b2014-04-01 15:37:22 -03003544 ibx_irq_pre_postinstall(dev);
3545
Ben Widawskyabd58f02013-11-02 21:07:09 -07003546 gen8_gt_irq_postinstall(dev_priv);
3547 gen8_de_irq_postinstall(dev_priv);
3548
3549 ibx_irq_postinstall(dev);
3550
3551 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3552 POSTING_READ(GEN8_MASTER_IRQ);
3553
3554 return 0;
3555}
3556
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003557static int cherryview_irq_postinstall(struct drm_device *dev)
3558{
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560 u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3561 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003562 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Ville Syrjälä3278f672014-04-09 13:28:49 +03003563 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3564 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3565 PIPE_CRC_DONE_INTERRUPT_STATUS;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003566 int pipe;
3567
3568 /*
3569 * Leave vblank interrupts masked initially. enable/disable will
3570 * toggle them based on usage.
3571 */
Ville Syrjälä3278f672014-04-09 13:28:49 +03003572 dev_priv->irq_mask = ~enable_mask;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003573
Damien Lespiau055e3932014-08-18 13:49:10 +01003574 for_each_pipe(dev_priv, pipe)
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003575 I915_WRITE(PIPESTAT(pipe), 0xffff);
3576
Daniel Vetterd6207432014-09-15 14:55:27 +02003577 spin_lock_irq(&dev_priv->irq_lock);
Ville Syrjälä3278f672014-04-09 13:28:49 +03003578 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
Damien Lespiau055e3932014-08-18 13:49:10 +01003579 for_each_pipe(dev_priv, pipe)
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003580 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
Daniel Vetterd6207432014-09-15 14:55:27 +02003581 spin_unlock_irq(&dev_priv->irq_lock);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003582
3583 I915_WRITE(VLV_IIR, 0xffffffff);
3584 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3585 I915_WRITE(VLV_IER, enable_mask);
3586
3587 gen8_gt_irq_postinstall(dev_priv);
3588
3589 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3590 POSTING_READ(GEN8_MASTER_IRQ);
3591
3592 return 0;
3593}
3594
Ben Widawskyabd58f02013-11-02 21:07:09 -07003595static void gen8_irq_uninstall(struct drm_device *dev)
3596{
3597 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003598
3599 if (!dev_priv)
3600 return;
3601
Paulo Zanoni823f6b32014-04-01 15:37:26 -03003602 gen8_irq_reset(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003603}
3604
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003605static void valleyview_irq_uninstall(struct drm_device *dev)
3606{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003607 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003608 int pipe;
3609
3610 if (!dev_priv)
3611 return;
3612
Imre Deak843d0e72014-04-14 20:24:23 +03003613 I915_WRITE(VLV_MASTER_IER, 0);
3614
Damien Lespiau055e3932014-08-18 13:49:10 +01003615 for_each_pipe(dev_priv, pipe)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003616 I915_WRITE(PIPESTAT(pipe), 0xffff);
3617
3618 I915_WRITE(HWSTAM, 0xffffffff);
3619 I915_WRITE(PORT_HOTPLUG_EN, 0);
3620 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Imre Deakf8b79e52014-03-04 19:23:07 +02003621
Daniel Vetterd6207432014-09-15 14:55:27 +02003622 /* Interrupt setup is already guaranteed to be single-threaded, this is
3623 * just to make the assert_spin_locked check happy. */
3624 spin_lock_irq(&dev_priv->irq_lock);
Imre Deakf8b79e52014-03-04 19:23:07 +02003625 if (dev_priv->display_irqs_enabled)
3626 valleyview_display_irqs_uninstall(dev_priv);
Daniel Vetterd6207432014-09-15 14:55:27 +02003627 spin_unlock_irq(&dev_priv->irq_lock);
Imre Deakf8b79e52014-03-04 19:23:07 +02003628
3629 dev_priv->irq_mask = 0;
3630
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003631 I915_WRITE(VLV_IIR, 0xffffffff);
3632 I915_WRITE(VLV_IMR, 0xffffffff);
3633 I915_WRITE(VLV_IER, 0x0);
3634 POSTING_READ(VLV_IER);
3635}
3636
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003637static void cherryview_irq_uninstall(struct drm_device *dev)
3638{
3639 struct drm_i915_private *dev_priv = dev->dev_private;
3640 int pipe;
3641
3642 if (!dev_priv)
3643 return;
3644
3645 I915_WRITE(GEN8_MASTER_IRQ, 0);
3646 POSTING_READ(GEN8_MASTER_IRQ);
3647
3648#define GEN8_IRQ_FINI_NDX(type, which) \
3649do { \
3650 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3651 I915_WRITE(GEN8_##type##_IER(which), 0); \
3652 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3653 POSTING_READ(GEN8_##type##_IIR(which)); \
3654 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3655} while (0)
3656
3657#define GEN8_IRQ_FINI(type) \
3658do { \
3659 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3660 I915_WRITE(GEN8_##type##_IER, 0); \
3661 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3662 POSTING_READ(GEN8_##type##_IIR); \
3663 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3664} while (0)
3665
3666 GEN8_IRQ_FINI_NDX(GT, 0);
3667 GEN8_IRQ_FINI_NDX(GT, 1);
3668 GEN8_IRQ_FINI_NDX(GT, 2);
3669 GEN8_IRQ_FINI_NDX(GT, 3);
3670
3671 GEN8_IRQ_FINI(PCU);
3672
3673#undef GEN8_IRQ_FINI
3674#undef GEN8_IRQ_FINI_NDX
3675
3676 I915_WRITE(PORT_HOTPLUG_EN, 0);
3677 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3678
Damien Lespiau055e3932014-08-18 13:49:10 +01003679 for_each_pipe(dev_priv, pipe)
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003680 I915_WRITE(PIPESTAT(pipe), 0xffff);
3681
3682 I915_WRITE(VLV_IMR, 0xffffffff);
3683 I915_WRITE(VLV_IER, 0x0);
3684 I915_WRITE(VLV_IIR, 0xffffffff);
3685 POSTING_READ(VLV_IIR);
3686}
3687
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003688static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003689{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003690 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes46979952011-04-07 13:53:55 -07003691
3692 if (!dev_priv)
3693 return;
3694
Paulo Zanonibe30b292014-04-01 15:37:25 -03003695 ironlake_irq_reset(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003696}
3697
Chris Wilsonc2798b12012-04-22 21:13:57 +01003698static void i8xx_irq_preinstall(struct drm_device * dev)
3699{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003700 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003701 int pipe;
3702
Damien Lespiau055e3932014-08-18 13:49:10 +01003703 for_each_pipe(dev_priv, pipe)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003704 I915_WRITE(PIPESTAT(pipe), 0);
3705 I915_WRITE16(IMR, 0xffff);
3706 I915_WRITE16(IER, 0x0);
3707 POSTING_READ16(IER);
3708}
3709
3710static int i8xx_irq_postinstall(struct drm_device *dev)
3711{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003712 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003713
Chris Wilsonc2798b12012-04-22 21:13:57 +01003714 I915_WRITE16(EMR,
3715 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3716
3717 /* Unmask the interrupts that we always want on. */
3718 dev_priv->irq_mask =
3719 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3720 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3721 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3722 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3723 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3724 I915_WRITE16(IMR, dev_priv->irq_mask);
3725
3726 I915_WRITE16(IER,
3727 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3728 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3729 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3730 I915_USER_INTERRUPT);
3731 POSTING_READ16(IER);
3732
Daniel Vetter379ef822013-10-16 22:55:56 +02003733 /* Interrupt setup is already guaranteed to be single-threaded, this is
3734 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003735 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003736 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3737 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003738 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter379ef822013-10-16 22:55:56 +02003739
Chris Wilsonc2798b12012-04-22 21:13:57 +01003740 return 0;
3741}
3742
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003743/*
3744 * Returns true when a page flip has completed.
3745 */
3746static bool i8xx_handle_vblank(struct drm_device *dev,
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003747 int plane, int pipe, u32 iir)
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003748{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003749 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003750 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003751
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03003752 if (!intel_pipe_handle_vblank(dev, pipe))
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003753 return false;
3754
3755 if ((iir & flip_pending) == 0)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003756 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003757
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003758 intel_prepare_page_flip(dev, plane);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003759
3760 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3761 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3762 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3763 * the flip is completed (no longer pending). Since this doesn't raise
3764 * an interrupt per se, we watch for the change at vblank.
3765 */
3766 if (I915_READ16(ISR) & flip_pending)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003767 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003768
3769 intel_finish_page_flip(dev, pipe);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003770 return true;
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003771
3772check_page_flip:
3773 intel_check_page_flip(dev, pipe);
3774 return false;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003775}
3776
Daniel Vetterff1f5252012-10-02 15:10:55 +02003777static irqreturn_t i8xx_irq_handler(int irq, void *arg)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003778{
Daniel Vetter45a83f82014-05-12 19:17:55 +02003779 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03003780 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003781 u16 iir, new_iir;
3782 u32 pipe_stats[2];
Chris Wilsonc2798b12012-04-22 21:13:57 +01003783 int pipe;
3784 u16 flip_mask =
3785 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3786 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3787
Chris Wilsonc2798b12012-04-22 21:13:57 +01003788 iir = I915_READ16(IIR);
3789 if (iir == 0)
3790 return IRQ_NONE;
3791
3792 while (iir & ~flip_mask) {
3793 /* Can't rely on pipestat interrupt bit in iir as it might
3794 * have been cleared after the pipestat interrupt was received.
3795 * It doesn't set the bit in iir again, but it still produces
3796 * interrupts (for non-MSI).
3797 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02003798 spin_lock(&dev_priv->irq_lock);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003799 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Mika Kuoppala58174462014-02-25 17:11:26 +02003800 i915_handle_error(dev, false,
3801 "Command parser error, iir 0x%08x",
3802 iir);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003803
Damien Lespiau055e3932014-08-18 13:49:10 +01003804 for_each_pipe(dev_priv, pipe) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003805 int reg = PIPESTAT(pipe);
3806 pipe_stats[pipe] = I915_READ(reg);
3807
3808 /*
3809 * Clear the PIPE*STAT regs before the IIR
3810 */
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003811 if (pipe_stats[pipe] & 0x8000ffff)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003812 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003813 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02003814 spin_unlock(&dev_priv->irq_lock);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003815
3816 I915_WRITE16(IIR, iir & ~flip_mask);
3817 new_iir = I915_READ16(IIR); /* Flush posted writes */
3818
Daniel Vetterd05c6172012-04-26 23:28:09 +02003819 i915_update_dri1_breadcrumb(dev);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003820
3821 if (iir & I915_USER_INTERRUPT)
3822 notify_ring(dev, &dev_priv->ring[RCS]);
3823
Damien Lespiau055e3932014-08-18 13:49:10 +01003824 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003825 int plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01003826 if (HAS_FBC(dev))
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003827 plane = !plane;
3828
Daniel Vetter4356d582013-10-16 22:55:55 +02003829 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003830 i8xx_handle_vblank(dev, plane, pipe, iir))
3831 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003832
Daniel Vetter4356d582013-10-16 22:55:55 +02003833 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02003834 i9xx_pipe_crc_irq_handler(dev, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003835
3836 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3837 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02003838 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
Daniel Vetter4356d582013-10-16 22:55:55 +02003839 }
Chris Wilsonc2798b12012-04-22 21:13:57 +01003840
3841 iir = new_iir;
3842 }
3843
3844 return IRQ_HANDLED;
3845}
3846
3847static void i8xx_irq_uninstall(struct drm_device * dev)
3848{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003849 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003850 int pipe;
3851
Damien Lespiau055e3932014-08-18 13:49:10 +01003852 for_each_pipe(dev_priv, pipe) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003853 /* Clear enable bits; then clear status bits */
3854 I915_WRITE(PIPESTAT(pipe), 0);
3855 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3856 }
3857 I915_WRITE16(IMR, 0xffff);
3858 I915_WRITE16(IER, 0x0);
3859 I915_WRITE16(IIR, I915_READ16(IIR));
3860}
3861
Chris Wilsona266c7d2012-04-24 22:59:44 +01003862static void i915_irq_preinstall(struct drm_device * dev)
3863{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003864 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003865 int pipe;
3866
Chris Wilsona266c7d2012-04-24 22:59:44 +01003867 if (I915_HAS_HOTPLUG(dev)) {
3868 I915_WRITE(PORT_HOTPLUG_EN, 0);
3869 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3870 }
3871
Chris Wilson00d98eb2012-04-24 22:59:48 +01003872 I915_WRITE16(HWSTAM, 0xeffe);
Damien Lespiau055e3932014-08-18 13:49:10 +01003873 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003874 I915_WRITE(PIPESTAT(pipe), 0);
3875 I915_WRITE(IMR, 0xffffffff);
3876 I915_WRITE(IER, 0x0);
3877 POSTING_READ(IER);
3878}
3879
3880static int i915_irq_postinstall(struct drm_device *dev)
3881{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003882 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson38bde182012-04-24 22:59:50 +01003883 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003884
Chris Wilson38bde182012-04-24 22:59:50 +01003885 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3886
3887 /* Unmask the interrupts that we always want on. */
3888 dev_priv->irq_mask =
3889 ~(I915_ASLE_INTERRUPT |
3890 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3891 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3892 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3893 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3894 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3895
3896 enable_mask =
3897 I915_ASLE_INTERRUPT |
3898 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3899 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3900 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3901 I915_USER_INTERRUPT;
3902
Chris Wilsona266c7d2012-04-24 22:59:44 +01003903 if (I915_HAS_HOTPLUG(dev)) {
Daniel Vetter20afbda2012-12-11 14:05:07 +01003904 I915_WRITE(PORT_HOTPLUG_EN, 0);
3905 POSTING_READ(PORT_HOTPLUG_EN);
3906
Chris Wilsona266c7d2012-04-24 22:59:44 +01003907 /* Enable in IER... */
3908 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3909 /* and unmask in IMR */
3910 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3911 }
3912
Chris Wilsona266c7d2012-04-24 22:59:44 +01003913 I915_WRITE(IMR, dev_priv->irq_mask);
3914 I915_WRITE(IER, enable_mask);
3915 POSTING_READ(IER);
3916
Jani Nikulaf49e38d2013-04-29 13:02:54 +03003917 i915_enable_asle_pipestat(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003918
Daniel Vetter379ef822013-10-16 22:55:56 +02003919 /* Interrupt setup is already guaranteed to be single-threaded, this is
3920 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003921 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003922 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3923 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003924 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter379ef822013-10-16 22:55:56 +02003925
Daniel Vetter20afbda2012-12-11 14:05:07 +01003926 return 0;
3927}
3928
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003929/*
3930 * Returns true when a page flip has completed.
3931 */
3932static bool i915_handle_vblank(struct drm_device *dev,
3933 int plane, int pipe, u32 iir)
3934{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003935 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003936 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3937
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03003938 if (!intel_pipe_handle_vblank(dev, pipe))
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003939 return false;
3940
3941 if ((iir & flip_pending) == 0)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003942 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003943
3944 intel_prepare_page_flip(dev, plane);
3945
3946 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3947 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3948 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3949 * the flip is completed (no longer pending). Since this doesn't raise
3950 * an interrupt per se, we watch for the change at vblank.
3951 */
3952 if (I915_READ(ISR) & flip_pending)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003953 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003954
3955 intel_finish_page_flip(dev, pipe);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003956 return true;
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003957
3958check_page_flip:
3959 intel_check_page_flip(dev, pipe);
3960 return false;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003961}
3962
Daniel Vetterff1f5252012-10-02 15:10:55 +02003963static irqreturn_t i915_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003964{
Daniel Vetter45a83f82014-05-12 19:17:55 +02003965 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03003966 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8291ee92012-04-24 22:59:47 +01003967 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
Chris Wilson38bde182012-04-24 22:59:50 +01003968 u32 flip_mask =
3969 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3970 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilson38bde182012-04-24 22:59:50 +01003971 int pipe, ret = IRQ_NONE;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003972
Chris Wilsona266c7d2012-04-24 22:59:44 +01003973 iir = I915_READ(IIR);
Chris Wilson38bde182012-04-24 22:59:50 +01003974 do {
3975 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson8291ee92012-04-24 22:59:47 +01003976 bool blc_event = false;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003977
3978 /* Can't rely on pipestat interrupt bit in iir as it might
3979 * have been cleared after the pipestat interrupt was received.
3980 * It doesn't set the bit in iir again, but it still produces
3981 * interrupts (for non-MSI).
3982 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02003983 spin_lock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003984 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Mika Kuoppala58174462014-02-25 17:11:26 +02003985 i915_handle_error(dev, false,
3986 "Command parser error, iir 0x%08x",
3987 iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003988
Damien Lespiau055e3932014-08-18 13:49:10 +01003989 for_each_pipe(dev_priv, pipe) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003990 int reg = PIPESTAT(pipe);
3991 pipe_stats[pipe] = I915_READ(reg);
3992
Chris Wilson38bde182012-04-24 22:59:50 +01003993 /* Clear the PIPE*STAT regs before the IIR */
Chris Wilsona266c7d2012-04-24 22:59:44 +01003994 if (pipe_stats[pipe] & 0x8000ffff) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003995 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilson38bde182012-04-24 22:59:50 +01003996 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003997 }
3998 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02003999 spin_unlock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004000
4001 if (!irq_received)
4002 break;
4003
Chris Wilsona266c7d2012-04-24 22:59:44 +01004004 /* Consume port. Then clear IIR or we'll miss events */
Ville Syrjälä16c6c562014-04-01 10:54:36 +03004005 if (I915_HAS_HOTPLUG(dev) &&
4006 iir & I915_DISPLAY_PORT_INTERRUPT)
4007 i9xx_hpd_irq_handler(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004008
Chris Wilson38bde182012-04-24 22:59:50 +01004009 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004010 new_iir = I915_READ(IIR); /* Flush posted writes */
4011
Chris Wilsona266c7d2012-04-24 22:59:44 +01004012 if (iir & I915_USER_INTERRUPT)
4013 notify_ring(dev, &dev_priv->ring[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004014
Damien Lespiau055e3932014-08-18 13:49:10 +01004015 for_each_pipe(dev_priv, pipe) {
Chris Wilson38bde182012-04-24 22:59:50 +01004016 int plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01004017 if (HAS_FBC(dev))
Chris Wilson38bde182012-04-24 22:59:50 +01004018 plane = !plane;
Ville Syrjälä5e2032d2013-02-19 15:16:38 +02004019
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004020 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4021 i915_handle_vblank(dev, plane, pipe, iir))
4022 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004023
4024 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4025 blc_event = true;
Daniel Vetter4356d582013-10-16 22:55:55 +02004026
4027 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02004028 i9xx_pipe_crc_irq_handler(dev, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004029
4030 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4031 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02004032 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
Chris Wilsona266c7d2012-04-24 22:59:44 +01004033 }
4034
Chris Wilsona266c7d2012-04-24 22:59:44 +01004035 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4036 intel_opregion_asle_intr(dev);
4037
4038 /* With MSI, interrupts are only generated when iir
4039 * transitions from zero to nonzero. If another bit got
4040 * set while we were handling the existing iir bits, then
4041 * we would never get another interrupt.
4042 *
4043 * This is fine on non-MSI as well, as if we hit this path
4044 * we avoid exiting the interrupt handler only to generate
4045 * another one.
4046 *
4047 * Note that for MSI this could cause a stray interrupt report
4048 * if an interrupt landed in the time between writing IIR and
4049 * the posting read. This should be rare enough to never
4050 * trigger the 99% of 100,000 interrupts test for disabling
4051 * stray interrupts.
4052 */
Chris Wilson38bde182012-04-24 22:59:50 +01004053 ret = IRQ_HANDLED;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004054 iir = new_iir;
Chris Wilson38bde182012-04-24 22:59:50 +01004055 } while (iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004056
Daniel Vetterd05c6172012-04-26 23:28:09 +02004057 i915_update_dri1_breadcrumb(dev);
Chris Wilson8291ee92012-04-24 22:59:47 +01004058
Chris Wilsona266c7d2012-04-24 22:59:44 +01004059 return ret;
4060}
4061
4062static void i915_irq_uninstall(struct drm_device * dev)
4063{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004064 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004065 int pipe;
4066
Chris Wilsona266c7d2012-04-24 22:59:44 +01004067 if (I915_HAS_HOTPLUG(dev)) {
4068 I915_WRITE(PORT_HOTPLUG_EN, 0);
4069 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4070 }
4071
Chris Wilson00d98eb2012-04-24 22:59:48 +01004072 I915_WRITE16(HWSTAM, 0xffff);
Damien Lespiau055e3932014-08-18 13:49:10 +01004073 for_each_pipe(dev_priv, pipe) {
Chris Wilson55b39752012-04-24 22:59:49 +01004074 /* Clear enable bits; then clear status bits */
Chris Wilsona266c7d2012-04-24 22:59:44 +01004075 I915_WRITE(PIPESTAT(pipe), 0);
Chris Wilson55b39752012-04-24 22:59:49 +01004076 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4077 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004078 I915_WRITE(IMR, 0xffffffff);
4079 I915_WRITE(IER, 0x0);
4080
Chris Wilsona266c7d2012-04-24 22:59:44 +01004081 I915_WRITE(IIR, I915_READ(IIR));
4082}
4083
4084static void i965_irq_preinstall(struct drm_device * dev)
4085{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004086 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004087 int pipe;
4088
Chris Wilsonadca4732012-05-11 18:01:31 +01004089 I915_WRITE(PORT_HOTPLUG_EN, 0);
4090 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01004091
4092 I915_WRITE(HWSTAM, 0xeffe);
Damien Lespiau055e3932014-08-18 13:49:10 +01004093 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004094 I915_WRITE(PIPESTAT(pipe), 0);
4095 I915_WRITE(IMR, 0xffffffff);
4096 I915_WRITE(IER, 0x0);
4097 POSTING_READ(IER);
4098}
4099
4100static int i965_irq_postinstall(struct drm_device *dev)
4101{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004102 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004103 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004104 u32 error_mask;
4105
Chris Wilsona266c7d2012-04-24 22:59:44 +01004106 /* Unmask the interrupts that we always want on. */
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004107 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
Chris Wilsonadca4732012-05-11 18:01:31 +01004108 I915_DISPLAY_PORT_INTERRUPT |
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004109 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4110 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4111 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4112 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4113 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4114
4115 enable_mask = ~dev_priv->irq_mask;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004116 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4117 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004118 enable_mask |= I915_USER_INTERRUPT;
4119
4120 if (IS_G4X(dev))
4121 enable_mask |= I915_BSD_USER_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004122
Daniel Vetterb79480b2013-06-27 17:52:10 +02004123 /* Interrupt setup is already guaranteed to be single-threaded, this is
4124 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02004125 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02004126 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4127 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4128 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02004129 spin_unlock_irq(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004130
Chris Wilsona266c7d2012-04-24 22:59:44 +01004131 /*
4132 * Enable some error detection, note the instruction error mask
4133 * bit is reserved, so we leave it masked.
4134 */
4135 if (IS_G4X(dev)) {
4136 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4137 GM45_ERROR_MEM_PRIV |
4138 GM45_ERROR_CP_PRIV |
4139 I915_ERROR_MEMORY_REFRESH);
4140 } else {
4141 error_mask = ~(I915_ERROR_PAGE_TABLE |
4142 I915_ERROR_MEMORY_REFRESH);
4143 }
4144 I915_WRITE(EMR, error_mask);
4145
4146 I915_WRITE(IMR, dev_priv->irq_mask);
4147 I915_WRITE(IER, enable_mask);
4148 POSTING_READ(IER);
4149
Daniel Vetter20afbda2012-12-11 14:05:07 +01004150 I915_WRITE(PORT_HOTPLUG_EN, 0);
4151 POSTING_READ(PORT_HOTPLUG_EN);
4152
Jani Nikulaf49e38d2013-04-29 13:02:54 +03004153 i915_enable_asle_pipestat(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01004154
4155 return 0;
4156}
4157
Egbert Eichbac56d52013-02-25 12:06:51 -05004158static void i915_hpd_irq_setup(struct drm_device *dev)
Daniel Vetter20afbda2012-12-11 14:05:07 +01004159{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004160 struct drm_i915_private *dev_priv = dev->dev_private;
Egbert Eichcd569ae2013-04-16 13:36:57 +02004161 struct intel_encoder *intel_encoder;
Daniel Vetter20afbda2012-12-11 14:05:07 +01004162 u32 hotplug_en;
4163
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02004164 assert_spin_locked(&dev_priv->irq_lock);
4165
Egbert Eichbac56d52013-02-25 12:06:51 -05004166 if (I915_HAS_HOTPLUG(dev)) {
4167 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4168 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4169 /* Note HDMI and DP share hotplug bits */
Egbert Eiche5868a32013-02-28 04:17:12 -05004170 /* enable bits are the same for all generations */
Damien Lespiaub2784e12014-08-05 11:29:37 +01004171 for_each_intel_encoder(dev, intel_encoder)
Egbert Eichcd569ae2013-04-16 13:36:57 +02004172 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4173 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
Egbert Eichbac56d52013-02-25 12:06:51 -05004174 /* Programming the CRT detection parameters tends
4175 to generate a spurious hotplug event about three
4176 seconds later. So just do it once.
4177 */
4178 if (IS_G4X(dev))
4179 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
Daniel Vetter85fc95b2013-03-27 15:47:11 +01004180 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
Egbert Eichbac56d52013-02-25 12:06:51 -05004181 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004182
Egbert Eichbac56d52013-02-25 12:06:51 -05004183 /* Ignore TV since it's buggy */
4184 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4185 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004186}
4187
Daniel Vetterff1f5252012-10-02 15:10:55 +02004188static irqreturn_t i965_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004189{
Daniel Vetter45a83f82014-05-12 19:17:55 +02004190 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03004191 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004192 u32 iir, new_iir;
4193 u32 pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01004194 int ret = IRQ_NONE, pipe;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004195 u32 flip_mask =
4196 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4197 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004198
Chris Wilsona266c7d2012-04-24 22:59:44 +01004199 iir = I915_READ(IIR);
4200
Chris Wilsona266c7d2012-04-24 22:59:44 +01004201 for (;;) {
Ville Syrjälä501e01d2014-01-17 11:35:15 +02004202 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson2c8ba292012-04-24 22:59:46 +01004203 bool blc_event = false;
4204
Chris Wilsona266c7d2012-04-24 22:59:44 +01004205 /* Can't rely on pipestat interrupt bit in iir as it might
4206 * have been cleared after the pipestat interrupt was received.
4207 * It doesn't set the bit in iir again, but it still produces
4208 * interrupts (for non-MSI).
4209 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02004210 spin_lock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004211 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Mika Kuoppala58174462014-02-25 17:11:26 +02004212 i915_handle_error(dev, false,
4213 "Command parser error, iir 0x%08x",
4214 iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004215
Damien Lespiau055e3932014-08-18 13:49:10 +01004216 for_each_pipe(dev_priv, pipe) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004217 int reg = PIPESTAT(pipe);
4218 pipe_stats[pipe] = I915_READ(reg);
4219
4220 /*
4221 * Clear the PIPE*STAT regs before the IIR
4222 */
4223 if (pipe_stats[pipe] & 0x8000ffff) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004224 I915_WRITE(reg, pipe_stats[pipe]);
Ville Syrjälä501e01d2014-01-17 11:35:15 +02004225 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004226 }
4227 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02004228 spin_unlock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004229
4230 if (!irq_received)
4231 break;
4232
4233 ret = IRQ_HANDLED;
4234
4235 /* Consume port. Then clear IIR or we'll miss events */
Ville Syrjälä16c6c562014-04-01 10:54:36 +03004236 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4237 i9xx_hpd_irq_handler(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004238
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004239 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004240 new_iir = I915_READ(IIR); /* Flush posted writes */
4241
Chris Wilsona266c7d2012-04-24 22:59:44 +01004242 if (iir & I915_USER_INTERRUPT)
4243 notify_ring(dev, &dev_priv->ring[RCS]);
4244 if (iir & I915_BSD_USER_INTERRUPT)
4245 notify_ring(dev, &dev_priv->ring[VCS]);
4246
Damien Lespiau055e3932014-08-18 13:49:10 +01004247 for_each_pipe(dev_priv, pipe) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01004248 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004249 i915_handle_vblank(dev, pipe, pipe, iir))
4250 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004251
4252 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4253 blc_event = true;
Daniel Vetter4356d582013-10-16 22:55:55 +02004254
4255 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02004256 i9xx_pipe_crc_irq_handler(dev, pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004257
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004258 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4259 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
Ville Syrjäläfc2c8072014-01-17 11:44:32 +02004260 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004261 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004262
4263 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4264 intel_opregion_asle_intr(dev);
4265
Daniel Vetter515ac2b2012-12-01 13:53:44 +01004266 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4267 gmbus_irq_handler(dev);
4268
Chris Wilsona266c7d2012-04-24 22:59:44 +01004269 /* With MSI, interrupts are only generated when iir
4270 * transitions from zero to nonzero. If another bit got
4271 * set while we were handling the existing iir bits, then
4272 * we would never get another interrupt.
4273 *
4274 * This is fine on non-MSI as well, as if we hit this path
4275 * we avoid exiting the interrupt handler only to generate
4276 * another one.
4277 *
4278 * Note that for MSI this could cause a stray interrupt report
4279 * if an interrupt landed in the time between writing IIR and
4280 * the posting read. This should be rare enough to never
4281 * trigger the 99% of 100,000 interrupts test for disabling
4282 * stray interrupts.
4283 */
4284 iir = new_iir;
4285 }
4286
Daniel Vetterd05c6172012-04-26 23:28:09 +02004287 i915_update_dri1_breadcrumb(dev);
Chris Wilson2c8ba292012-04-24 22:59:46 +01004288
Chris Wilsona266c7d2012-04-24 22:59:44 +01004289 return ret;
4290}
4291
4292static void i965_irq_uninstall(struct drm_device * dev)
4293{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004294 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004295 int pipe;
4296
4297 if (!dev_priv)
4298 return;
4299
Chris Wilsonadca4732012-05-11 18:01:31 +01004300 I915_WRITE(PORT_HOTPLUG_EN, 0);
4301 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01004302
4303 I915_WRITE(HWSTAM, 0xffffffff);
Damien Lespiau055e3932014-08-18 13:49:10 +01004304 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004305 I915_WRITE(PIPESTAT(pipe), 0);
4306 I915_WRITE(IMR, 0xffffffff);
4307 I915_WRITE(IER, 0x0);
4308
Damien Lespiau055e3932014-08-18 13:49:10 +01004309 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004310 I915_WRITE(PIPESTAT(pipe),
4311 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4312 I915_WRITE(IIR, I915_READ(IIR));
4313}
4314
Daniel Vetter4cb21832014-09-15 14:55:26 +02004315static void intel_hpd_irq_reenable_work(struct work_struct *work)
Egbert Eichac4c16c2013-04-16 13:36:58 +02004316{
Imre Deak63237512014-08-18 15:37:02 +03004317 struct drm_i915_private *dev_priv =
4318 container_of(work, typeof(*dev_priv),
4319 hotplug_reenable_work.work);
Egbert Eichac4c16c2013-04-16 13:36:58 +02004320 struct drm_device *dev = dev_priv->dev;
4321 struct drm_mode_config *mode_config = &dev->mode_config;
Egbert Eichac4c16c2013-04-16 13:36:58 +02004322 int i;
4323
Imre Deak63237512014-08-18 15:37:02 +03004324 intel_runtime_pm_get(dev_priv);
4325
Daniel Vetter4cb21832014-09-15 14:55:26 +02004326 spin_lock_irq(&dev_priv->irq_lock);
Egbert Eichac4c16c2013-04-16 13:36:58 +02004327 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4328 struct drm_connector *connector;
4329
4330 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4331 continue;
4332
4333 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4334
4335 list_for_each_entry(connector, &mode_config->connector_list, head) {
4336 struct intel_connector *intel_connector = to_intel_connector(connector);
4337
4338 if (intel_connector->encoder->hpd_pin == i) {
4339 if (connector->polled != intel_connector->polled)
4340 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03004341 connector->name);
Egbert Eichac4c16c2013-04-16 13:36:58 +02004342 connector->polled = intel_connector->polled;
4343 if (!connector->polled)
4344 connector->polled = DRM_CONNECTOR_POLL_HPD;
4345 }
4346 }
4347 }
4348 if (dev_priv->display.hpd_irq_setup)
4349 dev_priv->display.hpd_irq_setup(dev);
Daniel Vetter4cb21832014-09-15 14:55:26 +02004350 spin_unlock_irq(&dev_priv->irq_lock);
Imre Deak63237512014-08-18 15:37:02 +03004351
4352 intel_runtime_pm_put(dev_priv);
Egbert Eichac4c16c2013-04-16 13:36:58 +02004353}
4354
Daniel Vetterfca52a52014-09-30 10:56:45 +02004355/**
4356 * intel_irq_init - initializes irq support
4357 * @dev_priv: i915 device instance
4358 *
4359 * This function initializes all the irq support including work items, timers
4360 * and all the vtables. It does not setup the interrupt itself though.
4361 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004362void intel_irq_init(struct drm_i915_private *dev_priv)
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004363{
Daniel Vetterb9632912014-09-30 10:56:44 +02004364 struct drm_device *dev = dev_priv->dev;
Chris Wilson8b2e3262012-04-24 22:59:41 +01004365
4366 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
Dave Airlie13cf5502014-06-18 11:29:35 +10004367 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
Daniel Vetter99584db2012-11-14 17:14:04 +01004368 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02004369 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
Daniel Vettera4da4fa2012-11-02 19:55:07 +01004370 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
Chris Wilson8b2e3262012-04-24 22:59:41 +01004371
Deepak Sa6706b42014-03-15 20:23:22 +05304372 /* Let's track the enabled rps events */
Daniel Vetterb9632912014-09-30 10:56:44 +02004373 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
Ville Syrjälä6c65a582014-08-29 14:14:07 +03004374 /* WaGsvRC0ResidencyMethod:vlv */
Deepak S31685c22014-07-03 17:33:01 -04004375 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4376 else
4377 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
Deepak Sa6706b42014-03-15 20:23:22 +05304378
Daniel Vetter99584db2012-11-14 17:14:04 +01004379 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4380 i915_hangcheck_elapsed,
Daniel Vetter61bac782012-12-01 21:03:21 +01004381 (unsigned long) dev);
Imre Deak63237512014-08-18 15:37:02 +03004382 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
Daniel Vetter4cb21832014-09-15 14:55:26 +02004383 intel_hpd_irq_reenable_work);
Daniel Vetter61bac782012-12-01 21:03:21 +01004384
Tomas Janousek97a19a22012-12-08 13:48:13 +01004385 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01004386
Daniel Vetterb9632912014-09-30 10:56:44 +02004387 if (IS_GEN2(dev_priv)) {
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +03004388 dev->max_vblank_count = 0;
4389 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
Daniel Vetterb9632912014-09-30 10:56:44 +02004390 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004391 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4392 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
Ville Syrjälä391f75e2013-09-25 19:55:26 +03004393 } else {
4394 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4395 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004396 }
4397
Ville Syrjälä21da2702014-08-06 14:49:55 +03004398 /*
4399 * Opt out of the vblank disable timer on everything except gen2.
4400 * Gen2 doesn't have a hardware frame counter and so depends on
4401 * vblank interrupts to produce sane vblank seuquence numbers.
4402 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004403 if (!IS_GEN2(dev_priv))
Ville Syrjälä21da2702014-08-06 14:49:55 +03004404 dev->vblank_disable_immediate = true;
4405
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +03004406 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Keith Packardc3613de2011-08-12 17:05:54 -07004407 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +03004408 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4409 }
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004410
Daniel Vetterb9632912014-09-30 10:56:44 +02004411 if (IS_CHERRYVIEW(dev_priv)) {
Ville Syrjälä43f328d2014-04-09 20:40:52 +03004412 dev->driver->irq_handler = cherryview_irq_handler;
4413 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4414 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4415 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4416 dev->driver->enable_vblank = valleyview_enable_vblank;
4417 dev->driver->disable_vblank = valleyview_disable_vblank;
4418 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetterb9632912014-09-30 10:56:44 +02004419 } else if (IS_VALLEYVIEW(dev_priv)) {
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07004420 dev->driver->irq_handler = valleyview_irq_handler;
4421 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4422 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4423 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4424 dev->driver->enable_vblank = valleyview_enable_vblank;
4425 dev->driver->disable_vblank = valleyview_disable_vblank;
Egbert Eichfa00abe2013-02-25 12:06:48 -05004426 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetterb9632912014-09-30 10:56:44 +02004427 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
Ben Widawskyabd58f02013-11-02 21:07:09 -07004428 dev->driver->irq_handler = gen8_irq_handler;
Daniel Vetter723761b2014-05-22 17:56:34 +02004429 dev->driver->irq_preinstall = gen8_irq_reset;
Ben Widawskyabd58f02013-11-02 21:07:09 -07004430 dev->driver->irq_postinstall = gen8_irq_postinstall;
4431 dev->driver->irq_uninstall = gen8_irq_uninstall;
4432 dev->driver->enable_vblank = gen8_enable_vblank;
4433 dev->driver->disable_vblank = gen8_disable_vblank;
4434 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004435 } else if (HAS_PCH_SPLIT(dev)) {
4436 dev->driver->irq_handler = ironlake_irq_handler;
Daniel Vetter723761b2014-05-22 17:56:34 +02004437 dev->driver->irq_preinstall = ironlake_irq_reset;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004438 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4439 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4440 dev->driver->enable_vblank = ironlake_enable_vblank;
4441 dev->driver->disable_vblank = ironlake_disable_vblank;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01004442 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004443 } else {
Daniel Vetterb9632912014-09-30 10:56:44 +02004444 if (INTEL_INFO(dev_priv)->gen == 2) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01004445 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4446 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4447 dev->driver->irq_handler = i8xx_irq_handler;
4448 dev->driver->irq_uninstall = i8xx_irq_uninstall;
Daniel Vetterb9632912014-09-30 10:56:44 +02004449 } else if (INTEL_INFO(dev_priv)->gen == 3) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004450 dev->driver->irq_preinstall = i915_irq_preinstall;
4451 dev->driver->irq_postinstall = i915_irq_postinstall;
4452 dev->driver->irq_uninstall = i915_irq_uninstall;
4453 dev->driver->irq_handler = i915_irq_handler;
Daniel Vetter20afbda2012-12-11 14:05:07 +01004454 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Chris Wilsonc2798b12012-04-22 21:13:57 +01004455 } else {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004456 dev->driver->irq_preinstall = i965_irq_preinstall;
4457 dev->driver->irq_postinstall = i965_irq_postinstall;
4458 dev->driver->irq_uninstall = i965_irq_uninstall;
4459 dev->driver->irq_handler = i965_irq_handler;
Egbert Eichbac56d52013-02-25 12:06:51 -05004460 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Chris Wilsonc2798b12012-04-22 21:13:57 +01004461 }
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004462 dev->driver->enable_vblank = i915_enable_vblank;
4463 dev->driver->disable_vblank = i915_disable_vblank;
4464 }
4465}
Daniel Vetter20afbda2012-12-11 14:05:07 +01004466
Daniel Vetterfca52a52014-09-30 10:56:45 +02004467/**
4468 * intel_hpd_init - initializes and enables hpd support
4469 * @dev_priv: i915 device instance
4470 *
4471 * This function enables the hotplug support. It requires that interrupts have
4472 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4473 * poll request can run concurrently to other code, so locking rules must be
4474 * obeyed.
4475 *
4476 * This is a separate step from interrupt enabling to simplify the locking rules
4477 * in the driver load and resume code.
4478 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004479void intel_hpd_init(struct drm_i915_private *dev_priv)
Daniel Vetter20afbda2012-12-11 14:05:07 +01004480{
Daniel Vetterb9632912014-09-30 10:56:44 +02004481 struct drm_device *dev = dev_priv->dev;
Egbert Eich821450c2013-04-16 13:36:55 +02004482 struct drm_mode_config *mode_config = &dev->mode_config;
4483 struct drm_connector *connector;
4484 int i;
Daniel Vetter20afbda2012-12-11 14:05:07 +01004485
Egbert Eich821450c2013-04-16 13:36:55 +02004486 for (i = 1; i < HPD_NUM_PINS; i++) {
4487 dev_priv->hpd_stats[i].hpd_cnt = 0;
4488 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4489 }
4490 list_for_each_entry(connector, &mode_config->connector_list, head) {
4491 struct intel_connector *intel_connector = to_intel_connector(connector);
4492 connector->polled = intel_connector->polled;
Dave Airlie0e32b392014-05-02 14:02:48 +10004493 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4494 connector->polled = DRM_CONNECTOR_POLL_HPD;
4495 if (intel_connector->mst_port)
Egbert Eich821450c2013-04-16 13:36:55 +02004496 connector->polled = DRM_CONNECTOR_POLL_HPD;
4497 }
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02004498
4499 /* Interrupt setup is already guaranteed to be single-threaded, this is
4500 * just to make the assert_spin_locked checks happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02004501 spin_lock_irq(&dev_priv->irq_lock);
Daniel Vetter20afbda2012-12-11 14:05:07 +01004502 if (dev_priv->display.hpd_irq_setup)
4503 dev_priv->display.hpd_irq_setup(dev);
Daniel Vetterd6207432014-09-15 14:55:27 +02004504 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter20afbda2012-12-11 14:05:07 +01004505}
Paulo Zanonic67a4702013-08-19 13:18:09 -03004506
Daniel Vetterfca52a52014-09-30 10:56:45 +02004507/**
4508 * intel_irq_install - enables the hardware interrupt
4509 * @dev_priv: i915 device instance
4510 *
4511 * This function enables the hardware interrupt handling, but leaves the hotplug
4512 * handling still disabled. It is called after intel_irq_init().
4513 *
4514 * In the driver load and resume code we need working interrupts in a few places
4515 * but don't want to deal with the hassle of concurrent probe and hotplug
4516 * workers. Hence the split into this two-stage approach.
4517 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004518int intel_irq_install(struct drm_i915_private *dev_priv)
4519{
4520 /*
4521 * We enable some interrupt sources in our postinstall hooks, so mark
4522 * interrupts as enabled _before_ actually enabling them to avoid
4523 * special cases in our ordering checks.
4524 */
4525 dev_priv->pm.irqs_enabled = true;
4526
4527 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4528}
4529
Daniel Vetterfca52a52014-09-30 10:56:45 +02004530/**
4531 * intel_irq_uninstall - finilizes all irq handling
4532 * @dev_priv: i915 device instance
4533 *
4534 * This stops interrupt and hotplug handling and unregisters and frees all
4535 * resources acquired in the init functions.
4536 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004537void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4538{
4539 drm_irq_uninstall(dev_priv->dev);
4540 intel_hpd_cancel_work(dev_priv);
4541 dev_priv->pm.irqs_enabled = false;
4542}
4543
Daniel Vetterfca52a52014-09-30 10:56:45 +02004544/**
4545 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4546 * @dev_priv: i915 device instance
4547 *
4548 * This function is used to disable interrupts at runtime, both in the runtime
4549 * pm and the system suspend/resume code.
4550 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004551void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03004552{
Daniel Vetterb9632912014-09-30 10:56:44 +02004553 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004554 dev_priv->pm.irqs_enabled = false;
Paulo Zanonic67a4702013-08-19 13:18:09 -03004555}
4556
Daniel Vetterfca52a52014-09-30 10:56:45 +02004557/**
4558 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4559 * @dev_priv: i915 device instance
4560 *
4561 * This function is used to enable interrupts at runtime, both in the runtime
4562 * pm and the system suspend/resume code.
4563 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004564void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03004565{
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004566 dev_priv->pm.irqs_enabled = true;
Daniel Vetterb9632912014-09-30 10:56:44 +02004567 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4568 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03004569}