Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 31 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 33 | #include <linux/circ_buf.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 34 | #include <drm/drmP.h> |
| 35 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 37 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 40 | /** |
| 41 | * DOC: interrupt handling |
| 42 | * |
| 43 | * These functions provide the basic support for enabling and disabling the |
| 44 | * interrupt handling support. There's a lot more functionality in i915_irq.c |
| 45 | * and related files, but that will be described in separate chapters. |
| 46 | */ |
| 47 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 48 | static const u32 hpd_ibx[] = { |
| 49 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
| 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, |
| 51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, |
| 52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, |
| 53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG |
| 54 | }; |
| 55 | |
| 56 | static const u32 hpd_cpt[] = { |
| 57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
Daniel Vetter | 73c352a | 2013-03-26 22:38:43 +0100 | [diff] [blame] | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
| 60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, |
| 61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT |
| 62 | }; |
| 63 | |
| 64 | static const u32 hpd_mask_i915[] = { |
| 65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
| 66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, |
| 67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, |
| 68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, |
| 69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, |
| 70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN |
| 71 | }; |
| 72 | |
Daniel Vetter | 704cfb8 | 2013-12-18 09:08:43 +0100 | [diff] [blame] | 73 | static const u32 hpd_status_g4x[] = { |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, |
| 76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, |
| 77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 80 | }; |
| 81 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 82 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
| 83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, |
| 85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, |
| 86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 89 | }; |
| 90 | |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 91 | /* IIR can theoretically queue up two events. Be paranoid. */ |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 92 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 93 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
| 94 | POSTING_READ(GEN8_##type##_IMR(which)); \ |
| 95 | I915_WRITE(GEN8_##type##_IER(which), 0); \ |
| 96 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 97 | POSTING_READ(GEN8_##type##_IIR(which)); \ |
| 98 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 99 | POSTING_READ(GEN8_##type##_IIR(which)); \ |
| 100 | } while (0) |
| 101 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 102 | #define GEN5_IRQ_RESET(type) do { \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 103 | I915_WRITE(type##IMR, 0xffffffff); \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 104 | POSTING_READ(type##IMR); \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 105 | I915_WRITE(type##IER, 0); \ |
Paulo Zanoni | 5c50244 | 2014-04-01 15:37:11 -0300 | [diff] [blame] | 106 | I915_WRITE(type##IIR, 0xffffffff); \ |
| 107 | POSTING_READ(type##IIR); \ |
| 108 | I915_WRITE(type##IIR, 0xffffffff); \ |
| 109 | POSTING_READ(type##IIR); \ |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 110 | } while (0) |
| 111 | |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 112 | /* |
| 113 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. |
| 114 | */ |
| 115 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ |
| 116 | u32 val = I915_READ(reg); \ |
| 117 | if (val) { \ |
| 118 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ |
| 119 | (reg), val); \ |
| 120 | I915_WRITE((reg), 0xffffffff); \ |
| 121 | POSTING_READ(reg); \ |
| 122 | I915_WRITE((reg), 0xffffffff); \ |
| 123 | POSTING_READ(reg); \ |
| 124 | } \ |
| 125 | } while (0) |
| 126 | |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 127 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 128 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 129 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
Ville Syrjälä | 7d1bd539 | 2014-10-30 19:42:50 +0200 | [diff] [blame] | 130 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
| 131 | POSTING_READ(GEN8_##type##_IMR(which)); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 132 | } while (0) |
| 133 | |
| 134 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 135 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 136 | I915_WRITE(type##IER, (ier_val)); \ |
Ville Syrjälä | 7d1bd539 | 2014-10-30 19:42:50 +0200 | [diff] [blame] | 137 | I915_WRITE(type##IMR, (imr_val)); \ |
| 138 | POSTING_READ(type##IMR); \ |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 139 | } while (0) |
| 140 | |
Imre Deak | c9a9a26 | 2014-11-05 20:48:37 +0200 | [diff] [blame] | 141 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
| 142 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 143 | /* For display hotplug interrupt */ |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 144 | void |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 145 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 146 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 147 | assert_spin_locked(&dev_priv->irq_lock); |
| 148 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 149 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 150 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 151 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 152 | if ((dev_priv->irq_mask & mask) != 0) { |
| 153 | dev_priv->irq_mask &= ~mask; |
| 154 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 155 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 156 | } |
| 157 | } |
| 158 | |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 159 | void |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 160 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 161 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 162 | assert_spin_locked(&dev_priv->irq_lock); |
| 163 | |
Paulo Zanoni | 06ffc77 | 2014-07-17 17:43:46 -0300 | [diff] [blame] | 164 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 165 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 166 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 167 | if ((dev_priv->irq_mask & mask) != mask) { |
| 168 | dev_priv->irq_mask |= mask; |
| 169 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 170 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 171 | } |
| 172 | } |
| 173 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 174 | /** |
| 175 | * ilk_update_gt_irq - update GTIMR |
| 176 | * @dev_priv: driver private |
| 177 | * @interrupt_mask: mask of interrupt bits to update |
| 178 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 179 | */ |
| 180 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, |
| 181 | uint32_t interrupt_mask, |
| 182 | uint32_t enabled_irq_mask) |
| 183 | { |
| 184 | assert_spin_locked(&dev_priv->irq_lock); |
| 185 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 186 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 187 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 188 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 189 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
| 190 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); |
| 191 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 192 | POSTING_READ(GTIMR); |
| 193 | } |
| 194 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 195 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 196 | { |
| 197 | ilk_update_gt_irq(dev_priv, mask, mask); |
| 198 | } |
| 199 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 200 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 201 | { |
| 202 | ilk_update_gt_irq(dev_priv, mask, 0); |
| 203 | } |
| 204 | |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 205 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
| 206 | { |
| 207 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; |
| 208 | } |
| 209 | |
Imre Deak | a72fbc3 | 2014-11-05 20:48:31 +0200 | [diff] [blame] | 210 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
| 211 | { |
| 212 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; |
| 213 | } |
| 214 | |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 215 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
| 216 | { |
| 217 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; |
| 218 | } |
| 219 | |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 220 | /** |
| 221 | * snb_update_pm_irq - update GEN6_PMIMR |
| 222 | * @dev_priv: driver private |
| 223 | * @interrupt_mask: mask of interrupt bits to update |
| 224 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 225 | */ |
| 226 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
| 227 | uint32_t interrupt_mask, |
| 228 | uint32_t enabled_irq_mask) |
| 229 | { |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 230 | uint32_t new_val; |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 231 | |
| 232 | assert_spin_locked(&dev_priv->irq_lock); |
| 233 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 234 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 235 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 236 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 237 | new_val = dev_priv->pm_irq_mask; |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 238 | new_val &= ~interrupt_mask; |
| 239 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 240 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 241 | if (new_val != dev_priv->pm_irq_mask) { |
| 242 | dev_priv->pm_irq_mask = new_val; |
Imre Deak | a72fbc3 | 2014-11-05 20:48:31 +0200 | [diff] [blame] | 243 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
| 244 | POSTING_READ(gen6_pm_imr(dev_priv)); |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 245 | } |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 246 | } |
| 247 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 248 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 249 | { |
| 250 | snb_update_pm_irq(dev_priv, mask, mask); |
| 251 | } |
| 252 | |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 253 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 254 | { |
| 255 | snb_update_pm_irq(dev_priv, mask, 0); |
| 256 | } |
| 257 | |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame^] | 258 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
| 259 | { |
| 260 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 261 | uint32_t reg = gen6_pm_iir(dev_priv); |
| 262 | |
| 263 | spin_lock_irq(&dev_priv->irq_lock); |
| 264 | I915_WRITE(reg, dev_priv->pm_rps_events); |
| 265 | I915_WRITE(reg, dev_priv->pm_rps_events); |
| 266 | POSTING_READ(reg); |
| 267 | spin_unlock_irq(&dev_priv->irq_lock); |
| 268 | } |
| 269 | |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 270 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
| 271 | { |
| 272 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 273 | |
| 274 | spin_lock_irq(&dev_priv->irq_lock); |
| 275 | WARN_ON(dev_priv->rps.pm_iir); |
Imre Deak | 3cc134e | 2014-11-19 15:30:03 +0200 | [diff] [blame^] | 276 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 277 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
Imre Deak | b900b94 | 2014-11-05 20:48:48 +0200 | [diff] [blame] | 278 | spin_unlock_irq(&dev_priv->irq_lock); |
| 279 | } |
| 280 | |
| 281 | void gen6_disable_rps_interrupts(struct drm_device *dev) |
| 282 | { |
| 283 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 284 | |
| 285 | I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ? |
| 286 | ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0); |
| 287 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
| 288 | ~dev_priv->pm_rps_events); |
| 289 | /* Complete PM interrupt masking here doesn't race with the rps work |
| 290 | * item again unmasking PM interrupts because that is using a different |
| 291 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
| 292 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
| 293 | |
| 294 | spin_lock_irq(&dev_priv->irq_lock); |
| 295 | dev_priv->rps.pm_iir = 0; |
| 296 | spin_unlock_irq(&dev_priv->irq_lock); |
| 297 | |
| 298 | I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events); |
| 299 | } |
| 300 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 301 | /** |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 302 | * ibx_display_interrupt_update - update SDEIMR |
| 303 | * @dev_priv: driver private |
| 304 | * @interrupt_mask: mask of interrupt bits to update |
| 305 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 306 | */ |
Daniel Vetter | 47339cd | 2014-09-30 10:56:46 +0200 | [diff] [blame] | 307 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
| 308 | uint32_t interrupt_mask, |
| 309 | uint32_t enabled_irq_mask) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 310 | { |
| 311 | uint32_t sdeimr = I915_READ(SDEIMR); |
| 312 | sdeimr &= ~interrupt_mask; |
| 313 | sdeimr |= (~enabled_irq_mask & interrupt_mask); |
| 314 | |
| 315 | assert_spin_locked(&dev_priv->irq_lock); |
| 316 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 317 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 318 | return; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 319 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 320 | I915_WRITE(SDEIMR, sdeimr); |
| 321 | POSTING_READ(SDEIMR); |
| 322 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 323 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 324 | static void |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 325 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 326 | u32 enable_mask, u32 status_mask) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 327 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 328 | u32 reg = PIPESTAT(pipe); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 329 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 330 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 331 | assert_spin_locked(&dev_priv->irq_lock); |
Daniel Vetter | d518ce5 | 2014-08-27 10:43:37 +0200 | [diff] [blame] | 332 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 333 | |
Ville Syrjälä | 04feced | 2014-04-03 13:28:33 +0300 | [diff] [blame] | 334 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
| 335 | status_mask & ~PIPESTAT_INT_STATUS_MASK, |
| 336 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", |
| 337 | pipe_name(pipe), enable_mask, status_mask)) |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 338 | return; |
| 339 | |
| 340 | if ((pipestat & enable_mask) == enable_mask) |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 341 | return; |
| 342 | |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 343 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
| 344 | |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 345 | /* Enable the interrupt, clear any pending status */ |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 346 | pipestat |= enable_mask | status_mask; |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 347 | I915_WRITE(reg, pipestat); |
| 348 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 349 | } |
| 350 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 351 | static void |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 352 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 353 | u32 enable_mask, u32 status_mask) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 354 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 355 | u32 reg = PIPESTAT(pipe); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 356 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 357 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 358 | assert_spin_locked(&dev_priv->irq_lock); |
Daniel Vetter | d518ce5 | 2014-08-27 10:43:37 +0200 | [diff] [blame] | 359 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 360 | |
Ville Syrjälä | 04feced | 2014-04-03 13:28:33 +0300 | [diff] [blame] | 361 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
| 362 | status_mask & ~PIPESTAT_INT_STATUS_MASK, |
| 363 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", |
| 364 | pipe_name(pipe), enable_mask, status_mask)) |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 365 | return; |
| 366 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 367 | if ((pipestat & enable_mask) == 0) |
| 368 | return; |
| 369 | |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 370 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
| 371 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 372 | pipestat &= ~enable_mask; |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 373 | I915_WRITE(reg, pipestat); |
| 374 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 375 | } |
| 376 | |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 377 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
| 378 | { |
| 379 | u32 enable_mask = status_mask << 16; |
| 380 | |
| 381 | /* |
Ville Syrjälä | 724a690 | 2014-04-09 13:28:48 +0300 | [diff] [blame] | 382 | * On pipe A we don't support the PSR interrupt yet, |
| 383 | * on pipe B and C the same bit MBZ. |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 384 | */ |
| 385 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) |
| 386 | return 0; |
Ville Syrjälä | 724a690 | 2014-04-09 13:28:48 +0300 | [diff] [blame] | 387 | /* |
| 388 | * On pipe B and C we don't support the PSR interrupt yet, on pipe |
| 389 | * A the same bit is for perf counters which we don't use either. |
| 390 | */ |
| 391 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) |
| 392 | return 0; |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 393 | |
| 394 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | |
| 395 | SPRITE0_FLIP_DONE_INT_EN_VLV | |
| 396 | SPRITE1_FLIP_DONE_INT_EN_VLV); |
| 397 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) |
| 398 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; |
| 399 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) |
| 400 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; |
| 401 | |
| 402 | return enable_mask; |
| 403 | } |
| 404 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 405 | void |
| 406 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 407 | u32 status_mask) |
| 408 | { |
| 409 | u32 enable_mask; |
| 410 | |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 411 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 412 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
| 413 | status_mask); |
| 414 | else |
| 415 | enable_mask = status_mask << 16; |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 416 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
| 417 | } |
| 418 | |
| 419 | void |
| 420 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 421 | u32 status_mask) |
| 422 | { |
| 423 | u32 enable_mask; |
| 424 | |
Imre Deak | 10c59c5 | 2014-02-10 18:42:48 +0200 | [diff] [blame] | 425 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 426 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
| 427 | status_mask); |
| 428 | else |
| 429 | enable_mask = status_mask << 16; |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 430 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
| 431 | } |
| 432 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 433 | /** |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 434 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 435 | */ |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 436 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 437 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 438 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 439 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 440 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
| 441 | return; |
| 442 | |
Daniel Vetter | 1332178 | 2014-09-15 14:55:29 +0200 | [diff] [blame] | 443 | spin_lock_irq(&dev_priv->irq_lock); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 444 | |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 445 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
Jani Nikula | f898780 | 2013-04-29 13:02:53 +0300 | [diff] [blame] | 446 | if (INTEL_INFO(dev)->gen >= 4) |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 447 | i915_enable_pipestat(dev_priv, PIPE_A, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 448 | PIPE_LEGACY_BLC_EVENT_STATUS); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 449 | |
Daniel Vetter | 1332178 | 2014-09-15 14:55:29 +0200 | [diff] [blame] | 450 | spin_unlock_irq(&dev_priv->irq_lock); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 451 | } |
| 452 | |
| 453 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 454 | * i915_pipe_enabled - check if a pipe is enabled |
| 455 | * @dev: DRM device |
| 456 | * @pipe: pipe to check |
| 457 | * |
| 458 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 459 | * Use this routine to make sure the PLL is running and the pipe is active |
| 460 | * before reading such registers if unsure. |
| 461 | */ |
| 462 | static int |
| 463 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 464 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 465 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 466 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 467 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 468 | /* Locking is horribly broken here, but whatever. */ |
| 469 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 470 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 71f8ba6 | 2013-05-03 12:15:39 -0300 | [diff] [blame] | 471 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 472 | return intel_crtc->active; |
| 473 | } else { |
| 474 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
| 475 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 476 | } |
| 477 | |
Ville Syrjälä | f75f374 | 2014-05-15 20:20:36 +0300 | [diff] [blame] | 478 | /* |
| 479 | * This timing diagram depicts the video signal in and |
| 480 | * around the vertical blanking period. |
| 481 | * |
| 482 | * Assumptions about the fictitious mode used in this example: |
| 483 | * vblank_start >= 3 |
| 484 | * vsync_start = vblank_start + 1 |
| 485 | * vsync_end = vblank_start + 2 |
| 486 | * vtotal = vblank_start + 3 |
| 487 | * |
| 488 | * start of vblank: |
| 489 | * latch double buffered registers |
| 490 | * increment frame counter (ctg+) |
| 491 | * generate start of vblank interrupt (gen4+) |
| 492 | * | |
| 493 | * | frame start: |
| 494 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) |
| 495 | * | may be shifted forward 1-3 extra lines via PIPECONF |
| 496 | * | | |
| 497 | * | | start of vsync: |
| 498 | * | | generate vsync interrupt |
| 499 | * | | | |
| 500 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx |
| 501 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ |
| 502 | * ----va---> <-----------------vb--------------------> <--------va------------- |
| 503 | * | | <----vs-----> | |
| 504 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) |
| 505 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) |
| 506 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) |
| 507 | * | | | |
| 508 | * last visible pixel first visible pixel |
| 509 | * | increment frame counter (gen3/4) |
| 510 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) |
| 511 | * |
| 512 | * x = horizontal active |
| 513 | * _ = horizontal blanking |
| 514 | * hs = horizontal sync |
| 515 | * va = vertical active |
| 516 | * vb = vertical blanking |
| 517 | * vs = vertical sync |
| 518 | * vbs = vblank_start (number) |
| 519 | * |
| 520 | * Summary: |
| 521 | * - most events happen at the start of horizontal sync |
| 522 | * - frame start happens at the start of horizontal blank, 1-4 lines |
| 523 | * (depending on PIPECONF settings) after the start of vblank |
| 524 | * - gen3/4 pixel and frame counter are synchronized with the start |
| 525 | * of horizontal active on the first line of vertical active |
| 526 | */ |
| 527 | |
Ville Syrjälä | 4cdb83e | 2013-10-11 21:52:44 +0300 | [diff] [blame] | 528 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
| 529 | { |
| 530 | /* Gen2 doesn't have a hardware frame counter */ |
| 531 | return 0; |
| 532 | } |
| 533 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 534 | /* Called from drm generic code, passed a 'crtc', which |
| 535 | * we use as a pipe index |
| 536 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 537 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 538 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 539 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 540 | unsigned long high_frame; |
| 541 | unsigned long low_frame; |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 542 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 543 | |
| 544 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 545 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 546 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 547 | return 0; |
| 548 | } |
| 549 | |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 550 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 551 | struct intel_crtc *intel_crtc = |
| 552 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 553 | const struct drm_display_mode *mode = |
| 554 | &intel_crtc->config.adjusted_mode; |
| 555 | |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 556 | htotal = mode->crtc_htotal; |
| 557 | hsync_start = mode->crtc_hsync_start; |
| 558 | vbl_start = mode->crtc_vblank_start; |
| 559 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 560 | vbl_start = DIV_ROUND_UP(vbl_start, 2); |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 561 | } else { |
Daniel Vetter | a2d213d | 2014-02-07 16:34:05 +0100 | [diff] [blame] | 562 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 563 | |
| 564 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 565 | hsync_start = (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 566 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 567 | if ((I915_READ(PIPECONF(cpu_transcoder)) & |
| 568 | PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE) |
| 569 | vbl_start = DIV_ROUND_UP(vbl_start, 2); |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 570 | } |
| 571 | |
Ville Syrjälä | 0b2a8e0 | 2014-04-29 13:35:50 +0300 | [diff] [blame] | 572 | /* Convert to pixel count */ |
| 573 | vbl_start *= htotal; |
| 574 | |
| 575 | /* Start of vblank event occurs at start of hsync */ |
| 576 | vbl_start -= htotal - hsync_start; |
| 577 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 578 | high_frame = PIPEFRAME(pipe); |
| 579 | low_frame = PIPEFRAMEPIXEL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 580 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 581 | /* |
| 582 | * High & low register fields aren't synchronized, so make sure |
| 583 | * we get a low value that's stable across two reads of the high |
| 584 | * register. |
| 585 | */ |
| 586 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 587 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 588 | low = I915_READ(low_frame); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 589 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 590 | } while (high1 != high2); |
| 591 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 592 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 593 | pixel = low & PIPE_PIXEL_MASK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 594 | low >>= PIPE_FRAME_LOW_SHIFT; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 595 | |
| 596 | /* |
| 597 | * The frame counter increments at beginning of active. |
| 598 | * Cook up a vblank counter by also checking the pixel |
| 599 | * counter against vblank start. |
| 600 | */ |
Ville Syrjälä | edc08d0 | 2013-11-06 13:56:27 -0200 | [diff] [blame] | 601 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 602 | } |
| 603 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 604 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 605 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 606 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 607 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 608 | |
| 609 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 610 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 611 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 612 | return 0; |
| 613 | } |
| 614 | |
| 615 | return I915_READ(reg); |
| 616 | } |
| 617 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 618 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
| 619 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 620 | |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 621 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
| 622 | { |
| 623 | struct drm_device *dev = crtc->base.dev; |
| 624 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 625 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
| 626 | enum pipe pipe = crtc->pipe; |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 627 | int position, vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 628 | |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 629 | vtotal = mode->crtc_vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 630 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 631 | vtotal /= 2; |
| 632 | |
| 633 | if (IS_GEN2(dev)) |
| 634 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
| 635 | else |
| 636 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
| 637 | |
| 638 | /* |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 639 | * See update_scanline_offset() for the details on the |
| 640 | * scanline_offset adjustment. |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 641 | */ |
Ville Syrjälä | 80715b2 | 2014-05-15 20:23:23 +0300 | [diff] [blame] | 642 | return (position + crtc->scanline_offset) % vtotal; |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 643 | } |
| 644 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 645 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
Ville Syrjälä | abca9e4 | 2013-10-28 20:50:48 +0200 | [diff] [blame] | 646 | unsigned int flags, int *vpos, int *hpos, |
| 647 | ktime_t *stime, ktime_t *etime) |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 648 | { |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 649 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 650 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 651 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 652 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 653 | int position; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 654 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 655 | bool in_vbl = true; |
| 656 | int ret = 0; |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 657 | unsigned long irqflags; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 658 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 659 | if (!intel_crtc->active) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 660 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 661 | "pipe %c\n", pipe_name(pipe)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 662 | return 0; |
| 663 | } |
| 664 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 665 | htotal = mode->crtc_htotal; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 666 | hsync_start = mode->crtc_hsync_start; |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 667 | vtotal = mode->crtc_vtotal; |
| 668 | vbl_start = mode->crtc_vblank_start; |
| 669 | vbl_end = mode->crtc_vblank_end; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 670 | |
Ville Syrjälä | d31faf6 | 2013-10-28 16:31:41 +0200 | [diff] [blame] | 671 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 672 | vbl_start = DIV_ROUND_UP(vbl_start, 2); |
| 673 | vbl_end /= 2; |
| 674 | vtotal /= 2; |
| 675 | } |
| 676 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 677 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
| 678 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 679 | /* |
| 680 | * Lock uncore.lock, as we will do multiple timing critical raw |
| 681 | * register reads, potentially with preemption disabled, so the |
| 682 | * following code must not block on uncore.lock. |
| 683 | */ |
| 684 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 685 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 686 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
| 687 | |
| 688 | /* Get optional system timestamp before query. */ |
| 689 | if (stime) |
| 690 | *stime = ktime_get(); |
| 691 | |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 692 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 693 | /* No obvious pixelcount register. Only query vertical |
| 694 | * scanout position from Display scan line register. |
| 695 | */ |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 696 | position = __intel_get_crtc_scanline(intel_crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 697 | } else { |
| 698 | /* Have access to pixelcount since start of frame. |
| 699 | * We can split this into vertical and horizontal |
| 700 | * scanout position. |
| 701 | */ |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 702 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 703 | |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 704 | /* convert to pixel counts */ |
| 705 | vbl_start *= htotal; |
| 706 | vbl_end *= htotal; |
| 707 | vtotal *= htotal; |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 708 | |
| 709 | /* |
Ville Syrjälä | 7e78f1cb | 2014-04-29 13:35:49 +0300 | [diff] [blame] | 710 | * In interlaced modes, the pixel counter counts all pixels, |
| 711 | * so one field will have htotal more pixels. In order to avoid |
| 712 | * the reported position from jumping backwards when the pixel |
| 713 | * counter is beyond the length of the shorter field, just |
| 714 | * clamp the position the length of the shorter field. This |
| 715 | * matches how the scanline counter based position works since |
| 716 | * the scanline counter doesn't count the two half lines. |
| 717 | */ |
| 718 | if (position >= vtotal) |
| 719 | position = vtotal - 1; |
| 720 | |
| 721 | /* |
Ville Syrjälä | 78e8fc6 | 2014-04-29 13:35:44 +0300 | [diff] [blame] | 722 | * Start of vblank interrupt is triggered at start of hsync, |
| 723 | * just prior to the first active line of vblank. However we |
| 724 | * consider lines to start at the leading edge of horizontal |
| 725 | * active. So, should we get here before we've crossed into |
| 726 | * the horizontal active of the first line in vblank, we would |
| 727 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, |
| 728 | * always add htotal-hsync_start to the current pixel position. |
| 729 | */ |
| 730 | position = (position + htotal - hsync_start) % vtotal; |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 731 | } |
| 732 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 733 | /* Get optional system timestamp after query. */ |
| 734 | if (etime) |
| 735 | *etime = ktime_get(); |
| 736 | |
| 737 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ |
| 738 | |
| 739 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 740 | |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 741 | in_vbl = position >= vbl_start && position < vbl_end; |
| 742 | |
| 743 | /* |
| 744 | * While in vblank, position will be negative |
| 745 | * counting up towards 0 at vbl_end. And outside |
| 746 | * vblank, position will be positive counting |
| 747 | * up since vbl_end. |
| 748 | */ |
| 749 | if (position >= vbl_start) |
| 750 | position -= vbl_end; |
| 751 | else |
| 752 | position += vtotal - vbl_end; |
| 753 | |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 754 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 755 | *vpos = position; |
| 756 | *hpos = 0; |
| 757 | } else { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 758 | *vpos = position / htotal; |
| 759 | *hpos = position - (*vpos * htotal); |
| 760 | } |
| 761 | |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 762 | /* In vblank? */ |
| 763 | if (in_vbl) |
Daniel Vetter | 3d3cbd8 | 2014-09-10 17:36:11 +0200 | [diff] [blame] | 764 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 765 | |
| 766 | return ret; |
| 767 | } |
| 768 | |
Ville Syrjälä | a225f07 | 2014-04-29 13:35:45 +0300 | [diff] [blame] | 769 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
| 770 | { |
| 771 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 772 | unsigned long irqflags; |
| 773 | int position; |
| 774 | |
| 775 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 776 | position = __intel_get_crtc_scanline(crtc); |
| 777 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 778 | |
| 779 | return position; |
| 780 | } |
| 781 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 782 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 783 | int *max_error, |
| 784 | struct timeval *vblank_time, |
| 785 | unsigned flags) |
| 786 | { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 787 | struct drm_crtc *crtc; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 788 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 789 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 790 | DRM_ERROR("Invalid crtc %d\n", pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 791 | return -EINVAL; |
| 792 | } |
| 793 | |
| 794 | /* Get drm_crtc to timestamp: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 795 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
| 796 | if (crtc == NULL) { |
| 797 | DRM_ERROR("Invalid crtc %d\n", pipe); |
| 798 | return -EINVAL; |
| 799 | } |
| 800 | |
| 801 | if (!crtc->enabled) { |
| 802 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
| 803 | return -EBUSY; |
| 804 | } |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 805 | |
| 806 | /* Helper routine in DRM core does all the work: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 807 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
| 808 | vblank_time, flags, |
Ville Syrjälä | 7da903e | 2013-10-26 17:57:31 +0300 | [diff] [blame] | 809 | crtc, |
| 810 | &to_intel_crtc(crtc)->config.adjusted_mode); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 811 | } |
| 812 | |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 813 | static bool intel_hpd_irq_event(struct drm_device *dev, |
| 814 | struct drm_connector *connector) |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 815 | { |
| 816 | enum drm_connector_status old_status; |
| 817 | |
| 818 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
| 819 | old_status = connector->status; |
| 820 | |
| 821 | connector->status = connector->funcs->detect(connector, false); |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 822 | if (old_status == connector->status) |
| 823 | return false; |
| 824 | |
| 825 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 826 | connector->base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 827 | connector->name, |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 828 | drm_get_connector_status_name(old_status), |
| 829 | drm_get_connector_status_name(connector->status)); |
| 830 | |
| 831 | return true; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 832 | } |
| 833 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 834 | static void i915_digport_work_func(struct work_struct *work) |
| 835 | { |
| 836 | struct drm_i915_private *dev_priv = |
| 837 | container_of(work, struct drm_i915_private, dig_port_work); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 838 | u32 long_port_mask, short_port_mask; |
| 839 | struct intel_digital_port *intel_dig_port; |
| 840 | int i, ret; |
| 841 | u32 old_bits = 0; |
| 842 | |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 843 | spin_lock_irq(&dev_priv->irq_lock); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 844 | long_port_mask = dev_priv->long_hpd_port_mask; |
| 845 | dev_priv->long_hpd_port_mask = 0; |
| 846 | short_port_mask = dev_priv->short_hpd_port_mask; |
| 847 | dev_priv->short_hpd_port_mask = 0; |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 848 | spin_unlock_irq(&dev_priv->irq_lock); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 849 | |
| 850 | for (i = 0; i < I915_MAX_PORTS; i++) { |
| 851 | bool valid = false; |
| 852 | bool long_hpd = false; |
| 853 | intel_dig_port = dev_priv->hpd_irq_port[i]; |
| 854 | if (!intel_dig_port || !intel_dig_port->hpd_pulse) |
| 855 | continue; |
| 856 | |
| 857 | if (long_port_mask & (1 << i)) { |
| 858 | valid = true; |
| 859 | long_hpd = true; |
| 860 | } else if (short_port_mask & (1 << i)) |
| 861 | valid = true; |
| 862 | |
| 863 | if (valid) { |
| 864 | ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); |
| 865 | if (ret == true) { |
| 866 | /* if we get true fallback to old school hpd */ |
| 867 | old_bits |= (1 << intel_dig_port->base.hpd_pin); |
| 868 | } |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | if (old_bits) { |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 873 | spin_lock_irq(&dev_priv->irq_lock); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 874 | dev_priv->hpd_event_bits |= old_bits; |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 875 | spin_unlock_irq(&dev_priv->irq_lock); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 876 | schedule_work(&dev_priv->hotplug_work); |
| 877 | } |
| 878 | } |
| 879 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 880 | /* |
| 881 | * Handle hotplug events outside the interrupt handler proper. |
| 882 | */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 883 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
| 884 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 885 | static void i915_hotplug_work_func(struct work_struct *work) |
| 886 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 887 | struct drm_i915_private *dev_priv = |
| 888 | container_of(work, struct drm_i915_private, hotplug_work); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 889 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 890 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 891 | struct intel_connector *intel_connector; |
| 892 | struct intel_encoder *intel_encoder; |
| 893 | struct drm_connector *connector; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 894 | bool hpd_disabled = false; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 895 | bool changed = false; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 896 | u32 hpd_event_bits; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 897 | |
Keith Packard | a65e34c | 2011-07-25 10:04:56 -0700 | [diff] [blame] | 898 | mutex_lock(&mode_config->mutex); |
Jesse Barnes | e67189ab | 2011-02-11 14:44:51 -0800 | [diff] [blame] | 899 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
| 900 | |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 901 | spin_lock_irq(&dev_priv->irq_lock); |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 902 | |
| 903 | hpd_event_bits = dev_priv->hpd_event_bits; |
| 904 | dev_priv->hpd_event_bits = 0; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 905 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 906 | intel_connector = to_intel_connector(connector); |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 907 | if (!intel_connector->encoder) |
| 908 | continue; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 909 | intel_encoder = intel_connector->encoder; |
| 910 | if (intel_encoder->hpd_pin > HPD_NONE && |
| 911 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && |
| 912 | connector->polled == DRM_CONNECTOR_POLL_HPD) { |
| 913 | DRM_INFO("HPD interrupt storm detected on connector %s: " |
| 914 | "switching from hotplug detection to polling\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 915 | connector->name); |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 916 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
| 917 | connector->polled = DRM_CONNECTOR_POLL_CONNECT |
| 918 | | DRM_CONNECTOR_POLL_DISCONNECT; |
| 919 | hpd_disabled = true; |
| 920 | } |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 921 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 922 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 923 | connector->name, intel_encoder->hpd_pin); |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 924 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 925 | } |
| 926 | /* if there were no outputs to poll, poll was disabled, |
| 927 | * therefore make sure it's enabled when disabling HPD on |
| 928 | * some connectors */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 929 | if (hpd_disabled) { |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 930 | drm_kms_helper_poll_enable(dev); |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 931 | mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, |
| 932 | msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 933 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 934 | |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 935 | spin_unlock_irq(&dev_priv->irq_lock); |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 936 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 937 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 938 | intel_connector = to_intel_connector(connector); |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 939 | if (!intel_connector->encoder) |
| 940 | continue; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 941 | intel_encoder = intel_connector->encoder; |
| 942 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 943 | if (intel_encoder->hot_plug) |
| 944 | intel_encoder->hot_plug(intel_encoder); |
| 945 | if (intel_hpd_irq_event(dev, connector)) |
| 946 | changed = true; |
| 947 | } |
| 948 | } |
Keith Packard | 40ee338 | 2011-07-28 15:31:19 -0700 | [diff] [blame] | 949 | mutex_unlock(&mode_config->mutex); |
| 950 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 951 | if (changed) |
| 952 | drm_kms_helper_hotplug_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 953 | } |
| 954 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 955 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 956 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 957 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 958 | u32 busy_up, busy_down, max_avg, min_avg; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 959 | u8 new_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 960 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 961 | spin_lock(&mchdev_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 962 | |
Daniel Vetter | 73edd18f | 2012-08-08 23:35:37 +0200 | [diff] [blame] | 963 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
| 964 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 965 | new_delay = dev_priv->ips.cur_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 966 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 967 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 968 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 969 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 970 | max_avg = I915_READ(RCBMAXAVG); |
| 971 | min_avg = I915_READ(RCBMINAVG); |
| 972 | |
| 973 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 974 | if (busy_up > max_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 975 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
| 976 | new_delay = dev_priv->ips.cur_delay - 1; |
| 977 | if (new_delay < dev_priv->ips.max_delay) |
| 978 | new_delay = dev_priv->ips.max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 979 | } else if (busy_down < min_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 980 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
| 981 | new_delay = dev_priv->ips.cur_delay + 1; |
| 982 | if (new_delay > dev_priv->ips.min_delay) |
| 983 | new_delay = dev_priv->ips.min_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 984 | } |
| 985 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 986 | if (ironlake_set_drps(dev, new_delay)) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 987 | dev_priv->ips.cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 988 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 989 | spin_unlock(&mchdev_lock); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 990 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 991 | return; |
| 992 | } |
| 993 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 994 | static void notify_ring(struct drm_device *dev, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 995 | struct intel_engine_cs *ring) |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 996 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 997 | if (!intel_ring_initialized(ring)) |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 998 | return; |
| 999 | |
Chris Wilson | 814e9b5 | 2013-09-23 17:33:19 -0300 | [diff] [blame] | 1000 | trace_i915_gem_request_complete(ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 1001 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1002 | wake_up_all(&ring->irq_queue); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1003 | } |
| 1004 | |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1005 | static u32 vlv_c0_residency(struct drm_i915_private *dev_priv, |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1006 | struct intel_rps_ei *rps_ei) |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1007 | { |
| 1008 | u32 cz_ts, cz_freq_khz; |
| 1009 | u32 render_count, media_count; |
| 1010 | u32 elapsed_render, elapsed_media, elapsed_time; |
| 1011 | u32 residency = 0; |
| 1012 | |
| 1013 | cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
| 1014 | cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4); |
| 1015 | |
| 1016 | render_count = I915_READ(VLV_RENDER_C0_COUNT_REG); |
| 1017 | media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG); |
| 1018 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1019 | if (rps_ei->cz_clock == 0) { |
| 1020 | rps_ei->cz_clock = cz_ts; |
| 1021 | rps_ei->render_c0 = render_count; |
| 1022 | rps_ei->media_c0 = media_count; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1023 | |
| 1024 | return dev_priv->rps.cur_freq; |
| 1025 | } |
| 1026 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1027 | elapsed_time = cz_ts - rps_ei->cz_clock; |
| 1028 | rps_ei->cz_clock = cz_ts; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1029 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1030 | elapsed_render = render_count - rps_ei->render_c0; |
| 1031 | rps_ei->render_c0 = render_count; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1032 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1033 | elapsed_media = media_count - rps_ei->media_c0; |
| 1034 | rps_ei->media_c0 = media_count; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1035 | |
| 1036 | /* Convert all the counters into common unit of milli sec */ |
| 1037 | elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC; |
| 1038 | elapsed_render /= cz_freq_khz; |
| 1039 | elapsed_media /= cz_freq_khz; |
| 1040 | |
| 1041 | /* |
| 1042 | * Calculate overall C0 residency percentage |
| 1043 | * only if elapsed time is non zero |
| 1044 | */ |
| 1045 | if (elapsed_time) { |
| 1046 | residency = |
| 1047 | ((max(elapsed_render, elapsed_media) * 100) |
| 1048 | / elapsed_time); |
| 1049 | } |
| 1050 | |
| 1051 | return residency; |
| 1052 | } |
| 1053 | |
| 1054 | /** |
| 1055 | * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU |
| 1056 | * busy-ness calculated from C0 counters of render & media power wells |
| 1057 | * @dev_priv: DRM device private |
| 1058 | * |
| 1059 | */ |
Damien Lespiau | 4fa7904 | 2014-08-08 19:25:57 +0100 | [diff] [blame] | 1060 | static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv) |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1061 | { |
| 1062 | u32 residency_C0_up = 0, residency_C0_down = 0; |
Damien Lespiau | 4fa7904 | 2014-08-08 19:25:57 +0100 | [diff] [blame] | 1063 | int new_delay, adj; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1064 | |
| 1065 | dev_priv->rps.ei_interrupt_count++; |
| 1066 | |
| 1067 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 1068 | |
| 1069 | |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1070 | if (dev_priv->rps.up_ei.cz_clock == 0) { |
| 1071 | vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei); |
| 1072 | vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1073 | return dev_priv->rps.cur_freq; |
| 1074 | } |
| 1075 | |
| 1076 | |
| 1077 | /* |
| 1078 | * To down throttle, C0 residency should be less than down threshold |
| 1079 | * for continous EI intervals. So calculate down EI counters |
| 1080 | * once in VLV_INT_COUNT_FOR_DOWN_EI |
| 1081 | */ |
| 1082 | if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) { |
| 1083 | |
| 1084 | dev_priv->rps.ei_interrupt_count = 0; |
| 1085 | |
| 1086 | residency_C0_down = vlv_c0_residency(dev_priv, |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1087 | &dev_priv->rps.down_ei); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1088 | } else { |
| 1089 | residency_C0_up = vlv_c0_residency(dev_priv, |
Chris Wilson | bf225f2 | 2014-07-10 20:31:18 +0100 | [diff] [blame] | 1090 | &dev_priv->rps.up_ei); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1091 | } |
| 1092 | |
| 1093 | new_delay = dev_priv->rps.cur_freq; |
| 1094 | |
| 1095 | adj = dev_priv->rps.last_adj; |
| 1096 | /* C0 residency is greater than UP threshold. Increase Frequency */ |
| 1097 | if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) { |
| 1098 | if (adj > 0) |
| 1099 | adj *= 2; |
| 1100 | else |
| 1101 | adj = 1; |
| 1102 | |
| 1103 | if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit) |
| 1104 | new_delay = dev_priv->rps.cur_freq + adj; |
| 1105 | |
| 1106 | /* |
| 1107 | * For better performance, jump directly |
| 1108 | * to RPe if we're below it. |
| 1109 | */ |
| 1110 | if (new_delay < dev_priv->rps.efficient_freq) |
| 1111 | new_delay = dev_priv->rps.efficient_freq; |
| 1112 | |
| 1113 | } else if (!dev_priv->rps.ei_interrupt_count && |
| 1114 | (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) { |
| 1115 | if (adj < 0) |
| 1116 | adj *= 2; |
| 1117 | else |
| 1118 | adj = -1; |
| 1119 | /* |
| 1120 | * This means, C0 residency is less than down threshold over |
| 1121 | * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq |
| 1122 | */ |
| 1123 | if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit) |
| 1124 | new_delay = dev_priv->rps.cur_freq + adj; |
| 1125 | } |
| 1126 | |
| 1127 | return new_delay; |
| 1128 | } |
| 1129 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 1130 | static void gen6_pm_rps_work(struct work_struct *work) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1131 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1132 | struct drm_i915_private *dev_priv = |
| 1133 | container_of(work, struct drm_i915_private, rps.work); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 1134 | u32 pm_iir; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1135 | int new_delay, adj; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1136 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1137 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1138 | pm_iir = dev_priv->rps.pm_iir; |
| 1139 | dev_priv->rps.pm_iir = 0; |
Imre Deak | a72fbc3 | 2014-11-05 20:48:31 +0200 | [diff] [blame] | 1140 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
| 1141 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1142 | spin_unlock_irq(&dev_priv->irq_lock); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 1143 | |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 1144 | /* Make sure we didn't queue anything we're not going to process. */ |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1145 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 1146 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1147 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1148 | return; |
| 1149 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1150 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 1151 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1152 | adj = dev_priv->rps.last_adj; |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 1153 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1154 | if (adj > 0) |
| 1155 | adj *= 2; |
Deepak S | 13a5660 | 2014-05-23 21:00:21 +0530 | [diff] [blame] | 1156 | else { |
| 1157 | /* CHV needs even encode values */ |
| 1158 | adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; |
| 1159 | } |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1160 | new_delay = dev_priv->rps.cur_freq + adj; |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 1161 | |
| 1162 | /* |
| 1163 | * For better performance, jump directly |
| 1164 | * to RPe if we're below it. |
| 1165 | */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1166 | if (new_delay < dev_priv->rps.efficient_freq) |
| 1167 | new_delay = dev_priv->rps.efficient_freq; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1168 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1169 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
| 1170 | new_delay = dev_priv->rps.efficient_freq; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1171 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1172 | new_delay = dev_priv->rps.min_freq_softlimit; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1173 | adj = 0; |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 1174 | } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
| 1175 | new_delay = vlv_calc_delay_from_C0_counters(dev_priv); |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1176 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
| 1177 | if (adj < 0) |
| 1178 | adj *= 2; |
Deepak S | 13a5660 | 2014-05-23 21:00:21 +0530 | [diff] [blame] | 1179 | else { |
| 1180 | /* CHV needs even encode values */ |
| 1181 | adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; |
| 1182 | } |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1183 | new_delay = dev_priv->rps.cur_freq + adj; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1184 | } else { /* unknown event */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1185 | new_delay = dev_priv->rps.cur_freq; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1186 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1187 | |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 1188 | /* sysfs frequency interfaces may have snuck in while servicing the |
| 1189 | * interrupt |
| 1190 | */ |
Ville Syrjälä | 1272e7b | 2013-11-07 19:57:49 +0200 | [diff] [blame] | 1191 | new_delay = clamp_t(int, new_delay, |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1192 | dev_priv->rps.min_freq_softlimit, |
| 1193 | dev_priv->rps.max_freq_softlimit); |
Deepak S | 2754436 | 2014-01-27 21:35:05 +0530 | [diff] [blame] | 1194 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1195 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1196 | |
| 1197 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 1198 | valleyview_set_rps(dev_priv->dev, new_delay); |
| 1199 | else |
| 1200 | gen6_set_rps(dev_priv->dev, new_delay); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1201 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1202 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1203 | } |
| 1204 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1205 | |
| 1206 | /** |
| 1207 | * ivybridge_parity_work - Workqueue called when a parity error interrupt |
| 1208 | * occurred. |
| 1209 | * @work: workqueue struct |
| 1210 | * |
| 1211 | * Doesn't actually do anything except notify userspace. As a consequence of |
| 1212 | * this event, userspace should try to remap the bad rows since statistically |
| 1213 | * it is likely the same row is more likely to go bad again. |
| 1214 | */ |
| 1215 | static void ivybridge_parity_work(struct work_struct *work) |
| 1216 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1217 | struct drm_i915_private *dev_priv = |
| 1218 | container_of(work, struct drm_i915_private, l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1219 | u32 error_status, row, bank, subbank; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1220 | char *parity_event[6]; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1221 | uint32_t misccpctl; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1222 | uint8_t slice = 0; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1223 | |
| 1224 | /* We must turn off DOP level clock gating to access the L3 registers. |
| 1225 | * In order to prevent a get/put style interface, acquire struct mutex |
| 1226 | * any time we access those registers. |
| 1227 | */ |
| 1228 | mutex_lock(&dev_priv->dev->struct_mutex); |
| 1229 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1230 | /* If we've screwed up tracking, just let the interrupt fire again */ |
| 1231 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) |
| 1232 | goto out; |
| 1233 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1234 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 1235 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 1236 | POSTING_READ(GEN7_MISCCPCTL); |
| 1237 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1238 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
| 1239 | u32 reg; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1240 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1241 | slice--; |
| 1242 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) |
| 1243 | break; |
| 1244 | |
| 1245 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
| 1246 | |
| 1247 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
| 1248 | |
| 1249 | error_status = I915_READ(reg); |
| 1250 | row = GEN7_PARITY_ERROR_ROW(error_status); |
| 1251 | bank = GEN7_PARITY_ERROR_BANK(error_status); |
| 1252 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); |
| 1253 | |
| 1254 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); |
| 1255 | POSTING_READ(reg); |
| 1256 | |
| 1257 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; |
| 1258 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); |
| 1259 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); |
| 1260 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); |
| 1261 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); |
| 1262 | parity_event[5] = NULL; |
| 1263 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 1264 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1265 | KOBJ_CHANGE, parity_event); |
| 1266 | |
| 1267 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
| 1268 | slice, row, bank, subbank); |
| 1269 | |
| 1270 | kfree(parity_event[4]); |
| 1271 | kfree(parity_event[3]); |
| 1272 | kfree(parity_event[2]); |
| 1273 | kfree(parity_event[1]); |
| 1274 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1275 | |
| 1276 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 1277 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1278 | out: |
| 1279 | WARN_ON(dev_priv->l3_parity.which_slice); |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 1280 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1281 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 1282 | spin_unlock_irq(&dev_priv->irq_lock); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1283 | |
| 1284 | mutex_unlock(&dev_priv->dev->struct_mutex); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1285 | } |
| 1286 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1287 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1288 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1289 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1290 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1291 | if (!HAS_L3_DPF(dev)) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1292 | return; |
| 1293 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1294 | spin_lock(&dev_priv->irq_lock); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1295 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1296 | spin_unlock(&dev_priv->irq_lock); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1297 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1298 | iir &= GT_PARITY_ERROR(dev); |
| 1299 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
| 1300 | dev_priv->l3_parity.which_slice |= 1 << 1; |
| 1301 | |
| 1302 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) |
| 1303 | dev_priv->l3_parity.which_slice |= 1 << 0; |
| 1304 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1305 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1306 | } |
| 1307 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1308 | static void ilk_gt_irq_handler(struct drm_device *dev, |
| 1309 | struct drm_i915_private *dev_priv, |
| 1310 | u32 gt_iir) |
| 1311 | { |
| 1312 | if (gt_iir & |
| 1313 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
| 1314 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 1315 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
| 1316 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 1317 | } |
| 1318 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1319 | static void snb_gt_irq_handler(struct drm_device *dev, |
| 1320 | struct drm_i915_private *dev_priv, |
| 1321 | u32 gt_iir) |
| 1322 | { |
| 1323 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1324 | if (gt_iir & |
| 1325 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1326 | notify_ring(dev, &dev_priv->ring[RCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1327 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1328 | notify_ring(dev, &dev_priv->ring[VCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1329 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1330 | notify_ring(dev, &dev_priv->ring[BCS]); |
| 1331 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1332 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
| 1333 | GT_BSD_CS_ERROR_INTERRUPT | |
| 1334 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 1335 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
| 1336 | gt_iir); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1337 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1338 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1339 | if (gt_iir & GT_PARITY_ERROR(dev)) |
| 1340 | ivybridge_parity_error_irq_handler(dev, gt_iir); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1341 | } |
| 1342 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1343 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
| 1344 | struct drm_i915_private *dev_priv, |
| 1345 | u32 master_ctl) |
| 1346 | { |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1347 | struct intel_engine_cs *ring; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1348 | u32 rcs, bcs, vcs; |
| 1349 | uint32_t tmp = 0; |
| 1350 | irqreturn_t ret = IRQ_NONE; |
| 1351 | |
| 1352 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { |
| 1353 | tmp = I915_READ(GEN8_GT_IIR(0)); |
| 1354 | if (tmp) { |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 1355 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1356 | ret = IRQ_HANDLED; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1357 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1358 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1359 | ring = &dev_priv->ring[RCS]; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1360 | if (rcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1361 | notify_ring(dev, ring); |
| 1362 | if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) |
| 1363 | intel_execlists_handle_ctx_events(ring); |
| 1364 | |
| 1365 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; |
| 1366 | ring = &dev_priv->ring[BCS]; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1367 | if (bcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1368 | notify_ring(dev, ring); |
| 1369 | if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) |
| 1370 | intel_execlists_handle_ctx_events(ring); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1371 | } else |
| 1372 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); |
| 1373 | } |
| 1374 | |
Zhao Yakui | 85f9b5f | 2014-04-17 10:37:38 +0800 | [diff] [blame] | 1375 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1376 | tmp = I915_READ(GEN8_GT_IIR(1)); |
| 1377 | if (tmp) { |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 1378 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1379 | ret = IRQ_HANDLED; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1380 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1381 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1382 | ring = &dev_priv->ring[VCS]; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1383 | if (vcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1384 | notify_ring(dev, ring); |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1385 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1386 | intel_execlists_handle_ctx_events(ring); |
| 1387 | |
Zhao Yakui | 85f9b5f | 2014-04-17 10:37:38 +0800 | [diff] [blame] | 1388 | vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1389 | ring = &dev_priv->ring[VCS2]; |
Zhao Yakui | 85f9b5f | 2014-04-17 10:37:38 +0800 | [diff] [blame] | 1390 | if (vcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1391 | notify_ring(dev, ring); |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1392 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1393 | intel_execlists_handle_ctx_events(ring); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1394 | } else |
| 1395 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
| 1396 | } |
| 1397 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1398 | if (master_ctl & GEN8_GT_PM_IRQ) { |
| 1399 | tmp = I915_READ(GEN8_GT_IIR(2)); |
| 1400 | if (tmp & dev_priv->pm_rps_events) { |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1401 | I915_WRITE(GEN8_GT_IIR(2), |
| 1402 | tmp & dev_priv->pm_rps_events); |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 1403 | ret = IRQ_HANDLED; |
Imre Deak | c9a9a26 | 2014-11-05 20:48:37 +0200 | [diff] [blame] | 1404 | gen6_rps_irq_handler(dev_priv, tmp); |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 1405 | } else |
| 1406 | DRM_ERROR("The master control interrupt lied (PM)!\n"); |
| 1407 | } |
| 1408 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1409 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
| 1410 | tmp = I915_READ(GEN8_GT_IIR(3)); |
| 1411 | if (tmp) { |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 1412 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1413 | ret = IRQ_HANDLED; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1414 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1415 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1416 | ring = &dev_priv->ring[VECS]; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1417 | if (vcs & GT_RENDER_USER_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1418 | notify_ring(dev, ring); |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 1419 | if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) |
Thomas Daniel | e981e7b | 2014-07-24 17:04:39 +0100 | [diff] [blame] | 1420 | intel_execlists_handle_ctx_events(ring); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1421 | } else |
| 1422 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); |
| 1423 | } |
| 1424 | |
| 1425 | return ret; |
| 1426 | } |
| 1427 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1428 | #define HPD_STORM_DETECT_PERIOD 1000 |
| 1429 | #define HPD_STORM_THRESHOLD 5 |
| 1430 | |
Jani Nikula | 07c338c | 2014-10-02 11:16:32 +0300 | [diff] [blame] | 1431 | static int pch_port_to_hotplug_shift(enum port port) |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1432 | { |
| 1433 | switch (port) { |
| 1434 | case PORT_A: |
| 1435 | case PORT_E: |
| 1436 | default: |
| 1437 | return -1; |
| 1438 | case PORT_B: |
| 1439 | return 0; |
| 1440 | case PORT_C: |
| 1441 | return 8; |
| 1442 | case PORT_D: |
| 1443 | return 16; |
| 1444 | } |
| 1445 | } |
| 1446 | |
Jani Nikula | 07c338c | 2014-10-02 11:16:32 +0300 | [diff] [blame] | 1447 | static int i915_port_to_hotplug_shift(enum port port) |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1448 | { |
| 1449 | switch (port) { |
| 1450 | case PORT_A: |
| 1451 | case PORT_E: |
| 1452 | default: |
| 1453 | return -1; |
| 1454 | case PORT_B: |
| 1455 | return 17; |
| 1456 | case PORT_C: |
| 1457 | return 19; |
| 1458 | case PORT_D: |
| 1459 | return 21; |
| 1460 | } |
| 1461 | } |
| 1462 | |
| 1463 | static inline enum port get_port_from_pin(enum hpd_pin pin) |
| 1464 | { |
| 1465 | switch (pin) { |
| 1466 | case HPD_PORT_B: |
| 1467 | return PORT_B; |
| 1468 | case HPD_PORT_C: |
| 1469 | return PORT_C; |
| 1470 | case HPD_PORT_D: |
| 1471 | return PORT_D; |
| 1472 | default: |
| 1473 | return PORT_A; /* no hpd */ |
| 1474 | } |
| 1475 | } |
| 1476 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1477 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
Daniel Vetter | 22062db | 2013-06-27 17:52:11 +0200 | [diff] [blame] | 1478 | u32 hotplug_trigger, |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1479 | u32 dig_hotplug_reg, |
Daniel Vetter | 22062db | 2013-06-27 17:52:11 +0200 | [diff] [blame] | 1480 | const u32 *hpd) |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1481 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1482 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1483 | int i; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1484 | enum port port; |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1485 | bool storm_detected = false; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1486 | bool queue_dig = false, queue_hp = false; |
| 1487 | u32 dig_shift; |
| 1488 | u32 dig_port_mask = 0; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1489 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1490 | if (!hotplug_trigger) |
| 1491 | return; |
| 1492 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1493 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n", |
| 1494 | hotplug_trigger, dig_hotplug_reg); |
Imre Deak | cc9bd49 | 2014-01-16 19:56:54 +0200 | [diff] [blame] | 1495 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1496 | spin_lock(&dev_priv->irq_lock); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1497 | for (i = 1; i < HPD_NUM_PINS; i++) { |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1498 | if (!(hpd[i] & hotplug_trigger)) |
| 1499 | continue; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 1500 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1501 | port = get_port_from_pin(i); |
| 1502 | if (port && dev_priv->hpd_irq_port[port]) { |
| 1503 | bool long_hpd; |
| 1504 | |
Jani Nikula | 07c338c | 2014-10-02 11:16:32 +0300 | [diff] [blame] | 1505 | if (HAS_PCH_SPLIT(dev)) { |
| 1506 | dig_shift = pch_port_to_hotplug_shift(port); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1507 | long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
Jani Nikula | 07c338c | 2014-10-02 11:16:32 +0300 | [diff] [blame] | 1508 | } else { |
| 1509 | dig_shift = i915_port_to_hotplug_shift(port); |
| 1510 | long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1511 | } |
| 1512 | |
Ville Syrjälä | 26fbb77 | 2014-08-11 18:37:37 +0300 | [diff] [blame] | 1513 | DRM_DEBUG_DRIVER("digital hpd port %c - %s\n", |
| 1514 | port_name(port), |
| 1515 | long_hpd ? "long" : "short"); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1516 | /* for long HPD pulses we want to have the digital queue happen, |
| 1517 | but we still want HPD storm detection to function. */ |
| 1518 | if (long_hpd) { |
| 1519 | dev_priv->long_hpd_port_mask |= (1 << port); |
| 1520 | dig_port_mask |= hpd[i]; |
| 1521 | } else { |
| 1522 | /* for short HPD just trigger the digital queue */ |
| 1523 | dev_priv->short_hpd_port_mask |= (1 << port); |
| 1524 | hotplug_trigger &= ~hpd[i]; |
| 1525 | } |
| 1526 | queue_dig = true; |
| 1527 | } |
| 1528 | } |
| 1529 | |
| 1530 | for (i = 1; i < HPD_NUM_PINS; i++) { |
Daniel Vetter | 3ff04a16 | 2014-04-24 12:03:17 +0200 | [diff] [blame] | 1531 | if (hpd[i] & hotplug_trigger && |
| 1532 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { |
| 1533 | /* |
| 1534 | * On GMCH platforms the interrupt mask bits only |
| 1535 | * prevent irq generation, not the setting of the |
| 1536 | * hotplug bits itself. So only WARN about unexpected |
| 1537 | * interrupts on saner platforms. |
| 1538 | */ |
| 1539 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), |
| 1540 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", |
| 1541 | hotplug_trigger, i, hpd[i]); |
| 1542 | |
| 1543 | continue; |
| 1544 | } |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1545 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1546 | if (!(hpd[i] & hotplug_trigger) || |
| 1547 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) |
| 1548 | continue; |
| 1549 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1550 | if (!(dig_port_mask & hpd[i])) { |
| 1551 | dev_priv->hpd_event_bits |= (1 << i); |
| 1552 | queue_hp = true; |
| 1553 | } |
| 1554 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1555 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
| 1556 | dev_priv->hpd_stats[i].hpd_last_jiffies |
| 1557 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { |
| 1558 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; |
| 1559 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1560 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1561 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
| 1562 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1563 | dev_priv->hpd_event_bits &= ~(1 << i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1564 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1565 | storm_detected = true; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1566 | } else { |
| 1567 | dev_priv->hpd_stats[i].hpd_cnt++; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1568 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
| 1569 | dev_priv->hpd_stats[i].hpd_cnt); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1570 | } |
| 1571 | } |
| 1572 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1573 | if (storm_detected) |
| 1574 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1575 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 5876fa0 | 2013-06-27 17:52:13 +0200 | [diff] [blame] | 1576 | |
Daniel Vetter | 645416f | 2013-09-02 16:22:25 +0200 | [diff] [blame] | 1577 | /* |
| 1578 | * Our hotplug handler can grab modeset locks (by calling down into the |
| 1579 | * fb helpers). Hence it must not be run on our own dev-priv->wq work |
| 1580 | * queue for otherwise the flush_work in the pageflip code will |
| 1581 | * deadlock. |
| 1582 | */ |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1583 | if (queue_dig) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1584 | queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1585 | if (queue_hp) |
| 1586 | schedule_work(&dev_priv->hotplug_work); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1587 | } |
| 1588 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1589 | static void gmbus_irq_handler(struct drm_device *dev) |
| 1590 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1591 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1592 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1593 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1594 | } |
| 1595 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1596 | static void dp_aux_irq_handler(struct drm_device *dev) |
| 1597 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1598 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1599 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1600 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1601 | } |
| 1602 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1603 | #if defined(CONFIG_DEBUG_FS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1604 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
| 1605 | uint32_t crc0, uint32_t crc1, |
| 1606 | uint32_t crc2, uint32_t crc3, |
| 1607 | uint32_t crc4) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1608 | { |
| 1609 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1610 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
| 1611 | struct intel_pipe_crc_entry *entry; |
Damien Lespiau | ac2300d | 2013-10-15 18:55:30 +0100 | [diff] [blame] | 1612 | int head, tail; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1613 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1614 | spin_lock(&pipe_crc->lock); |
| 1615 | |
Damien Lespiau | 0c912c7 | 2013-10-15 18:55:37 +0100 | [diff] [blame] | 1616 | if (!pipe_crc->entries) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1617 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | 0c912c7 | 2013-10-15 18:55:37 +0100 | [diff] [blame] | 1618 | DRM_ERROR("spurious interrupt\n"); |
| 1619 | return; |
| 1620 | } |
| 1621 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1622 | head = pipe_crc->head; |
| 1623 | tail = pipe_crc->tail; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1624 | |
| 1625 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1626 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1627 | DRM_ERROR("CRC buffer overflowing\n"); |
| 1628 | return; |
| 1629 | } |
| 1630 | |
| 1631 | entry = &pipe_crc->entries[head]; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1632 | |
Daniel Vetter | 8bc5e95 | 2013-10-16 22:55:49 +0200 | [diff] [blame] | 1633 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1634 | entry->crc[0] = crc0; |
| 1635 | entry->crc[1] = crc1; |
| 1636 | entry->crc[2] = crc2; |
| 1637 | entry->crc[3] = crc3; |
| 1638 | entry->crc[4] = crc4; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1639 | |
| 1640 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1641 | pipe_crc->head = head; |
| 1642 | |
| 1643 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1644 | |
| 1645 | wake_up_interruptible(&pipe_crc->wq); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1646 | } |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1647 | #else |
| 1648 | static inline void |
| 1649 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
| 1650 | uint32_t crc0, uint32_t crc1, |
| 1651 | uint32_t crc2, uint32_t crc3, |
| 1652 | uint32_t crc4) {} |
| 1653 | #endif |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1654 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1655 | |
| 1656 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1657 | { |
| 1658 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1659 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1660 | display_pipe_crc_irq_handler(dev, pipe, |
| 1661 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
| 1662 | 0, 0, 0, 0); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1663 | } |
| 1664 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1665 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1666 | { |
| 1667 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1668 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1669 | display_pipe_crc_irq_handler(dev, pipe, |
| 1670 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
| 1671 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), |
| 1672 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), |
| 1673 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), |
| 1674 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1675 | } |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1676 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1677 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1678 | { |
| 1679 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 0b5c5ed | 2013-10-16 22:55:53 +0200 | [diff] [blame] | 1680 | uint32_t res1, res2; |
| 1681 | |
| 1682 | if (INTEL_INFO(dev)->gen >= 3) |
| 1683 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
| 1684 | else |
| 1685 | res1 = 0; |
| 1686 | |
| 1687 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
| 1688 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
| 1689 | else |
| 1690 | res2 = 0; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1691 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1692 | display_pipe_crc_irq_handler(dev, pipe, |
| 1693 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
| 1694 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), |
| 1695 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), |
| 1696 | res1, res2); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1697 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1698 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1699 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
| 1700 | * IMR bits until the work is done. Other interrupts can be processed without |
| 1701 | * the work queue. */ |
| 1702 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1703 | { |
Imre Deak | 4a74de8 | 2014-11-19 15:30:01 +0200 | [diff] [blame] | 1704 | /* TODO: RPS on GEN9+ is not supported yet. */ |
| 1705 | if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9, |
| 1706 | "GEN9+: unexpected RPS IRQ\n")) |
Imre Deak | 132f3f1 | 2014-11-10 15:34:33 +0200 | [diff] [blame] | 1707 | return; |
| 1708 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1709 | if (pm_iir & dev_priv->pm_rps_events) { |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1710 | spin_lock(&dev_priv->irq_lock); |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 1711 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1712 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1713 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 2adbee6 | 2013-07-04 23:35:27 +0200 | [diff] [blame] | 1714 | |
| 1715 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1716 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1717 | |
Imre Deak | c9a9a26 | 2014-11-05 20:48:37 +0200 | [diff] [blame] | 1718 | if (INTEL_INFO(dev_priv)->gen >= 8) |
| 1719 | return; |
| 1720 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1721 | if (HAS_VEBOX(dev_priv->dev)) { |
| 1722 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
| 1723 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1724 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1725 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 1726 | i915_handle_error(dev_priv->dev, false, |
| 1727 | "VEBOX CS error interrupt 0x%08x", |
| 1728 | pm_iir); |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1729 | } |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1730 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1731 | } |
| 1732 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 1733 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
| 1734 | { |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 1735 | if (!drm_handle_vblank(dev, pipe)) |
| 1736 | return false; |
| 1737 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 1738 | return true; |
| 1739 | } |
| 1740 | |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1741 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
| 1742 | { |
| 1743 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1744 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1745 | int pipe; |
| 1746 | |
Imre Deak | 58ead0d | 2014-02-04 21:35:47 +0200 | [diff] [blame] | 1747 | spin_lock(&dev_priv->irq_lock); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 1748 | for_each_pipe(dev_priv, pipe) { |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1749 | int reg; |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1750 | u32 mask, iir_bit = 0; |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1751 | |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1752 | /* |
| 1753 | * PIPESTAT bits get signalled even when the interrupt is |
| 1754 | * disabled with the mask bits, and some of the status bits do |
| 1755 | * not generate interrupts at all (like the underrun bit). Hence |
| 1756 | * we need to be careful that we only handle what we want to |
| 1757 | * handle. |
| 1758 | */ |
Daniel Vetter | 0f239f4 | 2014-09-30 10:56:49 +0200 | [diff] [blame] | 1759 | |
| 1760 | /* fifo underruns are filterered in the underrun handler. */ |
| 1761 | mask = PIPE_FIFO_UNDERRUN_STATUS; |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1762 | |
| 1763 | switch (pipe) { |
| 1764 | case PIPE_A: |
| 1765 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; |
| 1766 | break; |
| 1767 | case PIPE_B: |
| 1768 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
| 1769 | break; |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 1770 | case PIPE_C: |
| 1771 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
| 1772 | break; |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1773 | } |
| 1774 | if (iir & iir_bit) |
| 1775 | mask |= dev_priv->pipestat_irq_mask[pipe]; |
| 1776 | |
| 1777 | if (!mask) |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1778 | continue; |
| 1779 | |
| 1780 | reg = PIPESTAT(pipe); |
Daniel Vetter | bbb5eeb | 2014-02-12 17:55:36 +0100 | [diff] [blame] | 1781 | mask |= PIPESTAT_INT_ENABLE_MASK; |
| 1782 | pipe_stats[pipe] = I915_READ(reg) & mask; |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1783 | |
| 1784 | /* |
| 1785 | * Clear the PIPE*STAT regs before the IIR |
| 1786 | */ |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1787 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
| 1788 | PIPESTAT_INT_STATUS_MASK)) |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1789 | I915_WRITE(reg, pipe_stats[pipe]); |
| 1790 | } |
Imre Deak | 58ead0d | 2014-02-04 21:35:47 +0200 | [diff] [blame] | 1791 | spin_unlock(&dev_priv->irq_lock); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1792 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 1793 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 1794 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
| 1795 | intel_pipe_handle_vblank(dev, pipe)) |
| 1796 | intel_check_page_flip(dev, pipe); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1797 | |
Imre Deak | 579a9b0 | 2014-02-04 21:35:48 +0200 | [diff] [blame] | 1798 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1799 | intel_prepare_page_flip(dev, pipe); |
| 1800 | intel_finish_page_flip(dev, pipe); |
| 1801 | } |
| 1802 | |
| 1803 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
| 1804 | i9xx_pipe_crc_irq_handler(dev, pipe); |
| 1805 | |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 1806 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 1807 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
Imre Deak | c1874ed | 2014-02-04 21:35:46 +0200 | [diff] [blame] | 1808 | } |
| 1809 | |
| 1810 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 1811 | gmbus_irq_handler(dev); |
| 1812 | } |
| 1813 | |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 1814 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
| 1815 | { |
| 1816 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1817 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 1818 | |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1819 | if (hotplug_status) { |
| 1820 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 1821 | /* |
| 1822 | * Make sure hotplug status is cleared before we clear IIR, or else we |
| 1823 | * may miss hotplug events. |
| 1824 | */ |
| 1825 | POSTING_READ(PORT_HOTPLUG_STAT); |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 1826 | |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1827 | if (IS_G4X(dev)) { |
| 1828 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 1829 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1830 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1831 | } else { |
| 1832 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
| 1833 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1834 | intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1835 | } |
| 1836 | |
| 1837 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && |
| 1838 | hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) |
| 1839 | dp_aux_irq_handler(dev); |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 1840 | } |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 1841 | } |
| 1842 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 1843 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1844 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 1845 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1846 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1847 | u32 iir, gt_iir, pm_iir; |
| 1848 | irqreturn_t ret = IRQ_NONE; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1849 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1850 | while (true) { |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1851 | /* Find, clear, then process each source of interrupt */ |
| 1852 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1853 | gt_iir = I915_READ(GTIIR); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1854 | if (gt_iir) |
| 1855 | I915_WRITE(GTIIR, gt_iir); |
| 1856 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1857 | pm_iir = I915_READ(GEN6_PMIIR); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1858 | if (pm_iir) |
| 1859 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 1860 | |
| 1861 | iir = I915_READ(VLV_IIR); |
| 1862 | if (iir) { |
| 1863 | /* Consume port before clearing IIR or we'll miss events */ |
| 1864 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
| 1865 | i9xx_hpd_irq_handler(dev); |
| 1866 | I915_WRITE(VLV_IIR, iir); |
| 1867 | } |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1868 | |
| 1869 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) |
| 1870 | goto out; |
| 1871 | |
| 1872 | ret = IRQ_HANDLED; |
| 1873 | |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1874 | if (gt_iir) |
| 1875 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 1876 | if (pm_iir) |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1877 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Oscar Mateo | 3ff60f8 | 2014-06-16 16:10:58 +0100 | [diff] [blame] | 1878 | /* Call regardless, as some status bits might not be |
| 1879 | * signalled in iir */ |
| 1880 | valleyview_pipestat_irq_handler(dev, iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1881 | } |
| 1882 | |
| 1883 | out: |
| 1884 | return ret; |
| 1885 | } |
| 1886 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1887 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
| 1888 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 1889 | struct drm_device *dev = arg; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1890 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1891 | u32 master_ctl, iir; |
| 1892 | irqreturn_t ret = IRQ_NONE; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1893 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 1894 | for (;;) { |
| 1895 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
| 1896 | iir = I915_READ(VLV_IIR); |
Ville Syrjälä | 3278f67 | 2014-04-09 13:28:49 +0300 | [diff] [blame] | 1897 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 1898 | if (master_ctl == 0 && iir == 0) |
| 1899 | break; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1900 | |
Oscar Mateo | 27b6c12 | 2014-06-16 16:11:00 +0100 | [diff] [blame] | 1901 | ret = IRQ_HANDLED; |
| 1902 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 1903 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1904 | |
Oscar Mateo | 27b6c12 | 2014-06-16 16:11:00 +0100 | [diff] [blame] | 1905 | /* Find, clear, then process each source of interrupt */ |
| 1906 | |
| 1907 | if (iir) { |
| 1908 | /* Consume port before clearing IIR or we'll miss events */ |
| 1909 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
| 1910 | i9xx_hpd_irq_handler(dev); |
| 1911 | I915_WRITE(VLV_IIR, iir); |
| 1912 | } |
| 1913 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 1914 | gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1915 | |
Oscar Mateo | 27b6c12 | 2014-06-16 16:11:00 +0100 | [diff] [blame] | 1916 | /* Call regardless, as some status bits might not be |
| 1917 | * signalled in iir */ |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 1918 | valleyview_pipestat_irq_handler(dev, iir); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1919 | |
Ville Syrjälä | 8e5fd59 | 2014-04-09 13:28:50 +0300 | [diff] [blame] | 1920 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
| 1921 | POSTING_READ(GEN8_MASTER_IRQ); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1922 | } |
| 1923 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 1924 | return ret; |
| 1925 | } |
| 1926 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1927 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1928 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 1929 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1930 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1931 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1932 | u32 dig_hotplug_reg; |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1933 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 1934 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
| 1935 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
| 1936 | |
| 1937 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1938 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1939 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
| 1940 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> |
| 1941 | SDE_AUDIO_POWER_SHIFT); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1942 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1943 | port_name(port)); |
| 1944 | } |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1945 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1946 | if (pch_iir & SDE_AUX_MASK) |
| 1947 | dp_aux_irq_handler(dev); |
| 1948 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1949 | if (pch_iir & SDE_GMBUS) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1950 | gmbus_irq_handler(dev); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1951 | |
| 1952 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
| 1953 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
| 1954 | |
| 1955 | if (pch_iir & SDE_AUDIO_TRANS_MASK) |
| 1956 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); |
| 1957 | |
| 1958 | if (pch_iir & SDE_POISON) |
| 1959 | DRM_ERROR("PCH poison interrupt\n"); |
| 1960 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1961 | if (pch_iir & SDE_FDI_MASK) |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 1962 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1963 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 1964 | pipe_name(pipe), |
| 1965 | I915_READ(FDI_RX_IIR(pipe))); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1966 | |
| 1967 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) |
| 1968 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); |
| 1969 | |
| 1970 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) |
| 1971 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); |
| 1972 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1973 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 1974 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1975 | |
| 1976 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 1977 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1978 | } |
| 1979 | |
| 1980 | static void ivb_err_int_handler(struct drm_device *dev) |
| 1981 | { |
| 1982 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1983 | u32 err_int = I915_READ(GEN7_ERR_INT); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1984 | enum pipe pipe; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1985 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 1986 | if (err_int & ERR_INT_POISON) |
| 1987 | DRM_ERROR("Poison interrupt\n"); |
| 1988 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 1989 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 1990 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
| 1991 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1992 | |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1993 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
| 1994 | if (IS_IVYBRIDGE(dev)) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1995 | ivb_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1996 | else |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1997 | hsw_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1998 | } |
| 1999 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2000 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2001 | I915_WRITE(GEN7_ERR_INT, err_int); |
| 2002 | } |
| 2003 | |
| 2004 | static void cpt_serr_int_handler(struct drm_device *dev) |
| 2005 | { |
| 2006 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2007 | u32 serr_int = I915_READ(SERR_INT); |
| 2008 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 2009 | if (serr_int & SERR_INT_POISON) |
| 2010 | DRM_ERROR("PCH poison interrupt\n"); |
| 2011 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2012 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 2013 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2014 | |
| 2015 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 2016 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2017 | |
| 2018 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 2019 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2020 | |
| 2021 | I915_WRITE(SERR_INT, serr_int); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 2022 | } |
| 2023 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2024 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
| 2025 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2026 | struct drm_i915_private *dev_priv = dev->dev_private; |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2027 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 2028 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2029 | u32 dig_hotplug_reg; |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2030 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 2031 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
| 2032 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
| 2033 | |
| 2034 | intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2035 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 2036 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
| 2037 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> |
| 2038 | SDE_AUDIO_POWER_SHIFT_CPT); |
| 2039 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", |
| 2040 | port_name(port)); |
| 2041 | } |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2042 | |
| 2043 | if (pch_iir & SDE_AUX_MASK_CPT) |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 2044 | dp_aux_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2045 | |
| 2046 | if (pch_iir & SDE_GMBUS_CPT) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 2047 | gmbus_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2048 | |
| 2049 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) |
| 2050 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); |
| 2051 | |
| 2052 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) |
| 2053 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); |
| 2054 | |
| 2055 | if (pch_iir & SDE_FDI_MASK_CPT) |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2056 | for_each_pipe(dev_priv, pipe) |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2057 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 2058 | pipe_name(pipe), |
| 2059 | I915_READ(FDI_RX_IIR(pipe))); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2060 | |
| 2061 | if (pch_iir & SDE_ERROR_CPT) |
| 2062 | cpt_serr_int_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 2063 | } |
| 2064 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2065 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 2066 | { |
| 2067 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2068 | enum pipe pipe; |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2069 | |
| 2070 | if (de_iir & DE_AUX_CHANNEL_A) |
| 2071 | dp_aux_irq_handler(dev); |
| 2072 | |
| 2073 | if (de_iir & DE_GSE) |
| 2074 | intel_opregion_asle_intr(dev); |
| 2075 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2076 | if (de_iir & DE_POISON) |
| 2077 | DRM_ERROR("Poison interrupt\n"); |
| 2078 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2079 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 2080 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
| 2081 | intel_pipe_handle_vblank(dev, pipe)) |
| 2082 | intel_check_page_flip(dev, pipe); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2083 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2084 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 2085 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2086 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2087 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
| 2088 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2089 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2090 | /* plane/pipes map 1:1 on ilk+ */ |
| 2091 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { |
| 2092 | intel_prepare_page_flip(dev, pipe); |
| 2093 | intel_finish_page_flip_plane(dev, pipe); |
| 2094 | } |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 2095 | } |
| 2096 | |
| 2097 | /* check event from PCH */ |
| 2098 | if (de_iir & DE_PCH_EVENT) { |
| 2099 | u32 pch_iir = I915_READ(SDEIIR); |
| 2100 | |
| 2101 | if (HAS_PCH_CPT(dev)) |
| 2102 | cpt_irq_handler(dev, pch_iir); |
| 2103 | else |
| 2104 | ibx_irq_handler(dev, pch_iir); |
| 2105 | |
| 2106 | /* should clear PCH hotplug event before clear CPU irq */ |
| 2107 | I915_WRITE(SDEIIR, pch_iir); |
| 2108 | } |
| 2109 | |
| 2110 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
| 2111 | ironlake_rps_change_irq_handler(dev); |
| 2112 | } |
| 2113 | |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2114 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 2115 | { |
| 2116 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 2117 | enum pipe pipe; |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2118 | |
| 2119 | if (de_iir & DE_ERR_INT_IVB) |
| 2120 | ivb_err_int_handler(dev); |
| 2121 | |
| 2122 | if (de_iir & DE_AUX_CHANNEL_A_IVB) |
| 2123 | dp_aux_irq_handler(dev); |
| 2124 | |
| 2125 | if (de_iir & DE_GSE_IVB) |
| 2126 | intel_opregion_asle_intr(dev); |
| 2127 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2128 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 2129 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
| 2130 | intel_pipe_handle_vblank(dev, pipe)) |
| 2131 | intel_check_page_flip(dev, pipe); |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2132 | |
| 2133 | /* plane/pipes map 1:1 on ilk+ */ |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 2134 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
| 2135 | intel_prepare_page_flip(dev, pipe); |
| 2136 | intel_finish_page_flip_plane(dev, pipe); |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 2137 | } |
| 2138 | } |
| 2139 | |
| 2140 | /* check event from PCH */ |
| 2141 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { |
| 2142 | u32 pch_iir = I915_READ(SDEIIR); |
| 2143 | |
| 2144 | cpt_irq_handler(dev, pch_iir); |
| 2145 | |
| 2146 | /* clear PCH hotplug event before clear CPU irq */ |
| 2147 | I915_WRITE(SDEIIR, pch_iir); |
| 2148 | } |
| 2149 | } |
| 2150 | |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2151 | /* |
| 2152 | * To handle irqs with the minimum potential races with fresh interrupts, we: |
| 2153 | * 1 - Disable Master Interrupt Control. |
| 2154 | * 2 - Find the source(s) of the interrupt. |
| 2155 | * 3 - Clear the Interrupt Identity bits (IIR). |
| 2156 | * 4 - Process the interrupt(s) that had bits set in the IIRs. |
| 2157 | * 5 - Re-enable Master Interrupt Control. |
| 2158 | */ |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2159 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2160 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 2161 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2162 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2163 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2164 | irqreturn_t ret = IRQ_NONE; |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2165 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2166 | /* We get interrupts on unclaimed registers, so check for this before we |
| 2167 | * do any I915_{READ,WRITE}. */ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 2168 | intel_uncore_check_errors(dev); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2169 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2170 | /* disable master interrupt before clearing iir */ |
| 2171 | de_ier = I915_READ(DEIER); |
| 2172 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Paulo Zanoni | 23a7851 | 2013-07-12 16:35:14 -0300 | [diff] [blame] | 2173 | POSTING_READ(DEIER); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2174 | |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 2175 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
| 2176 | * interrupts will will be stored on its back queue, and then we'll be |
| 2177 | * able to process them after we restore SDEIER (as soon as we restore |
| 2178 | * it, we'll get an interrupt if SDEIIR still has something to process |
| 2179 | * due to its back queue). */ |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2180 | if (!HAS_PCH_NOP(dev)) { |
| 2181 | sde_ier = I915_READ(SDEIER); |
| 2182 | I915_WRITE(SDEIER, 0); |
| 2183 | POSTING_READ(SDEIER); |
| 2184 | } |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 2185 | |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2186 | /* Find, clear, then process each source of interrupt */ |
| 2187 | |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2188 | gt_iir = I915_READ(GTIIR); |
| 2189 | if (gt_iir) { |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2190 | I915_WRITE(GTIIR, gt_iir); |
| 2191 | ret = IRQ_HANDLED; |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 2192 | if (INTEL_INFO(dev)->gen >= 6) |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2193 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 2194 | else |
| 2195 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2196 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2197 | |
| 2198 | de_iir = I915_READ(DEIIR); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2199 | if (de_iir) { |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2200 | I915_WRITE(DEIIR, de_iir); |
| 2201 | ret = IRQ_HANDLED; |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2202 | if (INTEL_INFO(dev)->gen >= 7) |
| 2203 | ivb_display_irq_handler(dev, de_iir); |
| 2204 | else |
| 2205 | ilk_display_irq_handler(dev, de_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 2206 | } |
| 2207 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2208 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2209 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
| 2210 | if (pm_iir) { |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2211 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 2212 | ret = IRQ_HANDLED; |
Oscar Mateo | 72c90f6 | 2014-06-16 16:10:57 +0100 | [diff] [blame] | 2213 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 2214 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2215 | } |
| 2216 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2217 | I915_WRITE(DEIER, de_ier); |
| 2218 | POSTING_READ(DEIER); |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2219 | if (!HAS_PCH_NOP(dev)) { |
| 2220 | I915_WRITE(SDEIER, sde_ier); |
| 2221 | POSTING_READ(SDEIER); |
| 2222 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2223 | |
| 2224 | return ret; |
| 2225 | } |
| 2226 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2227 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
| 2228 | { |
| 2229 | struct drm_device *dev = arg; |
| 2230 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2231 | u32 master_ctl; |
| 2232 | irqreturn_t ret = IRQ_NONE; |
| 2233 | uint32_t tmp = 0; |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2234 | enum pipe pipe; |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 2235 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
| 2236 | |
| 2237 | if (IS_GEN9(dev)) |
| 2238 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
| 2239 | GEN9_AUX_CHANNEL_D; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2240 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2241 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
| 2242 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
| 2243 | if (!master_ctl) |
| 2244 | return IRQ_NONE; |
| 2245 | |
| 2246 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 2247 | POSTING_READ(GEN8_MASTER_IRQ); |
| 2248 | |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2249 | /* Find, clear, then process each source of interrupt */ |
| 2250 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2251 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
| 2252 | |
| 2253 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
| 2254 | tmp = I915_READ(GEN8_DE_MISC_IIR); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2255 | if (tmp) { |
| 2256 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); |
| 2257 | ret = IRQ_HANDLED; |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2258 | if (tmp & GEN8_DE_MISC_GSE) |
| 2259 | intel_opregion_asle_intr(dev); |
| 2260 | else |
| 2261 | DRM_ERROR("Unexpected DE Misc interrupt\n"); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2262 | } |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2263 | else |
| 2264 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2265 | } |
| 2266 | |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2267 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
| 2268 | tmp = I915_READ(GEN8_DE_PORT_IIR); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2269 | if (tmp) { |
| 2270 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); |
| 2271 | ret = IRQ_HANDLED; |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 2272 | |
| 2273 | if (tmp & aux_mask) |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2274 | dp_aux_irq_handler(dev); |
| 2275 | else |
| 2276 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2277 | } |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2278 | else |
| 2279 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2280 | } |
| 2281 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2282 | for_each_pipe(dev_priv, pipe) { |
Damien Lespiau | 770de83 | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 2283 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2284 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2285 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
| 2286 | continue; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2287 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2288 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2289 | if (pipe_iir) { |
| 2290 | ret = IRQ_HANDLED; |
| 2291 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); |
Damien Lespiau | 770de83 | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 2292 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 2293 | if (pipe_iir & GEN8_PIPE_VBLANK && |
| 2294 | intel_pipe_handle_vblank(dev, pipe)) |
| 2295 | intel_check_page_flip(dev, pipe); |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2296 | |
Damien Lespiau | 770de83 | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 2297 | if (IS_GEN9(dev)) |
| 2298 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; |
| 2299 | else |
| 2300 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; |
| 2301 | |
| 2302 | if (flip_done) { |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2303 | intel_prepare_page_flip(dev, pipe); |
| 2304 | intel_finish_page_flip_plane(dev, pipe); |
| 2305 | } |
| 2306 | |
| 2307 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
| 2308 | hsw_pipe_crc_irq_handler(dev, pipe); |
| 2309 | |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 2310 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
| 2311 | intel_cpu_fifo_underrun_irq_handler(dev_priv, |
| 2312 | pipe); |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2313 | |
Damien Lespiau | 770de83 | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 2314 | |
| 2315 | if (IS_GEN9(dev)) |
| 2316 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; |
| 2317 | else |
| 2318 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
| 2319 | |
| 2320 | if (fault_errors) |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2321 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
| 2322 | pipe_name(pipe), |
| 2323 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 2324 | } else |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2325 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
| 2326 | } |
| 2327 | |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2328 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
| 2329 | /* |
| 2330 | * FIXME(BDW): Assume for now that the new interrupt handling |
| 2331 | * scheme also closed the SDE interrupt handling race we've seen |
| 2332 | * on older pch-split platforms. But this needs testing. |
| 2333 | */ |
| 2334 | u32 pch_iir = I915_READ(SDEIIR); |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2335 | if (pch_iir) { |
| 2336 | I915_WRITE(SDEIIR, pch_iir); |
| 2337 | ret = IRQ_HANDLED; |
Oscar Mateo | 38cc46d | 2014-06-16 16:10:59 +0100 | [diff] [blame] | 2338 | cpt_irq_handler(dev, pch_iir); |
| 2339 | } else |
| 2340 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); |
| 2341 | |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 2342 | } |
| 2343 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2344 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
| 2345 | POSTING_READ(GEN8_MASTER_IRQ); |
| 2346 | |
| 2347 | return ret; |
| 2348 | } |
| 2349 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2350 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
| 2351 | bool reset_completed) |
| 2352 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2353 | struct intel_engine_cs *ring; |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2354 | int i; |
| 2355 | |
| 2356 | /* |
| 2357 | * Notify all waiters for GPU completion events that reset state has |
| 2358 | * been changed, and that they need to restart their wait after |
| 2359 | * checking for potential errors (and bail out to drop locks if there is |
| 2360 | * a gpu reset pending so that i915_error_work_func can acquire them). |
| 2361 | */ |
| 2362 | |
| 2363 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ |
| 2364 | for_each_ring(ring, dev_priv, i) |
| 2365 | wake_up_all(&ring->irq_queue); |
| 2366 | |
| 2367 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ |
| 2368 | wake_up_all(&dev_priv->pending_flip_queue); |
| 2369 | |
| 2370 | /* |
| 2371 | * Signal tasks blocked in i915_gem_wait_for_error that the pending |
| 2372 | * reset state is cleared. |
| 2373 | */ |
| 2374 | if (reset_completed) |
| 2375 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
| 2376 | } |
| 2377 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2378 | /** |
| 2379 | * i915_error_work_func - do process context error handling work |
| 2380 | * @work: work struct |
| 2381 | * |
| 2382 | * Fire an error uevent so userspace can see that a hang or error |
| 2383 | * was detected. |
| 2384 | */ |
| 2385 | static void i915_error_work_func(struct work_struct *work) |
| 2386 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2387 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
| 2388 | work); |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2389 | struct drm_i915_private *dev_priv = |
| 2390 | container_of(error, struct drm_i915_private, gpu_error); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2391 | struct drm_device *dev = dev_priv->dev; |
Ben Widawsky | cce723e | 2013-07-19 09:16:42 -0700 | [diff] [blame] | 2392 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
| 2393 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; |
| 2394 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2395 | int ret; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2396 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 2397 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2398 | |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 2399 | /* |
| 2400 | * Note that there's only one work item which does gpu resets, so we |
| 2401 | * need not worry about concurrent gpu resets potentially incrementing |
| 2402 | * error->reset_counter twice. We only need to take care of another |
| 2403 | * racing irq/hangcheck declaring the gpu dead for a second time. A |
| 2404 | * quick check for that is good enough: schedule_work ensures the |
| 2405 | * correct ordering between hang detection and this work item, and since |
| 2406 | * the reset in-progress bit is only ever set by code outside of this |
| 2407 | * work we don't need to worry about any other races. |
| 2408 | */ |
| 2409 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 2410 | DRM_DEBUG_DRIVER("resetting chip\n"); |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 2411 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 2412 | reset_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2413 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2414 | /* |
Imre Deak | f454c69 | 2014-04-23 01:09:04 +0300 | [diff] [blame] | 2415 | * In most cases it's guaranteed that we get here with an RPM |
| 2416 | * reference held, for example because there is a pending GPU |
| 2417 | * request that won't finish until the reset is done. This |
| 2418 | * isn't the case at least when we get here by doing a |
| 2419 | * simulated reset via debugs, so get an RPM reference. |
| 2420 | */ |
| 2421 | intel_runtime_pm_get(dev_priv); |
| 2422 | /* |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2423 | * All state reset _must_ be completed before we update the |
| 2424 | * reset counter, for otherwise waiters might miss the reset |
| 2425 | * pending state and not properly drop locks, resulting in |
| 2426 | * deadlocks with the reset work. |
| 2427 | */ |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2428 | ret = i915_reset(dev); |
| 2429 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2430 | intel_display_handle_reset(dev); |
| 2431 | |
Imre Deak | f454c69 | 2014-04-23 01:09:04 +0300 | [diff] [blame] | 2432 | intel_runtime_pm_put(dev_priv); |
| 2433 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2434 | if (ret == 0) { |
| 2435 | /* |
| 2436 | * After all the gem state is reset, increment the reset |
| 2437 | * counter and wake up everyone waiting for the reset to |
| 2438 | * complete. |
| 2439 | * |
| 2440 | * Since unlock operations are a one-sided barrier only, |
| 2441 | * we need to insert a barrier here to order any seqno |
| 2442 | * updates before |
| 2443 | * the counter increment. |
| 2444 | */ |
Peter Zijlstra | 4e857c5 | 2014-03-17 18:06:10 +0100 | [diff] [blame] | 2445 | smp_mb__before_atomic(); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2446 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
| 2447 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 2448 | kobject_uevent_env(&dev->primary->kdev->kobj, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2449 | KOBJ_CHANGE, reset_done_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2450 | } else { |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 2451 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 2452 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2453 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2454 | /* |
| 2455 | * Note: The wake_up also serves as a memory barrier so that |
| 2456 | * waiters see the update value of the reset counter atomic_t. |
| 2457 | */ |
| 2458 | i915_error_wake_up(dev_priv, true); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 2459 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2460 | } |
| 2461 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2462 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2463 | { |
| 2464 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 2465 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2466 | u32 eir = I915_READ(EIR); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2467 | int pipe, i; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2468 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2469 | if (!eir) |
| 2470 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2471 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2472 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2473 | |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 2474 | i915_get_extra_instdone(dev, instdone); |
| 2475 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2476 | if (IS_G4X(dev)) { |
| 2477 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 2478 | u32 ipeir = I915_READ(IPEIR_I965); |
| 2479 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2480 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 2481 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2482 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 2483 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2484 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2485 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2486 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2487 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2488 | } |
| 2489 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 2490 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2491 | pr_err("page table error\n"); |
| 2492 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2493 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2494 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2495 | } |
| 2496 | } |
| 2497 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2498 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2499 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 2500 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2501 | pr_err("page table error\n"); |
| 2502 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2503 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2504 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2505 | } |
| 2506 | } |
| 2507 | |
| 2508 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2509 | pr_err("memory refresh error:\n"); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 2510 | for_each_pipe(dev_priv, pipe) |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2511 | pr_err("pipe %c stat: 0x%08x\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2512 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2513 | /* pipestat has already been acked */ |
| 2514 | } |
| 2515 | if (eir & I915_ERROR_INSTRUCTION) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2516 | pr_err("instruction error\n"); |
| 2517 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2518 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 2519 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2520 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2521 | u32 ipeir = I915_READ(IPEIR); |
| 2522 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2523 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
| 2524 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2525 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2526 | I915_WRITE(IPEIR, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2527 | POSTING_READ(IPEIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2528 | } else { |
| 2529 | u32 ipeir = I915_READ(IPEIR_I965); |
| 2530 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2531 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 2532 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2533 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2534 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2535 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2536 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2537 | } |
| 2538 | } |
| 2539 | |
| 2540 | I915_WRITE(EIR, eir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2541 | POSTING_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2542 | eir = I915_READ(EIR); |
| 2543 | if (eir) { |
| 2544 | /* |
| 2545 | * some errors might have become stuck, |
| 2546 | * mask them. |
| 2547 | */ |
| 2548 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 2549 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 2550 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2551 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2552 | } |
| 2553 | |
| 2554 | /** |
| 2555 | * i915_handle_error - handle an error interrupt |
| 2556 | * @dev: drm device |
| 2557 | * |
| 2558 | * Do some basic checking of regsiter state at error interrupt time and |
| 2559 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 2560 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 2561 | * so userspace knows something bad happened (should trigger collection |
| 2562 | * of a ring dump etc.). |
| 2563 | */ |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2564 | void i915_handle_error(struct drm_device *dev, bool wedged, |
| 2565 | const char *fmt, ...) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2566 | { |
| 2567 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2568 | va_list args; |
| 2569 | char error_msg[80]; |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2570 | |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2571 | va_start(args, fmt); |
| 2572 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); |
| 2573 | va_end(args); |
| 2574 | |
| 2575 | i915_capture_error_state(dev, wedged, error_msg); |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2576 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2577 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2578 | if (wedged) { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2579 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
| 2580 | &dev_priv->gpu_error.reset_counter); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2581 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2582 | /* |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2583 | * Wakeup waiting processes so that the reset work function |
| 2584 | * i915_error_work_func doesn't deadlock trying to grab various |
| 2585 | * locks. By bumping the reset counter first, the woken |
| 2586 | * processes will see a reset in progress and back off, |
| 2587 | * releasing their locks and then wait for the reset completion. |
| 2588 | * We must do this for _all_ gpu waiters that might hold locks |
| 2589 | * that the reset work needs to acquire. |
| 2590 | * |
| 2591 | * Note: The wake_up serves as the required memory barrier to |
| 2592 | * ensure that the waiters see the updated value of the reset |
| 2593 | * counter atomic_t. |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2594 | */ |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2595 | i915_error_wake_up(dev_priv, false); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2596 | } |
| 2597 | |
Daniel Vetter | 122f46b | 2013-09-04 17:36:14 +0200 | [diff] [blame] | 2598 | /* |
| 2599 | * Our reset work can grab modeset locks (since it needs to reset the |
| 2600 | * state of outstanding pagelips). Hence it must not be run on our own |
| 2601 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip |
| 2602 | * code will deadlock. |
| 2603 | */ |
| 2604 | schedule_work(&dev_priv->gpu_error.work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2605 | } |
| 2606 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 2607 | /* Called from drm generic code, passed 'crtc' which |
| 2608 | * we use as a pipe index |
| 2609 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2610 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2611 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2612 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2613 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 2614 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2615 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 2616 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2617 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2618 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2619 | if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2620 | i915_enable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2621 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2622 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2623 | i915_enable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2624 | PIPE_VBLANK_INTERRUPT_STATUS); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2625 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 2626 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2627 | return 0; |
| 2628 | } |
| 2629 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2630 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2631 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2632 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2633 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2634 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2635 | DE_PIPE_VBLANK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2636 | |
| 2637 | if (!i915_pipe_enabled(dev, pipe)) |
| 2638 | return -EINVAL; |
| 2639 | |
| 2640 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2641 | ironlake_enable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2642 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2643 | |
| 2644 | return 0; |
| 2645 | } |
| 2646 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2647 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
| 2648 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2649 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2650 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2651 | |
| 2652 | if (!i915_pipe_enabled(dev, pipe)) |
| 2653 | return -EINVAL; |
| 2654 | |
| 2655 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2656 | i915_enable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2657 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2658 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2659 | |
| 2660 | return 0; |
| 2661 | } |
| 2662 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2663 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
| 2664 | { |
| 2665 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2666 | unsigned long irqflags; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2667 | |
| 2668 | if (!i915_pipe_enabled(dev, pipe)) |
| 2669 | return -EINVAL; |
| 2670 | |
| 2671 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 7167d7c | 2013-11-07 11:05:45 +0100 | [diff] [blame] | 2672 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
| 2673 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 2674 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2675 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2676 | return 0; |
| 2677 | } |
| 2678 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 2679 | /* Called from drm generic code, passed 'crtc' which |
| 2680 | * we use as a pipe index |
| 2681 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2682 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2683 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2684 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2685 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2686 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2687 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2688 | i915_disable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2689 | PIPE_VBLANK_INTERRUPT_STATUS | |
| 2690 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2691 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2692 | } |
| 2693 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2694 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2695 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2696 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2697 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2698 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2699 | DE_PIPE_VBLANK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2700 | |
| 2701 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2702 | ironlake_disable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2703 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2704 | } |
| 2705 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2706 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
| 2707 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2708 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2709 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2710 | |
| 2711 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2712 | i915_disable_pipestat(dev_priv, pipe, |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2713 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2714 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2715 | } |
| 2716 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2717 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
| 2718 | { |
| 2719 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2720 | unsigned long irqflags; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2721 | |
| 2722 | if (!i915_pipe_enabled(dev, pipe)) |
| 2723 | return; |
| 2724 | |
| 2725 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 7167d7c | 2013-11-07 11:05:45 +0100 | [diff] [blame] | 2726 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
| 2727 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 2728 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2729 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2730 | } |
| 2731 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2732 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2733 | ring_last_seqno(struct intel_engine_cs *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2734 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2735 | return list_entry(ring->request_list.prev, |
| 2736 | struct drm_i915_gem_request, list)->seqno; |
| 2737 | } |
| 2738 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2739 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2740 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2741 | { |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2742 | return (list_empty(&ring->request_list) || |
| 2743 | i915_seqno_passed(seqno, ring_last_seqno(ring))); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2744 | } |
| 2745 | |
Daniel Vetter | a028c4b | 2014-03-15 00:08:56 +0100 | [diff] [blame] | 2746 | static bool |
| 2747 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) |
| 2748 | { |
| 2749 | if (INTEL_INFO(dev)->gen >= 8) { |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2750 | return (ipehr >> 23) == 0x1c; |
Daniel Vetter | a028c4b | 2014-03-15 00:08:56 +0100 | [diff] [blame] | 2751 | } else { |
| 2752 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; |
| 2753 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | |
| 2754 | MI_SEMAPHORE_REGISTER); |
| 2755 | } |
| 2756 | } |
| 2757 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2758 | static struct intel_engine_cs * |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2759 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 2760 | { |
| 2761 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2762 | struct intel_engine_cs *signaller; |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 2763 | int i; |
| 2764 | |
| 2765 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2766 | for_each_ring(signaller, dev_priv, i) { |
| 2767 | if (ring == signaller) |
| 2768 | continue; |
| 2769 | |
| 2770 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) |
| 2771 | return signaller; |
| 2772 | } |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 2773 | } else { |
| 2774 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; |
| 2775 | |
| 2776 | for_each_ring(signaller, dev_priv, i) { |
| 2777 | if(ring == signaller) |
| 2778 | continue; |
| 2779 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2780 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 2781 | return signaller; |
| 2782 | } |
| 2783 | } |
| 2784 | |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2785 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
| 2786 | ring->id, ipehr, offset); |
Daniel Vetter | 921d42e | 2014-03-18 10:26:04 +0100 | [diff] [blame] | 2787 | |
| 2788 | return NULL; |
| 2789 | } |
| 2790 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2791 | static struct intel_engine_cs * |
| 2792 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2793 | { |
| 2794 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2795 | u32 cmd, ipehr, head; |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2796 | u64 offset = 0; |
| 2797 | int i, backwards; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2798 | |
| 2799 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); |
Daniel Vetter | a028c4b | 2014-03-15 00:08:56 +0100 | [diff] [blame] | 2800 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2801 | return NULL; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2802 | |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2803 | /* |
| 2804 | * HEAD is likely pointing to the dword after the actual command, |
| 2805 | * so scan backwards until we find the MBOX. But limit it to just 3 |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2806 | * or 4 dwords depending on the semaphore wait command size. |
| 2807 | * Note that we don't care about ACTHD here since that might |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2808 | * point at at batch, and semaphores are always emitted into the |
| 2809 | * ringbuffer itself. |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2810 | */ |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2811 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2812 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2813 | |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2814 | for (i = backwards; i; --i) { |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2815 | /* |
| 2816 | * Be paranoid and presume the hw has gone off into the wild - |
| 2817 | * our ring is smaller than what the hardware (and hence |
| 2818 | * HEAD_ADDR) allows. Also handles wrap-around. |
| 2819 | */ |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2820 | head &= ring->buffer->size - 1; |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2821 | |
| 2822 | /* This here seems to blow up */ |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2823 | cmd = ioread32(ring->buffer->virtual_start + head); |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2824 | if (cmd == ipehr) |
| 2825 | break; |
| 2826 | |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2827 | head -= 4; |
| 2828 | } |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2829 | |
Daniel Vetter | 88fe429 | 2014-03-15 00:08:55 +0100 | [diff] [blame] | 2830 | if (!i) |
| 2831 | return NULL; |
| 2832 | |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2833 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
Rodrigo Vivi | a6cdb93 | 2014-06-30 09:53:39 -0700 | [diff] [blame] | 2834 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 2835 | offset = ioread32(ring->buffer->virtual_start + head + 12); |
| 2836 | offset <<= 32; |
| 2837 | offset = ioread32(ring->buffer->virtual_start + head + 8); |
| 2838 | } |
| 2839 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2840 | } |
| 2841 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2842 | static int semaphore_passed(struct intel_engine_cs *ring) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2843 | { |
| 2844 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2845 | struct intel_engine_cs *signaller; |
Chris Wilson | a0d036b | 2014-07-19 12:40:42 +0100 | [diff] [blame] | 2846 | u32 seqno; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2847 | |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 2848 | ring->hangcheck.deadlock++; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2849 | |
| 2850 | signaller = semaphore_waits_for(ring, &seqno); |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 2851 | if (signaller == NULL) |
| 2852 | return -1; |
| 2853 | |
| 2854 | /* Prevent pathological recursion due to driver bugs */ |
| 2855 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2856 | return -1; |
| 2857 | |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 2858 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
| 2859 | return 1; |
| 2860 | |
Chris Wilson | a0d036b | 2014-07-19 12:40:42 +0100 | [diff] [blame] | 2861 | /* cursory check for an unkickable deadlock */ |
| 2862 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && |
| 2863 | semaphore_passed(signaller) < 0) |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 2864 | return -1; |
| 2865 | |
| 2866 | return 0; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2867 | } |
| 2868 | |
| 2869 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) |
| 2870 | { |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2871 | struct intel_engine_cs *ring; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2872 | int i; |
| 2873 | |
| 2874 | for_each_ring(ring, dev_priv, i) |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 2875 | ring->hangcheck.deadlock = 0; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2876 | } |
| 2877 | |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 2878 | static enum intel_ring_hangcheck_action |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2879 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2880 | { |
| 2881 | struct drm_device *dev = ring->dev; |
| 2882 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2883 | u32 tmp; |
| 2884 | |
Mika Kuoppala | f260fe7 | 2014-08-05 17:16:26 +0300 | [diff] [blame] | 2885 | if (acthd != ring->hangcheck.acthd) { |
| 2886 | if (acthd > ring->hangcheck.max_acthd) { |
| 2887 | ring->hangcheck.max_acthd = acthd; |
| 2888 | return HANGCHECK_ACTIVE; |
| 2889 | } |
| 2890 | |
| 2891 | return HANGCHECK_ACTIVE_LOOP; |
| 2892 | } |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2893 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2894 | if (IS_GEN2(dev)) |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2895 | return HANGCHECK_HUNG; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2896 | |
| 2897 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 2898 | * If so we can simply poke the RB_WAIT bit |
| 2899 | * and break the hang. This should work on |
| 2900 | * all but the second generation chipsets. |
| 2901 | */ |
| 2902 | tmp = I915_READ_CTL(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2903 | if (tmp & RING_WAIT) { |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2904 | i915_handle_error(dev, false, |
| 2905 | "Kicking stuck wait on %s", |
| 2906 | ring->name); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2907 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2908 | return HANGCHECK_KICK; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2909 | } |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2910 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2911 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { |
| 2912 | switch (semaphore_passed(ring)) { |
| 2913 | default: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2914 | return HANGCHECK_HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2915 | case 1: |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2916 | i915_handle_error(dev, false, |
| 2917 | "Kicking stuck semaphore on %s", |
| 2918 | ring->name); |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2919 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2920 | return HANGCHECK_KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2921 | case 0: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2922 | return HANGCHECK_WAIT; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2923 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2924 | } |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 2925 | |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2926 | return HANGCHECK_HUNG; |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 2927 | } |
| 2928 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2929 | /** |
| 2930 | * This is called when the chip hasn't reported back with completed |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2931 | * batchbuffers in a long time. We keep track per ring seqno progress and |
| 2932 | * if there are no progress, hangcheck score for that ring is increased. |
| 2933 | * Further, acthd is inspected to see if the ring is stuck. On stuck case |
| 2934 | * we kick the ring. If we see no progress on three subsequent calls |
| 2935 | * we assume chip is wedged and try to fix it by resetting the chip. |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2936 | */ |
Damien Lespiau | a658b5d | 2013-08-08 22:28:56 +0100 | [diff] [blame] | 2937 | static void i915_hangcheck_elapsed(unsigned long data) |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2938 | { |
| 2939 | struct drm_device *dev = (struct drm_device *)data; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 2940 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2941 | struct intel_engine_cs *ring; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2942 | int i; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2943 | int busy_count = 0, rings_hung = 0; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2944 | bool stuck[I915_NUM_RINGS] = { 0 }; |
| 2945 | #define BUSY 1 |
| 2946 | #define KICK 5 |
| 2947 | #define HUNG 20 |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2948 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2949 | if (!i915.enable_hangcheck) |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 2950 | return; |
| 2951 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2952 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 2953 | u64 acthd; |
| 2954 | u32 seqno; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2955 | bool busy = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2956 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2957 | semaphore_clear_deadlocks(dev_priv); |
| 2958 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2959 | seqno = ring->get_seqno(ring, false); |
| 2960 | acthd = intel_ring_get_active_head(ring); |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 2961 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2962 | if (ring->hangcheck.seqno == seqno) { |
| 2963 | if (ring_idle(ring, seqno)) { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 2964 | ring->hangcheck.action = HANGCHECK_IDLE; |
| 2965 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2966 | if (waitqueue_active(&ring->irq_queue)) { |
| 2967 | /* Issue a wake-up to catch stuck h/w. */ |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 2968 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
Daniel Vetter | f4adcd2 | 2013-10-28 09:24:13 +0100 | [diff] [blame] | 2969 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
| 2970 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", |
| 2971 | ring->name); |
| 2972 | else |
| 2973 | DRM_INFO("Fake missed irq on %s\n", |
| 2974 | ring->name); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 2975 | wake_up_all(&ring->irq_queue); |
| 2976 | } |
| 2977 | /* Safeguard against driver failure */ |
| 2978 | ring->hangcheck.score += BUSY; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2979 | } else |
| 2980 | busy = false; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2981 | } else { |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2982 | /* We always increment the hangcheck score |
| 2983 | * if the ring is busy and still processing |
| 2984 | * the same request, so that no single request |
| 2985 | * can run indefinitely (such as a chain of |
| 2986 | * batches). The only time we do not increment |
| 2987 | * the hangcheck score on this ring, if this |
| 2988 | * ring is in a legitimate wait for another |
| 2989 | * ring. In that case the waiting ring is a |
| 2990 | * victim and we want to be sure we catch the |
| 2991 | * right culprit. Then every time we do kick |
| 2992 | * the ring, add a small increment to the |
| 2993 | * score so that we can catch a batch that is |
| 2994 | * being repeatedly kicked and so responsible |
| 2995 | * for stalling the machine. |
| 2996 | */ |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 2997 | ring->hangcheck.action = ring_stuck(ring, |
| 2998 | acthd); |
| 2999 | |
| 3000 | switch (ring->hangcheck.action) { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 3001 | case HANGCHECK_IDLE: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3002 | case HANGCHECK_WAIT: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3003 | case HANGCHECK_ACTIVE: |
Mika Kuoppala | f260fe7 | 2014-08-05 17:16:26 +0300 | [diff] [blame] | 3004 | break; |
| 3005 | case HANGCHECK_ACTIVE_LOOP: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 3006 | ring->hangcheck.score += BUSY; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3007 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3008 | case HANGCHECK_KICK: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 3009 | ring->hangcheck.score += KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3010 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 3011 | case HANGCHECK_HUNG: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 3012 | ring->hangcheck.score += HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 3013 | stuck[i] = true; |
| 3014 | break; |
| 3015 | } |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3016 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3017 | } else { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 3018 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
| 3019 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3020 | /* Gradually reduce the count so that we catch DoS |
| 3021 | * attempts across multiple batches. |
| 3022 | */ |
| 3023 | if (ring->hangcheck.score > 0) |
| 3024 | ring->hangcheck.score--; |
Mika Kuoppala | f260fe7 | 2014-08-05 17:16:26 +0300 | [diff] [blame] | 3025 | |
| 3026 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 3027 | } |
| 3028 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3029 | ring->hangcheck.seqno = seqno; |
| 3030 | ring->hangcheck.acthd = acthd; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 3031 | busy_count += busy; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 3032 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 3033 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 3034 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 3035 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
Daniel Vetter | b8d88d1 | 2013-08-28 10:57:59 +0200 | [diff] [blame] | 3036 | DRM_INFO("%s on %s\n", |
| 3037 | stuck[i] ? "stuck" : "no progress", |
| 3038 | ring->name); |
Chris Wilson | a43adf0 | 2013-06-10 11:20:22 +0100 | [diff] [blame] | 3039 | rings_hung++; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 3040 | } |
| 3041 | } |
| 3042 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3043 | if (rings_hung) |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3044 | return i915_handle_error(dev, true, "Ring hung"); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 3045 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 3046 | if (busy_count) |
| 3047 | /* Reset timer case chip hangs without another request |
| 3048 | * being added */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 3049 | i915_queue_hangcheck(dev); |
| 3050 | } |
| 3051 | |
| 3052 | void i915_queue_hangcheck(struct drm_device *dev) |
| 3053 | { |
| 3054 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 672e7b7 | 2014-11-19 09:47:19 +0000 | [diff] [blame] | 3055 | struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer; |
| 3056 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 3057 | if (!i915.enable_hangcheck) |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 3058 | return; |
| 3059 | |
Chris Wilson | 672e7b7 | 2014-11-19 09:47:19 +0000 | [diff] [blame] | 3060 | /* Don't continually defer the hangcheck, but make sure it is active */ |
| 3061 | if (!timer_pending(timer)) |
| 3062 | timer->expires = round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES); |
| 3063 | mod_timer(timer, timer->expires); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 3064 | } |
| 3065 | |
Paulo Zanoni | 1c69eb4 | 2014-04-01 15:37:23 -0300 | [diff] [blame] | 3066 | static void ibx_irq_reset(struct drm_device *dev) |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 3067 | { |
| 3068 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3069 | |
| 3070 | if (HAS_PCH_NOP(dev)) |
| 3071 | return; |
| 3072 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3073 | GEN5_IRQ_RESET(SDE); |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3074 | |
| 3075 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
| 3076 | I915_WRITE(SERR_INT, 0xffffffff); |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3077 | } |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3078 | |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3079 | /* |
| 3080 | * SDEIER is also touched by the interrupt handler to work around missed PCH |
| 3081 | * interrupts. Hence we can't update it after the interrupt handler is enabled - |
| 3082 | * instead we unconditionally enable all PCH interrupt sources here, but then |
| 3083 | * only unmask them as needed with SDEIMR. |
| 3084 | * |
| 3085 | * This function needs to be called before interrupts are enabled. |
| 3086 | */ |
| 3087 | static void ibx_irq_pre_postinstall(struct drm_device *dev) |
| 3088 | { |
| 3089 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3090 | |
| 3091 | if (HAS_PCH_NOP(dev)) |
| 3092 | return; |
| 3093 | |
| 3094 | WARN_ON(I915_READ(SDEIER) != 0); |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 3095 | I915_WRITE(SDEIER, 0xffffffff); |
| 3096 | POSTING_READ(SDEIER); |
| 3097 | } |
| 3098 | |
Paulo Zanoni | 7c4d664 | 2014-04-01 15:37:19 -0300 | [diff] [blame] | 3099 | static void gen5_gt_irq_reset(struct drm_device *dev) |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 3100 | { |
| 3101 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3102 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3103 | GEN5_IRQ_RESET(GT); |
Paulo Zanoni | a9d356a | 2014-04-01 15:37:09 -0300 | [diff] [blame] | 3104 | if (INTEL_INFO(dev)->gen >= 6) |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3105 | GEN5_IRQ_RESET(GEN6_PM); |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 3106 | } |
| 3107 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3108 | /* drm_dma.h hooks |
| 3109 | */ |
Paulo Zanoni | be30b29 | 2014-04-01 15:37:25 -0300 | [diff] [blame] | 3110 | static void ironlake_irq_reset(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3111 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3112 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3113 | |
Paulo Zanoni | 0c84121 | 2014-04-01 15:37:27 -0300 | [diff] [blame] | 3114 | I915_WRITE(HWSTAM, 0xffffffff); |
Daniel Vetter | bdfcdb6 | 2012-01-05 01:05:26 +0100 | [diff] [blame] | 3115 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3116 | GEN5_IRQ_RESET(DE); |
Paulo Zanoni | c6d954c | 2014-04-01 15:37:18 -0300 | [diff] [blame] | 3117 | if (IS_GEN7(dev)) |
| 3118 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3119 | |
Paulo Zanoni | 7c4d664 | 2014-04-01 15:37:19 -0300 | [diff] [blame] | 3120 | gen5_gt_irq_reset(dev); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 3121 | |
Paulo Zanoni | 1c69eb4 | 2014-04-01 15:37:23 -0300 | [diff] [blame] | 3122 | ibx_irq_reset(dev); |
Ben Widawsky | 7d99163 | 2013-05-28 19:22:25 -0700 | [diff] [blame] | 3123 | } |
| 3124 | |
Ville Syrjälä | 70591a4 | 2014-10-30 19:42:58 +0200 | [diff] [blame] | 3125 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
| 3126 | { |
| 3127 | enum pipe pipe; |
| 3128 | |
| 3129 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3130 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 3131 | |
| 3132 | for_each_pipe(dev_priv, pipe) |
| 3133 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3134 | |
| 3135 | GEN5_IRQ_RESET(VLV_); |
| 3136 | } |
| 3137 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3138 | static void valleyview_irq_preinstall(struct drm_device *dev) |
| 3139 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3140 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3141 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3142 | /* VLV magic */ |
| 3143 | I915_WRITE(VLV_IMR, 0); |
| 3144 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); |
| 3145 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); |
| 3146 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); |
| 3147 | |
Paulo Zanoni | 7c4d664 | 2014-04-01 15:37:19 -0300 | [diff] [blame] | 3148 | gen5_gt_irq_reset(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3149 | |
Ville Syrjälä | 7c4cde3 | 2014-10-30 19:42:51 +0200 | [diff] [blame] | 3150 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3151 | |
Ville Syrjälä | 70591a4 | 2014-10-30 19:42:58 +0200 | [diff] [blame] | 3152 | vlv_display_irq_reset(dev_priv); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3153 | } |
| 3154 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3155 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
| 3156 | { |
| 3157 | GEN8_IRQ_RESET_NDX(GT, 0); |
| 3158 | GEN8_IRQ_RESET_NDX(GT, 1); |
| 3159 | GEN8_IRQ_RESET_NDX(GT, 2); |
| 3160 | GEN8_IRQ_RESET_NDX(GT, 3); |
| 3161 | } |
| 3162 | |
Paulo Zanoni | 823f6b3 | 2014-04-01 15:37:26 -0300 | [diff] [blame] | 3163 | static void gen8_irq_reset(struct drm_device *dev) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3164 | { |
| 3165 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3166 | int pipe; |
| 3167 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3168 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3169 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3170 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3171 | gen8_gt_irq_reset(dev_priv); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3172 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3173 | for_each_pipe(dev_priv, pipe) |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 3174 | if (intel_display_power_is_enabled(dev_priv, |
| 3175 | POWER_DOMAIN_PIPE(pipe))) |
Paulo Zanoni | 813bde4 | 2014-07-04 11:50:29 -0300 | [diff] [blame] | 3176 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3177 | |
Paulo Zanoni | f86f3fb | 2014-04-01 15:37:14 -0300 | [diff] [blame] | 3178 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
| 3179 | GEN5_IRQ_RESET(GEN8_DE_MISC_); |
| 3180 | GEN5_IRQ_RESET(GEN8_PCU_); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3181 | |
Paulo Zanoni | 1c69eb4 | 2014-04-01 15:37:23 -0300 | [diff] [blame] | 3182 | ibx_irq_reset(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3183 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3184 | |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3185 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) |
| 3186 | { |
Paulo Zanoni | 1180e20 | 2014-10-07 18:02:52 -0300 | [diff] [blame] | 3187 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3188 | |
Daniel Vetter | 1332178 | 2014-09-15 14:55:29 +0200 | [diff] [blame] | 3189 | spin_lock_irq(&dev_priv->irq_lock); |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3190 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], |
Paulo Zanoni | 1180e20 | 2014-10-07 18:02:52 -0300 | [diff] [blame] | 3191 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3192 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], |
Paulo Zanoni | 1180e20 | 2014-10-07 18:02:52 -0300 | [diff] [blame] | 3193 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); |
Daniel Vetter | 1332178 | 2014-09-15 14:55:29 +0200 | [diff] [blame] | 3194 | spin_unlock_irq(&dev_priv->irq_lock); |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 3195 | } |
| 3196 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3197 | static void cherryview_irq_preinstall(struct drm_device *dev) |
| 3198 | { |
| 3199 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3200 | |
| 3201 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3202 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3203 | |
Daniel Vetter | d6e3cca | 2014-05-22 22:18:22 +0200 | [diff] [blame] | 3204 | gen8_gt_irq_reset(dev_priv); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3205 | |
| 3206 | GEN5_IRQ_RESET(GEN8_PCU_); |
| 3207 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3208 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
| 3209 | |
Ville Syrjälä | 70591a4 | 2014-10-30 19:42:58 +0200 | [diff] [blame] | 3210 | vlv_display_irq_reset(dev_priv); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3211 | } |
| 3212 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3213 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3214 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3215 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3216 | struct intel_encoder *intel_encoder; |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3217 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3218 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3219 | if (HAS_PCH_IBX(dev)) { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3220 | hotplug_irqs = SDE_HOTPLUG_MASK; |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 3221 | for_each_intel_encoder(dev, intel_encoder) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 3222 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3223 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3224 | } else { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3225 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 3226 | for_each_intel_encoder(dev, intel_encoder) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 3227 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3228 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3229 | } |
| 3230 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 3231 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3232 | |
| 3233 | /* |
| 3234 | * Enable digital hotplug on the PCH, and configure the DP short pulse |
| 3235 | * duration to 2ms (which is the minimum in the Display Port spec) |
| 3236 | * |
| 3237 | * This register is the same on all known PCH chips. |
| 3238 | */ |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3239 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 3240 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); |
| 3241 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
| 3242 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
| 3243 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
| 3244 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 3245 | } |
| 3246 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3247 | static void ibx_irq_postinstall(struct drm_device *dev) |
| 3248 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3249 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3250 | u32 mask; |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3251 | |
Daniel Vetter | 692a04c | 2013-05-29 21:43:05 +0200 | [diff] [blame] | 3252 | if (HAS_PCH_NOP(dev)) |
| 3253 | return; |
| 3254 | |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3255 | if (HAS_PCH_IBX(dev)) |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3256 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
Paulo Zanoni | 105b122 | 2014-04-01 15:37:17 -0300 | [diff] [blame] | 3257 | else |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3258 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3259 | |
Paulo Zanoni | 337ba01 | 2014-04-01 15:37:16 -0300 | [diff] [blame] | 3260 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3261 | I915_WRITE(SDEIMR, ~mask); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3262 | } |
| 3263 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3264 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
| 3265 | { |
| 3266 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3267 | u32 pm_irqs, gt_irqs; |
| 3268 | |
| 3269 | pm_irqs = gt_irqs = 0; |
| 3270 | |
| 3271 | dev_priv->gt_irq_mask = ~0; |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 3272 | if (HAS_L3_DPF(dev)) { |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3273 | /* L3 parity interrupt is always unmasked. */ |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 3274 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
| 3275 | gt_irqs |= GT_PARITY_ERROR(dev); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3276 | } |
| 3277 | |
| 3278 | gt_irqs |= GT_RENDER_USER_INTERRUPT; |
| 3279 | if (IS_GEN5(dev)) { |
| 3280 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | |
| 3281 | ILK_BSD_USER_INTERRUPT; |
| 3282 | } else { |
| 3283 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; |
| 3284 | } |
| 3285 | |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 3286 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3287 | |
| 3288 | if (INTEL_INFO(dev)->gen >= 6) { |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 3289 | pm_irqs |= dev_priv->pm_rps_events; |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3290 | |
| 3291 | if (HAS_VEBOX(dev)) |
| 3292 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
| 3293 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 3294 | dev_priv->pm_irq_mask = 0xffffffff; |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 3295 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3296 | } |
| 3297 | } |
| 3298 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3299 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3300 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3301 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 3302 | u32 display_mask, extra_mask; |
| 3303 | |
| 3304 | if (INTEL_INFO(dev)->gen >= 7) { |
| 3305 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
| 3306 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | |
| 3307 | DE_PLANEB_FLIP_DONE_IVB | |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3308 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 3309 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3310 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 3311 | } else { |
| 3312 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 3313 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3314 | DE_AUX_CHANNEL_A | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3315 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
| 3316 | DE_POISON); |
Daniel Vetter | 5c673b6 | 2014-03-07 20:34:46 +0100 | [diff] [blame] | 3317 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
| 3318 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 3319 | } |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3320 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3321 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3322 | |
Paulo Zanoni | 0c84121 | 2014-04-01 15:37:27 -0300 | [diff] [blame] | 3323 | I915_WRITE(HWSTAM, 0xeffe); |
| 3324 | |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3325 | ibx_irq_pre_postinstall(dev); |
| 3326 | |
Paulo Zanoni | 3507989 | 2014-04-01 15:37:15 -0300 | [diff] [blame] | 3327 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3328 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3329 | gen5_gt_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3330 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 3331 | ibx_irq_postinstall(dev); |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 3332 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 3333 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 6005ce4 | 2013-06-27 13:44:59 +0200 | [diff] [blame] | 3334 | /* Enable PCU event interrupts |
| 3335 | * |
| 3336 | * spinlocking not required here for correctness since interrupt |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 3337 | * setup is guaranteed to run in single-threaded context. But we |
| 3338 | * need it to make the assert_spin_locked happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 3339 | spin_lock_irq(&dev_priv->irq_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 3340 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 3341 | spin_unlock_irq(&dev_priv->irq_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 3342 | } |
| 3343 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3344 | return 0; |
| 3345 | } |
| 3346 | |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3347 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
| 3348 | { |
| 3349 | u32 pipestat_mask; |
| 3350 | u32 iir_mask; |
Ville Syrjälä | 120dda4 | 2014-10-30 19:42:57 +0200 | [diff] [blame] | 3351 | enum pipe pipe; |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3352 | |
| 3353 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | |
| 3354 | PIPE_FIFO_UNDERRUN_STATUS; |
| 3355 | |
Ville Syrjälä | 120dda4 | 2014-10-30 19:42:57 +0200 | [diff] [blame] | 3356 | for_each_pipe(dev_priv, pipe) |
| 3357 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3358 | POSTING_READ(PIPESTAT(PIPE_A)); |
| 3359 | |
| 3360 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
| 3361 | PIPE_CRC_DONE_INTERRUPT_STATUS; |
| 3362 | |
Ville Syrjälä | 120dda4 | 2014-10-30 19:42:57 +0200 | [diff] [blame] | 3363 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
| 3364 | for_each_pipe(dev_priv, pipe) |
| 3365 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3366 | |
| 3367 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | |
| 3368 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3369 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
Ville Syrjälä | 120dda4 | 2014-10-30 19:42:57 +0200 | [diff] [blame] | 3370 | if (IS_CHERRYVIEW(dev_priv)) |
| 3371 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3372 | dev_priv->irq_mask &= ~iir_mask; |
| 3373 | |
| 3374 | I915_WRITE(VLV_IIR, iir_mask); |
| 3375 | I915_WRITE(VLV_IIR, iir_mask); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3376 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
Ville Syrjälä | 76e4186 | 2014-10-30 19:42:54 +0200 | [diff] [blame] | 3377 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 3378 | POSTING_READ(VLV_IMR); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3379 | } |
| 3380 | |
| 3381 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) |
| 3382 | { |
| 3383 | u32 pipestat_mask; |
| 3384 | u32 iir_mask; |
Ville Syrjälä | 120dda4 | 2014-10-30 19:42:57 +0200 | [diff] [blame] | 3385 | enum pipe pipe; |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3386 | |
| 3387 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | |
| 3388 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
Imre Deak | 6c7fba0 | 2014-03-10 19:44:48 +0200 | [diff] [blame] | 3389 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
Ville Syrjälä | 120dda4 | 2014-10-30 19:42:57 +0200 | [diff] [blame] | 3390 | if (IS_CHERRYVIEW(dev_priv)) |
| 3391 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3392 | |
| 3393 | dev_priv->irq_mask |= iir_mask; |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3394 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
Ville Syrjälä | 76e4186 | 2014-10-30 19:42:54 +0200 | [diff] [blame] | 3395 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3396 | I915_WRITE(VLV_IIR, iir_mask); |
| 3397 | I915_WRITE(VLV_IIR, iir_mask); |
| 3398 | POSTING_READ(VLV_IIR); |
| 3399 | |
| 3400 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
| 3401 | PIPE_CRC_DONE_INTERRUPT_STATUS; |
| 3402 | |
Ville Syrjälä | 120dda4 | 2014-10-30 19:42:57 +0200 | [diff] [blame] | 3403 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
| 3404 | for_each_pipe(dev_priv, pipe) |
| 3405 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3406 | |
| 3407 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | |
| 3408 | PIPE_FIFO_UNDERRUN_STATUS; |
Ville Syrjälä | 120dda4 | 2014-10-30 19:42:57 +0200 | [diff] [blame] | 3409 | |
| 3410 | for_each_pipe(dev_priv, pipe) |
| 3411 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3412 | POSTING_READ(PIPESTAT(PIPE_A)); |
| 3413 | } |
| 3414 | |
| 3415 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
| 3416 | { |
| 3417 | assert_spin_locked(&dev_priv->irq_lock); |
| 3418 | |
| 3419 | if (dev_priv->display_irqs_enabled) |
| 3420 | return; |
| 3421 | |
| 3422 | dev_priv->display_irqs_enabled = true; |
| 3423 | |
Imre Deak | 950eaba | 2014-09-08 15:21:09 +0300 | [diff] [blame] | 3424 | if (intel_irqs_enabled(dev_priv)) |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3425 | valleyview_display_irqs_install(dev_priv); |
| 3426 | } |
| 3427 | |
| 3428 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) |
| 3429 | { |
| 3430 | assert_spin_locked(&dev_priv->irq_lock); |
| 3431 | |
| 3432 | if (!dev_priv->display_irqs_enabled) |
| 3433 | return; |
| 3434 | |
| 3435 | dev_priv->display_irqs_enabled = false; |
| 3436 | |
Imre Deak | 950eaba | 2014-09-08 15:21:09 +0300 | [diff] [blame] | 3437 | if (intel_irqs_enabled(dev_priv)) |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3438 | valleyview_display_irqs_uninstall(dev_priv); |
| 3439 | } |
| 3440 | |
Ville Syrjälä | 0e6c9a9 | 2014-10-30 19:43:00 +0200 | [diff] [blame] | 3441 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3442 | { |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3443 | dev_priv->irq_mask = ~0; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3444 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3445 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3446 | POSTING_READ(PORT_HOTPLUG_EN); |
| 3447 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3448 | I915_WRITE(VLV_IIR, 0xffffffff); |
Ville Syrjälä | 76e4186 | 2014-10-30 19:42:54 +0200 | [diff] [blame] | 3449 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3450 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
| 3451 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 3452 | POSTING_READ(VLV_IMR); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3453 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 3454 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3455 | * just to make the assert_spin_locked check happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 3456 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3457 | if (dev_priv->display_irqs_enabled) |
| 3458 | valleyview_display_irqs_install(dev_priv); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 3459 | spin_unlock_irq(&dev_priv->irq_lock); |
Ville Syrjälä | 0e6c9a9 | 2014-10-30 19:43:00 +0200 | [diff] [blame] | 3460 | } |
| 3461 | |
| 3462 | static int valleyview_irq_postinstall(struct drm_device *dev) |
| 3463 | { |
| 3464 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3465 | |
| 3466 | vlv_display_irq_postinstall(dev_priv); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3467 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 3468 | gen5_gt_irq_postinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3469 | |
| 3470 | /* ack & enable invalid PTE error interrupts */ |
| 3471 | #if 0 /* FIXME: add support to irq handler for checking these bits */ |
| 3472 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
| 3473 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); |
| 3474 | #endif |
| 3475 | |
| 3476 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3477 | |
| 3478 | return 0; |
| 3479 | } |
| 3480 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3481 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
| 3482 | { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3483 | /* These are interrupts we'll toggle with the ring mask register */ |
| 3484 | uint32_t gt_interrupts[] = { |
| 3485 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 3486 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3487 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 3488 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
| 3489 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3490 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 3491 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
| 3492 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | |
| 3493 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3494 | 0, |
Oscar Mateo | 73d477f | 2014-07-24 17:04:31 +0100 | [diff] [blame] | 3495 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
| 3496 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3497 | }; |
| 3498 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 3499 | dev_priv->pm_irq_mask = 0xffffffff; |
Deepak S | 9a2d2d8 | 2014-08-22 08:32:40 +0530 | [diff] [blame] | 3500 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
| 3501 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); |
| 3502 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events); |
| 3503 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3504 | } |
| 3505 | |
| 3506 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) |
| 3507 | { |
Damien Lespiau | 770de83 | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3508 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
| 3509 | uint32_t de_pipe_enables; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3510 | int pipe; |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 3511 | u32 aux_en = GEN8_AUX_CHANNEL_A; |
Damien Lespiau | 770de83 | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3512 | |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 3513 | if (IS_GEN9(dev_priv)) { |
Damien Lespiau | 770de83 | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3514 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
| 3515 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 3516 | aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
| 3517 | GEN9_AUX_CHANNEL_D; |
| 3518 | } else |
Damien Lespiau | 770de83 | 2014-03-20 20:45:01 +0000 | [diff] [blame] | 3519 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
| 3520 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
| 3521 | |
| 3522 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | |
| 3523 | GEN8_PIPE_FIFO_UNDERRUN; |
| 3524 | |
Daniel Vetter | 13b3a0a | 2013-11-07 15:31:52 +0100 | [diff] [blame] | 3525 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
| 3526 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; |
| 3527 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3528 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3529 | for_each_pipe(dev_priv, pipe) |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 3530 | if (intel_display_power_is_enabled(dev_priv, |
Paulo Zanoni | 813bde4 | 2014-07-04 11:50:29 -0300 | [diff] [blame] | 3531 | POWER_DOMAIN_PIPE(pipe))) |
| 3532 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, |
| 3533 | dev_priv->de_irq_mask[pipe], |
| 3534 | de_pipe_enables); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3535 | |
Jesse Barnes | 88e0470 | 2014-11-13 17:51:48 +0000 | [diff] [blame] | 3536 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3537 | } |
| 3538 | |
| 3539 | static int gen8_irq_postinstall(struct drm_device *dev) |
| 3540 | { |
| 3541 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3542 | |
Paulo Zanoni | 622364b | 2014-04-01 15:37:22 -0300 | [diff] [blame] | 3543 | ibx_irq_pre_postinstall(dev); |
| 3544 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3545 | gen8_gt_irq_postinstall(dev_priv); |
| 3546 | gen8_de_irq_postinstall(dev_priv); |
| 3547 | |
| 3548 | ibx_irq_postinstall(dev); |
| 3549 | |
| 3550 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
| 3551 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3552 | |
| 3553 | return 0; |
| 3554 | } |
| 3555 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3556 | static int cherryview_irq_postinstall(struct drm_device *dev) |
| 3557 | { |
| 3558 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3559 | |
Ville Syrjälä | c2b6679 | 2014-10-30 19:43:02 +0200 | [diff] [blame] | 3560 | vlv_display_irq_postinstall(dev_priv); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3561 | |
| 3562 | gen8_gt_irq_postinstall(dev_priv); |
| 3563 | |
| 3564 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); |
| 3565 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3566 | |
| 3567 | return 0; |
| 3568 | } |
| 3569 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3570 | static void gen8_irq_uninstall(struct drm_device *dev) |
| 3571 | { |
| 3572 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3573 | |
| 3574 | if (!dev_priv) |
| 3575 | return; |
| 3576 | |
Paulo Zanoni | 823f6b3 | 2014-04-01 15:37:26 -0300 | [diff] [blame] | 3577 | gen8_irq_reset(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3578 | } |
| 3579 | |
Ville Syrjälä | 8ea0be4 | 2014-10-30 19:42:59 +0200 | [diff] [blame] | 3580 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
| 3581 | { |
| 3582 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3583 | * just to make the assert_spin_locked check happy. */ |
| 3584 | spin_lock_irq(&dev_priv->irq_lock); |
| 3585 | if (dev_priv->display_irqs_enabled) |
| 3586 | valleyview_display_irqs_uninstall(dev_priv); |
| 3587 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3588 | |
| 3589 | vlv_display_irq_reset(dev_priv); |
| 3590 | |
| 3591 | dev_priv->irq_mask = 0; |
| 3592 | } |
| 3593 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3594 | static void valleyview_irq_uninstall(struct drm_device *dev) |
| 3595 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3596 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3597 | |
| 3598 | if (!dev_priv) |
| 3599 | return; |
| 3600 | |
Imre Deak | 843d0e7 | 2014-04-14 20:24:23 +0300 | [diff] [blame] | 3601 | I915_WRITE(VLV_MASTER_IER, 0); |
| 3602 | |
Ville Syrjälä | 893fce8 | 2014-10-30 19:42:56 +0200 | [diff] [blame] | 3603 | gen5_gt_irq_reset(dev); |
| 3604 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3605 | I915_WRITE(HWSTAM, 0xffffffff); |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 3606 | |
Ville Syrjälä | 8ea0be4 | 2014-10-30 19:42:59 +0200 | [diff] [blame] | 3607 | vlv_display_irq_uninstall(dev_priv); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3608 | } |
| 3609 | |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3610 | static void cherryview_irq_uninstall(struct drm_device *dev) |
| 3611 | { |
| 3612 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3613 | |
| 3614 | if (!dev_priv) |
| 3615 | return; |
| 3616 | |
| 3617 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3618 | POSTING_READ(GEN8_MASTER_IRQ); |
| 3619 | |
Ville Syrjälä | a2c30fb | 2014-10-30 19:42:52 +0200 | [diff] [blame] | 3620 | gen8_gt_irq_reset(dev_priv); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3621 | |
Ville Syrjälä | a2c30fb | 2014-10-30 19:42:52 +0200 | [diff] [blame] | 3622 | GEN5_IRQ_RESET(GEN8_PCU_); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3623 | |
Ville Syrjälä | c2b6679 | 2014-10-30 19:43:02 +0200 | [diff] [blame] | 3624 | vlv_display_irq_uninstall(dev_priv); |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 3625 | } |
| 3626 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3627 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3628 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3629 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 3630 | |
| 3631 | if (!dev_priv) |
| 3632 | return; |
| 3633 | |
Paulo Zanoni | be30b29 | 2014-04-01 15:37:25 -0300 | [diff] [blame] | 3634 | ironlake_irq_reset(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3635 | } |
| 3636 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3637 | static void i8xx_irq_preinstall(struct drm_device * dev) |
| 3638 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3639 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3640 | int pipe; |
| 3641 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3642 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3643 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3644 | I915_WRITE16(IMR, 0xffff); |
| 3645 | I915_WRITE16(IER, 0x0); |
| 3646 | POSTING_READ16(IER); |
| 3647 | } |
| 3648 | |
| 3649 | static int i8xx_irq_postinstall(struct drm_device *dev) |
| 3650 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3651 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3652 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3653 | I915_WRITE16(EMR, |
| 3654 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 3655 | |
| 3656 | /* Unmask the interrupts that we always want on. */ |
| 3657 | dev_priv->irq_mask = |
| 3658 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3659 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3660 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3661 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 3662 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 3663 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 3664 | |
| 3665 | I915_WRITE16(IER, |
| 3666 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3667 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3668 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 3669 | I915_USER_INTERRUPT); |
| 3670 | POSTING_READ16(IER); |
| 3671 | |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3672 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3673 | * just to make the assert_spin_locked check happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 3674 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 3675 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 3676 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 3677 | spin_unlock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3678 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3679 | return 0; |
| 3680 | } |
| 3681 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3682 | /* |
| 3683 | * Returns true when a page flip has completed. |
| 3684 | */ |
| 3685 | static bool i8xx_handle_vblank(struct drm_device *dev, |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 3686 | int plane, int pipe, u32 iir) |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3687 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3688 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 3689 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3690 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 3691 | if (!intel_pipe_handle_vblank(dev, pipe)) |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3692 | return false; |
| 3693 | |
| 3694 | if ((iir & flip_pending) == 0) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 3695 | goto check_page_flip; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3696 | |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 3697 | intel_prepare_page_flip(dev, plane); |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3698 | |
| 3699 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 3700 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 3701 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 3702 | * the flip is completed (no longer pending). Since this doesn't raise |
| 3703 | * an interrupt per se, we watch for the change at vblank. |
| 3704 | */ |
| 3705 | if (I915_READ16(ISR) & flip_pending) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 3706 | goto check_page_flip; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3707 | |
| 3708 | intel_finish_page_flip(dev, pipe); |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3709 | return true; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 3710 | |
| 3711 | check_page_flip: |
| 3712 | intel_check_page_flip(dev, pipe); |
| 3713 | return false; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3714 | } |
| 3715 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 3716 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3717 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 3718 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3719 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3720 | u16 iir, new_iir; |
| 3721 | u32 pipe_stats[2]; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3722 | int pipe; |
| 3723 | u16 flip_mask = |
| 3724 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3725 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 3726 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3727 | iir = I915_READ16(IIR); |
| 3728 | if (iir == 0) |
| 3729 | return IRQ_NONE; |
| 3730 | |
| 3731 | while (iir & ~flip_mask) { |
| 3732 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 3733 | * have been cleared after the pipestat interrupt was received. |
| 3734 | * It doesn't set the bit in iir again, but it still produces |
| 3735 | * interrupts (for non-MSI). |
| 3736 | */ |
Daniel Vetter | 222c7f5 | 2014-09-15 14:55:28 +0200 | [diff] [blame] | 3737 | spin_lock(&dev_priv->irq_lock); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3738 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3739 | i915_handle_error(dev, false, |
| 3740 | "Command parser error, iir 0x%08x", |
| 3741 | iir); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3742 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3743 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3744 | int reg = PIPESTAT(pipe); |
| 3745 | pipe_stats[pipe] = I915_READ(reg); |
| 3746 | |
| 3747 | /* |
| 3748 | * Clear the PIPE*STAT regs before the IIR |
| 3749 | */ |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 3750 | if (pipe_stats[pipe] & 0x8000ffff) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3751 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3752 | } |
Daniel Vetter | 222c7f5 | 2014-09-15 14:55:28 +0200 | [diff] [blame] | 3753 | spin_unlock(&dev_priv->irq_lock); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3754 | |
| 3755 | I915_WRITE16(IIR, iir & ~flip_mask); |
| 3756 | new_iir = I915_READ16(IIR); /* Flush posted writes */ |
| 3757 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 3758 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3759 | |
| 3760 | if (iir & I915_USER_INTERRUPT) |
| 3761 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 3762 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3763 | for_each_pipe(dev_priv, pipe) { |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 3764 | int plane = pipe; |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 3765 | if (HAS_FBC(dev)) |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 3766 | plane = !plane; |
| 3767 | |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3768 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 3769 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
| 3770 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3771 | |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3772 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 3773 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 3774 | |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 3775 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 3776 | intel_cpu_fifo_underrun_irq_handler(dev_priv, |
| 3777 | pipe); |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3778 | } |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3779 | |
| 3780 | iir = new_iir; |
| 3781 | } |
| 3782 | |
| 3783 | return IRQ_HANDLED; |
| 3784 | } |
| 3785 | |
| 3786 | static void i8xx_irq_uninstall(struct drm_device * dev) |
| 3787 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3788 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3789 | int pipe; |
| 3790 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3791 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3792 | /* Clear enable bits; then clear status bits */ |
| 3793 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3794 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 3795 | } |
| 3796 | I915_WRITE16(IMR, 0xffff); |
| 3797 | I915_WRITE16(IER, 0x0); |
| 3798 | I915_WRITE16(IIR, I915_READ16(IIR)); |
| 3799 | } |
| 3800 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3801 | static void i915_irq_preinstall(struct drm_device * dev) |
| 3802 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3803 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3804 | int pipe; |
| 3805 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3806 | if (I915_HAS_HOTPLUG(dev)) { |
| 3807 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3808 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 3809 | } |
| 3810 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 3811 | I915_WRITE16(HWSTAM, 0xeffe); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3812 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3813 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3814 | I915_WRITE(IMR, 0xffffffff); |
| 3815 | I915_WRITE(IER, 0x0); |
| 3816 | POSTING_READ(IER); |
| 3817 | } |
| 3818 | |
| 3819 | static int i915_irq_postinstall(struct drm_device *dev) |
| 3820 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3821 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3822 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3823 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3824 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 3825 | |
| 3826 | /* Unmask the interrupts that we always want on. */ |
| 3827 | dev_priv->irq_mask = |
| 3828 | ~(I915_ASLE_INTERRUPT | |
| 3829 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3830 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3831 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3832 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 3833 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 3834 | |
| 3835 | enable_mask = |
| 3836 | I915_ASLE_INTERRUPT | |
| 3837 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3838 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3839 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 3840 | I915_USER_INTERRUPT; |
| 3841 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3842 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3843 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3844 | POSTING_READ(PORT_HOTPLUG_EN); |
| 3845 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3846 | /* Enable in IER... */ |
| 3847 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 3848 | /* and unmask in IMR */ |
| 3849 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 3850 | } |
| 3851 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3852 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 3853 | I915_WRITE(IER, enable_mask); |
| 3854 | POSTING_READ(IER); |
| 3855 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 3856 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3857 | |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3858 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3859 | * just to make the assert_spin_locked check happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 3860 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 3861 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 3862 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 3863 | spin_unlock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3864 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3865 | return 0; |
| 3866 | } |
| 3867 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3868 | /* |
| 3869 | * Returns true when a page flip has completed. |
| 3870 | */ |
| 3871 | static bool i915_handle_vblank(struct drm_device *dev, |
| 3872 | int plane, int pipe, u32 iir) |
| 3873 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3874 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3875 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
| 3876 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 3877 | if (!intel_pipe_handle_vblank(dev, pipe)) |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3878 | return false; |
| 3879 | |
| 3880 | if ((iir & flip_pending) == 0) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 3881 | goto check_page_flip; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3882 | |
| 3883 | intel_prepare_page_flip(dev, plane); |
| 3884 | |
| 3885 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 3886 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 3887 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 3888 | * the flip is completed (no longer pending). Since this doesn't raise |
| 3889 | * an interrupt per se, we watch for the change at vblank. |
| 3890 | */ |
| 3891 | if (I915_READ(ISR) & flip_pending) |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 3892 | goto check_page_flip; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3893 | |
| 3894 | intel_finish_page_flip(dev, pipe); |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3895 | return true; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 3896 | |
| 3897 | check_page_flip: |
| 3898 | intel_check_page_flip(dev, pipe); |
| 3899 | return false; |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3900 | } |
| 3901 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 3902 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3903 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 3904 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 3905 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 3906 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3907 | u32 flip_mask = |
| 3908 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3909 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3910 | int pipe, ret = IRQ_NONE; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3911 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3912 | iir = I915_READ(IIR); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3913 | do { |
| 3914 | bool irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 3915 | bool blc_event = false; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3916 | |
| 3917 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 3918 | * have been cleared after the pipestat interrupt was received. |
| 3919 | * It doesn't set the bit in iir again, but it still produces |
| 3920 | * interrupts (for non-MSI). |
| 3921 | */ |
Daniel Vetter | 222c7f5 | 2014-09-15 14:55:28 +0200 | [diff] [blame] | 3922 | spin_lock(&dev_priv->irq_lock); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3923 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3924 | i915_handle_error(dev, false, |
| 3925 | "Command parser error, iir 0x%08x", |
| 3926 | iir); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3927 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3928 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3929 | int reg = PIPESTAT(pipe); |
| 3930 | pipe_stats[pipe] = I915_READ(reg); |
| 3931 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3932 | /* Clear the PIPE*STAT regs before the IIR */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3933 | if (pipe_stats[pipe] & 0x8000ffff) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3934 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3935 | irq_received = true; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3936 | } |
| 3937 | } |
Daniel Vetter | 222c7f5 | 2014-09-15 14:55:28 +0200 | [diff] [blame] | 3938 | spin_unlock(&dev_priv->irq_lock); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3939 | |
| 3940 | if (!irq_received) |
| 3941 | break; |
| 3942 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3943 | /* Consume port. Then clear IIR or we'll miss events */ |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 3944 | if (I915_HAS_HOTPLUG(dev) && |
| 3945 | iir & I915_DISPLAY_PORT_INTERRUPT) |
| 3946 | i9xx_hpd_irq_handler(dev); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3947 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3948 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3949 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 3950 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3951 | if (iir & I915_USER_INTERRUPT) |
| 3952 | notify_ring(dev, &dev_priv->ring[RCS]); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3953 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 3954 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3955 | int plane = pipe; |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 3956 | if (HAS_FBC(dev)) |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3957 | plane = !plane; |
Ville Syrjälä | 5e2032d | 2013-02-19 15:16:38 +0200 | [diff] [blame] | 3958 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3959 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
| 3960 | i915_handle_vblank(dev, plane, pipe, iir)) |
| 3961 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3962 | |
| 3963 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 3964 | blc_event = true; |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3965 | |
| 3966 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 3967 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 3968 | |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 3969 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 3970 | intel_cpu_fifo_underrun_irq_handler(dev_priv, |
| 3971 | pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3972 | } |
| 3973 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3974 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 3975 | intel_opregion_asle_intr(dev); |
| 3976 | |
| 3977 | /* With MSI, interrupts are only generated when iir |
| 3978 | * transitions from zero to nonzero. If another bit got |
| 3979 | * set while we were handling the existing iir bits, then |
| 3980 | * we would never get another interrupt. |
| 3981 | * |
| 3982 | * This is fine on non-MSI as well, as if we hit this path |
| 3983 | * we avoid exiting the interrupt handler only to generate |
| 3984 | * another one. |
| 3985 | * |
| 3986 | * Note that for MSI this could cause a stray interrupt report |
| 3987 | * if an interrupt landed in the time between writing IIR and |
| 3988 | * the posting read. This should be rare enough to never |
| 3989 | * trigger the 99% of 100,000 interrupts test for disabling |
| 3990 | * stray interrupts. |
| 3991 | */ |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3992 | ret = IRQ_HANDLED; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3993 | iir = new_iir; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3994 | } while (iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3995 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 3996 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 3997 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3998 | return ret; |
| 3999 | } |
| 4000 | |
| 4001 | static void i915_irq_uninstall(struct drm_device * dev) |
| 4002 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4003 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4004 | int pipe; |
| 4005 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4006 | if (I915_HAS_HOTPLUG(dev)) { |
| 4007 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4008 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 4009 | } |
| 4010 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 4011 | I915_WRITE16(HWSTAM, 0xffff); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4012 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 4013 | /* Clear enable bits; then clear status bits */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4014 | I915_WRITE(PIPESTAT(pipe), 0); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 4015 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 4016 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4017 | I915_WRITE(IMR, 0xffffffff); |
| 4018 | I915_WRITE(IER, 0x0); |
| 4019 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4020 | I915_WRITE(IIR, I915_READ(IIR)); |
| 4021 | } |
| 4022 | |
| 4023 | static void i965_irq_preinstall(struct drm_device * dev) |
| 4024 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4025 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4026 | int pipe; |
| 4027 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 4028 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4029 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4030 | |
| 4031 | I915_WRITE(HWSTAM, 0xeffe); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4032 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4033 | I915_WRITE(PIPESTAT(pipe), 0); |
| 4034 | I915_WRITE(IMR, 0xffffffff); |
| 4035 | I915_WRITE(IER, 0x0); |
| 4036 | POSTING_READ(IER); |
| 4037 | } |
| 4038 | |
| 4039 | static int i965_irq_postinstall(struct drm_device *dev) |
| 4040 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4041 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4042 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4043 | u32 error_mask; |
| 4044 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4045 | /* Unmask the interrupts that we always want on. */ |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4046 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 4047 | I915_DISPLAY_PORT_INTERRUPT | |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4048 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 4049 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 4050 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4051 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 4052 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 4053 | |
| 4054 | enable_mask = ~dev_priv->irq_mask; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 4055 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4056 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 4057 | enable_mask |= I915_USER_INTERRUPT; |
| 4058 | |
| 4059 | if (IS_G4X(dev)) |
| 4060 | enable_mask |= I915_BSD_USER_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4061 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 4062 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4063 | * just to make the assert_spin_locked check happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4064 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 4065 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
| 4066 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
| 4067 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4068 | spin_unlock_irq(&dev_priv->irq_lock); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4069 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4070 | /* |
| 4071 | * Enable some error detection, note the instruction error mask |
| 4072 | * bit is reserved, so we leave it masked. |
| 4073 | */ |
| 4074 | if (IS_G4X(dev)) { |
| 4075 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 4076 | GM45_ERROR_MEM_PRIV | |
| 4077 | GM45_ERROR_CP_PRIV | |
| 4078 | I915_ERROR_MEMORY_REFRESH); |
| 4079 | } else { |
| 4080 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 4081 | I915_ERROR_MEMORY_REFRESH); |
| 4082 | } |
| 4083 | I915_WRITE(EMR, error_mask); |
| 4084 | |
| 4085 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 4086 | I915_WRITE(IER, enable_mask); |
| 4087 | POSTING_READ(IER); |
| 4088 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4089 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4090 | POSTING_READ(PORT_HOTPLUG_EN); |
| 4091 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 4092 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4093 | |
| 4094 | return 0; |
| 4095 | } |
| 4096 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4097 | static void i915_hpd_irq_setup(struct drm_device *dev) |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4098 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4099 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 4100 | struct intel_encoder *intel_encoder; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4101 | u32 hotplug_en; |
| 4102 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 4103 | assert_spin_locked(&dev_priv->irq_lock); |
| 4104 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4105 | if (I915_HAS_HOTPLUG(dev)) { |
| 4106 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 4107 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; |
| 4108 | /* Note HDMI and DP share hotplug bits */ |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 4109 | /* enable bits are the same for all generations */ |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 4110 | for_each_intel_encoder(dev, intel_encoder) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 4111 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
| 4112 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4113 | /* Programming the CRT detection parameters tends |
| 4114 | to generate a spurious hotplug event about three |
| 4115 | seconds later. So just do it once. |
| 4116 | */ |
| 4117 | if (IS_G4X(dev)) |
| 4118 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
Daniel Vetter | 85fc95b | 2013-03-27 15:47:11 +0100 | [diff] [blame] | 4119 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4120 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4121 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4122 | /* Ignore TV since it's buggy */ |
| 4123 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 4124 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4125 | } |
| 4126 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 4127 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4128 | { |
Daniel Vetter | 45a83f8 | 2014-05-12 19:17:55 +0200 | [diff] [blame] | 4129 | struct drm_device *dev = arg; |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4130 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4131 | u32 iir, new_iir; |
| 4132 | u32 pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4133 | int ret = IRQ_NONE, pipe; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 4134 | u32 flip_mask = |
| 4135 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 4136 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4137 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4138 | iir = I915_READ(IIR); |
| 4139 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4140 | for (;;) { |
Ville Syrjälä | 501e01d | 2014-01-17 11:35:15 +0200 | [diff] [blame] | 4141 | bool irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 4142 | bool blc_event = false; |
| 4143 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4144 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 4145 | * have been cleared after the pipestat interrupt was received. |
| 4146 | * It doesn't set the bit in iir again, but it still produces |
| 4147 | * interrupts (for non-MSI). |
| 4148 | */ |
Daniel Vetter | 222c7f5 | 2014-09-15 14:55:28 +0200 | [diff] [blame] | 4149 | spin_lock(&dev_priv->irq_lock); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4150 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 4151 | i915_handle_error(dev, false, |
| 4152 | "Command parser error, iir 0x%08x", |
| 4153 | iir); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4154 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4155 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4156 | int reg = PIPESTAT(pipe); |
| 4157 | pipe_stats[pipe] = I915_READ(reg); |
| 4158 | |
| 4159 | /* |
| 4160 | * Clear the PIPE*STAT regs before the IIR |
| 4161 | */ |
| 4162 | if (pipe_stats[pipe] & 0x8000ffff) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4163 | I915_WRITE(reg, pipe_stats[pipe]); |
Ville Syrjälä | 501e01d | 2014-01-17 11:35:15 +0200 | [diff] [blame] | 4164 | irq_received = true; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4165 | } |
| 4166 | } |
Daniel Vetter | 222c7f5 | 2014-09-15 14:55:28 +0200 | [diff] [blame] | 4167 | spin_unlock(&dev_priv->irq_lock); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4168 | |
| 4169 | if (!irq_received) |
| 4170 | break; |
| 4171 | |
| 4172 | ret = IRQ_HANDLED; |
| 4173 | |
| 4174 | /* Consume port. Then clear IIR or we'll miss events */ |
Ville Syrjälä | 16c6c56 | 2014-04-01 10:54:36 +0300 | [diff] [blame] | 4175 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
| 4176 | i9xx_hpd_irq_handler(dev); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4177 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 4178 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4179 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 4180 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4181 | if (iir & I915_USER_INTERRUPT) |
| 4182 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 4183 | if (iir & I915_BSD_USER_INTERRUPT) |
| 4184 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 4185 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4186 | for_each_pipe(dev_priv, pipe) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 4187 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 4188 | i915_handle_vblank(dev, pipe, pipe, iir)) |
| 4189 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4190 | |
| 4191 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 4192 | blc_event = true; |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 4193 | |
| 4194 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 4195 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4196 | |
Daniel Vetter | 1f7247c | 2014-09-30 10:56:48 +0200 | [diff] [blame] | 4197 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 4198 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4199 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4200 | |
| 4201 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 4202 | intel_opregion_asle_intr(dev); |
| 4203 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 4204 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 4205 | gmbus_irq_handler(dev); |
| 4206 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4207 | /* With MSI, interrupts are only generated when iir |
| 4208 | * transitions from zero to nonzero. If another bit got |
| 4209 | * set while we were handling the existing iir bits, then |
| 4210 | * we would never get another interrupt. |
| 4211 | * |
| 4212 | * This is fine on non-MSI as well, as if we hit this path |
| 4213 | * we avoid exiting the interrupt handler only to generate |
| 4214 | * another one. |
| 4215 | * |
| 4216 | * Note that for MSI this could cause a stray interrupt report |
| 4217 | * if an interrupt landed in the time between writing IIR and |
| 4218 | * the posting read. This should be rare enough to never |
| 4219 | * trigger the 99% of 100,000 interrupts test for disabling |
| 4220 | * stray interrupts. |
| 4221 | */ |
| 4222 | iir = new_iir; |
| 4223 | } |
| 4224 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 4225 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 4226 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4227 | return ret; |
| 4228 | } |
| 4229 | |
| 4230 | static void i965_irq_uninstall(struct drm_device * dev) |
| 4231 | { |
Jani Nikula | 2d1013d | 2014-03-31 14:27:17 +0300 | [diff] [blame] | 4232 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4233 | int pipe; |
| 4234 | |
| 4235 | if (!dev_priv) |
| 4236 | return; |
| 4237 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 4238 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 4239 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4240 | |
| 4241 | I915_WRITE(HWSTAM, 0xffffffff); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4242 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4243 | I915_WRITE(PIPESTAT(pipe), 0); |
| 4244 | I915_WRITE(IMR, 0xffffffff); |
| 4245 | I915_WRITE(IER, 0x0); |
| 4246 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4247 | for_each_pipe(dev_priv, pipe) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4248 | I915_WRITE(PIPESTAT(pipe), |
| 4249 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); |
| 4250 | I915_WRITE(IIR, I915_READ(IIR)); |
| 4251 | } |
| 4252 | |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 4253 | static void intel_hpd_irq_reenable_work(struct work_struct *work) |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4254 | { |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4255 | struct drm_i915_private *dev_priv = |
| 4256 | container_of(work, typeof(*dev_priv), |
| 4257 | hotplug_reenable_work.work); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4258 | struct drm_device *dev = dev_priv->dev; |
| 4259 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4260 | int i; |
| 4261 | |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4262 | intel_runtime_pm_get(dev_priv); |
| 4263 | |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 4264 | spin_lock_irq(&dev_priv->irq_lock); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4265 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
| 4266 | struct drm_connector *connector; |
| 4267 | |
| 4268 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) |
| 4269 | continue; |
| 4270 | |
| 4271 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 4272 | |
| 4273 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 4274 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4275 | |
| 4276 | if (intel_connector->encoder->hpd_pin == i) { |
| 4277 | if (connector->polled != intel_connector->polled) |
| 4278 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 4279 | connector->name); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4280 | connector->polled = intel_connector->polled; |
| 4281 | if (!connector->polled) |
| 4282 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 4283 | } |
| 4284 | } |
| 4285 | } |
| 4286 | if (dev_priv->display.hpd_irq_setup) |
| 4287 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 4288 | spin_unlock_irq(&dev_priv->irq_lock); |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4289 | |
| 4290 | intel_runtime_pm_put(dev_priv); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 4291 | } |
| 4292 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4293 | /** |
| 4294 | * intel_irq_init - initializes irq support |
| 4295 | * @dev_priv: i915 device instance |
| 4296 | * |
| 4297 | * This function initializes all the irq support including work items, timers |
| 4298 | * and all the vtables. It does not setup the interrupt itself though. |
| 4299 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4300 | void intel_irq_init(struct drm_i915_private *dev_priv) |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4301 | { |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4302 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 4303 | |
| 4304 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4305 | INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 4306 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 4307 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 4308 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 4309 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 4310 | /* Let's track the enabled rps events */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4311 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
Ville Syrjälä | 6c65a58 | 2014-08-29 14:14:07 +0300 | [diff] [blame] | 4312 | /* WaGsvRC0ResidencyMethod:vlv */ |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 4313 | dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; |
| 4314 | else |
| 4315 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 4316 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 4317 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 4318 | i915_hangcheck_elapsed, |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 4319 | (unsigned long) dev); |
Imre Deak | 6323751 | 2014-08-18 15:37:02 +0300 | [diff] [blame] | 4320 | INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, |
Daniel Vetter | 4cb2183 | 2014-09-15 14:55:26 +0200 | [diff] [blame] | 4321 | intel_hpd_irq_reenable_work); |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 4322 | |
Tomas Janousek | 97a19a2 | 2012-12-08 13:48:13 +0100 | [diff] [blame] | 4323 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 4324 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4325 | if (IS_GEN2(dev_priv)) { |
Ville Syrjälä | 4cdb83e | 2013-10-11 21:52:44 +0300 | [diff] [blame] | 4326 | dev->max_vblank_count = 0; |
| 4327 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4328 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4329 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
| 4330 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 4331 | } else { |
| 4332 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
| 4333 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4334 | } |
| 4335 | |
Ville Syrjälä | 21da270 | 2014-08-06 14:49:55 +0300 | [diff] [blame] | 4336 | /* |
| 4337 | * Opt out of the vblank disable timer on everything except gen2. |
| 4338 | * Gen2 doesn't have a hardware frame counter and so depends on |
| 4339 | * vblank interrupts to produce sane vblank seuquence numbers. |
| 4340 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4341 | if (!IS_GEN2(dev_priv)) |
Ville Syrjälä | 21da270 | 2014-08-06 14:49:55 +0300 | [diff] [blame] | 4342 | dev->vblank_disable_immediate = true; |
| 4343 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 4344 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Keith Packard | c3613de | 2011-08-12 17:05:54 -0700 | [diff] [blame] | 4345 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 4346 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
| 4347 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4348 | |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4349 | if (IS_CHERRYVIEW(dev_priv)) { |
Ville Syrjälä | 43f328d | 2014-04-09 20:40:52 +0300 | [diff] [blame] | 4350 | dev->driver->irq_handler = cherryview_irq_handler; |
| 4351 | dev->driver->irq_preinstall = cherryview_irq_preinstall; |
| 4352 | dev->driver->irq_postinstall = cherryview_irq_postinstall; |
| 4353 | dev->driver->irq_uninstall = cherryview_irq_uninstall; |
| 4354 | dev->driver->enable_vblank = valleyview_enable_vblank; |
| 4355 | dev->driver->disable_vblank = valleyview_disable_vblank; |
| 4356 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4357 | } else if (IS_VALLEYVIEW(dev_priv)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 4358 | dev->driver->irq_handler = valleyview_irq_handler; |
| 4359 | dev->driver->irq_preinstall = valleyview_irq_preinstall; |
| 4360 | dev->driver->irq_postinstall = valleyview_irq_postinstall; |
| 4361 | dev->driver->irq_uninstall = valleyview_irq_uninstall; |
| 4362 | dev->driver->enable_vblank = valleyview_enable_vblank; |
| 4363 | dev->driver->disable_vblank = valleyview_disable_vblank; |
Egbert Eich | fa00abe | 2013-02-25 12:06:48 -0500 | [diff] [blame] | 4364 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4365 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4366 | dev->driver->irq_handler = gen8_irq_handler; |
Daniel Vetter | 723761b | 2014-05-22 17:56:34 +0200 | [diff] [blame] | 4367 | dev->driver->irq_preinstall = gen8_irq_reset; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 4368 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
| 4369 | dev->driver->irq_uninstall = gen8_irq_uninstall; |
| 4370 | dev->driver->enable_vblank = gen8_enable_vblank; |
| 4371 | dev->driver->disable_vblank = gen8_disable_vblank; |
| 4372 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4373 | } else if (HAS_PCH_SPLIT(dev)) { |
| 4374 | dev->driver->irq_handler = ironlake_irq_handler; |
Daniel Vetter | 723761b | 2014-05-22 17:56:34 +0200 | [diff] [blame] | 4375 | dev->driver->irq_preinstall = ironlake_irq_reset; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4376 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
| 4377 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 4378 | dev->driver->enable_vblank = ironlake_enable_vblank; |
| 4379 | dev->driver->disable_vblank = ironlake_disable_vblank; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 4380 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4381 | } else { |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4382 | if (INTEL_INFO(dev_priv)->gen == 2) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4383 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
| 4384 | dev->driver->irq_postinstall = i8xx_irq_postinstall; |
| 4385 | dev->driver->irq_handler = i8xx_irq_handler; |
| 4386 | dev->driver->irq_uninstall = i8xx_irq_uninstall; |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4387 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4388 | dev->driver->irq_preinstall = i915_irq_preinstall; |
| 4389 | dev->driver->irq_postinstall = i915_irq_postinstall; |
| 4390 | dev->driver->irq_uninstall = i915_irq_uninstall; |
| 4391 | dev->driver->irq_handler = i915_irq_handler; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4392 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4393 | } else { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 4394 | dev->driver->irq_preinstall = i965_irq_preinstall; |
| 4395 | dev->driver->irq_postinstall = i965_irq_postinstall; |
| 4396 | dev->driver->irq_uninstall = i965_irq_uninstall; |
| 4397 | dev->driver->irq_handler = i965_irq_handler; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 4398 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 4399 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 4400 | dev->driver->enable_vblank = i915_enable_vblank; |
| 4401 | dev->driver->disable_vblank = i915_disable_vblank; |
| 4402 | } |
| 4403 | } |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4404 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4405 | /** |
| 4406 | * intel_hpd_init - initializes and enables hpd support |
| 4407 | * @dev_priv: i915 device instance |
| 4408 | * |
| 4409 | * This function enables the hotplug support. It requires that interrupts have |
| 4410 | * already been enabled with intel_irq_init_hw(). From this point on hotplug and |
| 4411 | * poll request can run concurrently to other code, so locking rules must be |
| 4412 | * obeyed. |
| 4413 | * |
| 4414 | * This is a separate step from interrupt enabling to simplify the locking rules |
| 4415 | * in the driver load and resume code. |
| 4416 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4417 | void intel_hpd_init(struct drm_i915_private *dev_priv) |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4418 | { |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4419 | struct drm_device *dev = dev_priv->dev; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 4420 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 4421 | struct drm_connector *connector; |
| 4422 | int i; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4423 | |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 4424 | for (i = 1; i < HPD_NUM_PINS; i++) { |
| 4425 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
| 4426 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 4427 | } |
| 4428 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 4429 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4430 | connector->polled = intel_connector->polled; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4431 | if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
| 4432 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 4433 | if (intel_connector->mst_port) |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 4434 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 4435 | } |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 4436 | |
| 4437 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 4438 | * just to make the assert_spin_locked checks happy. */ |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4439 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4440 | if (dev_priv->display.hpd_irq_setup) |
| 4441 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | d620743 | 2014-09-15 14:55:27 +0200 | [diff] [blame] | 4442 | spin_unlock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 4443 | } |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4444 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4445 | /** |
| 4446 | * intel_irq_install - enables the hardware interrupt |
| 4447 | * @dev_priv: i915 device instance |
| 4448 | * |
| 4449 | * This function enables the hardware interrupt handling, but leaves the hotplug |
| 4450 | * handling still disabled. It is called after intel_irq_init(). |
| 4451 | * |
| 4452 | * In the driver load and resume code we need working interrupts in a few places |
| 4453 | * but don't want to deal with the hassle of concurrent probe and hotplug |
| 4454 | * workers. Hence the split into this two-stage approach. |
| 4455 | */ |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4456 | int intel_irq_install(struct drm_i915_private *dev_priv) |
| 4457 | { |
| 4458 | /* |
| 4459 | * We enable some interrupt sources in our postinstall hooks, so mark |
| 4460 | * interrupts as enabled _before_ actually enabling them to avoid |
| 4461 | * special cases in our ordering checks. |
| 4462 | */ |
| 4463 | dev_priv->pm.irqs_enabled = true; |
| 4464 | |
| 4465 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); |
| 4466 | } |
| 4467 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4468 | /** |
| 4469 | * intel_irq_uninstall - finilizes all irq handling |
| 4470 | * @dev_priv: i915 device instance |
| 4471 | * |
| 4472 | * This stops interrupt and hotplug handling and unregisters and frees all |
| 4473 | * resources acquired in the init functions. |
| 4474 | */ |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4475 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
| 4476 | { |
| 4477 | drm_irq_uninstall(dev_priv->dev); |
| 4478 | intel_hpd_cancel_work(dev_priv); |
| 4479 | dev_priv->pm.irqs_enabled = false; |
| 4480 | } |
| 4481 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4482 | /** |
| 4483 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling |
| 4484 | * @dev_priv: i915 device instance |
| 4485 | * |
| 4486 | * This function is used to disable interrupts at runtime, both in the runtime |
| 4487 | * pm and the system suspend/resume code. |
| 4488 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4489 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4490 | { |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4491 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4492 | dev_priv->pm.irqs_enabled = false; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4493 | } |
| 4494 | |
Daniel Vetter | fca52a5 | 2014-09-30 10:56:45 +0200 | [diff] [blame] | 4495 | /** |
| 4496 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling |
| 4497 | * @dev_priv: i915 device instance |
| 4498 | * |
| 4499 | * This function is used to enable interrupts at runtime, both in the runtime |
| 4500 | * pm and the system suspend/resume code. |
| 4501 | */ |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4502 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4503 | { |
Daniel Vetter | 2aeb7d3 | 2014-09-30 10:56:43 +0200 | [diff] [blame] | 4504 | dev_priv->pm.irqs_enabled = true; |
Daniel Vetter | b963291 | 2014-09-30 10:56:44 +0200 | [diff] [blame] | 4505 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
| 4506 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 4507 | } |