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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
Tvrtko Ursulin93b81f52015-02-10 17:16:05 +000034#include <uapi/drm/drm_fourcc.h>
Chris Wilsone9b73c62012-12-03 21:03:14 +000035
Jesse Barnes585fb112008-07-29 11:54:06 -070036#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080038#include "intel_ringbuffer.h"
Oscar Mateob20385f2014-07-24 17:04:10 +010039#include "intel_lrc.h"
Ben Widawsky0260c422014-03-22 22:47:21 -070040#include "i915_gem_gtt.h"
Oscar Mateo564ddb22014-08-21 11:40:54 +010041#include "i915_gem_render_state.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070042#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070043#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010044#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020045#include <drm/intel-gtt.h>
Daniel Vetterba8286f2014-09-11 07:43:25 +020046#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
Daniel Vetterd9fc9412014-09-23 15:46:53 +020047#include <drm/drm_gem.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020048#include <linux/backlight.h>
Chris Wilson5cc9ed42014-05-16 14:22:37 +010049#include <linux/hashtable.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070050#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020051#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010052#include <linux/pm_qos.h>
Alex Dai33a732f2015-08-12 15:43:36 +010053#include "intel_guc.h"
Jesse Barnes585fb112008-07-29 11:54:06 -070054
Linus Torvalds1da177e2005-04-16 15:20:36 -070055/* General customization:
56 */
57
Linus Torvalds1da177e2005-04-16 15:20:36 -070058#define DRIVER_NAME "i915"
59#define DRIVER_DESC "Intel Graphics"
Daniel Vetteraed8bbd2015-10-23 11:57:40 +020060#define DRIVER_DATE "20151023"
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
Mika Kuoppalac883ef12014-10-28 17:32:30 +020062#undef WARN_ON
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010063/* Many gcc seem to no see through this and fall over :( */
64#if 0
65#define WARN_ON(x) ({ \
66 bool __i915_warn_cond = (x); \
67 if (__builtin_constant_p(__i915_warn_cond)) \
68 BUILD_BUG_ON(__i915_warn_cond); \
69 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70#else
Dave Gordon4eee4922015-08-17 17:30:52 +010071#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010072#endif
73
Jani Nikulacd9bfac2015-03-12 13:01:12 +020074#undef WARN_ON_ONCE
Dave Gordon4eee4922015-08-17 17:30:52 +010075#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
Jani Nikulacd9bfac2015-03-12 13:01:12 +020076
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010077#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
78 (long) (x), __func__);
Mika Kuoppalac883ef12014-10-28 17:32:30 +020079
Rob Clarke2c719b2014-12-15 13:56:32 -050080/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
81 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
82 * which may not necessarily be a user visible problem. This will either
83 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
84 * enable distros and users to tailor their preferred amount of i915 abrt
85 * spam.
86 */
87#define I915_STATE_WARN(condition, format...) ({ \
88 int __ret_warn_on = !!(condition); \
89 if (unlikely(__ret_warn_on)) { \
90 if (i915.verbose_state_checks) \
Jani Nikula2f3408c2015-01-12 15:45:31 +020091 WARN(1, format); \
Rob Clarke2c719b2014-12-15 13:56:32 -050092 else \
93 DRM_ERROR(format); \
94 } \
95 unlikely(__ret_warn_on); \
96})
97
98#define I915_STATE_WARN_ON(condition) ({ \
99 int __ret_warn_on = !!(condition); \
100 if (unlikely(__ret_warn_on)) { \
101 if (i915.verbose_state_checks) \
Jani Nikula2f3408c2015-01-12 15:45:31 +0200102 WARN(1, "WARN_ON(" #condition ")\n"); \
Rob Clarke2c719b2014-12-15 13:56:32 -0500103 else \
104 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 } \
106 unlikely(__ret_warn_on); \
107})
Jesse Barnes317c35d2008-08-25 15:11:06 -0700108
Jani Nikula42a8ca42015-08-27 16:23:30 +0300109static inline const char *yesno(bool v)
110{
111 return v ? "yes" : "no";
112}
113
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114enum pipe {
Jesse Barnes317c35d2008-08-25 15:11:06 -0700115 INVALID_PIPE = -1,
116 PIPE_A = 0,
117 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800118 PIPE_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200119 _PIPE_EDP,
120 I915_MAX_PIPES = _PIPE_EDP
Jesse Barnes317c35d2008-08-25 15:11:06 -0700121};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800122#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -0700123
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200124enum transcoder {
125 TRANSCODER_A = 0,
126 TRANSCODER_B,
127 TRANSCODER_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200128 TRANSCODER_EDP,
129 I915_MAX_TRANSCODERS
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200130};
131#define transcoder_name(t) ((t) + 'A')
132
Damien Lespiau84139d12014-03-28 00:18:32 +0530133/*
Matt Roper31409e92015-09-24 15:53:09 -0700134 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
135 * number of planes per CRTC. Not all platforms really have this many planes,
136 * which means some arrays of size I915_MAX_PLANES may have unused entries
137 * between the topmost sprite plane and the cursor plane.
Damien Lespiau84139d12014-03-28 00:18:32 +0530138 */
Jesse Barnes80824002009-09-10 15:28:06 -0700139enum plane {
140 PLANE_A = 0,
141 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800142 PLANE_C,
Matt Roper31409e92015-09-24 15:53:09 -0700143 PLANE_CURSOR,
144 I915_MAX_PLANES,
Jesse Barnes80824002009-09-10 15:28:06 -0700145};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800146#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -0800147
Damien Lespiaud615a162014-03-03 17:31:48 +0000148#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
Ville Syrjälä06da8da2013-04-17 17:48:51 +0300149
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300150enum port {
151 PORT_A = 0,
152 PORT_B,
153 PORT_C,
154 PORT_D,
155 PORT_E,
156 I915_MAX_PORTS
157};
158#define port_name(p) ((p) + 'A')
159
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300160#define I915_NUM_PHYS_VLV 2
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800161
162enum dpio_channel {
163 DPIO_CH0,
164 DPIO_CH1
165};
166
167enum dpio_phy {
168 DPIO_PHY0,
169 DPIO_PHY1
170};
171
Paulo Zanonib97186f2013-05-03 12:15:36 -0300172enum intel_display_power_domain {
173 POWER_DOMAIN_PIPE_A,
174 POWER_DOMAIN_PIPE_B,
175 POWER_DOMAIN_PIPE_C,
176 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
177 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
178 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
179 POWER_DOMAIN_TRANSCODER_A,
180 POWER_DOMAIN_TRANSCODER_B,
181 POWER_DOMAIN_TRANSCODER_C,
Imre Deakf52e3532013-10-16 17:25:48 +0300182 POWER_DOMAIN_TRANSCODER_EDP,
Patrik Jakobsson6331a702015-11-09 16:48:21 +0100183 POWER_DOMAIN_PORT_DDI_A_LANES,
184 POWER_DOMAIN_PORT_DDI_B_LANES,
185 POWER_DOMAIN_PORT_DDI_C_LANES,
186 POWER_DOMAIN_PORT_DDI_D_LANES,
187 POWER_DOMAIN_PORT_DDI_E_LANES,
Imre Deak319be8a2014-03-04 19:22:57 +0200188 POWER_DOMAIN_PORT_DSI,
189 POWER_DOMAIN_PORT_CRT,
190 POWER_DOMAIN_PORT_OTHER,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300191 POWER_DOMAIN_VGA,
Imre Deakfbeeaa22013-11-25 17:15:28 +0200192 POWER_DOMAIN_AUDIO,
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -0300193 POWER_DOMAIN_PLLS,
Satheeshakrishna M14071212015-01-16 15:57:51 +0000194 POWER_DOMAIN_AUX_A,
195 POWER_DOMAIN_AUX_B,
196 POWER_DOMAIN_AUX_C,
197 POWER_DOMAIN_AUX_D,
Ville Syrjäläf0ab43e2015-11-09 16:48:19 +0100198 POWER_DOMAIN_GMBUS,
Patrik Jakobssondfa57622015-11-09 16:48:22 +0100199 POWER_DOMAIN_MODESET,
Imre Deakbaa70702013-10-25 17:36:48 +0300200 POWER_DOMAIN_INIT,
Imre Deakbddc7642013-10-16 17:25:49 +0300201
202 POWER_DOMAIN_NUM,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300203};
204
205#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
206#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
207 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300208#define POWER_DOMAIN_TRANSCODER(tran) \
209 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
210 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300211
Egbert Eich1d843f92013-02-25 12:06:49 -0500212enum hpd_pin {
213 HPD_NONE = 0,
Egbert Eich1d843f92013-02-25 12:06:49 -0500214 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
215 HPD_CRT,
216 HPD_SDVO_B,
217 HPD_SDVO_C,
Imre Deakcc24fcd2015-07-21 15:32:45 -0700218 HPD_PORT_A,
Egbert Eich1d843f92013-02-25 12:06:49 -0500219 HPD_PORT_B,
220 HPD_PORT_C,
221 HPD_PORT_D,
Xiong Zhang26951ca2015-08-17 15:55:50 +0800222 HPD_PORT_E,
Egbert Eich1d843f92013-02-25 12:06:49 -0500223 HPD_NUM_PINS
224};
225
Jani Nikulac91711f2015-05-28 15:43:48 +0300226#define for_each_hpd_pin(__pin) \
227 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
228
Jani Nikula5fcece82015-05-27 15:03:42 +0300229struct i915_hotplug {
230 struct work_struct hotplug_work;
231
232 struct {
233 unsigned long last_jiffies;
234 int count;
235 enum {
236 HPD_ENABLED = 0,
237 HPD_DISABLED = 1,
238 HPD_MARK_DISABLED = 2
239 } state;
240 } stats[HPD_NUM_PINS];
241 u32 event_bits;
242 struct delayed_work reenable_work;
243
244 struct intel_digital_port *irq_port[I915_MAX_PORTS];
245 u32 long_port_mask;
246 u32 short_port_mask;
247 struct work_struct dig_port_work;
248
249 /*
250 * if we get a HPD irq from DP and a HPD irq from non-DP
251 * the non-DP HPD could block the workqueue on a mode config
252 * mutex getting, that userspace may have taken. However
253 * userspace is waiting on the DP workqueue to run which is
254 * blocked behind the non-DP one.
255 */
256 struct workqueue_struct *dp_wq;
257};
258
Chris Wilson2a2d5482012-12-03 11:49:06 +0000259#define I915_GEM_GPU_DOMAINS \
260 (I915_GEM_DOMAIN_RENDER | \
261 I915_GEM_DOMAIN_SAMPLER | \
262 I915_GEM_DOMAIN_COMMAND | \
263 I915_GEM_DOMAIN_INSTRUCTION | \
264 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700265
Damien Lespiau055e3932014-08-18 13:49:10 +0100266#define for_each_pipe(__dev_priv, __p) \
267 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
Damien Lespiaudd740782015-02-28 14:54:08 +0000268#define for_each_plane(__dev_priv, __pipe, __p) \
269 for ((__p) = 0; \
270 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
271 (__p)++)
Damien Lespiau3bdcfc02015-02-28 14:54:09 +0000272#define for_each_sprite(__dev_priv, __p, __s) \
273 for ((__s) = 0; \
274 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
275 (__s)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800276
Damien Lespiaud79b8142014-05-13 23:32:23 +0100277#define for_each_crtc(dev, crtc) \
278 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
279
Maarten Lankhorst27321ae2015-04-21 17:12:52 +0300280#define for_each_intel_plane(dev, intel_plane) \
281 list_for_each_entry(intel_plane, \
282 &dev->mode_config.plane_list, \
283 base.head)
284
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300285#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
286 list_for_each_entry(intel_plane, \
287 &(dev)->mode_config.plane_list, \
288 base.head) \
289 if ((intel_plane)->pipe == (intel_crtc)->pipe)
290
Damien Lespiaud063ae42014-05-13 23:32:21 +0100291#define for_each_intel_crtc(dev, intel_crtc) \
292 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
293
Damien Lespiaub2784e12014-08-05 11:29:37 +0100294#define for_each_intel_encoder(dev, intel_encoder) \
295 list_for_each_entry(intel_encoder, \
296 &(dev)->mode_config.encoder_list, \
297 base.head)
298
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +0200299#define for_each_intel_connector(dev, intel_connector) \
300 list_for_each_entry(intel_connector, \
301 &dev->mode_config.connector_list, \
302 base.head)
303
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200304#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
305 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
306 if ((intel_encoder)->base.crtc == (__crtc))
307
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800308#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
309 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
310 if ((intel_connector)->base.encoder == (__encoder))
311
Borun Fub04c5bd2014-07-12 10:02:27 +0530312#define for_each_power_domain(domain, mask) \
313 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
314 if ((1 << (domain)) & (mask))
315
Daniel Vettere7b903d2013-06-05 13:34:14 +0200316struct drm_i915_private;
Chris Wilsonad46cb52014-08-07 14:20:40 +0100317struct i915_mm_struct;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100318struct i915_mmu_object;
Daniel Vettere7b903d2013-06-05 13:34:14 +0200319
Chris Wilsona6f766f2015-04-27 13:41:20 +0100320struct drm_i915_file_private {
321 struct drm_i915_private *dev_priv;
322 struct drm_file *file;
323
324 struct {
325 spinlock_t lock;
326 struct list_head request_list;
Chris Wilsond0bc54f2015-05-21 21:01:48 +0100327/* 20ms is a fairly arbitrary limit (greater than the average frame time)
328 * chosen to prevent the CPU getting more than a frame ahead of the GPU
329 * (when using lax throttling for the frontbuffer). We also use it to
330 * offer free GPU waitboosts for severely congested workloads.
331 */
332#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
Chris Wilsona6f766f2015-04-27 13:41:20 +0100333 } mm;
334 struct idr context_idr;
335
Chris Wilson2e1b8732015-04-27 13:41:22 +0100336 struct intel_rps_client {
337 struct list_head link;
338 unsigned boosts;
339 } rps;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100340
Chris Wilson2e1b8732015-04-27 13:41:22 +0100341 struct intel_engine_cs *bsd_ring;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100342};
343
Daniel Vettere2b78262013-06-07 23:10:03 +0200344enum intel_dpll_id {
345 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
346 /* real shared dpll ids must be >= 0 */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300347 DPLL_ID_PCH_PLL_A = 0,
348 DPLL_ID_PCH_PLL_B = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000349 /* hsw/bdw */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300350 DPLL_ID_WRPLL1 = 0,
351 DPLL_ID_WRPLL2 = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000352 /* skl */
353 DPLL_ID_SKL_DPLL1 = 0,
354 DPLL_ID_SKL_DPLL2 = 1,
355 DPLL_ID_SKL_DPLL3 = 2,
Daniel Vettere2b78262013-06-07 23:10:03 +0200356};
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000357#define I915_NUM_PLLS 3
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100358
Daniel Vetter53589012013-06-05 13:34:16 +0200359struct intel_dpll_hw_state {
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100360 /* i9xx, pch plls */
Daniel Vetter66e985c2013-06-05 13:34:20 +0200361 uint32_t dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +0200362 uint32_t dpll_md;
Daniel Vetter66e985c2013-06-05 13:34:20 +0200363 uint32_t fp0;
364 uint32_t fp1;
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100365
366 /* hsw, bdw */
Daniel Vetterd452c5b2014-07-04 11:27:39 -0300367 uint32_t wrpll;
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +0000368
369 /* skl */
370 /*
371 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
Damien Lespiau71cd8422015-04-30 16:39:17 +0100372 * lower part of ctrl1 and they get shifted into position when writing
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +0000373 * the register. This allows us to easily compare the state to share
374 * the DPLL.
375 */
376 uint32_t ctrl1;
377 /* HDMI only, 0 when used for DP */
378 uint32_t cfgcr1, cfgcr2;
Satheeshakrishna Mdfb82402014-08-22 09:49:09 +0530379
380 /* bxt */
Imre Deak05712c12015-06-18 17:25:54 +0300381 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
382 pcsdw12;
Daniel Vetter53589012013-06-05 13:34:16 +0200383};
384
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200385struct intel_shared_dpll_config {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +0200386 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200387 struct intel_dpll_hw_state hw_state;
388};
389
390struct intel_shared_dpll {
391 struct intel_shared_dpll_config config;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +0200392
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393 int active; /* count of number of active CRTCs (i.e. DPMS on) */
394 bool on; /* is the PLL actually active? Disabled during modeset */
Daniel Vetter46edb022013-06-05 13:34:12 +0200395 const char *name;
396 /* should match the index in the dev_priv->shared_dplls array */
397 enum intel_dpll_id id;
Daniel Vetter96f61282014-06-25 22:01:58 +0300398 /* The mode_set hook is optional and should be used together with the
399 * intel_prepare_shared_dpll function. */
Daniel Vetter15bdd4c2013-06-05 13:34:23 +0200400 void (*mode_set)(struct drm_i915_private *dev_priv,
401 struct intel_shared_dpll *pll);
Daniel Vettere7b903d2013-06-05 13:34:14 +0200402 void (*enable)(struct drm_i915_private *dev_priv,
403 struct intel_shared_dpll *pll);
404 void (*disable)(struct drm_i915_private *dev_priv,
405 struct intel_shared_dpll *pll);
Daniel Vetter53589012013-06-05 13:34:16 +0200406 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
407 struct intel_shared_dpll *pll,
408 struct intel_dpll_hw_state *hw_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000411#define SKL_DPLL0 0
412#define SKL_DPLL1 1
413#define SKL_DPLL2 2
414#define SKL_DPLL3 3
415
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100416/* Used by dp and fdi links */
417struct intel_link_m_n {
418 uint32_t tu;
419 uint32_t gmch_m;
420 uint32_t gmch_n;
421 uint32_t link_m;
422 uint32_t link_n;
423};
424
425void intel_link_compute_m_n(int bpp, int nlanes,
426 int pixel_clock, int link_clock,
427 struct intel_link_m_n *m_n);
428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429/* Interface history:
430 *
431 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100432 * 1.2: Add Power Management
433 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100434 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000435 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000436 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
437 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 */
439#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000440#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441#define DRIVER_PATCHLEVEL 0
442
Chris Wilson23bc5982010-09-29 16:10:57 +0100443#define WATCH_LISTS 0
Eric Anholt673a3942008-07-30 12:06:12 -0700444
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700445struct opregion_header;
446struct opregion_acpi;
447struct opregion_swsci;
448struct opregion_asle;
449
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100450struct intel_opregion {
Williams, Dan J115719f2015-10-12 21:12:57 +0000451 struct opregion_header *header;
452 struct opregion_acpi *acpi;
453 struct opregion_swsci *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300454 u32 swsci_gbda_sub_functions;
455 u32 swsci_sbcb_sub_functions;
Williams, Dan J115719f2015-10-12 21:12:57 +0000456 struct opregion_asle *asle;
457 void *vbt;
458 u32 *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200459 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100460};
Chris Wilson44834a62010-08-19 16:09:23 +0100461#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100462
Chris Wilson6ef3d422010-08-04 20:26:07 +0100463struct intel_overlay;
464struct intel_overlay_error_state;
465
Jesse Barnesde151cf2008-11-12 10:03:55 -0800466#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300467#define I915_MAX_NUM_FENCES 32
468/* 32 fences + sign bit for FENCE_REG_NONE */
469#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800470
471struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200472 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000473 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100474 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800475};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000476
yakui_zhao9b9d1722009-05-31 17:17:17 +0800477struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100478 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800479 u8 dvo_port;
480 u8 slave_addr;
481 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100482 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400483 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800484};
485
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000486struct intel_display_error_state;
487
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700488struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200489 struct kref ref;
Ben Widawsky585b0282014-01-30 00:19:37 -0800490 struct timeval time;
491
Mika Kuoppalacb383002014-02-25 17:11:25 +0200492 char error_msg[128];
Chris Wilsoneb5be9d2015-08-07 20:24:15 +0100493 int iommu;
Mika Kuoppala48b031e2014-02-25 17:11:27 +0200494 u32 reset_count;
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200495 u32 suspend_count;
Mika Kuoppalacb383002014-02-25 17:11:25 +0200496
Ben Widawsky585b0282014-01-30 00:19:37 -0800497 /* Generic register state */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700498 u32 eir;
499 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700500 u32 ier;
Rodrigo Vivi885ea5a2014-08-05 10:07:13 -0700501 u32 gtier[4];
Ben Widawskyb9a39062012-06-04 14:42:52 -0700502 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000503 u32 derrmr;
504 u32 forcewake;
Ben Widawsky585b0282014-01-30 00:19:37 -0800505 u32 error; /* gen6+ */
506 u32 err_int; /* gen7 */
Mika Kuoppala6c826f32015-03-24 14:54:19 +0200507 u32 fault_data0; /* gen8, gen9 */
508 u32 fault_data1; /* gen8, gen9 */
Ben Widawsky585b0282014-01-30 00:19:37 -0800509 u32 done_reg;
Ben Widawsky91ec5d12014-01-30 00:19:39 -0800510 u32 gac_eco;
511 u32 gam_ecochk;
512 u32 gab_ctl;
513 u32 gfx_mode;
Ben Widawsky585b0282014-01-30 00:19:37 -0800514 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Ben Widawsky585b0282014-01-30 00:19:37 -0800515 u64 fence[I915_MAX_NUM_FENCES];
516 struct intel_overlay_error_state *overlay;
517 struct intel_display_error_state *display;
Ben Widawsky0ca36d72014-06-30 09:53:41 -0700518 struct drm_i915_error_object *semaphore_obj;
Ben Widawsky585b0282014-01-30 00:19:37 -0800519
Chris Wilson52d39a22012-02-15 11:25:37 +0000520 struct drm_i915_error_ring {
Chris Wilson372fbb82014-01-27 13:52:34 +0000521 bool valid;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800522 /* Software tracked state */
523 bool waiting;
524 int hangcheck_score;
525 enum intel_ring_hangcheck_action hangcheck_action;
526 int num_requests;
527
528 /* our own tracking of ring head and tail */
529 u32 cpu_ring_head;
530 u32 cpu_ring_tail;
531
532 u32 semaphore_seqno[I915_NUM_RINGS - 1];
533
534 /* Register state */
Chris Wilson94f8cf12015-04-07 16:20:47 +0100535 u32 start;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800536 u32 tail;
537 u32 head;
538 u32 ctl;
539 u32 hws;
540 u32 ipeir;
541 u32 ipehr;
542 u32 instdone;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800543 u32 bbstate;
544 u32 instpm;
545 u32 instps;
546 u32 seqno;
547 u64 bbaddr;
Chris Wilson50877442014-03-21 12:41:53 +0000548 u64 acthd;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800549 u32 fault_reg;
Ben Widawsky13ffadd2014-04-01 16:31:07 -0700550 u64 faddr;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800551 u32 rc_psmi; /* sleep state */
552 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
553
Chris Wilson52d39a22012-02-15 11:25:37 +0000554 struct drm_i915_error_object {
555 int page_count;
Michel Thierrye1f12322015-07-29 17:23:56 +0100556 u64 gtt_offset;
Chris Wilson52d39a22012-02-15 11:25:37 +0000557 u32 *pages[0];
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200558 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800559
Chris Wilson52d39a22012-02-15 11:25:37 +0000560 struct drm_i915_error_request {
561 long jiffies;
562 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000563 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000564 } *requests;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800565
566 struct {
567 u32 gfx_mode;
568 union {
569 u64 pdp[4];
570 u32 pp_dir_base;
571 };
572 } vm_info;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200573
574 pid_t pid;
575 char comm[TASK_COMM_LEN];
Chris Wilson52d39a22012-02-15 11:25:37 +0000576 } ring[I915_NUM_RINGS];
Chris Wilson3a448732014-08-12 20:05:47 +0100577
Chris Wilson9df30792010-02-18 10:24:56 +0000578 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000579 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000580 u32 name;
Chris Wilsonb4716182015-04-27 13:41:17 +0100581 u32 rseqno[I915_NUM_RINGS], wseqno;
Michel Thierrye1f12322015-07-29 17:23:56 +0100582 u64 gtt_offset;
Chris Wilson9df30792010-02-18 10:24:56 +0000583 u32 read_domains;
584 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200585 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000586 s32 pinned:2;
587 u32 tiling:2;
588 u32 dirty:1;
589 u32 purgeable:1;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100590 u32 userptr:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100591 s32 ring:4;
Chris Wilsonf56383c2013-09-25 10:23:19 +0100592 u32 cache_level:3;
Ben Widawsky95f53012013-07-31 17:00:15 -0700593 } **active_bo, **pinned_bo;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800594
Ben Widawsky95f53012013-07-31 17:00:15 -0700595 u32 *active_bo_count, *pinned_bo_count;
Chris Wilson3a448732014-08-12 20:05:47 +0100596 u32 vm_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700597};
598
Jani Nikula7bd688c2013-11-08 16:48:56 +0200599struct intel_connector;
Jani Nikula820d2d72014-10-27 16:26:47 +0200600struct intel_encoder;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200601struct intel_crtc_state;
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000602struct intel_initial_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100603struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200604struct intel_limit;
605struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100606
Jesse Barnese70236a2009-09-21 10:42:27 -0700607struct drm_i915_display_funcs {
Jesse Barnese70236a2009-09-21 10:42:27 -0700608 int (*get_display_clock_speed)(struct drm_device *dev);
609 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200610 /**
611 * find_dpll() - Find the best values for the PLL
612 * @limit: limits for the PLL
613 * @crtc: current CRTC
614 * @target: target frequency in kHz
615 * @refclk: reference clock frequency in kHz
616 * @match_clock: if provided, @best_clock P divider must
617 * match the P divider from @match_clock
618 * used for LVDS downclocking
619 * @best_clock: best PLL values found
620 *
621 * Returns true on success, false on failure.
622 */
623 bool (*find_dpll)(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200624 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200625 int target, int refclk,
626 struct dpll *match_clock,
627 struct dpll *best_clock);
Matt Roper86c8bbb2015-09-24 15:53:16 -0700628 int (*compute_pipe_wm)(struct intel_crtc *crtc,
629 struct drm_atomic_state *state);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300630 void (*update_wm)(struct drm_crtc *crtc);
Maarten Lankhorst27c329e2015-06-15 12:33:56 +0200631 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
632 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100633 /* Returns the active state of the crtc, and if the crtc is active,
634 * fills out the pipe-config with the hw state. */
635 bool (*get_pipe_config)(struct intel_crtc *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200636 struct intel_crtc_state *);
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000637 void (*get_initial_plane_config)(struct intel_crtc *,
638 struct intel_initial_plane_config *);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +0200639 int (*crtc_compute_clock)(struct intel_crtc *crtc,
640 struct intel_crtc_state *crtc_state);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200641 void (*crtc_enable)(struct drm_crtc *crtc);
642 void (*crtc_disable)(struct drm_crtc *crtc);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200643 void (*audio_codec_enable)(struct drm_connector *connector,
644 struct intel_encoder *encoder,
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300645 const struct drm_display_mode *adjusted_mode);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200646 void (*audio_codec_disable)(struct intel_encoder *encoder);
Jesse Barnes674cf962011-04-28 14:27:04 -0700647 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700648 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700649 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
650 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700651 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +0100652 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -0700653 uint32_t flags);
Daniel Vetter29b9bde2014-04-24 23:55:01 +0200654 void (*update_primary_plane)(struct drm_crtc *crtc,
655 struct drm_framebuffer *fb,
656 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100657 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700658 /* clock updates for mode set */
659 /* cursor updates */
660 /* render clock increase/decrease */
661 /* display clock increase/decrease */
662 /* pll clock increase/decrease */
Jesse Barnese70236a2009-09-21 10:42:27 -0700663};
664
Mika Kuoppala48c10262015-01-16 11:34:41 +0200665enum forcewake_domain_id {
666 FW_DOMAIN_ID_RENDER = 0,
667 FW_DOMAIN_ID_BLITTER,
668 FW_DOMAIN_ID_MEDIA,
669
670 FW_DOMAIN_ID_COUNT
671};
672
673enum forcewake_domains {
674 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
675 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
676 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
677 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
678 FORCEWAKE_BLITTER |
679 FORCEWAKE_MEDIA)
680};
681
Chris Wilson907b28c2013-07-19 20:36:52 +0100682struct intel_uncore_funcs {
Deepak Sc8d9a592013-11-23 14:55:42 +0530683 void (*force_wake_get)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200684 enum forcewake_domains domains);
Deepak Sc8d9a592013-11-23 14:55:42 +0530685 void (*force_wake_put)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200686 enum forcewake_domains domains);
Ben Widawsky0b274482013-10-04 21:22:51 -0700687
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200688 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
689 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
690 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
691 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
Ben Widawsky0b274482013-10-04 21:22:51 -0700692
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200693 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700694 uint8_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200695 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700696 uint16_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200697 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700698 uint32_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200699 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700700 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300701};
702
Chris Wilson907b28c2013-07-19 20:36:52 +0100703struct intel_uncore {
704 spinlock_t lock; /** lock is also taken in irq contexts. */
705
706 struct intel_uncore_funcs funcs;
707
708 unsigned fifo_count;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200709 enum forcewake_domains fw_domains;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100710
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200711 struct intel_uncore_forcewake_domain {
712 struct drm_i915_private *i915;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200713 enum forcewake_domain_id id;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200714 unsigned wake_count;
715 struct timer_list timer;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200716 i915_reg_t reg_set;
Mika Kuoppala05a2fb12015-01-19 16:20:43 +0200717 u32 val_set;
718 u32 val_clear;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200719 i915_reg_t reg_ack;
720 i915_reg_t reg_post;
Mika Kuoppala05a2fb12015-01-19 16:20:43 +0200721 u32 val_reset;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200722 } fw_domain[FW_DOMAIN_ID_COUNT];
Chris Wilson907b28c2013-07-19 20:36:52 +0100723};
724
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200725/* Iterate over initialised fw domains */
726#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
727 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
728 (i__) < FW_DOMAIN_ID_COUNT; \
729 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
730 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
731
732#define for_each_fw_domain(domain__, dev_priv__, i__) \
733 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
734
Damien Lespiaub6e7d892015-10-27 14:46:59 +0200735#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
736#define CSR_VERSION_MAJOR(version) ((version) >> 16)
737#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
738
Daniel Vettereb805622015-05-04 14:58:44 +0200739struct intel_csr {
Daniel Vetter8144ac52015-10-28 23:59:04 +0200740 struct work_struct work;
Daniel Vettereb805622015-05-04 14:58:44 +0200741 const char *fw_path;
Animesh Mannaa7f749f2015-08-03 21:55:32 +0530742 uint32_t *dmc_payload;
Daniel Vettereb805622015-05-04 14:58:44 +0200743 uint32_t dmc_fw_size;
Damien Lespiaub6e7d892015-10-27 14:46:59 +0200744 uint32_t version;
Daniel Vettereb805622015-05-04 14:58:44 +0200745 uint32_t mmio_count;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200746 i915_reg_t mmioaddr[8];
Daniel Vettereb805622015-05-04 14:58:44 +0200747 uint32_t mmiodata[8];
748};
749
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100750#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
751 func(is_mobile) sep \
752 func(is_i85x) sep \
753 func(is_i915g) sep \
754 func(is_i945gm) sep \
755 func(is_g33) sep \
756 func(need_gfx_hws) sep \
757 func(is_g4x) sep \
758 func(is_pineview) sep \
759 func(is_broadwater) sep \
760 func(is_crestline) sep \
761 func(is_ivybridge) sep \
762 func(is_valleyview) sep \
763 func(is_haswell) sep \
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530764 func(is_skylake) sep \
Rodrigo Vivi7526ac12015-10-27 10:14:54 -0700765 func(is_broxton) sep \
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700766 func(is_kabylake) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700767 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100768 func(has_fbc) sep \
769 func(has_pipe_cxsr) sep \
770 func(has_hotplug) sep \
771 func(cursor_needs_physical) sep \
772 func(has_overlay) sep \
773 func(overlay_needs_physical) sep \
774 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100775 func(has_llc) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100776 func(has_ddi) sep \
777 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200778
Damien Lespiaua587f772013-04-22 18:40:38 +0100779#define DEFINE_FLAG(name) u8 name:1
780#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200781
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500782struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200783 u32 display_mmio_offset;
Chris Wilson87f1f462014-08-09 19:18:42 +0100784 u16 device_id;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700785 u8 num_pipes:3;
Damien Lespiaud615a162014-03-03 17:31:48 +0000786 u8 num_sprites[I915_MAX_PIPES];
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000787 u8 gen;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700788 u8 ring_mask; /* Rings supported by the HW */
Damien Lespiaua587f772013-04-22 18:40:38 +0100789 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200790 /* Register offsets for the various display pipes and transcoders */
791 int pipe_offsets[I915_MAX_TRANSCODERS];
792 int trans_offsets[I915_MAX_TRANSCODERS];
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200793 int palette_offsets[I915_MAX_PIPES];
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300794 int cursor_offsets[I915_MAX_PIPES];
Jeff McGee38732182015-02-13 10:27:54 -0600795
796 /* Slice/subslice/EU info */
797 u8 slice_total;
798 u8 subslice_total;
799 u8 subslice_per_slice;
800 u8 eu_total;
801 u8 eu_per_subslice;
Damien Lespiaub7668792015-02-14 18:30:29 +0000802 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
803 u8 subslice_7eu[3];
Jeff McGee38732182015-02-13 10:27:54 -0600804 u8 has_slice_pg:1;
805 u8 has_subslice_pg:1;
806 u8 has_eu_pg:1;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500807};
808
Damien Lespiaua587f772013-04-22 18:40:38 +0100809#undef DEFINE_FLAG
810#undef SEP_SEMICOLON
811
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800812enum i915_cache_level {
813 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100814 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
815 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
816 caches, eg sampler/render caches, and the
817 large Last-Level-Cache. LLC is coherent with
818 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100819 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800820};
821
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300822struct i915_ctx_hang_stats {
823 /* This context had batch pending when hang was declared */
824 unsigned batch_pending;
825
826 /* This context had batch active when hang was declared */
827 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300828
829 /* Time when this context was last blamed for a GPU reset */
830 unsigned long guilty_ts;
831
Chris Wilson676fa572014-12-24 08:13:39 -0800832 /* If the contexts causes a second GPU hang within this time,
833 * it is permanently banned from submitting any more work.
834 */
835 unsigned long ban_period_seconds;
836
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300837 /* This context is banned to submit more work */
838 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300839};
Ben Widawsky40521052012-06-04 14:42:43 -0700840
841/* This must match up with the value previously used for execbuf2.rsvd1. */
Oscar Mateo821d66d2014-07-03 16:28:00 +0100842#define DEFAULT_CONTEXT_HANDLE 0
David Weinehallb1b38272015-05-20 17:00:13 +0300843
844#define CONTEXT_NO_ZEROMAP (1<<0)
Oscar Mateo31b7a882014-07-03 16:28:01 +0100845/**
846 * struct intel_context - as the name implies, represents a context.
847 * @ref: reference count.
848 * @user_handle: userspace tracking identity for this context.
849 * @remap_slice: l3 row remapping information.
David Weinehallb1b38272015-05-20 17:00:13 +0300850 * @flags: context specific flags:
851 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100852 * @file_priv: filp associated with this context (NULL for global default
853 * context).
854 * @hang_stats: information about the role of this context in possible GPU
855 * hangs.
Tvrtko Ursulin7df113e2015-04-17 12:49:07 +0100856 * @ppgtt: virtual memory space used by this context.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100857 * @legacy_hw_ctx: render context backing object and whether it is correctly
858 * initialized (legacy ring submission mechanism only).
859 * @link: link in the global list of contexts.
860 *
861 * Contexts are memory images used by the hardware to store copies of their
862 * internal state.
863 */
Oscar Mateo273497e2014-05-22 14:13:37 +0100864struct intel_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300865 struct kref ref;
Oscar Mateo821d66d2014-07-03 16:28:00 +0100866 int user_handle;
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700867 uint8_t remap_slice;
Chris Wilson9ea4fee2015-05-05 09:17:29 +0100868 struct drm_i915_private *i915;
David Weinehallb1b38272015-05-20 17:00:13 +0300869 int flags;
Ben Widawsky40521052012-06-04 14:42:43 -0700870 struct drm_i915_file_private *file_priv;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300871 struct i915_ctx_hang_stats hang_stats;
Daniel Vetterae6c4802014-08-06 15:04:53 +0200872 struct i915_hw_ppgtt *ppgtt;
Ben Widawskya33afea2013-09-17 21:12:45 -0700873
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100874 /* Legacy ring buffer submission */
Oscar Mateoea0c76f2014-07-03 16:27:59 +0100875 struct {
876 struct drm_i915_gem_object *rcs_state;
877 bool initialized;
878 } legacy_hw_ctx;
879
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100880 /* Execlists */
881 struct {
882 struct drm_i915_gem_object *state;
Oscar Mateo84c23772014-07-24 17:04:15 +0100883 struct intel_ringbuffer *ringbuf;
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +0200884 int pin_count;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100885 } engine[I915_NUM_RINGS];
886
Ben Widawskya33afea2013-09-17 21:12:45 -0700887 struct list_head link;
Ben Widawsky40521052012-06-04 14:42:43 -0700888};
889
Paulo Zanonia4001f12015-02-13 17:23:44 -0200890enum fb_op_origin {
891 ORIGIN_GTT,
892 ORIGIN_CPU,
893 ORIGIN_CS,
894 ORIGIN_FLIP,
Paulo Zanoni74b4ea12015-07-14 16:29:14 -0300895 ORIGIN_DIRTYFB,
Paulo Zanonia4001f12015-02-13 17:23:44 -0200896};
897
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700898struct i915_fbc {
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300899 /* This is always the inner lock when overlapping with struct_mutex and
900 * it's the outer lock when overlapping with stolen_lock. */
901 struct mutex lock;
Jani Nikula60ee5cd2015-02-05 12:04:27 +0200902 unsigned long uncompressed_size;
Ben Widawsky5e59f712014-06-30 10:41:24 -0700903 unsigned threshold;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700904 unsigned int fb_id;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200905 unsigned int possible_framebuffer_bits;
906 unsigned int busy_bits;
Paulo Zanonie35fef22015-02-09 14:46:29 -0200907 struct intel_crtc *crtc;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700908 int y;
909
Ben Widawskyc4213882014-06-19 12:06:10 -0700910 struct drm_mm_node compressed_fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700911 struct drm_mm_node *compressed_llb;
912
Rodrigo Vivida46f932014-08-01 02:04:45 -0700913 bool false_color;
914
Paulo Zanoni9adccc62014-09-19 16:04:55 -0300915 /* Tracks whether the HW is actually enabled, not whether the feature is
916 * possible. */
917 bool enabled;
918
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700919 struct intel_fbc_work {
920 struct delayed_work work;
Paulo Zanoni220285f2015-07-07 15:26:05 -0300921 struct intel_crtc *crtc;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700922 struct drm_framebuffer *fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700923 } *fbc_work;
924
Paulo Zanonibf6189c2015-10-27 14:50:03 -0200925 const char *no_fbc_reason;
Paulo Zanoniff2a3112015-07-07 15:26:03 -0300926
Paulo Zanoni7733b492015-07-07 15:26:04 -0300927 bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
Paulo Zanoni220285f2015-07-07 15:26:05 -0300928 void (*enable_fbc)(struct intel_crtc *crtc);
Paulo Zanoni7733b492015-07-07 15:26:04 -0300929 void (*disable_fbc)(struct drm_i915_private *dev_priv);
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800930};
931
Vandana Kannan96178ee2015-01-10 02:25:56 +0530932/**
933 * HIGH_RR is the highest eDP panel refresh rate read from EDID
934 * LOW_RR is the lowest eDP panel refresh rate found from EDID
935 * parsing for same resolution.
936 */
937enum drrs_refresh_rate_type {
938 DRRS_HIGH_RR,
939 DRRS_LOW_RR,
940 DRRS_MAX_RR, /* RR count */
941};
942
943enum drrs_support_type {
944 DRRS_NOT_SUPPORTED = 0,
945 STATIC_DRRS_SUPPORT = 1,
946 SEAMLESS_DRRS_SUPPORT = 2
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530947};
948
Daniel Vetter2807cf62014-07-11 10:30:11 -0700949struct intel_dp;
Vandana Kannan96178ee2015-01-10 02:25:56 +0530950struct i915_drrs {
951 struct mutex mutex;
952 struct delayed_work work;
953 struct intel_dp *dp;
954 unsigned busy_frontbuffer_bits;
955 enum drrs_refresh_rate_type refresh_rate_type;
956 enum drrs_support_type type;
957};
958
Rodrigo Vivia031d702013-10-03 16:15:06 -0300959struct i915_psr {
Daniel Vetterf0355c42014-07-11 10:30:15 -0700960 struct mutex lock;
Rodrigo Vivia031d702013-10-03 16:15:06 -0300961 bool sink_support;
962 bool source_ok;
Daniel Vetter2807cf62014-07-11 10:30:11 -0700963 struct intel_dp *enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -0700964 bool active;
965 struct delayed_work work;
Daniel Vetter9ca15302014-07-11 10:30:16 -0700966 unsigned busy_frontbuffer_bits;
Sonika Jindal474d1ec2015-04-02 11:02:44 +0530967 bool psr2_support;
968 bool aux_frame_sync;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300969};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700970
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800971enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300972 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800973 PCH_IBX, /* Ibexpeak PCH */
974 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300975 PCH_LPT, /* Lynxpoint PCH */
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530976 PCH_SPT, /* Sunrisepoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700977 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800978};
979
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200980enum intel_sbi_destination {
981 SBI_ICLK,
982 SBI_MPHY,
983};
984
Jesse Barnesb690e962010-07-19 13:53:12 -0700985#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700986#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100987#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Scot Doyle9c72cc62014-07-03 23:27:50 +0000988#define QUIRK_BACKLIGHT_PRESENT (1<<3)
Ville Syrjäläb6b5d042014-08-15 01:22:07 +0300989#define QUIRK_PIPEB_FORCE (1<<4)
Daniel Vetter656bfa32014-11-20 09:26:30 +0100990#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
Jesse Barnesb690e962010-07-19 13:53:12 -0700991
Dave Airlie8be48d92010-03-30 05:34:14 +0000992struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100993struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000994
Daniel Vetterc2b91522012-02-14 22:37:19 +0100995struct intel_gmbus {
996 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000997 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100998 u32 reg0;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200999 i915_reg_t gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +01001000 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +01001001 struct drm_i915_private *dev_priv;
1002};
1003
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001004struct i915_suspend_saved_registers {
Keith Packarde948e992008-05-07 12:27:53 +10001005 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001006 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -07001007 u32 savePP_ON_DELAYS;
1008 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001009 u32 savePP_ON;
1010 u32 savePP_OFF;
1011 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -07001012 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001013 u32 saveFBC_CONTROL;
Keith Packard1f84e552008-02-16 19:19:29 -08001014 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -08001015 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001016 u32 saveSWF0[16];
1017 u32 saveSWF1[16];
Ville Syrjälä85fa7922015-09-18 20:03:43 +03001018 u32 saveSWF3[3];
Daniel Vetter4b9de732011-10-09 21:52:02 +02001019 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Adam Jacksoncda2bb72011-07-26 16:53:06 -04001020 u32 savePCH_PORT_HOTPLUG;
Jesse Barnes9f49c372014-12-10 12:16:05 -08001021 u16 saveGCDGMBUS;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001022};
Daniel Vetterc85aa882012-11-02 19:55:03 +01001023
Imre Deakddeea5b2014-05-05 15:19:56 +03001024struct vlv_s0ix_state {
1025 /* GAM */
1026 u32 wr_watermark;
1027 u32 gfx_prio_ctrl;
1028 u32 arb_mode;
1029 u32 gfx_pend_tlb0;
1030 u32 gfx_pend_tlb1;
1031 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1032 u32 media_max_req_count;
1033 u32 gfx_max_req_count;
1034 u32 render_hwsp;
1035 u32 ecochk;
1036 u32 bsd_hwsp;
1037 u32 blt_hwsp;
1038 u32 tlb_rd_addr;
1039
1040 /* MBC */
1041 u32 g3dctl;
1042 u32 gsckgctl;
1043 u32 mbctl;
1044
1045 /* GCP */
1046 u32 ucgctl1;
1047 u32 ucgctl3;
1048 u32 rcgctl1;
1049 u32 rcgctl2;
1050 u32 rstctl;
1051 u32 misccpctl;
1052
1053 /* GPM */
1054 u32 gfxpause;
1055 u32 rpdeuhwtc;
1056 u32 rpdeuc;
1057 u32 ecobus;
1058 u32 pwrdwnupctl;
1059 u32 rp_down_timeout;
1060 u32 rp_deucsw;
1061 u32 rcubmabdtmr;
1062 u32 rcedata;
1063 u32 spare2gh;
1064
1065 /* Display 1 CZ domain */
1066 u32 gt_imr;
1067 u32 gt_ier;
1068 u32 pm_imr;
1069 u32 pm_ier;
1070 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1071
1072 /* GT SA CZ domain */
1073 u32 tilectl;
1074 u32 gt_fifoctl;
1075 u32 gtlc_wake_ctrl;
1076 u32 gtlc_survive;
1077 u32 pmwgicz;
1078
1079 /* Display 2 CZ domain */
1080 u32 gu_ctl0;
1081 u32 gu_ctl1;
Jesse Barnes9c252102015-04-01 14:22:57 -07001082 u32 pcbr;
Imre Deakddeea5b2014-05-05 15:19:56 +03001083 u32 clock_gate_dis2;
1084};
1085
Chris Wilsonbf225f22014-07-10 20:31:18 +01001086struct intel_rps_ei {
1087 u32 cz_clock;
1088 u32 render_c0;
1089 u32 media_c0;
Deepak S31685c22014-07-03 17:33:01 -04001090};
1091
Daniel Vetterc85aa882012-11-02 19:55:03 +01001092struct intel_gen6_power_mgmt {
Imre Deakd4d70aa2014-11-19 15:30:04 +02001093 /*
1094 * work, interrupts_enabled and pm_iir are protected by
1095 * dev_priv->irq_lock
1096 */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001097 struct work_struct work;
Imre Deakd4d70aa2014-11-19 15:30:04 +02001098 bool interrupts_enabled;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001099 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001100
Ben Widawskyb39fb292014-03-19 18:31:11 -07001101 /* Frequencies are stored in potentially platform dependent multiples.
1102 * In other words, *_freq needs to be multiplied by X to be interesting.
1103 * Soft limits are those which are used for the dynamic reclocking done
1104 * by the driver (raise frequencies under heavy loads, and lower for
1105 * lighter loads). Hard limits are those imposed by the hardware.
1106 *
1107 * A distinction is made for overclocking, which is never enabled by
1108 * default, and is considered to be above the hard limit if it's
1109 * possible at all.
1110 */
1111 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1112 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1113 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1114 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1115 u8 min_freq; /* AKA RPn. Minimum frequency */
Chris Wilsonaed242f2015-03-18 09:48:21 +00001116 u8 idle_freq; /* Frequency to request when we are idle */
Ben Widawskyb39fb292014-03-19 18:31:11 -07001117 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1118 u8 rp1_freq; /* "less than" RP0 power/freqency */
1119 u8 rp0_freq; /* Non-overclocked max frequency. */
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001120
Chris Wilson8fb55192015-04-07 16:20:28 +01001121 u8 up_threshold; /* Current %busy required to uplock */
1122 u8 down_threshold; /* Current %busy required to downclock */
1123
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001124 int last_adj;
1125 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1126
Chris Wilson8d3afd72015-05-21 21:01:47 +01001127 spinlock_t client_lock;
1128 struct list_head clients;
1129 bool client_boost;
1130
Chris Wilsonc0951f02013-10-10 21:58:50 +01001131 bool enabled;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001132 struct delayed_work delayed_resume_work;
Chris Wilson1854d5c2015-04-07 16:20:32 +01001133 unsigned boosts;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001134
Chris Wilson2e1b8732015-04-27 13:41:22 +01001135 struct intel_rps_client semaphores, mmioflips;
Chris Wilsona6f766f2015-04-27 13:41:20 +01001136
Chris Wilsonbf225f22014-07-10 20:31:18 +01001137 /* manual wa residency calculations */
1138 struct intel_rps_ei up_ei, down_ei;
1139
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001140 /*
1141 * Protects RPS/RC6 register access and PCU communication.
Chris Wilson8d3afd72015-05-21 21:01:47 +01001142 * Must be taken after struct_mutex if nested. Note that
1143 * this lock may be held for long periods of time when
1144 * talking to hw - so only take it when talking to hw!
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001145 */
1146 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001147};
1148
Daniel Vetter1a240d42012-11-29 22:18:51 +01001149/* defined intel_pm.c */
1150extern spinlock_t mchdev_lock;
1151
Daniel Vetterc85aa882012-11-02 19:55:03 +01001152struct intel_ilk_power_mgmt {
1153 u8 cur_delay;
1154 u8 min_delay;
1155 u8 max_delay;
1156 u8 fmax;
1157 u8 fstart;
1158
1159 u64 last_count1;
1160 unsigned long last_time1;
1161 unsigned long chipset_power;
1162 u64 last_count2;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001163 u64 last_time2;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001164 unsigned long gfx_power;
1165 u8 corr;
1166
1167 int c_m;
1168 int r_t;
1169};
1170
Imre Deakc6cb5822014-03-04 19:22:55 +02001171struct drm_i915_private;
1172struct i915_power_well;
1173
1174struct i915_power_well_ops {
1175 /*
1176 * Synchronize the well's hw state to match the current sw state, for
1177 * example enable/disable it based on the current refcount. Called
1178 * during driver init and resume time, possibly after first calling
1179 * the enable/disable handlers.
1180 */
1181 void (*sync_hw)(struct drm_i915_private *dev_priv,
1182 struct i915_power_well *power_well);
1183 /*
1184 * Enable the well and resources that depend on it (for example
1185 * interrupts located on the well). Called after the 0->1 refcount
1186 * transition.
1187 */
1188 void (*enable)(struct drm_i915_private *dev_priv,
1189 struct i915_power_well *power_well);
1190 /*
1191 * Disable the well and resources that depend on it. Called after
1192 * the 1->0 refcount transition.
1193 */
1194 void (*disable)(struct drm_i915_private *dev_priv,
1195 struct i915_power_well *power_well);
1196 /* Returns the hw enabled state. */
1197 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1198 struct i915_power_well *power_well);
1199};
1200
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001201/* Power well structure for haswell */
1202struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +02001203 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +02001204 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001205 /* power well enable/disable usage count */
1206 int count;
Imre Deakbfafe932014-06-05 20:31:47 +03001207 /* cached hw enabled state */
1208 bool hw_enabled;
Imre Deakc1ca7272013-11-25 17:15:29 +02001209 unsigned long domains;
Imre Deak77961eb2014-03-05 16:20:56 +02001210 unsigned long data;
Imre Deakc6cb5822014-03-04 19:22:55 +02001211 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001212};
1213
Imre Deak83c00f552013-10-25 17:36:47 +03001214struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +03001215 /*
1216 * Power wells needed for initialization at driver init and suspend
1217 * time are on. They are kept on until after the first modeset.
1218 */
1219 bool init_power_on;
Imre Deak0d116a22014-04-25 13:19:05 +03001220 bool initializing;
Imre Deakc1ca7272013-11-25 17:15:29 +02001221 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +03001222
Imre Deak83c00f552013-10-25 17:36:47 +03001223 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +02001224 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +02001225 struct i915_power_well *power_wells;
Imre Deak83c00f552013-10-25 17:36:47 +03001226};
1227
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001228#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001229struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001230 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001231 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001232 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001233};
1234
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001235struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001236 /** Memory allocator for GTT stolen memory */
1237 struct drm_mm stolen;
Paulo Zanoni92e97d22015-07-02 19:25:09 -03001238 /** Protects the usage of the GTT stolen memory allocator. This is
1239 * always the inner lock when overlapping with struct_mutex. */
1240 struct mutex stolen_lock;
1241
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001242 /** List of all objects in gtt_space. Used to restore gtt
1243 * mappings on resume */
1244 struct list_head bound_list;
1245 /**
1246 * List of objects which are not bound to the GTT (thus
1247 * are idle and not used by the GPU) but still have
1248 * (presumably uncached) pages still attached.
1249 */
1250 struct list_head unbound_list;
1251
1252 /** Usable portion of the GTT for GEM */
1253 unsigned long stolen_base; /* limited to low memory (32-bit) */
1254
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001255 /** PPGTT used for aliasing the PPGTT with the GTT */
1256 struct i915_hw_ppgtt *aliasing_ppgtt;
1257
Chris Wilson2cfcd322014-05-20 08:28:43 +01001258 struct notifier_block oom_notifier;
Chris Wilsonceabbba52014-03-25 13:23:04 +00001259 struct shrinker shrinker;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001260 bool shrinker_no_lock_stealing;
1261
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001262 /** LRU list of objects with fence regs on them. */
1263 struct list_head fence_list;
1264
1265 /**
1266 * We leave the user IRQ off as much as possible,
1267 * but this means that requests will finish and never
1268 * be retired once the system goes idle. Set a timer to
1269 * fire periodically while the ring is running. When it
1270 * fires, go retire requests.
1271 */
1272 struct delayed_work retire_work;
1273
1274 /**
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001275 * When we detect an idle GPU, we want to turn on
1276 * powersaving features. So once we see that there
1277 * are no more requests outstanding and no more
1278 * arrive within a small period of time, we fire
1279 * off the idle_work.
1280 */
1281 struct delayed_work idle_work;
1282
1283 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001284 * Are we in a non-interruptible section of code like
1285 * modesetting?
1286 */
1287 bool interruptible;
1288
Chris Wilsonf62a0072014-02-21 17:55:39 +00001289 /**
1290 * Is the GPU currently considered idle, or busy executing userspace
1291 * requests? Whilst idle, we attempt to power down the hardware and
1292 * display clocks. In order to reduce the effect on performance, there
1293 * is a slight delay before we do so.
1294 */
1295 bool busy;
1296
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001297 /* the indicator for dispatch video commands on two BSD rings */
1298 int bsd_ring_dispatch_index;
1299
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001300 /** Bit 6 swizzling required for X tiling */
1301 uint32_t bit_6_swizzle_x;
1302 /** Bit 6 swizzling required for Y tiling */
1303 uint32_t bit_6_swizzle_y;
1304
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001305 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001306 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001307 size_t object_memory;
1308 u32 object_count;
1309};
1310
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001311struct drm_i915_error_state_buf {
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01001312 struct drm_i915_private *i915;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001313 unsigned bytes;
1314 unsigned size;
1315 int err;
1316 u8 *buf;
1317 loff_t start;
1318 loff_t pos;
1319};
1320
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001321struct i915_error_state_file_priv {
1322 struct drm_device *dev;
1323 struct drm_i915_error_state *error;
1324};
1325
Daniel Vetter99584db2012-11-14 17:14:04 +01001326struct i915_gpu_error {
1327 /* For hangcheck timer */
1328#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1329#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001330 /* Hang gpu twice in this window and your context gets banned */
1331#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1332
Chris Wilson737b1502015-01-26 18:03:03 +02001333 struct workqueue_struct *hangcheck_wq;
1334 struct delayed_work hangcheck_work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001335
1336 /* For reset and error_state handling. */
1337 spinlock_t lock;
1338 /* Protected by the above dev->gpu_error.lock. */
1339 struct drm_i915_error_state *first_error;
Chris Wilson094f9a52013-09-25 17:34:55 +01001340
1341 unsigned long missed_irq_rings;
1342
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001343 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001344 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001345 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001346 * This is a counter which gets incremented when reset is triggered,
1347 * and again when reset has been handled. So odd values (lowest bit set)
1348 * means that reset is in progress and even values that
1349 * (reset_counter >> 1):th reset was successfully completed.
1350 *
1351 * If reset is not completed succesfully, the I915_WEDGE bit is
1352 * set meaning that hardware is terminally sour and there is no
1353 * recovery. All waiters on the reset_queue will be woken when
1354 * that happens.
1355 *
1356 * This counter is used by the wait_seqno code to notice that reset
1357 * event happened and it needs to restart the entire ioctl (since most
1358 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001359 *
1360 * This is important for lock-free wait paths, where no contended lock
1361 * naturally enforces the correct ordering between the bail-out of the
1362 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001363 */
1364 atomic_t reset_counter;
1365
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001366#define I915_RESET_IN_PROGRESS_FLAG 1
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001367#define I915_WEDGED (1 << 31)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001368
1369 /**
1370 * Waitqueue to signal when the reset has completed. Used by clients
1371 * that wait for dev_priv->mm.wedged to settle.
1372 */
1373 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001374
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02001375 /* Userspace knobs for gpu hang simulation;
1376 * combines both a ring mask, and extra flags
1377 */
1378 u32 stop_rings;
1379#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1380#define I915_STOP_RING_ALLOW_WARN (1 << 30)
Chris Wilson094f9a52013-09-25 17:34:55 +01001381
1382 /* For missed irq/seqno simulation. */
1383 unsigned int test_irq_rings;
McAulay, Alistair6689c162014-08-15 18:51:35 +01001384
1385 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1386 bool reload_in_reset;
Daniel Vetter99584db2012-11-14 17:14:04 +01001387};
1388
Zhang Ruib8efb172013-02-05 15:41:53 +08001389enum modeset_restore {
1390 MODESET_ON_LID_OPEN,
1391 MODESET_DONE,
1392 MODESET_SUSPENDED,
1393};
1394
Rodrigo Vivi500ea702015-08-07 17:01:16 -07001395#define DP_AUX_A 0x40
1396#define DP_AUX_B 0x10
1397#define DP_AUX_C 0x20
1398#define DP_AUX_D 0x30
1399
Xiong Zhang11c1b652015-08-17 16:04:04 +08001400#define DDC_PIN_B 0x05
1401#define DDC_PIN_C 0x04
1402#define DDC_PIN_D 0x06
1403
Paulo Zanoni6acab152013-09-12 17:06:24 -03001404struct ddi_vbt_port_info {
Damien Lespiauce4dd492014-08-01 11:07:54 +01001405 /*
1406 * This is an index in the HDMI/DVI DDI buffer translation table.
1407 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1408 * populate this field.
1409 */
1410#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
Paulo Zanoni6acab152013-09-12 17:06:24 -03001411 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001412
1413 uint8_t supports_dvi:1;
1414 uint8_t supports_hdmi:1;
1415 uint8_t supports_dp:1;
Rodrigo Vivi500ea702015-08-07 17:01:16 -07001416
1417 uint8_t alternate_aux_channel;
Xiong Zhang11c1b652015-08-17 16:04:04 +08001418 uint8_t alternate_ddc_pin;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001419
1420 uint8_t dp_boost_level;
1421 uint8_t hdmi_boost_level;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001422};
1423
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001424enum psr_lines_to_wait {
1425 PSR_0_LINES_TO_WAIT = 0,
1426 PSR_1_LINE_TO_WAIT,
1427 PSR_4_LINES_TO_WAIT,
1428 PSR_8_LINES_TO_WAIT
Pradeep Bhat83a72802014-03-28 10:14:57 +05301429};
1430
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001431struct intel_vbt_data {
1432 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1433 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1434
1435 /* Feature bits */
1436 unsigned int int_tv_support:1;
1437 unsigned int lvds_dither:1;
1438 unsigned int lvds_vbt:1;
1439 unsigned int int_crt_support:1;
1440 unsigned int lvds_use_ssc:1;
1441 unsigned int display_clock_mode:1;
1442 unsigned int fdi_rx_polarity_inverted:1;
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301443 unsigned int has_mipi:1;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001444 int lvds_ssc_freq;
1445 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1446
Pradeep Bhat83a72802014-03-28 10:14:57 +05301447 enum drrs_support_type drrs_type;
1448
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001449 /* eDP */
1450 int edp_rate;
1451 int edp_lanes;
1452 int edp_preemphasis;
1453 int edp_vswing;
1454 bool edp_initialized;
1455 bool edp_support;
1456 int edp_bpp;
1457 struct edp_power_seq edp_pps;
1458
Jani Nikulaf00076d2013-12-14 20:38:29 -02001459 struct {
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001460 bool full_link;
1461 bool require_aux_wakeup;
1462 int idle_frames;
1463 enum psr_lines_to_wait lines_to_wait;
1464 int tp1_wakeup_time;
1465 int tp2_tp3_wakeup_time;
1466 } psr;
1467
1468 struct {
Jani Nikulaf00076d2013-12-14 20:38:29 -02001469 u16 pwm_freq_hz;
Jani Nikula39fbc9c2014-04-09 11:22:06 +03001470 bool present;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001471 bool active_low_pwm;
Jani Nikula1de60682014-06-24 18:27:39 +03001472 u8 min_brightness; /* min_brightness/255 of max */
Jani Nikulaf00076d2013-12-14 20:38:29 -02001473 } backlight;
1474
Shobhit Kumard17c5442013-08-27 15:12:25 +03001475 /* MIPI DSI */
1476 struct {
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301477 u16 port;
Shobhit Kumard17c5442013-08-27 15:12:25 +03001478 u16 panel_id;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301479 struct mipi_config *config;
1480 struct mipi_pps_data *pps;
1481 u8 seq_version;
1482 u32 size;
1483 u8 *data;
1484 u8 *sequence[MIPI_SEQ_MAX];
Shobhit Kumard17c5442013-08-27 15:12:25 +03001485 } dsi;
1486
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001487 int crt_ddc_pin;
1488
1489 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001490 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001491
1492 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001493};
1494
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001495enum intel_ddb_partitioning {
1496 INTEL_DDB_PART_1_2,
1497 INTEL_DDB_PART_5_6, /* IVB+ */
1498};
1499
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001500struct intel_wm_level {
1501 bool enable;
1502 uint32_t pri_val;
1503 uint32_t spr_val;
1504 uint32_t cur_val;
1505 uint32_t fbc_val;
1506};
1507
Imre Deak820c1982013-12-17 14:46:36 +02001508struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001509 uint32_t wm_pipe[3];
1510 uint32_t wm_lp[3];
1511 uint32_t wm_lp_spr[3];
1512 uint32_t wm_linetime[3];
1513 bool enable_fbc_wm;
1514 enum intel_ddb_partitioning partitioning;
1515};
1516
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001517struct vlv_pipe_wm {
1518 uint16_t primary;
1519 uint16_t sprite[2];
1520 uint8_t cursor;
1521};
1522
1523struct vlv_sr_wm {
1524 uint16_t plane;
1525 uint8_t cursor;
1526};
1527
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001528struct vlv_wm_values {
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001529 struct vlv_pipe_wm pipe[3];
1530 struct vlv_sr_wm sr;
Ville Syrjäläae801522015-03-05 21:19:49 +02001531 struct {
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001532 uint8_t cursor;
1533 uint8_t sprite[2];
1534 uint8_t primary;
1535 } ddl[3];
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03001536 uint8_t level;
1537 bool cxsr;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001538};
1539
Damien Lespiauc1939242014-11-04 17:06:41 +00001540struct skl_ddb_entry {
Damien Lespiau16160e32014-11-04 17:06:53 +00001541 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
Damien Lespiauc1939242014-11-04 17:06:41 +00001542};
1543
1544static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1545{
Damien Lespiau16160e32014-11-04 17:06:53 +00001546 return entry->end - entry->start;
Damien Lespiauc1939242014-11-04 17:06:41 +00001547}
1548
Damien Lespiau08db6652014-11-04 17:06:52 +00001549static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1550 const struct skl_ddb_entry *e2)
1551{
1552 if (e1->start == e2->start && e1->end == e2->end)
1553 return true;
1554
1555 return false;
1556}
1557
Damien Lespiauc1939242014-11-04 17:06:41 +00001558struct skl_ddb_allocation {
Damien Lespiau34bb56a2014-11-04 17:07:01 +00001559 struct skl_ddb_entry pipe[I915_MAX_PIPES];
Chandra Konduru2cd601c2015-04-27 15:47:37 -07001560 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
Matt Roper4969d332015-09-24 15:53:10 -07001561 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001562};
1563
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001564struct skl_wm_values {
1565 bool dirty[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001566 struct skl_ddb_allocation ddb;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001567 uint32_t wm_linetime[I915_MAX_PIPES];
1568 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001569 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001570};
1571
1572struct skl_wm_level {
1573 bool plane_en[I915_MAX_PLANES];
1574 uint16_t plane_res_b[I915_MAX_PLANES];
1575 uint8_t plane_res_l[I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001576};
1577
Paulo Zanonic67a4702013-08-19 13:18:09 -03001578/*
Paulo Zanoni765dab62014-03-07 20:08:18 -03001579 * This struct helps tracking the state needed for runtime PM, which puts the
1580 * device in PCI D3 state. Notice that when this happens, nothing on the
1581 * graphics device works, even register access, so we don't get interrupts nor
1582 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001583 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001584 * Every piece of our code that needs to actually touch the hardware needs to
1585 * either call intel_runtime_pm_get or call intel_display_power_get with the
1586 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001587 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001588 * Our driver uses the autosuspend delay feature, which means we'll only really
1589 * suspend if we stay with zero refcount for a certain amount of time. The
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001590 * default value is currently very conservative (see intel_runtime_pm_enable), but
Paulo Zanoni765dab62014-03-07 20:08:18 -03001591 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001592 *
1593 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1594 * goes back to false exactly before we reenable the IRQs. We use this variable
1595 * to check if someone is trying to enable/disable IRQs while they're supposed
1596 * to be disabled. This shouldn't happen and we'll print some error messages in
Paulo Zanoni730488b2014-03-07 20:12:32 -03001597 * case it happens.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001598 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001599 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001600 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001601struct i915_runtime_pm {
1602 bool suspended;
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001603 bool irqs_enabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001604};
1605
Daniel Vetter926321d2013-10-16 13:30:34 +02001606enum intel_pipe_crc_source {
1607 INTEL_PIPE_CRC_SOURCE_NONE,
1608 INTEL_PIPE_CRC_SOURCE_PLANE1,
1609 INTEL_PIPE_CRC_SOURCE_PLANE2,
1610 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001611 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001612 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1613 INTEL_PIPE_CRC_SOURCE_TV,
1614 INTEL_PIPE_CRC_SOURCE_DP_B,
1615 INTEL_PIPE_CRC_SOURCE_DP_C,
1616 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001617 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001618 INTEL_PIPE_CRC_SOURCE_MAX,
1619};
1620
Shuang He8bf1e9f2013-10-15 18:55:27 +01001621struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001622 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001623 uint32_t crc[5];
1624};
1625
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001626#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001627struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001628 spinlock_t lock;
1629 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001630 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001631 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001632 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001633 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001634};
1635
Daniel Vetterf99d7062014-06-19 16:01:59 +02001636struct i915_frontbuffer_tracking {
1637 struct mutex lock;
1638
1639 /*
1640 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1641 * scheduled flips.
1642 */
1643 unsigned busy_bits;
1644 unsigned flip_bits;
1645};
1646
Mika Kuoppala72253422014-10-07 17:21:26 +03001647struct i915_wa_reg {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001648 i915_reg_t addr;
Mika Kuoppala72253422014-10-07 17:21:26 +03001649 u32 value;
1650 /* bitmask representing WA bits */
1651 u32 mask;
1652};
1653
1654#define I915_MAX_WA_REGS 16
1655
1656struct i915_workarounds {
1657 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1658 u32 count;
1659};
1660
Yu Zhangcf9d2892015-02-10 19:05:47 +08001661struct i915_virtual_gpu {
1662 bool active;
1663};
1664
John Harrison5f19e2b2015-05-29 17:43:27 +01001665struct i915_execbuffer_params {
1666 struct drm_device *dev;
1667 struct drm_file *file;
1668 uint32_t dispatch_flags;
1669 uint32_t args_batch_start_offset;
Michel Thierryaf987142015-07-29 17:23:59 +01001670 uint64_t batch_obj_vm_offset;
John Harrison5f19e2b2015-05-29 17:43:27 +01001671 struct intel_engine_cs *ring;
1672 struct drm_i915_gem_object *batch_obj;
1673 struct intel_context *ctx;
John Harrison6a6ae792015-05-29 17:43:30 +01001674 struct drm_i915_gem_request *request;
John Harrison5f19e2b2015-05-29 17:43:27 +01001675};
1676
Matt Roperaa363132015-09-24 15:53:18 -07001677/* used in computing the new watermarks state */
1678struct intel_wm_config {
1679 unsigned int num_pipes_active;
1680 bool sprites_enabled;
1681 bool sprites_scaled;
1682};
1683
Jani Nikula77fec552014-03-31 14:27:22 +03001684struct drm_i915_private {
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001685 struct drm_device *dev;
Chris Wilsonefab6d82015-04-07 16:20:57 +01001686 struct kmem_cache *objects;
Chris Wilsone20d2ab2015-04-07 16:20:58 +01001687 struct kmem_cache *vmas;
Chris Wilsonefab6d82015-04-07 16:20:57 +01001688 struct kmem_cache *requests;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001689
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001690 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001691
1692 int relative_constants_mode;
1693
1694 void __iomem *regs;
1695
Chris Wilson907b28c2013-07-19 20:36:52 +01001696 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001697
Yu Zhangcf9d2892015-02-10 19:05:47 +08001698 struct i915_virtual_gpu vgpu;
1699
Alex Dai33a732f2015-08-12 15:43:36 +01001700 struct intel_guc guc;
1701
Daniel Vettereb805622015-05-04 14:58:44 +02001702 struct intel_csr csr;
1703
Jani Nikula5ea6e5e2015-04-01 10:55:04 +03001704 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
Daniel Vetter28c70f12012-12-01 13:53:45 +01001705
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001706 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1707 * controller on different i2c buses. */
1708 struct mutex gmbus_mutex;
1709
1710 /**
1711 * Base address of the gmbus and gpio block.
1712 */
1713 uint32_t gpio_mmio_base;
1714
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301715 /* MMIO base address for MIPI regs */
1716 uint32_t mipi_mmio_base;
1717
Ville Syrjälä443a3892015-11-11 20:34:15 +02001718 uint32_t psr_mmio_base;
1719
Daniel Vetter28c70f12012-12-01 13:53:45 +01001720 wait_queue_head_t gmbus_wait_queue;
1721
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001722 struct pci_dev *bridge_dev;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001723 struct intel_engine_cs ring[I915_NUM_RINGS];
Ben Widawsky3e789982014-06-30 09:53:37 -07001724 struct drm_i915_gem_object *semaphore_obj;
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001725 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001726
Daniel Vetterba8286f2014-09-11 07:43:25 +02001727 struct drm_dma_handle *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001728 struct resource mch_res;
1729
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001730 /* protects the irq masks */
1731 spinlock_t irq_lock;
1732
Sourab Gupta84c33a62014-06-02 16:47:17 +05301733 /* protects the mmio flip data */
1734 spinlock_t mmio_flip_lock;
1735
Imre Deakf8b79e52014-03-04 19:23:07 +02001736 bool display_irqs_enabled;
1737
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001738 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1739 struct pm_qos_request pm_qos;
1740
Ville Syrjäläa5805162015-05-26 20:42:30 +03001741 /* Sideband mailbox protection */
1742 struct mutex sb_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001743
1744 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001745 union {
1746 u32 irq_mask;
1747 u32 de_irq_mask[I915_MAX_PIPES];
1748 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001749 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001750 u32 pm_irq_mask;
Deepak Sa6706b42014-03-15 20:23:22 +05301751 u32 pm_rps_events;
Imre Deak91d181d2014-02-10 18:42:49 +02001752 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001753
Jani Nikula5fcece82015-05-27 15:03:42 +03001754 struct i915_hotplug hotplug;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001755 struct i915_fbc fbc;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301756 struct i915_drrs drrs;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001757 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001758 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001759
Jesse Barnesd9ceb812014-10-09 12:57:43 -07001760 bool preserve_bios_swizzle;
1761
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001762 /* overlay */
1763 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001764
Jani Nikula58c68772013-11-08 16:48:54 +02001765 /* backlight registers and fields in struct intel_panel */
Daniel Vetter07f11d42014-09-15 14:35:09 +02001766 struct mutex backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001767
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001768 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001769 bool no_aux_handshake;
1770
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001771 /* protects panel power sequencer state */
1772 struct mutex pps_mutex;
1773
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001774 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1775 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1776 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1777
1778 unsigned int fsb_freq, mem_freq, is_ddr3;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01001779 unsigned int skl_boot_cdclk;
Ville Syrjälä44913152015-06-03 15:45:10 +03001780 unsigned int cdclk_freq, max_cdclk_freq;
Mika Kaholaadafdc62015-08-18 14:36:59 +03001781 unsigned int max_dotclk_freq;
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03001782 unsigned int hpll_freq;
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03001783 unsigned int czclk_freq;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001784
Daniel Vetter645416f2013-09-02 16:22:25 +02001785 /**
1786 * wq - Driver workqueue for GEM.
1787 *
1788 * NOTE: Work items scheduled here are not allowed to grab any modeset
1789 * locks, for otherwise the flushing done in the pageflip code will
1790 * result in deadlocks.
1791 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001792 struct workqueue_struct *wq;
1793
1794 /* Display functions */
1795 struct drm_i915_display_funcs display;
1796
1797 /* PCH chipset type */
1798 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001799 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001800
1801 unsigned long quirks;
1802
Zhang Ruib8efb172013-02-05 15:41:53 +08001803 enum modeset_restore modeset_restore;
1804 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001805
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001806 struct list_head vm_list; /* Global list of all address spaces */
Ben Widawsky0260c422014-03-22 22:47:21 -07001807 struct i915_gtt gtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001808
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001809 struct i915_gem_mm mm;
Chris Wilsonad46cb52014-08-07 14:20:40 +01001810 DECLARE_HASHTABLE(mm_structs, 7);
1811 struct mutex mm_lock;
Daniel Vetter87813422012-05-02 11:49:32 +02001812
Daniel Vetter87813422012-05-02 11:49:32 +02001813 /* Kernel Modesetting */
1814
yakui_zhao9b9d1722009-05-31 17:17:17 +08001815 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001816
Damien Lespiau76c4ac02014-02-07 19:12:52 +00001817 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1818 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001819 wait_queue_head_t pending_flip_queue;
1820
Daniel Vetterc4597872013-10-21 21:04:07 +02001821#ifdef CONFIG_DEBUG_FS
1822 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1823#endif
1824
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001825 int num_shared_dpll;
1826 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001827 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001828
Mika Kuoppala72253422014-10-07 17:21:26 +03001829 struct i915_workarounds workarounds;
Arun Siluvery888b5992014-08-26 14:44:51 +01001830
Jesse Barnes652c3932009-08-17 13:31:43 -07001831 /* Reclocking support */
1832 bool render_reclock_avail;
Daniel Vetterf99d7062014-06-19 16:01:59 +02001833
1834 struct i915_frontbuffer_tracking fb_tracking;
1835
Jesse Barnes652c3932009-08-17 13:31:43 -07001836 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001837
Zhenyu Wangc48044112009-12-17 14:48:43 +08001838 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001839
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001840 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001841
Ben Widawsky59124502013-07-04 11:02:05 -07001842 /* Cannot be determined by PCIID. You must always read a register. */
1843 size_t ellc_size;
1844
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001845 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001846 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001847
Daniel Vetter20e4d402012-08-08 23:35:39 +02001848 /* ilk-only ips/rps state. Everything in here is protected by the global
1849 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001850 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001851
Imre Deak83c00f552013-10-25 17:36:47 +03001852 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001853
Rodrigo Vivia031d702013-10-03 16:15:06 -03001854 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001855
Daniel Vetter99584db2012-11-14 17:14:04 +01001856 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001857
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001858 struct drm_i915_gem_object *vlv_pctx;
1859
Daniel Vetter06957262015-08-10 13:34:08 +02001860#ifdef CONFIG_DRM_FBDEV_EMULATION
Dave Airlie8be48d92010-03-30 05:34:14 +00001861 /* list of fbdev register on this device */
1862 struct intel_fbdev *fbdev;
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001863 struct work_struct fbdev_suspend_work;
Daniel Vetter4520f532013-10-09 09:18:51 +02001864#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001865
1866 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001867 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001868
Imre Deak58fddc22015-01-08 17:54:14 +02001869 /* hda/i915 audio component */
David Henningsson51e1d832015-08-19 10:48:56 +02001870 struct i915_audio_component *audio_component;
Imre Deak58fddc22015-01-08 17:54:14 +02001871 bool audio_component_registered;
Libin Yang4a21ef72015-09-02 14:11:39 +08001872 /**
1873 * av_mutex - mutex for audio/video sync
1874 *
1875 */
1876 struct mutex av_mutex;
Imre Deak58fddc22015-01-08 17:54:14 +02001877
Ben Widawsky254f9652012-06-04 14:42:42 -07001878 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001879 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001880
Damien Lespiau3e683202012-12-11 18:48:29 +00001881 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001882
Ville Syrjälä70722462015-04-10 18:21:28 +03001883 u32 chv_phy_control;
1884
Daniel Vetter842f1c82014-03-10 10:01:44 +01001885 u32 suspend_count;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001886 struct i915_suspend_saved_registers regfile;
Imre Deakddeea5b2014-05-05 15:19:56 +03001887 struct vlv_s0ix_state vlv_s0ix_state;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001888
Ville Syrjälä53615a52013-08-01 16:18:50 +03001889 struct {
1890 /*
1891 * Raw watermark latency values:
1892 * in 0.1us units for WM0,
1893 * in 0.5us units for WM1+.
1894 */
1895 /* primary */
1896 uint16_t pri_latency[5];
1897 /* sprite */
1898 uint16_t spr_latency[5];
1899 /* cursor */
1900 uint16_t cur_latency[5];
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001901 /*
1902 * Raw watermark memory latency values
1903 * for SKL for all 8 levels
1904 * in 1us units.
1905 */
1906 uint16_t skl_latency[8];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001907
Matt Roperaa363132015-09-24 15:53:18 -07001908 /* Committed wm config */
1909 struct intel_wm_config config;
1910
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001911 /*
1912 * The skl_wm_values structure is a bit too big for stack
1913 * allocation, so we keep the staging struct where we store
1914 * intermediate results here instead.
1915 */
1916 struct skl_wm_values skl_results;
1917
Ville Syrjälä609cede2013-10-09 19:18:03 +03001918 /* current hardware state */
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001919 union {
1920 struct ilk_wm_values hw;
1921 struct skl_wm_values skl_hw;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001922 struct vlv_wm_values vlv;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001923 };
Ville Syrjälä58590c12015-09-08 21:05:12 +03001924
1925 uint8_t max_level;
Ville Syrjälä53615a52013-08-01 16:18:50 +03001926 } wm;
1927
Paulo Zanoni8a187452013-12-06 20:32:13 -02001928 struct i915_runtime_pm pm;
1929
Oscar Mateoa83014d2014-07-24 17:04:21 +01001930 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1931 struct {
John Harrison5f19e2b2015-05-29 17:43:27 +01001932 int (*execbuf_submit)(struct i915_execbuffer_params *params,
John Harrisonf3dc74c2015-03-19 12:30:06 +00001933 struct drm_i915_gem_execbuffer2 *args,
John Harrison5f19e2b2015-05-29 17:43:27 +01001934 struct list_head *vmas);
Oscar Mateoa83014d2014-07-24 17:04:21 +01001935 int (*init_rings)(struct drm_device *dev);
1936 void (*cleanup_ring)(struct intel_engine_cs *ring);
1937 void (*stop_ring)(struct intel_engine_cs *ring);
1938 } gt;
1939
Sonika Jindal9e458032015-05-06 17:35:48 +05301940 bool edp_low_vswing;
1941
Ville Syrjälä3be60de2015-09-08 18:05:45 +03001942 /* perform PHY state sanity checks? */
1943 bool chv_phy_assert[2];
1944
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001945 /*
1946 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1947 * will be rejected. Instead look for a better place.
1948 */
Jani Nikula77fec552014-03-31 14:27:22 +03001949};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950
Chris Wilson2c1792a2013-08-01 18:39:55 +01001951static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1952{
1953 return dev->dev_private;
1954}
1955
Imre Deak888d0d42015-01-08 17:54:13 +02001956static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1957{
1958 return to_i915(dev_get_drvdata(dev));
1959}
1960
Alex Dai33a732f2015-08-12 15:43:36 +01001961static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1962{
1963 return container_of(guc, struct drm_i915_private, guc);
1964}
1965
Chris Wilsonb4519512012-05-11 14:29:30 +01001966/* Iterate over initialised rings */
1967#define for_each_ring(ring__, dev_priv__, i__) \
1968 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1969 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1970
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001971enum hdmi_force_audio {
1972 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1973 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1974 HDMI_AUDIO_AUTO, /* trust EDID */
1975 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1976};
1977
Daniel Vetter190d6cd2013-07-04 13:06:28 +02001978#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00001979
Chris Wilson37e680a2012-06-07 15:38:42 +01001980struct drm_i915_gem_object_ops {
1981 /* Interface between the GEM object and its backing storage.
1982 * get_pages() is called once prior to the use of the associated set
1983 * of pages before to binding them into the GTT, and put_pages() is
1984 * called after we no longer need them. As we expect there to be
1985 * associated cost with migrating pages between the backing storage
1986 * and making them available for the GPU (e.g. clflush), we may hold
1987 * onto the pages after they are no longer referenced by the GPU
1988 * in case they may be used again shortly (for example migrating the
1989 * pages to a different memory domain within the GTT). put_pages()
1990 * will therefore most likely be called when the object itself is
1991 * being released or under memory pressure (where we attempt to
1992 * reap pages for the shrinker).
1993 */
1994 int (*get_pages)(struct drm_i915_gem_object *);
1995 void (*put_pages)(struct drm_i915_gem_object *);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01001996 int (*dmabuf_export)(struct drm_i915_gem_object *);
1997 void (*release)(struct drm_i915_gem_object *);
Chris Wilson37e680a2012-06-07 15:38:42 +01001998};
1999
Daniel Vettera071fa02014-06-18 23:28:09 +02002000/*
2001 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302002 * considered to be the frontbuffer for the given plane interface-wise. This
Daniel Vettera071fa02014-06-18 23:28:09 +02002003 * doesn't mean that the hw necessarily already scans it out, but that any
2004 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2005 *
2006 * We have one bit per pipe and per scanout plane type.
2007 */
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302008#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2009#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
Daniel Vettera071fa02014-06-18 23:28:09 +02002010#define INTEL_FRONTBUFFER_BITS \
2011 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2012#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2013 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2014#define INTEL_FRONTBUFFER_CURSOR(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302015 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2016#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2017 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettera071fa02014-06-18 23:28:09 +02002018#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302019 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettercc365132014-06-18 13:59:13 +02002020#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302021 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
Daniel Vettera071fa02014-06-18 23:28:09 +02002022
Eric Anholt673a3942008-07-30 12:06:12 -07002023struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00002024 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07002025
Chris Wilson37e680a2012-06-07 15:38:42 +01002026 const struct drm_i915_gem_object_ops *ops;
2027
Ben Widawsky2f633152013-07-17 12:19:03 -07002028 /** List of VMAs backed by this object */
2029 struct list_head vma_list;
2030
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00002031 /** Stolen memory for this object, instead of being backed by shmem. */
2032 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07002033 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07002034
Chris Wilsonb4716182015-04-27 13:41:17 +01002035 struct list_head ring_list[I915_NUM_RINGS];
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02002036 /** Used in execbuf to temporarily hold a ref */
2037 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07002038
Chris Wilson8d9d5742015-04-07 16:20:38 +01002039 struct list_head batch_pool_link;
Brad Volkin493018d2014-12-11 12:13:08 -08002040
Eric Anholt673a3942008-07-30 12:06:12 -07002041 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01002042 * This is set if the object is on the active lists (has pending
2043 * rendering and so a non-zero seqno), and is not set if it i s on
2044 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07002045 */
Chris Wilsonb4716182015-04-27 13:41:17 +01002046 unsigned int active:I915_NUM_RINGS;
Eric Anholt673a3942008-07-30 12:06:12 -07002047
2048 /**
2049 * This is set if the object has been written to since last bound
2050 * to the GTT
2051 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002052 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02002053
2054 /**
2055 * Fence register bits (if any) for this object. Will be set
2056 * as needed when mapped into the GTT.
2057 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02002058 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02002059 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02002060
2061 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02002062 * Advice: are the backing pages purgeable?
2063 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002064 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02002065
2066 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02002067 * Current tiling mode for the object.
2068 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002069 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01002070 /**
2071 * Whether the tiling parameters for the currently associated fence
2072 * register have changed. Note that for the purposes of tracking
2073 * tiling changes we also treat the unfenced register, the register
2074 * slot that the object occupies whilst it executes a fenced
2075 * command (such as BLT on gen2/3), as a "fence".
2076 */
2077 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02002078
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002079 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01002080 * Is the object at the current location in the gtt mappable and
2081 * fenceable? Used to avoid costly recalculations.
2082 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002083 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01002084
2085 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002086 * Whether the current gtt mapping needs to be mappable (and isn't just
2087 * mappable by accident). Track pin and fault separate for a more
2088 * accurate mappable working set.
2089 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002090 unsigned int fault_mappable:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002091
Chris Wilsoncaea7472010-11-12 13:53:37 +00002092 /*
Akash Goel24f3a8c2014-06-17 10:59:42 +05302093 * Is the object to be mapped as read-only to the GPU
2094 * Only honoured if hardware has relevant pte bit
2095 */
2096 unsigned long gt_ro:1;
Chris Wilson651d7942013-08-08 14:41:10 +01002097 unsigned int cache_level:3;
Chris Wilson0f719792015-01-13 13:32:52 +00002098 unsigned int cache_dirty:1;
Chris Wilson93dfb402011-03-29 16:59:50 -07002099
Daniel Vettera071fa02014-06-18 23:28:09 +02002100 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2101
Tvrtko Ursulin8a0c39b2015-04-13 11:50:09 +01002102 unsigned int pin_display;
2103
Chris Wilson9da3da62012-06-01 15:20:22 +01002104 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01002105 int pages_pin_count;
Chris Wilsonee286372015-04-07 16:20:25 +01002106 struct get_page {
2107 struct scatterlist *sg;
2108 int last;
2109 } get_page;
Eric Anholt673a3942008-07-30 12:06:12 -07002110
Daniel Vetter1286ff72012-05-10 15:25:09 +02002111 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01002112 void *dma_buf_vmapping;
2113 int vmapping_count;
2114
Chris Wilsonb4716182015-04-27 13:41:17 +01002115 /** Breadcrumb of last rendering to the buffer.
2116 * There can only be one writer, but we allow for multiple readers.
2117 * If there is a writer that necessarily implies that all other
2118 * read requests are complete - but we may only be lazily clearing
2119 * the read requests. A read request is naturally the most recent
2120 * request on a ring, so we may have two different write and read
2121 * requests on one ring where the write request is older than the
2122 * read request. This allows for the CPU to read from an active
2123 * buffer by only waiting for the write to complete.
2124 * */
2125 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
John Harrison97b2a6a2014-11-24 18:49:26 +00002126 struct drm_i915_gem_request *last_write_req;
Chris Wilsoncaea7472010-11-12 13:53:37 +00002127 /** Breadcrumb of last fenced GPU access to the buffer. */
John Harrison97b2a6a2014-11-24 18:49:26 +00002128 struct drm_i915_gem_request *last_fenced_req;
Eric Anholt673a3942008-07-30 12:06:12 -07002129
Daniel Vetter778c3542010-05-13 11:49:44 +02002130 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08002131 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07002132
Daniel Vetter80075d42013-10-09 21:23:52 +02002133 /** References from framebuffers, locks out tiling changes. */
2134 unsigned long framebuffer_references;
2135
Eric Anholt280b7132009-03-12 16:56:27 -07002136 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01002137 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07002138
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002139 union {
Chris Wilson6a2c4232014-11-04 04:51:40 -08002140 /** for phy allocated objects */
2141 struct drm_dma_handle *phys_handle;
2142
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002143 struct i915_gem_userptr {
2144 uintptr_t ptr;
2145 unsigned read_only :1;
2146 unsigned workers :4;
2147#define I915_GEM_USERPTR_MAX_WORKERS 15
2148
Chris Wilsonad46cb52014-08-07 14:20:40 +01002149 struct i915_mm_struct *mm;
2150 struct i915_mmu_object *mmu_object;
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002151 struct work_struct *work;
2152 } userptr;
2153 };
2154};
Daniel Vetter62b8b212010-04-09 19:05:08 +00002155#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01002156
Daniel Vettera071fa02014-06-18 23:28:09 +02002157void i915_gem_track_fb(struct drm_i915_gem_object *old,
2158 struct drm_i915_gem_object *new,
2159 unsigned frontbuffer_bits);
2160
Eric Anholt673a3942008-07-30 12:06:12 -07002161/**
2162 * Request queue structure.
2163 *
2164 * The request queue allows us to note sequence numbers that have been emitted
2165 * and may be associated with active buffers to be retired.
2166 *
John Harrison97b2a6a2014-11-24 18:49:26 +00002167 * By keeping this list, we can avoid having to do questionable sequence
2168 * number comparisons on buffer last_read|write_seqno. It also allows an
2169 * emission time to be associated with the request for tracking how far ahead
2170 * of the GPU the submission is.
Nick Hoathb3a38992015-02-19 16:30:47 +00002171 *
2172 * The requests are reference counted, so upon creation they should have an
2173 * initial reference taken using kref_init
Eric Anholt673a3942008-07-30 12:06:12 -07002174 */
2175struct drm_i915_gem_request {
John Harrisonabfe2622014-11-24 18:49:24 +00002176 struct kref ref;
2177
Zou Nan hai852835f2010-05-21 09:08:56 +08002178 /** On Which ring this request was generated */
Chris Wilsonefab6d82015-04-07 16:20:57 +01002179 struct drm_i915_private *i915;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002180 struct intel_engine_cs *ring;
Zou Nan hai852835f2010-05-21 09:08:56 +08002181
Eric Anholt673a3942008-07-30 12:06:12 -07002182 /** GEM sequence number associated with this request. */
2183 uint32_t seqno;
2184
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002185 /** Position in the ringbuffer of the start of the request */
2186 u32 head;
2187
Nick Hoath72f95af2015-01-15 13:10:37 +00002188 /**
2189 * Position in the ringbuffer of the start of the postfix.
2190 * This is required to calculate the maximum available ringbuffer
2191 * space without overwriting the postfix.
2192 */
2193 u32 postfix;
2194
2195 /** Position in the ringbuffer of the end of the whole request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00002196 u32 tail;
2197
Nick Hoathb3a38992015-02-19 16:30:47 +00002198 /**
Dave Airliea8c6ecb2015-03-09 19:58:30 +10002199 * Context and ring buffer related to this request
Nick Hoathb3a38992015-02-19 16:30:47 +00002200 * Contexts are refcounted, so when this request is associated with a
2201 * context, we must increment the context's refcount, to guarantee that
2202 * it persists while any request is linked to it. Requests themselves
2203 * are also refcounted, so the request will only be freed when the last
2204 * reference to it is dismissed, and the code in
2205 * i915_gem_request_free() will then decrement the refcount on the
2206 * context.
2207 */
Oscar Mateo273497e2014-05-22 14:13:37 +01002208 struct intel_context *ctx;
John Harrison98e1bd42015-02-13 11:48:12 +00002209 struct intel_ringbuffer *ringbuf;
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002210
John Harrisondc4be60712015-05-29 17:43:39 +01002211 /** Batch buffer related to this request if any (used for
2212 error state dump only) */
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002213 struct drm_i915_gem_object *batch_obj;
2214
Eric Anholt673a3942008-07-30 12:06:12 -07002215 /** Time at which this request was emitted, in jiffies. */
2216 unsigned long emitted_jiffies;
2217
Eric Anholtb9624422009-06-03 07:27:35 +00002218 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07002219 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00002220
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002221 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00002222 /** file_priv list entry for this request */
2223 struct list_head client_list;
John Harrison67e29372014-12-05 13:49:35 +00002224
Mika Kuoppala071c92d2015-02-12 10:26:02 +02002225 /** process identifier submitting this request */
2226 struct pid *pid;
2227
Nick Hoath6d3d8272015-01-15 13:10:39 +00002228 /**
2229 * The ELSP only accepts two elements at a time, so we queue
2230 * context/tail pairs on a given queue (ring->execlist_queue) until the
2231 * hardware is available. The queue serves a double purpose: we also use
2232 * it to keep track of the up to 2 contexts currently in the hardware
2233 * (usually one in execution and the other queued up by the GPU): We
2234 * only remove elements from the head of the queue when the hardware
2235 * informs us that an element has been completed.
2236 *
2237 * All accesses to the queue are mediated by a spinlock
2238 * (ring->execlist_lock).
2239 */
2240
2241 /** Execlist link in the submission queue.*/
2242 struct list_head execlist_link;
2243
2244 /** Execlists no. of times this request has been sent to the ELSP */
2245 int elsp_submitted;
2246
Eric Anholt673a3942008-07-30 12:06:12 -07002247};
2248
John Harrison6689cb22015-03-19 12:30:08 +00002249int i915_gem_request_alloc(struct intel_engine_cs *ring,
John Harrison217e46b2015-05-29 17:43:29 +01002250 struct intel_context *ctx,
2251 struct drm_i915_gem_request **req_out);
John Harrison29b1b412015-06-18 13:10:09 +01002252void i915_gem_request_cancel(struct drm_i915_gem_request *req);
John Harrisonabfe2622014-11-24 18:49:24 +00002253void i915_gem_request_free(struct kref *req_ref);
John Harrisonfcfa423c2015-05-29 17:44:12 +01002254int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2255 struct drm_file *file);
John Harrisonabfe2622014-11-24 18:49:24 +00002256
John Harrisonb793a002014-11-24 18:49:25 +00002257static inline uint32_t
2258i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2259{
2260 return req ? req->seqno : 0;
2261}
2262
2263static inline struct intel_engine_cs *
2264i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2265{
2266 return req ? req->ring : NULL;
2267}
2268
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +01002269static inline struct drm_i915_gem_request *
John Harrisonabfe2622014-11-24 18:49:24 +00002270i915_gem_request_reference(struct drm_i915_gem_request *req)
2271{
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +01002272 if (req)
2273 kref_get(&req->ref);
2274 return req;
John Harrisonabfe2622014-11-24 18:49:24 +00002275}
2276
2277static inline void
2278i915_gem_request_unreference(struct drm_i915_gem_request *req)
2279{
Daniel Vetterf2458602014-11-26 10:26:05 +01002280 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
John Harrisonabfe2622014-11-24 18:49:24 +00002281 kref_put(&req->ref, i915_gem_request_free);
2282}
2283
Chris Wilson41037f92015-03-27 11:01:36 +00002284static inline void
2285i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2286{
Maarten Lankhorstb833bb62015-04-07 11:32:02 +02002287 struct drm_device *dev;
Chris Wilson41037f92015-03-27 11:01:36 +00002288
Maarten Lankhorstb833bb62015-04-07 11:32:02 +02002289 if (!req)
2290 return;
2291
2292 dev = req->ring->dev;
2293 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
Chris Wilson41037f92015-03-27 11:01:36 +00002294 mutex_unlock(&dev->struct_mutex);
Chris Wilson41037f92015-03-27 11:01:36 +00002295}
2296
John Harrisonabfe2622014-11-24 18:49:24 +00002297static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2298 struct drm_i915_gem_request *src)
2299{
2300 if (src)
2301 i915_gem_request_reference(src);
2302
2303 if (*pdst)
2304 i915_gem_request_unreference(*pdst);
2305
2306 *pdst = src;
2307}
2308
John Harrison1b5a4332014-11-24 18:49:42 +00002309/*
2310 * XXX: i915_gem_request_completed should be here but currently needs the
2311 * definition of i915_seqno_passed() which is below. It will be moved in
2312 * a later patch when the call to i915_seqno_passed() is obsoleted...
2313 */
2314
Brad Volkin351e3db2014-02-18 10:15:46 -08002315/*
2316 * A command that requires special handling by the command parser.
2317 */
2318struct drm_i915_cmd_descriptor {
2319 /*
2320 * Flags describing how the command parser processes the command.
2321 *
2322 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2323 * a length mask if not set
2324 * CMD_DESC_SKIP: The command is allowed but does not follow the
2325 * standard length encoding for the opcode range in
2326 * which it falls
2327 * CMD_DESC_REJECT: The command is never allowed
2328 * CMD_DESC_REGISTER: The command should be checked against the
2329 * register whitelist for the appropriate ring
2330 * CMD_DESC_MASTER: The command is allowed if the submitting process
2331 * is the DRM master
2332 */
2333 u32 flags;
2334#define CMD_DESC_FIXED (1<<0)
2335#define CMD_DESC_SKIP (1<<1)
2336#define CMD_DESC_REJECT (1<<2)
2337#define CMD_DESC_REGISTER (1<<3)
2338#define CMD_DESC_BITMASK (1<<4)
2339#define CMD_DESC_MASTER (1<<5)
2340
2341 /*
2342 * The command's unique identification bits and the bitmask to get them.
2343 * This isn't strictly the opcode field as defined in the spec and may
2344 * also include type, subtype, and/or subop fields.
2345 */
2346 struct {
2347 u32 value;
2348 u32 mask;
2349 } cmd;
2350
2351 /*
2352 * The command's length. The command is either fixed length (i.e. does
2353 * not include a length field) or has a length field mask. The flag
2354 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2355 * a length mask. All command entries in a command table must include
2356 * length information.
2357 */
2358 union {
2359 u32 fixed;
2360 u32 mask;
2361 } length;
2362
2363 /*
2364 * Describes where to find a register address in the command to check
2365 * against the ring's register whitelist. Only valid if flags has the
2366 * CMD_DESC_REGISTER bit set.
Francisco Jerez6a65c5b2015-05-29 16:44:13 +03002367 *
2368 * A non-zero step value implies that the command may access multiple
2369 * registers in sequence (e.g. LRI), in that case step gives the
2370 * distance in dwords between individual offset fields.
Brad Volkin351e3db2014-02-18 10:15:46 -08002371 */
2372 struct {
2373 u32 offset;
2374 u32 mask;
Francisco Jerez6a65c5b2015-05-29 16:44:13 +03002375 u32 step;
Brad Volkin351e3db2014-02-18 10:15:46 -08002376 } reg;
2377
2378#define MAX_CMD_DESC_BITMASKS 3
2379 /*
2380 * Describes command checks where a particular dword is masked and
2381 * compared against an expected value. If the command does not match
2382 * the expected value, the parser rejects it. Only valid if flags has
2383 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2384 * are valid.
Brad Volkind4d48032014-02-18 10:15:54 -08002385 *
2386 * If the check specifies a non-zero condition_mask then the parser
2387 * only performs the check when the bits specified by condition_mask
2388 * are non-zero.
Brad Volkin351e3db2014-02-18 10:15:46 -08002389 */
2390 struct {
2391 u32 offset;
2392 u32 mask;
2393 u32 expected;
Brad Volkind4d48032014-02-18 10:15:54 -08002394 u32 condition_offset;
2395 u32 condition_mask;
Brad Volkin351e3db2014-02-18 10:15:46 -08002396 } bits[MAX_CMD_DESC_BITMASKS];
2397};
2398
2399/*
2400 * A table of commands requiring special handling by the command parser.
2401 *
2402 * Each ring has an array of tables. Each table consists of an array of command
2403 * descriptors, which must be sorted with command opcodes in ascending order.
2404 */
2405struct drm_i915_cmd_table {
2406 const struct drm_i915_cmd_descriptor *table;
2407 int count;
2408};
2409
Chris Wilsondbbe9122014-08-09 19:18:43 +01002410/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
Chris Wilson7312e2d2014-08-13 12:14:12 +01002411#define __I915__(p) ({ \
2412 struct drm_i915_private *__p; \
2413 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2414 __p = (struct drm_i915_private *)p; \
2415 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2416 __p = to_i915((struct drm_device *)p); \
2417 else \
2418 BUILD_BUG(); \
2419 __p; \
2420})
Chris Wilsondbbe9122014-08-09 19:18:43 +01002421#define INTEL_INFO(p) (&__I915__(p)->info)
Chris Wilson87f1f462014-08-09 19:18:42 +01002422#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002423#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
Zou Nan haicae58522010-11-09 17:17:32 +08002424
Jani Nikulae87a0052015-10-20 15:22:02 +03002425#define REVID_FOREVER 0xff
2426/*
2427 * Return true if revision is in range [since,until] inclusive.
2428 *
2429 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2430 */
2431#define IS_REVID(p, since, until) \
2432 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2433
Chris Wilson87f1f462014-08-09 19:18:42 +01002434#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2435#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08002436#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002437#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08002438#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Chris Wilson87f1f462014-08-09 19:18:42 +01002439#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2440#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08002441#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2442#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2443#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Chris Wilson87f1f462014-08-09 19:18:42 +01002444#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08002445#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002446#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2447#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08002448#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2449#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Chris Wilson87f1f462014-08-09 19:18:42 +01002450#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07002451#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Chris Wilson87f1f462014-08-09 19:18:42 +01002452#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2453 INTEL_DEVID(dev) == 0x0152 || \
2454 INTEL_DEVID(dev) == 0x015a)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07002455#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Ville Syrjälä6df40272014-04-09 13:28:00 +03002456#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03002457#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Ville Syrjälä8179f1f2014-04-09 13:27:59 +03002458#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +05302459#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
Rodrigo Vivi7526ac12015-10-27 10:14:54 -07002460#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002461#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
Zou Nan haicae58522010-11-09 17:17:32 +08002462#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03002463#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002464 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002465#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
Rodrigo Vivi6b96d702015-01-19 16:16:15 -08002466 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
Rodrigo Vivi0dc6f202015-01-21 11:46:32 -08002467 (INTEL_DEVID(dev) & 0xf) == 0xb || \
Chris Wilson87f1f462014-08-09 19:18:42 +01002468 (INTEL_DEVID(dev) & 0xf) == 0xe))
Ville Syrjäläebb72aa2015-06-03 15:45:12 +03002469/* ULX machines are also considered ULT. */
2470#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2471 (INTEL_DEVID(dev) & 0xf) == 0xe)
Rodrigo Vivia0fcbd92014-09-19 20:16:26 -04002472#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2473 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002474#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002475 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
Rodrigo Vivi94353732013-08-28 16:45:46 -03002476#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002477 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Paulo Zanoni9bbfd202014-04-29 11:00:22 -03002478/* ULX machines are also considered ULT. */
Chris Wilson87f1f462014-08-09 19:18:42 +01002479#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2480 INTEL_DEVID(dev) == 0x0A1E)
David Weinehallf8896f52015-06-25 11:11:03 +03002481#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2482 INTEL_DEVID(dev) == 0x1913 || \
2483 INTEL_DEVID(dev) == 0x1916 || \
2484 INTEL_DEVID(dev) == 0x1921 || \
2485 INTEL_DEVID(dev) == 0x1926)
2486#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2487 INTEL_DEVID(dev) == 0x1915 || \
2488 INTEL_DEVID(dev) == 0x191E)
Sagar Arun Kamble7a58bad2015-09-12 10:17:50 +05302489#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2490 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2491#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2492 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2493
Ben Widawskyb833d682013-08-23 16:00:07 -07002494#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08002495
Jani Nikulaef712bb2015-10-20 15:22:00 +03002496#define SKL_REVID_A0 0x0
2497#define SKL_REVID_B0 0x1
2498#define SKL_REVID_C0 0x2
2499#define SKL_REVID_D0 0x3
2500#define SKL_REVID_E0 0x4
2501#define SKL_REVID_F0 0x5
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002502
Jani Nikulae87a0052015-10-20 15:22:02 +03002503#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2504
Jani Nikulaef712bb2015-10-20 15:22:00 +03002505#define BXT_REVID_A0 0x0
Jani Nikulafffda3f2015-10-20 15:22:01 +03002506#define BXT_REVID_A1 0x1
Jani Nikulaef712bb2015-10-20 15:22:00 +03002507#define BXT_REVID_B0 0x3
2508#define BXT_REVID_C0 0x9
Nick Hoath6c74c872015-03-20 09:03:52 +00002509
Jani Nikulae87a0052015-10-20 15:22:02 +03002510#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2511
Jesse Barnes85436692011-04-06 12:11:14 -07002512/*
2513 * The genX designation typically refers to the render engine, so render
2514 * capability related checks should use IS_GEN, while display and other checks
2515 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2516 * chips, etc.).
2517 */
Zou Nan haicae58522010-11-09 17:17:32 +08002518#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2519#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2520#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2521#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2522#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07002523#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Ben Widawskyd2980842013-11-02 21:06:59 -07002524#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
Damien Lespiaub71252d2013-02-13 15:27:24 +00002525#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
Zou Nan haicae58522010-11-09 17:17:32 +08002526
Ben Widawsky73ae4782013-10-15 10:02:57 -07002527#define RENDER_RING (1<<RCS)
2528#define BSD_RING (1<<VCS)
2529#define BLT_RING (1<<BCS)
2530#define VEBOX_RING (1<<VECS)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002531#define BSD2_RING (1<<VCS2)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002532#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002533#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002534#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2535#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2536#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2537#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002538 __I915__(dev)->ellc_size)
Zou Nan haicae58522010-11-09 17:17:32 +08002539#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2540
Ben Widawsky254f9652012-06-04 14:42:42 -07002541#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Oscar Mateod7f621e2014-07-24 17:04:49 +01002542#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
Jesse Barnes692ef702014-08-05 07:51:18 -07002543#define USES_PPGTT(dev) (i915.enable_ppgtt)
Michel Thierry81ba8aef2015-08-03 09:52:01 +01002544#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2545#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002546
Chris Wilson05394f32010-11-08 19:18:58 +00002547#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08002548#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2549
Daniel Vetterb45305f2012-12-17 16:21:27 +01002550/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2551#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002552/*
2553 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2554 * even when in MSI mode. This results in spurious interrupt warnings if the
2555 * legacy irq no. is shared with another device. The kernel then disables that
2556 * interrupt source and so prevents the other device from working properly.
2557 */
2558#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2559#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
Daniel Vetterb45305f2012-12-17 16:21:27 +01002560
Zou Nan haicae58522010-11-09 17:17:32 +08002561/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2562 * rows, which changed the alignment requirements and fence programming.
2563 */
2564#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2565 IS_I915GM(dev)))
Zou Nan haicae58522010-11-09 17:17:32 +08002566#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2567#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08002568
2569#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2570#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01002571#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08002572
Damien Lespiaudbf77862014-10-01 20:04:14 +01002573#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01002574
Jani Nikula0c9b3712015-05-18 17:10:01 +03002575#define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2576 INTEL_INFO(dev)->gen >= 9)
2577
Damien Lespiaudd93be52013-04-22 18:40:39 +01002578#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Damien Lespiau30568c42013-04-22 18:40:41 +01002579#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Rodrigo Vivib32c6f42014-11-20 03:44:37 -08002580#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
Sonika Jindale3d99842015-01-22 14:30:54 +05302581 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002582 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03002583#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
Suketu Shah00776512015-04-16 14:22:14 +05302584 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002585 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07002586#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2587#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002588
Animesh Manna7b403ff2015-08-04 22:02:42 +05302589#define HAS_CSR(dev) (IS_GEN9(dev))
Daniel Vettereb805622015-05-04 14:58:44 +02002590
Alex Dai33a732f2015-08-12 15:43:36 +01002591#define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
2592#define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
2593
Abdiel Janulguea9ed33c2015-07-01 10:12:23 +03002594#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2595 INTEL_INFO(dev)->gen >= 8)
2596
Akash Goel97d33082015-06-29 14:50:23 +05302597#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
Akash Goel430b7ad2015-06-29 14:50:24 +05302598 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
Akash Goel97d33082015-06-29 14:50:23 +05302599
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002600#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2601#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2602#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2603#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2604#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2605#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302606#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2607#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
Robert Beckett30c964a2015-08-28 13:10:22 +01002608#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002609
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002610#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302611#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03002612#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Ville Syrjäläc2699522015-08-27 23:55:59 +03002613#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
Zou Nan haicae58522010-11-09 17:17:32 +08002614#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2615#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07002616#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03002617#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08002618
Sonika Jindal5fafe292014-07-21 15:23:38 +05302619#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2620
Ben Widawsky040d2ba2013-09-19 11:01:40 -07002621/* DPF == dynamic parity feature */
2622#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2623#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07002624
Ben Widawskyc8735b02012-09-07 19:43:39 -07002625#define GT_FREQUENCY_MULTIPLIER 50
Akash Goelde43ae92015-03-06 11:07:14 +05302626#define GEN9_FREQ_SCALER 3
Ben Widawskyc8735b02012-09-07 19:43:39 -07002627
Chris Wilson05394f32010-11-08 19:18:58 +00002628#include "i915_trace.h"
2629
Rob Clarkbaa70942013-08-02 13:27:49 -04002630extern const struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10002631extern int i915_max_ioctl;
2632
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +02002633extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2634extern int i915_resume_switcheroo(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002635
Jani Nikulad330a952014-01-21 11:24:25 +02002636/* i915_params.c */
2637struct i915_params {
2638 int modeset;
2639 int panel_ignore_lid;
Jani Nikulad330a952014-01-21 11:24:25 +02002640 int semaphores;
Jani Nikulad330a952014-01-21 11:24:25 +02002641 int lvds_channel_mode;
2642 int panel_use_ssc;
2643 int vbt_sdvo_panel_type;
2644 int enable_rc6;
Patrik Jakobsson443646c2015-11-16 15:01:06 +01002645 int enable_dc;
Jani Nikulad330a952014-01-21 11:24:25 +02002646 int enable_fbc;
Jani Nikulad330a952014-01-21 11:24:25 +02002647 int enable_ppgtt;
Oscar Mateo127f1002014-07-24 17:04:11 +01002648 int enable_execlists;
Jani Nikulad330a952014-01-21 11:24:25 +02002649 int enable_psr;
2650 unsigned int preliminary_hw_support;
2651 int disable_power_well;
2652 int enable_ips;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002653 int invert_brightness;
Brad Volkin351e3db2014-02-18 10:15:46 -08002654 int enable_cmd_parser;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002655 /* leave bools at the end to not create holes */
2656 bool enable_hangcheck;
Jani Nikulad330a952014-01-21 11:24:25 +02002657 bool prefault_disable;
Daniel Vetter5bedeb22015-03-03 18:03:47 +01002658 bool load_detect_test;
Jani Nikulad330a952014-01-21 11:24:25 +02002659 bool reset;
Damien Lespiaua0bae572014-02-10 17:20:55 +00002660 bool disable_display;
Daniel Vetter7a10dfa2014-04-01 09:33:47 +02002661 bool disable_vtd_wa;
Alex Dai63dc0442015-07-09 19:29:03 +01002662 bool enable_guc_submission;
2663 int guc_log_level;
Sourab Gupta84c33a62014-06-02 16:47:17 +05302664 int use_mmio_flip;
Chris Wilson48572ed2014-12-18 10:55:50 +00002665 int mmio_debug;
Rob Clarke2c719b2014-12-15 13:56:32 -05002666 bool verbose_state_checks;
Maarten Lankhorstc5b852f2015-08-26 09:29:56 +02002667 bool nuclear_pageflip;
Sonika Jindal9e458032015-05-06 17:35:48 +05302668 int edp_vswing;
Jani Nikulad330a952014-01-21 11:24:25 +02002669};
2670extern struct i915_params i915 __read_mostly;
2671
Linus Torvalds1da177e2005-04-16 15:20:36 -07002672 /* i915_dma.c */
Dave Airlie22eae942005-11-10 22:16:34 +11002673extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002674extern int i915_driver_unload(struct drm_device *);
John Harrison2885f6a2014-06-26 18:23:52 +01002675extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002676extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10002677extern void i915_driver_preclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002678 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002679extern void i915_driver_postclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002680 struct drm_file *file);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002681#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11002682extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2683 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002684#endif
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07002685extern int intel_gpu_reset(struct drm_device *dev);
Chris Wilson49e4d842015-06-15 12:23:48 +01002686extern bool intel_has_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02002687extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002688extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2689extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2690extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2691extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
Imre Deak650ad972014-04-18 16:35:02 +03002692int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002693
Jani Nikula77913b32015-06-18 13:06:16 +03002694/* intel_hotplug.c */
2695void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2696void intel_hpd_init(struct drm_i915_private *dev_priv);
2697void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2698void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
Imre Deakcc24fcd2015-07-21 15:32:45 -07002699bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
Jani Nikula77913b32015-06-18 13:06:16 +03002700
Linus Torvalds1da177e2005-04-16 15:20:36 -07002701/* i915_irq.c */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03002702void i915_queue_hangcheck(struct drm_device *dev);
Mika Kuoppala58174462014-02-25 17:11:26 +02002703__printf(3, 4)
2704void i915_handle_error(struct drm_device *dev, bool wedged,
2705 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002706
Daniel Vetterb9632912014-09-30 10:56:44 +02002707extern void intel_irq_init(struct drm_i915_private *dev_priv);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02002708int intel_irq_install(struct drm_i915_private *dev_priv);
2709void intel_irq_uninstall(struct drm_i915_private *dev_priv);
Chris Wilson907b28c2013-07-19 20:36:52 +01002710
2711extern void intel_uncore_sanitize(struct drm_device *dev);
Imre Deak10018602014-06-06 12:59:39 +03002712extern void intel_uncore_early_sanitize(struct drm_device *dev,
2713 bool restore_forcewake);
Chris Wilson907b28c2013-07-19 20:36:52 +01002714extern void intel_uncore_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01002715extern void intel_uncore_check_errors(struct drm_device *dev);
Chris Wilsonaec347a2013-08-26 13:46:09 +01002716extern void intel_uncore_fini(struct drm_device *dev);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07002717extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
Mika Kuoppala48c10262015-01-16 11:34:41 +02002718const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002719void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002720 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002721void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002722 enum forcewake_domains domains);
Chris Wilsona6111f72015-04-07 16:21:02 +01002723/* Like above but the caller must manage the uncore.lock itself.
2724 * Must be used with I915_READ_FW and friends.
2725 */
2726void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2727 enum forcewake_domains domains);
2728void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2729 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002730void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
Yu Zhangcf9d2892015-02-10 19:05:47 +08002731static inline bool intel_vgpu_active(struct drm_device *dev)
2732{
2733 return to_i915(dev)->vgpu.active;
2734}
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002735
Keith Packard7c463582008-11-04 02:03:27 -08002736void
Jani Nikula50227e12014-03-31 14:27:21 +03002737i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002738 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002739
2740void
Jani Nikula50227e12014-03-31 14:27:21 +03002741i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002742 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002743
Imre Deakf8b79e52014-03-04 19:23:07 +02002744void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2745void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
Egbert Eich0706f172015-09-23 16:15:27 +02002746void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2747 uint32_t mask,
2748 uint32_t bits);
Daniel Vetter47339cd2014-09-30 10:56:46 +02002749void
2750ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2751void
2752ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2753void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2754 uint32_t interrupt_mask,
2755 uint32_t enabled_irq_mask);
2756#define ibx_enable_display_interrupt(dev_priv, bits) \
2757 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2758#define ibx_disable_display_interrupt(dev_priv, bits) \
2759 ibx_display_interrupt_update((dev_priv), (bits), 0)
Imre Deakf8b79e52014-03-04 19:23:07 +02002760
Eric Anholt673a3942008-07-30 12:06:12 -07002761/* i915_gem.c */
Eric Anholt673a3942008-07-30 12:06:12 -07002762int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2763 struct drm_file *file_priv);
2764int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2765 struct drm_file *file_priv);
2766int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2767 struct drm_file *file_priv);
2768int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2769 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002770int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2771 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002772int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2773 struct drm_file *file_priv);
2774int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2775 struct drm_file *file_priv);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +01002776void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
John Harrison8a8edb52015-05-29 17:43:33 +01002777 struct drm_i915_gem_request *req);
John Harrisonadeca762015-05-29 17:43:28 +01002778void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
John Harrison5f19e2b2015-05-29 17:43:27 +01002779int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
Oscar Mateoa83014d2014-07-24 17:04:21 +01002780 struct drm_i915_gem_execbuffer2 *args,
John Harrison5f19e2b2015-05-29 17:43:27 +01002781 struct list_head *vmas);
Eric Anholt673a3942008-07-30 12:06:12 -07002782int i915_gem_execbuffer(struct drm_device *dev, void *data,
2783 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05002784int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2785 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002786int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2787 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07002788int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2789 struct drm_file *file);
2790int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2791 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002792int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2793 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01002794int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2795 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002796int i915_gem_set_tiling(struct drm_device *dev, void *data,
2797 struct drm_file *file_priv);
2798int i915_gem_get_tiling(struct drm_device *dev, void *data,
2799 struct drm_file *file_priv);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002800int i915_gem_init_userptr(struct drm_device *dev);
2801int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2802 struct drm_file *file);
Eric Anholt5a125c32008-10-22 21:40:13 -07002803int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2804 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002805int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2806 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002807void i915_gem_load(struct drm_device *dev);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002808void *i915_gem_object_alloc(struct drm_device *dev);
2809void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01002810void i915_gem_object_init(struct drm_i915_gem_object *obj,
2811 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00002812struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2813 size_t size);
Dave Gordonea702992015-07-09 19:29:02 +01002814struct drm_i915_gem_object *i915_gem_object_create_from_data(
2815 struct drm_device *dev, const void *data, size_t size);
Eric Anholt673a3942008-07-30 12:06:12 -07002816void i915_gem_free_object(struct drm_gem_object *obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07002817void i915_gem_vma_destroy(struct i915_vma *vma);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002818
Daniel Vetter08755462015-04-20 09:04:05 -07002819/* Flags used by pin/bind&friends. */
2820#define PIN_MAPPABLE (1<<0)
2821#define PIN_NONBLOCK (1<<1)
2822#define PIN_GLOBAL (1<<2)
2823#define PIN_OFFSET_BIAS (1<<3)
2824#define PIN_USER (1<<4)
2825#define PIN_UPDATE (1<<5)
Michel Thierry101b5062015-10-01 13:33:57 +01002826#define PIN_ZONE_4G (1<<6)
2827#define PIN_HIGH (1<<7)
Chris Wilsond23db882014-05-23 08:48:08 +02002828#define PIN_OFFSET_MASK (~4095)
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002829int __must_check
2830i915_gem_object_pin(struct drm_i915_gem_object *obj,
2831 struct i915_address_space *vm,
2832 uint32_t alignment,
2833 uint64_t flags);
2834int __must_check
2835i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2836 const struct i915_ggtt_view *view,
2837 uint32_t alignment,
2838 uint64_t flags);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002839
2840int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2841 u32 flags);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07002842int __must_check i915_vma_unbind(struct i915_vma *vma);
Tvrtko Ursuline9f24d52015-10-05 13:26:36 +01002843/*
2844 * BEWARE: Do not use the function below unless you can _absolutely_
2845 * _guarantee_ VMA in question is _not in use_ anywhere.
2846 */
2847int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
Chris Wilsondd624af2013-01-15 12:39:35 +00002848int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Paulo Zanoni48018a52013-12-13 15:22:31 -02002849void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
Chris Wilson05394f32010-11-08 19:18:58 +00002850void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002851
Brad Volkin4c914c02014-02-18 10:15:45 -08002852int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2853 int *needs_clflush);
2854
Chris Wilson37e680a2012-06-07 15:38:42 +01002855int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilsonee286372015-04-07 16:20:25 +01002856
2857static inline int __sg_page_count(struct scatterlist *sg)
Chris Wilson9da3da62012-06-01 15:20:22 +01002858{
Chris Wilsonee286372015-04-07 16:20:25 +01002859 return sg->length >> PAGE_SHIFT;
Chris Wilson9da3da62012-06-01 15:20:22 +01002860}
Chris Wilsonee286372015-04-07 16:20:25 +01002861
2862static inline struct page *
2863i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2864{
2865 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2866 return NULL;
2867
2868 if (n < obj->get_page.last) {
2869 obj->get_page.sg = obj->pages->sgl;
2870 obj->get_page.last = 0;
2871 }
2872
2873 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2874 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2875 if (unlikely(sg_is_chain(obj->get_page.sg)))
2876 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2877 }
2878
2879 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2880}
2881
Chris Wilsona5570172012-09-04 21:02:54 +01002882static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2883{
2884 BUG_ON(obj->pages == NULL);
2885 obj->pages_pin_count++;
2886}
2887static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2888{
2889 BUG_ON(obj->pages_pin_count == 0);
2890 obj->pages_pin_count--;
2891}
2892
Chris Wilson54cf91d2010-11-25 18:00:26 +00002893int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07002894int i915_gem_object_sync(struct drm_i915_gem_object *obj,
John Harrison91af1272015-06-18 13:14:56 +01002895 struct intel_engine_cs *to,
2896 struct drm_i915_gem_request **to_req);
Ben Widawskye2d05a82013-09-24 09:57:58 -07002897void i915_vma_move_to_active(struct i915_vma *vma,
John Harrisonb2af0372015-05-29 17:43:50 +01002898 struct drm_i915_gem_request *req);
Dave Airlieff72145b2011-02-07 12:16:14 +10002899int i915_gem_dumb_create(struct drm_file *file_priv,
2900 struct drm_device *dev,
2901 struct drm_mode_create_dumb *args);
Dave Airlieda6b51d2014-12-24 13:11:17 +10002902int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2903 uint32_t handle, uint64_t *offset);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002904/**
2905 * Returns true if seq1 is later than seq2.
2906 */
2907static inline bool
2908i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2909{
2910 return (int32_t)(seq1 - seq2) >= 0;
2911}
2912
John Harrison1b5a4332014-11-24 18:49:42 +00002913static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2914 bool lazy_coherency)
2915{
2916 u32 seqno;
2917
2918 BUG_ON(req == NULL);
2919
2920 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2921
2922 return i915_seqno_passed(seqno, req->seqno);
2923}
2924
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002925int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2926int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002927
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002928struct drm_i915_gem_request *
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002929i915_gem_find_active_request(struct intel_engine_cs *ring);
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002930
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002931bool i915_gem_retire_requests(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002932void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
Daniel Vetter33196de2012-11-14 17:14:05 +01002933int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02002934 bool interruptible);
Sourab Gupta84c33a62014-06-02 16:47:17 +05302935
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002936static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2937{
2938 return unlikely(atomic_read(&error->reset_counter)
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002939 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002940}
2941
2942static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2943{
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002944 return atomic_read(&error->reset_counter) & I915_WEDGED;
2945}
2946
2947static inline u32 i915_reset_count(struct i915_gpu_error *error)
2948{
2949 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002950}
Chris Wilsona71d8d92012-02-15 11:25:36 +00002951
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02002952static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2953{
2954 return dev_priv->gpu_error.stop_rings == 0 ||
2955 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2956}
2957
2958static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2959{
2960 return dev_priv->gpu_error.stop_rings == 0 ||
2961 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2962}
2963
Chris Wilson069efc12010-09-30 16:53:18 +01002964void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01002965bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilson1070a422012-04-24 15:47:41 +01002966int __must_check i915_gem_init(struct drm_device *dev);
Oscar Mateoa83014d2014-07-24 17:04:21 +01002967int i915_gem_init_rings(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002968int __must_check i915_gem_init_hw(struct drm_device *dev);
John Harrison6909a662015-05-29 17:43:51 +01002969int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002970void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002971void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07002972int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01002973int __must_check i915_gem_suspend(struct drm_device *dev);
John Harrison75289872015-05-29 17:43:49 +01002974void __i915_add_request(struct drm_i915_gem_request *req,
John Harrison5b4a60c2015-05-29 17:43:34 +01002975 struct drm_i915_gem_object *batch_obj,
2976 bool flush_caches);
John Harrison75289872015-05-29 17:43:49 +01002977#define i915_add_request(req) \
John Harrisonfcfa423c2015-05-29 17:44:12 +01002978 __i915_add_request(req, NULL, true)
John Harrison75289872015-05-29 17:43:49 +01002979#define i915_add_request_no_flush(req) \
John Harrisonfcfa423c2015-05-29 17:44:12 +01002980 __i915_add_request(req, NULL, false)
John Harrison9c654812014-11-24 18:49:35 +00002981int __i915_wait_request(struct drm_i915_gem_request *req,
Ander Conselvan de Oliveira16e9a212014-11-06 09:26:38 +02002982 unsigned reset_counter,
2983 bool interruptible,
2984 s64 *timeout,
Chris Wilson2e1b8732015-04-27 13:41:22 +01002985 struct intel_rps_client *rps);
Daniel Vettera4b3a572014-11-26 14:17:05 +01002986int __must_check i915_wait_request(struct drm_i915_gem_request *req);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002987int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00002988int __must_check
Chris Wilson2e2f3512015-04-27 13:41:14 +01002989i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2990 bool readonly);
2991int __must_check
Chris Wilson20217462010-11-23 15:26:33 +00002992i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2993 bool write);
2994int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02002995i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2996int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002997i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2998 u32 alignment,
Tvrtko Ursuline6617332015-03-23 11:10:33 +00002999 const struct i915_ggtt_view *view);
3000void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3001 const struct i915_ggtt_view *view);
Chris Wilson00731152014-05-21 12:42:56 +01003002int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01003003 int align);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01003004int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00003005void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07003006
Chris Wilson467cffb2011-03-07 10:42:03 +00003007uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02003008i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3009uint32_t
Imre Deakd8651102013-01-07 21:47:33 +02003010i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3011 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00003012
Chris Wilsone4ffd172011-04-04 09:44:39 +01003013int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3014 enum i915_cache_level cache_level);
3015
Daniel Vetter1286ff72012-05-10 15:25:09 +02003016struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3017 struct dma_buf *dma_buf);
3018
3019struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3020 struct drm_gem_object *gem_obj, int flags);
3021
Michel Thierry088e0df2015-08-07 17:40:17 +01003022u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3023 const struct i915_ggtt_view *view);
3024u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3025 struct i915_address_space *vm);
3026static inline u64
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003027i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003028{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003029 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003030}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003031
Ben Widawskya70a3142013-07-31 16:59:56 -07003032bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003033bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003034 const struct i915_ggtt_view *view);
Ben Widawskya70a3142013-07-31 16:59:56 -07003035bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003036 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003037
Ben Widawskya70a3142013-07-31 16:59:56 -07003038unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3039 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003040struct i915_vma *
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003041i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3042 struct i915_address_space *vm);
3043struct i915_vma *
3044i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3045 const struct i915_ggtt_view *view);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003046
Ben Widawskyaccfef22013-08-14 11:38:35 +02003047struct i915_vma *
3048i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003049 struct i915_address_space *vm);
3050struct i915_vma *
3051i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3052 const struct i915_ggtt_view *view);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07003053
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003054static inline struct i915_vma *
3055i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3056{
3057 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08003058}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003059bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07003060
Ben Widawskya70a3142013-07-31 16:59:56 -07003061/* Some GGTT VM helpers */
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003062#define i915_obj_to_ggtt(obj) \
Ben Widawskya70a3142013-07-31 16:59:56 -07003063 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3064static inline bool i915_is_ggtt(struct i915_address_space *vm)
3065{
3066 struct i915_address_space *ggtt =
3067 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3068 return vm == ggtt;
3069}
3070
Daniel Vetter841cd772014-08-06 15:04:48 +02003071static inline struct i915_hw_ppgtt *
3072i915_vm_to_ppgtt(struct i915_address_space *vm)
3073{
3074 WARN_ON(i915_is_ggtt(vm));
3075
3076 return container_of(vm, struct i915_hw_ppgtt, base);
3077}
3078
3079
Ben Widawskya70a3142013-07-31 16:59:56 -07003080static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3081{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003082 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
Ben Widawskya70a3142013-07-31 16:59:56 -07003083}
3084
3085static inline unsigned long
3086i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3087{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003088 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07003089}
Ben Widawskyc37e2202013-07-31 16:59:58 -07003090
3091static inline int __must_check
3092i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3093 uint32_t alignment,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003094 unsigned flags)
Ben Widawskyc37e2202013-07-31 16:59:58 -07003095{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003096 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3097 alignment, flags | PIN_GLOBAL);
Ben Widawskyc37e2202013-07-31 16:59:58 -07003098}
Ben Widawskya70a3142013-07-31 16:59:56 -07003099
Daniel Vetterb2871102014-02-14 14:01:19 +01003100static inline int
3101i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3102{
3103 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3104}
3105
Tvrtko Ursuline6617332015-03-23 11:10:33 +00003106void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3107 const struct i915_ggtt_view *view);
3108static inline void
3109i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3110{
3111 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3112}
Daniel Vetterb2871102014-02-14 14:01:19 +01003113
Daniel Vetter41a36b72015-07-24 13:55:11 +02003114/* i915_gem_fence.c */
3115int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3116int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3117
3118bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3119void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3120
3121void i915_gem_restore_fences(struct drm_device *dev);
3122
Daniel Vetter7f96eca2015-07-24 17:40:14 +02003123void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3124void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3125void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3126
Ben Widawsky254f9652012-06-04 14:42:42 -07003127/* i915_gem_context.c */
Ben Widawsky8245be32013-11-06 13:56:29 -02003128int __must_check i915_gem_context_init(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07003129void i915_gem_context_fini(struct drm_device *dev);
Ben Widawskyacce9ff2013-12-06 14:11:03 -08003130void i915_gem_context_reset(struct drm_device *dev);
Ben Widawskye422b882013-12-06 14:10:58 -08003131int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
John Harrisonb3dd6b92015-05-29 17:43:40 +01003132int i915_gem_context_enable(struct drm_i915_gem_request *req);
Ben Widawsky254f9652012-06-04 14:42:42 -07003133void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
John Harrisonba01cc92015-05-29 17:43:41 +01003134int i915_switch_context(struct drm_i915_gem_request *req);
Oscar Mateo273497e2014-05-22 14:13:37 +01003135struct intel_context *
Ben Widawsky41bde552013-12-06 14:11:21 -08003136i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003137void i915_gem_context_free(struct kref *ctx_ref);
Oscar Mateo8c8579172014-07-24 17:04:14 +01003138struct drm_i915_gem_object *
3139i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
Oscar Mateo273497e2014-05-22 14:13:37 +01003140static inline void i915_gem_context_reference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03003141{
Chris Wilson691e6412014-04-09 09:07:36 +01003142 kref_get(&ctx->ref);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003143}
3144
Oscar Mateo273497e2014-05-22 14:13:37 +01003145static inline void i915_gem_context_unreference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03003146{
Chris Wilson691e6412014-04-09 09:07:36 +01003147 kref_put(&ctx->ref, i915_gem_context_free);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003148}
3149
Oscar Mateo273497e2014-05-22 14:13:37 +01003150static inline bool i915_gem_context_is_default(const struct intel_context *c)
Mika Kuoppala3fac8972014-01-30 16:05:48 +02003151{
Oscar Mateo821d66d2014-07-03 16:28:00 +01003152 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
Mika Kuoppala3fac8972014-01-30 16:05:48 +02003153}
3154
Ben Widawsky84624812012-06-04 14:42:54 -07003155int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3156 struct drm_file *file);
3157int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3158 struct drm_file *file);
Chris Wilsonc9dc0f32014-12-24 08:13:40 -08003159int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3160 struct drm_file *file_priv);
3161int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3162 struct drm_file *file_priv);
Daniel Vetter1286ff72012-05-10 15:25:09 +02003163
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003164/* i915_gem_evict.c */
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07003165int __must_check i915_gem_evict_something(struct drm_device *dev,
3166 struct i915_address_space *vm,
3167 int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01003168 unsigned alignment,
3169 unsigned cache_level,
Chris Wilsond23db882014-05-23 08:48:08 +02003170 unsigned long start,
3171 unsigned long end,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003172 unsigned flags);
Ben Widawsky68c8c172013-09-11 14:57:50 -07003173int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003174
Ben Widawsky0260c422014-03-22 22:47:21 -07003175/* belongs in i915_gem_gtt.h */
Eric Anholt673a3942008-07-30 12:06:12 -07003176static inline void i915_gem_chipset_flush(struct drm_device *dev)
3177{
Chris Wilson05394f32010-11-08 19:18:58 +00003178 if (INTEL_INFO(dev)->gen < 6)
3179 intel_gtt_chipset_flush();
Chris Wilson9797fbf2012-04-24 15:47:39 +01003180}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08003181
Chris Wilson9797fbf2012-04-24 15:47:39 +01003182/* i915_gem_stolen.c */
Paulo Zanonid713fd42015-07-02 19:25:07 -03003183int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3184 struct drm_mm_node *node, u64 size,
3185 unsigned alignment);
Paulo Zanonia9da5122015-09-14 15:19:57 -03003186int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3187 struct drm_mm_node *node, u64 size,
3188 unsigned alignment, u64 start,
3189 u64 end);
Paulo Zanonid713fd42015-07-02 19:25:07 -03003190void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3191 struct drm_mm_node *node);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003192int i915_gem_init_stolen(struct drm_device *dev);
3193void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00003194struct drm_i915_gem_object *
3195i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08003196struct drm_i915_gem_object *
3197i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3198 u32 stolen_offset,
3199 u32 gtt_offset,
3200 u32 size);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003201
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003202/* i915_gem_shrinker.c */
3203unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
Chris Wilson14387542015-10-01 12:18:25 +01003204 unsigned long target,
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003205 unsigned flags);
3206#define I915_SHRINK_PURGEABLE 0x1
3207#define I915_SHRINK_UNBOUND 0x2
3208#define I915_SHRINK_BOUND 0x4
Chris Wilson5763ff02015-10-01 12:18:29 +01003209#define I915_SHRINK_ACTIVE 0x8
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003210unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3211void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3212
3213
Eric Anholt673a3942008-07-30 12:06:12 -07003214/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01003215static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00003216{
Jani Nikula50227e12014-03-31 14:27:21 +03003217 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsone9b73c62012-12-03 21:03:14 +00003218
3219 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3220 obj->tiling_mode != I915_TILING_NONE;
3221}
3222
Eric Anholt673a3942008-07-30 12:06:12 -07003223/* i915_gem_debug.c */
Chris Wilson23bc5982010-09-29 16:10:57 +01003224#if WATCH_LISTS
3225int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07003226#else
Chris Wilson23bc5982010-09-29 16:10:57 +01003227#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07003228#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003229
Ben Gamari20172632009-02-17 20:08:50 -05003230/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04003231int i915_debugfs_init(struct drm_minor *minor);
3232void i915_debugfs_cleanup(struct drm_minor *minor);
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003233#ifdef CONFIG_DEBUG_FS
Jani Nikula249e87d2015-04-10 16:59:32 +03003234int i915_debugfs_connector_add(struct drm_connector *connector);
Damien Lespiau07144422013-10-15 18:55:40 +01003235void intel_display_crc_init(struct drm_device *dev);
3236#else
Daniel Vetter101057f2015-07-13 09:23:19 +02003237static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3238{ return 0; }
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003239static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01003240#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03003241
3242/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003243__printf(2, 3)
3244void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03003245int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3246 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003247int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003248 struct drm_i915_private *i915,
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003249 size_t count, loff_t pos);
3250static inline void i915_error_state_buf_release(
3251 struct drm_i915_error_state_buf *eb)
3252{
3253 kfree(eb->buf);
3254}
Mika Kuoppala58174462014-02-25 17:11:26 +02003255void i915_capture_error_state(struct drm_device *dev, bool wedge,
3256 const char *error_msg);
Mika Kuoppala84734a02013-07-12 16:50:57 +03003257void i915_error_state_get(struct drm_device *dev,
3258 struct i915_error_state_file_priv *error_priv);
3259void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3260void i915_destroy_error_state(struct drm_device *dev);
3261
3262void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003263const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
Ben Gamari20172632009-02-17 20:08:50 -05003264
Brad Volkin351e3db2014-02-18 10:15:46 -08003265/* i915_cmd_parser.c */
Brad Volkind728c8e2014-02-18 10:15:56 -08003266int i915_cmd_parser_get_version(void);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01003267int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3268void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3269bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3270int i915_parse_cmds(struct intel_engine_cs *ring,
Brad Volkin351e3db2014-02-18 10:15:46 -08003271 struct drm_i915_gem_object *batch_obj,
Brad Volkin78a42372014-12-11 12:13:09 -08003272 struct drm_i915_gem_object *shadow_batch_obj,
Brad Volkin351e3db2014-02-18 10:15:46 -08003273 u32 batch_start_offset,
Brad Volkinb9ffd802014-12-11 12:13:10 -08003274 u32 batch_len,
Brad Volkin351e3db2014-02-18 10:15:46 -08003275 bool is_master);
3276
Jesse Barnes317c35d2008-08-25 15:11:06 -07003277/* i915_suspend.c */
3278extern int i915_save_state(struct drm_device *dev);
3279extern int i915_restore_state(struct drm_device *dev);
3280
Ben Widawsky0136db582012-04-10 21:17:01 -07003281/* i915_sysfs.c */
3282void i915_setup_sysfs(struct drm_device *dev_priv);
3283void i915_teardown_sysfs(struct drm_device *dev_priv);
3284
Chris Wilsonf899fc62010-07-20 15:44:45 -07003285/* intel_i2c.c */
3286extern int intel_setup_gmbus(struct drm_device *dev);
3287extern void intel_teardown_gmbus(struct drm_device *dev);
Jani Nikula88ac7932015-03-27 00:20:22 +02003288extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3289 unsigned int pin);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003290
Jani Nikula0184df42015-03-27 00:20:20 +02003291extern struct i2c_adapter *
3292intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
Chris Wilsone957d772010-09-24 12:52:03 +01003293extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3294extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003295static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01003296{
3297 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3298}
Chris Wilsonf899fc62010-07-20 15:44:45 -07003299extern void intel_i2c_reset(struct drm_device *dev);
3300
Chris Wilson3b617962010-08-24 09:02:58 +01003301/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01003302#ifdef CONFIG_ACPI
Lv Zheng27d50c82013-12-06 16:52:05 +08003303extern int intel_opregion_setup(struct drm_device *dev);
Chris Wilson44834a62010-08-19 16:09:23 +01003304extern void intel_opregion_init(struct drm_device *dev);
3305extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01003306extern void intel_opregion_asle_intr(struct drm_device *dev);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003307extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3308 bool enable);
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003309extern int intel_opregion_notify_adapter(struct drm_device *dev,
3310 pci_power_t state);
Len Brown65e082c2008-10-24 17:18:10 -04003311#else
Lv Zheng27d50c82013-12-06 16:52:05 +08003312static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
Chris Wilson44834a62010-08-19 16:09:23 +01003313static inline void intel_opregion_init(struct drm_device *dev) { return; }
3314static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01003315static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003316static inline int
3317intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3318{
3319 return 0;
3320}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003321static inline int
3322intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3323{
3324 return 0;
3325}
Len Brown65e082c2008-10-24 17:18:10 -04003326#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01003327
Jesse Barnes723bfd72010-10-07 16:01:13 -07003328/* intel_acpi.c */
3329#ifdef CONFIG_ACPI
3330extern void intel_register_dsm_handler(void);
3331extern void intel_unregister_dsm_handler(void);
3332#else
3333static inline void intel_register_dsm_handler(void) { return; }
3334static inline void intel_unregister_dsm_handler(void) { return; }
3335#endif /* CONFIG_ACPI */
3336
Jesse Barnes79e53942008-11-07 14:24:08 -08003337/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02003338extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003339extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01003340extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003341extern void intel_modeset_cleanup(struct drm_device *dev);
Imre Deak4932e2c2014-02-11 17:12:48 +02003342extern void intel_connector_unregister(struct intel_connector *);
Dave Airlie28d52042009-09-21 14:33:58 +10003343extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +02003344extern void intel_display_resume(struct drm_device *dev);
Daniel Vetter44cec742013-01-25 17:53:21 +01003345extern void i915_redisable_vga(struct drm_device *dev);
Imre Deak04098752014-02-18 00:02:16 +02003346extern void i915_redisable_vga_power_on(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07003347extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02003348extern void intel_init_pch_refclk(struct drm_device *dev);
Ville Syrjäläffe02b42015-02-02 19:09:50 +02003349extern void intel_set_rps(struct drm_device *dev, u8 val);
Imre Deak5209b1f2014-07-01 12:36:17 +03003350extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3351 bool enable);
Akshay Joshi0206e352011-08-16 15:34:10 -04003352extern void intel_detect_pch(struct drm_device *dev);
Ben Widawsky0136db582012-04-10 21:17:01 -07003353extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08003354
Ben Widawsky2911a352012-04-05 14:47:36 -07003355extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07003356int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3357 struct drm_file *file);
Mika Kuoppalab6359912013-10-30 15:44:16 +02003358int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3359 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07003360
Chris Wilson6ef3d422010-08-04 20:26:07 +01003361/* overlay */
3362extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003363extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3364 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003365
3366extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003367extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003368 struct drm_device *dev,
3369 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01003370
Tom O'Rourke151a49d2014-11-13 18:50:10 -08003371int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3372int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003373
3374/* intel_sideband.c */
Deepak S707b6e32015-01-16 20:42:17 +05303375u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3376void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
Jani Nikula64936252013-05-22 15:36:20 +03003377u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003378u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3379void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3380u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3381void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3382u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3383void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08003384u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3385void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003386u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3387void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003388u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3389void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003390u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3391 enum intel_sbi_destination destination);
3392void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3393 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05303394u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3395void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003396
Ville Syrjälä616bc822015-01-23 21:04:25 +02003397int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3398int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
Deepak Sc8d9a592013-11-23 14:55:42 +05303399
Ben Widawsky0b274482013-10-04 21:22:51 -07003400#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3401#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00003402
Ben Widawsky0b274482013-10-04 21:22:51 -07003403#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3404#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3405#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3406#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003407
Ben Widawsky0b274482013-10-04 21:22:51 -07003408#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3409#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3410#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3411#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003412
Chris Wilson698b3132014-03-21 13:16:43 +00003413/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3414 * will be implemented using 2 32-bit writes in an arbitrary order with
3415 * an arbitrary delay between them. This can cause the hardware to
3416 * act upon the intermediate value, possibly leading to corruption and
3417 * machine death. You have been warned.
3418 */
Ben Widawsky0b274482013-10-04 21:22:51 -07003419#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3420#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08003421
Chris Wilson50877442014-03-21 12:41:53 +00003422#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003423 u32 upper, lower, old_upper, loop = 0; \
3424 upper = I915_READ(upper_reg); \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003425 do { \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003426 old_upper = upper; \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003427 lower = I915_READ(lower_reg); \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003428 upper = I915_READ(upper_reg); \
3429 } while (upper != old_upper && loop++ < 2); \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003430 (u64)upper << 32 | lower; })
Chris Wilson50877442014-03-21 12:41:53 +00003431
Zou Nan haicae58522010-11-09 17:17:32 +08003432#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3433#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3434
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003435#define __raw_read(x, s) \
3436static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003437 i915_reg_t reg) \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003438{ \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003439 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003440}
3441
3442#define __raw_write(x, s) \
3443static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003444 i915_reg_t reg, uint##x##_t val) \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003445{ \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003446 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003447}
3448__raw_read(8, b)
3449__raw_read(16, w)
3450__raw_read(32, l)
3451__raw_read(64, q)
3452
3453__raw_write(8, b)
3454__raw_write(16, w)
3455__raw_write(32, l)
3456__raw_write(64, q)
3457
3458#undef __raw_read
3459#undef __raw_write
3460
Chris Wilsona6111f72015-04-07 16:21:02 +01003461/* These are untraced mmio-accessors that are only valid to be used inside
3462 * criticial sections inside IRQ handlers where forcewake is explicitly
3463 * controlled.
3464 * Think twice, and think again, before using these.
3465 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3466 * intel_uncore_forcewake_irqunlock().
3467 */
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003468#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3469#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
Chris Wilsona6111f72015-04-07 16:21:02 +01003470#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3471
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003472/* "Broadcast RGB" property */
3473#define INTEL_BROADCAST_RGB_AUTO 0
3474#define INTEL_BROADCAST_RGB_FULL 1
3475#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08003476
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003477static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003478{
Sonika Jindal92e23b92014-07-21 15:23:40 +05303479 if (IS_VALLEYVIEW(dev))
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003480 return VLV_VGACNTRL;
Sonika Jindal92e23b92014-07-21 15:23:40 +05303481 else if (INTEL_INFO(dev)->gen >= 5)
3482 return CPU_VGACNTRL;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003483 else
3484 return VGACNTRL;
3485}
3486
Ville Syrjälä2bb46292013-02-22 16:12:51 +02003487static inline void __user *to_user_ptr(u64 address)
3488{
3489 return (void __user *)(uintptr_t)address;
3490}
3491
Imre Deakdf977292013-05-21 20:03:17 +03003492static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3493{
3494 unsigned long j = msecs_to_jiffies(m);
3495
3496 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3497}
3498
Daniel Vetter7bd0e222014-12-04 11:12:54 +01003499static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3500{
3501 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3502}
3503
Imre Deakdf977292013-05-21 20:03:17 +03003504static inline unsigned long
3505timespec_to_jiffies_timeout(const struct timespec *value)
3506{
3507 unsigned long j = timespec_to_jiffies(value);
3508
3509 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3510}
3511
Paulo Zanonidce56b32013-12-19 14:29:40 -02003512/*
3513 * If you need to wait X milliseconds between events A and B, but event B
3514 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3515 * when event A happened, then just before event B you call this function and
3516 * pass the timestamp as the first argument, and X as the second argument.
3517 */
3518static inline void
3519wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3520{
Imre Deakec5e0cf2014-01-29 13:25:40 +02003521 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02003522
3523 /*
3524 * Don't re-read the value of "jiffies" every time since it may change
3525 * behind our back and break the math.
3526 */
3527 tmp_jiffies = jiffies;
3528 target_jiffies = timestamp_jiffies +
3529 msecs_to_jiffies_timeout(to_wait_ms);
3530
3531 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02003532 remaining_jiffies = target_jiffies - tmp_jiffies;
3533 while (remaining_jiffies)
3534 remaining_jiffies =
3535 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02003536 }
3537}
3538
John Harrison581c26e82014-11-24 18:49:39 +00003539static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3540 struct drm_i915_gem_request *req)
3541{
3542 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3543 i915_gem_request_assign(&ring->trace_irq_req, req);
3544}
3545
Linus Torvalds1da177e2005-04-16 15:20:36 -07003546#endif